diff --git a/firmware/modularkbd/.cproject b/firmware/67percent/.cproject similarity index 100% rename from firmware/modularkbd/.cproject rename to firmware/67percent/.cproject diff --git a/firmware/modularkbd/.mxproject b/firmware/67percent/.mxproject similarity index 100% rename from firmware/modularkbd/.mxproject rename to firmware/67percent/.mxproject diff --git a/firmware/modularkbd/.project b/firmware/67percent/.project similarity index 100% rename from firmware/modularkbd/.project rename to firmware/67percent/.project diff --git a/firmware/modularkbd/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/firmware/67percent/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs similarity index 100% rename from firmware/modularkbd/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs rename to firmware/67percent/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs diff --git a/firmware/67percent/.settings/language.settings.xml b/firmware/67percent/.settings/language.settings.xml new file mode 100644 index 00000000..500b64f7 --- /dev/null +++ b/firmware/67percent/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/firmware/modularkbd/.settings/org.eclipse.core.resources.prefs b/firmware/67percent/.settings/org.eclipse.core.resources.prefs similarity index 100% rename from firmware/modularkbd/.settings/org.eclipse.core.resources.prefs rename to firmware/67percent/.settings/org.eclipse.core.resources.prefs diff --git a/firmware/modularkbd/.settings/stm32cubeide.project.prefs b/firmware/67percent/.settings/stm32cubeide.project.prefs similarity index 100% rename from firmware/modularkbd/.settings/stm32cubeide.project.prefs rename to firmware/67percent/.settings/stm32cubeide.project.prefs diff --git a/firmware/modularkbd/Core/Inc/Backup/dma.h.bak b/firmware/67percent/Core/Inc/Backup/dma.h.bak similarity index 100% rename from firmware/modularkbd/Core/Inc/Backup/dma.h.bak rename to firmware/67percent/Core/Inc/Backup/dma.h.bak diff --git a/firmware/modularkbd/Core/Inc/Backup/gpio.h.bak b/firmware/67percent/Core/Inc/Backup/gpio.h.bak similarity index 100% rename from firmware/modularkbd/Core/Inc/Backup/gpio.h.bak rename to firmware/67percent/Core/Inc/Backup/gpio.h.bak diff --git a/firmware/modularkbd/Core/Inc/Backup/i2c.h.bak b/firmware/67percent/Core/Inc/Backup/i2c.h.bak similarity index 100% rename from firmware/modularkbd/Core/Inc/Backup/i2c.h.bak rename to firmware/67percent/Core/Inc/Backup/i2c.h.bak diff --git a/firmware/modularkbd/Core/Inc/Backup/main.h.bak b/firmware/67percent/Core/Inc/Backup/main.h.bak similarity index 100% rename from firmware/modularkbd/Core/Inc/Backup/main.h.bak rename to firmware/67percent/Core/Inc/Backup/main.h.bak diff --git a/firmware/modularkbd/Core/Inc/Backup/stm32f4xx_hal_conf.h.bak b/firmware/67percent/Core/Inc/Backup/stm32f4xx_hal_conf.h.bak similarity index 100% rename from firmware/modularkbd/Core/Inc/Backup/stm32f4xx_hal_conf.h.bak rename to firmware/67percent/Core/Inc/Backup/stm32f4xx_hal_conf.h.bak diff --git a/firmware/modularkbd/Core/Inc/Backup/stm32f4xx_it.h.bak b/firmware/67percent/Core/Inc/Backup/stm32f4xx_it.h.bak similarity index 100% rename from firmware/modularkbd/Core/Inc/Backup/stm32f4xx_it.h.bak rename to firmware/67percent/Core/Inc/Backup/stm32f4xx_it.h.bak diff --git a/firmware/modularkbd/Core/Inc/Backup/tim.h.bak b/firmware/67percent/Core/Inc/Backup/tim.h.bak similarity index 100% rename from firmware/modularkbd/Core/Inc/Backup/tim.h.bak rename to firmware/67percent/Core/Inc/Backup/tim.h.bak diff --git a/firmware/modularkbd/Core/Inc/Backup/usart.h.bak b/firmware/67percent/Core/Inc/Backup/usart.h.bak similarity index 100% rename from firmware/modularkbd/Core/Inc/Backup/usart.h.bak rename to firmware/67percent/Core/Inc/Backup/usart.h.bak diff --git a/firmware/modularkbd/Core/Inc/dma.h b/firmware/67percent/Core/Inc/dma.h similarity index 100% rename from firmware/modularkbd/Core/Inc/dma.h rename to firmware/67percent/Core/Inc/dma.h diff --git a/firmware/modularkbd/Core/Inc/gpio.h b/firmware/67percent/Core/Inc/gpio.h similarity index 100% rename from firmware/modularkbd/Core/Inc/gpio.h rename to firmware/67percent/Core/Inc/gpio.h diff --git a/firmware/modularkbd/Core/Inc/hid_queue.h b/firmware/67percent/Core/Inc/hid_queue.h similarity index 100% rename from firmware/modularkbd/Core/Inc/hid_queue.h rename to firmware/67percent/Core/Inc/hid_queue.h diff --git a/firmware/modularkbd/Core/Inc/i2c.h b/firmware/67percent/Core/Inc/i2c.h similarity index 100% rename from firmware/modularkbd/Core/Inc/i2c.h rename to firmware/67percent/Core/Inc/i2c.h diff --git a/firmware/modularkbd/Core/Inc/main.h b/firmware/67percent/Core/Inc/main.h similarity index 100% rename from firmware/modularkbd/Core/Inc/main.h rename to firmware/67percent/Core/Inc/main.h diff --git a/firmware/67percent/Core/Inc/pwm.h b/firmware/67percent/Core/Inc/pwm.h new file mode 100644 index 00000000..cfa730df --- /dev/null +++ b/firmware/67percent/Core/Inc/pwm.h @@ -0,0 +1,24 @@ +#ifndef __PWM_H__ +#define __PWM_H__ + +#include "main.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Initialize PWM on TIM2 Channel 1 (PA5) +void MX_PWM_Init(void); +// Start/stop PWM output +void PWM_Start(void); +void PWM_Stop(void); +// Set duty as raw timer compare value (0..Period) +void PWM_SetDuty(uint32_t duty); +// Helper: set duty as percent (0..100) +void PWM_SetPercent(uint8_t percent); + +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/firmware/modularkbd/Core/Inc/stm32f4xx_hal_conf.h b/firmware/67percent/Core/Inc/stm32f4xx_hal_conf.h similarity index 100% rename from firmware/modularkbd/Core/Inc/stm32f4xx_hal_conf.h rename to firmware/67percent/Core/Inc/stm32f4xx_hal_conf.h diff --git a/firmware/modularkbd/Core/Inc/stm32f4xx_it.h b/firmware/67percent/Core/Inc/stm32f4xx_it.h similarity index 100% rename from firmware/modularkbd/Core/Inc/stm32f4xx_it.h rename to firmware/67percent/Core/Inc/stm32f4xx_it.h diff --git a/firmware/modularkbd/Core/Inc/tim.h b/firmware/67percent/Core/Inc/tim.h similarity index 100% rename from firmware/modularkbd/Core/Inc/tim.h rename to firmware/67percent/Core/Inc/tim.h diff --git a/firmware/modularkbd/Core/Inc/usart.h b/firmware/67percent/Core/Inc/usart.h similarity index 100% rename from firmware/modularkbd/Core/Inc/usart.h rename to firmware/67percent/Core/Inc/usart.h diff --git a/firmware/modularkbd/Core/Src/Backup/dma.c.bak b/firmware/67percent/Core/Src/Backup/dma.c.bak similarity index 100% rename from firmware/modularkbd/Core/Src/Backup/dma.c.bak rename to firmware/67percent/Core/Src/Backup/dma.c.bak diff --git a/firmware/modularkbd/Core/Src/Backup/gpio.c.bak b/firmware/67percent/Core/Src/Backup/gpio.c.bak similarity index 100% rename from firmware/modularkbd/Core/Src/Backup/gpio.c.bak rename to firmware/67percent/Core/Src/Backup/gpio.c.bak diff --git a/firmware/modularkbd/Core/Src/Backup/i2c.c.bak b/firmware/67percent/Core/Src/Backup/i2c.c.bak similarity index 100% rename from firmware/modularkbd/Core/Src/Backup/i2c.c.bak rename to firmware/67percent/Core/Src/Backup/i2c.c.bak diff --git a/firmware/modularkbd/Core/Src/Backup/main.c.bak b/firmware/67percent/Core/Src/Backup/main.c.bak similarity index 100% rename from firmware/modularkbd/Core/Src/Backup/main.c.bak rename to firmware/67percent/Core/Src/Backup/main.c.bak diff --git a/firmware/modularkbd/Core/Src/Backup/stm32f4xx_hal_msp.c.bak b/firmware/67percent/Core/Src/Backup/stm32f4xx_hal_msp.c.bak similarity index 100% rename from firmware/modularkbd/Core/Src/Backup/stm32f4xx_hal_msp.c.bak rename to firmware/67percent/Core/Src/Backup/stm32f4xx_hal_msp.c.bak diff --git a/firmware/modularkbd/Core/Src/Backup/stm32f4xx_it.c.bak b/firmware/67percent/Core/Src/Backup/stm32f4xx_it.c.bak similarity index 100% rename from firmware/modularkbd/Core/Src/Backup/stm32f4xx_it.c.bak rename to firmware/67percent/Core/Src/Backup/stm32f4xx_it.c.bak diff --git a/firmware/modularkbd/Core/Src/Backup/syscalls.c.bak b/firmware/67percent/Core/Src/Backup/syscalls.c.bak similarity index 100% rename from firmware/modularkbd/Core/Src/Backup/syscalls.c.bak rename to firmware/67percent/Core/Src/Backup/syscalls.c.bak diff --git a/firmware/modularkbd/Core/Src/Backup/sysmem.c.bak b/firmware/67percent/Core/Src/Backup/sysmem.c.bak similarity index 100% rename from firmware/modularkbd/Core/Src/Backup/sysmem.c.bak rename to firmware/67percent/Core/Src/Backup/sysmem.c.bak diff --git a/firmware/modularkbd/Core/Src/Backup/system_stm32f4xx.c.bak b/firmware/67percent/Core/Src/Backup/system_stm32f4xx.c.bak similarity index 100% rename from firmware/modularkbd/Core/Src/Backup/system_stm32f4xx.c.bak rename to firmware/67percent/Core/Src/Backup/system_stm32f4xx.c.bak diff --git a/firmware/modularkbd/Core/Src/Backup/tim.c.bak b/firmware/67percent/Core/Src/Backup/tim.c.bak similarity index 100% rename from firmware/modularkbd/Core/Src/Backup/tim.c.bak rename to firmware/67percent/Core/Src/Backup/tim.c.bak diff --git a/firmware/modularkbd/Core/Src/Backup/usart.c.bak b/firmware/67percent/Core/Src/Backup/usart.c.bak similarity index 100% rename from firmware/modularkbd/Core/Src/Backup/usart.c.bak rename to firmware/67percent/Core/Src/Backup/usart.c.bak diff --git a/firmware/modularkbd/Core/Src/dma.c b/firmware/67percent/Core/Src/dma.c similarity index 100% rename from firmware/modularkbd/Core/Src/dma.c rename to firmware/67percent/Core/Src/dma.c diff --git a/firmware/modularkbd/Core/Src/gpio.c b/firmware/67percent/Core/Src/gpio.c similarity index 100% rename from firmware/modularkbd/Core/Src/gpio.c rename to firmware/67percent/Core/Src/gpio.c diff --git a/firmware/modularkbd/Core/Src/hid_queue.c b/firmware/67percent/Core/Src/hid_queue.c similarity index 100% rename from firmware/modularkbd/Core/Src/hid_queue.c rename to firmware/67percent/Core/Src/hid_queue.c diff --git a/firmware/modularkbd/Core/Src/i2c.c b/firmware/67percent/Core/Src/i2c.c similarity index 100% rename from firmware/modularkbd/Core/Src/i2c.c rename to firmware/67percent/Core/Src/i2c.c diff --git a/firmware/67percent/Core/Src/main.c b/firmware/67percent/Core/Src/main.c new file mode 100644 index 00000000..fd75f93f --- /dev/null +++ b/firmware/67percent/Core/Src/main.c @@ -0,0 +1,610 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "dma.h" +#include "i2c.h" +#include "tim.h" +#include "usart.h" +#include "usb_device.h" +#include "gpio.h" +#include +#include "pwm.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "usbd_hid.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +typedef struct { + uint8_t MODIFIER; // Modifier keys (Ctrl, Shift, Alt, Win) + uint8_t RESERVED; // Always 0 + uint8_t KEYPRESS[12]; // Up to 12 keycodes +} __attribute__((packed)) HIDReport; + + +// Switch pin mapping structure +typedef struct { + GPIO_TypeDef* GPIOx; // Pointer to GPIO port (e.g., GPIOA, GPIOB) + uint16_t PIN; // Pin number on the GPIO port +} SwitchPins; + + +// UART message structure for sending/receiving key events +typedef struct { + uint16_t DEPTH; // Custom field: could represent queue depth, layer, or message size + uint16_t TYPE; // Message type identifier (defines what kind of message this is) + uint8_t KEYPRESS[12]; // Keypress data (similar to HIDReport, but for UART transmission) +} __attribute__((packed)) UARTMessage; + +#define PACKET_SIZE 12 +#define QUEUE_CAPACITY 32 + +typedef struct { + uint8_t data[QUEUE_CAPACITY][PACKET_SIZE]; + volatile uint8_t head; // accessed in main + volatile uint8_t tail; // accessed in ISR + volatile uint8_t count; // optional, only if needed +} PacketQueue; + +// Initialize +void pq_init(PacketQueue *q){ + q->head = 0; + q->tail = 0; + q->count = 0; +} + +// Called from ISR +bool pq_push(PacketQueue *q, const uint8_t packet[PACKET_SIZE]){ + uint8_t nextTail = (q->tail + 1) % QUEUE_CAPACITY; + if(nextTail == q->head) return false; // queue full + + memcpy(q->data[q->tail], packet, PACKET_SIZE); + q->tail = nextTail; + return true; +} + +// Called from main +bool pq_pop(PacketQueue *q, uint8_t out_packet[PACKET_SIZE]){ + if(q->head == q->tail) return false; // queue empty + + memcpy(out_packet, q->data[q->head], PACKET_SIZE); + q->head = (q->head + 1) % QUEUE_CAPACITY; + return true; +} + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +#define ROW 6 +#define COL 5 +#define MAXQUEUE 256 +#define MODE_INACTIVE 0 +#define MODE_MAINBOARD 1 +#define MODE_ACTIVE 2 +#define MODE_DEBUG 3 +#define UART_RX_BUFF_SIZE 64 +#define QUEUE_SIZ 8 +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +// Initialize HID report properly +HIDReport REPORT = {0, 0, {0}}; +UARTMessage RX5Msg; //Buffer for messages on uart5 +UARTMessage RX1Msg; //Buffer for messages on uart5 +UARTMessage RX2Msg; //Buffer for messages on uart5 +UARTMessage RX4Msg; //Buffer for messages on uart5 + + +SwitchPins ROW_PINS[ROW] = { + {GPIOB, GPIO_PIN_10}, + {GPIOB, GPIO_PIN_2}, + {GPIOB, GPIO_PIN_1}, + {GPIOB, GPIO_PIN_0}, + {GPIOC, GPIO_PIN_5}, + {GPIOC, GPIO_PIN_4}, +}; + +SwitchPins COLUMN_PINS[COL] = { + {GPIOA, GPIO_PIN_8}, + {GPIOC, GPIO_PIN_9}, + {GPIOC, GPIO_PIN_8}, + {GPIOC, GPIO_PIN_7}, + {GPIOC, GPIO_PIN_6} +}; + +// Initialize keycodes array +uint8_t KEYCODES[ROW][COL] = { + {0x00, KEY_F13, KEY_F14, KEY_F15, KEY_F16}, + {KEY_F17, NUM_LOCK, KEYPAD_SLASH, KEYPAD_ASTERISK, KEYPAD_MINUS}, + {KEY_F18, KEYPAD_7, KEYPAD_8, KEYPAD_9, KEYPAD_PLUS}, + {KEY_F19, KEYPAD_4, KEYPAD_5, KEYPAD_6, 0x00}, + {KEY_F20, KEYPAD_1, KEYPAD_2, KEYPAD_3, KEYPAD_ENTER}, + {KEY_F21, KEYPAD_0, 0x00, KEYPAD_DOT, 0x00} +}; + +uint16_t DEPTH = 0; +uint16_t PORT_DEPTH[] = {0xFF, 0xFF, 0xFF, 0xFF}; +UART_HandleTypeDef* PARENT; +UART_HandleTypeDef* PORTS[] = {&huart5, &huart1, &huart2, &huart4}; +uint8_t KEYSTATE_CHANGED_FLAG = 0; +uint8_t KEYSTATE[ROW][COL]; + //North East South West +UARTMessage reportBuff; + +extern USBD_HandleTypeDef hUsbDeviceFS; +volatile uint8_t MODE = MODE_INACTIVE; + +UARTMessage uartBuffer; +volatile int uartUpdateFlag = 0; +// Encoder state (TIM3 in encoder mode on PA6/PA7) +volatile int32_t LAST_ENCODER_COUNT = 0; + +uint8_t UART_KEYSTATE[4][12]; + + +PacketQueue huart1q; +PacketQueue huart2q; +PacketQueue huart4q; +PacketQueue huart5q; + + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +/* USER CODE BEGIN PFP */ +void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *huart); +void UART_DMA_SendReport(UART_HandleTypeDef *huart); +void addUSBReport(uint8_t usageID); +void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender); +void matrixScan(void); +void encoderProcess(void); +void resetReport(void); +void sendMessage(void); +void findBestParent(); +void mergeChild(); +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_DMA_Init();MX_PWM_Init(); + MX_TIM2_Init(); + MX_TIM3_Init(); + MX_UART4_Init(); + MX_UART5_Init(); + MX_USART1_UART_Init(); + MX_USART2_UART_Init(); + MX_I2C1_Init(); + MX_USB_DEVICE_Init(); + MX_PWM_Init(); + /* USER CODE BEGIN 2 */ + + //Enable UART RX DMA for all ports + HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); + HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); + HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); + HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); + + // Start TIM3 encoder (PA6/PA7) so we can read encoder delta + HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL); + LAST_ENCODER_COUNT = __HAL_TIM_GET_COUNTER(&htim3); + + //Prealloc Kestate matrix + memset(KEYSTATE, 0, sizeof(KEYSTATE)); + pq_init(&huart1q); + pq_init(&huart2q); + pq_init(&huart4q); + pq_init(&huart5q); + + PWM_Start(); + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + __HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, 67); + switch (MODE){ + case MODE_ACTIVE: + KEYSTATE_CHANGED_FLAG = 1; + resetReport(); + matrixScan(); + mergeChild(); + encoderProcess(); + if(KEYSTATE_CHANGED_FLAG == 1){ + UARTMessage UARTREPORT; + UARTREPORT.DEPTH = DEPTH; + UARTREPORT.TYPE = 0xEE; + memcpy(UARTREPORT.KEYPRESS, REPORT.KEYPRESS, sizeof(UARTREPORT.KEYPRESS)); + HAL_UART_Transmit_DMA(PARENT, (uint8_t*)&UARTREPORT, sizeof(UARTREPORT)); + } + break; + + case MODE_INACTIVE: + //If the module is connected through the USB then mode is mainboard + if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ + MODE = MODE_MAINBOARD; + DEPTH = 0; + }else{ + //TODO: Look for a parent module... + + + + UARTMessage REQ; + REQ.DEPTH = 0; + REQ.TYPE = 0xFF; //Message code for request is 0xFF + memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS)); + + //Send query' for parent module + HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ)); + HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ)); + HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); + HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); + HAL_Delay(500); + findBestParent(); //So true... + } + break; + + case MODE_MAINBOARD: + resetReport(); + matrixScan();//Something related to this making the key stick. Likely due to race conditions + mergeChild(); + encoderProcess(); + USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); + break; + + default: + break; + } + + HAL_Delay(20); + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +void mergeChild(){ + uint8_t packet[12]; + if (pq_pop(&huart1q, packet)) { + memcpy(UART_KEYSTATE[1], packet, 12); + KEYSTATE_CHANGED_FLAG = 1; + } + if (pq_pop(&huart2q, packet)) { + memcpy(UART_KEYSTATE[2], packet, 12); + KEYSTATE_CHANGED_FLAG = 1; + } + if (pq_pop(&huart4q, packet)) { + memcpy(UART_KEYSTATE[3], packet, 12); + KEYSTATE_CHANGED_FLAG = 1; + } + if (pq_pop(&huart5q, packet)) { + memcpy(UART_KEYSTATE[0], packet, 12); + KEYSTATE_CHANGED_FLAG = 1; + } + for(int i = 0; i < 4; i++){ + for(int j = 0; j < 12; j++){ + REPORT.KEYPRESS[j] |= UART_KEYSTATE[i][j]; + } + } +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator out put voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 96; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ +// UART Message Requests Goes Here +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { + if (huart->Instance == USART1) { + handleUARTMessages((uint8_t*)&RX1Msg, &huart1); + HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); + } + else if (huart->Instance == USART2) { + handleUARTMessages((uint8_t*)&RX2Msg, &huart2); + HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); + } + else if (huart->Instance == UART4) { + handleUARTMessages((uint8_t*)&RX4Msg, &huart4); + HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); + } + else if (huart->Instance == UART5) { + handleUARTMessages((uint8_t*)&RX5Msg, &huart5); + HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); + } +} + +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { + // Restart DMA on error + if (huart->Instance == USART1) { + HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); + } + else if (huart->Instance == USART2) { + HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); + } + else if (huart->Instance == UART4) { + HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); + } + else if (huart->Instance == UART5) { + HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); + } +} + + + +void findBestParent(){ + //Find least depth parent + uint16_t least_val = 0xFF; + UART_HandleTypeDef* least_port = NULL; + for(uint8_t i = 0; i < 4; i++){ + if(PORT_DEPTH[i] 0x73) return; //Usage ID is out of bounds + uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit + uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array + uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset + REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); +} + +void matrixScan(void){ + + for (uint8_t col = 0; col < COL; col++){ + HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); + HAL_Delay(1); + for(uint8_t row = 0; row < ROW; row++){ + uint8_t new_key = HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN); + if(new_key != KEYSTATE[row][col]){ + KEYSTATE_CHANGED_FLAG = 1; + KEYSTATE[row][col] = new_key; + } + if(new_key){ + addUSBReport(KEYCODES[row][col]); + } + } + HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); + } + +} + + +// Read TIM3 encoder counter, calculate delta and add corresponding keycodes +void encoderProcess(void){ + int32_t cnt = (int32_t)__HAL_TIM_GET_COUNTER(&htim3); + int32_t diff = cnt - LAST_ENCODER_COUNT; + // TIM3 configured as 16-bit counter (period 65535). Fix wrap-around. + if(diff > 32767) diff -= 65536; + if(diff < -32768) diff += 65536; + if(diff > 0){ + int steps = diff; + if(steps > 10) steps = 10; // cap bursts + for(int i = 0; i < steps; i++){ + // CW -> KEYCODES[0][0] + addUSBReport(KEYCODES[3][3]); + } + }else if(diff < 0){ + int steps = -diff; + if(steps > 10) steps = 10; + for(int i = 0; i < steps; i++){ + // CCW -> KEYCODES[0][1] + addUSBReport(KEYCODES[2][1]); + } + } + LAST_ENCODER_COUNT = cnt; +} + +void resetReport(void){ + memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); +} + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/firmware/67percent/Core/Src/pwm.c b/firmware/67percent/Core/Src/pwm.c new file mode 100644 index 00000000..2dfe6255 --- /dev/null +++ b/firmware/67percent/Core/Src/pwm.c @@ -0,0 +1,41 @@ +#include "pwm.h" +#include "tim.h" + +void MX_PWM_Init(void){ + TIM_OC_InitTypeDef sConfigOC = {0}; + + // Initialize TIM2 for PWM (safe to call even if TIM2 was previously initialized for OC) + if (HAL_TIM_PWM_Init(&htim2) != HAL_OK){ + Error_Handler(); + } + + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK){ + Error_Handler(); + } +} + +void PWM_Start(void){ + HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); +} + +void PWM_Stop(void){ + HAL_TIM_PWM_Stop(&htim2, TIM_CHANNEL_1); +} + +void PWM_SetDuty(uint32_t duty){ + // Clamp duty to timer period + uint32_t period = htim2.Init.Period; + if(duty > period) duty = period; + __HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, duty); +} + +void PWM_SetPercent(uint8_t percent){ + if(percent > 100) percent = 100; + uint32_t period = htim2.Init.Period; + uint32_t duty = (period * percent) / 100; + PWM_SetDuty(duty); +} diff --git a/firmware/modularkbd/Core/Src/stm32f4xx_hal_msp.c b/firmware/67percent/Core/Src/stm32f4xx_hal_msp.c similarity index 100% rename from firmware/modularkbd/Core/Src/stm32f4xx_hal_msp.c rename to firmware/67percent/Core/Src/stm32f4xx_hal_msp.c diff --git a/firmware/modularkbd/Core/Src/stm32f4xx_it.c b/firmware/67percent/Core/Src/stm32f4xx_it.c similarity index 100% rename from firmware/modularkbd/Core/Src/stm32f4xx_it.c rename to firmware/67percent/Core/Src/stm32f4xx_it.c diff --git a/firmware/modularkbd/Core/Src/syscalls.c b/firmware/67percent/Core/Src/syscalls.c similarity index 100% rename from firmware/modularkbd/Core/Src/syscalls.c rename to firmware/67percent/Core/Src/syscalls.c diff --git a/firmware/modularkbd/Core/Src/sysmem.c b/firmware/67percent/Core/Src/sysmem.c similarity index 100% rename from firmware/modularkbd/Core/Src/sysmem.c rename to firmware/67percent/Core/Src/sysmem.c diff --git a/firmware/modularkbd/Core/Src/system_stm32f4xx.c b/firmware/67percent/Core/Src/system_stm32f4xx.c similarity index 100% rename from firmware/modularkbd/Core/Src/system_stm32f4xx.c rename to firmware/67percent/Core/Src/system_stm32f4xx.c diff --git a/firmware/modularkbd/Core/Src/tim.c b/firmware/67percent/Core/Src/tim.c similarity index 100% rename from firmware/modularkbd/Core/Src/tim.c rename to firmware/67percent/Core/Src/tim.c diff --git a/firmware/modularkbd/Core/Src/usart.c b/firmware/67percent/Core/Src/usart.c similarity index 100% rename from firmware/modularkbd/Core/Src/usart.c rename to firmware/67percent/Core/Src/usart.c diff --git a/firmware/modularkbd/Core/Startup/startup_stm32f446retx.s b/firmware/67percent/Core/Startup/startup_stm32f446retx.s similarity index 100% rename from firmware/modularkbd/Core/Startup/startup_stm32f446retx.s rename to firmware/67percent/Core/Startup/startup_stm32f446retx.s diff --git a/firmware/modularkbd/Debug/Core/Src/dma.cyclo b/firmware/67percent/Debug/Core/Src/dma.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/dma.cyclo rename to firmware/67percent/Debug/Core/Src/dma.cyclo diff --git a/firmware/modularkbd/Debug/Core/Src/dma.d b/firmware/67percent/Debug/Core/Src/dma.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/dma.d rename to firmware/67percent/Debug/Core/Src/dma.d diff --git a/firmware/67percent/Debug/Core/Src/dma.o b/firmware/67percent/Debug/Core/Src/dma.o new file mode 100644 index 00000000..56de0de8 Binary files /dev/null and b/firmware/67percent/Debug/Core/Src/dma.o differ diff --git a/firmware/modularkbd/Debug/Core/Src/dma.su b/firmware/67percent/Debug/Core/Src/dma.su similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/dma.su rename to firmware/67percent/Debug/Core/Src/dma.su diff --git a/firmware/modularkbd/Debug/Core/Src/gpio.cyclo b/firmware/67percent/Debug/Core/Src/gpio.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/gpio.cyclo rename to firmware/67percent/Debug/Core/Src/gpio.cyclo diff --git a/firmware/modularkbd/Debug/Core/Src/gpio.d b/firmware/67percent/Debug/Core/Src/gpio.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/gpio.d rename to firmware/67percent/Debug/Core/Src/gpio.d diff --git a/firmware/67percent/Debug/Core/Src/gpio.o b/firmware/67percent/Debug/Core/Src/gpio.o new file mode 100644 index 00000000..b50eacfc Binary files /dev/null and b/firmware/67percent/Debug/Core/Src/gpio.o differ diff --git a/firmware/modularkbd/Debug/Core/Src/gpio.su b/firmware/67percent/Debug/Core/Src/gpio.su similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/gpio.su rename to firmware/67percent/Debug/Core/Src/gpio.su diff --git a/firmware/modularkbd/Debug/Core/Src/hid_queue.cyclo b/firmware/67percent/Debug/Core/Src/hid_queue.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/hid_queue.cyclo rename to firmware/67percent/Debug/Core/Src/hid_queue.cyclo diff --git a/firmware/modularkbd/Debug/Core/Src/hid_queue.d b/firmware/67percent/Debug/Core/Src/hid_queue.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/hid_queue.d rename to firmware/67percent/Debug/Core/Src/hid_queue.d diff --git a/firmware/67percent/Debug/Core/Src/hid_queue.o b/firmware/67percent/Debug/Core/Src/hid_queue.o new file mode 100644 index 00000000..dce98adc Binary files /dev/null and b/firmware/67percent/Debug/Core/Src/hid_queue.o differ diff --git a/firmware/modularkbd/Debug/Core/Src/hid_queue.su b/firmware/67percent/Debug/Core/Src/hid_queue.su similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/hid_queue.su rename to firmware/67percent/Debug/Core/Src/hid_queue.su diff --git a/firmware/modularkbd/Debug/Core/Src/i2c.cyclo b/firmware/67percent/Debug/Core/Src/i2c.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/i2c.cyclo rename to firmware/67percent/Debug/Core/Src/i2c.cyclo diff --git a/firmware/modularkbd/Debug/Core/Src/i2c.d b/firmware/67percent/Debug/Core/Src/i2c.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/i2c.d rename to firmware/67percent/Debug/Core/Src/i2c.d diff --git a/firmware/67percent/Debug/Core/Src/i2c.o b/firmware/67percent/Debug/Core/Src/i2c.o new file mode 100644 index 00000000..db118f05 Binary files /dev/null and b/firmware/67percent/Debug/Core/Src/i2c.o differ diff --git a/firmware/modularkbd/Debug/Core/Src/i2c.su b/firmware/67percent/Debug/Core/Src/i2c.su similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/i2c.su rename to firmware/67percent/Debug/Core/Src/i2c.su diff --git a/firmware/67percent/Debug/Core/Src/main.cyclo b/firmware/67percent/Debug/Core/Src/main.cyclo new file mode 100644 index 00000000..6281ec52 --- /dev/null +++ b/firmware/67percent/Debug/Core/Src/main.cyclo @@ -0,0 +1,15 @@ +../Core/Src/main.c:70:6:pq_init 1 +../Core/Src/main.c:77:6:pq_push 2 +../Core/Src/main.c:87:6:pq_pop 2 +../Core/Src/main.c:206:5:main 7 +../Core/Src/main.c:330:6:mergeChild 7 +../Core/Src/main.c:359:6:SystemClock_Config 3 +../Core/Src/main.c:403:6:HAL_UART_RxCpltCallback 5 +../Core/Src/main.c:422:6:HAL_UART_ErrorCallback 5 +../Core/Src/main.c:440:6:findBestParent 4 +../Core/Src/main.c:461:6:handleUARTMessages 14 +../Core/Src/main.c:520:6:addUSBReport 3 +../Core/Src/main.c:528:6:matrixScan 5 +../Core/Src/main.c:550:6:encoderProcess 9 +../Core/Src/main.c:574:6:resetReport 1 +../Core/Src/main.c:584:6:Error_Handler 1 diff --git a/firmware/67percent/Debug/Core/Src/main.d b/firmware/67percent/Debug/Core/Src/main.d new file mode 100644 index 00000000..454119d6 --- /dev/null +++ b/firmware/67percent/Debug/Core/Src/main.d @@ -0,0 +1,94 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/i2c.h ../Core/Inc/tim.h \ + ../Core/Inc/usart.h ../USB_DEVICE/App/usb_device.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/gpio.h ../Core/Inc/pwm.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Core/Inc/dma.h: +../Core/Inc/main.h: +../Core/Inc/i2c.h: +../Core/Inc/tim.h: +../Core/Inc/usart.h: +../USB_DEVICE/App/usb_device.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/gpio.h: +../Core/Inc/pwm.h: +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/firmware/67percent/Debug/Core/Src/main.o b/firmware/67percent/Debug/Core/Src/main.o new file mode 100644 index 00000000..5e91d85b Binary files /dev/null and b/firmware/67percent/Debug/Core/Src/main.o differ diff --git a/firmware/67percent/Debug/Core/Src/main.su b/firmware/67percent/Debug/Core/Src/main.su new file mode 100644 index 00000000..6c1dccd3 --- /dev/null +++ b/firmware/67percent/Debug/Core/Src/main.su @@ -0,0 +1,15 @@ +../Core/Src/main.c:70:6:pq_init 16 static +../Core/Src/main.c:77:6:pq_push 24 static +../Core/Src/main.c:87:6:pq_pop 16 static +../Core/Src/main.c:206:5:main 40 static +../Core/Src/main.c:330:6:mergeChild 40 static +../Core/Src/main.c:359:6:SystemClock_Config 88 static +../Core/Src/main.c:403:6:HAL_UART_RxCpltCallback 16 static +../Core/Src/main.c:422:6:HAL_UART_ErrorCallback 16 static +../Core/Src/main.c:440:6:findBestParent 24 static +../Core/Src/main.c:461:6:handleUARTMessages 56 static +../Core/Src/main.c:520:6:addUSBReport 24 static +../Core/Src/main.c:528:6:matrixScan 16 static +../Core/Src/main.c:550:6:encoderProcess 32 static +../Core/Src/main.c:574:6:resetReport 8 static +../Core/Src/main.c:584:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/firmware/67percent/Debug/Core/Src/pwm.cyclo b/firmware/67percent/Debug/Core/Src/pwm.cyclo new file mode 100644 index 00000000..ea82f127 --- /dev/null +++ b/firmware/67percent/Debug/Core/Src/pwm.cyclo @@ -0,0 +1,5 @@ +../Core/Src/pwm.c:4:6:MX_PWM_Init 3 +../Core/Src/pwm.c:21:6:PWM_Start 1 +../Core/Src/pwm.c:25:6:PWM_Stop 1 +../Core/Src/pwm.c:29:6:PWM_SetDuty 2 +../Core/Src/pwm.c:36:6:PWM_SetPercent 2 diff --git a/firmware/67percent/Debug/Core/Src/pwm.d b/firmware/67percent/Debug/Core/Src/pwm.d new file mode 100644 index 00000000..997f695f --- /dev/null +++ b/firmware/67percent/Debug/Core/Src/pwm.d @@ -0,0 +1,71 @@ +Core/Src/pwm.o: ../Core/Src/pwm.c ../Core/Inc/pwm.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Core/Inc/tim.h +../Core/Inc/pwm.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Core/Inc/tim.h: diff --git a/firmware/67percent/Debug/Core/Src/pwm.o b/firmware/67percent/Debug/Core/Src/pwm.o new file mode 100644 index 00000000..2311e384 Binary files /dev/null and b/firmware/67percent/Debug/Core/Src/pwm.o differ diff --git a/firmware/67percent/Debug/Core/Src/pwm.su b/firmware/67percent/Debug/Core/Src/pwm.su new file mode 100644 index 00000000..8f1e7001 --- /dev/null +++ b/firmware/67percent/Debug/Core/Src/pwm.su @@ -0,0 +1,5 @@ +../Core/Src/pwm.c:4:6:MX_PWM_Init 40 static +../Core/Src/pwm.c:21:6:PWM_Start 8 static +../Core/Src/pwm.c:25:6:PWM_Stop 8 static +../Core/Src/pwm.c:29:6:PWM_SetDuty 24 static +../Core/Src/pwm.c:36:6:PWM_SetPercent 24 static diff --git a/firmware/modularkbd/Debug/Core/Src/stm32f4xx_hal_msp.cyclo b/firmware/67percent/Debug/Core/Src/stm32f4xx_hal_msp.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/stm32f4xx_hal_msp.cyclo rename to firmware/67percent/Debug/Core/Src/stm32f4xx_hal_msp.cyclo diff --git a/firmware/modularkbd/Debug/Core/Src/stm32f4xx_hal_msp.d b/firmware/67percent/Debug/Core/Src/stm32f4xx_hal_msp.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/stm32f4xx_hal_msp.d rename to firmware/67percent/Debug/Core/Src/stm32f4xx_hal_msp.d diff --git a/firmware/67percent/Debug/Core/Src/stm32f4xx_hal_msp.o b/firmware/67percent/Debug/Core/Src/stm32f4xx_hal_msp.o new file mode 100644 index 00000000..edeced39 Binary files /dev/null and b/firmware/67percent/Debug/Core/Src/stm32f4xx_hal_msp.o differ diff --git a/firmware/modularkbd/Debug/Core/Src/stm32f4xx_hal_msp.su b/firmware/67percent/Debug/Core/Src/stm32f4xx_hal_msp.su similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/stm32f4xx_hal_msp.su rename to firmware/67percent/Debug/Core/Src/stm32f4xx_hal_msp.su diff --git a/firmware/modularkbd/Debug/Core/Src/stm32f4xx_it.cyclo b/firmware/67percent/Debug/Core/Src/stm32f4xx_it.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/stm32f4xx_it.cyclo rename to firmware/67percent/Debug/Core/Src/stm32f4xx_it.cyclo diff --git a/firmware/modularkbd/Debug/Core/Src/stm32f4xx_it.d b/firmware/67percent/Debug/Core/Src/stm32f4xx_it.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/stm32f4xx_it.d rename to firmware/67percent/Debug/Core/Src/stm32f4xx_it.d diff --git a/firmware/67percent/Debug/Core/Src/stm32f4xx_it.o b/firmware/67percent/Debug/Core/Src/stm32f4xx_it.o new file mode 100644 index 00000000..e19568c1 Binary files /dev/null and b/firmware/67percent/Debug/Core/Src/stm32f4xx_it.o differ diff --git a/firmware/modularkbd/Debug/Core/Src/stm32f4xx_it.su b/firmware/67percent/Debug/Core/Src/stm32f4xx_it.su similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/stm32f4xx_it.su rename to firmware/67percent/Debug/Core/Src/stm32f4xx_it.su diff --git a/firmware/67percent/Debug/Core/Src/subdir.mk b/firmware/67percent/Debug/Core/Src/subdir.mk new file mode 100644 index 00000000..e7a142ba --- /dev/null +++ b/firmware/67percent/Debug/Core/Src/subdir.mk @@ -0,0 +1,63 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/dma.c \ +../Core/Src/gpio.c \ +../Core/Src/hid_queue.c \ +../Core/Src/i2c.c \ +../Core/Src/main.c \ +../Core/Src/pwm.c \ +../Core/Src/stm32f4xx_hal_msp.c \ +../Core/Src/stm32f4xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f4xx.c \ +../Core/Src/tim.c \ +../Core/Src/usart.c + +OBJS += \ +./Core/Src/dma.o \ +./Core/Src/gpio.o \ +./Core/Src/hid_queue.o \ +./Core/Src/i2c.o \ +./Core/Src/main.o \ +./Core/Src/pwm.o \ +./Core/Src/stm32f4xx_hal_msp.o \ +./Core/Src/stm32f4xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f4xx.o \ +./Core/Src/tim.o \ +./Core/Src/usart.o + +C_DEPS += \ +./Core/Src/dma.d \ +./Core/Src/gpio.d \ +./Core/Src/hid_queue.d \ +./Core/Src/i2c.d \ +./Core/Src/main.d \ +./Core/Src/pwm.d \ +./Core/Src/stm32f4xx_hal_msp.d \ +./Core/Src/stm32f4xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f4xx.d \ +./Core/Src/tim.d \ +./Core/Src/usart.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Core-2f-Src + +clean-Core-2f-Src: + -$(RM) ./Core/Src/dma.cyclo ./Core/Src/dma.d ./Core/Src/dma.o ./Core/Src/dma.su ./Core/Src/gpio.cyclo ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/gpio.su ./Core/Src/hid_queue.cyclo ./Core/Src/hid_queue.d ./Core/Src/hid_queue.o ./Core/Src/hid_queue.su ./Core/Src/i2c.cyclo ./Core/Src/i2c.d ./Core/Src/i2c.o ./Core/Src/i2c.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/pwm.cyclo ./Core/Src/pwm.d ./Core/Src/pwm.o ./Core/Src/pwm.su ./Core/Src/stm32f4xx_hal_msp.cyclo ./Core/Src/stm32f4xx_hal_msp.d ./Core/Src/stm32f4xx_hal_msp.o ./Core/Src/stm32f4xx_hal_msp.su ./Core/Src/stm32f4xx_it.cyclo ./Core/Src/stm32f4xx_it.d ./Core/Src/stm32f4xx_it.o ./Core/Src/stm32f4xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f4xx.cyclo ./Core/Src/system_stm32f4xx.d ./Core/Src/system_stm32f4xx.o ./Core/Src/system_stm32f4xx.su ./Core/Src/tim.cyclo ./Core/Src/tim.d ./Core/Src/tim.o ./Core/Src/tim.su ./Core/Src/usart.cyclo ./Core/Src/usart.d ./Core/Src/usart.o ./Core/Src/usart.su + +.PHONY: clean-Core-2f-Src + diff --git a/firmware/modularkbd/Debug/Core/Src/syscalls.cyclo b/firmware/67percent/Debug/Core/Src/syscalls.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/syscalls.cyclo rename to firmware/67percent/Debug/Core/Src/syscalls.cyclo diff --git a/firmware/modularkbd/Debug/Core/Src/syscalls.d b/firmware/67percent/Debug/Core/Src/syscalls.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/syscalls.d rename to firmware/67percent/Debug/Core/Src/syscalls.d diff --git a/firmware/67percent/Debug/Core/Src/syscalls.o b/firmware/67percent/Debug/Core/Src/syscalls.o new file mode 100644 index 00000000..026d6a62 Binary files /dev/null and b/firmware/67percent/Debug/Core/Src/syscalls.o differ diff --git a/firmware/modularkbd/Debug/Core/Src/syscalls.su b/firmware/67percent/Debug/Core/Src/syscalls.su similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/syscalls.su rename to firmware/67percent/Debug/Core/Src/syscalls.su diff --git a/firmware/modularkbd/Debug/Core/Src/sysmem.cyclo b/firmware/67percent/Debug/Core/Src/sysmem.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/sysmem.cyclo rename to firmware/67percent/Debug/Core/Src/sysmem.cyclo diff --git a/firmware/modularkbd/Debug/Core/Src/sysmem.d b/firmware/67percent/Debug/Core/Src/sysmem.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/sysmem.d rename to firmware/67percent/Debug/Core/Src/sysmem.d diff --git a/firmware/67percent/Debug/Core/Src/sysmem.o b/firmware/67percent/Debug/Core/Src/sysmem.o new file mode 100644 index 00000000..92127518 Binary files /dev/null and b/firmware/67percent/Debug/Core/Src/sysmem.o differ diff --git a/firmware/modularkbd/Debug/Core/Src/sysmem.su b/firmware/67percent/Debug/Core/Src/sysmem.su similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/sysmem.su rename to firmware/67percent/Debug/Core/Src/sysmem.su diff --git a/firmware/modularkbd/Debug/Core/Src/system_stm32f4xx.cyclo b/firmware/67percent/Debug/Core/Src/system_stm32f4xx.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/system_stm32f4xx.cyclo rename to firmware/67percent/Debug/Core/Src/system_stm32f4xx.cyclo diff --git a/firmware/modularkbd/Debug/Core/Src/system_stm32f4xx.d b/firmware/67percent/Debug/Core/Src/system_stm32f4xx.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/system_stm32f4xx.d rename to firmware/67percent/Debug/Core/Src/system_stm32f4xx.d diff --git a/firmware/67percent/Debug/Core/Src/system_stm32f4xx.o b/firmware/67percent/Debug/Core/Src/system_stm32f4xx.o new file mode 100644 index 00000000..ab5551a5 Binary files /dev/null and b/firmware/67percent/Debug/Core/Src/system_stm32f4xx.o differ diff --git a/firmware/modularkbd/Debug/Core/Src/system_stm32f4xx.su b/firmware/67percent/Debug/Core/Src/system_stm32f4xx.su similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/system_stm32f4xx.su rename to firmware/67percent/Debug/Core/Src/system_stm32f4xx.su diff --git a/firmware/modularkbd/Debug/Core/Src/tim.cyclo b/firmware/67percent/Debug/Core/Src/tim.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/tim.cyclo rename to firmware/67percent/Debug/Core/Src/tim.cyclo diff --git a/firmware/modularkbd/Debug/Core/Src/tim.d b/firmware/67percent/Debug/Core/Src/tim.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/tim.d rename to firmware/67percent/Debug/Core/Src/tim.d diff --git a/firmware/67percent/Debug/Core/Src/tim.o b/firmware/67percent/Debug/Core/Src/tim.o new file mode 100644 index 00000000..df9bf7f9 Binary files /dev/null and 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a/firmware/modularkbd/Debug/Core/Src/usart.su b/firmware/67percent/Debug/Core/Src/usart.su similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/usart.su rename to firmware/67percent/Debug/Core/Src/usart.su diff --git a/firmware/modularkbd/Debug/Core/Startup/startup_stm32f446retx.d b/firmware/67percent/Debug/Core/Startup/startup_stm32f446retx.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Startup/startup_stm32f446retx.d rename to firmware/67percent/Debug/Core/Startup/startup_stm32f446retx.d diff --git a/firmware/modularkbd/Debug/Core/Startup/startup_stm32f446retx.o b/firmware/67percent/Debug/Core/Startup/startup_stm32f446retx.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Startup/startup_stm32f446retx.o rename to firmware/67percent/Debug/Core/Startup/startup_stm32f446retx.o diff --git a/firmware/modularkbd/Debug/Core/Startup/subdir.mk b/firmware/67percent/Debug/Core/Startup/subdir.mk similarity index 100% rename from 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similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su diff --git a/firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk b/firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk similarity index 100% rename from firmware/modularkbd/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk rename to firmware/67percent/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o diff --git a/firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su b/firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su similarity index 100% rename from firmware/modularkbd/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su rename to firmware/67percent/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su diff --git a/firmware/modularkbd/Debug/USB_DEVICE/App/subdir.mk b/firmware/67percent/Debug/USB_DEVICE/App/subdir.mk similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/App/subdir.mk rename to firmware/67percent/Debug/USB_DEVICE/App/subdir.mk diff --git a/firmware/modularkbd/Debug/USB_DEVICE/App/usb_device.cyclo b/firmware/67percent/Debug/USB_DEVICE/App/usb_device.cyclo similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/App/usb_device.cyclo rename to firmware/67percent/Debug/USB_DEVICE/App/usb_device.cyclo diff --git a/firmware/modularkbd/Debug/USB_DEVICE/App/usb_device.d b/firmware/67percent/Debug/USB_DEVICE/App/usb_device.d similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/App/usb_device.d rename to firmware/67percent/Debug/USB_DEVICE/App/usb_device.d diff --git a/firmware/modularkbd/Debug/USB_DEVICE/App/usb_device.o b/firmware/67percent/Debug/USB_DEVICE/App/usb_device.o similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/App/usb_device.o rename to firmware/67percent/Debug/USB_DEVICE/App/usb_device.o diff --git a/firmware/modularkbd/Debug/USB_DEVICE/App/usb_device.su b/firmware/67percent/Debug/USB_DEVICE/App/usb_device.su similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/App/usb_device.su rename to firmware/67percent/Debug/USB_DEVICE/App/usb_device.su diff --git a/firmware/modularkbd/Debug/USB_DEVICE/App/usbd_desc.cyclo b/firmware/67percent/Debug/USB_DEVICE/App/usbd_desc.cyclo similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/App/usbd_desc.cyclo rename to firmware/67percent/Debug/USB_DEVICE/App/usbd_desc.cyclo diff --git a/firmware/modularkbd/Debug/USB_DEVICE/App/usbd_desc.d b/firmware/67percent/Debug/USB_DEVICE/App/usbd_desc.d similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/App/usbd_desc.d rename to firmware/67percent/Debug/USB_DEVICE/App/usbd_desc.d diff --git a/firmware/modularkbd/Debug/USB_DEVICE/App/usbd_desc.o b/firmware/67percent/Debug/USB_DEVICE/App/usbd_desc.o similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/App/usbd_desc.o rename to firmware/67percent/Debug/USB_DEVICE/App/usbd_desc.o diff --git a/firmware/modularkbd/Debug/USB_DEVICE/App/usbd_desc.su b/firmware/67percent/Debug/USB_DEVICE/App/usbd_desc.su similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/App/usbd_desc.su rename to firmware/67percent/Debug/USB_DEVICE/App/usbd_desc.su diff --git a/firmware/modularkbd/Debug/USB_DEVICE/Target/subdir.mk b/firmware/67percent/Debug/USB_DEVICE/Target/subdir.mk similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/Target/subdir.mk rename to firmware/67percent/Debug/USB_DEVICE/Target/subdir.mk diff --git a/firmware/modularkbd/Debug/USB_DEVICE/Target/usbd_conf.cyclo b/firmware/67percent/Debug/USB_DEVICE/Target/usbd_conf.cyclo similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/Target/usbd_conf.cyclo rename to firmware/67percent/Debug/USB_DEVICE/Target/usbd_conf.cyclo diff --git a/firmware/modularkbd/Debug/USB_DEVICE/Target/usbd_conf.d b/firmware/67percent/Debug/USB_DEVICE/Target/usbd_conf.d similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/Target/usbd_conf.d rename to firmware/67percent/Debug/USB_DEVICE/Target/usbd_conf.d diff --git a/firmware/modularkbd/Debug/USB_DEVICE/Target/usbd_conf.o b/firmware/67percent/Debug/USB_DEVICE/Target/usbd_conf.o similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/Target/usbd_conf.o rename to firmware/67percent/Debug/USB_DEVICE/Target/usbd_conf.o diff --git a/firmware/modularkbd/Debug/USB_DEVICE/Target/usbd_conf.su b/firmware/67percent/Debug/USB_DEVICE/Target/usbd_conf.su similarity index 100% rename from firmware/modularkbd/Debug/USB_DEVICE/Target/usbd_conf.su rename to firmware/67percent/Debug/USB_DEVICE/Target/usbd_conf.su diff --git a/firmware/67percent/Debug/makefile b/firmware/67percent/Debug/makefile new file mode 100644 index 00000000..4176ad2b --- /dev/null +++ b/firmware/67percent/Debug/makefile @@ -0,0 +1,98 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include USB_DEVICE/Target/subdir.mk +-include USB_DEVICE/App/subdir.mk +-include Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk +-include Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk +-include Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := modularkbd +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +modularkbd.elf \ + +MAP_FILES += \ +modularkbd.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +modularkbd.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: modularkbd.elf secondary-outputs + +# Tool invocations +modularkbd.elf modularkbd.map: $(OBJS) $(USER_OBJS) /home/ukim/Projects/modular-kbd/firmware/67percent/STM32F446RETX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "modularkbd.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"/home/ukim/Projects/modular-kbd/firmware/67percent/STM32F446RETX_FLASH.ld" --specs=nosys.specs -Wl,-Map="modularkbd.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +modularkbd.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "modularkbd.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) default.size.stdout modularkbd.elf modularkbd.list modularkbd.map + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/firmware/67percent/Debug/modularkbd.elf b/firmware/67percent/Debug/modularkbd.elf new file mode 100755 index 00000000..4b7f5800 Binary files /dev/null and b/firmware/67percent/Debug/modularkbd.elf differ diff --git a/firmware/67percent/Debug/modularkbd.list b/firmware/67percent/Debug/modularkbd.list new file mode 100644 index 00000000..c1ab3d34 --- /dev/null +++ b/firmware/67percent/Debug/modularkbd.list @@ -0,0 +1,21363 @@ + +modularkbd.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000001c4 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 0000b218 080001c4 080001c4 000011c4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 0000005c 0800b3dc 0800b3dc 0000c3dc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 0800b438 0800b438 0000d1a0 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 0800b438 0800b438 0000c438 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 0800b440 0800b440 0000d1a0 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800b440 0800b440 0000c440 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 0800b444 0800b444 0000c444 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 000001a0 20000000 0800b448 0000d000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000015bc 200001a0 0800b5e8 0000d1a0 2**2 + ALLOC + 10 ._user_heap_stack 00000604 2000175c 0800b5e8 0000d75c 2**0 + ALLOC + 11 .ARM.attributes 00000030 00000000 00000000 0000d1a0 2**0 + CONTENTS, READONLY + 12 .debug_info 0001be15 00000000 00000000 0000d1d0 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 00004285 00000000 00000000 00028fe5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 000017f0 00000000 00000000 0002d270 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 00001291 00000000 00000000 0002ea60 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 000262b3 00000000 00000000 0002fcf1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 0001f083 00000000 00000000 00055fa4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 000d80a4 00000000 00000000 00075027 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 0014d0cb 2**0 + CONTENTS, READONLY + 20 .debug_frame 0000645c 00000000 00000000 0014d110 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000062 00000000 00000000 0015356c 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080001c4 <__do_global_dtors_aux>: + 80001c4: b510 push {r4, lr} + 80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>) + 80001c8: 7823 ldrb r3, [r4, #0] + 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> + 80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>) + 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> + 80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>) + 80001d2: f3af 8000 nop.w + 80001d6: 2301 movs r3, #1 + 80001d8: 7023 strb r3, [r4, #0] + 80001da: bd10 pop {r4, pc} + 80001dc: 200001a0 .word 0x200001a0 + 80001e0: 00000000 .word 0x00000000 + 80001e4: 0800b3c4 .word 0x0800b3c4 + +080001e8 : + 80001e8: b508 push {r3, lr} + 80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 ) + 80001ec: b11b cbz r3, 80001f6 + 80001ee: 4903 ldr r1, [pc, #12] @ (80001fc ) + 80001f0: 4803 ldr r0, [pc, #12] @ (8000200 ) + 80001f2: f3af 8000 nop.w + 80001f6: bd08 pop {r3, pc} + 80001f8: 00000000 .word 0x00000000 + 80001fc: 200001a4 .word 0x200001a4 + 8000200: 0800b3c4 .word 0x0800b3c4 + +08000204 <__aeabi_uldivmod>: + 8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18> + 8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18> + 8000208: 2900 cmp r1, #0 + 800020a: bf08 it eq + 800020c: 2800 cmpeq r0, #0 + 800020e: bf1c itt ne + 8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8000218: f000 b988 b.w 800052c <__aeabi_idiv0> + 800021c: f1ad 0c08 sub.w ip, sp, #8 + 8000220: e96d ce04 strd ip, lr, [sp, #-16]! + 8000224: f000 f806 bl 8000234 <__udivmoddi4> + 8000228: f8dd e004 ldr.w lr, [sp, #4] + 800022c: e9dd 2302 ldrd r2, r3, [sp, #8] + 8000230: b004 add sp, #16 + 8000232: 4770 bx lr + +08000234 <__udivmoddi4>: + 8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8000238: 9d08 ldr r5, [sp, #32] + 800023a: 468e mov lr, r1 + 800023c: 4604 mov r4, r0 + 800023e: 4688 mov r8, r1 + 8000240: 2b00 cmp r3, #0 + 8000242: d14a bne.n 80002da <__udivmoddi4+0xa6> + 8000244: 428a cmp r2, r1 + 8000246: 4617 mov r7, r2 + 8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc> + 800024a: fab2 f682 clz r6, r2 + 800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30> + 8000250: f1c6 0320 rsb r3, r6, #32 + 8000254: fa01 f806 lsl.w r8, r1, r6 + 8000258: fa20 f303 lsr.w r3, r0, r3 + 800025c: 40b7 lsls r7, r6 + 800025e: ea43 0808 orr.w r8, r3, r8 + 8000262: 40b4 lsls r4, r6 + 8000264: ea4f 4e17 mov.w lr, r7, lsr #16 + 8000268: fa1f fc87 uxth.w ip, r7 + 800026c: fbb8 f1fe udiv r1, r8, lr + 8000270: 0c23 lsrs r3, r4, #16 + 8000272: fb0e 8811 mls r8, lr, r1, r8 + 8000276: ea43 4308 orr.w r3, r3, r8, lsl #16 + 800027a: fb01 f20c mul.w r2, r1, ip + 800027e: 429a cmp r2, r3 + 8000280: d909 bls.n 8000296 <__udivmoddi4+0x62> + 8000282: 18fb adds r3, r7, r3 + 8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c> + 800028c: 429a cmp r2, r3 + 800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c> + 8000292: 3902 subs r1, #2 + 8000294: 443b add r3, r7 + 8000296: 1a9a subs r2, r3, r2 + 8000298: b2a3 uxth r3, r4 + 800029a: fbb2 f0fe udiv r0, r2, lr + 800029e: fb0e 2210 mls r2, lr, r0, r2 + 80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002a6: fb00 fc0c mul.w ip, r0, ip + 80002aa: 459c cmp ip, r3 + 80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e> + 80002ae: 18fb adds r3, r7, r3 + 80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230> + 80002b8: 459c cmp ip, r3 + 80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230> + 80002be: 443b add r3, r7 + 80002c0: 3802 subs r0, #2 + 80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16 + 80002c6: eba3 030c sub.w r3, r3, ip + 80002ca: 2100 movs r1, #0 + 80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2> + 80002ce: 40f3 lsrs r3, r6 + 80002d0: 2200 movs r2, #0 + 80002d2: e9c5 3200 strd r3, r2, [r5] + 80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 80002da: 428b cmp r3, r1 + 80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6> + 80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0> + 80002e0: e9c5 0100 strd r0, r1, [r5] + 80002e4: 2100 movs r1, #0 + 80002e6: 4608 mov r0, r1 + 80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2> + 80002ea: fab3 f183 clz r1, r3 + 80002ee: 2900 cmp r1, #0 + 80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c> + 80002f2: 4573 cmp r3, lr + 80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8> + 80002f6: 4282 cmp r2, r0 + 80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2> + 80002fc: 1a84 subs r4, r0, r2 + 80002fe: eb6e 0203 sbc.w r2, lr, r3 + 8000302: 2001 movs r0, #1 + 8000304: 4690 mov r8, r2 + 8000306: 2d00 cmp r5, #0 + 8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2> + 800030a: e9c5 4800 strd r4, r8, [r5] + 800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2> + 8000310: 2a00 cmp r2, #0 + 8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202> + 8000316: fab2 f682 clz r6, r2 + 800031a: 2e00 cmp r6, #0 + 800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234> + 8000320: 1a8a subs r2, r1, r2 + 8000322: 0c03 lsrs r3, r0, #16 + 8000324: ea4f 4e17 mov.w lr, r7, lsr #16 + 8000328: b280 uxth r0, r0 + 800032a: b2bc uxth r4, r7 + 800032c: 2101 movs r1, #1 + 800032e: fbb2 fcfe udiv ip, r2, lr + 8000332: fb0e 221c mls r2, lr, ip, r2 + 8000336: ea43 4302 orr.w r3, r3, r2, lsl #16 + 800033a: fb04 f20c mul.w r2, r4, ip + 800033e: 429a cmp r2, r3 + 8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e> + 8000342: 18fb adds r3, r7, r3 + 8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c> + 800034a: 429a cmp r2, r3 + 800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc> + 8000350: 46c4 mov ip, r8 + 8000352: 1a9b subs r3, r3, r2 + 8000354: fbb3 f2fe udiv r2, r3, lr + 8000358: fb0e 3312 mls r3, lr, r2, r3 + 800035c: ea40 4303 orr.w r3, r0, r3, lsl #16 + 8000360: fb02 f404 mul.w r4, r2, r4 + 8000364: 429c cmp r4, r3 + 8000366: d907 bls.n 8000378 <__udivmoddi4+0x144> + 8000368: 18fb adds r3, r7, r3 + 800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142> + 8000370: 429c cmp r4, r3 + 8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6> + 8000376: 4602 mov r2, r0 + 8000378: 1b1b subs r3, r3, r4 + 800037a: ea42 400c orr.w r0, r2, ip, lsl #16 + 800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98> + 8000380: f1c1 0620 rsb r6, r1, #32 + 8000384: 408b lsls r3, r1 + 8000386: fa22 f706 lsr.w r7, r2, r6 + 800038a: 431f orrs r7, r3 + 800038c: fa0e f401 lsl.w r4, lr, r1 + 8000390: fa20 f306 lsr.w r3, r0, r6 + 8000394: fa2e fe06 lsr.w lr, lr, r6 + 8000398: ea4f 4917 mov.w r9, r7, lsr #16 + 800039c: 4323 orrs r3, r4 + 800039e: fa00 f801 lsl.w r8, r0, r1 + 80003a2: fa1f fc87 uxth.w ip, r7 + 80003a6: fbbe f0f9 udiv r0, lr, r9 + 80003aa: 0c1c lsrs r4, r3, #16 + 80003ac: fb09 ee10 mls lr, r9, r0, lr + 80003b0: ea44 440e orr.w r4, r4, lr, lsl #16 + 80003b4: fb00 fe0c mul.w lr, r0, ip + 80003b8: 45a6 cmp lr, r4 + 80003ba: fa02 f201 lsl.w r2, r2, r1 + 80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0> + 80003c0: 193c adds r4, r7, r4 + 80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff + 80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce> + 80003ca: 45a6 cmp lr, r4 + 80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce> + 80003d0: 3802 subs r0, #2 + 80003d2: 443c add r4, r7 + 80003d4: eba4 040e sub.w r4, r4, lr + 80003d8: fa1f fe83 uxth.w lr, r3 + 80003dc: fbb4 f3f9 udiv r3, r4, r9 + 80003e0: fb09 4413 mls r4, r9, r3, r4 + 80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16 + 80003e8: fb03 fc0c mul.w ip, r3, ip + 80003ec: 45a4 cmp ip, r4 + 80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce> + 80003f0: 193c adds r4, r7, r4 + 80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff + 80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca> + 80003fa: 45a4 cmp ip, r4 + 80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca> + 80003fe: 3b02 subs r3, #2 + 8000400: 443c add r4, r7 + 8000402: ea43 4000 orr.w r0, r3, r0, lsl #16 + 8000406: eba4 040c sub.w r4, r4, ip + 800040a: fba0 ec02 umull lr, ip, r0, r2 + 800040e: 4564 cmp r4, ip + 8000410: 4673 mov r3, lr + 8000412: 46e1 mov r9, ip + 8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8> + 8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4> + 8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe> + 800041a: ebb8 0203 subs.w r2, r8, r3 + 800041e: eb64 0409 sbc.w r4, r4, r9 + 8000422: fa04 f606 lsl.w r6, r4, r6 + 8000426: fa22 f301 lsr.w r3, r2, r1 + 800042a: 431e orrs r6, r3 + 800042c: 40cc lsrs r4, r1 + 800042e: e9c5 6400 strd r6, r4, [r5] + 8000432: 2100 movs r1, #0 + 8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2> + 8000436: fbb1 fcf2 udiv ip, r1, r2 + 800043a: 0c01 lsrs r1, r0, #16 + 800043c: ea41 410e orr.w r1, r1, lr, lsl #16 + 8000440: b280 uxth r0, r0 + 8000442: ea40 4201 orr.w r2, r0, r1, lsl #16 + 8000446: 463b mov r3, r7 + 8000448: 4638 mov r0, r7 + 800044a: 463c mov r4, r7 + 800044c: 46b8 mov r8, r7 + 800044e: 46be mov lr, r7 + 8000450: 2620 movs r6, #32 + 8000452: fbb1 f1f7 udiv r1, r1, r7 + 8000456: eba2 0208 sub.w r2, r2, r8 + 800045a: ea41 410c orr.w r1, r1, ip, lsl #16 + 800045e: e766 b.n 800032e <__udivmoddi4+0xfa> + 8000460: 4601 mov r1, r0 + 8000462: e718 b.n 8000296 <__udivmoddi4+0x62> + 8000464: 4610 mov r0, r2 + 8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e> + 8000468: f1c6 0220 rsb r2, r6, #32 + 800046c: fa2e f302 lsr.w r3, lr, r2 + 8000470: 40b7 lsls r7, r6 + 8000472: 40b1 lsls r1, r6 + 8000474: fa20 f202 lsr.w r2, r0, r2 + 8000478: ea4f 4e17 mov.w lr, r7, lsr #16 + 800047c: 430a orrs r2, r1 + 800047e: fbb3 f8fe udiv r8, r3, lr + 8000482: b2bc uxth r4, r7 + 8000484: fb0e 3318 mls r3, lr, r8, r3 + 8000488: 0c11 lsrs r1, r2, #16 + 800048a: ea41 4103 orr.w r1, r1, r3, lsl #16 + 800048e: fb08 f904 mul.w r9, r8, r4 + 8000492: 40b0 lsls r0, r6 + 8000494: 4589 cmp r9, r1 + 8000496: ea4f 4310 mov.w r3, r0, lsr #16 + 800049a: b280 uxth r0, r0 + 800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8> + 800049e: 1879 adds r1, r7, r1 + 80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276> + 80004a6: 4589 cmp r9, r1 + 80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6> + 80004aa: eba1 0109 sub.w r1, r1, r9 + 80004ae: fbb1 f9fe udiv r9, r1, lr + 80004b2: fb09 f804 mul.w r8, r9, r4 + 80004b6: fb0e 1119 mls r1, lr, r9, r1 + 80004ba: b292 uxth r2, r2 + 80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16 + 80004c0: 4542 cmp r2, r8 + 80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4> + 80004c4: 18ba adds r2, r7, r2 + 80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222> + 80004cc: 4542 cmp r2, r8 + 80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222> + 80004d0: f1a9 0102 sub.w r1, r9, #2 + 80004d4: 443a add r2, r7 + 80004d6: e7be b.n 8000456 <__udivmoddi4+0x222> + 80004d8: 45f0 cmp r8, lr + 80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4> + 80004dc: ebbe 0302 subs.w r3, lr, r2 + 80004e0: eb6c 0c07 sbc.w ip, ip, r7 + 80004e4: 3801 subs r0, #1 + 80004e6: 46e1 mov r9, ip + 80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4> + 80004ea: eba7 0909 sub.w r9, r7, r9 + 80004ee: 4449 add r1, r9 + 80004f0: f1a8 0c02 sub.w ip, r8, #2 + 80004f4: fbb1 f9fe udiv r9, r1, lr + 80004f8: fb09 f804 mul.w r8, r9, r4 + 80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282> + 80004fe: 4673 mov r3, lr + 8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce> + 8000502: 4650 mov r0, sl + 8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0> + 8000506: 4608 mov r0, r1 + 8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2> + 800050a: 443b add r3, r7 + 800050c: 3a02 subs r2, #2 + 800050e: e733 b.n 8000378 <__udivmoddi4+0x144> + 8000510: f1ac 0c02 sub.w ip, ip, #2 + 8000514: 443b add r3, r7 + 8000516: e71c b.n 8000352 <__udivmoddi4+0x11e> + 8000518: 4649 mov r1, r9 + 800051a: e79c b.n 8000456 <__udivmoddi4+0x222> + 800051c: eba1 0109 sub.w r1, r1, r9 + 8000520: 46c4 mov ip, r8 + 8000522: fbb1 f9fe udiv r9, r1, lr + 8000526: fb09 f804 mul.w r8, r9, r4 + 800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282> + +0800052c <__aeabi_idiv0>: + 800052c: 4770 bx lr + 800052e: bf00 nop + +08000530 : + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + 8000530: b580 push {r7, lr} + 8000532: b082 sub sp, #8 + 8000534: af00 add r7, sp, #0 + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + 8000536: 2300 movs r3, #0 + 8000538: 607b str r3, [r7, #4] + 800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 ) + 800053c: 6b1b ldr r3, [r3, #48] @ 0x30 + 800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 ) + 8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 + 8000544: 6313 str r3, [r2, #48] @ 0x30 + 8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 ) + 8000548: 6b1b ldr r3, [r3, #48] @ 0x30 + 800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 800054e: 607b str r3, [r7, #4] + 8000550: 687b ldr r3, [r7, #4] + __HAL_RCC_DMA2_CLK_ENABLE(); + 8000552: 2300 movs r3, #0 + 8000554: 603b str r3, [r7, #0] + 8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 ) + 8000558: 6b1b ldr r3, [r3, #48] @ 0x30 + 800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 ) + 800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 + 8000560: 6313 str r3, [r2, #48] @ 0x30 + 8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 ) + 8000564: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 800056a: 603b str r3, [r7, #0] + 800056c: 683b ldr r3, [r7, #0] + + /* DMA interrupt init */ + /* DMA1_Stream0_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); + 800056e: 2200 movs r2, #0 + 8000570: 2100 movs r1, #0 + 8000572: 200b movs r0, #11 + 8000574: f001 fde3 bl 800213e + HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); + 8000578: 200b movs r0, #11 + 800057a: f001 fdfc bl 8002176 + /* DMA1_Stream2_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); + 800057e: 2200 movs r2, #0 + 8000580: 2100 movs r1, #0 + 8000582: 200d movs r0, #13 + 8000584: f001 fddb bl 800213e + HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); + 8000588: 200d movs r0, #13 + 800058a: f001 fdf4 bl 8002176 + /* DMA1_Stream4_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); + 800058e: 2200 movs r2, #0 + 8000590: 2100 movs r1, #0 + 8000592: 200f movs r0, #15 + 8000594: f001 fdd3 bl 800213e + HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); + 8000598: 200f movs r0, #15 + 800059a: f001 fdec bl 8002176 + /* DMA1_Stream5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); + 800059e: 2200 movs r2, #0 + 80005a0: 2100 movs r1, #0 + 80005a2: 2010 movs r0, #16 + 80005a4: f001 fdcb bl 800213e + HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); + 80005a8: 2010 movs r0, #16 + 80005aa: f001 fde4 bl 8002176 + /* DMA1_Stream6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); + 80005ae: 2200 movs r2, #0 + 80005b0: 2100 movs r1, #0 + 80005b2: 2011 movs r0, #17 + 80005b4: f001 fdc3 bl 800213e + HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); + 80005b8: 2011 movs r0, #17 + 80005ba: f001 fddc bl 8002176 + /* DMA1_Stream7_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); + 80005be: 2200 movs r2, #0 + 80005c0: 2100 movs r1, #0 + 80005c2: 202f movs r0, #47 @ 0x2f + 80005c4: f001 fdbb bl 800213e + HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); + 80005c8: 202f movs r0, #47 @ 0x2f + 80005ca: f001 fdd4 bl 8002176 + /* DMA2_Stream2_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); + 80005ce: 2200 movs r2, #0 + 80005d0: 2100 movs r1, #0 + 80005d2: 203a movs r0, #58 @ 0x3a + 80005d4: f001 fdb3 bl 800213e + HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); + 80005d8: 203a movs r0, #58 @ 0x3a + 80005da: f001 fdcc bl 8002176 + /* DMA2_Stream7_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); + 80005de: 2200 movs r2, #0 + 80005e0: 2100 movs r1, #0 + 80005e2: 2046 movs r0, #70 @ 0x46 + 80005e4: f001 fdab bl 800213e + HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); + 80005e8: 2046 movs r0, #70 @ 0x46 + 80005ea: f001 fdc4 bl 8002176 + +} + 80005ee: bf00 nop + 80005f0: 3708 adds r7, #8 + 80005f2: 46bd mov sp, r7 + 80005f4: bd80 pop {r7, pc} + 80005f6: bf00 nop + 80005f8: 40023800 .word 0x40023800 + +080005fc : + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + 80005fc: b580 push {r7, lr} + 80005fe: b08a sub sp, #40 @ 0x28 + 8000600: af00 add r7, sp, #0 + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000602: f107 0314 add.w r3, r7, #20 + 8000606: 2200 movs r2, #0 + 8000608: 601a str r2, [r3, #0] + 800060a: 605a str r2, [r3, #4] + 800060c: 609a str r2, [r3, #8] + 800060e: 60da str r2, [r3, #12] + 8000610: 611a str r2, [r3, #16] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOH_CLK_ENABLE(); + 8000612: 2300 movs r3, #0 + 8000614: 613b str r3, [r7, #16] + 8000616: 4b45 ldr r3, [pc, #276] @ (800072c ) + 8000618: 6b1b ldr r3, [r3, #48] @ 0x30 + 800061a: 4a44 ldr r2, [pc, #272] @ (800072c ) + 800061c: f043 0380 orr.w r3, r3, #128 @ 0x80 + 8000620: 6313 str r3, [r2, #48] @ 0x30 + 8000622: 4b42 ldr r3, [pc, #264] @ (800072c ) + 8000624: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000626: f003 0380 and.w r3, r3, #128 @ 0x80 + 800062a: 613b str r3, [r7, #16] + 800062c: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800062e: 2300 movs r3, #0 + 8000630: 60fb str r3, [r7, #12] + 8000632: 4b3e ldr r3, [pc, #248] @ (800072c ) + 8000634: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000636: 4a3d ldr r2, [pc, #244] @ (800072c ) + 8000638: f043 0301 orr.w r3, r3, #1 + 800063c: 6313 str r3, [r2, #48] @ 0x30 + 800063e: 4b3b ldr r3, [pc, #236] @ (800072c ) + 8000640: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000642: f003 0301 and.w r3, r3, #1 + 8000646: 60fb str r3, [r7, #12] + 8000648: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800064a: 2300 movs r3, #0 + 800064c: 60bb str r3, [r7, #8] + 800064e: 4b37 ldr r3, [pc, #220] @ (800072c ) + 8000650: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000652: 4a36 ldr r2, [pc, #216] @ (800072c ) + 8000654: f043 0304 orr.w r3, r3, #4 + 8000658: 6313 str r3, [r2, #48] @ 0x30 + 800065a: 4b34 ldr r3, [pc, #208] @ (800072c ) + 800065c: 6b1b ldr r3, [r3, #48] @ 0x30 + 800065e: f003 0304 and.w r3, r3, #4 + 8000662: 60bb str r3, [r7, #8] + 8000664: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000666: 2300 movs r3, #0 + 8000668: 607b str r3, [r7, #4] + 800066a: 4b30 ldr r3, [pc, #192] @ (800072c ) + 800066c: 6b1b ldr r3, [r3, #48] @ 0x30 + 800066e: 4a2f ldr r2, [pc, #188] @ (800072c ) + 8000670: f043 0302 orr.w r3, r3, #2 + 8000674: 6313 str r3, [r2, #48] @ 0x30 + 8000676: 4b2d ldr r3, [pc, #180] @ (800072c ) + 8000678: 6b1b ldr r3, [r3, #48] @ 0x30 + 800067a: f003 0302 and.w r3, r3, #2 + 800067e: 607b str r3, [r7, #4] + 8000680: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8000682: 2300 movs r3, #0 + 8000684: 603b str r3, [r7, #0] + 8000686: 4b29 ldr r3, [pc, #164] @ (800072c ) + 8000688: 6b1b ldr r3, [r3, #48] @ 0x30 + 800068a: 4a28 ldr r2, [pc, #160] @ (800072c ) + 800068c: f043 0308 orr.w r3, r3, #8 + 8000690: 6313 str r3, [r2, #48] @ 0x30 + 8000692: 4b26 ldr r3, [pc, #152] @ (800072c ) + 8000694: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000696: f003 0308 and.w r3, r3, #8 + 800069a: 603b str r3, [r7, #0] + 800069c: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); + 800069e: 2200 movs r2, #0 + 80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0 + 80006a4: 4822 ldr r0, [pc, #136] @ (8000730 ) + 80006a6: f002 fb2f bl 8002d08 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); + 80006aa: 2200 movs r2, #0 + 80006ac: f44f 7180 mov.w r1, #256 @ 0x100 + 80006b0: 4820 ldr r0, [pc, #128] @ (8000734 ) + 80006b2: f002 fb29 bl 8002d08 + + /*Configure GPIO pins : PC4 PC5 */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; + 80006b6: 2330 movs r3, #48 @ 0x30 + 80006b8: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 80006ba: 2300 movs r3, #0 + 80006bc: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + 80006be: 2302 movs r3, #2 + 80006c0: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80006c2: f107 0314 add.w r3, r7, #20 + 80006c6: 4619 mov r1, r3 + 80006c8: 4819 ldr r0, [pc, #100] @ (8000730 ) + 80006ca: f002 f971 bl 80029b0 + + /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; + 80006ce: f240 4307 movw r3, #1031 @ 0x407 + 80006d2: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 80006d4: 2300 movs r3, #0 + 80006d6: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + 80006d8: 2302 movs r3, #2 + 80006da: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80006dc: f107 0314 add.w r3, r7, #20 + 80006e0: 4619 mov r1, r3 + 80006e2: 4815 ldr r0, [pc, #84] @ (8000738 ) + 80006e4: f002 f964 bl 80029b0 + + /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; + 80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0 + 80006ec: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80006ee: 2301 movs r3, #1 + 80006f0: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80006f2: 2300 movs r3, #0 + 80006f4: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80006f6: 2300 movs r3, #0 + 80006f8: 623b str r3, [r7, #32] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80006fa: f107 0314 add.w r3, r7, #20 + 80006fe: 4619 mov r1, r3 + 8000700: 480b ldr r0, [pc, #44] @ (8000730 ) + 8000702: f002 f955 bl 80029b0 + + /*Configure GPIO pin : PA8 */ + GPIO_InitStruct.Pin = GPIO_PIN_8; + 8000706: f44f 7380 mov.w r3, #256 @ 0x100 + 800070a: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800070c: 2301 movs r3, #1 + 800070e: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000710: 2300 movs r3, #0 + 8000712: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000714: 2300 movs r3, #0 + 8000716: 623b str r3, [r7, #32] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000718: f107 0314 add.w r3, r7, #20 + 800071c: 4619 mov r1, r3 + 800071e: 4805 ldr r0, [pc, #20] @ (8000734 ) + 8000720: f002 f946 bl 80029b0 + +} + 8000724: bf00 nop + 8000726: 3728 adds r7, #40 @ 0x28 + 8000728: 46bd mov sp, r7 + 800072a: bd80 pop {r7, pc} + 800072c: 40023800 .word 0x40023800 + 8000730: 40020800 .word 0x40020800 + 8000734: 40020000 .word 0x40020000 + 8000738: 40020400 .word 0x40020400 + +0800073c : + +I2C_HandleTypeDef hi2c1; + +/* I2C1 init function */ +void MX_I2C1_Init(void) +{ + 800073c: b580 push {r7, lr} + 800073e: af00 add r7, sp, #0 + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + 8000740: 4b12 ldr r3, [pc, #72] @ (800078c ) + 8000742: 4a13 ldr r2, [pc, #76] @ (8000790 ) + 8000744: 601a str r2, [r3, #0] + hi2c1.Init.ClockSpeed = 100000; + 8000746: 4b11 ldr r3, [pc, #68] @ (800078c ) + 8000748: 4a12 ldr r2, [pc, #72] @ (8000794 ) + 800074a: 605a str r2, [r3, #4] + hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; + 800074c: 4b0f ldr r3, [pc, #60] @ (800078c ) + 800074e: 2200 movs r2, #0 + 8000750: 609a str r2, [r3, #8] + hi2c1.Init.OwnAddress1 = 0; + 8000752: 4b0e ldr r3, [pc, #56] @ (800078c ) + 8000754: 2200 movs r2, #0 + 8000756: 60da str r2, [r3, #12] + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 8000758: 4b0c ldr r3, [pc, #48] @ (800078c ) + 800075a: f44f 4280 mov.w r2, #16384 @ 0x4000 + 800075e: 611a str r2, [r3, #16] + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 8000760: 4b0a ldr r3, [pc, #40] @ (800078c ) + 8000762: 2200 movs r2, #0 + 8000764: 615a str r2, [r3, #20] + hi2c1.Init.OwnAddress2 = 0; + 8000766: 4b09 ldr r3, [pc, #36] @ (800078c ) + 8000768: 2200 movs r2, #0 + 800076a: 619a str r2, [r3, #24] + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 800076c: 4b07 ldr r3, [pc, #28] @ (800078c ) + 800076e: 2200 movs r2, #0 + 8000770: 61da str r2, [r3, #28] + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 8000772: 4b06 ldr r3, [pc, #24] @ (800078c ) + 8000774: 2200 movs r2, #0 + 8000776: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 8000778: 4804 ldr r0, [pc, #16] @ (800078c ) + 800077a: f002 fadf bl 8002d3c + 800077e: 4603 mov r3, r0 + 8000780: 2b00 cmp r3, #0 + 8000782: d001 beq.n 8000788 + { + Error_Handler(); + 8000784: f000 fd60 bl 8001248 + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + 8000788: bf00 nop + 800078a: bd80 pop {r7, pc} + 800078c: 200001bc .word 0x200001bc + 8000790: 40005400 .word 0x40005400 + 8000794: 000186a0 .word 0x000186a0 + +08000798 : + +void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) +{ + 8000798: b580 push {r7, lr} + 800079a: b08a sub sp, #40 @ 0x28 + 800079c: af00 add r7, sp, #0 + 800079e: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80007a0: f107 0314 add.w r3, r7, #20 + 80007a4: 2200 movs r2, #0 + 80007a6: 601a str r2, [r3, #0] + 80007a8: 605a str r2, [r3, #4] + 80007aa: 609a str r2, [r3, #8] + 80007ac: 60da str r2, [r3, #12] + 80007ae: 611a str r2, [r3, #16] + if(i2cHandle->Instance==I2C1) + 80007b0: 687b ldr r3, [r7, #4] + 80007b2: 681b ldr r3, [r3, #0] + 80007b4: 4a19 ldr r2, [pc, #100] @ (800081c ) + 80007b6: 4293 cmp r3, r2 + 80007b8: d12b bne.n 8000812 + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + 80007ba: 2300 movs r3, #0 + 80007bc: 613b str r3, [r7, #16] + 80007be: 4b18 ldr r3, [pc, #96] @ (8000820 ) + 80007c0: 6b1b ldr r3, [r3, #48] @ 0x30 + 80007c2: 4a17 ldr r2, [pc, #92] @ (8000820 ) + 80007c4: f043 0302 orr.w r3, r3, #2 + 80007c8: 6313 str r3, [r2, #48] @ 0x30 + 80007ca: 4b15 ldr r3, [pc, #84] @ (8000820 ) + 80007cc: 6b1b ldr r3, [r3, #48] @ 0x30 + 80007ce: f003 0302 and.w r3, r3, #2 + 80007d2: 613b str r3, [r7, #16] + 80007d4: 693b ldr r3, [r7, #16] + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + 80007d6: 23c0 movs r3, #192 @ 0xc0 + 80007d8: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 80007da: 2312 movs r3, #18 + 80007dc: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80007de: 2300 movs r3, #0 + 80007e0: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80007e2: 2303 movs r3, #3 + 80007e4: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 80007e6: 2304 movs r3, #4 + 80007e8: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80007ea: f107 0314 add.w r3, r7, #20 + 80007ee: 4619 mov r1, r3 + 80007f0: 480c ldr r0, [pc, #48] @ (8000824 ) + 80007f2: f002 f8dd bl 80029b0 + + /* I2C1 clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + 80007f6: 2300 movs r3, #0 + 80007f8: 60fb str r3, [r7, #12] + 80007fa: 4b09 ldr r3, [pc, #36] @ (8000820 ) + 80007fc: 6c1b ldr r3, [r3, #64] @ 0x40 + 80007fe: 4a08 ldr r2, [pc, #32] @ (8000820 ) + 8000800: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 + 8000804: 6413 str r3, [r2, #64] @ 0x40 + 8000806: 4b06 ldr r3, [pc, #24] @ (8000820 ) + 8000808: 6c1b ldr r3, [r3, #64] @ 0x40 + 800080a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 800080e: 60fb str r3, [r7, #12] + 8000810: 68fb ldr r3, [r7, #12] + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } +} + 8000812: bf00 nop + 8000814: 3728 adds r7, #40 @ 0x28 + 8000816: 46bd mov sp, r7 + 8000818: bd80 pop {r7, pc} + 800081a: bf00 nop + 800081c: 40005400 .word 0x40005400 + 8000820: 40023800 .word 0x40023800 + 8000824: 40020400 .word 0x40020400 + +08000828 : + volatile uint8_t tail; // accessed in ISR + volatile uint8_t count; // optional, only if needed +} PacketQueue; + +// Initialize +void pq_init(PacketQueue *q){ + 8000828: b480 push {r7} + 800082a: b083 sub sp, #12 + 800082c: af00 add r7, sp, #0 + 800082e: 6078 str r0, [r7, #4] + q->head = 0; + 8000830: 687b ldr r3, [r7, #4] + 8000832: 2200 movs r2, #0 + 8000834: f883 2180 strb.w r2, [r3, #384] @ 0x180 + q->tail = 0; + 8000838: 687b ldr r3, [r7, #4] + 800083a: 2200 movs r2, #0 + 800083c: f883 2181 strb.w r2, [r3, #385] @ 0x181 + q->count = 0; + 8000840: 687b ldr r3, [r7, #4] + 8000842: 2200 movs r2, #0 + 8000844: f883 2182 strb.w r2, [r3, #386] @ 0x182 +} + 8000848: bf00 nop + 800084a: 370c adds r7, #12 + 800084c: 46bd mov sp, r7 + 800084e: f85d 7b04 ldr.w r7, [sp], #4 + 8000852: 4770 bx lr + +08000854 : + +// Called from ISR +bool pq_push(PacketQueue *q, const uint8_t packet[PACKET_SIZE]){ + 8000854: b580 push {r7, lr} + 8000856: b084 sub sp, #16 + 8000858: af00 add r7, sp, #0 + 800085a: 6078 str r0, [r7, #4] + 800085c: 6039 str r1, [r7, #0] + uint8_t nextTail = (q->tail + 1) % QUEUE_CAPACITY; + 800085e: 687b ldr r3, [r7, #4] + 8000860: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 + 8000864: b2db uxtb r3, r3 + 8000866: 3301 adds r3, #1 + 8000868: 425a negs r2, r3 + 800086a: f003 031f and.w r3, r3, #31 + 800086e: f002 021f and.w r2, r2, #31 + 8000872: bf58 it pl + 8000874: 4253 negpl r3, r2 + 8000876: 73fb strb r3, [r7, #15] + if(nextTail == q->head) return false; // queue full + 8000878: 687b ldr r3, [r7, #4] + 800087a: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 + 800087e: b2db uxtb r3, r3 + 8000880: 7bfa ldrb r2, [r7, #15] + 8000882: 429a cmp r2, r3 + 8000884: d101 bne.n 800088a + 8000886: 2300 movs r3, #0 + 8000888: e014 b.n 80008b4 + + memcpy(q->data[q->tail], packet, PACKET_SIZE); + 800088a: 687b ldr r3, [r7, #4] + 800088c: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 + 8000890: b2db uxtb r3, r3 + 8000892: 461a mov r2, r3 + 8000894: 4613 mov r3, r2 + 8000896: 005b lsls r3, r3, #1 + 8000898: 4413 add r3, r2 + 800089a: 009b lsls r3, r3, #2 + 800089c: 687a ldr r2, [r7, #4] + 800089e: 4413 add r3, r2 + 80008a0: 220c movs r2, #12 + 80008a2: 6839 ldr r1, [r7, #0] + 80008a4: 4618 mov r0, r3 + 80008a6: f00a fd7f bl 800b3a8 + q->tail = nextTail; + 80008aa: 687b ldr r3, [r7, #4] + 80008ac: 7bfa ldrb r2, [r7, #15] + 80008ae: f883 2181 strb.w r2, [r3, #385] @ 0x181 + return true; + 80008b2: 2301 movs r3, #1 +} + 80008b4: 4618 mov r0, r3 + 80008b6: 3710 adds r7, #16 + 80008b8: 46bd mov sp, r7 + 80008ba: bd80 pop {r7, pc} + +080008bc : + +// Called from main +bool pq_pop(PacketQueue *q, uint8_t out_packet[PACKET_SIZE]){ + 80008bc: b580 push {r7, lr} + 80008be: b082 sub sp, #8 + 80008c0: af00 add r7, sp, #0 + 80008c2: 6078 str r0, [r7, #4] + 80008c4: 6039 str r1, [r7, #0] + if(q->head == q->tail) return false; // queue empty + 80008c6: 687b ldr r3, [r7, #4] + 80008c8: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 + 80008cc: b2da uxtb r2, r3 + 80008ce: 687b ldr r3, [r7, #4] + 80008d0: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 + 80008d4: b2db uxtb r3, r3 + 80008d6: 429a cmp r2, r3 + 80008d8: d101 bne.n 80008de + 80008da: 2300 movs r3, #0 + 80008dc: e020 b.n 8000920 + + memcpy(out_packet, q->data[q->head], PACKET_SIZE); + 80008de: 687b ldr r3, [r7, #4] + 80008e0: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 + 80008e4: b2db uxtb r3, r3 + 80008e6: 461a mov r2, r3 + 80008e8: 4613 mov r3, r2 + 80008ea: 005b lsls r3, r3, #1 + 80008ec: 4413 add r3, r2 + 80008ee: 009b lsls r3, r3, #2 + 80008f0: 687a ldr r2, [r7, #4] + 80008f2: 4413 add r3, r2 + 80008f4: 220c movs r2, #12 + 80008f6: 4619 mov r1, r3 + 80008f8: 6838 ldr r0, [r7, #0] + 80008fa: f00a fd55 bl 800b3a8 + q->head = (q->head + 1) % QUEUE_CAPACITY; + 80008fe: 687b ldr r3, [r7, #4] + 8000900: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 + 8000904: b2db uxtb r3, r3 + 8000906: 3301 adds r3, #1 + 8000908: 425a negs r2, r3 + 800090a: f003 031f and.w r3, r3, #31 + 800090e: f002 021f and.w r2, r2, #31 + 8000912: bf58 it pl + 8000914: 4253 negpl r3, r2 + 8000916: b2da uxtb r2, r3 + 8000918: 687b ldr r3, [r7, #4] + 800091a: f883 2180 strb.w r2, [r3, #384] @ 0x180 + return true; + 800091e: 2301 movs r3, #1 +} + 8000920: 4618 mov r0, r3 + 8000922: 3708 adds r7, #8 + 8000924: 46bd mov sp, r7 + 8000926: bd80 pop {r7, pc} + +08000928
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8000928: b580 push {r7, lr} + 800092a: b088 sub sp, #32 + 800092c: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 800092e: f001 fa95 bl 8001e5c + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8000932: f000 f97b bl 8000c2c + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000936: f7ff fe61 bl 80005fc + MX_DMA_Init();MX_PWM_Init(); + 800093a: f7ff fdf9 bl 8000530 + 800093e: f000 fc89 bl 8001254 + MX_TIM2_Init(); + 8000942: f000 fdab bl 800149c + MX_TIM3_Init(); + 8000946: f000 fe01 bl 800154c + MX_UART4_Init(); + 800094a: f000 fef3 bl 8001734 + MX_UART5_Init(); + 800094e: f000 ff1b bl 8001788 + MX_USART1_UART_Init(); + 8000952: f000 ff43 bl 80017dc + MX_USART2_UART_Init(); + 8000956: f000 ff6b bl 8001830 + MX_I2C1_Init(); + 800095a: f7ff feef bl 800073c + MX_USB_DEVICE_Init(); + 800095e: f00a f849 bl 800a9f4 + MX_PWM_Init(); + 8000962: f000 fc77 bl 8001254 + /* USER CODE BEGIN 2 */ + + //Enable UART RX DMA for all ports + HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); + 8000966: 2210 movs r2, #16 + 8000968: 4958 ldr r1, [pc, #352] @ (8000acc ) + 800096a: 4859 ldr r0, [pc, #356] @ (8000ad0 ) + 800096c: f005 fe48 bl 8006600 + HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); + 8000970: 2210 movs r2, #16 + 8000972: 4958 ldr r1, [pc, #352] @ (8000ad4 ) + 8000974: 4858 ldr r0, [pc, #352] @ (8000ad8 ) + 8000976: f005 fe43 bl 8006600 + HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); + 800097a: 2210 movs r2, #16 + 800097c: 4957 ldr r1, [pc, #348] @ (8000adc ) + 800097e: 4858 ldr r0, [pc, #352] @ (8000ae0 ) + 8000980: f005 fe3e bl 8006600 + HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); + 8000984: 2210 movs r2, #16 + 8000986: 4957 ldr r1, [pc, #348] @ (8000ae4 ) + 8000988: 4857 ldr r0, [pc, #348] @ (8000ae8 ) + 800098a: f005 fe39 bl 8006600 + + // Start TIM3 encoder (PA6/PA7) so we can read encoder delta + HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL); + 800098e: 213c movs r1, #60 @ 0x3c + 8000990: 4856 ldr r0, [pc, #344] @ (8000aec ) + 8000992: f005 f8c5 bl 8005b20 + LAST_ENCODER_COUNT = __HAL_TIM_GET_COUNTER(&htim3); + 8000996: 4b55 ldr r3, [pc, #340] @ (8000aec ) + 8000998: 681b ldr r3, [r3, #0] + 800099a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800099c: 461a mov r2, r3 + 800099e: 4b54 ldr r3, [pc, #336] @ (8000af0 ) + 80009a0: 601a str r2, [r3, #0] + + //Prealloc Kestate matrix + memset(KEYSTATE, 0, sizeof(KEYSTATE)); + 80009a2: 221e movs r2, #30 + 80009a4: 2100 movs r1, #0 + 80009a6: 4853 ldr r0, [pc, #332] @ (8000af4 ) + 80009a8: f00a fcd2 bl 800b350 + pq_init(&huart1q); + 80009ac: 4852 ldr r0, [pc, #328] @ (8000af8 ) + 80009ae: f7ff ff3b bl 8000828 + pq_init(&huart2q); + 80009b2: 4852 ldr r0, [pc, #328] @ (8000afc ) + 80009b4: f7ff ff38 bl 8000828 + pq_init(&huart4q); + 80009b8: 4851 ldr r0, [pc, #324] @ (8000b00 ) + 80009ba: f7ff ff35 bl 8000828 + pq_init(&huart5q); + 80009be: 4851 ldr r0, [pc, #324] @ (8000b04 ) + 80009c0: f7ff ff32 bl 8000828 + + PWM_Start(); + 80009c4: f000 fc74 bl 80012b0 + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + __HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, 67); + 80009c8: 4b4f ldr r3, [pc, #316] @ (8000b08 ) + 80009ca: 681b ldr r3, [r3, #0] + 80009cc: 2243 movs r2, #67 @ 0x43 + 80009ce: 635a str r2, [r3, #52] @ 0x34 + switch (MODE){ + 80009d0: 4b4e ldr r3, [pc, #312] @ (8000b0c ) + 80009d2: 781b ldrb r3, [r3, #0] + 80009d4: b2db uxtb r3, r3 + 80009d6: 2b02 cmp r3, #2 + 80009d8: d006 beq.n 80009e8 + 80009da: 2b02 cmp r3, #2 + 80009dc: dc6e bgt.n 8000abc + 80009de: 2b00 cmp r3, #0 + 80009e0: d027 beq.n 8000a32 + 80009e2: 2b01 cmp r3, #1 + 80009e4: d05c beq.n 8000aa0 + encoderProcess(); + USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); + break; + + default: + break; + 80009e6: e069 b.n 8000abc + KEYSTATE_CHANGED_FLAG = 1; + 80009e8: 4b49 ldr r3, [pc, #292] @ (8000b10 ) + 80009ea: 2201 movs r2, #1 + 80009ec: 701a strb r2, [r3, #0] + resetReport(); + 80009ee: f000 fc1f bl 8001230 + matrixScan(); + 80009f2: f000 fb47 bl 8001084 + mergeChild(); + 80009f6: f000 f895 bl 8000b24 + encoderProcess(); + 80009fa: f000 fbbb bl 8001174 + if(KEYSTATE_CHANGED_FLAG == 1){ + 80009fe: 4b44 ldr r3, [pc, #272] @ (8000b10 ) + 8000a00: 781b ldrb r3, [r3, #0] + 8000a02: 2b01 cmp r3, #1 + 8000a04: d15c bne.n 8000ac0 + UARTREPORT.DEPTH = DEPTH; + 8000a06: 4b43 ldr r3, [pc, #268] @ (8000b14 ) + 8000a08: 881b ldrh r3, [r3, #0] + 8000a0a: 823b strh r3, [r7, #16] + UARTREPORT.TYPE = 0xEE; + 8000a0c: 23ee movs r3, #238 @ 0xee + 8000a0e: 827b strh r3, [r7, #18] + memcpy(UARTREPORT.KEYPRESS, REPORT.KEYPRESS, sizeof(UARTREPORT.KEYPRESS)); + 8000a10: 4a41 ldr r2, [pc, #260] @ (8000b18 ) + 8000a12: f107 0314 add.w r3, r7, #20 + 8000a16: 3202 adds r2, #2 + 8000a18: 6810 ldr r0, [r2, #0] + 8000a1a: 6851 ldr r1, [r2, #4] + 8000a1c: 6892 ldr r2, [r2, #8] + 8000a1e: c307 stmia r3!, {r0, r1, r2} + HAL_UART_Transmit_DMA(PARENT, (uint8_t*)&UARTREPORT, sizeof(UARTREPORT)); + 8000a20: 4b3e ldr r3, [pc, #248] @ (8000b1c ) + 8000a22: 681b ldr r3, [r3, #0] + 8000a24: f107 0110 add.w r1, r7, #16 + 8000a28: 2210 movs r2, #16 + 8000a2a: 4618 mov r0, r3 + 8000a2c: f005 fd6c bl 8006508 + break; + 8000a30: e046 b.n 8000ac0 + if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ + 8000a32: 4b3b ldr r3, [pc, #236] @ (8000b20 ) + 8000a34: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8000a38: b2db uxtb r3, r3 + 8000a3a: 2b03 cmp r3, #3 + 8000a3c: d106 bne.n 8000a4c + MODE = MODE_MAINBOARD; + 8000a3e: 4b33 ldr r3, [pc, #204] @ (8000b0c ) + 8000a40: 2201 movs r2, #1 + 8000a42: 701a strb r2, [r3, #0] + DEPTH = 0; + 8000a44: 4b33 ldr r3, [pc, #204] @ (8000b14 ) + 8000a46: 2200 movs r2, #0 + 8000a48: 801a strh r2, [r3, #0] + break; + 8000a4a: e03a b.n 8000ac2 + REQ.DEPTH = 0; + 8000a4c: 2300 movs r3, #0 + 8000a4e: 803b strh r3, [r7, #0] + REQ.TYPE = 0xFF; //Message code for request is 0xFF + 8000a50: 23ff movs r3, #255 @ 0xff + 8000a52: 807b strh r3, [r7, #2] + memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS)); + 8000a54: 463b mov r3, r7 + 8000a56: 3304 adds r3, #4 + 8000a58: 220c movs r2, #12 + 8000a5a: 2100 movs r1, #0 + 8000a5c: 4618 mov r0, r3 + 8000a5e: f00a fc77 bl 800b350 + HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ)); + 8000a62: 463b mov r3, r7 + 8000a64: 2210 movs r2, #16 + 8000a66: 4619 mov r1, r3 + 8000a68: 4819 ldr r0, [pc, #100] @ (8000ad0 ) + 8000a6a: f005 fd4d bl 8006508 + HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ)); + 8000a6e: 463b mov r3, r7 + 8000a70: 2210 movs r2, #16 + 8000a72: 4619 mov r1, r3 + 8000a74: 4818 ldr r0, [pc, #96] @ (8000ad8 ) + 8000a76: f005 fd47 bl 8006508 + HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); + 8000a7a: 463b mov r3, r7 + 8000a7c: 2210 movs r2, #16 + 8000a7e: 4619 mov r1, r3 + 8000a80: 4817 ldr r0, [pc, #92] @ (8000ae0 ) + 8000a82: f005 fd41 bl 8006508 + HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); + 8000a86: 463b mov r3, r7 + 8000a88: 2210 movs r2, #16 + 8000a8a: 4619 mov r1, r3 + 8000a8c: 4816 ldr r0, [pc, #88] @ (8000ae8 ) + 8000a8e: f005 fd3b bl 8006508 + HAL_Delay(500); + 8000a92: f44f 70fa mov.w r0, #500 @ 0x1f4 + 8000a96: f001 fa53 bl 8001f40 + findBestParent(); //So true... + 8000a9a: f000 f9db bl 8000e54 + break; + 8000a9e: e010 b.n 8000ac2 + resetReport(); + 8000aa0: f000 fbc6 bl 8001230 + matrixScan();//Something related to this making the key stick. Likely due to race conditions + 8000aa4: f000 faee bl 8001084 + mergeChild(); + 8000aa8: f000 f83c bl 8000b24 + encoderProcess(); + 8000aac: f000 fb62 bl 8001174 + USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); + 8000ab0: 220e movs r2, #14 + 8000ab2: 4919 ldr r1, [pc, #100] @ (8000b18 ) + 8000ab4: 481a ldr r0, [pc, #104] @ (8000b20 ) + 8000ab6: f008 fbd1 bl 800925c + break; + 8000aba: e002 b.n 8000ac2 + break; + 8000abc: bf00 nop + 8000abe: e000 b.n 8000ac2 + break; + 8000ac0: bf00 nop + } + + HAL_Delay(20); + 8000ac2: 2014 movs r0, #20 + 8000ac4: f001 fa3c bl 8001f40 + __HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, 67); + 8000ac8: e77e b.n 80009c8 + 8000aca: bf00 nop + 8000acc: 20000230 .word 0x20000230 + 8000ad0: 200009f0 .word 0x200009f0 + 8000ad4: 20000240 .word 0x20000240 + 8000ad8: 20000a38 .word 0x20000a38 + 8000adc: 20000250 .word 0x20000250 + 8000ae0: 20000960 .word 0x20000960 + 8000ae4: 20000220 .word 0x20000220 + 8000ae8: 200009a8 .word 0x200009a8 + 8000aec: 20000918 .word 0x20000918 + 8000af0: 2000028c .word 0x2000028c + 8000af4: 2000026c .word 0x2000026c + 8000af8: 200002c0 .word 0x200002c0 + 8000afc: 20000444 .word 0x20000444 + 8000b00: 200005c8 .word 0x200005c8 + 8000b04: 2000074c .word 0x2000074c + 8000b08: 200008d0 .word 0x200008d0 + 8000b0c: 2000028a .word 0x2000028a + 8000b10: 20000268 .word 0x20000268 + 8000b14: 20000260 .word 0x20000260 + 8000b18: 20000210 .word 0x20000210 + 8000b1c: 20000264 .word 0x20000264 + 8000b20: 20000d88 .word 0x20000d88 + +08000b24 : + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +void mergeChild(){ + 8000b24: b590 push {r4, r7, lr} + 8000b26: b087 sub sp, #28 + 8000b28: af00 add r7, sp, #0 + uint8_t packet[12]; + if (pq_pop(&huart1q, packet)) { + 8000b2a: 1d3b adds r3, r7, #4 + 8000b2c: 4619 mov r1, r3 + 8000b2e: 4838 ldr r0, [pc, #224] @ (8000c10 ) + 8000b30: f7ff fec4 bl 80008bc + 8000b34: 4603 mov r3, r0 + 8000b36: 2b00 cmp r3, #0 + 8000b38: d008 beq.n 8000b4c + memcpy(UART_KEYSTATE[1], packet, 12); + 8000b3a: 4b36 ldr r3, [pc, #216] @ (8000c14 ) + 8000b3c: 330c adds r3, #12 + 8000b3e: 1d3a adds r2, r7, #4 + 8000b40: ca07 ldmia r2, {r0, r1, r2} + 8000b42: e883 0007 stmia.w r3, {r0, r1, r2} + KEYSTATE_CHANGED_FLAG = 1; + 8000b46: 4b34 ldr r3, [pc, #208] @ (8000c18 ) + 8000b48: 2201 movs r2, #1 + 8000b4a: 701a strb r2, [r3, #0] + } + if (pq_pop(&huart2q, packet)) { + 8000b4c: 1d3b adds r3, r7, #4 + 8000b4e: 4619 mov r1, r3 + 8000b50: 4832 ldr r0, [pc, #200] @ (8000c1c ) + 8000b52: f7ff feb3 bl 80008bc + 8000b56: 4603 mov r3, r0 + 8000b58: 2b00 cmp r3, #0 + 8000b5a: d008 beq.n 8000b6e + memcpy(UART_KEYSTATE[2], packet, 12); + 8000b5c: 4b2d ldr r3, [pc, #180] @ (8000c14 ) + 8000b5e: 3318 adds r3, #24 + 8000b60: 1d3a adds r2, r7, #4 + 8000b62: ca07 ldmia r2, {r0, r1, r2} + 8000b64: e883 0007 stmia.w r3, {r0, r1, r2} + KEYSTATE_CHANGED_FLAG = 1; + 8000b68: 4b2b ldr r3, [pc, #172] @ (8000c18 ) + 8000b6a: 2201 movs r2, #1 + 8000b6c: 701a strb r2, [r3, #0] + } + if (pq_pop(&huart4q, packet)) { + 8000b6e: 1d3b adds r3, r7, #4 + 8000b70: 4619 mov r1, r3 + 8000b72: 482b ldr r0, [pc, #172] @ (8000c20 ) + 8000b74: f7ff fea2 bl 80008bc + 8000b78: 4603 mov r3, r0 + 8000b7a: 2b00 cmp r3, #0 + 8000b7c: d008 beq.n 8000b90 + memcpy(UART_KEYSTATE[3], packet, 12); + 8000b7e: 4b25 ldr r3, [pc, #148] @ (8000c14 ) + 8000b80: 3324 adds r3, #36 @ 0x24 + 8000b82: 1d3a adds r2, r7, #4 + 8000b84: ca07 ldmia r2, {r0, r1, r2} + 8000b86: e883 0007 stmia.w r3, {r0, r1, r2} + KEYSTATE_CHANGED_FLAG = 1; + 8000b8a: 4b23 ldr r3, [pc, #140] @ (8000c18 ) + 8000b8c: 2201 movs r2, #1 + 8000b8e: 701a strb r2, [r3, #0] + } + if (pq_pop(&huart5q, packet)) { + 8000b90: 1d3b adds r3, r7, #4 + 8000b92: 4619 mov r1, r3 + 8000b94: 4823 ldr r0, [pc, #140] @ (8000c24 ) + 8000b96: f7ff fe91 bl 80008bc + 8000b9a: 4603 mov r3, r0 + 8000b9c: 2b00 cmp r3, #0 + 8000b9e: d009 beq.n 8000bb4 + memcpy(UART_KEYSTATE[0], packet, 12); + 8000ba0: 4b1c ldr r3, [pc, #112] @ (8000c14 ) + 8000ba2: 461c mov r4, r3 + 8000ba4: 1d3b adds r3, r7, #4 + 8000ba6: e893 0007 ldmia.w r3, {r0, r1, r2} + 8000baa: e884 0007 stmia.w r4, {r0, r1, r2} + KEYSTATE_CHANGED_FLAG = 1; + 8000bae: 4b1a ldr r3, [pc, #104] @ (8000c18 ) + 8000bb0: 2201 movs r2, #1 + 8000bb2: 701a strb r2, [r3, #0] + } + for(int i = 0; i < 4; i++){ + 8000bb4: 2300 movs r3, #0 + 8000bb6: 617b str r3, [r7, #20] + 8000bb8: e022 b.n 8000c00 + for(int j = 0; j < 12; j++){ + 8000bba: 2300 movs r3, #0 + 8000bbc: 613b str r3, [r7, #16] + 8000bbe: e019 b.n 8000bf4 + REPORT.KEYPRESS[j] |= UART_KEYSTATE[i][j]; + 8000bc0: 4a19 ldr r2, [pc, #100] @ (8000c28 ) + 8000bc2: 693b ldr r3, [r7, #16] + 8000bc4: 4413 add r3, r2 + 8000bc6: 3302 adds r3, #2 + 8000bc8: 7819 ldrb r1, [r3, #0] + 8000bca: 4812 ldr r0, [pc, #72] @ (8000c14 ) + 8000bcc: 697a ldr r2, [r7, #20] + 8000bce: 4613 mov r3, r2 + 8000bd0: 005b lsls r3, r3, #1 + 8000bd2: 4413 add r3, r2 + 8000bd4: 009b lsls r3, r3, #2 + 8000bd6: 18c2 adds r2, r0, r3 + 8000bd8: 693b ldr r3, [r7, #16] + 8000bda: 4413 add r3, r2 + 8000bdc: 781b ldrb r3, [r3, #0] + 8000bde: 430b orrs r3, r1 + 8000be0: b2d9 uxtb r1, r3 + 8000be2: 4a11 ldr r2, [pc, #68] @ (8000c28 ) + 8000be4: 693b ldr r3, [r7, #16] + 8000be6: 4413 add r3, r2 + 8000be8: 3302 adds r3, #2 + 8000bea: 460a mov r2, r1 + 8000bec: 701a strb r2, [r3, #0] + for(int j = 0; j < 12; j++){ + 8000bee: 693b ldr r3, [r7, #16] + 8000bf0: 3301 adds r3, #1 + 8000bf2: 613b str r3, [r7, #16] + 8000bf4: 693b ldr r3, [r7, #16] + 8000bf6: 2b0b cmp r3, #11 + 8000bf8: dde2 ble.n 8000bc0 + for(int i = 0; i < 4; i++){ + 8000bfa: 697b ldr r3, [r7, #20] + 8000bfc: 3301 adds r3, #1 + 8000bfe: 617b str r3, [r7, #20] + 8000c00: 697b ldr r3, [r7, #20] + 8000c02: 2b03 cmp r3, #3 + 8000c04: ddd9 ble.n 8000bba + } + } +} + 8000c06: bf00 nop + 8000c08: bf00 nop + 8000c0a: 371c adds r7, #28 + 8000c0c: 46bd mov sp, r7 + 8000c0e: bd90 pop {r4, r7, pc} + 8000c10: 200002c0 .word 0x200002c0 + 8000c14: 20000290 .word 0x20000290 + 8000c18: 20000268 .word 0x20000268 + 8000c1c: 20000444 .word 0x20000444 + 8000c20: 200005c8 .word 0x200005c8 + 8000c24: 2000074c .word 0x2000074c + 8000c28: 20000210 .word 0x20000210 + +08000c2c : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000c2c: b580 push {r7, lr} + 8000c2e: b094 sub sp, #80 @ 0x50 + 8000c30: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000c32: f107 031c add.w r3, r7, #28 + 8000c36: 2234 movs r2, #52 @ 0x34 + 8000c38: 2100 movs r1, #0 + 8000c3a: 4618 mov r0, r3 + 8000c3c: f00a fb88 bl 800b350 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000c40: f107 0308 add.w r3, r7, #8 + 8000c44: 2200 movs r2, #0 + 8000c46: 601a str r2, [r3, #0] + 8000c48: 605a str r2, [r3, #4] + 8000c4a: 609a str r2, [r3, #8] + 8000c4c: 60da str r2, [r3, #12] + 8000c4e: 611a str r2, [r3, #16] + + /** Configure the main internal regulator out put voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + 8000c50: 2300 movs r3, #0 + 8000c52: 607b str r3, [r7, #4] + 8000c54: 4b29 ldr r3, [pc, #164] @ (8000cfc ) + 8000c56: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000c58: 4a28 ldr r2, [pc, #160] @ (8000cfc ) + 8000c5a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000c5e: 6413 str r3, [r2, #64] @ 0x40 + 8000c60: 4b26 ldr r3, [pc, #152] @ (8000cfc ) + 8000c62: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000c64: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8000c68: 607b str r3, [r7, #4] + 8000c6a: 687b ldr r3, [r7, #4] + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + 8000c6c: 2300 movs r3, #0 + 8000c6e: 603b str r3, [r7, #0] + 8000c70: 4b23 ldr r3, [pc, #140] @ (8000d00 ) + 8000c72: 681b ldr r3, [r3, #0] + 8000c74: f423 4340 bic.w r3, r3, #49152 @ 0xc000 + 8000c78: 4a21 ldr r2, [pc, #132] @ (8000d00 ) + 8000c7a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 8000c7e: 6013 str r3, [r2, #0] + 8000c80: 4b1f ldr r3, [pc, #124] @ (8000d00 ) + 8000c82: 681b ldr r3, [r3, #0] + 8000c84: f403 4340 and.w r3, r3, #49152 @ 0xc000 + 8000c88: 603b str r3, [r7, #0] + 8000c8a: 683b ldr r3, [r7, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + 8000c8c: 2301 movs r3, #1 + 8000c8e: 61fb str r3, [r7, #28] + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 8000c90: f44f 3380 mov.w r3, #65536 @ 0x10000 + 8000c94: 623b str r3, [r7, #32] + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 8000c96: 2302 movs r3, #2 + 8000c98: 637b str r3, [r7, #52] @ 0x34 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 8000c9a: f44f 0380 mov.w r3, #4194304 @ 0x400000 + 8000c9e: 63bb str r3, [r7, #56] @ 0x38 + RCC_OscInitStruct.PLL.PLLM = 4; + 8000ca0: 2304 movs r3, #4 + 8000ca2: 63fb str r3, [r7, #60] @ 0x3c + RCC_OscInitStruct.PLL.PLLN = 96; + 8000ca4: 2360 movs r3, #96 @ 0x60 + 8000ca6: 643b str r3, [r7, #64] @ 0x40 + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + 8000ca8: 2302 movs r3, #2 + 8000caa: 647b str r3, [r7, #68] @ 0x44 + RCC_OscInitStruct.PLL.PLLQ = 4; + 8000cac: 2304 movs r3, #4 + 8000cae: 64bb str r3, [r7, #72] @ 0x48 + RCC_OscInitStruct.PLL.PLLR = 2; + 8000cb0: 2302 movs r3, #2 + 8000cb2: 64fb str r3, [r7, #76] @ 0x4c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000cb4: f107 031c add.w r3, r7, #28 + 8000cb8: 4618 mov r0, r3 + 8000cba: f004 fa7d bl 80051b8 + 8000cbe: 4603 mov r3, r0 + 8000cc0: 2b00 cmp r3, #0 + 8000cc2: d001 beq.n 8000cc8 + { + Error_Handler(); + 8000cc4: f000 fac0 bl 8001248 + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8000cc8: 230f movs r3, #15 + 8000cca: 60bb str r3, [r7, #8] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 8000ccc: 2302 movs r3, #2 + 8000cce: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; + 8000cd0: 2380 movs r3, #128 @ 0x80 + 8000cd2: 613b str r3, [r7, #16] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + 8000cd4: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8000cd8: 617b str r3, [r7, #20] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000cda: 2300 movs r3, #0 + 8000cdc: 61bb str r3, [r7, #24] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + 8000cde: f107 0308 add.w r3, r7, #8 + 8000ce2: 2101 movs r1, #1 + 8000ce4: 4618 mov r0, r3 + 8000ce6: f003 fbf3 bl 80044d0 + 8000cea: 4603 mov r3, r0 + 8000cec: 2b00 cmp r3, #0 + 8000cee: d001 beq.n 8000cf4 + { + Error_Handler(); + 8000cf0: f000 faaa bl 8001248 + } +} + 8000cf4: bf00 nop + 8000cf6: 3750 adds r7, #80 @ 0x50 + 8000cf8: 46bd mov sp, r7 + 8000cfa: bd80 pop {r7, pc} + 8000cfc: 40023800 .word 0x40023800 + 8000d00: 40007000 .word 0x40007000 + +08000d04 : + +/* USER CODE BEGIN 4 */ +// UART Message Requests Goes Here +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { + 8000d04: b580 push {r7, lr} + 8000d06: b082 sub sp, #8 + 8000d08: af00 add r7, sp, #0 + 8000d0a: 6078 str r0, [r7, #4] + if (huart->Instance == USART1) { + 8000d0c: 687b ldr r3, [r7, #4] + 8000d0e: 681b ldr r3, [r3, #0] + 8000d10: 4a1e ldr r2, [pc, #120] @ (8000d8c ) + 8000d12: 4293 cmp r3, r2 + 8000d14: d109 bne.n 8000d2a + handleUARTMessages((uint8_t*)&RX1Msg, &huart1); + 8000d16: 491e ldr r1, [pc, #120] @ (8000d90 ) + 8000d18: 481e ldr r0, [pc, #120] @ (8000d94 ) + 8000d1a: f000 f8dd bl 8000ed8 + HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); + 8000d1e: 2210 movs r2, #16 + 8000d20: 491c ldr r1, [pc, #112] @ (8000d94 ) + 8000d22: 481b ldr r0, [pc, #108] @ (8000d90 ) + 8000d24: f005 fc6c bl 8006600 + } + else if (huart->Instance == UART5) { + handleUARTMessages((uint8_t*)&RX5Msg, &huart5); + HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); + } +} + 8000d28: e02b b.n 8000d82 + else if (huart->Instance == USART2) { + 8000d2a: 687b ldr r3, [r7, #4] + 8000d2c: 681b ldr r3, [r3, #0] + 8000d2e: 4a1a ldr r2, [pc, #104] @ (8000d98 ) + 8000d30: 4293 cmp r3, r2 + 8000d32: d109 bne.n 8000d48 + handleUARTMessages((uint8_t*)&RX2Msg, &huart2); + 8000d34: 4919 ldr r1, [pc, #100] @ (8000d9c ) + 8000d36: 481a ldr r0, [pc, #104] @ (8000da0 ) + 8000d38: f000 f8ce bl 8000ed8 + HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); + 8000d3c: 2210 movs r2, #16 + 8000d3e: 4918 ldr r1, [pc, #96] @ (8000da0 ) + 8000d40: 4816 ldr r0, [pc, #88] @ (8000d9c ) + 8000d42: f005 fc5d bl 8006600 +} + 8000d46: e01c b.n 8000d82 + else if (huart->Instance == UART4) { + 8000d48: 687b ldr r3, [r7, #4] + 8000d4a: 681b ldr r3, [r3, #0] + 8000d4c: 4a15 ldr r2, [pc, #84] @ (8000da4 ) + 8000d4e: 4293 cmp r3, r2 + 8000d50: d109 bne.n 8000d66 + handleUARTMessages((uint8_t*)&RX4Msg, &huart4); + 8000d52: 4915 ldr r1, [pc, #84] @ (8000da8 ) + 8000d54: 4815 ldr r0, [pc, #84] @ (8000dac ) + 8000d56: f000 f8bf bl 8000ed8 + HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); + 8000d5a: 2210 movs r2, #16 + 8000d5c: 4913 ldr r1, [pc, #76] @ (8000dac ) + 8000d5e: 4812 ldr r0, [pc, #72] @ (8000da8 ) + 8000d60: f005 fc4e bl 8006600 +} + 8000d64: e00d b.n 8000d82 + else if (huart->Instance == UART5) { + 8000d66: 687b ldr r3, [r7, #4] + 8000d68: 681b ldr r3, [r3, #0] + 8000d6a: 4a11 ldr r2, [pc, #68] @ (8000db0 ) + 8000d6c: 4293 cmp r3, r2 + 8000d6e: d108 bne.n 8000d82 + handleUARTMessages((uint8_t*)&RX5Msg, &huart5); + 8000d70: 4910 ldr r1, [pc, #64] @ (8000db4 ) + 8000d72: 4811 ldr r0, [pc, #68] @ (8000db8 ) + 8000d74: f000 f8b0 bl 8000ed8 + HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); + 8000d78: 2210 movs r2, #16 + 8000d7a: 490f ldr r1, [pc, #60] @ (8000db8 ) + 8000d7c: 480d ldr r0, [pc, #52] @ (8000db4 ) + 8000d7e: f005 fc3f bl 8006600 +} + 8000d82: bf00 nop + 8000d84: 3708 adds r7, #8 + 8000d86: 46bd mov sp, r7 + 8000d88: bd80 pop {r7, pc} + 8000d8a: bf00 nop + 8000d8c: 40011000 .word 0x40011000 + 8000d90: 200009f0 .word 0x200009f0 + 8000d94: 20000230 .word 0x20000230 + 8000d98: 40004400 .word 0x40004400 + 8000d9c: 20000a38 .word 0x20000a38 + 8000da0: 20000240 .word 0x20000240 + 8000da4: 40004c00 .word 0x40004c00 + 8000da8: 20000960 .word 0x20000960 + 8000dac: 20000250 .word 0x20000250 + 8000db0: 40005000 .word 0x40005000 + 8000db4: 200009a8 .word 0x200009a8 + 8000db8: 20000220 .word 0x20000220 + +08000dbc : + +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { + 8000dbc: b580 push {r7, lr} + 8000dbe: b082 sub sp, #8 + 8000dc0: af00 add r7, sp, #0 + 8000dc2: 6078 str r0, [r7, #4] + // Restart DMA on error + if (huart->Instance == USART1) { + 8000dc4: 687b ldr r3, [r7, #4] + 8000dc6: 681b ldr r3, [r3, #0] + 8000dc8: 4a16 ldr r2, [pc, #88] @ (8000e24 ) + 8000dca: 4293 cmp r3, r2 + 8000dcc: d105 bne.n 8000dda + HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); + 8000dce: 2210 movs r2, #16 + 8000dd0: 4915 ldr r1, [pc, #84] @ (8000e28 ) + 8000dd2: 4816 ldr r0, [pc, #88] @ (8000e2c ) + 8000dd4: f005 fc14 bl 8006600 + HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); + } + else if (huart->Instance == UART5) { + HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); + } +} + 8000dd8: e01f b.n 8000e1a + else if (huart->Instance == USART2) { + 8000dda: 687b ldr r3, [r7, #4] + 8000ddc: 681b ldr r3, [r3, #0] + 8000dde: 4a14 ldr r2, [pc, #80] @ (8000e30 ) + 8000de0: 4293 cmp r3, r2 + 8000de2: d105 bne.n 8000df0 + HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); + 8000de4: 2210 movs r2, #16 + 8000de6: 4913 ldr r1, [pc, #76] @ (8000e34 ) + 8000de8: 4813 ldr r0, [pc, #76] @ (8000e38 ) + 8000dea: f005 fc09 bl 8006600 +} + 8000dee: e014 b.n 8000e1a + else if (huart->Instance == UART4) { + 8000df0: 687b ldr r3, [r7, #4] + 8000df2: 681b ldr r3, [r3, #0] + 8000df4: 4a11 ldr r2, [pc, #68] @ (8000e3c ) + 8000df6: 4293 cmp r3, r2 + 8000df8: d105 bne.n 8000e06 + HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); + 8000dfa: 2210 movs r2, #16 + 8000dfc: 4910 ldr r1, [pc, #64] @ (8000e40 ) + 8000dfe: 4811 ldr r0, [pc, #68] @ (8000e44 ) + 8000e00: f005 fbfe bl 8006600 +} + 8000e04: e009 b.n 8000e1a + else if (huart->Instance == UART5) { + 8000e06: 687b ldr r3, [r7, #4] + 8000e08: 681b ldr r3, [r3, #0] + 8000e0a: 4a0f ldr r2, [pc, #60] @ (8000e48 ) + 8000e0c: 4293 cmp r3, r2 + 8000e0e: d104 bne.n 8000e1a + HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); + 8000e10: 2210 movs r2, #16 + 8000e12: 490e ldr r1, [pc, #56] @ (8000e4c ) + 8000e14: 480e ldr r0, [pc, #56] @ (8000e50 ) + 8000e16: f005 fbf3 bl 8006600 +} + 8000e1a: bf00 nop + 8000e1c: 3708 adds r7, #8 + 8000e1e: 46bd mov sp, r7 + 8000e20: bd80 pop {r7, pc} + 8000e22: bf00 nop + 8000e24: 40011000 .word 0x40011000 + 8000e28: 20000230 .word 0x20000230 + 8000e2c: 200009f0 .word 0x200009f0 + 8000e30: 40004400 .word 0x40004400 + 8000e34: 20000240 .word 0x20000240 + 8000e38: 20000a38 .word 0x20000a38 + 8000e3c: 40004c00 .word 0x40004c00 + 8000e40: 20000250 .word 0x20000250 + 8000e44: 20000960 .word 0x20000960 + 8000e48: 40005000 .word 0x40005000 + 8000e4c: 20000220 .word 0x20000220 + 8000e50: 200009a8 .word 0x200009a8 + +08000e54 : + + + +void findBestParent(){ + 8000e54: b580 push {r7, lr} + 8000e56: b084 sub sp, #16 + 8000e58: af00 add r7, sp, #0 + //Find least depth parent + uint16_t least_val = 0xFF; + 8000e5a: 23ff movs r3, #255 @ 0xff + 8000e5c: 81fb strh r3, [r7, #14] + UART_HandleTypeDef* least_port = NULL; + 8000e5e: 2300 movs r3, #0 + 8000e60: 60bb str r3, [r7, #8] + for(uint8_t i = 0; i < 4; i++){ + 8000e62: 2300 movs r3, #0 + 8000e64: 71fb strb r3, [r7, #7] + 8000e66: e013 b.n 8000e90 + if(PORT_DEPTH[i]) + 8000e6c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8000e70: 89fa ldrh r2, [r7, #14] + 8000e72: 429a cmp r2, r3 + 8000e74: d909 bls.n 8000e8a + least_port = PORTS[i]; + 8000e76: 79fb ldrb r3, [r7, #7] + 8000e78: 4a13 ldr r2, [pc, #76] @ (8000ec8 ) + 8000e7a: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8000e7e: 60bb str r3, [r7, #8] + least_val = PORT_DEPTH[i]; + 8000e80: 79fb ldrb r3, [r7, #7] + 8000e82: 4a10 ldr r2, [pc, #64] @ (8000ec4 ) + 8000e84: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8000e88: 81fb strh r3, [r7, #14] + for(uint8_t i = 0; i < 4; i++){ + 8000e8a: 79fb ldrb r3, [r7, #7] + 8000e8c: 3301 adds r3, #1 + 8000e8e: 71fb strb r3, [r7, #7] + 8000e90: 79fb ldrb r3, [r7, #7] + 8000e92: 2b03 cmp r3, #3 + 8000e94: d9e8 bls.n 8000e68 + } + } + + //Assign if valid + if(least_val < 0xFF){ + 8000e96: 89fb ldrh r3, [r7, #14] + 8000e98: 2bfe cmp r3, #254 @ 0xfe + 8000e9a: d80e bhi.n 8000eba + PARENT = least_port; + 8000e9c: 4a0b ldr r2, [pc, #44] @ (8000ecc ) + 8000e9e: 68bb ldr r3, [r7, #8] + 8000ea0: 6013 str r3, [r2, #0] + DEPTH = least_val + 1; + 8000ea2: 89fb ldrh r3, [r7, #14] + 8000ea4: 3301 adds r3, #1 + 8000ea6: b29a uxth r2, r3 + 8000ea8: 4b09 ldr r3, [pc, #36] @ (8000ed0 ) + 8000eaa: 801a strh r2, [r3, #0] + MODE = MODE_ACTIVE; + 8000eac: 4b09 ldr r3, [pc, #36] @ (8000ed4 ) + 8000eae: 2202 movs r2, #2 + 8000eb0: 701a strb r2, [r3, #0] + HAL_Delay(500); + 8000eb2: f44f 70fa mov.w r0, #500 @ 0x1f4 + 8000eb6: f001 f843 bl 8001f40 + } +} + 8000eba: bf00 nop + 8000ebc: 3710 adds r7, #16 + 8000ebe: 46bd mov sp, r7 + 8000ec0: bd80 pop {r7, pc} + 8000ec2: bf00 nop + 8000ec4: 20000078 .word 0x20000078 + 8000ec8: 20000080 .word 0x20000080 + 8000ecc: 20000264 .word 0x20000264 + 8000ed0: 20000260 .word 0x20000260 + 8000ed4: 2000028a .word 0x2000028a + +08000ed8 : + +// Called when UART RX interrupt completes +void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender) { + 8000ed8: b590 push {r4, r7, lr} + 8000eda: b08b sub sp, #44 @ 0x2c + 8000edc: af00 add r7, sp, #0 + 8000ede: 6078 str r0, [r7, #4] + 8000ee0: 6039 str r1, [r7, #0] + UARTMessage msg; + UARTMessage reply; + + // Parse incoming message into struct + memcpy(&msg, data, sizeof(UARTMessage)); + 8000ee2: 687b ldr r3, [r7, #4] + 8000ee4: f107 0418 add.w r4, r7, #24 + 8000ee8: 6818 ldr r0, [r3, #0] + 8000eea: 6859 ldr r1, [r3, #4] + 8000eec: 689a ldr r2, [r3, #8] + 8000eee: 68db ldr r3, [r3, #12] + 8000ef0: c40f stmia r4!, {r0, r1, r2, r3} + + switch(msg.TYPE) { + 8000ef2: 8b7b ldrh r3, [r7, #26] + 8000ef4: 2bff cmp r3, #255 @ 0xff + 8000ef6: d026 beq.n 8000f46 + 8000ef8: 2bff cmp r3, #255 @ 0xff + 8000efa: dc6e bgt.n 8000fda + 8000efc: 2baa cmp r3, #170 @ 0xaa + 8000efe: d002 beq.n 8000f06 + 8000f00: 2bee cmp r3, #238 @ 0xee + 8000f02: d03a beq.n 8000f7a + } + + break; + + default: + break; + 8000f04: e069 b.n 8000fda + if(sender == &huart5) { + 8000f06: 683b ldr r3, [r7, #0] + 8000f08: 4a39 ldr r2, [pc, #228] @ (8000ff0 ) + 8000f0a: 4293 cmp r3, r2 + 8000f0c: d103 bne.n 8000f16 + PORT_DEPTH[0] = msg.DEPTH; + 8000f0e: 8b3a ldrh r2, [r7, #24] + 8000f10: 4b38 ldr r3, [pc, #224] @ (8000ff4 ) + 8000f12: 801a strh r2, [r3, #0] + break; + 8000f14: e063 b.n 8000fde + } else if(sender == &huart1) { + 8000f16: 683b ldr r3, [r7, #0] + 8000f18: 4a37 ldr r2, [pc, #220] @ (8000ff8 ) + 8000f1a: 4293 cmp r3, r2 + 8000f1c: d103 bne.n 8000f26 + PORT_DEPTH[1] = msg.DEPTH; + 8000f1e: 8b3a ldrh r2, [r7, #24] + 8000f20: 4b34 ldr r3, [pc, #208] @ (8000ff4 ) + 8000f22: 805a strh r2, [r3, #2] + break; + 8000f24: e05b b.n 8000fde + } else if(sender == &huart2) { + 8000f26: 683b ldr r3, [r7, #0] + 8000f28: 4a34 ldr r2, [pc, #208] @ (8000ffc ) + 8000f2a: 4293 cmp r3, r2 + 8000f2c: d103 bne.n 8000f36 + PORT_DEPTH[2] = msg.DEPTH; + 8000f2e: 8b3a ldrh r2, [r7, #24] + 8000f30: 4b30 ldr r3, [pc, #192] @ (8000ff4 ) + 8000f32: 809a strh r2, [r3, #4] + break; + 8000f34: e053 b.n 8000fde + } else if(sender == &huart4) { + 8000f36: 683b ldr r3, [r7, #0] + 8000f38: 4a31 ldr r2, [pc, #196] @ (8001000 ) + 8000f3a: 4293 cmp r3, r2 + 8000f3c: d14f bne.n 8000fde + PORT_DEPTH[3] = msg.DEPTH; + 8000f3e: 8b3a ldrh r2, [r7, #24] + 8000f40: 4b2c ldr r3, [pc, #176] @ (8000ff4 ) + 8000f42: 80da strh r2, [r3, #6] + break; + 8000f44: e04b b.n 8000fde + if(MODE!=MODE_INACTIVE){ + 8000f46: 4b2f ldr r3, [pc, #188] @ (8001004 ) + 8000f48: 781b ldrb r3, [r3, #0] + 8000f4a: b2db uxtb r3, r3 + 8000f4c: 2b00 cmp r3, #0 + 8000f4e: d048 beq.n 8000fe2 + reply.TYPE = 0xAA; + 8000f50: 23aa movs r3, #170 @ 0xaa + 8000f52: 817b strh r3, [r7, #10] + reply.DEPTH = DEPTH; // use your local DEPTH + 8000f54: 4b2c ldr r3, [pc, #176] @ (8001008 ) + 8000f56: 881b ldrh r3, [r3, #0] + 8000f58: 813b strh r3, [r7, #8] + memset(reply.KEYPRESS, 0, sizeof(reply.KEYPRESS)); + 8000f5a: f107 0308 add.w r3, r7, #8 + 8000f5e: 3304 adds r3, #4 + 8000f60: 220c movs r2, #12 + 8000f62: 2100 movs r1, #0 + 8000f64: 4618 mov r0, r3 + 8000f66: f00a f9f3 bl 800b350 + HAL_UART_Transmit_DMA(sender, (uint8_t*)&reply, sizeof(reply)); + 8000f6a: f107 0308 add.w r3, r7, #8 + 8000f6e: 2210 movs r2, #16 + 8000f70: 4619 mov r1, r3 + 8000f72: 6838 ldr r0, [r7, #0] + 8000f74: f005 fac8 bl 8006508 + break; + 8000f78: e033 b.n 8000fe2 + if(sender == &huart5) { + 8000f7a: 683b ldr r3, [r7, #0] + 8000f7c: 4a1c ldr r2, [pc, #112] @ (8000ff0 ) + 8000f7e: 4293 cmp r3, r2 + 8000f80: d107 bne.n 8000f92 + pq_push(&huart5q, msg.KEYPRESS); + 8000f82: f107 0318 add.w r3, r7, #24 + 8000f86: 3304 adds r3, #4 + 8000f88: 4619 mov r1, r3 + 8000f8a: 4820 ldr r0, [pc, #128] @ (800100c ) + 8000f8c: f7ff fc62 bl 8000854 + break; + 8000f90: e029 b.n 8000fe6 + } else if(sender == &huart1) { + 8000f92: 683b ldr r3, [r7, #0] + 8000f94: 4a18 ldr r2, [pc, #96] @ (8000ff8 ) + 8000f96: 4293 cmp r3, r2 + 8000f98: d107 bne.n 8000faa + pq_push(&huart1q, msg.KEYPRESS); + 8000f9a: f107 0318 add.w r3, r7, #24 + 8000f9e: 3304 adds r3, #4 + 8000fa0: 4619 mov r1, r3 + 8000fa2: 481b ldr r0, [pc, #108] @ (8001010 ) + 8000fa4: f7ff fc56 bl 8000854 + break; + 8000fa8: e01d b.n 8000fe6 + } else if(sender == &huart2) { + 8000faa: 683b ldr r3, [r7, #0] + 8000fac: 4a13 ldr r2, [pc, #76] @ (8000ffc ) + 8000fae: 4293 cmp r3, r2 + 8000fb0: d107 bne.n 8000fc2 + pq_push(&huart2q, msg.KEYPRESS); + 8000fb2: f107 0318 add.w r3, r7, #24 + 8000fb6: 3304 adds r3, #4 + 8000fb8: 4619 mov r1, r3 + 8000fba: 4816 ldr r0, [pc, #88] @ (8001014 ) + 8000fbc: f7ff fc4a bl 8000854 + break; + 8000fc0: e011 b.n 8000fe6 + } else if(sender == &huart4) { + 8000fc2: 683b ldr r3, [r7, #0] + 8000fc4: 4a0e ldr r2, [pc, #56] @ (8001000 ) + 8000fc6: 4293 cmp r3, r2 + 8000fc8: d10d bne.n 8000fe6 + pq_push(&huart4q, msg.KEYPRESS); + 8000fca: f107 0318 add.w r3, r7, #24 + 8000fce: 3304 adds r3, #4 + 8000fd0: 4619 mov r1, r3 + 8000fd2: 4811 ldr r0, [pc, #68] @ (8001018 ) + 8000fd4: f7ff fc3e bl 8000854 + break; + 8000fd8: e005 b.n 8000fe6 + break; + 8000fda: bf00 nop + 8000fdc: e004 b.n 8000fe8 + break; + 8000fde: bf00 nop + 8000fe0: e002 b.n 8000fe8 + break; + 8000fe2: bf00 nop + 8000fe4: e000 b.n 8000fe8 + break; + 8000fe6: bf00 nop + + } +} + 8000fe8: bf00 nop + 8000fea: 372c adds r7, #44 @ 0x2c + 8000fec: 46bd mov sp, r7 + 8000fee: bd90 pop {r4, r7, pc} + 8000ff0: 200009a8 .word 0x200009a8 + 8000ff4: 20000078 .word 0x20000078 + 8000ff8: 200009f0 .word 0x200009f0 + 8000ffc: 20000a38 .word 0x20000a38 + 8001000: 20000960 .word 0x20000960 + 8001004: 2000028a .word 0x2000028a + 8001008: 20000260 .word 0x20000260 + 800100c: 2000074c .word 0x2000074c + 8001010: 200002c0 .word 0x200002c0 + 8001014: 20000444 .word 0x20000444 + 8001018: 200005c8 .word 0x200005c8 + +0800101c : + + +void addUSBReport(uint8_t usageID){ + 800101c: b480 push {r7} + 800101e: b085 sub sp, #20 + 8001020: af00 add r7, sp, #0 + 8001022: 4603 mov r3, r0 + 8001024: 71fb strb r3, [r7, #7] + if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds + 8001026: 79fb ldrb r3, [r7, #7] + 8001028: 2b03 cmp r3, #3 + 800102a: d922 bls.n 8001072 + 800102c: 79fb ldrb r3, [r7, #7] + 800102e: 2b73 cmp r3, #115 @ 0x73 + 8001030: d81f bhi.n 8001072 + uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit + 8001032: 79fb ldrb r3, [r7, #7] + 8001034: b29b uxth r3, r3 + 8001036: 3b04 subs r3, #4 + 8001038: 81fb strh r3, [r7, #14] + uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array + 800103a: 89fb ldrh r3, [r7, #14] + 800103c: 08db lsrs r3, r3, #3 + 800103e: b29b uxth r3, r3 + 8001040: 737b strb r3, [r7, #13] + uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset + 8001042: 89fb ldrh r3, [r7, #14] + 8001044: b2db uxtb r3, r3 + 8001046: f003 0307 and.w r3, r3, #7 + 800104a: 733b strb r3, [r7, #12] + REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); + 800104c: 7b7b ldrb r3, [r7, #13] + 800104e: 4a0c ldr r2, [pc, #48] @ (8001080 ) + 8001050: 4413 add r3, r2 + 8001052: 789b ldrb r3, [r3, #2] + 8001054: b25a sxtb r2, r3 + 8001056: 7b3b ldrb r3, [r7, #12] + 8001058: 2101 movs r1, #1 + 800105a: fa01 f303 lsl.w r3, r1, r3 + 800105e: b25b sxtb r3, r3 + 8001060: 4313 orrs r3, r2 + 8001062: b25a sxtb r2, r3 + 8001064: 7b7b ldrb r3, [r7, #13] + 8001066: b2d1 uxtb r1, r2 + 8001068: 4a05 ldr r2, [pc, #20] @ (8001080 ) + 800106a: 4413 add r3, r2 + 800106c: 460a mov r2, r1 + 800106e: 709a strb r2, [r3, #2] + 8001070: e000 b.n 8001074 + if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds + 8001072: bf00 nop +} + 8001074: 3714 adds r7, #20 + 8001076: 46bd mov sp, r7 + 8001078: f85d 7b04 ldr.w r7, [sp], #4 + 800107c: 4770 bx lr + 800107e: bf00 nop + 8001080: 20000210 .word 0x20000210 + +08001084 : + +void matrixScan(void){ + 8001084: b580 push {r7, lr} + 8001086: b082 sub sp, #8 + 8001088: af00 add r7, sp, #0 + + for (uint8_t col = 0; col < COL; col++){ + 800108a: 2300 movs r3, #0 + 800108c: 71fb strb r3, [r7, #7] + 800108e: e05f b.n 8001150 + HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); + 8001090: 79fb ldrb r3, [r7, #7] + 8001092: 4a33 ldr r2, [pc, #204] @ (8001160 ) + 8001094: f852 0033 ldr.w r0, [r2, r3, lsl #3] + 8001098: 79fb ldrb r3, [r7, #7] + 800109a: 4a31 ldr r2, [pc, #196] @ (8001160 ) + 800109c: 00db lsls r3, r3, #3 + 800109e: 4413 add r3, r2 + 80010a0: 889b ldrh r3, [r3, #4] + 80010a2: 2201 movs r2, #1 + 80010a4: 4619 mov r1, r3 + 80010a6: f001 fe2f bl 8002d08 + HAL_Delay(1); + 80010aa: 2001 movs r0, #1 + 80010ac: f000 ff48 bl 8001f40 + for(uint8_t row = 0; row < ROW; row++){ + 80010b0: 2300 movs r3, #0 + 80010b2: 71bb strb r3, [r7, #6] + 80010b4: e039 b.n 800112a + uint8_t new_key = HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN); + 80010b6: 79bb ldrb r3, [r7, #6] + 80010b8: 4a2a ldr r2, [pc, #168] @ (8001164 ) + 80010ba: f852 2033 ldr.w r2, [r2, r3, lsl #3] + 80010be: 79bb ldrb r3, [r7, #6] + 80010c0: 4928 ldr r1, [pc, #160] @ (8001164 ) + 80010c2: 00db lsls r3, r3, #3 + 80010c4: 440b add r3, r1 + 80010c6: 889b ldrh r3, [r3, #4] + 80010c8: 4619 mov r1, r3 + 80010ca: 4610 mov r0, r2 + 80010cc: f001 fe04 bl 8002cd8 + 80010d0: 4603 mov r3, r0 + 80010d2: 717b strb r3, [r7, #5] + if(new_key != KEYSTATE[row][col]){ + 80010d4: 79ba ldrb r2, [r7, #6] + 80010d6: 79f9 ldrb r1, [r7, #7] + 80010d8: 4823 ldr r0, [pc, #140] @ (8001168 ) + 80010da: 4613 mov r3, r2 + 80010dc: 009b lsls r3, r3, #2 + 80010de: 4413 add r3, r2 + 80010e0: 4403 add r3, r0 + 80010e2: 440b add r3, r1 + 80010e4: 781b ldrb r3, [r3, #0] + 80010e6: 797a ldrb r2, [r7, #5] + 80010e8: 429a cmp r2, r3 + 80010ea: d00c beq.n 8001106 + KEYSTATE_CHANGED_FLAG = 1; + 80010ec: 4b1f ldr r3, [pc, #124] @ (800116c ) + 80010ee: 2201 movs r2, #1 + 80010f0: 701a strb r2, [r3, #0] + KEYSTATE[row][col] = new_key; + 80010f2: 79ba ldrb r2, [r7, #6] + 80010f4: 79f9 ldrb r1, [r7, #7] + 80010f6: 481c ldr r0, [pc, #112] @ (8001168 ) + 80010f8: 4613 mov r3, r2 + 80010fa: 009b lsls r3, r3, #2 + 80010fc: 4413 add r3, r2 + 80010fe: 4403 add r3, r0 + 8001100: 440b add r3, r1 + 8001102: 797a ldrb r2, [r7, #5] + 8001104: 701a strb r2, [r3, #0] + } + if(new_key){ + 8001106: 797b ldrb r3, [r7, #5] + 8001108: 2b00 cmp r3, #0 + 800110a: d00b beq.n 8001124 + addUSBReport(KEYCODES[row][col]); + 800110c: 79ba ldrb r2, [r7, #6] + 800110e: 79f9 ldrb r1, [r7, #7] + 8001110: 4817 ldr r0, [pc, #92] @ (8001170 ) + 8001112: 4613 mov r3, r2 + 8001114: 009b lsls r3, r3, #2 + 8001116: 4413 add r3, r2 + 8001118: 4403 add r3, r0 + 800111a: 440b add r3, r1 + 800111c: 781b ldrb r3, [r3, #0] + 800111e: 4618 mov r0, r3 + 8001120: f7ff ff7c bl 800101c + for(uint8_t row = 0; row < ROW; row++){ + 8001124: 79bb ldrb r3, [r7, #6] + 8001126: 3301 adds r3, #1 + 8001128: 71bb strb r3, [r7, #6] + 800112a: 79bb ldrb r3, [r7, #6] + 800112c: 2b05 cmp r3, #5 + 800112e: d9c2 bls.n 80010b6 + } + } + HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); + 8001130: 79fb ldrb r3, [r7, #7] + 8001132: 4a0b ldr r2, [pc, #44] @ (8001160 ) + 8001134: f852 0033 ldr.w r0, [r2, r3, lsl #3] + 8001138: 79fb ldrb r3, [r7, #7] + 800113a: 4a09 ldr r2, [pc, #36] @ (8001160 ) + 800113c: 00db lsls r3, r3, #3 + 800113e: 4413 add r3, r2 + 8001140: 889b ldrh r3, [r3, #4] + 8001142: 2200 movs r2, #0 + 8001144: 4619 mov r1, r3 + 8001146: f001 fddf bl 8002d08 + for (uint8_t col = 0; col < COL; col++){ + 800114a: 79fb ldrb r3, [r7, #7] + 800114c: 3301 adds r3, #1 + 800114e: 71fb strb r3, [r7, #7] + 8001150: 79fb ldrb r3, [r7, #7] + 8001152: 2b04 cmp r3, #4 + 8001154: d99c bls.n 8001090 + } + +} + 8001156: bf00 nop + 8001158: bf00 nop + 800115a: 3708 adds r7, #8 + 800115c: 46bd mov sp, r7 + 800115e: bd80 pop {r7, pc} + 8001160: 20000030 .word 0x20000030 + 8001164: 20000000 .word 0x20000000 + 8001168: 2000026c .word 0x2000026c + 800116c: 20000268 .word 0x20000268 + 8001170: 20000058 .word 0x20000058 + +08001174 : + + +// Read TIM3 encoder counter, calculate delta and add corresponding keycodes +void encoderProcess(void){ + 8001174: b580 push {r7, lr} + 8001176: b086 sub sp, #24 + 8001178: af00 add r7, sp, #0 + int32_t cnt = (int32_t)__HAL_TIM_GET_COUNTER(&htim3); + 800117a: 4b2a ldr r3, [pc, #168] @ (8001224 ) + 800117c: 681b ldr r3, [r3, #0] + 800117e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001180: 603b str r3, [r7, #0] + int32_t diff = cnt - LAST_ENCODER_COUNT; + 8001182: 4b29 ldr r3, [pc, #164] @ (8001228 ) + 8001184: 681b ldr r3, [r3, #0] + 8001186: 683a ldr r2, [r7, #0] + 8001188: 1ad3 subs r3, r2, r3 + 800118a: 617b str r3, [r7, #20] + // TIM3 configured as 16-bit counter (period 65535). Fix wrap-around. + if(diff > 32767) diff -= 65536; + 800118c: 697b ldr r3, [r7, #20] + 800118e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8001192: db03 blt.n 800119c + 8001194: 697b ldr r3, [r7, #20] + 8001196: f5a3 3380 sub.w r3, r3, #65536 @ 0x10000 + 800119a: 617b str r3, [r7, #20] + if(diff < -32768) diff += 65536; + 800119c: 697b ldr r3, [r7, #20] + 800119e: f513 4f00 cmn.w r3, #32768 @ 0x8000 + 80011a2: da03 bge.n 80011ac + 80011a4: 697b ldr r3, [r7, #20] + 80011a6: f503 3380 add.w r3, r3, #65536 @ 0x10000 + 80011aa: 617b str r3, [r7, #20] + if(diff > 0){ + 80011ac: 697b ldr r3, [r7, #20] + 80011ae: 2b00 cmp r3, #0 + 80011b0: dd16 ble.n 80011e0 + int steps = diff; + 80011b2: 697b ldr r3, [r7, #20] + 80011b4: 613b str r3, [r7, #16] + if(steps > 10) steps = 10; // cap bursts + 80011b6: 693b ldr r3, [r7, #16] + 80011b8: 2b0a cmp r3, #10 + 80011ba: dd01 ble.n 80011c0 + 80011bc: 230a movs r3, #10 + 80011be: 613b str r3, [r7, #16] + for(int i = 0; i < steps; i++){ + 80011c0: 2300 movs r3, #0 + 80011c2: 60fb str r3, [r7, #12] + 80011c4: e007 b.n 80011d6 + // CW -> KEYCODES[0][0] + addUSBReport(KEYCODES[3][3]); + 80011c6: 4b19 ldr r3, [pc, #100] @ (800122c ) + 80011c8: 7c9b ldrb r3, [r3, #18] + 80011ca: 4618 mov r0, r3 + 80011cc: f7ff ff26 bl 800101c + for(int i = 0; i < steps; i++){ + 80011d0: 68fb ldr r3, [r7, #12] + 80011d2: 3301 adds r3, #1 + 80011d4: 60fb str r3, [r7, #12] + 80011d6: 68fa ldr r2, [r7, #12] + 80011d8: 693b ldr r3, [r7, #16] + 80011da: 429a cmp r2, r3 + 80011dc: dbf3 blt.n 80011c6 + 80011de: e019 b.n 8001214 + } + }else if(diff < 0){ + 80011e0: 697b ldr r3, [r7, #20] + 80011e2: 2b00 cmp r3, #0 + 80011e4: da16 bge.n 8001214 + int steps = -diff; + 80011e6: 697b ldr r3, [r7, #20] + 80011e8: 425b negs r3, r3 + 80011ea: 60bb str r3, [r7, #8] + if(steps > 10) steps = 10; + 80011ec: 68bb ldr r3, [r7, #8] + 80011ee: 2b0a cmp r3, #10 + 80011f0: dd01 ble.n 80011f6 + 80011f2: 230a movs r3, #10 + 80011f4: 60bb str r3, [r7, #8] + for(int i = 0; i < steps; i++){ + 80011f6: 2300 movs r3, #0 + 80011f8: 607b str r3, [r7, #4] + 80011fa: e007 b.n 800120c + // CCW -> KEYCODES[0][1] + addUSBReport(KEYCODES[2][1]); + 80011fc: 4b0b ldr r3, [pc, #44] @ (800122c ) + 80011fe: 7adb ldrb r3, [r3, #11] + 8001200: 4618 mov r0, r3 + 8001202: f7ff ff0b bl 800101c + for(int i = 0; i < steps; i++){ + 8001206: 687b ldr r3, [r7, #4] + 8001208: 3301 adds r3, #1 + 800120a: 607b str r3, [r7, #4] + 800120c: 687a ldr r2, [r7, #4] + 800120e: 68bb ldr r3, [r7, #8] + 8001210: 429a cmp r2, r3 + 8001212: dbf3 blt.n 80011fc + } + } + LAST_ENCODER_COUNT = cnt; + 8001214: 4a04 ldr r2, [pc, #16] @ (8001228 ) + 8001216: 683b ldr r3, [r7, #0] + 8001218: 6013 str r3, [r2, #0] +} + 800121a: bf00 nop + 800121c: 3718 adds r7, #24 + 800121e: 46bd mov sp, r7 + 8001220: bd80 pop {r7, pc} + 8001222: bf00 nop + 8001224: 20000918 .word 0x20000918 + 8001228: 2000028c .word 0x2000028c + 800122c: 20000058 .word 0x20000058 + +08001230 : + +void resetReport(void){ + 8001230: b580 push {r7, lr} + 8001232: af00 add r7, sp, #0 + memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); + 8001234: 220c movs r2, #12 + 8001236: 2100 movs r1, #0 + 8001238: 4802 ldr r0, [pc, #8] @ (8001244 ) + 800123a: f00a f889 bl 800b350 +} + 800123e: bf00 nop + 8001240: bd80 pop {r7, pc} + 8001242: bf00 nop + 8001244: 20000212 .word 0x20000212 + +08001248 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8001248: b480 push {r7} + 800124a: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 800124c: b672 cpsid i +} + 800124e: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8001250: bf00 nop + 8001252: e7fd b.n 8001250 + +08001254 : +#include "pwm.h" +#include "tim.h" + +void MX_PWM_Init(void){ + 8001254: b580 push {r7, lr} + 8001256: b088 sub sp, #32 + 8001258: af00 add r7, sp, #0 + TIM_OC_InitTypeDef sConfigOC = {0}; + 800125a: 1d3b adds r3, r7, #4 + 800125c: 2200 movs r2, #0 + 800125e: 601a str r2, [r3, #0] + 8001260: 605a str r2, [r3, #4] + 8001262: 609a str r2, [r3, #8] + 8001264: 60da str r2, [r3, #12] + 8001266: 611a str r2, [r3, #16] + 8001268: 615a str r2, [r3, #20] + 800126a: 619a str r2, [r3, #24] + + // Initialize TIM2 for PWM (safe to call even if TIM2 was previously initialized for OC) + if (HAL_TIM_PWM_Init(&htim2) != HAL_OK){ + 800126c: 480f ldr r0, [pc, #60] @ (80012ac ) + 800126e: f004 fa90 bl 8005792 + 8001272: 4603 mov r3, r0 + 8001274: 2b00 cmp r3, #0 + 8001276: d001 beq.n 800127c + Error_Handler(); + 8001278: f7ff ffe6 bl 8001248 + } + + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 800127c: 2360 movs r3, #96 @ 0x60 + 800127e: 607b str r3, [r7, #4] + sConfigOC.Pulse = 0; + 8001280: 2300 movs r3, #0 + 8001282: 60bb str r3, [r7, #8] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 8001284: 2300 movs r3, #0 + 8001286: 60fb str r3, [r7, #12] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 8001288: 2300 movs r3, #0 + 800128a: 617b str r3, [r7, #20] + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK){ + 800128c: 1d3b adds r3, r7, #4 + 800128e: 2200 movs r2, #0 + 8001290: 4619 mov r1, r3 + 8001292: 4806 ldr r0, [pc, #24] @ (80012ac ) + 8001294: f004 fd2e bl 8005cf4 + 8001298: 4603 mov r3, r0 + 800129a: 2b00 cmp r3, #0 + 800129c: d001 beq.n 80012a2 + Error_Handler(); + 800129e: f7ff ffd3 bl 8001248 + } +} + 80012a2: bf00 nop + 80012a4: 3720 adds r7, #32 + 80012a6: 46bd mov sp, r7 + 80012a8: bd80 pop {r7, pc} + 80012aa: bf00 nop + 80012ac: 200008d0 .word 0x200008d0 + +080012b0 : + +void PWM_Start(void){ + 80012b0: b580 push {r7, lr} + 80012b2: af00 add r7, sp, #0 + HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); + 80012b4: 2100 movs r1, #0 + 80012b6: 4802 ldr r0, [pc, #8] @ (80012c0 ) + 80012b8: f004 fac4 bl 8005844 +} + 80012bc: bf00 nop + 80012be: bd80 pop {r7, pc} + 80012c0: 200008d0 .word 0x200008d0 + +080012c4 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 80012c4: b480 push {r7} + 80012c6: b083 sub sp, #12 + 80012c8: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80012ca: 2300 movs r3, #0 + 80012cc: 607b str r3, [r7, #4] + 80012ce: 4b10 ldr r3, [pc, #64] @ (8001310 ) + 80012d0: 6c5b ldr r3, [r3, #68] @ 0x44 + 80012d2: 4a0f ldr r2, [pc, #60] @ (8001310 ) + 80012d4: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 80012d8: 6453 str r3, [r2, #68] @ 0x44 + 80012da: 4b0d ldr r3, [pc, #52] @ (8001310 ) + 80012dc: 6c5b ldr r3, [r3, #68] @ 0x44 + 80012de: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 80012e2: 607b str r3, [r7, #4] + 80012e4: 687b ldr r3, [r7, #4] + __HAL_RCC_PWR_CLK_ENABLE(); + 80012e6: 2300 movs r3, #0 + 80012e8: 603b str r3, [r7, #0] + 80012ea: 4b09 ldr r3, [pc, #36] @ (8001310 ) + 80012ec: 6c1b ldr r3, [r3, #64] @ 0x40 + 80012ee: 4a08 ldr r2, [pc, #32] @ (8001310 ) + 80012f0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 80012f4: 6413 str r3, [r2, #64] @ 0x40 + 80012f6: 4b06 ldr r3, [pc, #24] @ (8001310 ) + 80012f8: 6c1b ldr r3, [r3, #64] @ 0x40 + 80012fa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80012fe: 603b str r3, [r7, #0] + 8001300: 683b ldr r3, [r7, #0] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8001302: bf00 nop + 8001304: 370c adds r7, #12 + 8001306: 46bd mov sp, r7 + 8001308: f85d 7b04 ldr.w r7, [sp], #4 + 800130c: 4770 bx lr + 800130e: bf00 nop + 8001310: 40023800 .word 0x40023800 + +08001314 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8001314: b480 push {r7} + 8001316: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8001318: bf00 nop + 800131a: e7fd b.n 8001318 + +0800131c : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 800131c: b480 push {r7} + 800131e: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8001320: bf00 nop + 8001322: e7fd b.n 8001320 + +08001324 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8001324: b480 push {r7} + 8001326: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8001328: bf00 nop + 800132a: e7fd b.n 8001328 + +0800132c : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 800132c: b480 push {r7} + 800132e: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8001330: bf00 nop + 8001332: e7fd b.n 8001330 + +08001334 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8001334: b480 push {r7} + 8001336: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8001338: bf00 nop + 800133a: e7fd b.n 8001338 + +0800133c : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 800133c: b480 push {r7} + 800133e: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 8001340: bf00 nop + 8001342: 46bd mov sp, r7 + 8001344: f85d 7b04 ldr.w r7, [sp], #4 + 8001348: 4770 bx lr + +0800134a : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 800134a: b480 push {r7} + 800134c: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 800134e: bf00 nop + 8001350: 46bd mov sp, r7 + 8001352: f85d 7b04 ldr.w r7, [sp], #4 + 8001356: 4770 bx lr + +08001358 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8001358: b480 push {r7} + 800135a: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 800135c: bf00 nop + 800135e: 46bd mov sp, r7 + 8001360: f85d 7b04 ldr.w r7, [sp], #4 + 8001364: 4770 bx lr + +08001366 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8001366: b580 push {r7, lr} + 8001368: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 800136a: f000 fdc9 bl 8001f00 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 800136e: bf00 nop + 8001370: bd80 pop {r7, pc} + ... + +08001374 : + +/** + * @brief This function handles DMA1 stream0 global interrupt. + */ +void DMA1_Stream0_IRQHandler(void) +{ + 8001374: b580 push {r7, lr} + 8001376: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ + + /* USER CODE END DMA1_Stream0_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart5_rx); + 8001378: 4802 ldr r0, [pc, #8] @ (8001384 ) + 800137a: f001 f8af bl 80024dc + /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ + + /* USER CODE END DMA1_Stream0_IRQn 1 */ +} + 800137e: bf00 nop + 8001380: bd80 pop {r7, pc} + 8001382: bf00 nop + 8001384: 20000b40 .word 0x20000b40 + +08001388 : + +/** + * @brief This function handles DMA1 stream2 global interrupt. + */ +void DMA1_Stream2_IRQHandler(void) +{ + 8001388: b580 push {r7, lr} + 800138a: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ + + /* USER CODE END DMA1_Stream2_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart4_rx); + 800138c: 4802 ldr r0, [pc, #8] @ (8001398 ) + 800138e: f001 f8a5 bl 80024dc + /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ + + /* USER CODE END DMA1_Stream2_IRQn 1 */ +} + 8001392: bf00 nop + 8001394: bd80 pop {r7, pc} + 8001396: bf00 nop + 8001398: 20000a80 .word 0x20000a80 + +0800139c : + +/** + * @brief This function handles DMA1 stream4 global interrupt. + */ +void DMA1_Stream4_IRQHandler(void) +{ + 800139c: b580 push {r7, lr} + 800139e: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ + + /* USER CODE END DMA1_Stream4_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart4_tx); + 80013a0: 4802 ldr r0, [pc, #8] @ (80013ac ) + 80013a2: f001 f89b bl 80024dc + /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ + + /* USER CODE END DMA1_Stream4_IRQn 1 */ +} + 80013a6: bf00 nop + 80013a8: bd80 pop {r7, pc} + 80013aa: bf00 nop + 80013ac: 20000ae0 .word 0x20000ae0 + +080013b0 : + +/** + * @brief This function handles DMA1 stream5 global interrupt. + */ +void DMA1_Stream5_IRQHandler(void) +{ + 80013b0: b580 push {r7, lr} + 80013b2: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ + + /* USER CODE END DMA1_Stream5_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_rx); + 80013b4: 4802 ldr r0, [pc, #8] @ (80013c0 ) + 80013b6: f001 f891 bl 80024dc + /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ + + /* USER CODE END DMA1_Stream5_IRQn 1 */ +} + 80013ba: bf00 nop + 80013bc: bd80 pop {r7, pc} + 80013be: bf00 nop + 80013c0: 20000cc0 .word 0x20000cc0 + +080013c4 : + +/** + * @brief This function handles DMA1 stream6 global interrupt. + */ +void DMA1_Stream6_IRQHandler(void) +{ + 80013c4: b580 push {r7, lr} + 80013c6: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ + + /* USER CODE END DMA1_Stream6_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_tx); + 80013c8: 4802 ldr r0, [pc, #8] @ (80013d4 ) + 80013ca: f001 f887 bl 80024dc + /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ + + /* USER CODE END DMA1_Stream6_IRQn 1 */ +} + 80013ce: bf00 nop + 80013d0: bd80 pop {r7, pc} + 80013d2: bf00 nop + 80013d4: 20000d20 .word 0x20000d20 + +080013d8 : + +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + 80013d8: b580 push {r7, lr} + 80013da: af00 add r7, sp, #0 + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + 80013dc: 4802 ldr r0, [pc, #8] @ (80013e8 ) + 80013de: f005 f935 bl 800664c + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + 80013e2: bf00 nop + 80013e4: bd80 pop {r7, pc} + 80013e6: bf00 nop + 80013e8: 200009f0 .word 0x200009f0 + +080013ec : + +/** + * @brief This function handles USART2 global interrupt. + */ +void USART2_IRQHandler(void) +{ + 80013ec: b580 push {r7, lr} + 80013ee: af00 add r7, sp, #0 + /* USER CODE BEGIN USART2_IRQn 0 */ + + /* USER CODE END USART2_IRQn 0 */ + HAL_UART_IRQHandler(&huart2); + 80013f0: 4802 ldr r0, [pc, #8] @ (80013fc ) + 80013f2: f005 f92b bl 800664c + /* USER CODE BEGIN USART2_IRQn 1 */ + + /* USER CODE END USART2_IRQn 1 */ +} + 80013f6: bf00 nop + 80013f8: bd80 pop {r7, pc} + 80013fa: bf00 nop + 80013fc: 20000a38 .word 0x20000a38 + +08001400 : + +/** + * @brief This function handles DMA1 stream7 global interrupt. + */ +void DMA1_Stream7_IRQHandler(void) +{ + 8001400: b580 push {r7, lr} + 8001402: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ + + /* USER CODE END DMA1_Stream7_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart5_tx); + 8001404: 4802 ldr r0, [pc, #8] @ (8001410 ) + 8001406: f001 f869 bl 80024dc + /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ + + /* USER CODE END DMA1_Stream7_IRQn 1 */ +} + 800140a: bf00 nop + 800140c: bd80 pop {r7, pc} + 800140e: bf00 nop + 8001410: 20000ba0 .word 0x20000ba0 + +08001414 : + +/** + * @brief This function handles UART4 global interrupt. + */ +void UART4_IRQHandler(void) +{ + 8001414: b580 push {r7, lr} + 8001416: af00 add r7, sp, #0 + /* USER CODE BEGIN UART4_IRQn 0 */ + + /* USER CODE END UART4_IRQn 0 */ + HAL_UART_IRQHandler(&huart4); + 8001418: 4802 ldr r0, [pc, #8] @ (8001424 ) + 800141a: f005 f917 bl 800664c + /* USER CODE BEGIN UART4_IRQn 1 */ + + /* USER CODE END UART4_IRQn 1 */ +} + 800141e: bf00 nop + 8001420: bd80 pop {r7, pc} + 8001422: bf00 nop + 8001424: 20000960 .word 0x20000960 + +08001428 : + +/** + * @brief This function handles UART5 global interrupt. + */ +void UART5_IRQHandler(void) +{ + 8001428: b580 push {r7, lr} + 800142a: af00 add r7, sp, #0 + /* USER CODE BEGIN UART5_IRQn 0 */ + + /* USER CODE END UART5_IRQn 0 */ + HAL_UART_IRQHandler(&huart5); + 800142c: 4802 ldr r0, [pc, #8] @ (8001438 ) + 800142e: f005 f90d bl 800664c + /* USER CODE BEGIN UART5_IRQn 1 */ + + /* USER CODE END UART5_IRQn 1 */ +} + 8001432: bf00 nop + 8001434: bd80 pop {r7, pc} + 8001436: bf00 nop + 8001438: 200009a8 .word 0x200009a8 + +0800143c : + +/** + * @brief This function handles DMA2 stream2 global interrupt. + */ +void DMA2_Stream2_IRQHandler(void) +{ + 800143c: b580 push {r7, lr} + 800143e: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ + + /* USER CODE END DMA2_Stream2_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart1_rx); + 8001440: 4802 ldr r0, [pc, #8] @ (800144c ) + 8001442: f001 f84b bl 80024dc + /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ + + /* USER CODE END DMA2_Stream2_IRQn 1 */ +} + 8001446: bf00 nop + 8001448: bd80 pop {r7, pc} + 800144a: bf00 nop + 800144c: 20000c00 .word 0x20000c00 + +08001450 : + +/** + * @brief This function handles USB On The Go FS global interrupt. + */ +void OTG_FS_IRQHandler(void) +{ + 8001450: b580 push {r7, lr} + 8001452: af00 add r7, sp, #0 + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); + 8001454: 4802 ldr r0, [pc, #8] @ (8001460 ) + 8001456: f001 ff00 bl 800325a + /* USER CODE BEGIN OTG_FS_IRQn 1 */ + + /* USER CODE END OTG_FS_IRQn 1 */ +} + 800145a: bf00 nop + 800145c: bd80 pop {r7, pc} + 800145e: bf00 nop + 8001460: 20001264 .word 0x20001264 + +08001464 : + +/** + * @brief This function handles DMA2 stream7 global interrupt. + */ +void DMA2_Stream7_IRQHandler(void) +{ + 8001464: b580 push {r7, lr} + 8001466: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ + + /* USER CODE END DMA2_Stream7_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart1_tx); + 8001468: 4802 ldr r0, [pc, #8] @ (8001474 ) + 800146a: f001 f837 bl 80024dc + /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ + + /* USER CODE END DMA2_Stream7_IRQn 1 */ +} + 800146e: bf00 nop + 8001470: bd80 pop {r7, pc} + 8001472: bf00 nop + 8001474: 20000c60 .word 0x20000c60 + +08001478 : + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8001478: b480 push {r7} + 800147a: af00 add r7, sp, #0 + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 800147c: 4b06 ldr r3, [pc, #24] @ (8001498 ) + 800147e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8001482: 4a05 ldr r2, [pc, #20] @ (8001498 ) + 8001484: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 + 8001488: f8c2 3088 str.w r3, [r2, #136] @ 0x88 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 800148c: bf00 nop + 800148e: 46bd mov sp, r7 + 8001490: f85d 7b04 ldr.w r7, [sp], #4 + 8001494: 4770 bx lr + 8001496: bf00 nop + 8001498: e000ed00 .word 0xe000ed00 + +0800149c : +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim3; + +/* TIM2 init function */ +void MX_TIM2_Init(void) +{ + 800149c: b580 push {r7, lr} + 800149e: b08a sub sp, #40 @ 0x28 + 80014a0: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 80014a2: f107 0320 add.w r3, r7, #32 + 80014a6: 2200 movs r2, #0 + 80014a8: 601a str r2, [r3, #0] + 80014aa: 605a str r2, [r3, #4] + TIM_OC_InitTypeDef sConfigOC = {0}; + 80014ac: 1d3b adds r3, r7, #4 + 80014ae: 2200 movs r2, #0 + 80014b0: 601a str r2, [r3, #0] + 80014b2: 605a str r2, [r3, #4] + 80014b4: 609a str r2, [r3, #8] + 80014b6: 60da str r2, [r3, #12] + 80014b8: 611a str r2, [r3, #16] + 80014ba: 615a str r2, [r3, #20] + 80014bc: 619a str r2, [r3, #24] + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 80014be: 4b22 ldr r3, [pc, #136] @ (8001548 ) + 80014c0: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 + 80014c4: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 0; + 80014c6: 4b20 ldr r3, [pc, #128] @ (8001548 ) + 80014c8: 2200 movs r2, #0 + 80014ca: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 80014cc: 4b1e ldr r3, [pc, #120] @ (8001548 ) + 80014ce: 2200 movs r2, #0 + 80014d0: 609a str r2, [r3, #8] + htim2.Init.Period = 4294967295; + 80014d2: 4b1d ldr r3, [pc, #116] @ (8001548 ) + 80014d4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 80014d8: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 80014da: 4b1b ldr r3, [pc, #108] @ (8001548 ) + 80014dc: 2200 movs r2, #0 + 80014de: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 80014e0: 4b19 ldr r3, [pc, #100] @ (8001548 ) + 80014e2: 2200 movs r2, #0 + 80014e4: 619a str r2, [r3, #24] + if (HAL_TIM_OC_Init(&htim2) != HAL_OK) + 80014e6: 4818 ldr r0, [pc, #96] @ (8001548 ) + 80014e8: f004 f904 bl 80056f4 + 80014ec: 4603 mov r3, r0 + 80014ee: 2b00 cmp r3, #0 + 80014f0: d001 beq.n 80014f6 + { + Error_Handler(); + 80014f2: f7ff fea9 bl 8001248 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 80014f6: 2300 movs r3, #0 + 80014f8: 623b str r3, [r7, #32] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 80014fa: 2300 movs r3, #0 + 80014fc: 627b str r3, [r7, #36] @ 0x24 + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + 80014fe: f107 0320 add.w r3, r7, #32 + 8001502: 4619 mov r1, r3 + 8001504: 4810 ldr r0, [pc, #64] @ (8001548 ) + 8001506: f004 ff33 bl 8006370 + 800150a: 4603 mov r3, r0 + 800150c: 2b00 cmp r3, #0 + 800150e: d001 beq.n 8001514 + { + Error_Handler(); + 8001510: f7ff fe9a bl 8001248 + } + sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE; + 8001514: 2350 movs r3, #80 @ 0x50 + 8001516: 607b str r3, [r7, #4] + sConfigOC.Pulse = 0; + 8001518: 2300 movs r3, #0 + 800151a: 60bb str r3, [r7, #8] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 800151c: 2300 movs r3, #0 + 800151e: 60fb str r3, [r7, #12] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 8001520: 2300 movs r3, #0 + 8001522: 617b str r3, [r7, #20] + if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 8001524: 1d3b adds r3, r7, #4 + 8001526: 2200 movs r2, #0 + 8001528: 4619 mov r1, r3 + 800152a: 4807 ldr r0, [pc, #28] @ (8001548 ) + 800152c: f004 fb86 bl 8005c3c + 8001530: 4603 mov r3, r0 + 8001532: 2b00 cmp r3, #0 + 8001534: d001 beq.n 800153a + { + Error_Handler(); + 8001536: f7ff fe87 bl 8001248 + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + HAL_TIM_MspPostInit(&htim2); + 800153a: 4803 ldr r0, [pc, #12] @ (8001548 ) + 800153c: f000 f8c2 bl 80016c4 + +} + 8001540: bf00 nop + 8001542: 3728 adds r7, #40 @ 0x28 + 8001544: 46bd mov sp, r7 + 8001546: bd80 pop {r7, pc} + 8001548: 200008d0 .word 0x200008d0 + +0800154c : +/* TIM3 init function */ +void MX_TIM3_Init(void) +{ + 800154c: b580 push {r7, lr} + 800154e: b08c sub sp, #48 @ 0x30 + 8001550: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = {0}; + 8001552: f107 030c add.w r3, r7, #12 + 8001556: 2224 movs r2, #36 @ 0x24 + 8001558: 2100 movs r1, #0 + 800155a: 4618 mov r0, r3 + 800155c: f009 fef8 bl 800b350 + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8001560: 1d3b adds r3, r7, #4 + 8001562: 2200 movs r2, #0 + 8001564: 601a str r2, [r3, #0] + 8001566: 605a str r2, [r3, #4] + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + 8001568: 4b20 ldr r3, [pc, #128] @ (80015ec ) + 800156a: 4a21 ldr r2, [pc, #132] @ (80015f0 ) + 800156c: 601a str r2, [r3, #0] + htim3.Init.Prescaler = 0; + 800156e: 4b1f ldr r3, [pc, #124] @ (80015ec ) + 8001570: 2200 movs r2, #0 + 8001572: 605a str r2, [r3, #4] + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + 8001574: 4b1d ldr r3, [pc, #116] @ (80015ec ) + 8001576: 2200 movs r2, #0 + 8001578: 609a str r2, [r3, #8] + htim3.Init.Period = 65535; + 800157a: 4b1c ldr r3, [pc, #112] @ (80015ec ) + 800157c: f64f 72ff movw r2, #65535 @ 0xffff + 8001580: 60da str r2, [r3, #12] + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8001582: 4b1a ldr r3, [pc, #104] @ (80015ec ) + 8001584: 2200 movs r2, #0 + 8001586: 611a str r2, [r3, #16] + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8001588: 4b18 ldr r3, [pc, #96] @ (80015ec ) + 800158a: 2200 movs r2, #0 + 800158c: 619a str r2, [r3, #24] + sConfig.EncoderMode = TIM_ENCODERMODE_TI1; + 800158e: 2301 movs r3, #1 + 8001590: 60fb str r3, [r7, #12] + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + 8001592: 2300 movs r3, #0 + 8001594: 613b str r3, [r7, #16] + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + 8001596: 2301 movs r3, #1 + 8001598: 617b str r3, [r7, #20] + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + 800159a: 2300 movs r3, #0 + 800159c: 61bb str r3, [r7, #24] + sConfig.IC1Filter = 0; + 800159e: 2300 movs r3, #0 + 80015a0: 61fb str r3, [r7, #28] + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + 80015a2: 2300 movs r3, #0 + 80015a4: 623b str r3, [r7, #32] + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + 80015a6: 2301 movs r3, #1 + 80015a8: 627b str r3, [r7, #36] @ 0x24 + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + 80015aa: 2300 movs r3, #0 + 80015ac: 62bb str r3, [r7, #40] @ 0x28 + sConfig.IC2Filter = 0; + 80015ae: 2300 movs r3, #0 + 80015b0: 62fb str r3, [r7, #44] @ 0x2c + if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) + 80015b2: f107 030c add.w r3, r7, #12 + 80015b6: 4619 mov r1, r3 + 80015b8: 480c ldr r0, [pc, #48] @ (80015ec ) + 80015ba: f004 fa0b bl 80059d4 + 80015be: 4603 mov r3, r0 + 80015c0: 2b00 cmp r3, #0 + 80015c2: d001 beq.n 80015c8 + { + Error_Handler(); + 80015c4: f7ff fe40 bl 8001248 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 80015c8: 2300 movs r3, #0 + 80015ca: 607b str r3, [r7, #4] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 80015cc: 2300 movs r3, #0 + 80015ce: 60bb str r3, [r7, #8] + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + 80015d0: 1d3b adds r3, r7, #4 + 80015d2: 4619 mov r1, r3 + 80015d4: 4805 ldr r0, [pc, #20] @ (80015ec ) + 80015d6: f004 fecb bl 8006370 + 80015da: 4603 mov r3, r0 + 80015dc: 2b00 cmp r3, #0 + 80015de: d001 beq.n 80015e4 + { + Error_Handler(); + 80015e0: f7ff fe32 bl 8001248 + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + +} + 80015e4: bf00 nop + 80015e6: 3730 adds r7, #48 @ 0x30 + 80015e8: 46bd mov sp, r7 + 80015ea: bd80 pop {r7, pc} + 80015ec: 20000918 .word 0x20000918 + 80015f0: 40000400 .word 0x40000400 + +080015f4 : + +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle) +{ + 80015f4: b480 push {r7} + 80015f6: b085 sub sp, #20 + 80015f8: af00 add r7, sp, #0 + 80015fa: 6078 str r0, [r7, #4] + + if(tim_ocHandle->Instance==TIM2) + 80015fc: 687b ldr r3, [r7, #4] + 80015fe: 681b ldr r3, [r3, #0] + 8001600: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8001604: d10d bne.n 8001622 + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* TIM2 clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + 8001606: 2300 movs r3, #0 + 8001608: 60fb str r3, [r7, #12] + 800160a: 4b09 ldr r3, [pc, #36] @ (8001630 ) + 800160c: 6c1b ldr r3, [r3, #64] @ 0x40 + 800160e: 4a08 ldr r2, [pc, #32] @ (8001630 ) + 8001610: f043 0301 orr.w r3, r3, #1 + 8001614: 6413 str r3, [r2, #64] @ 0x40 + 8001616: 4b06 ldr r3, [pc, #24] @ (8001630 ) + 8001618: 6c1b ldr r3, [r3, #64] @ 0x40 + 800161a: f003 0301 and.w r3, r3, #1 + 800161e: 60fb str r3, [r7, #12] + 8001620: 68fb ldr r3, [r7, #12] + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } +} + 8001622: bf00 nop + 8001624: 3714 adds r7, #20 + 8001626: 46bd mov sp, r7 + 8001628: f85d 7b04 ldr.w r7, [sp], #4 + 800162c: 4770 bx lr + 800162e: bf00 nop + 8001630: 40023800 .word 0x40023800 + +08001634 : + +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) +{ + 8001634: b580 push {r7, lr} + 8001636: b08a sub sp, #40 @ 0x28 + 8001638: af00 add r7, sp, #0 + 800163a: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800163c: f107 0314 add.w r3, r7, #20 + 8001640: 2200 movs r2, #0 + 8001642: 601a str r2, [r3, #0] + 8001644: 605a str r2, [r3, #4] + 8001646: 609a str r2, [r3, #8] + 8001648: 60da str r2, [r3, #12] + 800164a: 611a str r2, [r3, #16] + if(tim_encoderHandle->Instance==TIM3) + 800164c: 687b ldr r3, [r7, #4] + 800164e: 681b ldr r3, [r3, #0] + 8001650: 4a19 ldr r2, [pc, #100] @ (80016b8 ) + 8001652: 4293 cmp r3, r2 + 8001654: d12b bne.n 80016ae + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* TIM3 clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + 8001656: 2300 movs r3, #0 + 8001658: 613b str r3, [r7, #16] + 800165a: 4b18 ldr r3, [pc, #96] @ (80016bc ) + 800165c: 6c1b ldr r3, [r3, #64] @ 0x40 + 800165e: 4a17 ldr r2, [pc, #92] @ (80016bc ) + 8001660: f043 0302 orr.w r3, r3, #2 + 8001664: 6413 str r3, [r2, #64] @ 0x40 + 8001666: 4b15 ldr r3, [pc, #84] @ (80016bc ) + 8001668: 6c1b ldr r3, [r3, #64] @ 0x40 + 800166a: f003 0302 and.w r3, r3, #2 + 800166e: 613b str r3, [r7, #16] + 8001670: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001672: 2300 movs r3, #0 + 8001674: 60fb str r3, [r7, #12] + 8001676: 4b11 ldr r3, [pc, #68] @ (80016bc ) + 8001678: 6b1b ldr r3, [r3, #48] @ 0x30 + 800167a: 4a10 ldr r2, [pc, #64] @ (80016bc ) + 800167c: f043 0301 orr.w r3, r3, #1 + 8001680: 6313 str r3, [r2, #48] @ 0x30 + 8001682: 4b0e ldr r3, [pc, #56] @ (80016bc ) + 8001684: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001686: f003 0301 and.w r3, r3, #1 + 800168a: 60fb str r3, [r7, #12] + 800168c: 68fb ldr r3, [r7, #12] + /**TIM3 GPIO Configuration + PA6 ------> TIM3_CH1 + PA7 ------> TIM3_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + 800168e: 23c0 movs r3, #192 @ 0xc0 + 8001690: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001692: 2302 movs r3, #2 + 8001694: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001696: 2300 movs r3, #0 + 8001698: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800169a: 2300 movs r3, #0 + 800169c: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + 800169e: 2302 movs r3, #2 + 80016a0: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80016a2: f107 0314 add.w r3, r7, #20 + 80016a6: 4619 mov r1, r3 + 80016a8: 4805 ldr r0, [pc, #20] @ (80016c0 ) + 80016aa: f001 f981 bl 80029b0 + + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } +} + 80016ae: bf00 nop + 80016b0: 3728 adds r7, #40 @ 0x28 + 80016b2: 46bd mov sp, r7 + 80016b4: bd80 pop {r7, pc} + 80016b6: bf00 nop + 80016b8: 40000400 .word 0x40000400 + 80016bc: 40023800 .word 0x40023800 + 80016c0: 40020000 .word 0x40020000 + +080016c4 : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) +{ + 80016c4: b580 push {r7, lr} + 80016c6: b088 sub sp, #32 + 80016c8: af00 add r7, sp, #0 + 80016ca: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80016cc: f107 030c add.w r3, r7, #12 + 80016d0: 2200 movs r2, #0 + 80016d2: 601a str r2, [r3, #0] + 80016d4: 605a str r2, [r3, #4] + 80016d6: 609a str r2, [r3, #8] + 80016d8: 60da str r2, [r3, #12] + 80016da: 611a str r2, [r3, #16] + if(timHandle->Instance==TIM2) + 80016dc: 687b ldr r3, [r7, #4] + 80016de: 681b ldr r3, [r3, #0] + 80016e0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80016e4: d11d bne.n 8001722 + { + /* USER CODE BEGIN TIM2_MspPostInit 0 */ + + /* USER CODE END TIM2_MspPostInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80016e6: 2300 movs r3, #0 + 80016e8: 60bb str r3, [r7, #8] + 80016ea: 4b10 ldr r3, [pc, #64] @ (800172c ) + 80016ec: 6b1b ldr r3, [r3, #48] @ 0x30 + 80016ee: 4a0f ldr r2, [pc, #60] @ (800172c ) + 80016f0: f043 0301 orr.w r3, r3, #1 + 80016f4: 6313 str r3, [r2, #48] @ 0x30 + 80016f6: 4b0d ldr r3, [pc, #52] @ (800172c ) + 80016f8: 6b1b ldr r3, [r3, #48] @ 0x30 + 80016fa: f003 0301 and.w r3, r3, #1 + 80016fe: 60bb str r3, [r7, #8] + 8001700: 68bb ldr r3, [r7, #8] + /**TIM2 GPIO Configuration + PA5 ------> TIM2_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_5; + 8001702: 2320 movs r3, #32 + 8001704: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001706: 2302 movs r3, #2 + 8001708: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800170a: 2300 movs r3, #0 + 800170c: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800170e: 2300 movs r3, #0 + 8001710: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + 8001712: 2301 movs r3, #1 + 8001714: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001716: f107 030c add.w r3, r7, #12 + 800171a: 4619 mov r1, r3 + 800171c: 4804 ldr r0, [pc, #16] @ (8001730 ) + 800171e: f001 f947 bl 80029b0 + /* USER CODE BEGIN TIM2_MspPostInit 1 */ + + /* USER CODE END TIM2_MspPostInit 1 */ + } + +} + 8001722: bf00 nop + 8001724: 3720 adds r7, #32 + 8001726: 46bd mov sp, r7 + 8001728: bd80 pop {r7, pc} + 800172a: bf00 nop + 800172c: 40023800 .word 0x40023800 + 8001730: 40020000 .word 0x40020000 + +08001734 : +DMA_HandleTypeDef hdma_usart2_rx; +DMA_HandleTypeDef hdma_usart2_tx; + +/* UART4 init function */ +void MX_UART4_Init(void) +{ + 8001734: b580 push {r7, lr} + 8001736: af00 add r7, sp, #0 + /* USER CODE END UART4_Init 0 */ + + /* USER CODE BEGIN UART4_Init 1 */ + + /* USER CODE END UART4_Init 1 */ + huart4.Instance = UART4; + 8001738: 4b11 ldr r3, [pc, #68] @ (8001780 ) + 800173a: 4a12 ldr r2, [pc, #72] @ (8001784 ) + 800173c: 601a str r2, [r3, #0] + huart4.Init.BaudRate = 115200; + 800173e: 4b10 ldr r3, [pc, #64] @ (8001780 ) + 8001740: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 8001744: 605a str r2, [r3, #4] + huart4.Init.WordLength = UART_WORDLENGTH_8B; + 8001746: 4b0e ldr r3, [pc, #56] @ (8001780 ) + 8001748: 2200 movs r2, #0 + 800174a: 609a str r2, [r3, #8] + huart4.Init.StopBits = UART_STOPBITS_1; + 800174c: 4b0c ldr r3, [pc, #48] @ (8001780 ) + 800174e: 2200 movs r2, #0 + 8001750: 60da str r2, [r3, #12] + huart4.Init.Parity = UART_PARITY_NONE; + 8001752: 4b0b ldr r3, [pc, #44] @ (8001780 ) + 8001754: 2200 movs r2, #0 + 8001756: 611a str r2, [r3, #16] + huart4.Init.Mode = UART_MODE_TX_RX; + 8001758: 4b09 ldr r3, [pc, #36] @ (8001780 ) + 800175a: 220c movs r2, #12 + 800175c: 615a str r2, [r3, #20] + huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 800175e: 4b08 ldr r3, [pc, #32] @ (8001780 ) + 8001760: 2200 movs r2, #0 + 8001762: 619a str r2, [r3, #24] + huart4.Init.OverSampling = UART_OVERSAMPLING_16; + 8001764: 4b06 ldr r3, [pc, #24] @ (8001780 ) + 8001766: 2200 movs r2, #0 + 8001768: 61da str r2, [r3, #28] + if (HAL_UART_Init(&huart4) != HAL_OK) + 800176a: 4805 ldr r0, [pc, #20] @ (8001780 ) + 800176c: f004 fe7c bl 8006468 + 8001770: 4603 mov r3, r0 + 8001772: 2b00 cmp r3, #0 + 8001774: d001 beq.n 800177a + { + Error_Handler(); + 8001776: f7ff fd67 bl 8001248 + } + /* USER CODE BEGIN UART4_Init 2 */ + + /* USER CODE END UART4_Init 2 */ + +} + 800177a: bf00 nop + 800177c: bd80 pop {r7, pc} + 800177e: bf00 nop + 8001780: 20000960 .word 0x20000960 + 8001784: 40004c00 .word 0x40004c00 + +08001788 : +/* UART5 init function */ +void MX_UART5_Init(void) +{ + 8001788: b580 push {r7, lr} + 800178a: af00 add r7, sp, #0 + /* USER CODE END UART5_Init 0 */ + + /* USER CODE BEGIN UART5_Init 1 */ + + /* USER CODE END UART5_Init 1 */ + huart5.Instance = UART5; + 800178c: 4b11 ldr r3, [pc, #68] @ (80017d4 ) + 800178e: 4a12 ldr r2, [pc, #72] @ (80017d8 ) + 8001790: 601a str r2, [r3, #0] + huart5.Init.BaudRate = 115200; + 8001792: 4b10 ldr r3, [pc, #64] @ (80017d4 ) + 8001794: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 8001798: 605a str r2, [r3, #4] + huart5.Init.WordLength = UART_WORDLENGTH_8B; + 800179a: 4b0e ldr r3, [pc, #56] @ (80017d4 ) + 800179c: 2200 movs r2, #0 + 800179e: 609a str r2, [r3, #8] + huart5.Init.StopBits = UART_STOPBITS_1; + 80017a0: 4b0c ldr r3, [pc, #48] @ (80017d4 ) + 80017a2: 2200 movs r2, #0 + 80017a4: 60da str r2, [r3, #12] + huart5.Init.Parity = UART_PARITY_NONE; + 80017a6: 4b0b ldr r3, [pc, #44] @ (80017d4 ) + 80017a8: 2200 movs r2, #0 + 80017aa: 611a str r2, [r3, #16] + huart5.Init.Mode = UART_MODE_TX_RX; + 80017ac: 4b09 ldr r3, [pc, #36] @ (80017d4 ) + 80017ae: 220c movs r2, #12 + 80017b0: 615a str r2, [r3, #20] + huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 80017b2: 4b08 ldr r3, [pc, #32] @ (80017d4 ) + 80017b4: 2200 movs r2, #0 + 80017b6: 619a str r2, [r3, #24] + huart5.Init.OverSampling = UART_OVERSAMPLING_16; + 80017b8: 4b06 ldr r3, [pc, #24] @ (80017d4 ) + 80017ba: 2200 movs r2, #0 + 80017bc: 61da str r2, [r3, #28] + if (HAL_UART_Init(&huart5) != HAL_OK) + 80017be: 4805 ldr r0, [pc, #20] @ (80017d4 ) + 80017c0: f004 fe52 bl 8006468 + 80017c4: 4603 mov r3, r0 + 80017c6: 2b00 cmp r3, #0 + 80017c8: d001 beq.n 80017ce + { + Error_Handler(); + 80017ca: f7ff fd3d bl 8001248 + } + /* USER CODE BEGIN UART5_Init 2 */ + + /* USER CODE END UART5_Init 2 */ + +} + 80017ce: bf00 nop + 80017d0: bd80 pop {r7, pc} + 80017d2: bf00 nop + 80017d4: 200009a8 .word 0x200009a8 + 80017d8: 40005000 .word 0x40005000 + +080017dc : +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + 80017dc: b580 push {r7, lr} + 80017de: af00 add r7, sp, #0 + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + 80017e0: 4b11 ldr r3, [pc, #68] @ (8001828 ) + 80017e2: 4a12 ldr r2, [pc, #72] @ (800182c ) + 80017e4: 601a str r2, [r3, #0] + huart1.Init.BaudRate = 115200; + 80017e6: 4b10 ldr r3, [pc, #64] @ (8001828 ) + 80017e8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 80017ec: 605a str r2, [r3, #4] + huart1.Init.WordLength = UART_WORDLENGTH_8B; + 80017ee: 4b0e ldr r3, [pc, #56] @ (8001828 ) + 80017f0: 2200 movs r2, #0 + 80017f2: 609a str r2, [r3, #8] + huart1.Init.StopBits = UART_STOPBITS_1; + 80017f4: 4b0c ldr r3, [pc, #48] @ (8001828 ) + 80017f6: 2200 movs r2, #0 + 80017f8: 60da str r2, [r3, #12] + huart1.Init.Parity = UART_PARITY_NONE; + 80017fa: 4b0b ldr r3, [pc, #44] @ (8001828 ) + 80017fc: 2200 movs r2, #0 + 80017fe: 611a str r2, [r3, #16] + huart1.Init.Mode = UART_MODE_TX_RX; + 8001800: 4b09 ldr r3, [pc, #36] @ (8001828 ) + 8001802: 220c movs r2, #12 + 8001804: 615a str r2, [r3, #20] + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 8001806: 4b08 ldr r3, [pc, #32] @ (8001828 ) + 8001808: 2200 movs r2, #0 + 800180a: 619a str r2, [r3, #24] + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + 800180c: 4b06 ldr r3, [pc, #24] @ (8001828 ) + 800180e: 2200 movs r2, #0 + 8001810: 61da str r2, [r3, #28] + if (HAL_UART_Init(&huart1) != HAL_OK) + 8001812: 4805 ldr r0, [pc, #20] @ (8001828 ) + 8001814: f004 fe28 bl 8006468 + 8001818: 4603 mov r3, r0 + 800181a: 2b00 cmp r3, #0 + 800181c: d001 beq.n 8001822 + { + Error_Handler(); + 800181e: f7ff fd13 bl 8001248 + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + 8001822: bf00 nop + 8001824: bd80 pop {r7, pc} + 8001826: bf00 nop + 8001828: 200009f0 .word 0x200009f0 + 800182c: 40011000 .word 0x40011000 + +08001830 : +/* USART2 init function */ + +void MX_USART2_UART_Init(void) +{ + 8001830: b580 push {r7, lr} + 8001832: af00 add r7, sp, #0 + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + 8001834: 4b11 ldr r3, [pc, #68] @ (800187c ) + 8001836: 4a12 ldr r2, [pc, #72] @ (8001880 ) + 8001838: 601a str r2, [r3, #0] + huart2.Init.BaudRate = 115200; + 800183a: 4b10 ldr r3, [pc, #64] @ (800187c ) + 800183c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 + 8001840: 605a str r2, [r3, #4] + huart2.Init.WordLength = UART_WORDLENGTH_8B; + 8001842: 4b0e ldr r3, [pc, #56] @ (800187c ) + 8001844: 2200 movs r2, #0 + 8001846: 609a str r2, [r3, #8] + huart2.Init.StopBits = UART_STOPBITS_1; + 8001848: 4b0c ldr r3, [pc, #48] @ (800187c ) + 800184a: 2200 movs r2, #0 + 800184c: 60da str r2, [r3, #12] + huart2.Init.Parity = UART_PARITY_NONE; + 800184e: 4b0b ldr r3, [pc, #44] @ (800187c ) + 8001850: 2200 movs r2, #0 + 8001852: 611a str r2, [r3, #16] + huart2.Init.Mode = UART_MODE_TX_RX; + 8001854: 4b09 ldr r3, [pc, #36] @ (800187c ) + 8001856: 220c movs r2, #12 + 8001858: 615a str r2, [r3, #20] + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 800185a: 4b08 ldr r3, [pc, #32] @ (800187c ) + 800185c: 2200 movs r2, #0 + 800185e: 619a str r2, [r3, #24] + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + 8001860: 4b06 ldr r3, [pc, #24] @ (800187c ) + 8001862: 2200 movs r2, #0 + 8001864: 61da str r2, [r3, #28] + if (HAL_UART_Init(&huart2) != HAL_OK) + 8001866: 4805 ldr r0, [pc, #20] @ (800187c ) + 8001868: f004 fdfe bl 8006468 + 800186c: 4603 mov r3, r0 + 800186e: 2b00 cmp r3, #0 + 8001870: d001 beq.n 8001876 + { + Error_Handler(); + 8001872: f7ff fce9 bl 8001248 + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + 8001876: bf00 nop + 8001878: bd80 pop {r7, pc} + 800187a: bf00 nop + 800187c: 20000a38 .word 0x20000a38 + 8001880: 40004400 .word 0x40004400 + +08001884 : + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + 8001884: b580 push {r7, lr} + 8001886: b090 sub sp, #64 @ 0x40 + 8001888: af00 add r7, sp, #0 + 800188a: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800188c: f107 032c add.w r3, r7, #44 @ 0x2c + 8001890: 2200 movs r2, #0 + 8001892: 601a str r2, [r3, #0] + 8001894: 605a str r2, [r3, #4] + 8001896: 609a str r2, [r3, #8] + 8001898: 60da str r2, [r3, #12] + 800189a: 611a str r2, [r3, #16] + if(uartHandle->Instance==UART4) + 800189c: 687b ldr r3, [r7, #4] + 800189e: 681b ldr r3, [r3, #0] + 80018a0: 4a4a ldr r2, [pc, #296] @ (80019cc ) + 80018a2: 4293 cmp r3, r2 + 80018a4: f040 80a0 bne.w 80019e8 + { + /* USER CODE BEGIN UART4_MspInit 0 */ + + /* USER CODE END UART4_MspInit 0 */ + /* UART4 clock enable */ + __HAL_RCC_UART4_CLK_ENABLE(); + 80018a8: 2300 movs r3, #0 + 80018aa: 62bb str r3, [r7, #40] @ 0x28 + 80018ac: 4b48 ldr r3, [pc, #288] @ (80019d0 ) + 80018ae: 6c1b ldr r3, [r3, #64] @ 0x40 + 80018b0: 4a47 ldr r2, [pc, #284] @ (80019d0 ) + 80018b2: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 80018b6: 6413 str r3, [r2, #64] @ 0x40 + 80018b8: 4b45 ldr r3, [pc, #276] @ (80019d0 ) + 80018ba: 6c1b ldr r3, [r3, #64] @ 0x40 + 80018bc: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 80018c0: 62bb str r3, [r7, #40] @ 0x28 + 80018c2: 6abb ldr r3, [r7, #40] @ 0x28 + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80018c4: 2300 movs r3, #0 + 80018c6: 627b str r3, [r7, #36] @ 0x24 + 80018c8: 4b41 ldr r3, [pc, #260] @ (80019d0 ) + 80018ca: 6b1b ldr r3, [r3, #48] @ 0x30 + 80018cc: 4a40 ldr r2, [pc, #256] @ (80019d0 ) + 80018ce: f043 0301 orr.w r3, r3, #1 + 80018d2: 6313 str r3, [r2, #48] @ 0x30 + 80018d4: 4b3e ldr r3, [pc, #248] @ (80019d0 ) + 80018d6: 6b1b ldr r3, [r3, #48] @ 0x30 + 80018d8: f003 0301 and.w r3, r3, #1 + 80018dc: 627b str r3, [r7, #36] @ 0x24 + 80018de: 6a7b ldr r3, [r7, #36] @ 0x24 + /**UART4 GPIO Configuration + PA0-WKUP ------> UART4_TX + PA1 ------> UART4_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + 80018e0: 2303 movs r3, #3 + 80018e2: 62fb str r3, [r7, #44] @ 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80018e4: 2302 movs r3, #2 + 80018e6: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80018e8: 2300 movs r3, #0 + 80018ea: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80018ec: 2303 movs r3, #3 + 80018ee: 63bb str r3, [r7, #56] @ 0x38 + GPIO_InitStruct.Alternate = GPIO_AF8_UART4; + 80018f0: 2308 movs r3, #8 + 80018f2: 63fb str r3, [r7, #60] @ 0x3c + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80018f4: f107 032c add.w r3, r7, #44 @ 0x2c + 80018f8: 4619 mov r1, r3 + 80018fa: 4836 ldr r0, [pc, #216] @ (80019d4 ) + 80018fc: f001 f858 bl 80029b0 + + /* UART4 DMA Init */ + /* UART4_RX Init */ + hdma_uart4_rx.Instance = DMA1_Stream2; + 8001900: 4b35 ldr r3, [pc, #212] @ (80019d8 ) + 8001902: 4a36 ldr r2, [pc, #216] @ (80019dc ) + 8001904: 601a str r2, [r3, #0] + hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; + 8001906: 4b34 ldr r3, [pc, #208] @ (80019d8 ) + 8001908: f04f 6200 mov.w r2, #134217728 @ 0x8000000 + 800190c: 605a str r2, [r3, #4] + hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + 800190e: 4b32 ldr r3, [pc, #200] @ (80019d8 ) + 8001910: 2200 movs r2, #0 + 8001912: 609a str r2, [r3, #8] + hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; + 8001914: 4b30 ldr r3, [pc, #192] @ (80019d8 ) + 8001916: 2200 movs r2, #0 + 8001918: 60da str r2, [r3, #12] + hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; + 800191a: 4b2f ldr r3, [pc, #188] @ (80019d8 ) + 800191c: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001920: 611a str r2, [r3, #16] + hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 8001922: 4b2d ldr r3, [pc, #180] @ (80019d8 ) + 8001924: 2200 movs r2, #0 + 8001926: 615a str r2, [r3, #20] + hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 8001928: 4b2b ldr r3, [pc, #172] @ (80019d8 ) + 800192a: 2200 movs r2, #0 + 800192c: 619a str r2, [r3, #24] + hdma_uart4_rx.Init.Mode = DMA_NORMAL; + 800192e: 4b2a ldr r3, [pc, #168] @ (80019d8 ) + 8001930: 2200 movs r2, #0 + 8001932: 61da str r2, [r3, #28] + hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; + 8001934: 4b28 ldr r3, [pc, #160] @ (80019d8 ) + 8001936: 2200 movs r2, #0 + 8001938: 621a str r2, [r3, #32] + hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + 800193a: 4b27 ldr r3, [pc, #156] @ (80019d8 ) + 800193c: 2200 movs r2, #0 + 800193e: 625a str r2, [r3, #36] @ 0x24 + if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) + 8001940: 4825 ldr r0, [pc, #148] @ (80019d8 ) + 8001942: f000 fc33 bl 80021ac + 8001946: 4603 mov r3, r0 + 8001948: 2b00 cmp r3, #0 + 800194a: d001 beq.n 8001950 + { + Error_Handler(); + 800194c: f7ff fc7c bl 8001248 + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); + 8001950: 687b ldr r3, [r7, #4] + 8001952: 4a21 ldr r2, [pc, #132] @ (80019d8 ) + 8001954: 63da str r2, [r3, #60] @ 0x3c + 8001956: 4a20 ldr r2, [pc, #128] @ (80019d8 ) + 8001958: 687b ldr r3, [r7, #4] + 800195a: 6393 str r3, [r2, #56] @ 0x38 + + /* UART4_TX Init */ + hdma_uart4_tx.Instance = DMA1_Stream4; + 800195c: 4b20 ldr r3, [pc, #128] @ (80019e0 ) + 800195e: 4a21 ldr r2, [pc, #132] @ (80019e4 ) + 8001960: 601a str r2, [r3, #0] + hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; + 8001962: 4b1f ldr r3, [pc, #124] @ (80019e0 ) + 8001964: f04f 6200 mov.w r2, #134217728 @ 0x8000000 + 8001968: 605a str r2, [r3, #4] + hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + 800196a: 4b1d ldr r3, [pc, #116] @ (80019e0 ) + 800196c: 2240 movs r2, #64 @ 0x40 + 800196e: 609a str r2, [r3, #8] + hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; + 8001970: 4b1b ldr r3, [pc, #108] @ (80019e0 ) + 8001972: 2200 movs r2, #0 + 8001974: 60da str r2, [r3, #12] + hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; + 8001976: 4b1a ldr r3, [pc, #104] @ (80019e0 ) + 8001978: f44f 6280 mov.w r2, #1024 @ 0x400 + 800197c: 611a str r2, [r3, #16] + hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 800197e: 4b18 ldr r3, [pc, #96] @ (80019e0 ) + 8001980: 2200 movs r2, #0 + 8001982: 615a str r2, [r3, #20] + hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 8001984: 4b16 ldr r3, [pc, #88] @ (80019e0 ) + 8001986: 2200 movs r2, #0 + 8001988: 619a str r2, [r3, #24] + hdma_uart4_tx.Init.Mode = DMA_NORMAL; + 800198a: 4b15 ldr r3, [pc, #84] @ (80019e0 ) + 800198c: 2200 movs r2, #0 + 800198e: 61da str r2, [r3, #28] + hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; + 8001990: 4b13 ldr r3, [pc, #76] @ (80019e0 ) + 8001992: 2200 movs r2, #0 + 8001994: 621a str r2, [r3, #32] + hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + 8001996: 4b12 ldr r3, [pc, #72] @ (80019e0 ) + 8001998: 2200 movs r2, #0 + 800199a: 625a str r2, [r3, #36] @ 0x24 + if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) + 800199c: 4810 ldr r0, [pc, #64] @ (80019e0 ) + 800199e: f000 fc05 bl 80021ac + 80019a2: 4603 mov r3, r0 + 80019a4: 2b00 cmp r3, #0 + 80019a6: d001 beq.n 80019ac + { + Error_Handler(); + 80019a8: f7ff fc4e bl 8001248 + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); + 80019ac: 687b ldr r3, [r7, #4] + 80019ae: 4a0c ldr r2, [pc, #48] @ (80019e0 ) + 80019b0: 639a str r2, [r3, #56] @ 0x38 + 80019b2: 4a0b ldr r2, [pc, #44] @ (80019e0 ) + 80019b4: 687b ldr r3, [r7, #4] + 80019b6: 6393 str r3, [r2, #56] @ 0x38 + + /* UART4 interrupt Init */ + HAL_NVIC_SetPriority(UART4_IRQn, 5, 0); + 80019b8: 2200 movs r2, #0 + 80019ba: 2105 movs r1, #5 + 80019bc: 2034 movs r0, #52 @ 0x34 + 80019be: f000 fbbe bl 800213e + HAL_NVIC_EnableIRQ(UART4_IRQn); + 80019c2: 2034 movs r0, #52 @ 0x34 + 80019c4: f000 fbd7 bl 8002176 + HAL_NVIC_EnableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } +} + 80019c8: e202 b.n 8001dd0 + 80019ca: bf00 nop + 80019cc: 40004c00 .word 0x40004c00 + 80019d0: 40023800 .word 0x40023800 + 80019d4: 40020000 .word 0x40020000 + 80019d8: 20000a80 .word 0x20000a80 + 80019dc: 40026040 .word 0x40026040 + 80019e0: 20000ae0 .word 0x20000ae0 + 80019e4: 40026070 .word 0x40026070 + else if(uartHandle->Instance==UART5) + 80019e8: 687b ldr r3, [r7, #4] + 80019ea: 681b ldr r3, [r3, #0] + 80019ec: 4a59 ldr r2, [pc, #356] @ (8001b54 ) + 80019ee: 4293 cmp r3, r2 + 80019f0: f040 80c0 bne.w 8001b74 + __HAL_RCC_UART5_CLK_ENABLE(); + 80019f4: 2300 movs r3, #0 + 80019f6: 623b str r3, [r7, #32] + 80019f8: 4b57 ldr r3, [pc, #348] @ (8001b58 ) + 80019fa: 6c1b ldr r3, [r3, #64] @ 0x40 + 80019fc: 4a56 ldr r2, [pc, #344] @ (8001b58 ) + 80019fe: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 8001a02: 6413 str r3, [r2, #64] @ 0x40 + 8001a04: 4b54 ldr r3, [pc, #336] @ (8001b58 ) + 8001a06: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001a08: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8001a0c: 623b str r3, [r7, #32] + 8001a0e: 6a3b ldr r3, [r7, #32] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8001a10: 2300 movs r3, #0 + 8001a12: 61fb str r3, [r7, #28] + 8001a14: 4b50 ldr r3, [pc, #320] @ (8001b58 ) + 8001a16: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001a18: 4a4f ldr r2, [pc, #316] @ (8001b58 ) + 8001a1a: f043 0304 orr.w r3, r3, #4 + 8001a1e: 6313 str r3, [r2, #48] @ 0x30 + 8001a20: 4b4d ldr r3, [pc, #308] @ (8001b58 ) + 8001a22: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001a24: f003 0304 and.w r3, r3, #4 + 8001a28: 61fb str r3, [r7, #28] + 8001a2a: 69fb ldr r3, [r7, #28] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8001a2c: 2300 movs r3, #0 + 8001a2e: 61bb str r3, [r7, #24] + 8001a30: 4b49 ldr r3, [pc, #292] @ (8001b58 ) + 8001a32: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001a34: 4a48 ldr r2, [pc, #288] @ (8001b58 ) + 8001a36: f043 0308 orr.w r3, r3, #8 + 8001a3a: 6313 str r3, [r2, #48] @ 0x30 + 8001a3c: 4b46 ldr r3, [pc, #280] @ (8001b58 ) + 8001a3e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001a40: f003 0308 and.w r3, r3, #8 + 8001a44: 61bb str r3, [r7, #24] + 8001a46: 69bb ldr r3, [r7, #24] + GPIO_InitStruct.Pin = GPIO_PIN_12; + 8001a48: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8001a4c: 62fb str r3, [r7, #44] @ 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001a4e: 2302 movs r3, #2 + 8001a50: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001a52: 2300 movs r3, #0 + 8001a54: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001a56: 2303 movs r3, #3 + 8001a58: 63bb str r3, [r7, #56] @ 0x38 + GPIO_InitStruct.Alternate = GPIO_AF8_UART5; + 8001a5a: 2308 movs r3, #8 + 8001a5c: 63fb str r3, [r7, #60] @ 0x3c + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8001a5e: f107 032c add.w r3, r7, #44 @ 0x2c + 8001a62: 4619 mov r1, r3 + 8001a64: 483d ldr r0, [pc, #244] @ (8001b5c ) + 8001a66: f000 ffa3 bl 80029b0 + GPIO_InitStruct.Pin = GPIO_PIN_2; + 8001a6a: 2304 movs r3, #4 + 8001a6c: 62fb str r3, [r7, #44] @ 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001a6e: 2302 movs r3, #2 + 8001a70: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001a72: 2300 movs r3, #0 + 8001a74: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001a76: 2303 movs r3, #3 + 8001a78: 63bb str r3, [r7, #56] @ 0x38 + GPIO_InitStruct.Alternate = GPIO_AF8_UART5; + 8001a7a: 2308 movs r3, #8 + 8001a7c: 63fb str r3, [r7, #60] @ 0x3c + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8001a7e: f107 032c add.w r3, r7, #44 @ 0x2c + 8001a82: 4619 mov r1, r3 + 8001a84: 4836 ldr r0, [pc, #216] @ (8001b60 ) + 8001a86: f000 ff93 bl 80029b0 + hdma_uart5_rx.Instance = DMA1_Stream0; + 8001a8a: 4b36 ldr r3, [pc, #216] @ (8001b64 ) + 8001a8c: 4a36 ldr r2, [pc, #216] @ (8001b68 ) + 8001a8e: 601a str r2, [r3, #0] + hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; + 8001a90: 4b34 ldr r3, [pc, #208] @ (8001b64 ) + 8001a92: f04f 6200 mov.w r2, #134217728 @ 0x8000000 + 8001a96: 605a str r2, [r3, #4] + hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + 8001a98: 4b32 ldr r3, [pc, #200] @ (8001b64 ) + 8001a9a: 2200 movs r2, #0 + 8001a9c: 609a str r2, [r3, #8] + hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; + 8001a9e: 4b31 ldr r3, [pc, #196] @ (8001b64 ) + 8001aa0: 2200 movs r2, #0 + 8001aa2: 60da str r2, [r3, #12] + hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; + 8001aa4: 4b2f ldr r3, [pc, #188] @ (8001b64 ) + 8001aa6: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001aaa: 611a str r2, [r3, #16] + hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 8001aac: 4b2d ldr r3, [pc, #180] @ (8001b64 ) + 8001aae: 2200 movs r2, #0 + 8001ab0: 615a str r2, [r3, #20] + hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 8001ab2: 4b2c ldr r3, [pc, #176] @ (8001b64 ) + 8001ab4: 2200 movs r2, #0 + 8001ab6: 619a str r2, [r3, #24] + hdma_uart5_rx.Init.Mode = DMA_NORMAL; + 8001ab8: 4b2a ldr r3, [pc, #168] @ (8001b64 ) + 8001aba: 2200 movs r2, #0 + 8001abc: 61da str r2, [r3, #28] + hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; + 8001abe: 4b29 ldr r3, [pc, #164] @ (8001b64 ) + 8001ac0: 2200 movs r2, #0 + 8001ac2: 621a str r2, [r3, #32] + hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + 8001ac4: 4b27 ldr r3, [pc, #156] @ (8001b64 ) + 8001ac6: 2200 movs r2, #0 + 8001ac8: 625a str r2, [r3, #36] @ 0x24 + if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) + 8001aca: 4826 ldr r0, [pc, #152] @ (8001b64 ) + 8001acc: f000 fb6e bl 80021ac + 8001ad0: 4603 mov r3, r0 + 8001ad2: 2b00 cmp r3, #0 + 8001ad4: d001 beq.n 8001ada + Error_Handler(); + 8001ad6: f7ff fbb7 bl 8001248 + __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); + 8001ada: 687b ldr r3, [r7, #4] + 8001adc: 4a21 ldr r2, [pc, #132] @ (8001b64 ) + 8001ade: 63da str r2, [r3, #60] @ 0x3c + 8001ae0: 4a20 ldr r2, [pc, #128] @ (8001b64 ) + 8001ae2: 687b ldr r3, [r7, #4] + 8001ae4: 6393 str r3, [r2, #56] @ 0x38 + hdma_uart5_tx.Instance = DMA1_Stream7; + 8001ae6: 4b21 ldr r3, [pc, #132] @ (8001b6c ) + 8001ae8: 4a21 ldr r2, [pc, #132] @ (8001b70 ) + 8001aea: 601a str r2, [r3, #0] + hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; + 8001aec: 4b1f ldr r3, [pc, #124] @ (8001b6c ) + 8001aee: f04f 6200 mov.w r2, #134217728 @ 0x8000000 + 8001af2: 605a str r2, [r3, #4] + hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + 8001af4: 4b1d ldr r3, [pc, #116] @ (8001b6c ) + 8001af6: 2240 movs r2, #64 @ 0x40 + 8001af8: 609a str r2, [r3, #8] + hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; + 8001afa: 4b1c ldr r3, [pc, #112] @ (8001b6c ) + 8001afc: 2200 movs r2, #0 + 8001afe: 60da str r2, [r3, #12] + hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; + 8001b00: 4b1a ldr r3, [pc, #104] @ (8001b6c ) + 8001b02: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001b06: 611a str r2, [r3, #16] + hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 8001b08: 4b18 ldr r3, [pc, #96] @ (8001b6c ) + 8001b0a: 2200 movs r2, #0 + 8001b0c: 615a str r2, [r3, #20] + hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 8001b0e: 4b17 ldr r3, [pc, #92] @ (8001b6c ) + 8001b10: 2200 movs r2, #0 + 8001b12: 619a str r2, [r3, #24] + hdma_uart5_tx.Init.Mode = DMA_NORMAL; + 8001b14: 4b15 ldr r3, [pc, #84] @ (8001b6c ) + 8001b16: 2200 movs r2, #0 + 8001b18: 61da str r2, [r3, #28] + hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; + 8001b1a: 4b14 ldr r3, [pc, #80] @ (8001b6c ) + 8001b1c: 2200 movs r2, #0 + 8001b1e: 621a str r2, [r3, #32] + hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + 8001b20: 4b12 ldr r3, [pc, #72] @ (8001b6c ) + 8001b22: 2200 movs r2, #0 + 8001b24: 625a str r2, [r3, #36] @ 0x24 + if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) + 8001b26: 4811 ldr r0, [pc, #68] @ (8001b6c ) + 8001b28: f000 fb40 bl 80021ac + 8001b2c: 4603 mov r3, r0 + 8001b2e: 2b00 cmp r3, #0 + 8001b30: d001 beq.n 8001b36 + Error_Handler(); + 8001b32: f7ff fb89 bl 8001248 + __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); + 8001b36: 687b ldr r3, [r7, #4] + 8001b38: 4a0c ldr r2, [pc, #48] @ (8001b6c ) + 8001b3a: 639a str r2, [r3, #56] @ 0x38 + 8001b3c: 4a0b ldr r2, [pc, #44] @ (8001b6c ) + 8001b3e: 687b ldr r3, [r7, #4] + 8001b40: 6393 str r3, [r2, #56] @ 0x38 + HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); + 8001b42: 2200 movs r2, #0 + 8001b44: 2105 movs r1, #5 + 8001b46: 2035 movs r0, #53 @ 0x35 + 8001b48: f000 faf9 bl 800213e + HAL_NVIC_EnableIRQ(UART5_IRQn); + 8001b4c: 2035 movs r0, #53 @ 0x35 + 8001b4e: f000 fb12 bl 8002176 +} + 8001b52: e13d b.n 8001dd0 + 8001b54: 40005000 .word 0x40005000 + 8001b58: 40023800 .word 0x40023800 + 8001b5c: 40020800 .word 0x40020800 + 8001b60: 40020c00 .word 0x40020c00 + 8001b64: 20000b40 .word 0x20000b40 + 8001b68: 40026010 .word 0x40026010 + 8001b6c: 20000ba0 .word 0x20000ba0 + 8001b70: 400260b8 .word 0x400260b8 + else if(uartHandle->Instance==USART1) + 8001b74: 687b ldr r3, [r7, #4] + 8001b76: 681b ldr r3, [r3, #0] + 8001b78: 4a97 ldr r2, [pc, #604] @ (8001dd8 ) + 8001b7a: 4293 cmp r3, r2 + 8001b7c: f040 8092 bne.w 8001ca4 + __HAL_RCC_USART1_CLK_ENABLE(); + 8001b80: 2300 movs r3, #0 + 8001b82: 617b str r3, [r7, #20] + 8001b84: 4b95 ldr r3, [pc, #596] @ (8001ddc ) + 8001b86: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001b88: 4a94 ldr r2, [pc, #592] @ (8001ddc ) + 8001b8a: f043 0310 orr.w r3, r3, #16 + 8001b8e: 6453 str r3, [r2, #68] @ 0x44 + 8001b90: 4b92 ldr r3, [pc, #584] @ (8001ddc ) + 8001b92: 6c5b ldr r3, [r3, #68] @ 0x44 + 8001b94: f003 0310 and.w r3, r3, #16 + 8001b98: 617b str r3, [r7, #20] + 8001b9a: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001b9c: 2300 movs r3, #0 + 8001b9e: 613b str r3, [r7, #16] + 8001ba0: 4b8e ldr r3, [pc, #568] @ (8001ddc ) + 8001ba2: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001ba4: 4a8d ldr r2, [pc, #564] @ (8001ddc ) + 8001ba6: f043 0301 orr.w r3, r3, #1 + 8001baa: 6313 str r3, [r2, #48] @ 0x30 + 8001bac: 4b8b ldr r3, [pc, #556] @ (8001ddc ) + 8001bae: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001bb0: f003 0301 and.w r3, r3, #1 + 8001bb4: 613b str r3, [r7, #16] + 8001bb6: 693b ldr r3, [r7, #16] + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + 8001bb8: f44f 63c0 mov.w r3, #1536 @ 0x600 + 8001bbc: 62fb str r3, [r7, #44] @ 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001bbe: 2302 movs r3, #2 + 8001bc0: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001bc2: 2300 movs r3, #0 + 8001bc4: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001bc6: 2303 movs r3, #3 + 8001bc8: 63bb str r3, [r7, #56] @ 0x38 + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + 8001bca: 2307 movs r3, #7 + 8001bcc: 63fb str r3, [r7, #60] @ 0x3c + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001bce: f107 032c add.w r3, r7, #44 @ 0x2c + 8001bd2: 4619 mov r1, r3 + 8001bd4: 4882 ldr r0, [pc, #520] @ (8001de0 ) + 8001bd6: f000 feeb bl 80029b0 + hdma_usart1_rx.Instance = DMA2_Stream2; + 8001bda: 4b82 ldr r3, [pc, #520] @ (8001de4 ) + 8001bdc: 4a82 ldr r2, [pc, #520] @ (8001de8 ) + 8001bde: 601a str r2, [r3, #0] + hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; + 8001be0: 4b80 ldr r3, [pc, #512] @ (8001de4 ) + 8001be2: f04f 6200 mov.w r2, #134217728 @ 0x8000000 + 8001be6: 605a str r2, [r3, #4] + hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + 8001be8: 4b7e ldr r3, [pc, #504] @ (8001de4 ) + 8001bea: 2200 movs r2, #0 + 8001bec: 609a str r2, [r3, #8] + hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; + 8001bee: 4b7d ldr r3, [pc, #500] @ (8001de4 ) + 8001bf0: 2200 movs r2, #0 + 8001bf2: 60da str r2, [r3, #12] + hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; + 8001bf4: 4b7b ldr r3, [pc, #492] @ (8001de4 ) + 8001bf6: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001bfa: 611a str r2, [r3, #16] + hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 8001bfc: 4b79 ldr r3, [pc, #484] @ (8001de4 ) + 8001bfe: 2200 movs r2, #0 + 8001c00: 615a str r2, [r3, #20] + hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 8001c02: 4b78 ldr r3, [pc, #480] @ (8001de4 ) + 8001c04: 2200 movs r2, #0 + 8001c06: 619a str r2, [r3, #24] + hdma_usart1_rx.Init.Mode = DMA_NORMAL; + 8001c08: 4b76 ldr r3, [pc, #472] @ (8001de4 ) + 8001c0a: 2200 movs r2, #0 + 8001c0c: 61da str r2, [r3, #28] + hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; + 8001c0e: 4b75 ldr r3, [pc, #468] @ (8001de4 ) + 8001c10: 2200 movs r2, #0 + 8001c12: 621a str r2, [r3, #32] + hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + 8001c14: 4b73 ldr r3, [pc, #460] @ (8001de4 ) + 8001c16: 2200 movs r2, #0 + 8001c18: 625a str r2, [r3, #36] @ 0x24 + if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) + 8001c1a: 4872 ldr r0, [pc, #456] @ (8001de4 ) + 8001c1c: f000 fac6 bl 80021ac + 8001c20: 4603 mov r3, r0 + 8001c22: 2b00 cmp r3, #0 + 8001c24: d001 beq.n 8001c2a + Error_Handler(); + 8001c26: f7ff fb0f bl 8001248 + __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); + 8001c2a: 687b ldr r3, [r7, #4] + 8001c2c: 4a6d ldr r2, [pc, #436] @ (8001de4 ) + 8001c2e: 63da str r2, [r3, #60] @ 0x3c + 8001c30: 4a6c ldr r2, [pc, #432] @ (8001de4 ) + 8001c32: 687b ldr r3, [r7, #4] + 8001c34: 6393 str r3, [r2, #56] @ 0x38 + hdma_usart1_tx.Instance = DMA2_Stream7; + 8001c36: 4b6d ldr r3, [pc, #436] @ (8001dec ) + 8001c38: 4a6d ldr r2, [pc, #436] @ (8001df0 ) + 8001c3a: 601a str r2, [r3, #0] + hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; + 8001c3c: 4b6b ldr r3, [pc, #428] @ (8001dec ) + 8001c3e: f04f 6200 mov.w r2, #134217728 @ 0x8000000 + 8001c42: 605a str r2, [r3, #4] + hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + 8001c44: 4b69 ldr r3, [pc, #420] @ (8001dec ) + 8001c46: 2240 movs r2, #64 @ 0x40 + 8001c48: 609a str r2, [r3, #8] + hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; + 8001c4a: 4b68 ldr r3, [pc, #416] @ (8001dec ) + 8001c4c: 2200 movs r2, #0 + 8001c4e: 60da str r2, [r3, #12] + hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; + 8001c50: 4b66 ldr r3, [pc, #408] @ (8001dec ) + 8001c52: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001c56: 611a str r2, [r3, #16] + hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 8001c58: 4b64 ldr r3, [pc, #400] @ (8001dec ) + 8001c5a: 2200 movs r2, #0 + 8001c5c: 615a str r2, [r3, #20] + hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 8001c5e: 4b63 ldr r3, [pc, #396] @ (8001dec ) + 8001c60: 2200 movs r2, #0 + 8001c62: 619a str r2, [r3, #24] + hdma_usart1_tx.Init.Mode = DMA_NORMAL; + 8001c64: 4b61 ldr r3, [pc, #388] @ (8001dec ) + 8001c66: 2200 movs r2, #0 + 8001c68: 61da str r2, [r3, #28] + hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; + 8001c6a: 4b60 ldr r3, [pc, #384] @ (8001dec ) + 8001c6c: 2200 movs r2, #0 + 8001c6e: 621a str r2, [r3, #32] + hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + 8001c70: 4b5e ldr r3, [pc, #376] @ (8001dec ) + 8001c72: 2200 movs r2, #0 + 8001c74: 625a str r2, [r3, #36] @ 0x24 + if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) + 8001c76: 485d ldr r0, [pc, #372] @ (8001dec ) + 8001c78: f000 fa98 bl 80021ac + 8001c7c: 4603 mov r3, r0 + 8001c7e: 2b00 cmp r3, #0 + 8001c80: d001 beq.n 8001c86 + Error_Handler(); + 8001c82: f7ff fae1 bl 8001248 + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); + 8001c86: 687b ldr r3, [r7, #4] + 8001c88: 4a58 ldr r2, [pc, #352] @ (8001dec ) + 8001c8a: 639a str r2, [r3, #56] @ 0x38 + 8001c8c: 4a57 ldr r2, [pc, #348] @ (8001dec ) + 8001c8e: 687b ldr r3, [r7, #4] + 8001c90: 6393 str r3, [r2, #56] @ 0x38 + HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); + 8001c92: 2200 movs r2, #0 + 8001c94: 2105 movs r1, #5 + 8001c96: 2025 movs r0, #37 @ 0x25 + 8001c98: f000 fa51 bl 800213e + HAL_NVIC_EnableIRQ(USART1_IRQn); + 8001c9c: 2025 movs r0, #37 @ 0x25 + 8001c9e: f000 fa6a bl 8002176 +} + 8001ca2: e095 b.n 8001dd0 + else if(uartHandle->Instance==USART2) + 8001ca4: 687b ldr r3, [r7, #4] + 8001ca6: 681b ldr r3, [r3, #0] + 8001ca8: 4a52 ldr r2, [pc, #328] @ (8001df4 ) + 8001caa: 4293 cmp r3, r2 + 8001cac: f040 8090 bne.w 8001dd0 + __HAL_RCC_USART2_CLK_ENABLE(); + 8001cb0: 2300 movs r3, #0 + 8001cb2: 60fb str r3, [r7, #12] + 8001cb4: 4b49 ldr r3, [pc, #292] @ (8001ddc ) + 8001cb6: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001cb8: 4a48 ldr r2, [pc, #288] @ (8001ddc ) + 8001cba: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8001cbe: 6413 str r3, [r2, #64] @ 0x40 + 8001cc0: 4b46 ldr r3, [pc, #280] @ (8001ddc ) + 8001cc2: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001cc4: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001cc8: 60fb str r3, [r7, #12] + 8001cca: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001ccc: 2300 movs r3, #0 + 8001cce: 60bb str r3, [r7, #8] + 8001cd0: 4b42 ldr r3, [pc, #264] @ (8001ddc ) + 8001cd2: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001cd4: 4a41 ldr r2, [pc, #260] @ (8001ddc ) + 8001cd6: f043 0301 orr.w r3, r3, #1 + 8001cda: 6313 str r3, [r2, #48] @ 0x30 + 8001cdc: 4b3f ldr r3, [pc, #252] @ (8001ddc ) + 8001cde: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001ce0: f003 0301 and.w r3, r3, #1 + 8001ce4: 60bb str r3, [r7, #8] + 8001ce6: 68bb ldr r3, [r7, #8] + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + 8001ce8: 230c movs r3, #12 + 8001cea: 62fb str r3, [r7, #44] @ 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001cec: 2302 movs r3, #2 + 8001cee: 633b str r3, [r7, #48] @ 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001cf0: 2300 movs r3, #0 + 8001cf2: 637b str r3, [r7, #52] @ 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001cf4: 2303 movs r3, #3 + 8001cf6: 63bb str r3, [r7, #56] @ 0x38 + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + 8001cf8: 2307 movs r3, #7 + 8001cfa: 63fb str r3, [r7, #60] @ 0x3c + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001cfc: f107 032c add.w r3, r7, #44 @ 0x2c + 8001d00: 4619 mov r1, r3 + 8001d02: 4837 ldr r0, [pc, #220] @ (8001de0 ) + 8001d04: f000 fe54 bl 80029b0 + hdma_usart2_rx.Instance = DMA1_Stream5; + 8001d08: 4b3b ldr r3, [pc, #236] @ (8001df8 ) + 8001d0a: 4a3c ldr r2, [pc, #240] @ (8001dfc ) + 8001d0c: 601a str r2, [r3, #0] + hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; + 8001d0e: 4b3a ldr r3, [pc, #232] @ (8001df8 ) + 8001d10: f04f 6200 mov.w r2, #134217728 @ 0x8000000 + 8001d14: 605a str r2, [r3, #4] + hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + 8001d16: 4b38 ldr r3, [pc, #224] @ (8001df8 ) + 8001d18: 2200 movs r2, #0 + 8001d1a: 609a str r2, [r3, #8] + hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; + 8001d1c: 4b36 ldr r3, [pc, #216] @ (8001df8 ) + 8001d1e: 2200 movs r2, #0 + 8001d20: 60da str r2, [r3, #12] + hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; + 8001d22: 4b35 ldr r3, [pc, #212] @ (8001df8 ) + 8001d24: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001d28: 611a str r2, [r3, #16] + hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 8001d2a: 4b33 ldr r3, [pc, #204] @ (8001df8 ) + 8001d2c: 2200 movs r2, #0 + 8001d2e: 615a str r2, [r3, #20] + hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 8001d30: 4b31 ldr r3, [pc, #196] @ (8001df8 ) + 8001d32: 2200 movs r2, #0 + 8001d34: 619a str r2, [r3, #24] + hdma_usart2_rx.Init.Mode = DMA_NORMAL; + 8001d36: 4b30 ldr r3, [pc, #192] @ (8001df8 ) + 8001d38: 2200 movs r2, #0 + 8001d3a: 61da str r2, [r3, #28] + hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; + 8001d3c: 4b2e ldr r3, [pc, #184] @ (8001df8 ) + 8001d3e: 2200 movs r2, #0 + 8001d40: 621a str r2, [r3, #32] + hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + 8001d42: 4b2d ldr r3, [pc, #180] @ (8001df8 ) + 8001d44: 2200 movs r2, #0 + 8001d46: 625a str r2, [r3, #36] @ 0x24 + if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) + 8001d48: 482b ldr r0, [pc, #172] @ (8001df8 ) + 8001d4a: f000 fa2f bl 80021ac + 8001d4e: 4603 mov r3, r0 + 8001d50: 2b00 cmp r3, #0 + 8001d52: d001 beq.n 8001d58 + Error_Handler(); + 8001d54: f7ff fa78 bl 8001248 + __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); + 8001d58: 687b ldr r3, [r7, #4] + 8001d5a: 4a27 ldr r2, [pc, #156] @ (8001df8 ) + 8001d5c: 63da str r2, [r3, #60] @ 0x3c + 8001d5e: 4a26 ldr r2, [pc, #152] @ (8001df8 ) + 8001d60: 687b ldr r3, [r7, #4] + 8001d62: 6393 str r3, [r2, #56] @ 0x38 + hdma_usart2_tx.Instance = DMA1_Stream6; + 8001d64: 4b26 ldr r3, [pc, #152] @ (8001e00 ) + 8001d66: 4a27 ldr r2, [pc, #156] @ (8001e04 ) + 8001d68: 601a str r2, [r3, #0] + hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; + 8001d6a: 4b25 ldr r3, [pc, #148] @ (8001e00 ) + 8001d6c: f04f 6200 mov.w r2, #134217728 @ 0x8000000 + 8001d70: 605a str r2, [r3, #4] + hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + 8001d72: 4b23 ldr r3, [pc, #140] @ (8001e00 ) + 8001d74: 2240 movs r2, #64 @ 0x40 + 8001d76: 609a str r2, [r3, #8] + hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + 8001d78: 4b21 ldr r3, [pc, #132] @ (8001e00 ) + 8001d7a: 2200 movs r2, #0 + 8001d7c: 60da str r2, [r3, #12] + hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; + 8001d7e: 4b20 ldr r3, [pc, #128] @ (8001e00 ) + 8001d80: f44f 6280 mov.w r2, #1024 @ 0x400 + 8001d84: 611a str r2, [r3, #16] + hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 8001d86: 4b1e ldr r3, [pc, #120] @ (8001e00 ) + 8001d88: 2200 movs r2, #0 + 8001d8a: 615a str r2, [r3, #20] + hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 8001d8c: 4b1c ldr r3, [pc, #112] @ (8001e00 ) + 8001d8e: 2200 movs r2, #0 + 8001d90: 619a str r2, [r3, #24] + hdma_usart2_tx.Init.Mode = DMA_NORMAL; + 8001d92: 4b1b ldr r3, [pc, #108] @ (8001e00 ) + 8001d94: 2200 movs r2, #0 + 8001d96: 61da str r2, [r3, #28] + hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; + 8001d98: 4b19 ldr r3, [pc, #100] @ (8001e00 ) + 8001d9a: 2200 movs r2, #0 + 8001d9c: 621a str r2, [r3, #32] + hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + 8001d9e: 4b18 ldr r3, [pc, #96] @ (8001e00 ) + 8001da0: 2200 movs r2, #0 + 8001da2: 625a str r2, [r3, #36] @ 0x24 + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + 8001da4: 4816 ldr r0, [pc, #88] @ (8001e00 ) + 8001da6: f000 fa01 bl 80021ac + 8001daa: 4603 mov r3, r0 + 8001dac: 2b00 cmp r3, #0 + 8001dae: d001 beq.n 8001db4 + Error_Handler(); + 8001db0: f7ff fa4a bl 8001248 + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); + 8001db4: 687b ldr r3, [r7, #4] + 8001db6: 4a12 ldr r2, [pc, #72] @ (8001e00 ) + 8001db8: 639a str r2, [r3, #56] @ 0x38 + 8001dba: 4a11 ldr r2, [pc, #68] @ (8001e00 ) + 8001dbc: 687b ldr r3, [r7, #4] + 8001dbe: 6393 str r3, [r2, #56] @ 0x38 + HAL_NVIC_SetPriority(USART2_IRQn, 5, 0); + 8001dc0: 2200 movs r2, #0 + 8001dc2: 2105 movs r1, #5 + 8001dc4: 2026 movs r0, #38 @ 0x26 + 8001dc6: f000 f9ba bl 800213e + HAL_NVIC_EnableIRQ(USART2_IRQn); + 8001dca: 2026 movs r0, #38 @ 0x26 + 8001dcc: f000 f9d3 bl 8002176 +} + 8001dd0: bf00 nop + 8001dd2: 3740 adds r7, #64 @ 0x40 + 8001dd4: 46bd mov sp, r7 + 8001dd6: bd80 pop {r7, pc} + 8001dd8: 40011000 .word 0x40011000 + 8001ddc: 40023800 .word 0x40023800 + 8001de0: 40020000 .word 0x40020000 + 8001de4: 20000c00 .word 0x20000c00 + 8001de8: 40026440 .word 0x40026440 + 8001dec: 20000c60 .word 0x20000c60 + 8001df0: 400264b8 .word 0x400264b8 + 8001df4: 40004400 .word 0x40004400 + 8001df8: 20000cc0 .word 0x20000cc0 + 8001dfc: 40026088 .word 0x40026088 + 8001e00: 20000d20 .word 0x20000d20 + 8001e04: 400260a0 .word 0x400260a0 + +08001e08 : + 8001e08: f8df d034 ldr.w sp, [pc, #52] @ 8001e40 + 8001e0c: f7ff fb34 bl 8001478 + 8001e10: 480c ldr r0, [pc, #48] @ (8001e44 ) + 8001e12: 490d ldr r1, [pc, #52] @ (8001e48 ) + 8001e14: 4a0d ldr r2, [pc, #52] @ (8001e4c ) + 8001e16: 2300 movs r3, #0 + 8001e18: e002 b.n 8001e20 + +08001e1a : + 8001e1a: 58d4 ldr r4, [r2, r3] + 8001e1c: 50c4 str r4, [r0, r3] + 8001e1e: 3304 adds r3, #4 + +08001e20 : + 8001e20: 18c4 adds r4, r0, r3 + 8001e22: 428c cmp r4, r1 + 8001e24: d3f9 bcc.n 8001e1a + 8001e26: 4a0a ldr r2, [pc, #40] @ (8001e50 ) + 8001e28: 4c0a ldr r4, [pc, #40] @ (8001e54 ) + 8001e2a: 2300 movs r3, #0 + 8001e2c: e001 b.n 8001e32 + +08001e2e : + 8001e2e: 6013 str r3, [r2, #0] + 8001e30: 3204 adds r2, #4 + +08001e32 : + 8001e32: 42a2 cmp r2, r4 + 8001e34: d3fb bcc.n 8001e2e + 8001e36: f009 fa93 bl 800b360 <__libc_init_array> + 8001e3a: f7fe fd75 bl 8000928
+ 8001e3e: 4770 bx lr + 8001e40: 20020000 .word 0x20020000 + 8001e44: 20000000 .word 0x20000000 + 8001e48: 200001a0 .word 0x200001a0 + 8001e4c: 0800b448 .word 0x0800b448 + 8001e50: 200001a0 .word 0x200001a0 + 8001e54: 2000175c .word 0x2000175c + +08001e58 : + 8001e58: e7fe b.n 8001e58 + ... + +08001e5c : + 8001e5c: b580 push {r7, lr} + 8001e5e: af00 add r7, sp, #0 + 8001e60: 4b0e ldr r3, [pc, #56] @ (8001e9c ) + 8001e62: 681b ldr r3, [r3, #0] + 8001e64: 4a0d ldr r2, [pc, #52] @ (8001e9c ) + 8001e66: f443 7300 orr.w r3, r3, #512 @ 0x200 + 8001e6a: 6013 str r3, [r2, #0] + 8001e6c: 4b0b ldr r3, [pc, #44] @ (8001e9c ) + 8001e6e: 681b ldr r3, [r3, #0] + 8001e70: 4a0a ldr r2, [pc, #40] @ (8001e9c ) + 8001e72: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 8001e76: 6013 str r3, [r2, #0] + 8001e78: 4b08 ldr r3, [pc, #32] @ (8001e9c ) + 8001e7a: 681b ldr r3, [r3, #0] + 8001e7c: 4a07 ldr r2, [pc, #28] @ (8001e9c ) + 8001e7e: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001e82: 6013 str r3, [r2, #0] + 8001e84: 2003 movs r0, #3 + 8001e86: f000 f94f bl 8002128 + 8001e8a: 200f movs r0, #15 + 8001e8c: f000 f808 bl 8001ea0 + 8001e90: f7ff fa18 bl 80012c4 + 8001e94: 2300 movs r3, #0 + 8001e96: 4618 mov r0, r3 + 8001e98: bd80 pop {r7, pc} + 8001e9a: bf00 nop + 8001e9c: 40023c00 .word 0x40023c00 + +08001ea0 : + 8001ea0: b580 push {r7, lr} + 8001ea2: b082 sub sp, #8 + 8001ea4: af00 add r7, sp, #0 + 8001ea6: 6078 str r0, [r7, #4] + 8001ea8: 4b12 ldr r3, [pc, #72] @ (8001ef4 ) + 8001eaa: 681a ldr r2, [r3, #0] + 8001eac: 4b12 ldr r3, [pc, #72] @ (8001ef8 ) + 8001eae: 781b ldrb r3, [r3, #0] + 8001eb0: 4619 mov r1, r3 + 8001eb2: f44f 737a mov.w r3, #1000 @ 0x3e8 + 8001eb6: fbb3 f3f1 udiv r3, r3, r1 + 8001eba: fbb2 f3f3 udiv r3, r2, r3 + 8001ebe: 4618 mov r0, r3 + 8001ec0: f000 f967 bl 8002192 + 8001ec4: 4603 mov r3, r0 + 8001ec6: 2b00 cmp r3, #0 + 8001ec8: d001 beq.n 8001ece + 8001eca: 2301 movs r3, #1 + 8001ecc: e00e b.n 8001eec + 8001ece: 687b ldr r3, [r7, #4] + 8001ed0: 2b0f cmp r3, #15 + 8001ed2: d80a bhi.n 8001eea + 8001ed4: 2200 movs r2, #0 + 8001ed6: 6879 ldr r1, [r7, #4] + 8001ed8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8001edc: f000 f92f bl 800213e + 8001ee0: 4a06 ldr r2, [pc, #24] @ (8001efc ) + 8001ee2: 687b ldr r3, [r7, #4] + 8001ee4: 6013 str r3, [r2, #0] + 8001ee6: 2300 movs r3, #0 + 8001ee8: e000 b.n 8001eec + 8001eea: 2301 movs r3, #1 + 8001eec: 4618 mov r0, r3 + 8001eee: 3708 adds r7, #8 + 8001ef0: 46bd mov sp, r7 + 8001ef2: bd80 pop {r7, pc} + 8001ef4: 20000090 .word 0x20000090 + 8001ef8: 20000098 .word 0x20000098 + 8001efc: 20000094 .word 0x20000094 + +08001f00 : + 8001f00: b480 push {r7} + 8001f02: af00 add r7, sp, #0 + 8001f04: 4b06 ldr r3, [pc, #24] @ (8001f20 ) + 8001f06: 781b ldrb r3, [r3, #0] + 8001f08: 461a mov r2, r3 + 8001f0a: 4b06 ldr r3, [pc, #24] @ (8001f24 ) + 8001f0c: 681b ldr r3, [r3, #0] + 8001f0e: 4413 add r3, r2 + 8001f10: 4a04 ldr r2, [pc, #16] @ (8001f24 ) + 8001f12: 6013 str r3, [r2, #0] + 8001f14: bf00 nop + 8001f16: 46bd mov sp, r7 + 8001f18: f85d 7b04 ldr.w r7, [sp], #4 + 8001f1c: 4770 bx lr + 8001f1e: bf00 nop + 8001f20: 20000098 .word 0x20000098 + 8001f24: 20000d80 .word 0x20000d80 + +08001f28 : + 8001f28: b480 push {r7} + 8001f2a: af00 add r7, sp, #0 + 8001f2c: 4b03 ldr r3, [pc, #12] @ (8001f3c ) + 8001f2e: 681b ldr r3, [r3, #0] + 8001f30: 4618 mov r0, r3 + 8001f32: 46bd mov sp, r7 + 8001f34: f85d 7b04 ldr.w r7, [sp], #4 + 8001f38: 4770 bx lr + 8001f3a: bf00 nop + 8001f3c: 20000d80 .word 0x20000d80 + +08001f40 : + 8001f40: b580 push {r7, lr} + 8001f42: b084 sub sp, #16 + 8001f44: af00 add r7, sp, #0 + 8001f46: 6078 str r0, [r7, #4] + 8001f48: f7ff ffee bl 8001f28 + 8001f4c: 60b8 str r0, [r7, #8] + 8001f4e: 687b ldr r3, [r7, #4] + 8001f50: 60fb str r3, [r7, #12] + 8001f52: 68fb ldr r3, [r7, #12] + 8001f54: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001f58: d005 beq.n 8001f66 + 8001f5a: 4b0a ldr r3, [pc, #40] @ (8001f84 ) + 8001f5c: 781b ldrb r3, [r3, #0] + 8001f5e: 461a mov r2, r3 + 8001f60: 68fb ldr r3, [r7, #12] + 8001f62: 4413 add r3, r2 + 8001f64: 60fb str r3, [r7, #12] + 8001f66: bf00 nop + 8001f68: f7ff ffde bl 8001f28 + 8001f6c: 4602 mov r2, r0 + 8001f6e: 68bb ldr r3, [r7, #8] + 8001f70: 1ad3 subs r3, r2, r3 + 8001f72: 68fa ldr r2, [r7, #12] + 8001f74: 429a cmp r2, r3 + 8001f76: d8f7 bhi.n 8001f68 + 8001f78: bf00 nop + 8001f7a: bf00 nop + 8001f7c: 3710 adds r7, #16 + 8001f7e: 46bd mov sp, r7 + 8001f80: bd80 pop {r7, pc} + 8001f82: bf00 nop + 8001f84: 20000098 .word 0x20000098 + +08001f88 <__NVIC_SetPriorityGrouping>: + 8001f88: b480 push {r7} + 8001f8a: b085 sub sp, #20 + 8001f8c: af00 add r7, sp, #0 + 8001f8e: 6078 str r0, [r7, #4] + 8001f90: 687b ldr r3, [r7, #4] + 8001f92: f003 0307 and.w r3, r3, #7 + 8001f96: 60fb str r3, [r7, #12] + 8001f98: 4b0c ldr r3, [pc, #48] @ (8001fcc <__NVIC_SetPriorityGrouping+0x44>) + 8001f9a: 68db ldr r3, [r3, #12] + 8001f9c: 60bb str r3, [r7, #8] + 8001f9e: 68ba ldr r2, [r7, #8] + 8001fa0: f64f 03ff movw r3, #63743 @ 0xf8ff + 8001fa4: 4013 ands r3, r2 + 8001fa6: 60bb str r3, [r7, #8] + 8001fa8: 68fb ldr r3, [r7, #12] + 8001faa: 021a lsls r2, r3, #8 + 8001fac: 68bb ldr r3, [r7, #8] + 8001fae: 4313 orrs r3, r2 + 8001fb0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8001fb4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8001fb8: 60bb str r3, [r7, #8] + 8001fba: 4a04 ldr r2, [pc, #16] @ (8001fcc <__NVIC_SetPriorityGrouping+0x44>) + 8001fbc: 68bb ldr r3, [r7, #8] + 8001fbe: 60d3 str r3, [r2, #12] + 8001fc0: bf00 nop + 8001fc2: 3714 adds r7, #20 + 8001fc4: 46bd mov sp, r7 + 8001fc6: f85d 7b04 ldr.w r7, [sp], #4 + 8001fca: 4770 bx lr + 8001fcc: e000ed00 .word 0xe000ed00 + +08001fd0 <__NVIC_GetPriorityGrouping>: + 8001fd0: b480 push {r7} + 8001fd2: af00 add r7, sp, #0 + 8001fd4: 4b04 ldr r3, [pc, #16] @ (8001fe8 <__NVIC_GetPriorityGrouping+0x18>) + 8001fd6: 68db ldr r3, [r3, #12] + 8001fd8: 0a1b lsrs r3, r3, #8 + 8001fda: f003 0307 and.w r3, r3, #7 + 8001fde: 4618 mov r0, r3 + 8001fe0: 46bd mov sp, r7 + 8001fe2: f85d 7b04 ldr.w r7, [sp], #4 + 8001fe6: 4770 bx lr + 8001fe8: e000ed00 .word 0xe000ed00 + +08001fec <__NVIC_EnableIRQ>: + 8001fec: b480 push {r7} + 8001fee: b083 sub sp, #12 + 8001ff0: af00 add r7, sp, #0 + 8001ff2: 4603 mov r3, r0 + 8001ff4: 71fb strb r3, [r7, #7] + 8001ff6: f997 3007 ldrsb.w r3, [r7, #7] + 8001ffa: 2b00 cmp r3, #0 + 8001ffc: db0b blt.n 8002016 <__NVIC_EnableIRQ+0x2a> + 8001ffe: 79fb ldrb r3, [r7, #7] + 8002000: f003 021f and.w r2, r3, #31 + 8002004: 4907 ldr r1, [pc, #28] @ (8002024 <__NVIC_EnableIRQ+0x38>) + 8002006: f997 3007 ldrsb.w r3, [r7, #7] + 800200a: 095b lsrs r3, r3, #5 + 800200c: 2001 movs r0, #1 + 800200e: fa00 f202 lsl.w r2, r0, r2 + 8002012: f841 2023 str.w r2, [r1, r3, lsl #2] + 8002016: bf00 nop + 8002018: 370c adds r7, #12 + 800201a: 46bd mov sp, r7 + 800201c: f85d 7b04 ldr.w r7, [sp], #4 + 8002020: 4770 bx lr + 8002022: bf00 nop + 8002024: e000e100 .word 0xe000e100 + +08002028 <__NVIC_SetPriority>: + 8002028: b480 push {r7} + 800202a: b083 sub sp, #12 + 800202c: af00 add r7, sp, #0 + 800202e: 4603 mov r3, r0 + 8002030: 6039 str r1, [r7, #0] + 8002032: 71fb strb r3, [r7, #7] + 8002034: f997 3007 ldrsb.w r3, [r7, #7] + 8002038: 2b00 cmp r3, #0 + 800203a: db0a blt.n 8002052 <__NVIC_SetPriority+0x2a> + 800203c: 683b ldr r3, [r7, #0] + 800203e: b2da uxtb r2, r3 + 8002040: 490c ldr r1, [pc, #48] @ (8002074 <__NVIC_SetPriority+0x4c>) + 8002042: f997 3007 ldrsb.w r3, [r7, #7] + 8002046: 0112 lsls r2, r2, #4 + 8002048: b2d2 uxtb r2, r2 + 800204a: 440b add r3, r1 + 800204c: f883 2300 strb.w r2, [r3, #768] @ 0x300 + 8002050: e00a b.n 8002068 <__NVIC_SetPriority+0x40> + 8002052: 683b ldr r3, [r7, #0] + 8002054: b2da uxtb r2, r3 + 8002056: 4908 ldr r1, [pc, #32] @ (8002078 <__NVIC_SetPriority+0x50>) + 8002058: 79fb ldrb r3, [r7, #7] + 800205a: f003 030f and.w r3, r3, #15 + 800205e: 3b04 subs r3, #4 + 8002060: 0112 lsls r2, r2, #4 + 8002062: b2d2 uxtb r2, r2 + 8002064: 440b add r3, r1 + 8002066: 761a strb r2, [r3, #24] + 8002068: bf00 nop + 800206a: 370c adds r7, #12 + 800206c: 46bd mov sp, r7 + 800206e: f85d 7b04 ldr.w r7, [sp], #4 + 8002072: 4770 bx lr + 8002074: e000e100 .word 0xe000e100 + 8002078: e000ed00 .word 0xe000ed00 + +0800207c : + 800207c: b480 push {r7} + 800207e: b089 sub sp, #36 @ 0x24 + 8002080: af00 add r7, sp, #0 + 8002082: 60f8 str r0, [r7, #12] + 8002084: 60b9 str r1, [r7, #8] + 8002086: 607a str r2, [r7, #4] + 8002088: 68fb ldr r3, [r7, #12] + 800208a: f003 0307 and.w r3, r3, #7 + 800208e: 61fb str r3, [r7, #28] + 8002090: 69fb ldr r3, [r7, #28] + 8002092: f1c3 0307 rsb r3, r3, #7 + 8002096: 2b04 cmp r3, #4 + 8002098: bf28 it cs + 800209a: 2304 movcs r3, #4 + 800209c: 61bb str r3, [r7, #24] + 800209e: 69fb ldr r3, [r7, #28] + 80020a0: 3304 adds r3, #4 + 80020a2: 2b06 cmp r3, #6 + 80020a4: d902 bls.n 80020ac + 80020a6: 69fb ldr r3, [r7, #28] + 80020a8: 3b03 subs r3, #3 + 80020aa: e000 b.n 80020ae + 80020ac: 2300 movs r3, #0 + 80020ae: 617b str r3, [r7, #20] + 80020b0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 80020b4: 69bb ldr r3, [r7, #24] + 80020b6: fa02 f303 lsl.w r3, r2, r3 + 80020ba: 43da mvns r2, r3 + 80020bc: 68bb ldr r3, [r7, #8] + 80020be: 401a ands r2, r3 + 80020c0: 697b ldr r3, [r7, #20] + 80020c2: 409a lsls r2, r3 + 80020c4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 80020c8: 697b ldr r3, [r7, #20] + 80020ca: fa01 f303 lsl.w r3, r1, r3 + 80020ce: 43d9 mvns r1, r3 + 80020d0: 687b ldr r3, [r7, #4] + 80020d2: 400b ands r3, r1 + 80020d4: 4313 orrs r3, r2 + 80020d6: 4618 mov r0, r3 + 80020d8: 3724 adds r7, #36 @ 0x24 + 80020da: 46bd mov sp, r7 + 80020dc: f85d 7b04 ldr.w r7, [sp], #4 + 80020e0: 4770 bx lr + ... + +080020e4 : + 80020e4: b580 push {r7, lr} + 80020e6: b082 sub sp, #8 + 80020e8: af00 add r7, sp, #0 + 80020ea: 6078 str r0, [r7, #4] + 80020ec: 687b ldr r3, [r7, #4] + 80020ee: 3b01 subs r3, #1 + 80020f0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 80020f4: d301 bcc.n 80020fa + 80020f6: 2301 movs r3, #1 + 80020f8: e00f b.n 800211a + 80020fa: 4a0a ldr r2, [pc, #40] @ (8002124 ) + 80020fc: 687b ldr r3, [r7, #4] + 80020fe: 3b01 subs r3, #1 + 8002100: 6053 str r3, [r2, #4] + 8002102: 210f movs r1, #15 + 8002104: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8002108: f7ff ff8e bl 8002028 <__NVIC_SetPriority> + 800210c: 4b05 ldr r3, [pc, #20] @ (8002124 ) + 800210e: 2200 movs r2, #0 + 8002110: 609a str r2, [r3, #8] + 8002112: 4b04 ldr r3, [pc, #16] @ (8002124 ) + 8002114: 2207 movs r2, #7 + 8002116: 601a str r2, [r3, #0] + 8002118: 2300 movs r3, #0 + 800211a: 4618 mov r0, r3 + 800211c: 3708 adds r7, #8 + 800211e: 46bd mov sp, r7 + 8002120: bd80 pop {r7, pc} + 8002122: bf00 nop + 8002124: e000e010 .word 0xe000e010 + +08002128 : + 8002128: b580 push {r7, lr} + 800212a: b082 sub sp, #8 + 800212c: af00 add r7, sp, #0 + 800212e: 6078 str r0, [r7, #4] + 8002130: 6878 ldr r0, [r7, #4] + 8002132: f7ff ff29 bl 8001f88 <__NVIC_SetPriorityGrouping> + 8002136: bf00 nop + 8002138: 3708 adds r7, #8 + 800213a: 46bd mov sp, r7 + 800213c: bd80 pop {r7, pc} + +0800213e : + 800213e: b580 push {r7, lr} + 8002140: b086 sub sp, #24 + 8002142: af00 add r7, sp, #0 + 8002144: 4603 mov r3, r0 + 8002146: 60b9 str r1, [r7, #8] + 8002148: 607a str r2, [r7, #4] + 800214a: 73fb strb r3, [r7, #15] + 800214c: 2300 movs r3, #0 + 800214e: 617b str r3, [r7, #20] + 8002150: f7ff ff3e bl 8001fd0 <__NVIC_GetPriorityGrouping> + 8002154: 6178 str r0, [r7, #20] + 8002156: 687a ldr r2, [r7, #4] + 8002158: 68b9 ldr r1, [r7, #8] + 800215a: 6978 ldr r0, [r7, #20] + 800215c: f7ff ff8e bl 800207c + 8002160: 4602 mov r2, r0 + 8002162: f997 300f ldrsb.w r3, [r7, #15] + 8002166: 4611 mov r1, r2 + 8002168: 4618 mov r0, r3 + 800216a: f7ff ff5d bl 8002028 <__NVIC_SetPriority> + 800216e: bf00 nop + 8002170: 3718 adds r7, #24 + 8002172: 46bd mov sp, r7 + 8002174: bd80 pop {r7, pc} + +08002176 : + 8002176: b580 push {r7, lr} + 8002178: b082 sub sp, #8 + 800217a: af00 add r7, sp, #0 + 800217c: 4603 mov r3, r0 + 800217e: 71fb strb r3, [r7, #7] + 8002180: f997 3007 ldrsb.w r3, [r7, #7] + 8002184: 4618 mov r0, r3 + 8002186: f7ff ff31 bl 8001fec <__NVIC_EnableIRQ> + 800218a: bf00 nop + 800218c: 3708 adds r7, #8 + 800218e: 46bd mov sp, r7 + 8002190: bd80 pop {r7, pc} + +08002192 : + 8002192: b580 push {r7, lr} + 8002194: b082 sub sp, #8 + 8002196: af00 add r7, sp, #0 + 8002198: 6078 str r0, [r7, #4] + 800219a: 6878 ldr r0, [r7, #4] + 800219c: f7ff ffa2 bl 80020e4 + 80021a0: 4603 mov r3, r0 + 80021a2: 4618 mov r0, r3 + 80021a4: 3708 adds r7, #8 + 80021a6: 46bd mov sp, r7 + 80021a8: bd80 pop {r7, pc} + ... + +080021ac : + 80021ac: b580 push {r7, lr} + 80021ae: b086 sub sp, #24 + 80021b0: af00 add r7, sp, #0 + 80021b2: 6078 str r0, [r7, #4] + 80021b4: 2300 movs r3, #0 + 80021b6: 617b str r3, [r7, #20] + 80021b8: f7ff feb6 bl 8001f28 + 80021bc: 6138 str r0, [r7, #16] + 80021be: 687b ldr r3, [r7, #4] + 80021c0: 2b00 cmp r3, #0 + 80021c2: d101 bne.n 80021c8 + 80021c4: 2301 movs r3, #1 + 80021c6: e099 b.n 80022fc + 80021c8: 687b ldr r3, [r7, #4] + 80021ca: 2202 movs r2, #2 + 80021cc: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 80021d0: 687b ldr r3, [r7, #4] + 80021d2: 2200 movs r2, #0 + 80021d4: f883 2034 strb.w r2, [r3, #52] @ 0x34 + 80021d8: 687b ldr r3, [r7, #4] + 80021da: 681b ldr r3, [r3, #0] + 80021dc: 681a ldr r2, [r3, #0] + 80021de: 687b ldr r3, [r7, #4] + 80021e0: 681b ldr r3, [r3, #0] + 80021e2: f022 0201 bic.w r2, r2, #1 + 80021e6: 601a str r2, [r3, #0] + 80021e8: e00f b.n 800220a + 80021ea: f7ff fe9d bl 8001f28 + 80021ee: 4602 mov r2, r0 + 80021f0: 693b ldr r3, [r7, #16] + 80021f2: 1ad3 subs r3, r2, r3 + 80021f4: 2b05 cmp r3, #5 + 80021f6: d908 bls.n 800220a + 80021f8: 687b ldr r3, [r7, #4] + 80021fa: 2220 movs r2, #32 + 80021fc: 655a str r2, [r3, #84] @ 0x54 + 80021fe: 687b ldr r3, [r7, #4] + 8002200: 2203 movs r2, #3 + 8002202: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 8002206: 2303 movs r3, #3 + 8002208: e078 b.n 80022fc + 800220a: 687b ldr r3, [r7, #4] + 800220c: 681b ldr r3, [r3, #0] + 800220e: 681b ldr r3, [r3, #0] + 8002210: f003 0301 and.w r3, r3, #1 + 8002214: 2b00 cmp r3, #0 + 8002216: d1e8 bne.n 80021ea + 8002218: 687b ldr r3, [r7, #4] + 800221a: 681b ldr r3, [r3, #0] + 800221c: 681b ldr r3, [r3, #0] + 800221e: 617b str r3, [r7, #20] + 8002220: 697a ldr r2, [r7, #20] + 8002222: 4b38 ldr r3, [pc, #224] @ (8002304 ) + 8002224: 4013 ands r3, r2 + 8002226: 617b str r3, [r7, #20] + 8002228: 687b ldr r3, [r7, #4] + 800222a: 685a ldr r2, [r3, #4] + 800222c: 687b ldr r3, [r7, #4] + 800222e: 689b ldr r3, [r3, #8] + 8002230: 431a orrs r2, r3 + 8002232: 687b ldr r3, [r7, #4] + 8002234: 68db ldr r3, [r3, #12] + 8002236: 431a orrs r2, r3 + 8002238: 687b ldr r3, [r7, #4] + 800223a: 691b ldr r3, [r3, #16] + 800223c: 431a orrs r2, r3 + 800223e: 687b ldr r3, [r7, #4] + 8002240: 695b ldr r3, [r3, #20] + 8002242: 431a orrs r2, r3 + 8002244: 687b ldr r3, [r7, #4] + 8002246: 699b ldr r3, [r3, #24] + 8002248: 431a orrs r2, r3 + 800224a: 687b ldr r3, [r7, #4] + 800224c: 69db ldr r3, [r3, #28] + 800224e: 431a orrs r2, r3 + 8002250: 687b ldr r3, [r7, #4] + 8002252: 6a1b ldr r3, [r3, #32] + 8002254: 4313 orrs r3, r2 + 8002256: 697a ldr r2, [r7, #20] + 8002258: 4313 orrs r3, r2 + 800225a: 617b str r3, [r7, #20] + 800225c: 687b ldr r3, [r7, #4] + 800225e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002260: 2b04 cmp r3, #4 + 8002262: d107 bne.n 8002274 + 8002264: 687b ldr r3, [r7, #4] + 8002266: 6ada ldr r2, [r3, #44] @ 0x2c + 8002268: 687b ldr r3, [r7, #4] + 800226a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800226c: 4313 orrs r3, r2 + 800226e: 697a ldr r2, [r7, #20] + 8002270: 4313 orrs r3, r2 + 8002272: 617b str r3, [r7, #20] + 8002274: 687b ldr r3, [r7, #4] + 8002276: 681b ldr r3, [r3, #0] + 8002278: 697a ldr r2, [r7, #20] + 800227a: 601a str r2, [r3, #0] + 800227c: 687b ldr r3, [r7, #4] + 800227e: 681b ldr r3, [r3, #0] + 8002280: 695b ldr r3, [r3, #20] + 8002282: 617b str r3, [r7, #20] + 8002284: 697b ldr r3, [r7, #20] + 8002286: f023 0307 bic.w r3, r3, #7 + 800228a: 617b str r3, [r7, #20] + 800228c: 687b ldr r3, [r7, #4] + 800228e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002290: 697a ldr r2, [r7, #20] + 8002292: 4313 orrs r3, r2 + 8002294: 617b str r3, [r7, #20] + 8002296: 687b ldr r3, [r7, #4] + 8002298: 6a5b ldr r3, [r3, #36] @ 0x24 + 800229a: 2b04 cmp r3, #4 + 800229c: d117 bne.n 80022ce + 800229e: 687b ldr r3, [r7, #4] + 80022a0: 6a9b ldr r3, [r3, #40] @ 0x28 + 80022a2: 697a ldr r2, [r7, #20] + 80022a4: 4313 orrs r3, r2 + 80022a6: 617b str r3, [r7, #20] + 80022a8: 687b ldr r3, [r7, #4] + 80022aa: 6adb ldr r3, [r3, #44] @ 0x2c + 80022ac: 2b00 cmp r3, #0 + 80022ae: d00e beq.n 80022ce + 80022b0: 6878 ldr r0, [r7, #4] + 80022b2: f000 fb01 bl 80028b8 + 80022b6: 4603 mov r3, r0 + 80022b8: 2b00 cmp r3, #0 + 80022ba: d008 beq.n 80022ce + 80022bc: 687b ldr r3, [r7, #4] + 80022be: 2240 movs r2, #64 @ 0x40 + 80022c0: 655a str r2, [r3, #84] @ 0x54 + 80022c2: 687b ldr r3, [r7, #4] + 80022c4: 2201 movs r2, #1 + 80022c6: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 80022ca: 2301 movs r3, #1 + 80022cc: e016 b.n 80022fc + 80022ce: 687b ldr r3, [r7, #4] + 80022d0: 681b ldr r3, [r3, #0] + 80022d2: 697a ldr r2, [r7, #20] + 80022d4: 615a str r2, [r3, #20] + 80022d6: 6878 ldr r0, [r7, #4] + 80022d8: f000 fab8 bl 800284c + 80022dc: 4603 mov r3, r0 + 80022de: 60fb str r3, [r7, #12] + 80022e0: 687b ldr r3, [r7, #4] + 80022e2: 6ddb ldr r3, [r3, #92] @ 0x5c + 80022e4: 223f movs r2, #63 @ 0x3f + 80022e6: 409a lsls r2, r3 + 80022e8: 68fb ldr r3, [r7, #12] + 80022ea: 609a str r2, [r3, #8] + 80022ec: 687b ldr r3, [r7, #4] + 80022ee: 2200 movs r2, #0 + 80022f0: 655a str r2, [r3, #84] @ 0x54 + 80022f2: 687b ldr r3, [r7, #4] + 80022f4: 2201 movs r2, #1 + 80022f6: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 80022fa: 2300 movs r3, #0 + 80022fc: 4618 mov r0, r3 + 80022fe: 3718 adds r7, #24 + 8002300: 46bd mov sp, r7 + 8002302: bd80 pop {r7, pc} + 8002304: f010803f .word 0xf010803f + +08002308 : + 8002308: b580 push {r7, lr} + 800230a: b086 sub sp, #24 + 800230c: af00 add r7, sp, #0 + 800230e: 60f8 str r0, [r7, #12] + 8002310: 60b9 str r1, [r7, #8] + 8002312: 607a str r2, [r7, #4] + 8002314: 603b str r3, [r7, #0] + 8002316: 2300 movs r3, #0 + 8002318: 75fb strb r3, [r7, #23] + 800231a: 68fb ldr r3, [r7, #12] + 800231c: 6d9b ldr r3, [r3, #88] @ 0x58 + 800231e: 613b str r3, [r7, #16] + 8002320: 68fb ldr r3, [r7, #12] + 8002322: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 + 8002326: 2b01 cmp r3, #1 + 8002328: d101 bne.n 800232e + 800232a: 2302 movs r3, #2 + 800232c: e040 b.n 80023b0 + 800232e: 68fb ldr r3, [r7, #12] + 8002330: 2201 movs r2, #1 + 8002332: f883 2034 strb.w r2, [r3, #52] @ 0x34 + 8002336: 68fb ldr r3, [r7, #12] + 8002338: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 + 800233c: b2db uxtb r3, r3 + 800233e: 2b01 cmp r3, #1 + 8002340: d12f bne.n 80023a2 + 8002342: 68fb ldr r3, [r7, #12] + 8002344: 2202 movs r2, #2 + 8002346: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 800234a: 68fb ldr r3, [r7, #12] + 800234c: 2200 movs r2, #0 + 800234e: 655a str r2, [r3, #84] @ 0x54 + 8002350: 683b ldr r3, [r7, #0] + 8002352: 687a ldr r2, [r7, #4] + 8002354: 68b9 ldr r1, [r7, #8] + 8002356: 68f8 ldr r0, [r7, #12] + 8002358: f000 fa4a bl 80027f0 + 800235c: 68fb ldr r3, [r7, #12] + 800235e: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002360: 223f movs r2, #63 @ 0x3f + 8002362: 409a lsls r2, r3 + 8002364: 693b ldr r3, [r7, #16] + 8002366: 609a str r2, [r3, #8] + 8002368: 68fb ldr r3, [r7, #12] + 800236a: 681b ldr r3, [r3, #0] + 800236c: 681a ldr r2, [r3, #0] + 800236e: 68fb ldr r3, [r7, #12] + 8002370: 681b ldr r3, [r3, #0] + 8002372: f042 0216 orr.w r2, r2, #22 + 8002376: 601a str r2, [r3, #0] + 8002378: 68fb ldr r3, [r7, #12] + 800237a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800237c: 2b00 cmp r3, #0 + 800237e: d007 beq.n 8002390 + 8002380: 68fb ldr r3, [r7, #12] + 8002382: 681b ldr r3, [r3, #0] + 8002384: 681a ldr r2, [r3, #0] + 8002386: 68fb ldr r3, [r7, #12] + 8002388: 681b ldr r3, [r3, #0] + 800238a: f042 0208 orr.w r2, r2, #8 + 800238e: 601a str r2, [r3, #0] + 8002390: 68fb ldr r3, [r7, #12] + 8002392: 681b ldr r3, [r3, #0] + 8002394: 681a ldr r2, [r3, #0] + 8002396: 68fb ldr r3, [r7, #12] + 8002398: 681b ldr r3, [r3, #0] + 800239a: f042 0201 orr.w r2, r2, #1 + 800239e: 601a str r2, [r3, #0] + 80023a0: e005 b.n 80023ae + 80023a2: 68fb ldr r3, [r7, #12] + 80023a4: 2200 movs r2, #0 + 80023a6: f883 2034 strb.w r2, [r3, #52] @ 0x34 + 80023aa: 2302 movs r3, #2 + 80023ac: 75fb strb r3, [r7, #23] + 80023ae: 7dfb ldrb r3, [r7, #23] + 80023b0: 4618 mov r0, r3 + 80023b2: 3718 adds r7, #24 + 80023b4: 46bd mov sp, r7 + 80023b6: bd80 pop {r7, pc} + +080023b8 : + 80023b8: b580 push {r7, lr} + 80023ba: b084 sub sp, #16 + 80023bc: af00 add r7, sp, #0 + 80023be: 6078 str r0, [r7, #4] + 80023c0: 687b ldr r3, [r7, #4] + 80023c2: 6d9b ldr r3, [r3, #88] @ 0x58 + 80023c4: 60fb str r3, [r7, #12] + 80023c6: f7ff fdaf bl 8001f28 + 80023ca: 60b8 str r0, [r7, #8] + 80023cc: 687b ldr r3, [r7, #4] + 80023ce: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 + 80023d2: b2db uxtb r3, r3 + 80023d4: 2b02 cmp r3, #2 + 80023d6: d008 beq.n 80023ea + 80023d8: 687b ldr r3, [r7, #4] + 80023da: 2280 movs r2, #128 @ 0x80 + 80023dc: 655a str r2, [r3, #84] @ 0x54 + 80023de: 687b ldr r3, [r7, #4] + 80023e0: 2200 movs r2, #0 + 80023e2: f883 2034 strb.w r2, [r3, #52] @ 0x34 + 80023e6: 2301 movs r3, #1 + 80023e8: e052 b.n 8002490 + 80023ea: 687b ldr r3, [r7, #4] + 80023ec: 681b ldr r3, [r3, #0] + 80023ee: 681a ldr r2, [r3, #0] + 80023f0: 687b ldr r3, [r7, #4] + 80023f2: 681b ldr r3, [r3, #0] + 80023f4: f022 0216 bic.w r2, r2, #22 + 80023f8: 601a str r2, [r3, #0] + 80023fa: 687b ldr r3, [r7, #4] + 80023fc: 681b ldr r3, [r3, #0] + 80023fe: 695a ldr r2, [r3, #20] + 8002400: 687b ldr r3, [r7, #4] + 8002402: 681b ldr r3, [r3, #0] + 8002404: f022 0280 bic.w r2, r2, #128 @ 0x80 + 8002408: 615a str r2, [r3, #20] + 800240a: 687b ldr r3, [r7, #4] + 800240c: 6c1b ldr r3, [r3, #64] @ 0x40 + 800240e: 2b00 cmp r3, #0 + 8002410: d103 bne.n 800241a + 8002412: 687b ldr r3, [r7, #4] + 8002414: 6c9b ldr r3, [r3, #72] @ 0x48 + 8002416: 2b00 cmp r3, #0 + 8002418: d007 beq.n 800242a + 800241a: 687b ldr r3, [r7, #4] + 800241c: 681b ldr r3, [r3, #0] + 800241e: 681a ldr r2, [r3, #0] + 8002420: 687b ldr r3, [r7, #4] + 8002422: 681b ldr r3, [r3, #0] + 8002424: f022 0208 bic.w r2, r2, #8 + 8002428: 601a str r2, [r3, #0] + 800242a: 687b ldr r3, [r7, #4] + 800242c: 681b ldr r3, [r3, #0] + 800242e: 681a ldr r2, [r3, #0] + 8002430: 687b ldr r3, [r7, #4] + 8002432: 681b ldr r3, [r3, #0] + 8002434: f022 0201 bic.w r2, r2, #1 + 8002438: 601a str r2, [r3, #0] + 800243a: e013 b.n 8002464 + 800243c: f7ff fd74 bl 8001f28 + 8002440: 4602 mov r2, r0 + 8002442: 68bb ldr r3, [r7, #8] + 8002444: 1ad3 subs r3, r2, r3 + 8002446: 2b05 cmp r3, #5 + 8002448: d90c bls.n 8002464 + 800244a: 687b ldr r3, [r7, #4] + 800244c: 2220 movs r2, #32 + 800244e: 655a str r2, [r3, #84] @ 0x54 + 8002450: 687b ldr r3, [r7, #4] + 8002452: 2203 movs r2, #3 + 8002454: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 8002458: 687b ldr r3, [r7, #4] + 800245a: 2200 movs r2, #0 + 800245c: f883 2034 strb.w r2, [r3, #52] @ 0x34 + 8002460: 2303 movs r3, #3 + 8002462: e015 b.n 8002490 + 8002464: 687b ldr r3, [r7, #4] + 8002466: 681b ldr r3, [r3, #0] + 8002468: 681b ldr r3, [r3, #0] + 800246a: f003 0301 and.w r3, r3, #1 + 800246e: 2b00 cmp r3, #0 + 8002470: d1e4 bne.n 800243c + 8002472: 687b ldr r3, [r7, #4] + 8002474: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002476: 223f movs r2, #63 @ 0x3f + 8002478: 409a lsls r2, r3 + 800247a: 68fb ldr r3, [r7, #12] + 800247c: 609a str r2, [r3, #8] + 800247e: 687b ldr r3, [r7, #4] + 8002480: 2201 movs r2, #1 + 8002482: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 8002486: 687b ldr r3, [r7, #4] + 8002488: 2200 movs r2, #0 + 800248a: f883 2034 strb.w r2, [r3, #52] @ 0x34 + 800248e: 2300 movs r3, #0 + 8002490: 4618 mov r0, r3 + 8002492: 3710 adds r7, #16 + 8002494: 46bd mov sp, r7 + 8002496: bd80 pop {r7, pc} + +08002498 : + 8002498: b480 push {r7} + 800249a: b083 sub sp, #12 + 800249c: af00 add r7, sp, #0 + 800249e: 6078 str r0, [r7, #4] + 80024a0: 687b ldr r3, [r7, #4] + 80024a2: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 + 80024a6: b2db uxtb r3, r3 + 80024a8: 2b02 cmp r3, #2 + 80024aa: d004 beq.n 80024b6 + 80024ac: 687b ldr r3, [r7, #4] + 80024ae: 2280 movs r2, #128 @ 0x80 + 80024b0: 655a str r2, [r3, #84] @ 0x54 + 80024b2: 2301 movs r3, #1 + 80024b4: e00c b.n 80024d0 + 80024b6: 687b ldr r3, [r7, #4] + 80024b8: 2205 movs r2, #5 + 80024ba: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 80024be: 687b ldr r3, [r7, #4] + 80024c0: 681b ldr r3, [r3, #0] + 80024c2: 681a ldr r2, [r3, #0] + 80024c4: 687b ldr r3, [r7, #4] + 80024c6: 681b ldr r3, [r3, #0] + 80024c8: f022 0201 bic.w r2, r2, #1 + 80024cc: 601a str r2, [r3, #0] + 80024ce: 2300 movs r3, #0 + 80024d0: 4618 mov r0, r3 + 80024d2: 370c adds r7, #12 + 80024d4: 46bd mov sp, r7 + 80024d6: f85d 7b04 ldr.w r7, [sp], #4 + 80024da: 4770 bx lr + +080024dc : + 80024dc: b580 push {r7, lr} + 80024de: b086 sub sp, #24 + 80024e0: af00 add r7, sp, #0 + 80024e2: 6078 str r0, [r7, #4] + 80024e4: 2300 movs r3, #0 + 80024e6: 60bb str r3, [r7, #8] + 80024e8: 4b8e ldr r3, [pc, #568] @ (8002724 ) + 80024ea: 681b ldr r3, [r3, #0] + 80024ec: 4a8e ldr r2, [pc, #568] @ (8002728 ) + 80024ee: fba2 2303 umull r2, r3, r2, r3 + 80024f2: 0a9b lsrs r3, r3, #10 + 80024f4: 617b str r3, [r7, #20] + 80024f6: 687b ldr r3, [r7, #4] + 80024f8: 6d9b ldr r3, [r3, #88] @ 0x58 + 80024fa: 613b str r3, [r7, #16] + 80024fc: 693b ldr r3, [r7, #16] + 80024fe: 681b ldr r3, [r3, #0] + 8002500: 60fb str r3, [r7, #12] + 8002502: 687b ldr r3, [r7, #4] + 8002504: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002506: 2208 movs r2, #8 + 8002508: 409a lsls r2, r3 + 800250a: 68fb ldr r3, [r7, #12] + 800250c: 4013 ands r3, r2 + 800250e: 2b00 cmp r3, #0 + 8002510: d01a beq.n 8002548 + 8002512: 687b ldr r3, [r7, #4] + 8002514: 681b ldr r3, [r3, #0] + 8002516: 681b ldr r3, [r3, #0] + 8002518: f003 0304 and.w r3, r3, #4 + 800251c: 2b00 cmp r3, #0 + 800251e: d013 beq.n 8002548 + 8002520: 687b ldr r3, [r7, #4] + 8002522: 681b ldr r3, [r3, #0] + 8002524: 681a ldr r2, [r3, #0] + 8002526: 687b ldr r3, [r7, #4] + 8002528: 681b ldr r3, [r3, #0] + 800252a: f022 0204 bic.w r2, r2, #4 + 800252e: 601a str r2, [r3, #0] + 8002530: 687b ldr r3, [r7, #4] + 8002532: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002534: 2208 movs r2, #8 + 8002536: 409a lsls r2, r3 + 8002538: 693b ldr r3, [r7, #16] + 800253a: 609a str r2, [r3, #8] + 800253c: 687b ldr r3, [r7, #4] + 800253e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002540: f043 0201 orr.w r2, r3, #1 + 8002544: 687b ldr r3, [r7, #4] + 8002546: 655a str r2, [r3, #84] @ 0x54 + 8002548: 687b ldr r3, [r7, #4] + 800254a: 6ddb ldr r3, [r3, #92] @ 0x5c + 800254c: 2201 movs r2, #1 + 800254e: 409a lsls r2, r3 + 8002550: 68fb ldr r3, [r7, #12] + 8002552: 4013 ands r3, r2 + 8002554: 2b00 cmp r3, #0 + 8002556: d012 beq.n 800257e + 8002558: 687b ldr r3, [r7, #4] + 800255a: 681b ldr r3, [r3, #0] + 800255c: 695b ldr r3, [r3, #20] + 800255e: f003 0380 and.w r3, r3, #128 @ 0x80 + 8002562: 2b00 cmp r3, #0 + 8002564: d00b beq.n 800257e + 8002566: 687b ldr r3, [r7, #4] + 8002568: 6ddb ldr r3, [r3, #92] @ 0x5c + 800256a: 2201 movs r2, #1 + 800256c: 409a lsls r2, r3 + 800256e: 693b ldr r3, [r7, #16] + 8002570: 609a str r2, [r3, #8] + 8002572: 687b ldr r3, [r7, #4] + 8002574: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002576: f043 0202 orr.w r2, r3, #2 + 800257a: 687b ldr r3, [r7, #4] + 800257c: 655a str r2, [r3, #84] @ 0x54 + 800257e: 687b ldr r3, [r7, #4] + 8002580: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002582: 2204 movs r2, #4 + 8002584: 409a lsls r2, r3 + 8002586: 68fb ldr r3, [r7, #12] + 8002588: 4013 ands r3, r2 + 800258a: 2b00 cmp r3, #0 + 800258c: d012 beq.n 80025b4 + 800258e: 687b ldr r3, [r7, #4] + 8002590: 681b ldr r3, [r3, #0] + 8002592: 681b ldr r3, [r3, #0] + 8002594: f003 0302 and.w r3, r3, #2 + 8002598: 2b00 cmp r3, #0 + 800259a: d00b beq.n 80025b4 + 800259c: 687b ldr r3, [r7, #4] + 800259e: 6ddb ldr r3, [r3, #92] @ 0x5c + 80025a0: 2204 movs r2, #4 + 80025a2: 409a lsls r2, r3 + 80025a4: 693b ldr r3, [r7, #16] + 80025a6: 609a str r2, [r3, #8] + 80025a8: 687b ldr r3, [r7, #4] + 80025aa: 6d5b ldr r3, [r3, #84] @ 0x54 + 80025ac: f043 0204 orr.w r2, r3, #4 + 80025b0: 687b ldr r3, [r7, #4] + 80025b2: 655a str r2, [r3, #84] @ 0x54 + 80025b4: 687b ldr r3, [r7, #4] + 80025b6: 6ddb ldr r3, [r3, #92] @ 0x5c + 80025b8: 2210 movs r2, #16 + 80025ba: 409a lsls r2, r3 + 80025bc: 68fb ldr r3, [r7, #12] + 80025be: 4013 ands r3, r2 + 80025c0: 2b00 cmp r3, #0 + 80025c2: d043 beq.n 800264c + 80025c4: 687b ldr r3, [r7, #4] + 80025c6: 681b ldr r3, [r3, #0] + 80025c8: 681b ldr r3, [r3, #0] + 80025ca: f003 0308 and.w r3, r3, #8 + 80025ce: 2b00 cmp r3, #0 + 80025d0: d03c beq.n 800264c + 80025d2: 687b ldr r3, [r7, #4] + 80025d4: 6ddb ldr r3, [r3, #92] @ 0x5c + 80025d6: 2210 movs r2, #16 + 80025d8: 409a lsls r2, r3 + 80025da: 693b ldr r3, [r7, #16] + 80025dc: 609a str r2, [r3, #8] + 80025de: 687b ldr r3, [r7, #4] + 80025e0: 681b ldr r3, [r3, #0] + 80025e2: 681b ldr r3, [r3, #0] + 80025e4: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 80025e8: 2b00 cmp r3, #0 + 80025ea: d018 beq.n 800261e + 80025ec: 687b ldr r3, [r7, #4] + 80025ee: 681b ldr r3, [r3, #0] + 80025f0: 681b ldr r3, [r3, #0] + 80025f2: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 80025f6: 2b00 cmp r3, #0 + 80025f8: d108 bne.n 800260c + 80025fa: 687b ldr r3, [r7, #4] + 80025fc: 6c1b ldr r3, [r3, #64] @ 0x40 + 80025fe: 2b00 cmp r3, #0 + 8002600: d024 beq.n 800264c + 8002602: 687b ldr r3, [r7, #4] + 8002604: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002606: 6878 ldr r0, [r7, #4] + 8002608: 4798 blx r3 + 800260a: e01f b.n 800264c + 800260c: 687b ldr r3, [r7, #4] + 800260e: 6c9b ldr r3, [r3, #72] @ 0x48 + 8002610: 2b00 cmp r3, #0 + 8002612: d01b beq.n 800264c + 8002614: 687b ldr r3, [r7, #4] + 8002616: 6c9b ldr r3, [r3, #72] @ 0x48 + 8002618: 6878 ldr r0, [r7, #4] + 800261a: 4798 blx r3 + 800261c: e016 b.n 800264c + 800261e: 687b ldr r3, [r7, #4] + 8002620: 681b ldr r3, [r3, #0] + 8002622: 681b ldr r3, [r3, #0] + 8002624: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002628: 2b00 cmp r3, #0 + 800262a: d107 bne.n 800263c + 800262c: 687b ldr r3, [r7, #4] + 800262e: 681b ldr r3, [r3, #0] + 8002630: 681a ldr r2, [r3, #0] + 8002632: 687b ldr r3, [r7, #4] + 8002634: 681b ldr r3, [r3, #0] + 8002636: f022 0208 bic.w r2, r2, #8 + 800263a: 601a str r2, [r3, #0] + 800263c: 687b ldr r3, [r7, #4] + 800263e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002640: 2b00 cmp r3, #0 + 8002642: d003 beq.n 800264c + 8002644: 687b ldr r3, [r7, #4] + 8002646: 6c1b ldr r3, [r3, #64] @ 0x40 + 8002648: 6878 ldr r0, [r7, #4] + 800264a: 4798 blx r3 + 800264c: 687b ldr r3, [r7, #4] + 800264e: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002650: 2220 movs r2, #32 + 8002652: 409a lsls r2, r3 + 8002654: 68fb ldr r3, [r7, #12] + 8002656: 4013 ands r3, r2 + 8002658: 2b00 cmp r3, #0 + 800265a: f000 808f beq.w 800277c + 800265e: 687b ldr r3, [r7, #4] + 8002660: 681b ldr r3, [r3, #0] + 8002662: 681b ldr r3, [r3, #0] + 8002664: f003 0310 and.w r3, r3, #16 + 8002668: 2b00 cmp r3, #0 + 800266a: f000 8087 beq.w 800277c + 800266e: 687b ldr r3, [r7, #4] + 8002670: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002672: 2220 movs r2, #32 + 8002674: 409a lsls r2, r3 + 8002676: 693b ldr r3, [r7, #16] + 8002678: 609a str r2, [r3, #8] + 800267a: 687b ldr r3, [r7, #4] + 800267c: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 + 8002680: b2db uxtb r3, r3 + 8002682: 2b05 cmp r3, #5 + 8002684: d136 bne.n 80026f4 + 8002686: 687b ldr r3, [r7, #4] + 8002688: 681b ldr r3, [r3, #0] + 800268a: 681a ldr r2, [r3, #0] + 800268c: 687b ldr r3, [r7, #4] + 800268e: 681b ldr r3, [r3, #0] + 8002690: f022 0216 bic.w r2, r2, #22 + 8002694: 601a str r2, [r3, #0] + 8002696: 687b ldr r3, [r7, #4] + 8002698: 681b ldr r3, [r3, #0] + 800269a: 695a ldr r2, [r3, #20] + 800269c: 687b ldr r3, [r7, #4] + 800269e: 681b ldr r3, [r3, #0] + 80026a0: f022 0280 bic.w r2, r2, #128 @ 0x80 + 80026a4: 615a str r2, [r3, #20] + 80026a6: 687b ldr r3, [r7, #4] + 80026a8: 6c1b ldr r3, [r3, #64] @ 0x40 + 80026aa: 2b00 cmp r3, #0 + 80026ac: d103 bne.n 80026b6 + 80026ae: 687b ldr r3, [r7, #4] + 80026b0: 6c9b ldr r3, [r3, #72] @ 0x48 + 80026b2: 2b00 cmp r3, #0 + 80026b4: d007 beq.n 80026c6 + 80026b6: 687b ldr r3, [r7, #4] + 80026b8: 681b ldr r3, [r3, #0] + 80026ba: 681a ldr r2, [r3, #0] + 80026bc: 687b ldr r3, [r7, #4] + 80026be: 681b ldr r3, [r3, #0] + 80026c0: f022 0208 bic.w r2, r2, #8 + 80026c4: 601a str r2, [r3, #0] + 80026c6: 687b ldr r3, [r7, #4] + 80026c8: 6ddb ldr r3, [r3, #92] @ 0x5c + 80026ca: 223f movs r2, #63 @ 0x3f + 80026cc: 409a lsls r2, r3 + 80026ce: 693b ldr r3, [r7, #16] + 80026d0: 609a str r2, [r3, #8] + 80026d2: 687b ldr r3, [r7, #4] + 80026d4: 2201 movs r2, #1 + 80026d6: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 80026da: 687b ldr r3, [r7, #4] + 80026dc: 2200 movs r2, #0 + 80026de: f883 2034 strb.w r2, [r3, #52] @ 0x34 + 80026e2: 687b ldr r3, [r7, #4] + 80026e4: 6d1b ldr r3, [r3, #80] @ 0x50 + 80026e6: 2b00 cmp r3, #0 + 80026e8: d07e beq.n 80027e8 + 80026ea: 687b ldr r3, [r7, #4] + 80026ec: 6d1b ldr r3, [r3, #80] @ 0x50 + 80026ee: 6878 ldr r0, [r7, #4] + 80026f0: 4798 blx r3 + 80026f2: e079 b.n 80027e8 + 80026f4: 687b ldr r3, [r7, #4] + 80026f6: 681b ldr r3, [r3, #0] + 80026f8: 681b ldr r3, [r3, #0] + 80026fa: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 80026fe: 2b00 cmp r3, #0 + 8002700: d01d beq.n 800273e + 8002702: 687b ldr r3, [r7, #4] + 8002704: 681b ldr r3, [r3, #0] + 8002706: 681b ldr r3, [r3, #0] + 8002708: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 800270c: 2b00 cmp r3, #0 + 800270e: d10d bne.n 800272c + 8002710: 687b ldr r3, [r7, #4] + 8002712: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002714: 2b00 cmp r3, #0 + 8002716: d031 beq.n 800277c + 8002718: 687b ldr r3, [r7, #4] + 800271a: 6c5b ldr r3, [r3, #68] @ 0x44 + 800271c: 6878 ldr r0, [r7, #4] + 800271e: 4798 blx r3 + 8002720: e02c b.n 800277c + 8002722: bf00 nop + 8002724: 20000090 .word 0x20000090 + 8002728: 1b4e81b5 .word 0x1b4e81b5 + 800272c: 687b ldr r3, [r7, #4] + 800272e: 6bdb ldr r3, [r3, #60] @ 0x3c + 8002730: 2b00 cmp r3, #0 + 8002732: d023 beq.n 800277c + 8002734: 687b ldr r3, [r7, #4] + 8002736: 6bdb ldr r3, [r3, #60] @ 0x3c + 8002738: 6878 ldr r0, [r7, #4] + 800273a: 4798 blx r3 + 800273c: e01e b.n 800277c + 800273e: 687b ldr r3, [r7, #4] + 8002740: 681b ldr r3, [r3, #0] + 8002742: 681b ldr r3, [r3, #0] + 8002744: f403 7380 and.w r3, r3, #256 @ 0x100 + 8002748: 2b00 cmp r3, #0 + 800274a: d10f bne.n 800276c + 800274c: 687b ldr r3, [r7, #4] + 800274e: 681b ldr r3, [r3, #0] + 8002750: 681a ldr r2, [r3, #0] + 8002752: 687b ldr r3, [r7, #4] + 8002754: 681b ldr r3, [r3, #0] + 8002756: f022 0210 bic.w r2, r2, #16 + 800275a: 601a str r2, [r3, #0] + 800275c: 687b ldr r3, [r7, #4] + 800275e: 2201 movs r2, #1 + 8002760: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 8002764: 687b ldr r3, [r7, #4] + 8002766: 2200 movs r2, #0 + 8002768: f883 2034 strb.w r2, [r3, #52] @ 0x34 + 800276c: 687b ldr r3, [r7, #4] + 800276e: 6bdb ldr r3, [r3, #60] @ 0x3c + 8002770: 2b00 cmp r3, #0 + 8002772: d003 beq.n 800277c + 8002774: 687b ldr r3, [r7, #4] + 8002776: 6bdb ldr r3, [r3, #60] @ 0x3c + 8002778: 6878 ldr r0, [r7, #4] + 800277a: 4798 blx r3 + 800277c: 687b ldr r3, [r7, #4] + 800277e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002780: 2b00 cmp r3, #0 + 8002782: d032 beq.n 80027ea + 8002784: 687b ldr r3, [r7, #4] + 8002786: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002788: f003 0301 and.w r3, r3, #1 + 800278c: 2b00 cmp r3, #0 + 800278e: d022 beq.n 80027d6 + 8002790: 687b ldr r3, [r7, #4] + 8002792: 2205 movs r2, #5 + 8002794: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 8002798: 687b ldr r3, [r7, #4] + 800279a: 681b ldr r3, [r3, #0] + 800279c: 681a ldr r2, [r3, #0] + 800279e: 687b ldr r3, [r7, #4] + 80027a0: 681b ldr r3, [r3, #0] + 80027a2: f022 0201 bic.w r2, r2, #1 + 80027a6: 601a str r2, [r3, #0] + 80027a8: 68bb ldr r3, [r7, #8] + 80027aa: 3301 adds r3, #1 + 80027ac: 60bb str r3, [r7, #8] + 80027ae: 697a ldr r2, [r7, #20] + 80027b0: 429a cmp r2, r3 + 80027b2: d307 bcc.n 80027c4 + 80027b4: 687b ldr r3, [r7, #4] + 80027b6: 681b ldr r3, [r3, #0] + 80027b8: 681b ldr r3, [r3, #0] + 80027ba: f003 0301 and.w r3, r3, #1 + 80027be: 2b00 cmp r3, #0 + 80027c0: d1f2 bne.n 80027a8 + 80027c2: e000 b.n 80027c6 + 80027c4: bf00 nop + 80027c6: 687b ldr r3, [r7, #4] + 80027c8: 2201 movs r2, #1 + 80027ca: f883 2035 strb.w r2, [r3, #53] @ 0x35 + 80027ce: 687b ldr r3, [r7, #4] + 80027d0: 2200 movs r2, #0 + 80027d2: f883 2034 strb.w r2, [r3, #52] @ 0x34 + 80027d6: 687b ldr r3, [r7, #4] + 80027d8: 6cdb ldr r3, [r3, #76] @ 0x4c + 80027da: 2b00 cmp r3, #0 + 80027dc: d005 beq.n 80027ea + 80027de: 687b ldr r3, [r7, #4] + 80027e0: 6cdb ldr r3, [r3, #76] @ 0x4c + 80027e2: 6878 ldr r0, [r7, #4] + 80027e4: 4798 blx r3 + 80027e6: e000 b.n 80027ea + 80027e8: bf00 nop + 80027ea: 3718 adds r7, #24 + 80027ec: 46bd mov sp, r7 + 80027ee: bd80 pop {r7, pc} + +080027f0 : + 80027f0: b480 push {r7} + 80027f2: b085 sub sp, #20 + 80027f4: af00 add r7, sp, #0 + 80027f6: 60f8 str r0, [r7, #12] + 80027f8: 60b9 str r1, [r7, #8] + 80027fa: 607a str r2, [r7, #4] + 80027fc: 603b str r3, [r7, #0] + 80027fe: 68fb ldr r3, [r7, #12] + 8002800: 681b ldr r3, [r3, #0] + 8002802: 681a ldr r2, [r3, #0] + 8002804: 68fb ldr r3, [r7, #12] + 8002806: 681b ldr r3, [r3, #0] + 8002808: f422 2280 bic.w r2, r2, #262144 @ 0x40000 + 800280c: 601a str r2, [r3, #0] + 800280e: 68fb ldr r3, [r7, #12] + 8002810: 681b ldr r3, [r3, #0] + 8002812: 683a ldr r2, [r7, #0] + 8002814: 605a str r2, [r3, #4] + 8002816: 68fb ldr r3, [r7, #12] + 8002818: 689b ldr r3, [r3, #8] + 800281a: 2b40 cmp r3, #64 @ 0x40 + 800281c: d108 bne.n 8002830 + 800281e: 68fb ldr r3, [r7, #12] + 8002820: 681b ldr r3, [r3, #0] + 8002822: 687a ldr r2, [r7, #4] + 8002824: 609a str r2, [r3, #8] + 8002826: 68fb ldr r3, [r7, #12] + 8002828: 681b ldr r3, [r3, #0] + 800282a: 68ba ldr r2, [r7, #8] + 800282c: 60da str r2, [r3, #12] + 800282e: e007 b.n 8002840 + 8002830: 68fb ldr r3, [r7, #12] + 8002832: 681b ldr r3, [r3, #0] + 8002834: 68ba ldr r2, [r7, #8] + 8002836: 609a str r2, [r3, #8] + 8002838: 68fb ldr r3, [r7, #12] + 800283a: 681b ldr r3, [r3, #0] + 800283c: 687a ldr r2, [r7, #4] + 800283e: 60da str r2, [r3, #12] + 8002840: bf00 nop + 8002842: 3714 adds r7, #20 + 8002844: 46bd mov sp, r7 + 8002846: f85d 7b04 ldr.w r7, [sp], #4 + 800284a: 4770 bx lr + +0800284c : + 800284c: b480 push {r7} + 800284e: b085 sub sp, #20 + 8002850: af00 add r7, sp, #0 + 8002852: 6078 str r0, [r7, #4] + 8002854: 687b ldr r3, [r7, #4] + 8002856: 681b ldr r3, [r3, #0] + 8002858: b2db uxtb r3, r3 + 800285a: 3b10 subs r3, #16 + 800285c: 4a14 ldr r2, [pc, #80] @ (80028b0 ) + 800285e: fba2 2303 umull r2, r3, r2, r3 + 8002862: 091b lsrs r3, r3, #4 + 8002864: 60fb str r3, [r7, #12] + 8002866: 4a13 ldr r2, [pc, #76] @ (80028b4 ) + 8002868: 68fb ldr r3, [r7, #12] + 800286a: 4413 add r3, r2 + 800286c: 781b ldrb r3, [r3, #0] + 800286e: 461a mov r2, r3 + 8002870: 687b ldr r3, [r7, #4] + 8002872: 65da str r2, [r3, #92] @ 0x5c + 8002874: 68fb ldr r3, [r7, #12] + 8002876: 2b03 cmp r3, #3 + 8002878: d909 bls.n 800288e + 800287a: 687b ldr r3, [r7, #4] + 800287c: 681b ldr r3, [r3, #0] + 800287e: f423 737f bic.w r3, r3, #1020 @ 0x3fc + 8002882: f023 0303 bic.w r3, r3, #3 + 8002886: 1d1a adds r2, r3, #4 + 8002888: 687b ldr r3, [r7, #4] + 800288a: 659a str r2, [r3, #88] @ 0x58 + 800288c: e007 b.n 800289e + 800288e: 687b ldr r3, [r7, #4] + 8002890: 681b ldr r3, [r3, #0] + 8002892: f423 737f bic.w r3, r3, #1020 @ 0x3fc + 8002896: f023 0303 bic.w r3, r3, #3 + 800289a: 687a ldr r2, [r7, #4] + 800289c: 6593 str r3, [r2, #88] @ 0x58 + 800289e: 687b ldr r3, [r7, #4] + 80028a0: 6d9b ldr r3, [r3, #88] @ 0x58 + 80028a2: 4618 mov r0, r3 + 80028a4: 3714 adds r7, #20 + 80028a6: 46bd mov sp, r7 + 80028a8: f85d 7b04 ldr.w r7, [sp], #4 + 80028ac: 4770 bx lr + 80028ae: bf00 nop + 80028b0: aaaaaaab .word 0xaaaaaaab + 80028b4: 0800b430 .word 0x0800b430 + +080028b8 : + 80028b8: b480 push {r7} + 80028ba: b085 sub sp, #20 + 80028bc: af00 add r7, sp, #0 + 80028be: 6078 str r0, [r7, #4] + 80028c0: 2300 movs r3, #0 + 80028c2: 73fb strb r3, [r7, #15] + 80028c4: 687b ldr r3, [r7, #4] + 80028c6: 6a9b ldr r3, [r3, #40] @ 0x28 + 80028c8: 60bb str r3, [r7, #8] + 80028ca: 687b ldr r3, [r7, #4] + 80028cc: 699b ldr r3, [r3, #24] + 80028ce: 2b00 cmp r3, #0 + 80028d0: d11f bne.n 8002912 + 80028d2: 68bb ldr r3, [r7, #8] + 80028d4: 2b03 cmp r3, #3 + 80028d6: d856 bhi.n 8002986 + 80028d8: a201 add r2, pc, #4 @ (adr r2, 80028e0 ) + 80028da: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80028de: bf00 nop + 80028e0: 080028f1 .word 0x080028f1 + 80028e4: 08002903 .word 0x08002903 + 80028e8: 080028f1 .word 0x080028f1 + 80028ec: 08002987 .word 0x08002987 + 80028f0: 687b ldr r3, [r7, #4] + 80028f2: 6adb ldr r3, [r3, #44] @ 0x2c + 80028f4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 80028f8: 2b00 cmp r3, #0 + 80028fa: d046 beq.n 800298a + 80028fc: 2301 movs r3, #1 + 80028fe: 73fb strb r3, [r7, #15] + 8002900: e043 b.n 800298a + 8002902: 687b ldr r3, [r7, #4] + 8002904: 6adb ldr r3, [r3, #44] @ 0x2c + 8002906: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 + 800290a: d140 bne.n 800298e + 800290c: 2301 movs r3, #1 + 800290e: 73fb strb r3, [r7, #15] + 8002910: e03d b.n 800298e + 8002912: 687b ldr r3, [r7, #4] + 8002914: 699b ldr r3, [r3, #24] + 8002916: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 800291a: d121 bne.n 8002960 + 800291c: 68bb ldr r3, [r7, #8] + 800291e: 2b03 cmp r3, #3 + 8002920: d837 bhi.n 8002992 + 8002922: a201 add r2, pc, #4 @ (adr r2, 8002928 ) + 8002924: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002928: 08002939 .word 0x08002939 + 800292c: 0800293f .word 0x0800293f + 8002930: 08002939 .word 0x08002939 + 8002934: 08002951 .word 0x08002951 + 8002938: 2301 movs r3, #1 + 800293a: 73fb strb r3, [r7, #15] + 800293c: e030 b.n 80029a0 + 800293e: 687b ldr r3, [r7, #4] + 8002940: 6adb ldr r3, [r3, #44] @ 0x2c + 8002942: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 8002946: 2b00 cmp r3, #0 + 8002948: d025 beq.n 8002996 + 800294a: 2301 movs r3, #1 + 800294c: 73fb strb r3, [r7, #15] + 800294e: e022 b.n 8002996 + 8002950: 687b ldr r3, [r7, #4] + 8002952: 6adb ldr r3, [r3, #44] @ 0x2c + 8002954: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 + 8002958: d11f bne.n 800299a + 800295a: 2301 movs r3, #1 + 800295c: 73fb strb r3, [r7, #15] + 800295e: e01c b.n 800299a + 8002960: 68bb ldr r3, [r7, #8] + 8002962: 2b02 cmp r3, #2 + 8002964: d903 bls.n 800296e + 8002966: 68bb ldr r3, [r7, #8] + 8002968: 2b03 cmp r3, #3 + 800296a: d003 beq.n 8002974 + 800296c: e018 b.n 80029a0 + 800296e: 2301 movs r3, #1 + 8002970: 73fb strb r3, [r7, #15] + 8002972: e015 b.n 80029a0 + 8002974: 687b ldr r3, [r7, #4] + 8002976: 6adb ldr r3, [r3, #44] @ 0x2c + 8002978: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 800297c: 2b00 cmp r3, #0 + 800297e: d00e beq.n 800299e + 8002980: 2301 movs r3, #1 + 8002982: 73fb strb r3, [r7, #15] + 8002984: e00b b.n 800299e + 8002986: bf00 nop + 8002988: e00a b.n 80029a0 + 800298a: bf00 nop + 800298c: e008 b.n 80029a0 + 800298e: bf00 nop + 8002990: e006 b.n 80029a0 + 8002992: bf00 nop + 8002994: e004 b.n 80029a0 + 8002996: bf00 nop + 8002998: e002 b.n 80029a0 + 800299a: bf00 nop + 800299c: e000 b.n 80029a0 + 800299e: bf00 nop + 80029a0: 7bfb ldrb r3, [r7, #15] + 80029a2: 4618 mov r0, r3 + 80029a4: 3714 adds r7, #20 + 80029a6: 46bd mov sp, r7 + 80029a8: f85d 7b04 ldr.w r7, [sp], #4 + 80029ac: 4770 bx lr + 80029ae: bf00 nop + +080029b0 : + 80029b0: b480 push {r7} + 80029b2: b089 sub sp, #36 @ 0x24 + 80029b4: af00 add r7, sp, #0 + 80029b6: 6078 str r0, [r7, #4] + 80029b8: 6039 str r1, [r7, #0] + 80029ba: 2300 movs r3, #0 + 80029bc: 617b str r3, [r7, #20] + 80029be: 2300 movs r3, #0 + 80029c0: 613b str r3, [r7, #16] + 80029c2: 2300 movs r3, #0 + 80029c4: 61bb str r3, [r7, #24] + 80029c6: 2300 movs r3, #0 + 80029c8: 61fb str r3, [r7, #28] + 80029ca: e165 b.n 8002c98 + 80029cc: 2201 movs r2, #1 + 80029ce: 69fb ldr r3, [r7, #28] + 80029d0: fa02 f303 lsl.w r3, r2, r3 + 80029d4: 617b str r3, [r7, #20] + 80029d6: 683b ldr r3, [r7, #0] + 80029d8: 681b ldr r3, [r3, #0] + 80029da: 697a ldr r2, [r7, #20] + 80029dc: 4013 ands r3, r2 + 80029de: 613b str r3, [r7, #16] + 80029e0: 693a ldr r2, [r7, #16] + 80029e2: 697b ldr r3, [r7, #20] + 80029e4: 429a cmp r2, r3 + 80029e6: f040 8154 bne.w 8002c92 + 80029ea: 683b ldr r3, [r7, #0] + 80029ec: 685b ldr r3, [r3, #4] + 80029ee: f003 0303 and.w r3, r3, #3 + 80029f2: 2b01 cmp r3, #1 + 80029f4: d005 beq.n 8002a02 + 80029f6: 683b ldr r3, [r7, #0] + 80029f8: 685b ldr r3, [r3, #4] + 80029fa: f003 0303 and.w r3, r3, #3 + 80029fe: 2b02 cmp r3, #2 + 8002a00: d130 bne.n 8002a64 + 8002a02: 687b ldr r3, [r7, #4] + 8002a04: 689b ldr r3, [r3, #8] + 8002a06: 61bb str r3, [r7, #24] + 8002a08: 69fb ldr r3, [r7, #28] + 8002a0a: 005b lsls r3, r3, #1 + 8002a0c: 2203 movs r2, #3 + 8002a0e: fa02 f303 lsl.w r3, r2, r3 + 8002a12: 43db mvns r3, r3 + 8002a14: 69ba ldr r2, [r7, #24] + 8002a16: 4013 ands r3, r2 + 8002a18: 61bb str r3, [r7, #24] + 8002a1a: 683b ldr r3, [r7, #0] + 8002a1c: 68da ldr r2, [r3, #12] + 8002a1e: 69fb ldr r3, [r7, #28] + 8002a20: 005b lsls r3, r3, #1 + 8002a22: fa02 f303 lsl.w r3, r2, r3 + 8002a26: 69ba ldr r2, [r7, #24] + 8002a28: 4313 orrs r3, r2 + 8002a2a: 61bb str r3, [r7, #24] + 8002a2c: 687b ldr r3, [r7, #4] + 8002a2e: 69ba ldr r2, [r7, #24] + 8002a30: 609a str r2, [r3, #8] + 8002a32: 687b ldr r3, [r7, #4] + 8002a34: 685b ldr r3, [r3, #4] + 8002a36: 61bb str r3, [r7, #24] + 8002a38: 2201 movs r2, #1 + 8002a3a: 69fb ldr r3, [r7, #28] + 8002a3c: fa02 f303 lsl.w r3, r2, r3 + 8002a40: 43db mvns r3, r3 + 8002a42: 69ba ldr r2, [r7, #24] + 8002a44: 4013 ands r3, r2 + 8002a46: 61bb str r3, [r7, #24] + 8002a48: 683b ldr r3, [r7, #0] + 8002a4a: 685b ldr r3, [r3, #4] + 8002a4c: 091b lsrs r3, r3, #4 + 8002a4e: f003 0201 and.w r2, r3, #1 + 8002a52: 69fb ldr r3, [r7, #28] + 8002a54: fa02 f303 lsl.w r3, r2, r3 + 8002a58: 69ba ldr r2, [r7, #24] + 8002a5a: 4313 orrs r3, r2 + 8002a5c: 61bb str r3, [r7, #24] + 8002a5e: 687b ldr r3, [r7, #4] + 8002a60: 69ba ldr r2, [r7, #24] + 8002a62: 605a str r2, [r3, #4] + 8002a64: 683b ldr r3, [r7, #0] + 8002a66: 685b ldr r3, [r3, #4] + 8002a68: f003 0303 and.w r3, r3, #3 + 8002a6c: 2b03 cmp r3, #3 + 8002a6e: d017 beq.n 8002aa0 + 8002a70: 687b ldr r3, [r7, #4] + 8002a72: 68db ldr r3, [r3, #12] + 8002a74: 61bb str r3, [r7, #24] + 8002a76: 69fb ldr r3, [r7, #28] + 8002a78: 005b lsls r3, r3, #1 + 8002a7a: 2203 movs r2, #3 + 8002a7c: fa02 f303 lsl.w r3, r2, r3 + 8002a80: 43db mvns r3, r3 + 8002a82: 69ba ldr r2, [r7, #24] + 8002a84: 4013 ands r3, r2 + 8002a86: 61bb str r3, [r7, #24] + 8002a88: 683b ldr r3, [r7, #0] + 8002a8a: 689a ldr r2, [r3, #8] + 8002a8c: 69fb ldr r3, [r7, #28] + 8002a8e: 005b lsls r3, r3, #1 + 8002a90: fa02 f303 lsl.w r3, r2, r3 + 8002a94: 69ba ldr r2, [r7, #24] + 8002a96: 4313 orrs r3, r2 + 8002a98: 61bb str r3, [r7, #24] + 8002a9a: 687b ldr r3, [r7, #4] + 8002a9c: 69ba ldr r2, [r7, #24] + 8002a9e: 60da str r2, [r3, #12] + 8002aa0: 683b ldr r3, [r7, #0] + 8002aa2: 685b ldr r3, [r3, #4] + 8002aa4: f003 0303 and.w r3, r3, #3 + 8002aa8: 2b02 cmp r3, #2 + 8002aaa: d123 bne.n 8002af4 + 8002aac: 69fb ldr r3, [r7, #28] + 8002aae: 08da lsrs r2, r3, #3 + 8002ab0: 687b ldr r3, [r7, #4] + 8002ab2: 3208 adds r2, #8 + 8002ab4: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8002ab8: 61bb str r3, [r7, #24] + 8002aba: 69fb ldr r3, [r7, #28] + 8002abc: f003 0307 and.w r3, r3, #7 + 8002ac0: 009b lsls r3, r3, #2 + 8002ac2: 220f movs r2, #15 + 8002ac4: fa02 f303 lsl.w r3, r2, r3 + 8002ac8: 43db mvns r3, r3 + 8002aca: 69ba ldr r2, [r7, #24] + 8002acc: 4013 ands r3, r2 + 8002ace: 61bb str r3, [r7, #24] + 8002ad0: 683b ldr r3, [r7, #0] + 8002ad2: 691a ldr r2, [r3, #16] + 8002ad4: 69fb ldr r3, [r7, #28] + 8002ad6: f003 0307 and.w r3, r3, #7 + 8002ada: 009b lsls r3, r3, #2 + 8002adc: fa02 f303 lsl.w r3, r2, r3 + 8002ae0: 69ba ldr r2, [r7, #24] + 8002ae2: 4313 orrs r3, r2 + 8002ae4: 61bb str r3, [r7, #24] + 8002ae6: 69fb ldr r3, [r7, #28] + 8002ae8: 08da lsrs r2, r3, #3 + 8002aea: 687b ldr r3, [r7, #4] + 8002aec: 3208 adds r2, #8 + 8002aee: 69b9 ldr r1, [r7, #24] + 8002af0: f843 1022 str.w r1, [r3, r2, lsl #2] + 8002af4: 687b ldr r3, [r7, #4] + 8002af6: 681b ldr r3, [r3, #0] + 8002af8: 61bb str r3, [r7, #24] + 8002afa: 69fb ldr r3, [r7, #28] + 8002afc: 005b lsls r3, r3, #1 + 8002afe: 2203 movs r2, #3 + 8002b00: fa02 f303 lsl.w r3, r2, r3 + 8002b04: 43db mvns r3, r3 + 8002b06: 69ba ldr r2, [r7, #24] + 8002b08: 4013 ands r3, r2 + 8002b0a: 61bb str r3, [r7, #24] + 8002b0c: 683b ldr r3, [r7, #0] + 8002b0e: 685b ldr r3, [r3, #4] + 8002b10: f003 0203 and.w r2, r3, #3 + 8002b14: 69fb ldr r3, [r7, #28] + 8002b16: 005b lsls r3, r3, #1 + 8002b18: fa02 f303 lsl.w r3, r2, r3 + 8002b1c: 69ba ldr r2, [r7, #24] + 8002b1e: 4313 orrs r3, r2 + 8002b20: 61bb str r3, [r7, #24] + 8002b22: 687b ldr r3, [r7, #4] + 8002b24: 69ba ldr r2, [r7, #24] + 8002b26: 601a str r2, [r3, #0] + 8002b28: 683b ldr r3, [r7, #0] + 8002b2a: 685b ldr r3, [r3, #4] + 8002b2c: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8002b30: 2b00 cmp r3, #0 + 8002b32: f000 80ae beq.w 8002c92 + 8002b36: 2300 movs r3, #0 + 8002b38: 60fb str r3, [r7, #12] + 8002b3a: 4b5d ldr r3, [pc, #372] @ (8002cb0 ) + 8002b3c: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002b3e: 4a5c ldr r2, [pc, #368] @ (8002cb0 ) + 8002b40: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 8002b44: 6453 str r3, [r2, #68] @ 0x44 + 8002b46: 4b5a ldr r3, [pc, #360] @ (8002cb0 ) + 8002b48: 6c5b ldr r3, [r3, #68] @ 0x44 + 8002b4a: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8002b4e: 60fb str r3, [r7, #12] + 8002b50: 68fb ldr r3, [r7, #12] + 8002b52: 4a58 ldr r2, [pc, #352] @ (8002cb4 ) + 8002b54: 69fb ldr r3, [r7, #28] + 8002b56: 089b lsrs r3, r3, #2 + 8002b58: 3302 adds r3, #2 + 8002b5a: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002b5e: 61bb str r3, [r7, #24] + 8002b60: 69fb ldr r3, [r7, #28] + 8002b62: f003 0303 and.w r3, r3, #3 + 8002b66: 009b lsls r3, r3, #2 + 8002b68: 220f movs r2, #15 + 8002b6a: fa02 f303 lsl.w r3, r2, r3 + 8002b6e: 43db mvns r3, r3 + 8002b70: 69ba ldr r2, [r7, #24] + 8002b72: 4013 ands r3, r2 + 8002b74: 61bb str r3, [r7, #24] + 8002b76: 687b ldr r3, [r7, #4] + 8002b78: 4a4f ldr r2, [pc, #316] @ (8002cb8 ) + 8002b7a: 4293 cmp r3, r2 + 8002b7c: d025 beq.n 8002bca + 8002b7e: 687b ldr r3, [r7, #4] + 8002b80: 4a4e ldr r2, [pc, #312] @ (8002cbc ) + 8002b82: 4293 cmp r3, r2 + 8002b84: d01f beq.n 8002bc6 + 8002b86: 687b ldr r3, [r7, #4] + 8002b88: 4a4d ldr r2, [pc, #308] @ (8002cc0 ) + 8002b8a: 4293 cmp r3, r2 + 8002b8c: d019 beq.n 8002bc2 + 8002b8e: 687b ldr r3, [r7, #4] + 8002b90: 4a4c ldr r2, [pc, #304] @ (8002cc4 ) + 8002b92: 4293 cmp r3, r2 + 8002b94: d013 beq.n 8002bbe + 8002b96: 687b ldr r3, [r7, #4] + 8002b98: 4a4b ldr r2, [pc, #300] @ (8002cc8 ) + 8002b9a: 4293 cmp r3, r2 + 8002b9c: d00d beq.n 8002bba + 8002b9e: 687b ldr r3, [r7, #4] + 8002ba0: 4a4a ldr r2, [pc, #296] @ (8002ccc ) + 8002ba2: 4293 cmp r3, r2 + 8002ba4: d007 beq.n 8002bb6 + 8002ba6: 687b ldr r3, [r7, #4] + 8002ba8: 4a49 ldr r2, [pc, #292] @ (8002cd0 ) + 8002baa: 4293 cmp r3, r2 + 8002bac: d101 bne.n 8002bb2 + 8002bae: 2306 movs r3, #6 + 8002bb0: e00c b.n 8002bcc + 8002bb2: 2307 movs r3, #7 + 8002bb4: e00a b.n 8002bcc + 8002bb6: 2305 movs r3, #5 + 8002bb8: e008 b.n 8002bcc + 8002bba: 2304 movs r3, #4 + 8002bbc: e006 b.n 8002bcc + 8002bbe: 2303 movs r3, #3 + 8002bc0: e004 b.n 8002bcc + 8002bc2: 2302 movs r3, #2 + 8002bc4: e002 b.n 8002bcc + 8002bc6: 2301 movs r3, #1 + 8002bc8: e000 b.n 8002bcc + 8002bca: 2300 movs r3, #0 + 8002bcc: 69fa ldr r2, [r7, #28] + 8002bce: f002 0203 and.w r2, r2, #3 + 8002bd2: 0092 lsls r2, r2, #2 + 8002bd4: 4093 lsls r3, r2 + 8002bd6: 69ba ldr r2, [r7, #24] + 8002bd8: 4313 orrs r3, r2 + 8002bda: 61bb str r3, [r7, #24] + 8002bdc: 4935 ldr r1, [pc, #212] @ (8002cb4 ) + 8002bde: 69fb ldr r3, [r7, #28] + 8002be0: 089b lsrs r3, r3, #2 + 8002be2: 3302 adds r3, #2 + 8002be4: 69ba ldr r2, [r7, #24] + 8002be6: f841 2023 str.w r2, [r1, r3, lsl #2] + 8002bea: 4b3a ldr r3, [pc, #232] @ (8002cd4 ) + 8002bec: 689b ldr r3, [r3, #8] + 8002bee: 61bb str r3, [r7, #24] + 8002bf0: 693b ldr r3, [r7, #16] + 8002bf2: 43db mvns r3, r3 + 8002bf4: 69ba ldr r2, [r7, #24] + 8002bf6: 4013 ands r3, r2 + 8002bf8: 61bb str r3, [r7, #24] + 8002bfa: 683b ldr r3, [r7, #0] + 8002bfc: 685b ldr r3, [r3, #4] + 8002bfe: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8002c02: 2b00 cmp r3, #0 + 8002c04: d003 beq.n 8002c0e + 8002c06: 69ba ldr r2, [r7, #24] + 8002c08: 693b ldr r3, [r7, #16] + 8002c0a: 4313 orrs r3, r2 + 8002c0c: 61bb str r3, [r7, #24] + 8002c0e: 4a31 ldr r2, [pc, #196] @ (8002cd4 ) + 8002c10: 69bb ldr r3, [r7, #24] + 8002c12: 6093 str r3, [r2, #8] + 8002c14: 4b2f ldr r3, [pc, #188] @ (8002cd4 ) + 8002c16: 68db ldr r3, [r3, #12] + 8002c18: 61bb str r3, [r7, #24] + 8002c1a: 693b ldr r3, [r7, #16] + 8002c1c: 43db mvns r3, r3 + 8002c1e: 69ba ldr r2, [r7, #24] + 8002c20: 4013 ands r3, r2 + 8002c22: 61bb str r3, [r7, #24] + 8002c24: 683b ldr r3, [r7, #0] + 8002c26: 685b ldr r3, [r3, #4] + 8002c28: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8002c2c: 2b00 cmp r3, #0 + 8002c2e: d003 beq.n 8002c38 + 8002c30: 69ba ldr r2, [r7, #24] + 8002c32: 693b ldr r3, [r7, #16] + 8002c34: 4313 orrs r3, r2 + 8002c36: 61bb str r3, [r7, #24] + 8002c38: 4a26 ldr r2, [pc, #152] @ (8002cd4 ) + 8002c3a: 69bb ldr r3, [r7, #24] + 8002c3c: 60d3 str r3, [r2, #12] + 8002c3e: 4b25 ldr r3, [pc, #148] @ (8002cd4 ) + 8002c40: 685b ldr r3, [r3, #4] + 8002c42: 61bb str r3, [r7, #24] + 8002c44: 693b ldr r3, [r7, #16] + 8002c46: 43db mvns r3, r3 + 8002c48: 69ba ldr r2, [r7, #24] + 8002c4a: 4013 ands r3, r2 + 8002c4c: 61bb str r3, [r7, #24] + 8002c4e: 683b ldr r3, [r7, #0] + 8002c50: 685b ldr r3, [r3, #4] + 8002c52: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002c56: 2b00 cmp r3, #0 + 8002c58: d003 beq.n 8002c62 + 8002c5a: 69ba ldr r2, [r7, #24] + 8002c5c: 693b ldr r3, [r7, #16] + 8002c5e: 4313 orrs r3, r2 + 8002c60: 61bb str r3, [r7, #24] + 8002c62: 4a1c ldr r2, [pc, #112] @ (8002cd4 ) + 8002c64: 69bb ldr r3, [r7, #24] + 8002c66: 6053 str r3, [r2, #4] + 8002c68: 4b1a ldr r3, [pc, #104] @ (8002cd4 ) + 8002c6a: 681b ldr r3, [r3, #0] + 8002c6c: 61bb str r3, [r7, #24] + 8002c6e: 693b ldr r3, [r7, #16] + 8002c70: 43db mvns r3, r3 + 8002c72: 69ba ldr r2, [r7, #24] + 8002c74: 4013 ands r3, r2 + 8002c76: 61bb str r3, [r7, #24] + 8002c78: 683b ldr r3, [r7, #0] + 8002c7a: 685b ldr r3, [r3, #4] + 8002c7c: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002c80: 2b00 cmp r3, #0 + 8002c82: d003 beq.n 8002c8c + 8002c84: 69ba ldr r2, [r7, #24] + 8002c86: 693b ldr r3, [r7, #16] + 8002c88: 4313 orrs r3, r2 + 8002c8a: 61bb str r3, [r7, #24] + 8002c8c: 4a11 ldr r2, [pc, #68] @ (8002cd4 ) + 8002c8e: 69bb ldr r3, [r7, #24] + 8002c90: 6013 str r3, [r2, #0] + 8002c92: 69fb ldr r3, [r7, #28] + 8002c94: 3301 adds r3, #1 + 8002c96: 61fb str r3, [r7, #28] + 8002c98: 69fb ldr r3, [r7, #28] + 8002c9a: 2b0f cmp r3, #15 + 8002c9c: f67f ae96 bls.w 80029cc + 8002ca0: bf00 nop + 8002ca2: bf00 nop + 8002ca4: 3724 adds r7, #36 @ 0x24 + 8002ca6: 46bd mov sp, r7 + 8002ca8: f85d 7b04 ldr.w r7, [sp], #4 + 8002cac: 4770 bx lr + 8002cae: bf00 nop + 8002cb0: 40023800 .word 0x40023800 + 8002cb4: 40013800 .word 0x40013800 + 8002cb8: 40020000 .word 0x40020000 + 8002cbc: 40020400 .word 0x40020400 + 8002cc0: 40020800 .word 0x40020800 + 8002cc4: 40020c00 .word 0x40020c00 + 8002cc8: 40021000 .word 0x40021000 + 8002ccc: 40021400 .word 0x40021400 + 8002cd0: 40021800 .word 0x40021800 + 8002cd4: 40013c00 .word 0x40013c00 + +08002cd8 : + 8002cd8: b480 push {r7} + 8002cda: b085 sub sp, #20 + 8002cdc: af00 add r7, sp, #0 + 8002cde: 6078 str r0, [r7, #4] + 8002ce0: 460b mov r3, r1 + 8002ce2: 807b strh r3, [r7, #2] + 8002ce4: 687b ldr r3, [r7, #4] + 8002ce6: 691a ldr r2, [r3, #16] + 8002ce8: 887b ldrh r3, [r7, #2] + 8002cea: 4013 ands r3, r2 + 8002cec: 2b00 cmp r3, #0 + 8002cee: d002 beq.n 8002cf6 + 8002cf0: 2301 movs r3, #1 + 8002cf2: 73fb strb r3, [r7, #15] + 8002cf4: e001 b.n 8002cfa + 8002cf6: 2300 movs r3, #0 + 8002cf8: 73fb strb r3, [r7, #15] + 8002cfa: 7bfb ldrb r3, [r7, #15] + 8002cfc: 4618 mov r0, r3 + 8002cfe: 3714 adds r7, #20 + 8002d00: 46bd mov sp, r7 + 8002d02: f85d 7b04 ldr.w r7, [sp], #4 + 8002d06: 4770 bx lr + +08002d08 : + 8002d08: b480 push {r7} + 8002d0a: b083 sub sp, #12 + 8002d0c: af00 add r7, sp, #0 + 8002d0e: 6078 str r0, [r7, #4] + 8002d10: 460b mov r3, r1 + 8002d12: 807b strh r3, [r7, #2] + 8002d14: 4613 mov r3, r2 + 8002d16: 707b strb r3, [r7, #1] + 8002d18: 787b ldrb r3, [r7, #1] + 8002d1a: 2b00 cmp r3, #0 + 8002d1c: d003 beq.n 8002d26 + 8002d1e: 887a ldrh r2, [r7, #2] + 8002d20: 687b ldr r3, [r7, #4] + 8002d22: 619a str r2, [r3, #24] + 8002d24: e003 b.n 8002d2e + 8002d26: 887b ldrh r3, [r7, #2] + 8002d28: 041a lsls r2, r3, #16 + 8002d2a: 687b ldr r3, [r7, #4] + 8002d2c: 619a str r2, [r3, #24] + 8002d2e: bf00 nop + 8002d30: 370c adds r7, #12 + 8002d32: 46bd mov sp, r7 + 8002d34: f85d 7b04 ldr.w r7, [sp], #4 + 8002d38: 4770 bx lr + ... + +08002d3c : + 8002d3c: b580 push {r7, lr} + 8002d3e: b084 sub sp, #16 + 8002d40: af00 add r7, sp, #0 + 8002d42: 6078 str r0, [r7, #4] + 8002d44: 687b ldr r3, [r7, #4] + 8002d46: 2b00 cmp r3, #0 + 8002d48: d101 bne.n 8002d4e + 8002d4a: 2301 movs r3, #1 + 8002d4c: e12b b.n 8002fa6 + 8002d4e: 687b ldr r3, [r7, #4] + 8002d50: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 8002d54: b2db uxtb r3, r3 + 8002d56: 2b00 cmp r3, #0 + 8002d58: d106 bne.n 8002d68 + 8002d5a: 687b ldr r3, [r7, #4] + 8002d5c: 2200 movs r2, #0 + 8002d5e: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002d62: 6878 ldr r0, [r7, #4] + 8002d64: f7fd fd18 bl 8000798 + 8002d68: 687b ldr r3, [r7, #4] + 8002d6a: 2224 movs r2, #36 @ 0x24 + 8002d6c: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8002d70: 687b ldr r3, [r7, #4] + 8002d72: 681b ldr r3, [r3, #0] + 8002d74: 681a ldr r2, [r3, #0] + 8002d76: 687b ldr r3, [r7, #4] + 8002d78: 681b ldr r3, [r3, #0] + 8002d7a: f022 0201 bic.w r2, r2, #1 + 8002d7e: 601a str r2, [r3, #0] + 8002d80: 687b ldr r3, [r7, #4] + 8002d82: 681b ldr r3, [r3, #0] + 8002d84: 681a ldr r2, [r3, #0] + 8002d86: 687b ldr r3, [r7, #4] + 8002d88: 681b ldr r3, [r3, #0] + 8002d8a: f442 4200 orr.w r2, r2, #32768 @ 0x8000 + 8002d8e: 601a str r2, [r3, #0] + 8002d90: 687b ldr r3, [r7, #4] + 8002d92: 681b ldr r3, [r3, #0] + 8002d94: 681a ldr r2, [r3, #0] + 8002d96: 687b ldr r3, [r7, #4] + 8002d98: 681b ldr r3, [r3, #0] + 8002d9a: f422 4200 bic.w r2, r2, #32768 @ 0x8000 + 8002d9e: 601a str r2, [r3, #0] + 8002da0: f001 fc88 bl 80046b4 + 8002da4: 60f8 str r0, [r7, #12] + 8002da6: 687b ldr r3, [r7, #4] + 8002da8: 685b ldr r3, [r3, #4] + 8002daa: 4a81 ldr r2, [pc, #516] @ (8002fb0 ) + 8002dac: 4293 cmp r3, r2 + 8002dae: d807 bhi.n 8002dc0 + 8002db0: 68fb ldr r3, [r7, #12] + 8002db2: 4a80 ldr r2, [pc, #512] @ (8002fb4 ) + 8002db4: 4293 cmp r3, r2 + 8002db6: bf94 ite ls + 8002db8: 2301 movls r3, #1 + 8002dba: 2300 movhi r3, #0 + 8002dbc: b2db uxtb r3, r3 + 8002dbe: e006 b.n 8002dce + 8002dc0: 68fb ldr r3, [r7, #12] + 8002dc2: 4a7d ldr r2, [pc, #500] @ (8002fb8 ) + 8002dc4: 4293 cmp r3, r2 + 8002dc6: bf94 ite ls + 8002dc8: 2301 movls r3, #1 + 8002dca: 2300 movhi r3, #0 + 8002dcc: b2db uxtb r3, r3 + 8002dce: 2b00 cmp r3, #0 + 8002dd0: d001 beq.n 8002dd6 + 8002dd2: 2301 movs r3, #1 + 8002dd4: e0e7 b.n 8002fa6 + 8002dd6: 68fb ldr r3, [r7, #12] + 8002dd8: 4a78 ldr r2, [pc, #480] @ (8002fbc ) + 8002dda: fba2 2303 umull r2, r3, r2, r3 + 8002dde: 0c9b lsrs r3, r3, #18 + 8002de0: 60bb str r3, [r7, #8] + 8002de2: 687b ldr r3, [r7, #4] + 8002de4: 681b ldr r3, [r3, #0] + 8002de6: 685b ldr r3, [r3, #4] + 8002de8: f023 013f bic.w r1, r3, #63 @ 0x3f + 8002dec: 687b ldr r3, [r7, #4] + 8002dee: 681b ldr r3, [r3, #0] + 8002df0: 68ba ldr r2, [r7, #8] + 8002df2: 430a orrs r2, r1 + 8002df4: 605a str r2, [r3, #4] + 8002df6: 687b ldr r3, [r7, #4] + 8002df8: 681b ldr r3, [r3, #0] + 8002dfa: 6a1b ldr r3, [r3, #32] + 8002dfc: f023 013f bic.w r1, r3, #63 @ 0x3f + 8002e00: 687b ldr r3, [r7, #4] + 8002e02: 685b ldr r3, [r3, #4] + 8002e04: 4a6a ldr r2, [pc, #424] @ (8002fb0 ) + 8002e06: 4293 cmp r3, r2 + 8002e08: d802 bhi.n 8002e10 + 8002e0a: 68bb ldr r3, [r7, #8] + 8002e0c: 3301 adds r3, #1 + 8002e0e: e009 b.n 8002e24 + 8002e10: 68bb ldr r3, [r7, #8] + 8002e12: f44f 7296 mov.w r2, #300 @ 0x12c + 8002e16: fb02 f303 mul.w r3, r2, r3 + 8002e1a: 4a69 ldr r2, [pc, #420] @ (8002fc0 ) + 8002e1c: fba2 2303 umull r2, r3, r2, r3 + 8002e20: 099b lsrs r3, r3, #6 + 8002e22: 3301 adds r3, #1 + 8002e24: 687a ldr r2, [r7, #4] + 8002e26: 6812 ldr r2, [r2, #0] + 8002e28: 430b orrs r3, r1 + 8002e2a: 6213 str r3, [r2, #32] + 8002e2c: 687b ldr r3, [r7, #4] + 8002e2e: 681b ldr r3, [r3, #0] + 8002e30: 69db ldr r3, [r3, #28] + 8002e32: f423 424f bic.w r2, r3, #52992 @ 0xcf00 + 8002e36: f022 02ff bic.w r2, r2, #255 @ 0xff + 8002e3a: 687b ldr r3, [r7, #4] + 8002e3c: 685b ldr r3, [r3, #4] + 8002e3e: 495c ldr r1, [pc, #368] @ (8002fb0 ) + 8002e40: 428b cmp r3, r1 + 8002e42: d819 bhi.n 8002e78 + 8002e44: 68fb ldr r3, [r7, #12] + 8002e46: 1e59 subs r1, r3, #1 + 8002e48: 687b ldr r3, [r7, #4] + 8002e4a: 685b ldr r3, [r3, #4] + 8002e4c: 005b lsls r3, r3, #1 + 8002e4e: fbb1 f3f3 udiv r3, r1, r3 + 8002e52: 1c59 adds r1, r3, #1 + 8002e54: f640 73fc movw r3, #4092 @ 0xffc + 8002e58: 400b ands r3, r1 + 8002e5a: 2b00 cmp r3, #0 + 8002e5c: d00a beq.n 8002e74 + 8002e5e: 68fb ldr r3, [r7, #12] + 8002e60: 1e59 subs r1, r3, #1 + 8002e62: 687b ldr r3, [r7, #4] + 8002e64: 685b ldr r3, [r3, #4] + 8002e66: 005b lsls r3, r3, #1 + 8002e68: fbb1 f3f3 udiv r3, r1, r3 + 8002e6c: 3301 adds r3, #1 + 8002e6e: f3c3 030b ubfx r3, r3, #0, #12 + 8002e72: e051 b.n 8002f18 + 8002e74: 2304 movs r3, #4 + 8002e76: e04f b.n 8002f18 + 8002e78: 687b ldr r3, [r7, #4] + 8002e7a: 689b ldr r3, [r3, #8] + 8002e7c: 2b00 cmp r3, #0 + 8002e7e: d111 bne.n 8002ea4 + 8002e80: 68fb ldr r3, [r7, #12] + 8002e82: 1e58 subs r0, r3, #1 + 8002e84: 687b ldr r3, [r7, #4] + 8002e86: 6859 ldr r1, [r3, #4] + 8002e88: 460b mov r3, r1 + 8002e8a: 005b lsls r3, r3, #1 + 8002e8c: 440b add r3, r1 + 8002e8e: fbb0 f3f3 udiv r3, r0, r3 + 8002e92: 3301 adds r3, #1 + 8002e94: f3c3 030b ubfx r3, r3, #0, #12 + 8002e98: 2b00 cmp r3, #0 + 8002e9a: bf0c ite eq + 8002e9c: 2301 moveq r3, #1 + 8002e9e: 2300 movne r3, #0 + 8002ea0: b2db uxtb r3, r3 + 8002ea2: e012 b.n 8002eca + 8002ea4: 68fb ldr r3, [r7, #12] + 8002ea6: 1e58 subs r0, r3, #1 + 8002ea8: 687b ldr r3, [r7, #4] + 8002eaa: 6859 ldr r1, [r3, #4] + 8002eac: 460b mov r3, r1 + 8002eae: 009b lsls r3, r3, #2 + 8002eb0: 440b add r3, r1 + 8002eb2: 0099 lsls r1, r3, #2 + 8002eb4: 440b add r3, r1 + 8002eb6: fbb0 f3f3 udiv r3, r0, r3 + 8002eba: 3301 adds r3, #1 + 8002ebc: f3c3 030b ubfx r3, r3, #0, #12 + 8002ec0: 2b00 cmp r3, #0 + 8002ec2: bf0c ite eq + 8002ec4: 2301 moveq r3, #1 + 8002ec6: 2300 movne r3, #0 + 8002ec8: b2db uxtb r3, r3 + 8002eca: 2b00 cmp r3, #0 + 8002ecc: d001 beq.n 8002ed2 + 8002ece: 2301 movs r3, #1 + 8002ed0: e022 b.n 8002f18 + 8002ed2: 687b ldr r3, [r7, #4] + 8002ed4: 689b ldr r3, [r3, #8] + 8002ed6: 2b00 cmp r3, #0 + 8002ed8: d10e bne.n 8002ef8 + 8002eda: 68fb ldr r3, [r7, #12] + 8002edc: 1e58 subs r0, r3, #1 + 8002ede: 687b ldr r3, [r7, #4] + 8002ee0: 6859 ldr r1, [r3, #4] + 8002ee2: 460b mov r3, r1 + 8002ee4: 005b lsls r3, r3, #1 + 8002ee6: 440b add r3, r1 + 8002ee8: fbb0 f3f3 udiv r3, r0, r3 + 8002eec: 3301 adds r3, #1 + 8002eee: f3c3 030b ubfx r3, r3, #0, #12 + 8002ef2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 8002ef6: e00f b.n 8002f18 + 8002ef8: 68fb ldr r3, [r7, #12] + 8002efa: 1e58 subs r0, r3, #1 + 8002efc: 687b ldr r3, [r7, #4] + 8002efe: 6859 ldr r1, [r3, #4] + 8002f00: 460b mov r3, r1 + 8002f02: 009b lsls r3, r3, #2 + 8002f04: 440b add r3, r1 + 8002f06: 0099 lsls r1, r3, #2 + 8002f08: 440b add r3, r1 + 8002f0a: fbb0 f3f3 udiv r3, r0, r3 + 8002f0e: 3301 adds r3, #1 + 8002f10: f3c3 030b ubfx r3, r3, #0, #12 + 8002f14: f443 4340 orr.w r3, r3, #49152 @ 0xc000 + 8002f18: 6879 ldr r1, [r7, #4] + 8002f1a: 6809 ldr r1, [r1, #0] + 8002f1c: 4313 orrs r3, r2 + 8002f1e: 61cb str r3, [r1, #28] + 8002f20: 687b ldr r3, [r7, #4] + 8002f22: 681b ldr r3, [r3, #0] + 8002f24: 681b ldr r3, [r3, #0] + 8002f26: f023 01c0 bic.w r1, r3, #192 @ 0xc0 + 8002f2a: 687b ldr r3, [r7, #4] + 8002f2c: 69da ldr r2, [r3, #28] + 8002f2e: 687b ldr r3, [r7, #4] + 8002f30: 6a1b ldr r3, [r3, #32] + 8002f32: 431a orrs r2, r3 + 8002f34: 687b ldr r3, [r7, #4] + 8002f36: 681b ldr r3, [r3, #0] + 8002f38: 430a orrs r2, r1 + 8002f3a: 601a str r2, [r3, #0] + 8002f3c: 687b ldr r3, [r7, #4] + 8002f3e: 681b ldr r3, [r3, #0] + 8002f40: 689b ldr r3, [r3, #8] + 8002f42: f423 4303 bic.w r3, r3, #33536 @ 0x8300 + 8002f46: f023 03ff bic.w r3, r3, #255 @ 0xff + 8002f4a: 687a ldr r2, [r7, #4] + 8002f4c: 6911 ldr r1, [r2, #16] + 8002f4e: 687a ldr r2, [r7, #4] + 8002f50: 68d2 ldr r2, [r2, #12] + 8002f52: 4311 orrs r1, r2 + 8002f54: 687a ldr r2, [r7, #4] + 8002f56: 6812 ldr r2, [r2, #0] + 8002f58: 430b orrs r3, r1 + 8002f5a: 6093 str r3, [r2, #8] + 8002f5c: 687b ldr r3, [r7, #4] + 8002f5e: 681b ldr r3, [r3, #0] + 8002f60: 68db ldr r3, [r3, #12] + 8002f62: f023 01ff bic.w r1, r3, #255 @ 0xff + 8002f66: 687b ldr r3, [r7, #4] + 8002f68: 695a ldr r2, [r3, #20] + 8002f6a: 687b ldr r3, [r7, #4] + 8002f6c: 699b ldr r3, [r3, #24] + 8002f6e: 431a orrs r2, r3 + 8002f70: 687b ldr r3, [r7, #4] + 8002f72: 681b ldr r3, [r3, #0] + 8002f74: 430a orrs r2, r1 + 8002f76: 60da str r2, [r3, #12] + 8002f78: 687b ldr r3, [r7, #4] + 8002f7a: 681b ldr r3, [r3, #0] + 8002f7c: 681a ldr r2, [r3, #0] + 8002f7e: 687b ldr r3, [r7, #4] + 8002f80: 681b ldr r3, [r3, #0] + 8002f82: f042 0201 orr.w r2, r2, #1 + 8002f86: 601a str r2, [r3, #0] + 8002f88: 687b ldr r3, [r7, #4] + 8002f8a: 2200 movs r2, #0 + 8002f8c: 641a str r2, [r3, #64] @ 0x40 + 8002f8e: 687b ldr r3, [r7, #4] + 8002f90: 2220 movs r2, #32 + 8002f92: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8002f96: 687b ldr r3, [r7, #4] + 8002f98: 2200 movs r2, #0 + 8002f9a: 631a str r2, [r3, #48] @ 0x30 + 8002f9c: 687b ldr r3, [r7, #4] + 8002f9e: 2200 movs r2, #0 + 8002fa0: f883 203e strb.w r2, [r3, #62] @ 0x3e + 8002fa4: 2300 movs r3, #0 + 8002fa6: 4618 mov r0, r3 + 8002fa8: 3710 adds r7, #16 + 8002faa: 46bd mov sp, r7 + 8002fac: bd80 pop {r7, pc} + 8002fae: bf00 nop + 8002fb0: 000186a0 .word 0x000186a0 + 8002fb4: 001e847f .word 0x001e847f + 8002fb8: 003d08ff .word 0x003d08ff + 8002fbc: 431bde83 .word 0x431bde83 + 8002fc0: 10624dd3 .word 0x10624dd3 + +08002fc4 : + 8002fc4: b580 push {r7, lr} + 8002fc6: b086 sub sp, #24 + 8002fc8: af02 add r7, sp, #8 + 8002fca: 6078 str r0, [r7, #4] + 8002fcc: 687b ldr r3, [r7, #4] + 8002fce: 2b00 cmp r3, #0 + 8002fd0: d101 bne.n 8002fd6 + 8002fd2: 2301 movs r3, #1 + 8002fd4: e108 b.n 80031e8 + 8002fd6: 687b ldr r3, [r7, #4] + 8002fd8: 681b ldr r3, [r3, #0] + 8002fda: 60bb str r3, [r7, #8] + 8002fdc: 687b ldr r3, [r7, #4] + 8002fde: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495 + 8002fe2: b2db uxtb r3, r3 + 8002fe4: 2b00 cmp r3, #0 + 8002fe6: d106 bne.n 8002ff6 + 8002fe8: 687b ldr r3, [r7, #4] + 8002fea: 2200 movs r2, #0 + 8002fec: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8002ff0: 6878 ldr r0, [r7, #4] + 8002ff2: f007 fe47 bl 800ac84 + 8002ff6: 687b ldr r3, [r7, #4] + 8002ff8: 2203 movs r2, #3 + 8002ffa: f883 2495 strb.w r2, [r3, #1173] @ 0x495 + 8002ffe: 68bb ldr r3, [r7, #8] + 8003000: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8003004: d102 bne.n 800300c + 8003006: 687b ldr r3, [r7, #4] + 8003008: 2200 movs r2, #0 + 800300a: 719a strb r2, [r3, #6] + 800300c: 687b ldr r3, [r7, #4] + 800300e: 681b ldr r3, [r3, #0] + 8003010: 4618 mov r0, r3 + 8003012: f004 fd3c bl 8007a8e + 8003016: 687b ldr r3, [r7, #4] + 8003018: 6818 ldr r0, [r3, #0] + 800301a: 687b ldr r3, [r7, #4] + 800301c: 7c1a ldrb r2, [r3, #16] + 800301e: f88d 2000 strb.w r2, [sp] + 8003022: 3304 adds r3, #4 + 8003024: cb0e ldmia r3, {r1, r2, r3} + 8003026: f004 fc1b bl 8007860 + 800302a: 4603 mov r3, r0 + 800302c: 2b00 cmp r3, #0 + 800302e: d005 beq.n 800303c + 8003030: 687b ldr r3, [r7, #4] + 8003032: 2202 movs r2, #2 + 8003034: f883 2495 strb.w r2, [r3, #1173] @ 0x495 + 8003038: 2301 movs r3, #1 + 800303a: e0d5 b.n 80031e8 + 800303c: 687b ldr r3, [r7, #4] + 800303e: 681b ldr r3, [r3, #0] + 8003040: 2100 movs r1, #0 + 8003042: 4618 mov r0, r3 + 8003044: f004 fd34 bl 8007ab0 + 8003048: 4603 mov r3, r0 + 800304a: 2b00 cmp r3, #0 + 800304c: d005 beq.n 800305a + 800304e: 687b ldr r3, [r7, #4] + 8003050: 2202 movs r2, #2 + 8003052: f883 2495 strb.w r2, [r3, #1173] @ 0x495 + 8003056: 2301 movs r3, #1 + 8003058: e0c6 b.n 80031e8 + 800305a: 2300 movs r3, #0 + 800305c: 73fb strb r3, [r7, #15] + 800305e: e04a b.n 80030f6 + 8003060: 7bfa ldrb r2, [r7, #15] + 8003062: 6879 ldr r1, [r7, #4] + 8003064: 4613 mov r3, r2 + 8003066: 00db lsls r3, r3, #3 + 8003068: 4413 add r3, r2 + 800306a: 009b lsls r3, r3, #2 + 800306c: 440b add r3, r1 + 800306e: 3315 adds r3, #21 + 8003070: 2201 movs r2, #1 + 8003072: 701a strb r2, [r3, #0] + 8003074: 7bfa ldrb r2, [r7, #15] + 8003076: 6879 ldr r1, [r7, #4] + 8003078: 4613 mov r3, r2 + 800307a: 00db lsls r3, r3, #3 + 800307c: 4413 add r3, r2 + 800307e: 009b lsls r3, r3, #2 + 8003080: 440b add r3, r1 + 8003082: 3314 adds r3, #20 + 8003084: 7bfa ldrb r2, [r7, #15] + 8003086: 701a strb r2, [r3, #0] + 8003088: 7bfa ldrb r2, [r7, #15] + 800308a: 7bfb ldrb r3, [r7, #15] + 800308c: b298 uxth r0, r3 + 800308e: 6879 ldr r1, [r7, #4] + 8003090: 4613 mov r3, r2 + 8003092: 00db lsls r3, r3, #3 + 8003094: 4413 add r3, r2 + 8003096: 009b lsls r3, r3, #2 + 8003098: 440b add r3, r1 + 800309a: 332e adds r3, #46 @ 0x2e + 800309c: 4602 mov r2, r0 + 800309e: 801a strh r2, [r3, #0] + 80030a0: 7bfa ldrb r2, [r7, #15] + 80030a2: 6879 ldr r1, [r7, #4] + 80030a4: 4613 mov r3, r2 + 80030a6: 00db lsls r3, r3, #3 + 80030a8: 4413 add r3, r2 + 80030aa: 009b lsls r3, r3, #2 + 80030ac: 440b add r3, r1 + 80030ae: 3318 adds r3, #24 + 80030b0: 2200 movs r2, #0 + 80030b2: 701a strb r2, [r3, #0] + 80030b4: 7bfa ldrb r2, [r7, #15] + 80030b6: 6879 ldr r1, [r7, #4] + 80030b8: 4613 mov r3, r2 + 80030ba: 00db lsls r3, r3, #3 + 80030bc: 4413 add r3, r2 + 80030be: 009b lsls r3, r3, #2 + 80030c0: 440b add r3, r1 + 80030c2: 331c adds r3, #28 + 80030c4: 2200 movs r2, #0 + 80030c6: 601a str r2, [r3, #0] + 80030c8: 7bfa ldrb r2, [r7, #15] + 80030ca: 6879 ldr r1, [r7, #4] + 80030cc: 4613 mov r3, r2 + 80030ce: 00db lsls r3, r3, #3 + 80030d0: 4413 add r3, r2 + 80030d2: 009b lsls r3, r3, #2 + 80030d4: 440b add r3, r1 + 80030d6: 3320 adds r3, #32 + 80030d8: 2200 movs r2, #0 + 80030da: 601a str r2, [r3, #0] + 80030dc: 7bfa ldrb r2, [r7, #15] + 80030de: 6879 ldr r1, [r7, #4] + 80030e0: 4613 mov r3, r2 + 80030e2: 00db lsls r3, r3, #3 + 80030e4: 4413 add r3, r2 + 80030e6: 009b lsls r3, r3, #2 + 80030e8: 440b add r3, r1 + 80030ea: 3324 adds r3, #36 @ 0x24 + 80030ec: 2200 movs r2, #0 + 80030ee: 601a str r2, [r3, #0] + 80030f0: 7bfb ldrb r3, [r7, #15] + 80030f2: 3301 adds r3, #1 + 80030f4: 73fb strb r3, [r7, #15] + 80030f6: 687b ldr r3, [r7, #4] + 80030f8: 791b ldrb r3, [r3, #4] + 80030fa: 7bfa ldrb r2, [r7, #15] + 80030fc: 429a cmp r2, r3 + 80030fe: d3af bcc.n 8003060 + 8003100: 2300 movs r3, #0 + 8003102: 73fb strb r3, [r7, #15] + 8003104: e044 b.n 8003190 + 8003106: 7bfa ldrb r2, [r7, #15] + 8003108: 6879 ldr r1, [r7, #4] + 800310a: 4613 mov r3, r2 + 800310c: 00db lsls r3, r3, #3 + 800310e: 4413 add r3, r2 + 8003110: 009b lsls r3, r3, #2 + 8003112: 440b add r3, r1 + 8003114: f203 2355 addw r3, r3, #597 @ 0x255 + 8003118: 2200 movs r2, #0 + 800311a: 701a strb r2, [r3, #0] + 800311c: 7bfa ldrb r2, [r7, #15] + 800311e: 6879 ldr r1, [r7, #4] + 8003120: 4613 mov r3, r2 + 8003122: 00db lsls r3, r3, #3 + 8003124: 4413 add r3, r2 + 8003126: 009b lsls r3, r3, #2 + 8003128: 440b add r3, r1 + 800312a: f503 7315 add.w r3, r3, #596 @ 0x254 + 800312e: 7bfa ldrb r2, [r7, #15] + 8003130: 701a strb r2, [r3, #0] + 8003132: 7bfa ldrb r2, [r7, #15] + 8003134: 6879 ldr r1, [r7, #4] + 8003136: 4613 mov r3, r2 + 8003138: 00db lsls r3, r3, #3 + 800313a: 4413 add r3, r2 + 800313c: 009b lsls r3, r3, #2 + 800313e: 440b add r3, r1 + 8003140: f503 7316 add.w r3, r3, #600 @ 0x258 + 8003144: 2200 movs r2, #0 + 8003146: 701a strb r2, [r3, #0] + 8003148: 7bfa ldrb r2, [r7, #15] + 800314a: 6879 ldr r1, [r7, #4] + 800314c: 4613 mov r3, r2 + 800314e: 00db lsls r3, r3, #3 + 8003150: 4413 add r3, r2 + 8003152: 009b lsls r3, r3, #2 + 8003154: 440b add r3, r1 + 8003156: f503 7317 add.w r3, r3, #604 @ 0x25c + 800315a: 2200 movs r2, #0 + 800315c: 601a str r2, [r3, #0] + 800315e: 7bfa ldrb r2, [r7, #15] + 8003160: 6879 ldr r1, [r7, #4] + 8003162: 4613 mov r3, r2 + 8003164: 00db lsls r3, r3, #3 + 8003166: 4413 add r3, r2 + 8003168: 009b lsls r3, r3, #2 + 800316a: 440b add r3, r1 + 800316c: f503 7318 add.w r3, r3, #608 @ 0x260 + 8003170: 2200 movs r2, #0 + 8003172: 601a str r2, [r3, #0] + 8003174: 7bfa ldrb r2, [r7, #15] + 8003176: 6879 ldr r1, [r7, #4] + 8003178: 4613 mov r3, r2 + 800317a: 00db lsls r3, r3, #3 + 800317c: 4413 add r3, r2 + 800317e: 009b lsls r3, r3, #2 + 8003180: 440b add r3, r1 + 8003182: f503 7319 add.w r3, r3, #612 @ 0x264 + 8003186: 2200 movs r2, #0 + 8003188: 601a str r2, [r3, #0] + 800318a: 7bfb ldrb r3, [r7, #15] + 800318c: 3301 adds r3, #1 + 800318e: 73fb strb r3, [r7, #15] + 8003190: 687b ldr r3, [r7, #4] + 8003192: 791b ldrb r3, [r3, #4] + 8003194: 7bfa ldrb r2, [r7, #15] + 8003196: 429a cmp r2, r3 + 8003198: d3b5 bcc.n 8003106 + 800319a: 687b ldr r3, [r7, #4] + 800319c: 6818 ldr r0, [r3, #0] + 800319e: 687b ldr r3, [r7, #4] + 80031a0: 7c1a ldrb r2, [r3, #16] + 80031a2: f88d 2000 strb.w r2, [sp] + 80031a6: 3304 adds r3, #4 + 80031a8: cb0e ldmia r3, {r1, r2, r3} + 80031aa: f004 fccd bl 8007b48 + 80031ae: 4603 mov r3, r0 + 80031b0: 2b00 cmp r3, #0 + 80031b2: d005 beq.n 80031c0 + 80031b4: 687b ldr r3, [r7, #4] + 80031b6: 2202 movs r2, #2 + 80031b8: f883 2495 strb.w r2, [r3, #1173] @ 0x495 + 80031bc: 2301 movs r3, #1 + 80031be: e013 b.n 80031e8 + 80031c0: 687b ldr r3, [r7, #4] + 80031c2: 2200 movs r2, #0 + 80031c4: 745a strb r2, [r3, #17] + 80031c6: 687b ldr r3, [r7, #4] + 80031c8: 2201 movs r2, #1 + 80031ca: f883 2495 strb.w r2, [r3, #1173] @ 0x495 + 80031ce: 687b ldr r3, [r7, #4] + 80031d0: 7b1b ldrb r3, [r3, #12] + 80031d2: 2b01 cmp r3, #1 + 80031d4: d102 bne.n 80031dc + 80031d6: 6878 ldr r0, [r7, #4] + 80031d8: f001 f956 bl 8004488 + 80031dc: 687b ldr r3, [r7, #4] + 80031de: 681b ldr r3, [r3, #0] + 80031e0: 4618 mov r0, r3 + 80031e2: f005 fd0a bl 8008bfa + 80031e6: 2300 movs r3, #0 + 80031e8: 4618 mov r0, r3 + 80031ea: 3710 adds r7, #16 + 80031ec: 46bd mov sp, r7 + 80031ee: bd80 pop {r7, pc} + +080031f0 : + 80031f0: b580 push {r7, lr} + 80031f2: b084 sub sp, #16 + 80031f4: af00 add r7, sp, #0 + 80031f6: 6078 str r0, [r7, #4] + 80031f8: 687b ldr r3, [r7, #4] + 80031fa: 681b ldr r3, [r3, #0] + 80031fc: 60fb str r3, [r7, #12] + 80031fe: 687b ldr r3, [r7, #4] + 8003200: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 + 8003204: 2b01 cmp r3, #1 + 8003206: d101 bne.n 800320c + 8003208: 2302 movs r3, #2 + 800320a: e022 b.n 8003252 + 800320c: 687b ldr r3, [r7, #4] + 800320e: 2201 movs r2, #1 + 8003210: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003214: 68fb ldr r3, [r7, #12] + 8003216: 68db ldr r3, [r3, #12] + 8003218: f003 0340 and.w r3, r3, #64 @ 0x40 + 800321c: 2b00 cmp r3, #0 + 800321e: d009 beq.n 8003234 + 8003220: 687b ldr r3, [r7, #4] + 8003222: 7b5b ldrb r3, [r3, #13] + 8003224: 2b01 cmp r3, #1 + 8003226: d105 bne.n 8003234 + 8003228: 68fb ldr r3, [r7, #12] + 800322a: 6b9b ldr r3, [r3, #56] @ 0x38 + 800322c: f443 3280 orr.w r2, r3, #65536 @ 0x10000 + 8003230: 68fb ldr r3, [r7, #12] + 8003232: 639a str r2, [r3, #56] @ 0x38 + 8003234: 687b ldr r3, [r7, #4] + 8003236: 681b ldr r3, [r3, #0] + 8003238: 4618 mov r0, r3 + 800323a: f004 fc17 bl 8007a6c + 800323e: 687b ldr r3, [r7, #4] + 8003240: 681b ldr r3, [r3, #0] + 8003242: 4618 mov r0, r3 + 8003244: f005 fcb8 bl 8008bb8 + 8003248: 687b ldr r3, [r7, #4] + 800324a: 2200 movs r2, #0 + 800324c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003250: 2300 movs r3, #0 + 8003252: 4618 mov r0, r3 + 8003254: 3710 adds r7, #16 + 8003256: 46bd mov sp, r7 + 8003258: bd80 pop {r7, pc} + +0800325a : + 800325a: b590 push {r4, r7, lr} + 800325c: b08d sub sp, #52 @ 0x34 + 800325e: af00 add r7, sp, #0 + 8003260: 6078 str r0, [r7, #4] + 8003262: 687b ldr r3, [r7, #4] + 8003264: 681b ldr r3, [r3, #0] + 8003266: 623b str r3, [r7, #32] + 8003268: 6a3b ldr r3, [r7, #32] + 800326a: 61fb str r3, [r7, #28] + 800326c: 687b ldr r3, [r7, #4] + 800326e: 681b ldr r3, [r3, #0] + 8003270: 4618 mov r0, r3 + 8003272: f005 fd76 bl 8008d62 + 8003276: 4603 mov r3, r0 + 8003278: 2b00 cmp r3, #0 + 800327a: f040 84b9 bne.w 8003bf0 + 800327e: 687b ldr r3, [r7, #4] + 8003280: 681b ldr r3, [r3, #0] + 8003282: 4618 mov r0, r3 + 8003284: f005 fcda bl 8008c3c + 8003288: 4603 mov r3, r0 + 800328a: 2b00 cmp r3, #0 + 800328c: f000 84af beq.w 8003bee + 8003290: 69fb ldr r3, [r7, #28] + 8003292: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8003296: 689b ldr r3, [r3, #8] + 8003298: 0a1b lsrs r3, r3, #8 + 800329a: f3c3 020d ubfx r2, r3, #0, #14 + 800329e: 687b ldr r3, [r7, #4] + 80032a0: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4 + 80032a4: 687b ldr r3, [r7, #4] + 80032a6: 681b ldr r3, [r3, #0] + 80032a8: 4618 mov r0, r3 + 80032aa: f005 fcc7 bl 8008c3c + 80032ae: 4603 mov r3, r0 + 80032b0: f003 0302 and.w r3, r3, #2 + 80032b4: 2b02 cmp r3, #2 + 80032b6: d107 bne.n 80032c8 + 80032b8: 687b ldr r3, [r7, #4] + 80032ba: 681b ldr r3, [r3, #0] + 80032bc: 695a ldr r2, [r3, #20] + 80032be: 687b ldr r3, [r7, #4] + 80032c0: 681b ldr r3, [r3, #0] + 80032c2: f002 0202 and.w r2, r2, #2 + 80032c6: 615a str r2, [r3, #20] + 80032c8: 687b ldr r3, [r7, #4] + 80032ca: 681b ldr r3, [r3, #0] + 80032cc: 4618 mov r0, r3 + 80032ce: f005 fcb5 bl 8008c3c + 80032d2: 4603 mov r3, r0 + 80032d4: f003 0310 and.w r3, r3, #16 + 80032d8: 2b10 cmp r3, #16 + 80032da: d161 bne.n 80033a0 + 80032dc: 687b ldr r3, [r7, #4] + 80032de: 681b ldr r3, [r3, #0] + 80032e0: 699a ldr r2, [r3, #24] + 80032e2: 687b ldr r3, [r7, #4] + 80032e4: 681b ldr r3, [r3, #0] + 80032e6: f022 0210 bic.w r2, r2, #16 + 80032ea: 619a str r2, [r3, #24] + 80032ec: 6a3b ldr r3, [r7, #32] + 80032ee: 6a1b ldr r3, [r3, #32] + 80032f0: 61bb str r3, [r7, #24] + 80032f2: 69bb ldr r3, [r7, #24] + 80032f4: f003 020f and.w r2, r3, #15 + 80032f8: 4613 mov r3, r2 + 80032fa: 00db lsls r3, r3, #3 + 80032fc: 4413 add r3, r2 + 80032fe: 009b lsls r3, r3, #2 + 8003300: f503 7314 add.w r3, r3, #592 @ 0x250 + 8003304: 687a ldr r2, [r7, #4] + 8003306: 4413 add r3, r2 + 8003308: 3304 adds r3, #4 + 800330a: 617b str r3, [r7, #20] + 800330c: 69bb ldr r3, [r7, #24] + 800330e: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 + 8003312: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 + 8003316: d124 bne.n 8003362 + 8003318: 69ba ldr r2, [r7, #24] + 800331a: f647 73f0 movw r3, #32752 @ 0x7ff0 + 800331e: 4013 ands r3, r2 + 8003320: 2b00 cmp r3, #0 + 8003322: d035 beq.n 8003390 + 8003324: 697b ldr r3, [r7, #20] + 8003326: 68d9 ldr r1, [r3, #12] + 8003328: 69bb ldr r3, [r7, #24] + 800332a: 091b lsrs r3, r3, #4 + 800332c: b29b uxth r3, r3 + 800332e: f3c3 030a ubfx r3, r3, #0, #11 + 8003332: b29b uxth r3, r3 + 8003334: 461a mov r2, r3 + 8003336: 6a38 ldr r0, [r7, #32] + 8003338: f005 faec bl 8008914 + 800333c: 697b ldr r3, [r7, #20] + 800333e: 68da ldr r2, [r3, #12] + 8003340: 69bb ldr r3, [r7, #24] + 8003342: 091b lsrs r3, r3, #4 + 8003344: f3c3 030a ubfx r3, r3, #0, #11 + 8003348: 441a add r2, r3 + 800334a: 697b ldr r3, [r7, #20] + 800334c: 60da str r2, [r3, #12] + 800334e: 697b ldr r3, [r7, #20] + 8003350: 695a ldr r2, [r3, #20] + 8003352: 69bb ldr r3, [r7, #24] + 8003354: 091b lsrs r3, r3, #4 + 8003356: f3c3 030a ubfx r3, r3, #0, #11 + 800335a: 441a add r2, r3 + 800335c: 697b ldr r3, [r7, #20] + 800335e: 615a str r2, [r3, #20] + 8003360: e016 b.n 8003390 + 8003362: 69bb ldr r3, [r7, #24] + 8003364: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 + 8003368: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 + 800336c: d110 bne.n 8003390 + 800336e: 687b ldr r3, [r7, #4] + 8003370: f203 439c addw r3, r3, #1180 @ 0x49c + 8003374: 2208 movs r2, #8 + 8003376: 4619 mov r1, r3 + 8003378: 6a38 ldr r0, [r7, #32] + 800337a: f005 facb bl 8008914 + 800337e: 697b ldr r3, [r7, #20] + 8003380: 695a ldr r2, [r3, #20] + 8003382: 69bb ldr r3, [r7, #24] + 8003384: 091b lsrs r3, r3, #4 + 8003386: f3c3 030a ubfx r3, r3, #0, #11 + 800338a: 441a add r2, r3 + 800338c: 697b ldr r3, [r7, #20] + 800338e: 615a str r2, [r3, #20] + 8003390: 687b ldr r3, [r7, #4] + 8003392: 681b ldr r3, [r3, #0] + 8003394: 699a ldr r2, [r3, #24] + 8003396: 687b ldr r3, [r7, #4] + 8003398: 681b ldr r3, [r3, #0] + 800339a: f042 0210 orr.w r2, r2, #16 + 800339e: 619a str r2, [r3, #24] + 80033a0: 687b ldr r3, [r7, #4] + 80033a2: 681b ldr r3, [r3, #0] + 80033a4: 4618 mov r0, r3 + 80033a6: f005 fc49 bl 8008c3c + 80033aa: 4603 mov r3, r0 + 80033ac: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 80033b0: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 + 80033b4: f040 80a7 bne.w 8003506 + 80033b8: 2300 movs r3, #0 + 80033ba: 627b str r3, [r7, #36] @ 0x24 + 80033bc: 687b ldr r3, [r7, #4] + 80033be: 681b ldr r3, [r3, #0] + 80033c0: 4618 mov r0, r3 + 80033c2: f005 fc4e bl 8008c62 + 80033c6: 62b8 str r0, [r7, #40] @ 0x28 + 80033c8: e099 b.n 80034fe + 80033ca: 6abb ldr r3, [r7, #40] @ 0x28 + 80033cc: f003 0301 and.w r3, r3, #1 + 80033d0: 2b00 cmp r3, #0 + 80033d2: f000 808e beq.w 80034f2 + 80033d6: 687b ldr r3, [r7, #4] + 80033d8: 681b ldr r3, [r3, #0] + 80033da: 6a7a ldr r2, [r7, #36] @ 0x24 + 80033dc: b2d2 uxtb r2, r2 + 80033de: 4611 mov r1, r2 + 80033e0: 4618 mov r0, r3 + 80033e2: f005 fc72 bl 8008cca + 80033e6: 6138 str r0, [r7, #16] + 80033e8: 693b ldr r3, [r7, #16] + 80033ea: f003 0301 and.w r3, r3, #1 + 80033ee: 2b00 cmp r3, #0 + 80033f0: d00c beq.n 800340c + 80033f2: 6a7b ldr r3, [r7, #36] @ 0x24 + 80033f4: 015a lsls r2, r3, #5 + 80033f6: 69fb ldr r3, [r7, #28] + 80033f8: 4413 add r3, r2 + 80033fa: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80033fe: 461a mov r2, r3 + 8003400: 2301 movs r3, #1 + 8003402: 6093 str r3, [r2, #8] + 8003404: 6a79 ldr r1, [r7, #36] @ 0x24 + 8003406: 6878 ldr r0, [r7, #4] + 8003408: f000 feb8 bl 800417c + 800340c: 693b ldr r3, [r7, #16] + 800340e: f003 0308 and.w r3, r3, #8 + 8003412: 2b00 cmp r3, #0 + 8003414: d00c beq.n 8003430 + 8003416: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003418: 015a lsls r2, r3, #5 + 800341a: 69fb ldr r3, [r7, #28] + 800341c: 4413 add r3, r2 + 800341e: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8003422: 461a mov r2, r3 + 8003424: 2308 movs r3, #8 + 8003426: 6093 str r3, [r2, #8] + 8003428: 6a79 ldr r1, [r7, #36] @ 0x24 + 800342a: 6878 ldr r0, [r7, #4] + 800342c: f000 ff8e bl 800434c + 8003430: 693b ldr r3, [r7, #16] + 8003432: f003 0310 and.w r3, r3, #16 + 8003436: 2b00 cmp r3, #0 + 8003438: d008 beq.n 800344c + 800343a: 6a7b ldr r3, [r7, #36] @ 0x24 + 800343c: 015a lsls r2, r3, #5 + 800343e: 69fb ldr r3, [r7, #28] + 8003440: 4413 add r3, r2 + 8003442: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8003446: 461a mov r2, r3 + 8003448: 2310 movs r3, #16 + 800344a: 6093 str r3, [r2, #8] + 800344c: 693b ldr r3, [r7, #16] + 800344e: f003 0302 and.w r3, r3, #2 + 8003452: 2b00 cmp r3, #0 + 8003454: d030 beq.n 80034b8 + 8003456: 6a3b ldr r3, [r7, #32] + 8003458: 695b ldr r3, [r3, #20] + 800345a: f003 0380 and.w r3, r3, #128 @ 0x80 + 800345e: 2b80 cmp r3, #128 @ 0x80 + 8003460: d109 bne.n 8003476 + 8003462: 69fb ldr r3, [r7, #28] + 8003464: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8003468: 685b ldr r3, [r3, #4] + 800346a: 69fa ldr r2, [r7, #28] + 800346c: f502 6200 add.w r2, r2, #2048 @ 0x800 + 8003470: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 8003474: 6053 str r3, [r2, #4] + 8003476: 6a7a ldr r2, [r7, #36] @ 0x24 + 8003478: 4613 mov r3, r2 + 800347a: 00db lsls r3, r3, #3 + 800347c: 4413 add r3, r2 + 800347e: 009b lsls r3, r3, #2 + 8003480: f503 7314 add.w r3, r3, #592 @ 0x250 + 8003484: 687a ldr r2, [r7, #4] + 8003486: 4413 add r3, r2 + 8003488: 3304 adds r3, #4 + 800348a: 617b str r3, [r7, #20] + 800348c: 697b ldr r3, [r7, #20] + 800348e: 78db ldrb r3, [r3, #3] + 8003490: 2b01 cmp r3, #1 + 8003492: d108 bne.n 80034a6 + 8003494: 697b ldr r3, [r7, #20] + 8003496: 2200 movs r2, #0 + 8003498: 70da strb r2, [r3, #3] + 800349a: 6a7b ldr r3, [r7, #36] @ 0x24 + 800349c: b2db uxtb r3, r3 + 800349e: 4619 mov r1, r3 + 80034a0: 6878 ldr r0, [r7, #4] + 80034a2: f007 fd0b bl 800aebc + 80034a6: 6a7b ldr r3, [r7, #36] @ 0x24 + 80034a8: 015a lsls r2, r3, #5 + 80034aa: 69fb ldr r3, [r7, #28] + 80034ac: 4413 add r3, r2 + 80034ae: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80034b2: 461a mov r2, r3 + 80034b4: 2302 movs r3, #2 + 80034b6: 6093 str r3, [r2, #8] + 80034b8: 693b ldr r3, [r7, #16] + 80034ba: f003 0320 and.w r3, r3, #32 + 80034be: 2b00 cmp r3, #0 + 80034c0: d008 beq.n 80034d4 + 80034c2: 6a7b ldr r3, [r7, #36] @ 0x24 + 80034c4: 015a lsls r2, r3, #5 + 80034c6: 69fb ldr r3, [r7, #28] + 80034c8: 4413 add r3, r2 + 80034ca: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80034ce: 461a mov r2, r3 + 80034d0: 2320 movs r3, #32 + 80034d2: 6093 str r3, [r2, #8] + 80034d4: 693b ldr r3, [r7, #16] + 80034d6: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 80034da: 2b00 cmp r3, #0 + 80034dc: d009 beq.n 80034f2 + 80034de: 6a7b ldr r3, [r7, #36] @ 0x24 + 80034e0: 015a lsls r2, r3, #5 + 80034e2: 69fb ldr r3, [r7, #28] + 80034e4: 4413 add r3, r2 + 80034e6: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80034ea: 461a mov r2, r3 + 80034ec: f44f 5300 mov.w r3, #8192 @ 0x2000 + 80034f0: 6093 str r3, [r2, #8] + 80034f2: 6a7b ldr r3, [r7, #36] @ 0x24 + 80034f4: 3301 adds r3, #1 + 80034f6: 627b str r3, [r7, #36] @ 0x24 + 80034f8: 6abb ldr r3, [r7, #40] @ 0x28 + 80034fa: 085b lsrs r3, r3, #1 + 80034fc: 62bb str r3, [r7, #40] @ 0x28 + 80034fe: 6abb ldr r3, [r7, #40] @ 0x28 + 8003500: 2b00 cmp r3, #0 + 8003502: f47f af62 bne.w 80033ca + 8003506: 687b ldr r3, [r7, #4] + 8003508: 681b ldr r3, [r3, #0] + 800350a: 4618 mov r0, r3 + 800350c: f005 fb96 bl 8008c3c + 8003510: 4603 mov r3, r0 + 8003512: f403 2380 and.w r3, r3, #262144 @ 0x40000 + 8003516: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 + 800351a: f040 80db bne.w 80036d4 + 800351e: 687b ldr r3, [r7, #4] + 8003520: 681b ldr r3, [r3, #0] + 8003522: 4618 mov r0, r3 + 8003524: f005 fbb7 bl 8008c96 + 8003528: 62b8 str r0, [r7, #40] @ 0x28 + 800352a: 2300 movs r3, #0 + 800352c: 627b str r3, [r7, #36] @ 0x24 + 800352e: e0cd b.n 80036cc + 8003530: 6abb ldr r3, [r7, #40] @ 0x28 + 8003532: f003 0301 and.w r3, r3, #1 + 8003536: 2b00 cmp r3, #0 + 8003538: f000 80c2 beq.w 80036c0 + 800353c: 687b ldr r3, [r7, #4] + 800353e: 681b ldr r3, [r3, #0] + 8003540: 6a7a ldr r2, [r7, #36] @ 0x24 + 8003542: b2d2 uxtb r2, r2 + 8003544: 4611 mov r1, r2 + 8003546: 4618 mov r0, r3 + 8003548: f005 fbdd bl 8008d06 + 800354c: 6138 str r0, [r7, #16] + 800354e: 693b ldr r3, [r7, #16] + 8003550: f003 0301 and.w r3, r3, #1 + 8003554: 2b00 cmp r3, #0 + 8003556: d057 beq.n 8003608 + 8003558: 6a7b ldr r3, [r7, #36] @ 0x24 + 800355a: f003 030f and.w r3, r3, #15 + 800355e: 2201 movs r2, #1 + 8003560: fa02 f303 lsl.w r3, r2, r3 + 8003564: 60fb str r3, [r7, #12] + 8003566: 69fb ldr r3, [r7, #28] + 8003568: f503 6300 add.w r3, r3, #2048 @ 0x800 + 800356c: 6b5a ldr r2, [r3, #52] @ 0x34 + 800356e: 68fb ldr r3, [r7, #12] + 8003570: 43db mvns r3, r3 + 8003572: 69f9 ldr r1, [r7, #28] + 8003574: f501 6100 add.w r1, r1, #2048 @ 0x800 + 8003578: 4013 ands r3, r2 + 800357a: 634b str r3, [r1, #52] @ 0x34 + 800357c: 6a7b ldr r3, [r7, #36] @ 0x24 + 800357e: 015a lsls r2, r3, #5 + 8003580: 69fb ldr r3, [r7, #28] + 8003582: 4413 add r3, r2 + 8003584: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8003588: 461a mov r2, r3 + 800358a: 2301 movs r3, #1 + 800358c: 6093 str r3, [r2, #8] + 800358e: 687b ldr r3, [r7, #4] + 8003590: 799b ldrb r3, [r3, #6] + 8003592: 2b01 cmp r3, #1 + 8003594: d132 bne.n 80035fc + 8003596: 6879 ldr r1, [r7, #4] + 8003598: 6a7a ldr r2, [r7, #36] @ 0x24 + 800359a: 4613 mov r3, r2 + 800359c: 00db lsls r3, r3, #3 + 800359e: 4413 add r3, r2 + 80035a0: 009b lsls r3, r3, #2 + 80035a2: 440b add r3, r1 + 80035a4: 3320 adds r3, #32 + 80035a6: 6819 ldr r1, [r3, #0] + 80035a8: 6878 ldr r0, [r7, #4] + 80035aa: 6a7a ldr r2, [r7, #36] @ 0x24 + 80035ac: 4613 mov r3, r2 + 80035ae: 00db lsls r3, r3, #3 + 80035b0: 4413 add r3, r2 + 80035b2: 009b lsls r3, r3, #2 + 80035b4: 4403 add r3, r0 + 80035b6: 331c adds r3, #28 + 80035b8: 681b ldr r3, [r3, #0] + 80035ba: 4419 add r1, r3 + 80035bc: 6878 ldr r0, [r7, #4] + 80035be: 6a7a ldr r2, [r7, #36] @ 0x24 + 80035c0: 4613 mov r3, r2 + 80035c2: 00db lsls r3, r3, #3 + 80035c4: 4413 add r3, r2 + 80035c6: 009b lsls r3, r3, #2 + 80035c8: 4403 add r3, r0 + 80035ca: 3320 adds r3, #32 + 80035cc: 6019 str r1, [r3, #0] + 80035ce: 6a7b ldr r3, [r7, #36] @ 0x24 + 80035d0: 2b00 cmp r3, #0 + 80035d2: d113 bne.n 80035fc + 80035d4: 6879 ldr r1, [r7, #4] + 80035d6: 6a7a ldr r2, [r7, #36] @ 0x24 + 80035d8: 4613 mov r3, r2 + 80035da: 00db lsls r3, r3, #3 + 80035dc: 4413 add r3, r2 + 80035de: 009b lsls r3, r3, #2 + 80035e0: 440b add r3, r1 + 80035e2: 3324 adds r3, #36 @ 0x24 + 80035e4: 681b ldr r3, [r3, #0] + 80035e6: 2b00 cmp r3, #0 + 80035e8: d108 bne.n 80035fc + 80035ea: 687b ldr r3, [r7, #4] + 80035ec: 6818 ldr r0, [r3, #0] + 80035ee: 687b ldr r3, [r7, #4] + 80035f0: f203 439c addw r3, r3, #1180 @ 0x49c + 80035f4: 461a mov r2, r3 + 80035f6: 2101 movs r1, #1 + 80035f8: f005 fbe4 bl 8008dc4 + 80035fc: 6a7b ldr r3, [r7, #36] @ 0x24 + 80035fe: b2db uxtb r3, r3 + 8003600: 4619 mov r1, r3 + 8003602: 6878 ldr r0, [r7, #4] + 8003604: f007 fbd5 bl 800adb2 + 8003608: 693b ldr r3, [r7, #16] + 800360a: f003 0308 and.w r3, r3, #8 + 800360e: 2b00 cmp r3, #0 + 8003610: d008 beq.n 8003624 + 8003612: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003614: 015a lsls r2, r3, #5 + 8003616: 69fb ldr r3, [r7, #28] + 8003618: 4413 add r3, r2 + 800361a: f503 6310 add.w r3, r3, #2304 @ 0x900 + 800361e: 461a mov r2, r3 + 8003620: 2308 movs r3, #8 + 8003622: 6093 str r3, [r2, #8] + 8003624: 693b ldr r3, [r7, #16] + 8003626: f003 0310 and.w r3, r3, #16 + 800362a: 2b00 cmp r3, #0 + 800362c: d008 beq.n 8003640 + 800362e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003630: 015a lsls r2, r3, #5 + 8003632: 69fb ldr r3, [r7, #28] + 8003634: 4413 add r3, r2 + 8003636: f503 6310 add.w r3, r3, #2304 @ 0x900 + 800363a: 461a mov r2, r3 + 800363c: 2310 movs r3, #16 + 800363e: 6093 str r3, [r2, #8] + 8003640: 693b ldr r3, [r7, #16] + 8003642: f003 0340 and.w r3, r3, #64 @ 0x40 + 8003646: 2b00 cmp r3, #0 + 8003648: d008 beq.n 800365c + 800364a: 6a7b ldr r3, [r7, #36] @ 0x24 + 800364c: 015a lsls r2, r3, #5 + 800364e: 69fb ldr r3, [r7, #28] + 8003650: 4413 add r3, r2 + 8003652: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8003656: 461a mov r2, r3 + 8003658: 2340 movs r3, #64 @ 0x40 + 800365a: 6093 str r3, [r2, #8] + 800365c: 693b ldr r3, [r7, #16] + 800365e: f003 0302 and.w r3, r3, #2 + 8003662: 2b00 cmp r3, #0 + 8003664: d023 beq.n 80036ae + 8003666: 6a79 ldr r1, [r7, #36] @ 0x24 + 8003668: 6a38 ldr r0, [r7, #32] + 800366a: f004 fbcb bl 8007e04 + 800366e: 6a7a ldr r2, [r7, #36] @ 0x24 + 8003670: 4613 mov r3, r2 + 8003672: 00db lsls r3, r3, #3 + 8003674: 4413 add r3, r2 + 8003676: 009b lsls r3, r3, #2 + 8003678: 3310 adds r3, #16 + 800367a: 687a ldr r2, [r7, #4] + 800367c: 4413 add r3, r2 + 800367e: 3304 adds r3, #4 + 8003680: 617b str r3, [r7, #20] + 8003682: 697b ldr r3, [r7, #20] + 8003684: 78db ldrb r3, [r3, #3] + 8003686: 2b01 cmp r3, #1 + 8003688: d108 bne.n 800369c + 800368a: 697b ldr r3, [r7, #20] + 800368c: 2200 movs r2, #0 + 800368e: 70da strb r2, [r3, #3] + 8003690: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003692: b2db uxtb r3, r3 + 8003694: 4619 mov r1, r3 + 8003696: 6878 ldr r0, [r7, #4] + 8003698: f007 fc22 bl 800aee0 + 800369c: 6a7b ldr r3, [r7, #36] @ 0x24 + 800369e: 015a lsls r2, r3, #5 + 80036a0: 69fb ldr r3, [r7, #28] + 80036a2: 4413 add r3, r2 + 80036a4: f503 6310 add.w r3, r3, #2304 @ 0x900 + 80036a8: 461a mov r2, r3 + 80036aa: 2302 movs r3, #2 + 80036ac: 6093 str r3, [r2, #8] + 80036ae: 693b ldr r3, [r7, #16] + 80036b0: f003 0380 and.w r3, r3, #128 @ 0x80 + 80036b4: 2b00 cmp r3, #0 + 80036b6: d003 beq.n 80036c0 + 80036b8: 6a79 ldr r1, [r7, #36] @ 0x24 + 80036ba: 6878 ldr r0, [r7, #4] + 80036bc: f000 fcd2 bl 8004064 + 80036c0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80036c2: 3301 adds r3, #1 + 80036c4: 627b str r3, [r7, #36] @ 0x24 + 80036c6: 6abb ldr r3, [r7, #40] @ 0x28 + 80036c8: 085b lsrs r3, r3, #1 + 80036ca: 62bb str r3, [r7, #40] @ 0x28 + 80036cc: 6abb ldr r3, [r7, #40] @ 0x28 + 80036ce: 2b00 cmp r3, #0 + 80036d0: f47f af2e bne.w 8003530 + 80036d4: 687b ldr r3, [r7, #4] + 80036d6: 681b ldr r3, [r3, #0] + 80036d8: 4618 mov r0, r3 + 80036da: f005 faaf bl 8008c3c + 80036de: 4603 mov r3, r0 + 80036e0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 80036e4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 80036e8: d122 bne.n 8003730 + 80036ea: 69fb ldr r3, [r7, #28] + 80036ec: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80036f0: 685b ldr r3, [r3, #4] + 80036f2: 69fa ldr r2, [r7, #28] + 80036f4: f502 6200 add.w r2, r2, #2048 @ 0x800 + 80036f8: f023 0301 bic.w r3, r3, #1 + 80036fc: 6053 str r3, [r2, #4] + 80036fe: 687b ldr r3, [r7, #4] + 8003700: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc + 8003704: 2b01 cmp r3, #1 + 8003706: d108 bne.n 800371a + 8003708: 687b ldr r3, [r7, #4] + 800370a: 2200 movs r2, #0 + 800370c: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc + 8003710: 2100 movs r1, #0 + 8003712: 6878 ldr r0, [r7, #4] + 8003714: f007 fd8a bl 800b22c + 8003718: e002 b.n 8003720 + 800371a: 6878 ldr r0, [r7, #4] + 800371c: f007 fbc0 bl 800aea0 + 8003720: 687b ldr r3, [r7, #4] + 8003722: 681b ldr r3, [r3, #0] + 8003724: 695a ldr r2, [r3, #20] + 8003726: 687b ldr r3, [r7, #4] + 8003728: 681b ldr r3, [r3, #0] + 800372a: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000 + 800372e: 615a str r2, [r3, #20] + 8003730: 687b ldr r3, [r7, #4] + 8003732: 681b ldr r3, [r3, #0] + 8003734: 4618 mov r0, r3 + 8003736: f005 fa81 bl 8008c3c + 800373a: 4603 mov r3, r0 + 800373c: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8003740: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8003744: d112 bne.n 800376c + 8003746: 69fb ldr r3, [r7, #28] + 8003748: f503 6300 add.w r3, r3, #2048 @ 0x800 + 800374c: 689b ldr r3, [r3, #8] + 800374e: f003 0301 and.w r3, r3, #1 + 8003752: 2b01 cmp r3, #1 + 8003754: d102 bne.n 800375c + 8003756: 6878 ldr r0, [r7, #4] + 8003758: f007 fb7c bl 800ae54 + 800375c: 687b ldr r3, [r7, #4] + 800375e: 681b ldr r3, [r3, #0] + 8003760: 695a ldr r2, [r3, #20] + 8003762: 687b ldr r3, [r7, #4] + 8003764: 681b ldr r3, [r3, #0] + 8003766: f402 6200 and.w r2, r2, #2048 @ 0x800 + 800376a: 615a str r2, [r3, #20] + 800376c: 687b ldr r3, [r7, #4] + 800376e: 681b ldr r3, [r3, #0] + 8003770: 4618 mov r0, r3 + 8003772: f005 fa63 bl 8008c3c + 8003776: 4603 mov r3, r0 + 8003778: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 800377c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 + 8003780: d121 bne.n 80037c6 + 8003782: 687b ldr r3, [r7, #4] + 8003784: 681b ldr r3, [r3, #0] + 8003786: 695a ldr r2, [r3, #20] + 8003788: 687b ldr r3, [r7, #4] + 800378a: 681b ldr r3, [r3, #0] + 800378c: f002 6200 and.w r2, r2, #134217728 @ 0x8000000 + 8003790: 615a str r2, [r3, #20] + 8003792: 687b ldr r3, [r7, #4] + 8003794: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc + 8003798: 2b00 cmp r3, #0 + 800379a: d111 bne.n 80037c0 + 800379c: 687b ldr r3, [r7, #4] + 800379e: 2201 movs r2, #1 + 80037a0: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc + 80037a4: 687b ldr r3, [r7, #4] + 80037a6: 681b ldr r3, [r3, #0] + 80037a8: 6d5b ldr r3, [r3, #84] @ 0x54 + 80037aa: 089b lsrs r3, r3, #2 + 80037ac: f003 020f and.w r2, r3, #15 + 80037b0: 687b ldr r3, [r7, #4] + 80037b2: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0 + 80037b6: 2101 movs r1, #1 + 80037b8: 6878 ldr r0, [r7, #4] + 80037ba: f007 fd37 bl 800b22c + 80037be: e002 b.n 80037c6 + 80037c0: 6878 ldr r0, [r7, #4] + 80037c2: f007 fb47 bl 800ae54 + 80037c6: 687b ldr r3, [r7, #4] + 80037c8: 681b ldr r3, [r3, #0] + 80037ca: 4618 mov r0, r3 + 80037cc: f005 fa36 bl 8008c3c + 80037d0: 4603 mov r3, r0 + 80037d2: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 80037d6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80037da: f040 80b7 bne.w 800394c + 80037de: 69fb ldr r3, [r7, #28] + 80037e0: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80037e4: 685b ldr r3, [r3, #4] + 80037e6: 69fa ldr r2, [r7, #28] + 80037e8: f502 6200 add.w r2, r2, #2048 @ 0x800 + 80037ec: f023 0301 bic.w r3, r3, #1 + 80037f0: 6053 str r3, [r2, #4] + 80037f2: 687b ldr r3, [r7, #4] + 80037f4: 681b ldr r3, [r3, #0] + 80037f6: 2110 movs r1, #16 + 80037f8: 4618 mov r0, r3 + 80037fa: f004 fb03 bl 8007e04 + 80037fe: 2300 movs r3, #0 + 8003800: 62fb str r3, [r7, #44] @ 0x2c + 8003802: e046 b.n 8003892 + 8003804: 6afb ldr r3, [r7, #44] @ 0x2c + 8003806: 015a lsls r2, r3, #5 + 8003808: 69fb ldr r3, [r7, #28] + 800380a: 4413 add r3, r2 + 800380c: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8003810: 461a mov r2, r3 + 8003812: f64f 337f movw r3, #64383 @ 0xfb7f + 8003816: 6093 str r3, [r2, #8] + 8003818: 6afb ldr r3, [r7, #44] @ 0x2c + 800381a: 015a lsls r2, r3, #5 + 800381c: 69fb ldr r3, [r7, #28] + 800381e: 4413 add r3, r2 + 8003820: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8003824: 681b ldr r3, [r3, #0] + 8003826: 6afa ldr r2, [r7, #44] @ 0x2c + 8003828: 0151 lsls r1, r2, #5 + 800382a: 69fa ldr r2, [r7, #28] + 800382c: 440a add r2, r1 + 800382e: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8003832: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 + 8003836: 6013 str r3, [r2, #0] + 8003838: 6afb ldr r3, [r7, #44] @ 0x2c + 800383a: 015a lsls r2, r3, #5 + 800383c: 69fb ldr r3, [r7, #28] + 800383e: 4413 add r3, r2 + 8003840: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8003844: 461a mov r2, r3 + 8003846: f64f 337f movw r3, #64383 @ 0xfb7f + 800384a: 6093 str r3, [r2, #8] + 800384c: 6afb ldr r3, [r7, #44] @ 0x2c + 800384e: 015a lsls r2, r3, #5 + 8003850: 69fb ldr r3, [r7, #28] + 8003852: 4413 add r3, r2 + 8003854: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8003858: 681b ldr r3, [r3, #0] + 800385a: 6afa ldr r2, [r7, #44] @ 0x2c + 800385c: 0151 lsls r1, r2, #5 + 800385e: 69fa ldr r2, [r7, #28] + 8003860: 440a add r2, r1 + 8003862: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8003866: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 + 800386a: 6013 str r3, [r2, #0] + 800386c: 6afb ldr r3, [r7, #44] @ 0x2c + 800386e: 015a lsls r2, r3, #5 + 8003870: 69fb ldr r3, [r7, #28] + 8003872: 4413 add r3, r2 + 8003874: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8003878: 681b ldr r3, [r3, #0] + 800387a: 6afa ldr r2, [r7, #44] @ 0x2c + 800387c: 0151 lsls r1, r2, #5 + 800387e: 69fa ldr r2, [r7, #28] + 8003880: 440a add r2, r1 + 8003882: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8003886: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 + 800388a: 6013 str r3, [r2, #0] + 800388c: 6afb ldr r3, [r7, #44] @ 0x2c + 800388e: 3301 adds r3, #1 + 8003890: 62fb str r3, [r7, #44] @ 0x2c + 8003892: 687b ldr r3, [r7, #4] + 8003894: 791b ldrb r3, [r3, #4] + 8003896: 461a mov r2, r3 + 8003898: 6afb ldr r3, [r7, #44] @ 0x2c + 800389a: 4293 cmp r3, r2 + 800389c: d3b2 bcc.n 8003804 + 800389e: 69fb ldr r3, [r7, #28] + 80038a0: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80038a4: 69db ldr r3, [r3, #28] + 80038a6: 69fa ldr r2, [r7, #28] + 80038a8: f502 6200 add.w r2, r2, #2048 @ 0x800 + 80038ac: f043 1301 orr.w r3, r3, #65537 @ 0x10001 + 80038b0: 61d3 str r3, [r2, #28] + 80038b2: 687b ldr r3, [r7, #4] + 80038b4: 7bdb ldrb r3, [r3, #15] + 80038b6: 2b00 cmp r3, #0 + 80038b8: d016 beq.n 80038e8 + 80038ba: 69fb ldr r3, [r7, #28] + 80038bc: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80038c0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 + 80038c4: 69fa ldr r2, [r7, #28] + 80038c6: f502 6200 add.w r2, r2, #2048 @ 0x800 + 80038ca: f043 030b orr.w r3, r3, #11 + 80038ce: f8c2 3084 str.w r3, [r2, #132] @ 0x84 + 80038d2: 69fb ldr r3, [r7, #28] + 80038d4: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80038d8: 6c5b ldr r3, [r3, #68] @ 0x44 + 80038da: 69fa ldr r2, [r7, #28] + 80038dc: f502 6200 add.w r2, r2, #2048 @ 0x800 + 80038e0: f043 030b orr.w r3, r3, #11 + 80038e4: 6453 str r3, [r2, #68] @ 0x44 + 80038e6: e015 b.n 8003914 + 80038e8: 69fb ldr r3, [r7, #28] + 80038ea: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80038ee: 695b ldr r3, [r3, #20] + 80038f0: 69fa ldr r2, [r7, #28] + 80038f2: f502 6200 add.w r2, r2, #2048 @ 0x800 + 80038f6: f443 5300 orr.w r3, r3, #8192 @ 0x2000 + 80038fa: f043 032b orr.w r3, r3, #43 @ 0x2b + 80038fe: 6153 str r3, [r2, #20] + 8003900: 69fb ldr r3, [r7, #28] + 8003902: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8003906: 691b ldr r3, [r3, #16] + 8003908: 69fa ldr r2, [r7, #28] + 800390a: f502 6200 add.w r2, r2, #2048 @ 0x800 + 800390e: f043 030b orr.w r3, r3, #11 + 8003912: 6113 str r3, [r2, #16] + 8003914: 69fb ldr r3, [r7, #28] + 8003916: f503 6300 add.w r3, r3, #2048 @ 0x800 + 800391a: 681b ldr r3, [r3, #0] + 800391c: 69fa ldr r2, [r7, #28] + 800391e: f502 6200 add.w r2, r2, #2048 @ 0x800 + 8003922: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 + 8003926: 6013 str r3, [r2, #0] + 8003928: 687b ldr r3, [r7, #4] + 800392a: 6818 ldr r0, [r3, #0] + 800392c: 687b ldr r3, [r7, #4] + 800392e: 7999 ldrb r1, [r3, #6] + 8003930: 687b ldr r3, [r7, #4] + 8003932: f203 439c addw r3, r3, #1180 @ 0x49c + 8003936: 461a mov r2, r3 + 8003938: f005 fa44 bl 8008dc4 + 800393c: 687b ldr r3, [r7, #4] + 800393e: 681b ldr r3, [r3, #0] + 8003940: 695a ldr r2, [r3, #20] + 8003942: 687b ldr r3, [r7, #4] + 8003944: 681b ldr r3, [r3, #0] + 8003946: f402 5280 and.w r2, r2, #4096 @ 0x1000 + 800394a: 615a str r2, [r3, #20] + 800394c: 687b ldr r3, [r7, #4] + 800394e: 681b ldr r3, [r3, #0] + 8003950: 4618 mov r0, r3 + 8003952: f005 f973 bl 8008c3c + 8003956: 4603 mov r3, r0 + 8003958: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 800395c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8003960: d123 bne.n 80039aa + 8003962: 687b ldr r3, [r7, #4] + 8003964: 681b ldr r3, [r3, #0] + 8003966: 4618 mov r0, r3 + 8003968: f005 fa09 bl 8008d7e + 800396c: 687b ldr r3, [r7, #4] + 800396e: 681b ldr r3, [r3, #0] + 8003970: 4618 mov r0, r3 + 8003972: f004 fac0 bl 8007ef6 + 8003976: 4603 mov r3, r0 + 8003978: 461a mov r2, r3 + 800397a: 687b ldr r3, [r7, #4] + 800397c: 71da strb r2, [r3, #7] + 800397e: 687b ldr r3, [r7, #4] + 8003980: 681c ldr r4, [r3, #0] + 8003982: f000 fe8b bl 800469c + 8003986: 4601 mov r1, r0 + 8003988: 687b ldr r3, [r7, #4] + 800398a: 79db ldrb r3, [r3, #7] + 800398c: 461a mov r2, r3 + 800398e: 4620 mov r0, r4 + 8003990: f003 ffca bl 8007928 + 8003994: 6878 ldr r0, [r7, #4] + 8003996: f007 fa34 bl 800ae02 + 800399a: 687b ldr r3, [r7, #4] + 800399c: 681b ldr r3, [r3, #0] + 800399e: 695a ldr r2, [r3, #20] + 80039a0: 687b ldr r3, [r7, #4] + 80039a2: 681b ldr r3, [r3, #0] + 80039a4: f402 5200 and.w r2, r2, #8192 @ 0x2000 + 80039a8: 615a str r2, [r3, #20] + 80039aa: 687b ldr r3, [r7, #4] + 80039ac: 681b ldr r3, [r3, #0] + 80039ae: 4618 mov r0, r3 + 80039b0: f005 f944 bl 8008c3c + 80039b4: 4603 mov r3, r0 + 80039b6: f003 0308 and.w r3, r3, #8 + 80039ba: 2b08 cmp r3, #8 + 80039bc: d10a bne.n 80039d4 + 80039be: 6878 ldr r0, [r7, #4] + 80039c0: f007 fa11 bl 800ade6 + 80039c4: 687b ldr r3, [r7, #4] + 80039c6: 681b ldr r3, [r3, #0] + 80039c8: 695a ldr r2, [r3, #20] + 80039ca: 687b ldr r3, [r7, #4] + 80039cc: 681b ldr r3, [r3, #0] + 80039ce: f002 0208 and.w r2, r2, #8 + 80039d2: 615a str r2, [r3, #20] + 80039d4: 687b ldr r3, [r7, #4] + 80039d6: 681b ldr r3, [r3, #0] + 80039d8: 4618 mov r0, r3 + 80039da: f005 f92f bl 8008c3c + 80039de: 4603 mov r3, r0 + 80039e0: f003 0380 and.w r3, r3, #128 @ 0x80 + 80039e4: 2b80 cmp r3, #128 @ 0x80 + 80039e6: d123 bne.n 8003a30 + 80039e8: 6a3b ldr r3, [r7, #32] + 80039ea: 699b ldr r3, [r3, #24] + 80039ec: f023 0280 bic.w r2, r3, #128 @ 0x80 + 80039f0: 6a3b ldr r3, [r7, #32] + 80039f2: 619a str r2, [r3, #24] + 80039f4: 2301 movs r3, #1 + 80039f6: 627b str r3, [r7, #36] @ 0x24 + 80039f8: e014 b.n 8003a24 + 80039fa: 6879 ldr r1, [r7, #4] + 80039fc: 6a7a ldr r2, [r7, #36] @ 0x24 + 80039fe: 4613 mov r3, r2 + 8003a00: 00db lsls r3, r3, #3 + 8003a02: 4413 add r3, r2 + 8003a04: 009b lsls r3, r3, #2 + 8003a06: 440b add r3, r1 + 8003a08: f203 2357 addw r3, r3, #599 @ 0x257 + 8003a0c: 781b ldrb r3, [r3, #0] + 8003a0e: 2b01 cmp r3, #1 + 8003a10: d105 bne.n 8003a1e + 8003a12: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003a14: b2db uxtb r3, r3 + 8003a16: 4619 mov r1, r3 + 8003a18: 6878 ldr r0, [r7, #4] + 8003a1a: f000 faf2 bl 8004002 + 8003a1e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003a20: 3301 adds r3, #1 + 8003a22: 627b str r3, [r7, #36] @ 0x24 + 8003a24: 687b ldr r3, [r7, #4] + 8003a26: 791b ldrb r3, [r3, #4] + 8003a28: 461a mov r2, r3 + 8003a2a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003a2c: 4293 cmp r3, r2 + 8003a2e: d3e4 bcc.n 80039fa + 8003a30: 687b ldr r3, [r7, #4] + 8003a32: 681b ldr r3, [r3, #0] + 8003a34: 4618 mov r0, r3 + 8003a36: f005 f901 bl 8008c3c + 8003a3a: 4603 mov r3, r0 + 8003a3c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8003a40: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 8003a44: d13c bne.n 8003ac0 + 8003a46: 2301 movs r3, #1 + 8003a48: 627b str r3, [r7, #36] @ 0x24 + 8003a4a: e02b b.n 8003aa4 + 8003a4c: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003a4e: 015a lsls r2, r3, #5 + 8003a50: 69fb ldr r3, [r7, #28] + 8003a52: 4413 add r3, r2 + 8003a54: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8003a58: 681b ldr r3, [r3, #0] + 8003a5a: 61bb str r3, [r7, #24] + 8003a5c: 6879 ldr r1, [r7, #4] + 8003a5e: 6a7a ldr r2, [r7, #36] @ 0x24 + 8003a60: 4613 mov r3, r2 + 8003a62: 00db lsls r3, r3, #3 + 8003a64: 4413 add r3, r2 + 8003a66: 009b lsls r3, r3, #2 + 8003a68: 440b add r3, r1 + 8003a6a: 3318 adds r3, #24 + 8003a6c: 781b ldrb r3, [r3, #0] + 8003a6e: 2b01 cmp r3, #1 + 8003a70: d115 bne.n 8003a9e + 8003a72: 69bb ldr r3, [r7, #24] + 8003a74: 2b00 cmp r3, #0 + 8003a76: da12 bge.n 8003a9e + 8003a78: 6879 ldr r1, [r7, #4] + 8003a7a: 6a7a ldr r2, [r7, #36] @ 0x24 + 8003a7c: 4613 mov r3, r2 + 8003a7e: 00db lsls r3, r3, #3 + 8003a80: 4413 add r3, r2 + 8003a82: 009b lsls r3, r3, #2 + 8003a84: 440b add r3, r1 + 8003a86: 3317 adds r3, #23 + 8003a88: 2201 movs r2, #1 + 8003a8a: 701a strb r2, [r3, #0] + 8003a8c: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003a8e: b2db uxtb r3, r3 + 8003a90: f063 037f orn r3, r3, #127 @ 0x7f + 8003a94: b2db uxtb r3, r3 + 8003a96: 4619 mov r1, r3 + 8003a98: 6878 ldr r0, [r7, #4] + 8003a9a: f000 fab2 bl 8004002 + 8003a9e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003aa0: 3301 adds r3, #1 + 8003aa2: 627b str r3, [r7, #36] @ 0x24 + 8003aa4: 687b ldr r3, [r7, #4] + 8003aa6: 791b ldrb r3, [r3, #4] + 8003aa8: 461a mov r2, r3 + 8003aaa: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003aac: 4293 cmp r3, r2 + 8003aae: d3cd bcc.n 8003a4c + 8003ab0: 687b ldr r3, [r7, #4] + 8003ab2: 681b ldr r3, [r3, #0] + 8003ab4: 695a ldr r2, [r3, #20] + 8003ab6: 687b ldr r3, [r7, #4] + 8003ab8: 681b ldr r3, [r3, #0] + 8003aba: f402 1280 and.w r2, r2, #1048576 @ 0x100000 + 8003abe: 615a str r2, [r3, #20] + 8003ac0: 687b ldr r3, [r7, #4] + 8003ac2: 681b ldr r3, [r3, #0] + 8003ac4: 4618 mov r0, r3 + 8003ac6: f005 f8b9 bl 8008c3c + 8003aca: 4603 mov r3, r0 + 8003acc: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8003ad0: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 + 8003ad4: d156 bne.n 8003b84 + 8003ad6: 2301 movs r3, #1 + 8003ad8: 627b str r3, [r7, #36] @ 0x24 + 8003ada: e045 b.n 8003b68 + 8003adc: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003ade: 015a lsls r2, r3, #5 + 8003ae0: 69fb ldr r3, [r7, #28] + 8003ae2: 4413 add r3, r2 + 8003ae4: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8003ae8: 681b ldr r3, [r3, #0] + 8003aea: 61bb str r3, [r7, #24] + 8003aec: 6879 ldr r1, [r7, #4] + 8003aee: 6a7a ldr r2, [r7, #36] @ 0x24 + 8003af0: 4613 mov r3, r2 + 8003af2: 00db lsls r3, r3, #3 + 8003af4: 4413 add r3, r2 + 8003af6: 009b lsls r3, r3, #2 + 8003af8: 440b add r3, r1 + 8003afa: f503 7316 add.w r3, r3, #600 @ 0x258 + 8003afe: 781b ldrb r3, [r3, #0] + 8003b00: 2b01 cmp r3, #1 + 8003b02: d12e bne.n 8003b62 + 8003b04: 69bb ldr r3, [r7, #24] + 8003b06: 2b00 cmp r3, #0 + 8003b08: da2b bge.n 8003b62 + 8003b0a: 69bb ldr r3, [r7, #24] + 8003b0c: 0c1a lsrs r2, r3, #16 + 8003b0e: 687b ldr r3, [r7, #4] + 8003b10: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4 + 8003b14: 4053 eors r3, r2 + 8003b16: f003 0301 and.w r3, r3, #1 + 8003b1a: 2b00 cmp r3, #0 + 8003b1c: d121 bne.n 8003b62 + 8003b1e: 6879 ldr r1, [r7, #4] + 8003b20: 6a7a ldr r2, [r7, #36] @ 0x24 + 8003b22: 4613 mov r3, r2 + 8003b24: 00db lsls r3, r3, #3 + 8003b26: 4413 add r3, r2 + 8003b28: 009b lsls r3, r3, #2 + 8003b2a: 440b add r3, r1 + 8003b2c: f203 2357 addw r3, r3, #599 @ 0x257 + 8003b30: 2201 movs r2, #1 + 8003b32: 701a strb r2, [r3, #0] + 8003b34: 6a3b ldr r3, [r7, #32] + 8003b36: 699b ldr r3, [r3, #24] + 8003b38: f043 0280 orr.w r2, r3, #128 @ 0x80 + 8003b3c: 6a3b ldr r3, [r7, #32] + 8003b3e: 619a str r2, [r3, #24] + 8003b40: 6a3b ldr r3, [r7, #32] + 8003b42: 695b ldr r3, [r3, #20] + 8003b44: f003 0380 and.w r3, r3, #128 @ 0x80 + 8003b48: 2b00 cmp r3, #0 + 8003b4a: d10a bne.n 8003b62 + 8003b4c: 69fb ldr r3, [r7, #28] + 8003b4e: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8003b52: 685b ldr r3, [r3, #4] + 8003b54: 69fa ldr r2, [r7, #28] + 8003b56: f502 6200 add.w r2, r2, #2048 @ 0x800 + 8003b5a: f443 7300 orr.w r3, r3, #512 @ 0x200 + 8003b5e: 6053 str r3, [r2, #4] + 8003b60: e008 b.n 8003b74 + 8003b62: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003b64: 3301 adds r3, #1 + 8003b66: 627b str r3, [r7, #36] @ 0x24 + 8003b68: 687b ldr r3, [r7, #4] + 8003b6a: 791b ldrb r3, [r3, #4] + 8003b6c: 461a mov r2, r3 + 8003b6e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8003b70: 4293 cmp r3, r2 + 8003b72: d3b3 bcc.n 8003adc + 8003b74: 687b ldr r3, [r7, #4] + 8003b76: 681b ldr r3, [r3, #0] + 8003b78: 695a ldr r2, [r3, #20] + 8003b7a: 687b ldr r3, [r7, #4] + 8003b7c: 681b ldr r3, [r3, #0] + 8003b7e: f402 1200 and.w r2, r2, #2097152 @ 0x200000 + 8003b82: 615a str r2, [r3, #20] + 8003b84: 687b ldr r3, [r7, #4] + 8003b86: 681b ldr r3, [r3, #0] + 8003b88: 4618 mov r0, r3 + 8003b8a: f005 f857 bl 8008c3c + 8003b8e: 4603 mov r3, r0 + 8003b90: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 + 8003b94: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8003b98: d10a bne.n 8003bb0 + 8003b9a: 6878 ldr r0, [r7, #4] + 8003b9c: f007 f9b2 bl 800af04 + 8003ba0: 687b ldr r3, [r7, #4] + 8003ba2: 681b ldr r3, [r3, #0] + 8003ba4: 695a ldr r2, [r3, #20] + 8003ba6: 687b ldr r3, [r7, #4] + 8003ba8: 681b ldr r3, [r3, #0] + 8003baa: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 + 8003bae: 615a str r2, [r3, #20] + 8003bb0: 687b ldr r3, [r7, #4] + 8003bb2: 681b ldr r3, [r3, #0] + 8003bb4: 4618 mov r0, r3 + 8003bb6: f005 f841 bl 8008c3c + 8003bba: 4603 mov r3, r0 + 8003bbc: f003 0304 and.w r3, r3, #4 + 8003bc0: 2b04 cmp r3, #4 + 8003bc2: d115 bne.n 8003bf0 + 8003bc4: 687b ldr r3, [r7, #4] + 8003bc6: 681b ldr r3, [r3, #0] + 8003bc8: 685b ldr r3, [r3, #4] + 8003bca: 61bb str r3, [r7, #24] + 8003bcc: 69bb ldr r3, [r7, #24] + 8003bce: f003 0304 and.w r3, r3, #4 + 8003bd2: 2b00 cmp r3, #0 + 8003bd4: d002 beq.n 8003bdc + 8003bd6: 6878 ldr r0, [r7, #4] + 8003bd8: f007 f9a2 bl 800af20 + 8003bdc: 687b ldr r3, [r7, #4] + 8003bde: 681b ldr r3, [r3, #0] + 8003be0: 6859 ldr r1, [r3, #4] + 8003be2: 687b ldr r3, [r7, #4] + 8003be4: 681b ldr r3, [r3, #0] + 8003be6: 69ba ldr r2, [r7, #24] + 8003be8: 430a orrs r2, r1 + 8003bea: 605a str r2, [r3, #4] + 8003bec: e000 b.n 8003bf0 + 8003bee: bf00 nop + 8003bf0: 3734 adds r7, #52 @ 0x34 + 8003bf2: 46bd mov sp, r7 + 8003bf4: bd90 pop {r4, r7, pc} + +08003bf6 : + 8003bf6: b580 push {r7, lr} + 8003bf8: b082 sub sp, #8 + 8003bfa: af00 add r7, sp, #0 + 8003bfc: 6078 str r0, [r7, #4] + 8003bfe: 460b mov r3, r1 + 8003c00: 70fb strb r3, [r7, #3] + 8003c02: 687b ldr r3, [r7, #4] + 8003c04: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 + 8003c08: 2b01 cmp r3, #1 + 8003c0a: d101 bne.n 8003c10 + 8003c0c: 2302 movs r3, #2 + 8003c0e: e012 b.n 8003c36 + 8003c10: 687b ldr r3, [r7, #4] + 8003c12: 2201 movs r2, #1 + 8003c14: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003c18: 687b ldr r3, [r7, #4] + 8003c1a: 78fa ldrb r2, [r7, #3] + 8003c1c: 745a strb r2, [r3, #17] + 8003c1e: 687b ldr r3, [r7, #4] + 8003c20: 681b ldr r3, [r3, #0] + 8003c22: 78fa ldrb r2, [r7, #3] + 8003c24: 4611 mov r1, r2 + 8003c26: 4618 mov r0, r3 + 8003c28: f004 ffa0 bl 8008b6c + 8003c2c: 687b ldr r3, [r7, #4] + 8003c2e: 2200 movs r2, #0 + 8003c30: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003c34: 2300 movs r3, #0 + 8003c36: 4618 mov r0, r3 + 8003c38: 3708 adds r7, #8 + 8003c3a: 46bd mov sp, r7 + 8003c3c: bd80 pop {r7, pc} + +08003c3e : + 8003c3e: b580 push {r7, lr} + 8003c40: b084 sub sp, #16 + 8003c42: af00 add r7, sp, #0 + 8003c44: 6078 str r0, [r7, #4] + 8003c46: 4608 mov r0, r1 + 8003c48: 4611 mov r1, r2 + 8003c4a: 461a mov r2, r3 + 8003c4c: 4603 mov r3, r0 + 8003c4e: 70fb strb r3, [r7, #3] + 8003c50: 460b mov r3, r1 + 8003c52: 803b strh r3, [r7, #0] + 8003c54: 4613 mov r3, r2 + 8003c56: 70bb strb r3, [r7, #2] + 8003c58: 2300 movs r3, #0 + 8003c5a: 72fb strb r3, [r7, #11] + 8003c5c: f997 3003 ldrsb.w r3, [r7, #3] + 8003c60: 2b00 cmp r3, #0 + 8003c62: da0f bge.n 8003c84 + 8003c64: 78fb ldrb r3, [r7, #3] + 8003c66: f003 020f and.w r2, r3, #15 + 8003c6a: 4613 mov r3, r2 + 8003c6c: 00db lsls r3, r3, #3 + 8003c6e: 4413 add r3, r2 + 8003c70: 009b lsls r3, r3, #2 + 8003c72: 3310 adds r3, #16 + 8003c74: 687a ldr r2, [r7, #4] + 8003c76: 4413 add r3, r2 + 8003c78: 3304 adds r3, #4 + 8003c7a: 60fb str r3, [r7, #12] + 8003c7c: 68fb ldr r3, [r7, #12] + 8003c7e: 2201 movs r2, #1 + 8003c80: 705a strb r2, [r3, #1] + 8003c82: e00f b.n 8003ca4 + 8003c84: 78fb ldrb r3, [r7, #3] + 8003c86: f003 020f and.w r2, r3, #15 + 8003c8a: 4613 mov r3, r2 + 8003c8c: 00db lsls r3, r3, #3 + 8003c8e: 4413 add r3, r2 + 8003c90: 009b lsls r3, r3, #2 + 8003c92: f503 7314 add.w r3, r3, #592 @ 0x250 + 8003c96: 687a ldr r2, [r7, #4] + 8003c98: 4413 add r3, r2 + 8003c9a: 3304 adds r3, #4 + 8003c9c: 60fb str r3, [r7, #12] + 8003c9e: 68fb ldr r3, [r7, #12] + 8003ca0: 2200 movs r2, #0 + 8003ca2: 705a strb r2, [r3, #1] + 8003ca4: 78fb ldrb r3, [r7, #3] + 8003ca6: f003 030f and.w r3, r3, #15 + 8003caa: b2da uxtb r2, r3 + 8003cac: 68fb ldr r3, [r7, #12] + 8003cae: 701a strb r2, [r3, #0] + 8003cb0: 883b ldrh r3, [r7, #0] + 8003cb2: f3c3 020a ubfx r2, r3, #0, #11 + 8003cb6: 68fb ldr r3, [r7, #12] + 8003cb8: 609a str r2, [r3, #8] + 8003cba: 68fb ldr r3, [r7, #12] + 8003cbc: 78ba ldrb r2, [r7, #2] + 8003cbe: 711a strb r2, [r3, #4] + 8003cc0: 68fb ldr r3, [r7, #12] + 8003cc2: 785b ldrb r3, [r3, #1] + 8003cc4: 2b00 cmp r3, #0 + 8003cc6: d004 beq.n 8003cd2 + 8003cc8: 68fb ldr r3, [r7, #12] + 8003cca: 781b ldrb r3, [r3, #0] + 8003ccc: 461a mov r2, r3 + 8003cce: 68fb ldr r3, [r7, #12] + 8003cd0: 835a strh r2, [r3, #26] + 8003cd2: 78bb ldrb r3, [r7, #2] + 8003cd4: 2b02 cmp r3, #2 + 8003cd6: d102 bne.n 8003cde + 8003cd8: 68fb ldr r3, [r7, #12] + 8003cda: 2200 movs r2, #0 + 8003cdc: 715a strb r2, [r3, #5] + 8003cde: 687b ldr r3, [r7, #4] + 8003ce0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 + 8003ce4: 2b01 cmp r3, #1 + 8003ce6: d101 bne.n 8003cec + 8003ce8: 2302 movs r3, #2 + 8003cea: e00e b.n 8003d0a + 8003cec: 687b ldr r3, [r7, #4] + 8003cee: 2201 movs r2, #1 + 8003cf0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003cf4: 687b ldr r3, [r7, #4] + 8003cf6: 681b ldr r3, [r3, #0] + 8003cf8: 68f9 ldr r1, [r7, #12] + 8003cfa: 4618 mov r0, r3 + 8003cfc: f004 f920 bl 8007f40 + 8003d00: 687b ldr r3, [r7, #4] + 8003d02: 2200 movs r2, #0 + 8003d04: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003d08: 7afb ldrb r3, [r7, #11] + 8003d0a: 4618 mov r0, r3 + 8003d0c: 3710 adds r7, #16 + 8003d0e: 46bd mov sp, r7 + 8003d10: bd80 pop {r7, pc} + +08003d12 : + 8003d12: b580 push {r7, lr} + 8003d14: b084 sub sp, #16 + 8003d16: af00 add r7, sp, #0 + 8003d18: 6078 str r0, [r7, #4] + 8003d1a: 460b mov r3, r1 + 8003d1c: 70fb strb r3, [r7, #3] + 8003d1e: f997 3003 ldrsb.w r3, [r7, #3] + 8003d22: 2b00 cmp r3, #0 + 8003d24: da0f bge.n 8003d46 + 8003d26: 78fb ldrb r3, [r7, #3] + 8003d28: f003 020f and.w r2, r3, #15 + 8003d2c: 4613 mov r3, r2 + 8003d2e: 00db lsls r3, r3, #3 + 8003d30: 4413 add r3, r2 + 8003d32: 009b lsls r3, r3, #2 + 8003d34: 3310 adds r3, #16 + 8003d36: 687a ldr r2, [r7, #4] + 8003d38: 4413 add r3, r2 + 8003d3a: 3304 adds r3, #4 + 8003d3c: 60fb str r3, [r7, #12] + 8003d3e: 68fb ldr r3, [r7, #12] + 8003d40: 2201 movs r2, #1 + 8003d42: 705a strb r2, [r3, #1] + 8003d44: e00f b.n 8003d66 + 8003d46: 78fb ldrb r3, [r7, #3] + 8003d48: f003 020f and.w r2, r3, #15 + 8003d4c: 4613 mov r3, r2 + 8003d4e: 00db lsls r3, r3, #3 + 8003d50: 4413 add r3, r2 + 8003d52: 009b lsls r3, r3, #2 + 8003d54: f503 7314 add.w r3, r3, #592 @ 0x250 + 8003d58: 687a ldr r2, [r7, #4] + 8003d5a: 4413 add r3, r2 + 8003d5c: 3304 adds r3, #4 + 8003d5e: 60fb str r3, [r7, #12] + 8003d60: 68fb ldr r3, [r7, #12] + 8003d62: 2200 movs r2, #0 + 8003d64: 705a strb r2, [r3, #1] + 8003d66: 78fb ldrb r3, [r7, #3] + 8003d68: f003 030f and.w r3, r3, #15 + 8003d6c: b2da uxtb r2, r3 + 8003d6e: 68fb ldr r3, [r7, #12] + 8003d70: 701a strb r2, [r3, #0] + 8003d72: 687b ldr r3, [r7, #4] + 8003d74: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 + 8003d78: 2b01 cmp r3, #1 + 8003d7a: d101 bne.n 8003d80 + 8003d7c: 2302 movs r3, #2 + 8003d7e: e00e b.n 8003d9e + 8003d80: 687b ldr r3, [r7, #4] + 8003d82: 2201 movs r2, #1 + 8003d84: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003d88: 687b ldr r3, [r7, #4] + 8003d8a: 681b ldr r3, [r3, #0] + 8003d8c: 68f9 ldr r1, [r7, #12] + 8003d8e: 4618 mov r0, r3 + 8003d90: f004 f95e bl 8008050 + 8003d94: 687b ldr r3, [r7, #4] + 8003d96: 2200 movs r2, #0 + 8003d98: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003d9c: 2300 movs r3, #0 + 8003d9e: 4618 mov r0, r3 + 8003da0: 3710 adds r7, #16 + 8003da2: 46bd mov sp, r7 + 8003da4: bd80 pop {r7, pc} + +08003da6 : + 8003da6: b580 push {r7, lr} + 8003da8: b086 sub sp, #24 + 8003daa: af00 add r7, sp, #0 + 8003dac: 60f8 str r0, [r7, #12] + 8003dae: 607a str r2, [r7, #4] + 8003db0: 603b str r3, [r7, #0] + 8003db2: 460b mov r3, r1 + 8003db4: 72fb strb r3, [r7, #11] + 8003db6: 7afb ldrb r3, [r7, #11] + 8003db8: f003 020f and.w r2, r3, #15 + 8003dbc: 4613 mov r3, r2 + 8003dbe: 00db lsls r3, r3, #3 + 8003dc0: 4413 add r3, r2 + 8003dc2: 009b lsls r3, r3, #2 + 8003dc4: f503 7314 add.w r3, r3, #592 @ 0x250 + 8003dc8: 68fa ldr r2, [r7, #12] + 8003dca: 4413 add r3, r2 + 8003dcc: 3304 adds r3, #4 + 8003dce: 617b str r3, [r7, #20] + 8003dd0: 697b ldr r3, [r7, #20] + 8003dd2: 687a ldr r2, [r7, #4] + 8003dd4: 60da str r2, [r3, #12] + 8003dd6: 697b ldr r3, [r7, #20] + 8003dd8: 683a ldr r2, [r7, #0] + 8003dda: 611a str r2, [r3, #16] + 8003ddc: 697b ldr r3, [r7, #20] + 8003dde: 2200 movs r2, #0 + 8003de0: 615a str r2, [r3, #20] + 8003de2: 697b ldr r3, [r7, #20] + 8003de4: 2200 movs r2, #0 + 8003de6: 705a strb r2, [r3, #1] + 8003de8: 7afb ldrb r3, [r7, #11] + 8003dea: f003 030f and.w r3, r3, #15 + 8003dee: b2da uxtb r2, r3 + 8003df0: 697b ldr r3, [r7, #20] + 8003df2: 701a strb r2, [r3, #0] + 8003df4: 68fb ldr r3, [r7, #12] + 8003df6: 799b ldrb r3, [r3, #6] + 8003df8: 2b01 cmp r3, #1 + 8003dfa: d102 bne.n 8003e02 + 8003dfc: 687a ldr r2, [r7, #4] + 8003dfe: 697b ldr r3, [r7, #20] + 8003e00: 61da str r2, [r3, #28] + 8003e02: 68fb ldr r3, [r7, #12] + 8003e04: 6818 ldr r0, [r3, #0] + 8003e06: 68fb ldr r3, [r7, #12] + 8003e08: 799b ldrb r3, [r3, #6] + 8003e0a: 461a mov r2, r3 + 8003e0c: 6979 ldr r1, [r7, #20] + 8003e0e: f004 f9fb bl 8008208 + 8003e12: 2300 movs r3, #0 + 8003e14: 4618 mov r0, r3 + 8003e16: 3718 adds r7, #24 + 8003e18: 46bd mov sp, r7 + 8003e1a: bd80 pop {r7, pc} + +08003e1c : + 8003e1c: b580 push {r7, lr} + 8003e1e: b086 sub sp, #24 + 8003e20: af00 add r7, sp, #0 + 8003e22: 60f8 str r0, [r7, #12] + 8003e24: 607a str r2, [r7, #4] + 8003e26: 603b str r3, [r7, #0] + 8003e28: 460b mov r3, r1 + 8003e2a: 72fb strb r3, [r7, #11] + 8003e2c: 7afb ldrb r3, [r7, #11] + 8003e2e: f003 020f and.w r2, r3, #15 + 8003e32: 4613 mov r3, r2 + 8003e34: 00db lsls r3, r3, #3 + 8003e36: 4413 add r3, r2 + 8003e38: 009b lsls r3, r3, #2 + 8003e3a: 3310 adds r3, #16 + 8003e3c: 68fa ldr r2, [r7, #12] + 8003e3e: 4413 add r3, r2 + 8003e40: 3304 adds r3, #4 + 8003e42: 617b str r3, [r7, #20] + 8003e44: 697b ldr r3, [r7, #20] + 8003e46: 687a ldr r2, [r7, #4] + 8003e48: 60da str r2, [r3, #12] + 8003e4a: 697b ldr r3, [r7, #20] + 8003e4c: 683a ldr r2, [r7, #0] + 8003e4e: 611a str r2, [r3, #16] + 8003e50: 697b ldr r3, [r7, #20] + 8003e52: 2200 movs r2, #0 + 8003e54: 615a str r2, [r3, #20] + 8003e56: 697b ldr r3, [r7, #20] + 8003e58: 2201 movs r2, #1 + 8003e5a: 705a strb r2, [r3, #1] + 8003e5c: 7afb ldrb r3, [r7, #11] + 8003e5e: f003 030f and.w r3, r3, #15 + 8003e62: b2da uxtb r2, r3 + 8003e64: 697b ldr r3, [r7, #20] + 8003e66: 701a strb r2, [r3, #0] + 8003e68: 68fb ldr r3, [r7, #12] + 8003e6a: 799b ldrb r3, [r3, #6] + 8003e6c: 2b01 cmp r3, #1 + 8003e6e: d102 bne.n 8003e76 + 8003e70: 687a ldr r2, [r7, #4] + 8003e72: 697b ldr r3, [r7, #20] + 8003e74: 61da str r2, [r3, #28] + 8003e76: 68fb ldr r3, [r7, #12] + 8003e78: 6818 ldr r0, [r3, #0] + 8003e7a: 68fb ldr r3, [r7, #12] + 8003e7c: 799b ldrb r3, [r3, #6] + 8003e7e: 461a mov r2, r3 + 8003e80: 6979 ldr r1, [r7, #20] + 8003e82: f004 f9c1 bl 8008208 + 8003e86: 2300 movs r3, #0 + 8003e88: 4618 mov r0, r3 + 8003e8a: 3718 adds r7, #24 + 8003e8c: 46bd mov sp, r7 + 8003e8e: bd80 pop {r7, pc} + +08003e90 : + 8003e90: b580 push {r7, lr} + 8003e92: b084 sub sp, #16 + 8003e94: af00 add r7, sp, #0 + 8003e96: 6078 str r0, [r7, #4] + 8003e98: 460b mov r3, r1 + 8003e9a: 70fb strb r3, [r7, #3] + 8003e9c: 78fb ldrb r3, [r7, #3] + 8003e9e: f003 030f and.w r3, r3, #15 + 8003ea2: 687a ldr r2, [r7, #4] + 8003ea4: 7912 ldrb r2, [r2, #4] + 8003ea6: 4293 cmp r3, r2 + 8003ea8: d901 bls.n 8003eae + 8003eaa: 2301 movs r3, #1 + 8003eac: e04f b.n 8003f4e + 8003eae: f997 3003 ldrsb.w r3, [r7, #3] + 8003eb2: 2b00 cmp r3, #0 + 8003eb4: da0f bge.n 8003ed6 + 8003eb6: 78fb ldrb r3, [r7, #3] + 8003eb8: f003 020f and.w r2, r3, #15 + 8003ebc: 4613 mov r3, r2 + 8003ebe: 00db lsls r3, r3, #3 + 8003ec0: 4413 add r3, r2 + 8003ec2: 009b lsls r3, r3, #2 + 8003ec4: 3310 adds r3, #16 + 8003ec6: 687a ldr r2, [r7, #4] + 8003ec8: 4413 add r3, r2 + 8003eca: 3304 adds r3, #4 + 8003ecc: 60fb str r3, [r7, #12] + 8003ece: 68fb ldr r3, [r7, #12] + 8003ed0: 2201 movs r2, #1 + 8003ed2: 705a strb r2, [r3, #1] + 8003ed4: e00d b.n 8003ef2 + 8003ed6: 78fa ldrb r2, [r7, #3] + 8003ed8: 4613 mov r3, r2 + 8003eda: 00db lsls r3, r3, #3 + 8003edc: 4413 add r3, r2 + 8003ede: 009b lsls r3, r3, #2 + 8003ee0: f503 7314 add.w r3, r3, #592 @ 0x250 + 8003ee4: 687a ldr r2, [r7, #4] + 8003ee6: 4413 add r3, r2 + 8003ee8: 3304 adds r3, #4 + 8003eea: 60fb str r3, [r7, #12] + 8003eec: 68fb ldr r3, [r7, #12] + 8003eee: 2200 movs r2, #0 + 8003ef0: 705a strb r2, [r3, #1] + 8003ef2: 68fb ldr r3, [r7, #12] + 8003ef4: 2201 movs r2, #1 + 8003ef6: 709a strb r2, [r3, #2] + 8003ef8: 78fb ldrb r3, [r7, #3] + 8003efa: f003 030f and.w r3, r3, #15 + 8003efe: b2da uxtb r2, r3 + 8003f00: 68fb ldr r3, [r7, #12] + 8003f02: 701a strb r2, [r3, #0] + 8003f04: 687b ldr r3, [r7, #4] + 8003f06: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 + 8003f0a: 2b01 cmp r3, #1 + 8003f0c: d101 bne.n 8003f12 + 8003f0e: 2302 movs r3, #2 + 8003f10: e01d b.n 8003f4e + 8003f12: 687b ldr r3, [r7, #4] + 8003f14: 2201 movs r2, #1 + 8003f16: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003f1a: 687b ldr r3, [r7, #4] + 8003f1c: 681b ldr r3, [r3, #0] + 8003f1e: 68f9 ldr r1, [r7, #12] + 8003f20: 4618 mov r0, r3 + 8003f22: f004 fd4f bl 80089c4 + 8003f26: 78fb ldrb r3, [r7, #3] + 8003f28: f003 030f and.w r3, r3, #15 + 8003f2c: 2b00 cmp r3, #0 + 8003f2e: d109 bne.n 8003f44 + 8003f30: 687b ldr r3, [r7, #4] + 8003f32: 6818 ldr r0, [r3, #0] + 8003f34: 687b ldr r3, [r7, #4] + 8003f36: 7999 ldrb r1, [r3, #6] + 8003f38: 687b ldr r3, [r7, #4] + 8003f3a: f203 439c addw r3, r3, #1180 @ 0x49c + 8003f3e: 461a mov r2, r3 + 8003f40: f004 ff40 bl 8008dc4 + 8003f44: 687b ldr r3, [r7, #4] + 8003f46: 2200 movs r2, #0 + 8003f48: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003f4c: 2300 movs r3, #0 + 8003f4e: 4618 mov r0, r3 + 8003f50: 3710 adds r7, #16 + 8003f52: 46bd mov sp, r7 + 8003f54: bd80 pop {r7, pc} + +08003f56 : + 8003f56: b580 push {r7, lr} + 8003f58: b084 sub sp, #16 + 8003f5a: af00 add r7, sp, #0 + 8003f5c: 6078 str r0, [r7, #4] + 8003f5e: 460b mov r3, r1 + 8003f60: 70fb strb r3, [r7, #3] + 8003f62: 78fb ldrb r3, [r7, #3] + 8003f64: f003 030f and.w r3, r3, #15 + 8003f68: 687a ldr r2, [r7, #4] + 8003f6a: 7912 ldrb r2, [r2, #4] + 8003f6c: 4293 cmp r3, r2 + 8003f6e: d901 bls.n 8003f74 + 8003f70: 2301 movs r3, #1 + 8003f72: e042 b.n 8003ffa + 8003f74: f997 3003 ldrsb.w r3, [r7, #3] + 8003f78: 2b00 cmp r3, #0 + 8003f7a: da0f bge.n 8003f9c + 8003f7c: 78fb ldrb r3, [r7, #3] + 8003f7e: f003 020f and.w r2, r3, #15 + 8003f82: 4613 mov r3, r2 + 8003f84: 00db lsls r3, r3, #3 + 8003f86: 4413 add r3, r2 + 8003f88: 009b lsls r3, r3, #2 + 8003f8a: 3310 adds r3, #16 + 8003f8c: 687a ldr r2, [r7, #4] + 8003f8e: 4413 add r3, r2 + 8003f90: 3304 adds r3, #4 + 8003f92: 60fb str r3, [r7, #12] + 8003f94: 68fb ldr r3, [r7, #12] + 8003f96: 2201 movs r2, #1 + 8003f98: 705a strb r2, [r3, #1] + 8003f9a: e00f b.n 8003fbc + 8003f9c: 78fb ldrb r3, [r7, #3] + 8003f9e: f003 020f and.w r2, r3, #15 + 8003fa2: 4613 mov r3, r2 + 8003fa4: 00db lsls r3, r3, #3 + 8003fa6: 4413 add r3, r2 + 8003fa8: 009b lsls r3, r3, #2 + 8003faa: f503 7314 add.w r3, r3, #592 @ 0x250 + 8003fae: 687a ldr r2, [r7, #4] + 8003fb0: 4413 add r3, r2 + 8003fb2: 3304 adds r3, #4 + 8003fb4: 60fb str r3, [r7, #12] + 8003fb6: 68fb ldr r3, [r7, #12] + 8003fb8: 2200 movs r2, #0 + 8003fba: 705a strb r2, [r3, #1] + 8003fbc: 68fb ldr r3, [r7, #12] + 8003fbe: 2200 movs r2, #0 + 8003fc0: 709a strb r2, [r3, #2] + 8003fc2: 78fb ldrb r3, [r7, #3] + 8003fc4: f003 030f and.w r3, r3, #15 + 8003fc8: b2da uxtb r2, r3 + 8003fca: 68fb ldr r3, [r7, #12] + 8003fcc: 701a strb r2, [r3, #0] + 8003fce: 687b ldr r3, [r7, #4] + 8003fd0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 + 8003fd4: 2b01 cmp r3, #1 + 8003fd6: d101 bne.n 8003fdc + 8003fd8: 2302 movs r3, #2 + 8003fda: e00e b.n 8003ffa + 8003fdc: 687b ldr r3, [r7, #4] + 8003fde: 2201 movs r2, #1 + 8003fe0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003fe4: 687b ldr r3, [r7, #4] + 8003fe6: 681b ldr r3, [r3, #0] + 8003fe8: 68f9 ldr r1, [r7, #12] + 8003fea: 4618 mov r0, r3 + 8003fec: f004 fd58 bl 8008aa0 + 8003ff0: 687b ldr r3, [r7, #4] + 8003ff2: 2200 movs r2, #0 + 8003ff4: f883 2494 strb.w r2, [r3, #1172] @ 0x494 + 8003ff8: 2300 movs r3, #0 + 8003ffa: 4618 mov r0, r3 + 8003ffc: 3710 adds r7, #16 + 8003ffe: 46bd mov sp, r7 + 8004000: bd80 pop {r7, pc} + +08004002 : + 8004002: b580 push {r7, lr} + 8004004: b084 sub sp, #16 + 8004006: af00 add r7, sp, #0 + 8004008: 6078 str r0, [r7, #4] + 800400a: 460b mov r3, r1 + 800400c: 70fb strb r3, [r7, #3] + 800400e: f997 3003 ldrsb.w r3, [r7, #3] + 8004012: 2b00 cmp r3, #0 + 8004014: da0c bge.n 8004030 + 8004016: 78fb ldrb r3, [r7, #3] + 8004018: f003 020f and.w r2, r3, #15 + 800401c: 4613 mov r3, r2 + 800401e: 00db lsls r3, r3, #3 + 8004020: 4413 add r3, r2 + 8004022: 009b lsls r3, r3, #2 + 8004024: 3310 adds r3, #16 + 8004026: 687a ldr r2, [r7, #4] + 8004028: 4413 add r3, r2 + 800402a: 3304 adds r3, #4 + 800402c: 60fb str r3, [r7, #12] + 800402e: e00c b.n 800404a + 8004030: 78fb ldrb r3, [r7, #3] + 8004032: f003 020f and.w r2, r3, #15 + 8004036: 4613 mov r3, r2 + 8004038: 00db lsls r3, r3, #3 + 800403a: 4413 add r3, r2 + 800403c: 009b lsls r3, r3, #2 + 800403e: f503 7314 add.w r3, r3, #592 @ 0x250 + 8004042: 687a ldr r2, [r7, #4] + 8004044: 4413 add r3, r2 + 8004046: 3304 adds r3, #4 + 8004048: 60fb str r3, [r7, #12] + 800404a: 687b ldr r3, [r7, #4] + 800404c: 681b ldr r3, [r3, #0] + 800404e: 68f9 ldr r1, [r7, #12] + 8004050: 4618 mov r0, r3 + 8004052: f004 fb77 bl 8008744 + 8004056: 4603 mov r3, r0 + 8004058: 72fb strb r3, [r7, #11] + 800405a: 7afb ldrb r3, [r7, #11] + 800405c: 4618 mov r0, r3 + 800405e: 3710 adds r7, #16 + 8004060: 46bd mov sp, r7 + 8004062: bd80 pop {r7, pc} + +08004064 : + 8004064: b580 push {r7, lr} + 8004066: b08a sub sp, #40 @ 0x28 + 8004068: af02 add r7, sp, #8 + 800406a: 6078 str r0, [r7, #4] + 800406c: 6039 str r1, [r7, #0] + 800406e: 687b ldr r3, [r7, #4] + 8004070: 681b ldr r3, [r3, #0] + 8004072: 617b str r3, [r7, #20] + 8004074: 697b ldr r3, [r7, #20] + 8004076: 613b str r3, [r7, #16] + 8004078: 683a ldr r2, [r7, #0] + 800407a: 4613 mov r3, r2 + 800407c: 00db lsls r3, r3, #3 + 800407e: 4413 add r3, r2 + 8004080: 009b lsls r3, r3, #2 + 8004082: 3310 adds r3, #16 + 8004084: 687a ldr r2, [r7, #4] + 8004086: 4413 add r3, r2 + 8004088: 3304 adds r3, #4 + 800408a: 60fb str r3, [r7, #12] + 800408c: 68fb ldr r3, [r7, #12] + 800408e: 695a ldr r2, [r3, #20] + 8004090: 68fb ldr r3, [r7, #12] + 8004092: 691b ldr r3, [r3, #16] + 8004094: 429a cmp r2, r3 + 8004096: d901 bls.n 800409c + 8004098: 2301 movs r3, #1 + 800409a: e06b b.n 8004174 + 800409c: 68fb ldr r3, [r7, #12] + 800409e: 691a ldr r2, [r3, #16] + 80040a0: 68fb ldr r3, [r7, #12] + 80040a2: 695b ldr r3, [r3, #20] + 80040a4: 1ad3 subs r3, r2, r3 + 80040a6: 61fb str r3, [r7, #28] + 80040a8: 68fb ldr r3, [r7, #12] + 80040aa: 689b ldr r3, [r3, #8] + 80040ac: 69fa ldr r2, [r7, #28] + 80040ae: 429a cmp r2, r3 + 80040b0: d902 bls.n 80040b8 + 80040b2: 68fb ldr r3, [r7, #12] + 80040b4: 689b ldr r3, [r3, #8] + 80040b6: 61fb str r3, [r7, #28] + 80040b8: 69fb ldr r3, [r7, #28] + 80040ba: 3303 adds r3, #3 + 80040bc: 089b lsrs r3, r3, #2 + 80040be: 61bb str r3, [r7, #24] + 80040c0: e02a b.n 8004118 + 80040c2: 68fb ldr r3, [r7, #12] + 80040c4: 691a ldr r2, [r3, #16] + 80040c6: 68fb ldr r3, [r7, #12] + 80040c8: 695b ldr r3, [r3, #20] + 80040ca: 1ad3 subs r3, r2, r3 + 80040cc: 61fb str r3, [r7, #28] + 80040ce: 68fb ldr r3, [r7, #12] + 80040d0: 689b ldr r3, [r3, #8] + 80040d2: 69fa ldr r2, [r7, #28] + 80040d4: 429a cmp r2, r3 + 80040d6: d902 bls.n 80040de + 80040d8: 68fb ldr r3, [r7, #12] + 80040da: 689b ldr r3, [r3, #8] + 80040dc: 61fb str r3, [r7, #28] + 80040de: 69fb ldr r3, [r7, #28] + 80040e0: 3303 adds r3, #3 + 80040e2: 089b lsrs r3, r3, #2 + 80040e4: 61bb str r3, [r7, #24] + 80040e6: 68fb ldr r3, [r7, #12] + 80040e8: 68d9 ldr r1, [r3, #12] + 80040ea: 683b ldr r3, [r7, #0] + 80040ec: b2da uxtb r2, r3 + 80040ee: 69fb ldr r3, [r7, #28] + 80040f0: b298 uxth r0, r3 + 80040f2: 687b ldr r3, [r7, #4] + 80040f4: 799b ldrb r3, [r3, #6] + 80040f6: 9300 str r3, [sp, #0] + 80040f8: 4603 mov r3, r0 + 80040fa: 6978 ldr r0, [r7, #20] + 80040fc: f004 fbcc bl 8008898 + 8004100: 68fb ldr r3, [r7, #12] + 8004102: 68da ldr r2, [r3, #12] + 8004104: 69fb ldr r3, [r7, #28] + 8004106: 441a add r2, r3 + 8004108: 68fb ldr r3, [r7, #12] + 800410a: 60da str r2, [r3, #12] + 800410c: 68fb ldr r3, [r7, #12] + 800410e: 695a ldr r2, [r3, #20] + 8004110: 69fb ldr r3, [r7, #28] + 8004112: 441a add r2, r3 + 8004114: 68fb ldr r3, [r7, #12] + 8004116: 615a str r2, [r3, #20] + 8004118: 683b ldr r3, [r7, #0] + 800411a: 015a lsls r2, r3, #5 + 800411c: 693b ldr r3, [r7, #16] + 800411e: 4413 add r3, r2 + 8004120: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8004124: 699b ldr r3, [r3, #24] + 8004126: b29b uxth r3, r3 + 8004128: 69ba ldr r2, [r7, #24] + 800412a: 429a cmp r2, r3 + 800412c: d809 bhi.n 8004142 + 800412e: 68fb ldr r3, [r7, #12] + 8004130: 695a ldr r2, [r3, #20] + 8004132: 68fb ldr r3, [r7, #12] + 8004134: 691b ldr r3, [r3, #16] + 8004136: 429a cmp r2, r3 + 8004138: d203 bcs.n 8004142 + 800413a: 68fb ldr r3, [r7, #12] + 800413c: 691b ldr r3, [r3, #16] + 800413e: 2b00 cmp r3, #0 + 8004140: d1bf bne.n 80040c2 + 8004142: 68fb ldr r3, [r7, #12] + 8004144: 691a ldr r2, [r3, #16] + 8004146: 68fb ldr r3, [r7, #12] + 8004148: 695b ldr r3, [r3, #20] + 800414a: 429a cmp r2, r3 + 800414c: d811 bhi.n 8004172 + 800414e: 683b ldr r3, [r7, #0] + 8004150: f003 030f and.w r3, r3, #15 + 8004154: 2201 movs r2, #1 + 8004156: fa02 f303 lsl.w r3, r2, r3 + 800415a: 60bb str r3, [r7, #8] + 800415c: 693b ldr r3, [r7, #16] + 800415e: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8004162: 6b5a ldr r2, [r3, #52] @ 0x34 + 8004164: 68bb ldr r3, [r7, #8] + 8004166: 43db mvns r3, r3 + 8004168: 6939 ldr r1, [r7, #16] + 800416a: f501 6100 add.w r1, r1, #2048 @ 0x800 + 800416e: 4013 ands r3, r2 + 8004170: 634b str r3, [r1, #52] @ 0x34 + 8004172: 2300 movs r3, #0 + 8004174: 4618 mov r0, r3 + 8004176: 3720 adds r7, #32 + 8004178: 46bd mov sp, r7 + 800417a: bd80 pop {r7, pc} + +0800417c : + 800417c: b580 push {r7, lr} + 800417e: b088 sub sp, #32 + 8004180: af00 add r7, sp, #0 + 8004182: 6078 str r0, [r7, #4] + 8004184: 6039 str r1, [r7, #0] + 8004186: 687b ldr r3, [r7, #4] + 8004188: 681b ldr r3, [r3, #0] + 800418a: 61fb str r3, [r7, #28] + 800418c: 69fb ldr r3, [r7, #28] + 800418e: 61bb str r3, [r7, #24] + 8004190: 69fb ldr r3, [r7, #28] + 8004192: 333c adds r3, #60 @ 0x3c + 8004194: 3304 adds r3, #4 + 8004196: 681b ldr r3, [r3, #0] + 8004198: 617b str r3, [r7, #20] + 800419a: 683b ldr r3, [r7, #0] + 800419c: 015a lsls r2, r3, #5 + 800419e: 69bb ldr r3, [r7, #24] + 80041a0: 4413 add r3, r2 + 80041a2: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80041a6: 689b ldr r3, [r3, #8] + 80041a8: 613b str r3, [r7, #16] + 80041aa: 687b ldr r3, [r7, #4] + 80041ac: 799b ldrb r3, [r3, #6] + 80041ae: 2b01 cmp r3, #1 + 80041b0: d17b bne.n 80042aa + 80041b2: 693b ldr r3, [r7, #16] + 80041b4: f003 0308 and.w r3, r3, #8 + 80041b8: 2b00 cmp r3, #0 + 80041ba: d015 beq.n 80041e8 + 80041bc: 697b ldr r3, [r7, #20] + 80041be: 4a61 ldr r2, [pc, #388] @ (8004344 ) + 80041c0: 4293 cmp r3, r2 + 80041c2: f240 80b9 bls.w 8004338 + 80041c6: 693b ldr r3, [r7, #16] + 80041c8: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 80041cc: 2b00 cmp r3, #0 + 80041ce: f000 80b3 beq.w 8004338 + 80041d2: 683b ldr r3, [r7, #0] + 80041d4: 015a lsls r2, r3, #5 + 80041d6: 69bb ldr r3, [r7, #24] + 80041d8: 4413 add r3, r2 + 80041da: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80041de: 461a mov r2, r3 + 80041e0: f44f 4300 mov.w r3, #32768 @ 0x8000 + 80041e4: 6093 str r3, [r2, #8] + 80041e6: e0a7 b.n 8004338 + 80041e8: 693b ldr r3, [r7, #16] + 80041ea: f003 0320 and.w r3, r3, #32 + 80041ee: 2b00 cmp r3, #0 + 80041f0: d009 beq.n 8004206 + 80041f2: 683b ldr r3, [r7, #0] + 80041f4: 015a lsls r2, r3, #5 + 80041f6: 69bb ldr r3, [r7, #24] + 80041f8: 4413 add r3, r2 + 80041fa: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80041fe: 461a mov r2, r3 + 8004200: 2320 movs r3, #32 + 8004202: 6093 str r3, [r2, #8] + 8004204: e098 b.n 8004338 + 8004206: 693b ldr r3, [r7, #16] + 8004208: f003 0328 and.w r3, r3, #40 @ 0x28 + 800420c: 2b00 cmp r3, #0 + 800420e: f040 8093 bne.w 8004338 + 8004212: 697b ldr r3, [r7, #20] + 8004214: 4a4b ldr r2, [pc, #300] @ (8004344 ) + 8004216: 4293 cmp r3, r2 + 8004218: d90f bls.n 800423a + 800421a: 693b ldr r3, [r7, #16] + 800421c: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 8004220: 2b00 cmp r3, #0 + 8004222: d00a beq.n 800423a + 8004224: 683b ldr r3, [r7, #0] + 8004226: 015a lsls r2, r3, #5 + 8004228: 69bb ldr r3, [r7, #24] + 800422a: 4413 add r3, r2 + 800422c: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8004230: 461a mov r2, r3 + 8004232: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8004236: 6093 str r3, [r2, #8] + 8004238: e07e b.n 8004338 + 800423a: 683a ldr r2, [r7, #0] + 800423c: 4613 mov r3, r2 + 800423e: 00db lsls r3, r3, #3 + 8004240: 4413 add r3, r2 + 8004242: 009b lsls r3, r3, #2 + 8004244: f503 7314 add.w r3, r3, #592 @ 0x250 + 8004248: 687a ldr r2, [r7, #4] + 800424a: 4413 add r3, r2 + 800424c: 3304 adds r3, #4 + 800424e: 60fb str r3, [r7, #12] + 8004250: 68fb ldr r3, [r7, #12] + 8004252: 6a1a ldr r2, [r3, #32] + 8004254: 683b ldr r3, [r7, #0] + 8004256: 0159 lsls r1, r3, #5 + 8004258: 69bb ldr r3, [r7, #24] + 800425a: 440b add r3, r1 + 800425c: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8004260: 691b ldr r3, [r3, #16] + 8004262: f3c3 0312 ubfx r3, r3, #0, #19 + 8004266: 1ad2 subs r2, r2, r3 + 8004268: 68fb ldr r3, [r7, #12] + 800426a: 615a str r2, [r3, #20] + 800426c: 683b ldr r3, [r7, #0] + 800426e: 2b00 cmp r3, #0 + 8004270: d114 bne.n 800429c + 8004272: 68fb ldr r3, [r7, #12] + 8004274: 691b ldr r3, [r3, #16] + 8004276: 2b00 cmp r3, #0 + 8004278: d109 bne.n 800428e + 800427a: 687b ldr r3, [r7, #4] + 800427c: 6818 ldr r0, [r3, #0] + 800427e: 687b ldr r3, [r7, #4] + 8004280: f203 439c addw r3, r3, #1180 @ 0x49c + 8004284: 461a mov r2, r3 + 8004286: 2101 movs r1, #1 + 8004288: f004 fd9c bl 8008dc4 + 800428c: e006 b.n 800429c + 800428e: 68fb ldr r3, [r7, #12] + 8004290: 68da ldr r2, [r3, #12] + 8004292: 68fb ldr r3, [r7, #12] + 8004294: 695b ldr r3, [r3, #20] + 8004296: 441a add r2, r3 + 8004298: 68fb ldr r3, [r7, #12] + 800429a: 60da str r2, [r3, #12] + 800429c: 683b ldr r3, [r7, #0] + 800429e: b2db uxtb r3, r3 + 80042a0: 4619 mov r1, r3 + 80042a2: 6878 ldr r0, [r7, #4] + 80042a4: f006 fd6a bl 800ad7c + 80042a8: e046 b.n 8004338 + 80042aa: 697b ldr r3, [r7, #20] + 80042ac: 4a26 ldr r2, [pc, #152] @ (8004348 ) + 80042ae: 4293 cmp r3, r2 + 80042b0: d124 bne.n 80042fc + 80042b2: 693b ldr r3, [r7, #16] + 80042b4: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 80042b8: 2b00 cmp r3, #0 + 80042ba: d00a beq.n 80042d2 + 80042bc: 683b ldr r3, [r7, #0] + 80042be: 015a lsls r2, r3, #5 + 80042c0: 69bb ldr r3, [r7, #24] + 80042c2: 4413 add r3, r2 + 80042c4: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80042c8: 461a mov r2, r3 + 80042ca: f44f 4300 mov.w r3, #32768 @ 0x8000 + 80042ce: 6093 str r3, [r2, #8] + 80042d0: e032 b.n 8004338 + 80042d2: 693b ldr r3, [r7, #16] + 80042d4: f003 0320 and.w r3, r3, #32 + 80042d8: 2b00 cmp r3, #0 + 80042da: d008 beq.n 80042ee + 80042dc: 683b ldr r3, [r7, #0] + 80042de: 015a lsls r2, r3, #5 + 80042e0: 69bb ldr r3, [r7, #24] + 80042e2: 4413 add r3, r2 + 80042e4: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80042e8: 461a mov r2, r3 + 80042ea: 2320 movs r3, #32 + 80042ec: 6093 str r3, [r2, #8] + 80042ee: 683b ldr r3, [r7, #0] + 80042f0: b2db uxtb r3, r3 + 80042f2: 4619 mov r1, r3 + 80042f4: 6878 ldr r0, [r7, #4] + 80042f6: f006 fd41 bl 800ad7c + 80042fa: e01d b.n 8004338 + 80042fc: 683b ldr r3, [r7, #0] + 80042fe: 2b00 cmp r3, #0 + 8004300: d114 bne.n 800432c + 8004302: 6879 ldr r1, [r7, #4] + 8004304: 683a ldr r2, [r7, #0] + 8004306: 4613 mov r3, r2 + 8004308: 00db lsls r3, r3, #3 + 800430a: 4413 add r3, r2 + 800430c: 009b lsls r3, r3, #2 + 800430e: 440b add r3, r1 + 8004310: f503 7319 add.w r3, r3, #612 @ 0x264 + 8004314: 681b ldr r3, [r3, #0] + 8004316: 2b00 cmp r3, #0 + 8004318: d108 bne.n 800432c + 800431a: 687b ldr r3, [r7, #4] + 800431c: 6818 ldr r0, [r3, #0] + 800431e: 687b ldr r3, [r7, #4] + 8004320: f203 439c addw r3, r3, #1180 @ 0x49c + 8004324: 461a mov r2, r3 + 8004326: 2100 movs r1, #0 + 8004328: f004 fd4c bl 8008dc4 + 800432c: 683b ldr r3, [r7, #0] + 800432e: b2db uxtb r3, r3 + 8004330: 4619 mov r1, r3 + 8004332: 6878 ldr r0, [r7, #4] + 8004334: f006 fd22 bl 800ad7c + 8004338: 2300 movs r3, #0 + 800433a: 4618 mov r0, r3 + 800433c: 3720 adds r7, #32 + 800433e: 46bd mov sp, r7 + 8004340: bd80 pop {r7, pc} + 8004342: bf00 nop + 8004344: 4f54300a .word 0x4f54300a + 8004348: 4f54310a .word 0x4f54310a + +0800434c : + 800434c: b580 push {r7, lr} + 800434e: b086 sub sp, #24 + 8004350: af00 add r7, sp, #0 + 8004352: 6078 str r0, [r7, #4] + 8004354: 6039 str r1, [r7, #0] + 8004356: 687b ldr r3, [r7, #4] + 8004358: 681b ldr r3, [r3, #0] + 800435a: 617b str r3, [r7, #20] + 800435c: 697b ldr r3, [r7, #20] + 800435e: 613b str r3, [r7, #16] + 8004360: 697b ldr r3, [r7, #20] + 8004362: 333c adds r3, #60 @ 0x3c + 8004364: 3304 adds r3, #4 + 8004366: 681b ldr r3, [r3, #0] + 8004368: 60fb str r3, [r7, #12] + 800436a: 683b ldr r3, [r7, #0] + 800436c: 015a lsls r2, r3, #5 + 800436e: 693b ldr r3, [r7, #16] + 8004370: 4413 add r3, r2 + 8004372: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8004376: 689b ldr r3, [r3, #8] + 8004378: 60bb str r3, [r7, #8] + 800437a: 68fb ldr r3, [r7, #12] + 800437c: 4a15 ldr r2, [pc, #84] @ (80043d4 ) + 800437e: 4293 cmp r3, r2 + 8004380: d90e bls.n 80043a0 + 8004382: 68bb ldr r3, [r7, #8] + 8004384: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 8004388: 2b00 cmp r3, #0 + 800438a: d009 beq.n 80043a0 + 800438c: 683b ldr r3, [r7, #0] + 800438e: 015a lsls r2, r3, #5 + 8004390: 693b ldr r3, [r7, #16] + 8004392: 4413 add r3, r2 + 8004394: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8004398: 461a mov r2, r3 + 800439a: f44f 4300 mov.w r3, #32768 @ 0x8000 + 800439e: 6093 str r3, [r2, #8] + 80043a0: 6878 ldr r0, [r7, #4] + 80043a2: f006 fcd9 bl 800ad58 + 80043a6: 68fb ldr r3, [r7, #12] + 80043a8: 4a0a ldr r2, [pc, #40] @ (80043d4 ) + 80043aa: 4293 cmp r3, r2 + 80043ac: d90c bls.n 80043c8 + 80043ae: 687b ldr r3, [r7, #4] + 80043b0: 799b ldrb r3, [r3, #6] + 80043b2: 2b01 cmp r3, #1 + 80043b4: d108 bne.n 80043c8 + 80043b6: 687b ldr r3, [r7, #4] + 80043b8: 6818 ldr r0, [r3, #0] + 80043ba: 687b ldr r3, [r7, #4] + 80043bc: f203 439c addw r3, r3, #1180 @ 0x49c + 80043c0: 461a mov r2, r3 + 80043c2: 2101 movs r1, #1 + 80043c4: f004 fcfe bl 8008dc4 + 80043c8: 2300 movs r3, #0 + 80043ca: 4618 mov r0, r3 + 80043cc: 3718 adds r7, #24 + 80043ce: 46bd mov sp, r7 + 80043d0: bd80 pop {r7, pc} + 80043d2: bf00 nop + 80043d4: 4f54300a .word 0x4f54300a + +080043d8 : + 80043d8: b480 push {r7} + 80043da: b085 sub sp, #20 + 80043dc: af00 add r7, sp, #0 + 80043de: 6078 str r0, [r7, #4] + 80043e0: 460b mov r3, r1 + 80043e2: 70fb strb r3, [r7, #3] + 80043e4: 4613 mov r3, r2 + 80043e6: 803b strh r3, [r7, #0] + 80043e8: 687b ldr r3, [r7, #4] + 80043ea: 681b ldr r3, [r3, #0] + 80043ec: 6a5b ldr r3, [r3, #36] @ 0x24 + 80043ee: 60bb str r3, [r7, #8] + 80043f0: 78fb ldrb r3, [r7, #3] + 80043f2: 2b00 cmp r3, #0 + 80043f4: d107 bne.n 8004406 + 80043f6: 883b ldrh r3, [r7, #0] + 80043f8: 0419 lsls r1, r3, #16 + 80043fa: 687b ldr r3, [r7, #4] + 80043fc: 681b ldr r3, [r3, #0] + 80043fe: 68ba ldr r2, [r7, #8] + 8004400: 430a orrs r2, r1 + 8004402: 629a str r2, [r3, #40] @ 0x28 + 8004404: e028 b.n 8004458 + 8004406: 687b ldr r3, [r7, #4] + 8004408: 681b ldr r3, [r3, #0] + 800440a: 6a9b ldr r3, [r3, #40] @ 0x28 + 800440c: 0c1b lsrs r3, r3, #16 + 800440e: 68ba ldr r2, [r7, #8] + 8004410: 4413 add r3, r2 + 8004412: 60bb str r3, [r7, #8] + 8004414: 2300 movs r3, #0 + 8004416: 73fb strb r3, [r7, #15] + 8004418: e00d b.n 8004436 + 800441a: 687b ldr r3, [r7, #4] + 800441c: 681a ldr r2, [r3, #0] + 800441e: 7bfb ldrb r3, [r7, #15] + 8004420: 3340 adds r3, #64 @ 0x40 + 8004422: 009b lsls r3, r3, #2 + 8004424: 4413 add r3, r2 + 8004426: 685b ldr r3, [r3, #4] + 8004428: 0c1b lsrs r3, r3, #16 + 800442a: 68ba ldr r2, [r7, #8] + 800442c: 4413 add r3, r2 + 800442e: 60bb str r3, [r7, #8] + 8004430: 7bfb ldrb r3, [r7, #15] + 8004432: 3301 adds r3, #1 + 8004434: 73fb strb r3, [r7, #15] + 8004436: 7bfa ldrb r2, [r7, #15] + 8004438: 78fb ldrb r3, [r7, #3] + 800443a: 3b01 subs r3, #1 + 800443c: 429a cmp r2, r3 + 800443e: d3ec bcc.n 800441a + 8004440: 883b ldrh r3, [r7, #0] + 8004442: 0418 lsls r0, r3, #16 + 8004444: 687b ldr r3, [r7, #4] + 8004446: 6819 ldr r1, [r3, #0] + 8004448: 78fb ldrb r3, [r7, #3] + 800444a: 3b01 subs r3, #1 + 800444c: 68ba ldr r2, [r7, #8] + 800444e: 4302 orrs r2, r0 + 8004450: 3340 adds r3, #64 @ 0x40 + 8004452: 009b lsls r3, r3, #2 + 8004454: 440b add r3, r1 + 8004456: 605a str r2, [r3, #4] + 8004458: 2300 movs r3, #0 + 800445a: 4618 mov r0, r3 + 800445c: 3714 adds r7, #20 + 800445e: 46bd mov sp, r7 + 8004460: f85d 7b04 ldr.w r7, [sp], #4 + 8004464: 4770 bx lr + +08004466 : + 8004466: b480 push {r7} + 8004468: b083 sub sp, #12 + 800446a: af00 add r7, sp, #0 + 800446c: 6078 str r0, [r7, #4] + 800446e: 460b mov r3, r1 + 8004470: 807b strh r3, [r7, #2] + 8004472: 687b ldr r3, [r7, #4] + 8004474: 681b ldr r3, [r3, #0] + 8004476: 887a ldrh r2, [r7, #2] + 8004478: 625a str r2, [r3, #36] @ 0x24 + 800447a: 2300 movs r3, #0 + 800447c: 4618 mov r0, r3 + 800447e: 370c adds r7, #12 + 8004480: 46bd mov sp, r7 + 8004482: f85d 7b04 ldr.w r7, [sp], #4 + 8004486: 4770 bx lr + +08004488 : + 8004488: b480 push {r7} + 800448a: b085 sub sp, #20 + 800448c: af00 add r7, sp, #0 + 800448e: 6078 str r0, [r7, #4] + 8004490: 687b ldr r3, [r7, #4] + 8004492: 681b ldr r3, [r3, #0] + 8004494: 60fb str r3, [r7, #12] + 8004496: 687b ldr r3, [r7, #4] + 8004498: 2201 movs r2, #1 + 800449a: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8 + 800449e: 687b ldr r3, [r7, #4] + 80044a0: 2200 movs r2, #0 + 80044a2: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc + 80044a6: 68fb ldr r3, [r7, #12] + 80044a8: 699b ldr r3, [r3, #24] + 80044aa: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 + 80044ae: 68fb ldr r3, [r7, #12] + 80044b0: 619a str r2, [r3, #24] + 80044b2: 68fb ldr r3, [r7, #12] + 80044b4: 6d5b ldr r3, [r3, #84] @ 0x54 + 80044b6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 80044ba: f043 0303 orr.w r3, r3, #3 + 80044be: 68fa ldr r2, [r7, #12] + 80044c0: 6553 str r3, [r2, #84] @ 0x54 + 80044c2: 2300 movs r3, #0 + 80044c4: 4618 mov r0, r3 + 80044c6: 3714 adds r7, #20 + 80044c8: 46bd mov sp, r7 + 80044ca: f85d 7b04 ldr.w r7, [sp], #4 + 80044ce: 4770 bx lr + +080044d0 : + 80044d0: b580 push {r7, lr} + 80044d2: b084 sub sp, #16 + 80044d4: af00 add r7, sp, #0 + 80044d6: 6078 str r0, [r7, #4] + 80044d8: 6039 str r1, [r7, #0] + 80044da: 687b ldr r3, [r7, #4] + 80044dc: 2b00 cmp r3, #0 + 80044de: d101 bne.n 80044e4 + 80044e0: 2301 movs r3, #1 + 80044e2: e0cc b.n 800467e + 80044e4: 4b68 ldr r3, [pc, #416] @ (8004688 ) + 80044e6: 681b ldr r3, [r3, #0] + 80044e8: f003 030f and.w r3, r3, #15 + 80044ec: 683a ldr r2, [r7, #0] + 80044ee: 429a cmp r2, r3 + 80044f0: d90c bls.n 800450c + 80044f2: 4b65 ldr r3, [pc, #404] @ (8004688 ) + 80044f4: 683a ldr r2, [r7, #0] + 80044f6: b2d2 uxtb r2, r2 + 80044f8: 701a strb r2, [r3, #0] + 80044fa: 4b63 ldr r3, [pc, #396] @ (8004688 ) + 80044fc: 681b ldr r3, [r3, #0] + 80044fe: f003 030f and.w r3, r3, #15 + 8004502: 683a ldr r2, [r7, #0] + 8004504: 429a cmp r2, r3 + 8004506: d001 beq.n 800450c + 8004508: 2301 movs r3, #1 + 800450a: e0b8 b.n 800467e + 800450c: 687b ldr r3, [r7, #4] + 800450e: 681b ldr r3, [r3, #0] + 8004510: f003 0302 and.w r3, r3, #2 + 8004514: 2b00 cmp r3, #0 + 8004516: d020 beq.n 800455a + 8004518: 687b ldr r3, [r7, #4] + 800451a: 681b ldr r3, [r3, #0] + 800451c: f003 0304 and.w r3, r3, #4 + 8004520: 2b00 cmp r3, #0 + 8004522: d005 beq.n 8004530 + 8004524: 4b59 ldr r3, [pc, #356] @ (800468c ) + 8004526: 689b ldr r3, [r3, #8] + 8004528: 4a58 ldr r2, [pc, #352] @ (800468c ) + 800452a: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 + 800452e: 6093 str r3, [r2, #8] + 8004530: 687b ldr r3, [r7, #4] + 8004532: 681b ldr r3, [r3, #0] + 8004534: f003 0308 and.w r3, r3, #8 + 8004538: 2b00 cmp r3, #0 + 800453a: d005 beq.n 8004548 + 800453c: 4b53 ldr r3, [pc, #332] @ (800468c ) + 800453e: 689b ldr r3, [r3, #8] + 8004540: 4a52 ldr r2, [pc, #328] @ (800468c ) + 8004542: f443 4360 orr.w r3, r3, #57344 @ 0xe000 + 8004546: 6093 str r3, [r2, #8] + 8004548: 4b50 ldr r3, [pc, #320] @ (800468c ) + 800454a: 689b ldr r3, [r3, #8] + 800454c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8004550: 687b ldr r3, [r7, #4] + 8004552: 689b ldr r3, [r3, #8] + 8004554: 494d ldr r1, [pc, #308] @ (800468c ) + 8004556: 4313 orrs r3, r2 + 8004558: 608b str r3, [r1, #8] + 800455a: 687b ldr r3, [r7, #4] + 800455c: 681b ldr r3, [r3, #0] + 800455e: f003 0301 and.w r3, r3, #1 + 8004562: 2b00 cmp r3, #0 + 8004564: d044 beq.n 80045f0 + 8004566: 687b ldr r3, [r7, #4] + 8004568: 685b ldr r3, [r3, #4] + 800456a: 2b01 cmp r3, #1 + 800456c: d107 bne.n 800457e + 800456e: 4b47 ldr r3, [pc, #284] @ (800468c ) + 8004570: 681b ldr r3, [r3, #0] + 8004572: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8004576: 2b00 cmp r3, #0 + 8004578: d119 bne.n 80045ae + 800457a: 2301 movs r3, #1 + 800457c: e07f b.n 800467e + 800457e: 687b ldr r3, [r7, #4] + 8004580: 685b ldr r3, [r3, #4] + 8004582: 2b02 cmp r3, #2 + 8004584: d003 beq.n 800458e + 8004586: 687b ldr r3, [r7, #4] + 8004588: 685b ldr r3, [r3, #4] + 800458a: 2b03 cmp r3, #3 + 800458c: d107 bne.n 800459e + 800458e: 4b3f ldr r3, [pc, #252] @ (800468c ) + 8004590: 681b ldr r3, [r3, #0] + 8004592: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8004596: 2b00 cmp r3, #0 + 8004598: d109 bne.n 80045ae + 800459a: 2301 movs r3, #1 + 800459c: e06f b.n 800467e + 800459e: 4b3b ldr r3, [pc, #236] @ (800468c ) + 80045a0: 681b ldr r3, [r3, #0] + 80045a2: f003 0302 and.w r3, r3, #2 + 80045a6: 2b00 cmp r3, #0 + 80045a8: d101 bne.n 80045ae + 80045aa: 2301 movs r3, #1 + 80045ac: e067 b.n 800467e + 80045ae: 4b37 ldr r3, [pc, #220] @ (800468c ) + 80045b0: 689b ldr r3, [r3, #8] + 80045b2: f023 0203 bic.w r2, r3, #3 + 80045b6: 687b ldr r3, [r7, #4] + 80045b8: 685b ldr r3, [r3, #4] + 80045ba: 4934 ldr r1, [pc, #208] @ (800468c ) + 80045bc: 4313 orrs r3, r2 + 80045be: 608b str r3, [r1, #8] + 80045c0: f7fd fcb2 bl 8001f28 + 80045c4: 60f8 str r0, [r7, #12] + 80045c6: e00a b.n 80045de + 80045c8: f7fd fcae bl 8001f28 + 80045cc: 4602 mov r2, r0 + 80045ce: 68fb ldr r3, [r7, #12] + 80045d0: 1ad3 subs r3, r2, r3 + 80045d2: f241 3288 movw r2, #5000 @ 0x1388 + 80045d6: 4293 cmp r3, r2 + 80045d8: d901 bls.n 80045de + 80045da: 2303 movs r3, #3 + 80045dc: e04f b.n 800467e + 80045de: 4b2b ldr r3, [pc, #172] @ (800468c ) + 80045e0: 689b ldr r3, [r3, #8] + 80045e2: f003 020c and.w r2, r3, #12 + 80045e6: 687b ldr r3, [r7, #4] + 80045e8: 685b ldr r3, [r3, #4] + 80045ea: 009b lsls r3, r3, #2 + 80045ec: 429a cmp r2, r3 + 80045ee: d1eb bne.n 80045c8 + 80045f0: 4b25 ldr r3, [pc, #148] @ (8004688 ) + 80045f2: 681b ldr r3, [r3, #0] + 80045f4: f003 030f and.w r3, r3, #15 + 80045f8: 683a ldr r2, [r7, #0] + 80045fa: 429a cmp r2, r3 + 80045fc: d20c bcs.n 8004618 + 80045fe: 4b22 ldr r3, [pc, #136] @ (8004688 ) + 8004600: 683a ldr r2, [r7, #0] + 8004602: b2d2 uxtb r2, r2 + 8004604: 701a strb r2, [r3, #0] + 8004606: 4b20 ldr r3, [pc, #128] @ (8004688 ) + 8004608: 681b ldr r3, [r3, #0] + 800460a: f003 030f and.w r3, r3, #15 + 800460e: 683a ldr r2, [r7, #0] + 8004610: 429a cmp r2, r3 + 8004612: d001 beq.n 8004618 + 8004614: 2301 movs r3, #1 + 8004616: e032 b.n 800467e + 8004618: 687b ldr r3, [r7, #4] + 800461a: 681b ldr r3, [r3, #0] + 800461c: f003 0304 and.w r3, r3, #4 + 8004620: 2b00 cmp r3, #0 + 8004622: d008 beq.n 8004636 + 8004624: 4b19 ldr r3, [pc, #100] @ (800468c ) + 8004626: 689b ldr r3, [r3, #8] + 8004628: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 + 800462c: 687b ldr r3, [r7, #4] + 800462e: 68db ldr r3, [r3, #12] + 8004630: 4916 ldr r1, [pc, #88] @ (800468c ) + 8004632: 4313 orrs r3, r2 + 8004634: 608b str r3, [r1, #8] + 8004636: 687b ldr r3, [r7, #4] + 8004638: 681b ldr r3, [r3, #0] + 800463a: f003 0308 and.w r3, r3, #8 + 800463e: 2b00 cmp r3, #0 + 8004640: d009 beq.n 8004656 + 8004642: 4b12 ldr r3, [pc, #72] @ (800468c ) + 8004644: 689b ldr r3, [r3, #8] + 8004646: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 800464a: 687b ldr r3, [r7, #4] + 800464c: 691b ldr r3, [r3, #16] + 800464e: 00db lsls r3, r3, #3 + 8004650: 490e ldr r1, [pc, #56] @ (800468c ) + 8004652: 4313 orrs r3, r2 + 8004654: 608b str r3, [r1, #8] + 8004656: f000 fb7f bl 8004d58 + 800465a: 4602 mov r2, r0 + 800465c: 4b0b ldr r3, [pc, #44] @ (800468c ) + 800465e: 689b ldr r3, [r3, #8] + 8004660: 091b lsrs r3, r3, #4 + 8004662: f003 030f and.w r3, r3, #15 + 8004666: 490a ldr r1, [pc, #40] @ (8004690 ) + 8004668: 5ccb ldrb r3, [r1, r3] + 800466a: fa22 f303 lsr.w r3, r2, r3 + 800466e: 4a09 ldr r2, [pc, #36] @ (8004694 ) + 8004670: 6013 str r3, [r2, #0] + 8004672: 4b09 ldr r3, [pc, #36] @ (8004698 ) + 8004674: 681b ldr r3, [r3, #0] + 8004676: 4618 mov r0, r3 + 8004678: f7fd fc12 bl 8001ea0 + 800467c: 2300 movs r3, #0 + 800467e: 4618 mov r0, r3 + 8004680: 3710 adds r7, #16 + 8004682: 46bd mov sp, r7 + 8004684: bd80 pop {r7, pc} + 8004686: bf00 nop + 8004688: 40023c00 .word 0x40023c00 + 800468c: 40023800 .word 0x40023800 + 8004690: 0800b418 .word 0x0800b418 + 8004694: 20000090 .word 0x20000090 + 8004698: 20000094 .word 0x20000094 + +0800469c : + 800469c: b480 push {r7} + 800469e: af00 add r7, sp, #0 + 80046a0: 4b03 ldr r3, [pc, #12] @ (80046b0 ) + 80046a2: 681b ldr r3, [r3, #0] + 80046a4: 4618 mov r0, r3 + 80046a6: 46bd mov sp, r7 + 80046a8: f85d 7b04 ldr.w r7, [sp], #4 + 80046ac: 4770 bx lr + 80046ae: bf00 nop + 80046b0: 20000090 .word 0x20000090 + +080046b4 : + 80046b4: b580 push {r7, lr} + 80046b6: af00 add r7, sp, #0 + 80046b8: f7ff fff0 bl 800469c + 80046bc: 4602 mov r2, r0 + 80046be: 4b05 ldr r3, [pc, #20] @ (80046d4 ) + 80046c0: 689b ldr r3, [r3, #8] + 80046c2: 0a9b lsrs r3, r3, #10 + 80046c4: f003 0307 and.w r3, r3, #7 + 80046c8: 4903 ldr r1, [pc, #12] @ (80046d8 ) + 80046ca: 5ccb ldrb r3, [r1, r3] + 80046cc: fa22 f303 lsr.w r3, r2, r3 + 80046d0: 4618 mov r0, r3 + 80046d2: bd80 pop {r7, pc} + 80046d4: 40023800 .word 0x40023800 + 80046d8: 0800b428 .word 0x0800b428 + +080046dc : + 80046dc: b580 push {r7, lr} + 80046de: af00 add r7, sp, #0 + 80046e0: f7ff ffdc bl 800469c + 80046e4: 4602 mov r2, r0 + 80046e6: 4b05 ldr r3, [pc, #20] @ (80046fc ) + 80046e8: 689b ldr r3, [r3, #8] + 80046ea: 0b5b lsrs r3, r3, #13 + 80046ec: f003 0307 and.w r3, r3, #7 + 80046f0: 4903 ldr r1, [pc, #12] @ (8004700 ) + 80046f2: 5ccb ldrb r3, [r1, r3] + 80046f4: fa22 f303 lsr.w r3, r2, r3 + 80046f8: 4618 mov r0, r3 + 80046fa: bd80 pop {r7, pc} + 80046fc: 40023800 .word 0x40023800 + 8004700: 0800b428 .word 0x0800b428 + +08004704 : + 8004704: b580 push {r7, lr} + 8004706: b08c sub sp, #48 @ 0x30 + 8004708: af00 add r7, sp, #0 + 800470a: 6078 str r0, [r7, #4] + 800470c: 2300 movs r3, #0 + 800470e: 627b str r3, [r7, #36] @ 0x24 + 8004710: 2300 movs r3, #0 + 8004712: 623b str r3, [r7, #32] + 8004714: 2300 movs r3, #0 + 8004716: 61fb str r3, [r7, #28] + 8004718: 2300 movs r3, #0 + 800471a: 61bb str r3, [r7, #24] + 800471c: 2300 movs r3, #0 + 800471e: 617b str r3, [r7, #20] + 8004720: 2300 movs r3, #0 + 8004722: 613b str r3, [r7, #16] + 8004724: 2300 movs r3, #0 + 8004726: 60fb str r3, [r7, #12] + 8004728: 2300 movs r3, #0 + 800472a: 62fb str r3, [r7, #44] @ 0x2c + 800472c: 2300 movs r3, #0 + 800472e: 62bb str r3, [r7, #40] @ 0x28 + 8004730: 687b ldr r3, [r7, #4] + 8004732: 681b ldr r3, [r3, #0] + 8004734: f003 0301 and.w r3, r3, #1 + 8004738: 2b00 cmp r3, #0 + 800473a: d010 beq.n 800475e + 800473c: 4b6f ldr r3, [pc, #444] @ (80048fc ) + 800473e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8004742: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000 + 8004746: 687b ldr r3, [r7, #4] + 8004748: 6b9b ldr r3, [r3, #56] @ 0x38 + 800474a: 496c ldr r1, [pc, #432] @ (80048fc ) + 800474c: 4313 orrs r3, r2 + 800474e: f8c1 308c str.w r3, [r1, #140] @ 0x8c + 8004752: 687b ldr r3, [r7, #4] + 8004754: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004756: 2b00 cmp r3, #0 + 8004758: d101 bne.n 800475e + 800475a: 2301 movs r3, #1 + 800475c: 62fb str r3, [r7, #44] @ 0x2c + 800475e: 687b ldr r3, [r7, #4] + 8004760: 681b ldr r3, [r3, #0] + 8004762: f003 0302 and.w r3, r3, #2 + 8004766: 2b00 cmp r3, #0 + 8004768: d010 beq.n 800478c + 800476a: 4b64 ldr r3, [pc, #400] @ (80048fc ) + 800476c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8004770: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000 + 8004774: 687b ldr r3, [r7, #4] + 8004776: 6bdb ldr r3, [r3, #60] @ 0x3c + 8004778: 4960 ldr r1, [pc, #384] @ (80048fc ) + 800477a: 4313 orrs r3, r2 + 800477c: f8c1 308c str.w r3, [r1, #140] @ 0x8c + 8004780: 687b ldr r3, [r7, #4] + 8004782: 6bdb ldr r3, [r3, #60] @ 0x3c + 8004784: 2b00 cmp r3, #0 + 8004786: d101 bne.n 800478c + 8004788: 2301 movs r3, #1 + 800478a: 62fb str r3, [r7, #44] @ 0x2c + 800478c: 687b ldr r3, [r7, #4] + 800478e: 681b ldr r3, [r3, #0] + 8004790: f003 0304 and.w r3, r3, #4 + 8004794: 2b00 cmp r3, #0 + 8004796: d017 beq.n 80047c8 + 8004798: 4b58 ldr r3, [pc, #352] @ (80048fc ) + 800479a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 800479e: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 + 80047a2: 687b ldr r3, [r7, #4] + 80047a4: 6b1b ldr r3, [r3, #48] @ 0x30 + 80047a6: 4955 ldr r1, [pc, #340] @ (80048fc ) + 80047a8: 4313 orrs r3, r2 + 80047aa: f8c1 308c str.w r3, [r1, #140] @ 0x8c + 80047ae: 687b ldr r3, [r7, #4] + 80047b0: 6b1b ldr r3, [r3, #48] @ 0x30 + 80047b2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 80047b6: d101 bne.n 80047bc + 80047b8: 2301 movs r3, #1 + 80047ba: 62fb str r3, [r7, #44] @ 0x2c + 80047bc: 687b ldr r3, [r7, #4] + 80047be: 6b1b ldr r3, [r3, #48] @ 0x30 + 80047c0: 2b00 cmp r3, #0 + 80047c2: d101 bne.n 80047c8 + 80047c4: 2301 movs r3, #1 + 80047c6: 62bb str r3, [r7, #40] @ 0x28 + 80047c8: 687b ldr r3, [r7, #4] + 80047ca: 681b ldr r3, [r3, #0] + 80047cc: f003 0308 and.w r3, r3, #8 + 80047d0: 2b00 cmp r3, #0 + 80047d2: d017 beq.n 8004804 + 80047d4: 4b49 ldr r3, [pc, #292] @ (80048fc ) + 80047d6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 80047da: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 + 80047de: 687b ldr r3, [r7, #4] + 80047e0: 6b5b ldr r3, [r3, #52] @ 0x34 + 80047e2: 4946 ldr r1, [pc, #280] @ (80048fc ) + 80047e4: 4313 orrs r3, r2 + 80047e6: f8c1 308c str.w r3, [r1, #140] @ 0x8c + 80047ea: 687b ldr r3, [r7, #4] + 80047ec: 6b5b ldr r3, [r3, #52] @ 0x34 + 80047ee: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 80047f2: d101 bne.n 80047f8 + 80047f4: 2301 movs r3, #1 + 80047f6: 62fb str r3, [r7, #44] @ 0x2c + 80047f8: 687b ldr r3, [r7, #4] + 80047fa: 6b5b ldr r3, [r3, #52] @ 0x34 + 80047fc: 2b00 cmp r3, #0 + 80047fe: d101 bne.n 8004804 + 8004800: 2301 movs r3, #1 + 8004802: 62bb str r3, [r7, #40] @ 0x28 + 8004804: 687b ldr r3, [r7, #4] + 8004806: 681b ldr r3, [r3, #0] + 8004808: f003 0320 and.w r3, r3, #32 + 800480c: 2b00 cmp r3, #0 + 800480e: f000 808a beq.w 8004926 + 8004812: 2300 movs r3, #0 + 8004814: 60bb str r3, [r7, #8] + 8004816: 4b39 ldr r3, [pc, #228] @ (80048fc ) + 8004818: 6c1b ldr r3, [r3, #64] @ 0x40 + 800481a: 4a38 ldr r2, [pc, #224] @ (80048fc ) + 800481c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8004820: 6413 str r3, [r2, #64] @ 0x40 + 8004822: 4b36 ldr r3, [pc, #216] @ (80048fc ) + 8004824: 6c1b ldr r3, [r3, #64] @ 0x40 + 8004826: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800482a: 60bb str r3, [r7, #8] + 800482c: 68bb ldr r3, [r7, #8] + 800482e: 4b34 ldr r3, [pc, #208] @ (8004900 ) + 8004830: 681b ldr r3, [r3, #0] + 8004832: 4a33 ldr r2, [pc, #204] @ (8004900 ) + 8004834: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8004838: 6013 str r3, [r2, #0] + 800483a: f7fd fb75 bl 8001f28 + 800483e: 6278 str r0, [r7, #36] @ 0x24 + 8004840: e008 b.n 8004854 + 8004842: f7fd fb71 bl 8001f28 + 8004846: 4602 mov r2, r0 + 8004848: 6a7b ldr r3, [r7, #36] @ 0x24 + 800484a: 1ad3 subs r3, r2, r3 + 800484c: 2b02 cmp r3, #2 + 800484e: d901 bls.n 8004854 + 8004850: 2303 movs r3, #3 + 8004852: e278 b.n 8004d46 + 8004854: 4b2a ldr r3, [pc, #168] @ (8004900 ) + 8004856: 681b ldr r3, [r3, #0] + 8004858: f403 7380 and.w r3, r3, #256 @ 0x100 + 800485c: 2b00 cmp r3, #0 + 800485e: d0f0 beq.n 8004842 + 8004860: 4b26 ldr r3, [pc, #152] @ (80048fc ) + 8004862: 6f1b ldr r3, [r3, #112] @ 0x70 + 8004864: f403 7340 and.w r3, r3, #768 @ 0x300 + 8004868: 623b str r3, [r7, #32] + 800486a: 6a3b ldr r3, [r7, #32] + 800486c: 2b00 cmp r3, #0 + 800486e: d02f beq.n 80048d0 + 8004870: 687b ldr r3, [r7, #4] + 8004872: 6c1b ldr r3, [r3, #64] @ 0x40 + 8004874: f403 7340 and.w r3, r3, #768 @ 0x300 + 8004878: 6a3a ldr r2, [r7, #32] + 800487a: 429a cmp r2, r3 + 800487c: d028 beq.n 80048d0 + 800487e: 4b1f ldr r3, [pc, #124] @ (80048fc ) + 8004880: 6f1b ldr r3, [r3, #112] @ 0x70 + 8004882: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8004886: 623b str r3, [r7, #32] + 8004888: 4b1e ldr r3, [pc, #120] @ (8004904 ) + 800488a: 2201 movs r2, #1 + 800488c: 601a str r2, [r3, #0] + 800488e: 4b1d ldr r3, [pc, #116] @ (8004904 ) + 8004890: 2200 movs r2, #0 + 8004892: 601a str r2, [r3, #0] + 8004894: 4a19 ldr r2, [pc, #100] @ (80048fc ) + 8004896: 6a3b ldr r3, [r7, #32] + 8004898: 6713 str r3, [r2, #112] @ 0x70 + 800489a: 4b18 ldr r3, [pc, #96] @ (80048fc ) + 800489c: 6f1b ldr r3, [r3, #112] @ 0x70 + 800489e: f003 0301 and.w r3, r3, #1 + 80048a2: 2b01 cmp r3, #1 + 80048a4: d114 bne.n 80048d0 + 80048a6: f7fd fb3f bl 8001f28 + 80048aa: 6278 str r0, [r7, #36] @ 0x24 + 80048ac: e00a b.n 80048c4 + 80048ae: f7fd fb3b bl 8001f28 + 80048b2: 4602 mov r2, r0 + 80048b4: 6a7b ldr r3, [r7, #36] @ 0x24 + 80048b6: 1ad3 subs r3, r2, r3 + 80048b8: f241 3288 movw r2, #5000 @ 0x1388 + 80048bc: 4293 cmp r3, r2 + 80048be: d901 bls.n 80048c4 + 80048c0: 2303 movs r3, #3 + 80048c2: e240 b.n 8004d46 + 80048c4: 4b0d ldr r3, [pc, #52] @ (80048fc ) + 80048c6: 6f1b ldr r3, [r3, #112] @ 0x70 + 80048c8: f003 0302 and.w r3, r3, #2 + 80048cc: 2b00 cmp r3, #0 + 80048ce: d0ee beq.n 80048ae + 80048d0: 687b ldr r3, [r7, #4] + 80048d2: 6c1b ldr r3, [r3, #64] @ 0x40 + 80048d4: f403 7340 and.w r3, r3, #768 @ 0x300 + 80048d8: f5b3 7f40 cmp.w r3, #768 @ 0x300 + 80048dc: d114 bne.n 8004908 + 80048de: 4b07 ldr r3, [pc, #28] @ (80048fc ) + 80048e0: 689b ldr r3, [r3, #8] + 80048e2: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 + 80048e6: 687b ldr r3, [r7, #4] + 80048e8: 6c1b ldr r3, [r3, #64] @ 0x40 + 80048ea: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 + 80048ee: f423 7340 bic.w r3, r3, #768 @ 0x300 + 80048f2: 4902 ldr r1, [pc, #8] @ (80048fc ) + 80048f4: 4313 orrs r3, r2 + 80048f6: 608b str r3, [r1, #8] + 80048f8: e00c b.n 8004914 + 80048fa: bf00 nop + 80048fc: 40023800 .word 0x40023800 + 8004900: 40007000 .word 0x40007000 + 8004904: 42470e40 .word 0x42470e40 + 8004908: 4b4a ldr r3, [pc, #296] @ (8004a34 ) + 800490a: 689b ldr r3, [r3, #8] + 800490c: 4a49 ldr r2, [pc, #292] @ (8004a34 ) + 800490e: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 + 8004912: 6093 str r3, [r2, #8] + 8004914: 4b47 ldr r3, [pc, #284] @ (8004a34 ) + 8004916: 6f1a ldr r2, [r3, #112] @ 0x70 + 8004918: 687b ldr r3, [r7, #4] + 800491a: 6c1b ldr r3, [r3, #64] @ 0x40 + 800491c: f3c3 030b ubfx r3, r3, #0, #12 + 8004920: 4944 ldr r1, [pc, #272] @ (8004a34 ) + 8004922: 4313 orrs r3, r2 + 8004924: 670b str r3, [r1, #112] @ 0x70 + 8004926: 687b ldr r3, [r7, #4] + 8004928: 681b ldr r3, [r3, #0] + 800492a: f003 0310 and.w r3, r3, #16 + 800492e: 2b00 cmp r3, #0 + 8004930: d004 beq.n 800493c + 8004932: 687b ldr r3, [r7, #4] + 8004934: f893 2058 ldrb.w r2, [r3, #88] @ 0x58 + 8004938: 4b3f ldr r3, [pc, #252] @ (8004a38 ) + 800493a: 601a str r2, [r3, #0] + 800493c: 687b ldr r3, [r7, #4] + 800493e: 681b ldr r3, [r3, #0] + 8004940: f003 0380 and.w r3, r3, #128 @ 0x80 + 8004944: 2b00 cmp r3, #0 + 8004946: d00a beq.n 800495e + 8004948: 4b3a ldr r3, [pc, #232] @ (8004a34 ) + 800494a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 800494e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 + 8004952: 687b ldr r3, [r7, #4] + 8004954: 6cdb ldr r3, [r3, #76] @ 0x4c + 8004956: 4937 ldr r1, [pc, #220] @ (8004a34 ) + 8004958: 4313 orrs r3, r2 + 800495a: f8c1 3094 str.w r3, [r1, #148] @ 0x94 + 800495e: 687b ldr r3, [r7, #4] + 8004960: 681b ldr r3, [r3, #0] + 8004962: f003 0340 and.w r3, r3, #64 @ 0x40 + 8004966: 2b00 cmp r3, #0 + 8004968: d00a beq.n 8004980 + 800496a: 4b32 ldr r3, [pc, #200] @ (8004a34 ) + 800496c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8004970: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000 + 8004974: 687b ldr r3, [r7, #4] + 8004976: 6c9b ldr r3, [r3, #72] @ 0x48 + 8004978: 492e ldr r1, [pc, #184] @ (8004a34 ) + 800497a: 4313 orrs r3, r2 + 800497c: f8c1 3094 str.w r3, [r1, #148] @ 0x94 + 8004980: 687b ldr r3, [r7, #4] + 8004982: 681b ldr r3, [r3, #0] + 8004984: f403 7380 and.w r3, r3, #256 @ 0x100 + 8004988: 2b00 cmp r3, #0 + 800498a: d011 beq.n 80049b0 + 800498c: 4b29 ldr r3, [pc, #164] @ (8004a34 ) + 800498e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8004992: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000 + 8004996: 687b ldr r3, [r7, #4] + 8004998: 6d5b ldr r3, [r3, #84] @ 0x54 + 800499a: 4926 ldr r1, [pc, #152] @ (8004a34 ) + 800499c: 4313 orrs r3, r2 + 800499e: f8c1 3094 str.w r3, [r1, #148] @ 0x94 + 80049a2: 687b ldr r3, [r7, #4] + 80049a4: 6d5b ldr r3, [r3, #84] @ 0x54 + 80049a6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 + 80049aa: d101 bne.n 80049b0 + 80049ac: 2301 movs r3, #1 + 80049ae: 62bb str r3, [r7, #40] @ 0x28 + 80049b0: 687b ldr r3, [r7, #4] + 80049b2: 681b ldr r3, [r3, #0] + 80049b4: f403 7300 and.w r3, r3, #512 @ 0x200 + 80049b8: 2b00 cmp r3, #0 + 80049ba: d00a beq.n 80049d2 + 80049bc: 4b1d ldr r3, [pc, #116] @ (8004a34 ) + 80049be: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80049c2: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000 + 80049c6: 687b ldr r3, [r7, #4] + 80049c8: 6c5b ldr r3, [r3, #68] @ 0x44 + 80049ca: 491a ldr r1, [pc, #104] @ (8004a34 ) + 80049cc: 4313 orrs r3, r2 + 80049ce: f8c1 3094 str.w r3, [r1, #148] @ 0x94 + 80049d2: 687b ldr r3, [r7, #4] + 80049d4: 681b ldr r3, [r3, #0] + 80049d6: f403 6380 and.w r3, r3, #1024 @ 0x400 + 80049da: 2b00 cmp r3, #0 + 80049dc: d011 beq.n 8004a02 + 80049de: 4b15 ldr r3, [pc, #84] @ (8004a34 ) + 80049e0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 80049e4: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000 + 80049e8: 687b ldr r3, [r7, #4] + 80049ea: 6d1b ldr r3, [r3, #80] @ 0x50 + 80049ec: 4911 ldr r1, [pc, #68] @ (8004a34 ) + 80049ee: 4313 orrs r3, r2 + 80049f0: f8c1 3094 str.w r3, [r1, #148] @ 0x94 + 80049f4: 687b ldr r3, [r7, #4] + 80049f6: 6d1b ldr r3, [r3, #80] @ 0x50 + 80049f8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 80049fc: d101 bne.n 8004a02 + 80049fe: 2301 movs r3, #1 + 8004a00: 62fb str r3, [r7, #44] @ 0x2c + 8004a02: 6afb ldr r3, [r7, #44] @ 0x2c + 8004a04: 2b01 cmp r3, #1 + 8004a06: d005 beq.n 8004a14 + 8004a08: 687b ldr r3, [r7, #4] + 8004a0a: 681b ldr r3, [r3, #0] + 8004a0c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8004a10: f040 80ff bne.w 8004c12 + 8004a14: 4b09 ldr r3, [pc, #36] @ (8004a3c ) + 8004a16: 2200 movs r2, #0 + 8004a18: 601a str r2, [r3, #0] + 8004a1a: f7fd fa85 bl 8001f28 + 8004a1e: 6278 str r0, [r7, #36] @ 0x24 + 8004a20: e00e b.n 8004a40 + 8004a22: f7fd fa81 bl 8001f28 + 8004a26: 4602 mov r2, r0 + 8004a28: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004a2a: 1ad3 subs r3, r2, r3 + 8004a2c: 2b02 cmp r3, #2 + 8004a2e: d907 bls.n 8004a40 + 8004a30: 2303 movs r3, #3 + 8004a32: e188 b.n 8004d46 + 8004a34: 40023800 .word 0x40023800 + 8004a38: 424711e0 .word 0x424711e0 + 8004a3c: 42470068 .word 0x42470068 + 8004a40: 4b7e ldr r3, [pc, #504] @ (8004c3c ) + 8004a42: 681b ldr r3, [r3, #0] + 8004a44: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 8004a48: 2b00 cmp r3, #0 + 8004a4a: d1ea bne.n 8004a22 + 8004a4c: 687b ldr r3, [r7, #4] + 8004a4e: 681b ldr r3, [r3, #0] + 8004a50: f003 0301 and.w r3, r3, #1 + 8004a54: 2b00 cmp r3, #0 + 8004a56: d003 beq.n 8004a60 + 8004a58: 687b ldr r3, [r7, #4] + 8004a5a: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004a5c: 2b00 cmp r3, #0 + 8004a5e: d009 beq.n 8004a74 + 8004a60: 687b ldr r3, [r7, #4] + 8004a62: 681b ldr r3, [r3, #0] + 8004a64: f003 0302 and.w r3, r3, #2 + 8004a68: 2b00 cmp r3, #0 + 8004a6a: d028 beq.n 8004abe + 8004a6c: 687b ldr r3, [r7, #4] + 8004a6e: 6bdb ldr r3, [r3, #60] @ 0x3c + 8004a70: 2b00 cmp r3, #0 + 8004a72: d124 bne.n 8004abe + 8004a74: 4b71 ldr r3, [pc, #452] @ (8004c3c ) + 8004a76: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 + 8004a7a: 0c1b lsrs r3, r3, #16 + 8004a7c: f003 0303 and.w r3, r3, #3 + 8004a80: 3301 adds r3, #1 + 8004a82: 005b lsls r3, r3, #1 + 8004a84: 61fb str r3, [r7, #28] + 8004a86: 4b6d ldr r3, [pc, #436] @ (8004c3c ) + 8004a88: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 + 8004a8c: 0e1b lsrs r3, r3, #24 + 8004a8e: f003 030f and.w r3, r3, #15 + 8004a92: 61bb str r3, [r7, #24] + 8004a94: 687b ldr r3, [r7, #4] + 8004a96: 685a ldr r2, [r3, #4] + 8004a98: 687b ldr r3, [r7, #4] + 8004a9a: 689b ldr r3, [r3, #8] + 8004a9c: 019b lsls r3, r3, #6 + 8004a9e: 431a orrs r2, r3 + 8004aa0: 69fb ldr r3, [r7, #28] + 8004aa2: 085b lsrs r3, r3, #1 + 8004aa4: 3b01 subs r3, #1 + 8004aa6: 041b lsls r3, r3, #16 + 8004aa8: 431a orrs r2, r3 + 8004aaa: 69bb ldr r3, [r7, #24] + 8004aac: 061b lsls r3, r3, #24 + 8004aae: 431a orrs r2, r3 + 8004ab0: 687b ldr r3, [r7, #4] + 8004ab2: 695b ldr r3, [r3, #20] + 8004ab4: 071b lsls r3, r3, #28 + 8004ab6: 4961 ldr r1, [pc, #388] @ (8004c3c ) + 8004ab8: 4313 orrs r3, r2 + 8004aba: f8c1 3084 str.w r3, [r1, #132] @ 0x84 + 8004abe: 687b ldr r3, [r7, #4] + 8004ac0: 681b ldr r3, [r3, #0] + 8004ac2: f003 0304 and.w r3, r3, #4 + 8004ac6: 2b00 cmp r3, #0 + 8004ac8: d004 beq.n 8004ad4 + 8004aca: 687b ldr r3, [r7, #4] + 8004acc: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004ace: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 8004ad2: d00a beq.n 8004aea + 8004ad4: 687b ldr r3, [r7, #4] + 8004ad6: 681b ldr r3, [r3, #0] + 8004ad8: f003 0308 and.w r3, r3, #8 + 8004adc: 2b00 cmp r3, #0 + 8004ade: d035 beq.n 8004b4c + 8004ae0: 687b ldr r3, [r7, #4] + 8004ae2: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004ae4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8004ae8: d130 bne.n 8004b4c + 8004aea: 4b54 ldr r3, [pc, #336] @ (8004c3c ) + 8004aec: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 + 8004af0: 0c1b lsrs r3, r3, #16 + 8004af2: f003 0303 and.w r3, r3, #3 + 8004af6: 3301 adds r3, #1 + 8004af8: 005b lsls r3, r3, #1 + 8004afa: 61fb str r3, [r7, #28] + 8004afc: 4b4f ldr r3, [pc, #316] @ (8004c3c ) + 8004afe: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 + 8004b02: 0f1b lsrs r3, r3, #28 + 8004b04: f003 0307 and.w r3, r3, #7 + 8004b08: 617b str r3, [r7, #20] + 8004b0a: 687b ldr r3, [r7, #4] + 8004b0c: 685a ldr r2, [r3, #4] + 8004b0e: 687b ldr r3, [r7, #4] + 8004b10: 689b ldr r3, [r3, #8] + 8004b12: 019b lsls r3, r3, #6 + 8004b14: 431a orrs r2, r3 + 8004b16: 69fb ldr r3, [r7, #28] + 8004b18: 085b lsrs r3, r3, #1 + 8004b1a: 3b01 subs r3, #1 + 8004b1c: 041b lsls r3, r3, #16 + 8004b1e: 431a orrs r2, r3 + 8004b20: 687b ldr r3, [r7, #4] + 8004b22: 691b ldr r3, [r3, #16] + 8004b24: 061b lsls r3, r3, #24 + 8004b26: 431a orrs r2, r3 + 8004b28: 697b ldr r3, [r7, #20] + 8004b2a: 071b lsls r3, r3, #28 + 8004b2c: 4943 ldr r1, [pc, #268] @ (8004c3c ) + 8004b2e: 4313 orrs r3, r2 + 8004b30: f8c1 3084 str.w r3, [r1, #132] @ 0x84 + 8004b34: 4b41 ldr r3, [pc, #260] @ (8004c3c ) + 8004b36: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8004b3a: f023 021f bic.w r2, r3, #31 + 8004b3e: 687b ldr r3, [r7, #4] + 8004b40: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004b42: 3b01 subs r3, #1 + 8004b44: 493d ldr r1, [pc, #244] @ (8004c3c ) + 8004b46: 4313 orrs r3, r2 + 8004b48: f8c1 308c str.w r3, [r1, #140] @ 0x8c + 8004b4c: 687b ldr r3, [r7, #4] + 8004b4e: 681b ldr r3, [r3, #0] + 8004b50: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8004b54: 2b00 cmp r3, #0 + 8004b56: d029 beq.n 8004bac + 8004b58: 687b ldr r3, [r7, #4] + 8004b5a: 6d1b ldr r3, [r3, #80] @ 0x50 + 8004b5c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 8004b60: d124 bne.n 8004bac + 8004b62: 4b36 ldr r3, [pc, #216] @ (8004c3c ) + 8004b64: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 + 8004b68: 0c1b lsrs r3, r3, #16 + 8004b6a: f003 0303 and.w r3, r3, #3 + 8004b6e: 3301 adds r3, #1 + 8004b70: 005b lsls r3, r3, #1 + 8004b72: 61bb str r3, [r7, #24] + 8004b74: 4b31 ldr r3, [pc, #196] @ (8004c3c ) + 8004b76: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 + 8004b7a: 0f1b lsrs r3, r3, #28 + 8004b7c: f003 0307 and.w r3, r3, #7 + 8004b80: 617b str r3, [r7, #20] + 8004b82: 687b ldr r3, [r7, #4] + 8004b84: 685a ldr r2, [r3, #4] + 8004b86: 687b ldr r3, [r7, #4] + 8004b88: 689b ldr r3, [r3, #8] + 8004b8a: 019b lsls r3, r3, #6 + 8004b8c: 431a orrs r2, r3 + 8004b8e: 687b ldr r3, [r7, #4] + 8004b90: 68db ldr r3, [r3, #12] + 8004b92: 085b lsrs r3, r3, #1 + 8004b94: 3b01 subs r3, #1 + 8004b96: 041b lsls r3, r3, #16 + 8004b98: 431a orrs r2, r3 + 8004b9a: 69bb ldr r3, [r7, #24] + 8004b9c: 061b lsls r3, r3, #24 + 8004b9e: 431a orrs r2, r3 + 8004ba0: 697b ldr r3, [r7, #20] + 8004ba2: 071b lsls r3, r3, #28 + 8004ba4: 4925 ldr r1, [pc, #148] @ (8004c3c ) + 8004ba6: 4313 orrs r3, r2 + 8004ba8: f8c1 3084 str.w r3, [r1, #132] @ 0x84 + 8004bac: 687b ldr r3, [r7, #4] + 8004bae: 681b ldr r3, [r3, #0] + 8004bb0: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8004bb4: 2b00 cmp r3, #0 + 8004bb6: d016 beq.n 8004be6 + 8004bb8: 687b ldr r3, [r7, #4] + 8004bba: 685a ldr r2, [r3, #4] + 8004bbc: 687b ldr r3, [r7, #4] + 8004bbe: 689b ldr r3, [r3, #8] + 8004bc0: 019b lsls r3, r3, #6 + 8004bc2: 431a orrs r2, r3 + 8004bc4: 687b ldr r3, [r7, #4] + 8004bc6: 68db ldr r3, [r3, #12] + 8004bc8: 085b lsrs r3, r3, #1 + 8004bca: 3b01 subs r3, #1 + 8004bcc: 041b lsls r3, r3, #16 + 8004bce: 431a orrs r2, r3 + 8004bd0: 687b ldr r3, [r7, #4] + 8004bd2: 691b ldr r3, [r3, #16] + 8004bd4: 061b lsls r3, r3, #24 + 8004bd6: 431a orrs r2, r3 + 8004bd8: 687b ldr r3, [r7, #4] + 8004bda: 695b ldr r3, [r3, #20] + 8004bdc: 071b lsls r3, r3, #28 + 8004bde: 4917 ldr r1, [pc, #92] @ (8004c3c ) + 8004be0: 4313 orrs r3, r2 + 8004be2: f8c1 3084 str.w r3, [r1, #132] @ 0x84 + 8004be6: 4b16 ldr r3, [pc, #88] @ (8004c40 ) + 8004be8: 2201 movs r2, #1 + 8004bea: 601a str r2, [r3, #0] + 8004bec: f7fd f99c bl 8001f28 + 8004bf0: 6278 str r0, [r7, #36] @ 0x24 + 8004bf2: e008 b.n 8004c06 + 8004bf4: f7fd f998 bl 8001f28 + 8004bf8: 4602 mov r2, r0 + 8004bfa: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004bfc: 1ad3 subs r3, r2, r3 + 8004bfe: 2b02 cmp r3, #2 + 8004c00: d901 bls.n 8004c06 + 8004c02: 2303 movs r3, #3 + 8004c04: e09f b.n 8004d46 + 8004c06: 4b0d ldr r3, [pc, #52] @ (8004c3c ) + 8004c08: 681b ldr r3, [r3, #0] + 8004c0a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 + 8004c0e: 2b00 cmp r3, #0 + 8004c10: d0f0 beq.n 8004bf4 + 8004c12: 6abb ldr r3, [r7, #40] @ 0x28 + 8004c14: 2b01 cmp r3, #1 + 8004c16: f040 8095 bne.w 8004d44 + 8004c1a: 4b0a ldr r3, [pc, #40] @ (8004c44 ) + 8004c1c: 2200 movs r2, #0 + 8004c1e: 601a str r2, [r3, #0] + 8004c20: f7fd f982 bl 8001f28 + 8004c24: 6278 str r0, [r7, #36] @ 0x24 + 8004c26: e00f b.n 8004c48 + 8004c28: f7fd f97e bl 8001f28 + 8004c2c: 4602 mov r2, r0 + 8004c2e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004c30: 1ad3 subs r3, r2, r3 + 8004c32: 2b02 cmp r3, #2 + 8004c34: d908 bls.n 8004c48 + 8004c36: 2303 movs r3, #3 + 8004c38: e085 b.n 8004d46 + 8004c3a: bf00 nop + 8004c3c: 40023800 .word 0x40023800 + 8004c40: 42470068 .word 0x42470068 + 8004c44: 42470070 .word 0x42470070 + 8004c48: 4b41 ldr r3, [pc, #260] @ (8004d50 ) + 8004c4a: 681b ldr r3, [r3, #0] + 8004c4c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 + 8004c50: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 8004c54: d0e8 beq.n 8004c28 + 8004c56: 687b ldr r3, [r7, #4] + 8004c58: 681b ldr r3, [r3, #0] + 8004c5a: f003 0304 and.w r3, r3, #4 + 8004c5e: 2b00 cmp r3, #0 + 8004c60: d003 beq.n 8004c6a + 8004c62: 687b ldr r3, [r7, #4] + 8004c64: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004c66: 2b00 cmp r3, #0 + 8004c68: d009 beq.n 8004c7e + 8004c6a: 687b ldr r3, [r7, #4] + 8004c6c: 681b ldr r3, [r3, #0] + 8004c6e: f003 0308 and.w r3, r3, #8 + 8004c72: 2b00 cmp r3, #0 + 8004c74: d02b beq.n 8004cce + 8004c76: 687b ldr r3, [r7, #4] + 8004c78: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004c7a: 2b00 cmp r3, #0 + 8004c7c: d127 bne.n 8004cce + 8004c7e: 4b34 ldr r3, [pc, #208] @ (8004d50 ) + 8004c80: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8004c84: 0c1b lsrs r3, r3, #16 + 8004c86: f003 0303 and.w r3, r3, #3 + 8004c8a: 3301 adds r3, #1 + 8004c8c: 005b lsls r3, r3, #1 + 8004c8e: 613b str r3, [r7, #16] + 8004c90: 687b ldr r3, [r7, #4] + 8004c92: 699a ldr r2, [r3, #24] + 8004c94: 687b ldr r3, [r7, #4] + 8004c96: 69db ldr r3, [r3, #28] + 8004c98: 019b lsls r3, r3, #6 + 8004c9a: 431a orrs r2, r3 + 8004c9c: 693b ldr r3, [r7, #16] + 8004c9e: 085b lsrs r3, r3, #1 + 8004ca0: 3b01 subs r3, #1 + 8004ca2: 041b lsls r3, r3, #16 + 8004ca4: 431a orrs r2, r3 + 8004ca6: 687b ldr r3, [r7, #4] + 8004ca8: 6a5b ldr r3, [r3, #36] @ 0x24 + 8004caa: 061b lsls r3, r3, #24 + 8004cac: 4928 ldr r1, [pc, #160] @ (8004d50 ) + 8004cae: 4313 orrs r3, r2 + 8004cb0: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8004cb4: 4b26 ldr r3, [pc, #152] @ (8004d50 ) + 8004cb6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8004cba: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8004cbe: 687b ldr r3, [r7, #4] + 8004cc0: 6adb ldr r3, [r3, #44] @ 0x2c + 8004cc2: 3b01 subs r3, #1 + 8004cc4: 021b lsls r3, r3, #8 + 8004cc6: 4922 ldr r1, [pc, #136] @ (8004d50 ) + 8004cc8: 4313 orrs r3, r2 + 8004cca: f8c1 308c str.w r3, [r1, #140] @ 0x8c + 8004cce: 687b ldr r3, [r7, #4] + 8004cd0: 681b ldr r3, [r3, #0] + 8004cd2: f403 7380 and.w r3, r3, #256 @ 0x100 + 8004cd6: 2b00 cmp r3, #0 + 8004cd8: d01d beq.n 8004d16 + 8004cda: 687b ldr r3, [r7, #4] + 8004cdc: 6d5b ldr r3, [r3, #84] @ 0x54 + 8004cde: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 + 8004ce2: d118 bne.n 8004d16 + 8004ce4: 4b1a ldr r3, [pc, #104] @ (8004d50 ) + 8004ce6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8004cea: 0e1b lsrs r3, r3, #24 + 8004cec: f003 030f and.w r3, r3, #15 + 8004cf0: 60fb str r3, [r7, #12] + 8004cf2: 687b ldr r3, [r7, #4] + 8004cf4: 699a ldr r2, [r3, #24] + 8004cf6: 687b ldr r3, [r7, #4] + 8004cf8: 69db ldr r3, [r3, #28] + 8004cfa: 019b lsls r3, r3, #6 + 8004cfc: 431a orrs r2, r3 + 8004cfe: 687b ldr r3, [r7, #4] + 8004d00: 6a1b ldr r3, [r3, #32] + 8004d02: 085b lsrs r3, r3, #1 + 8004d04: 3b01 subs r3, #1 + 8004d06: 041b lsls r3, r3, #16 + 8004d08: 431a orrs r2, r3 + 8004d0a: 68fb ldr r3, [r7, #12] + 8004d0c: 061b lsls r3, r3, #24 + 8004d0e: 4910 ldr r1, [pc, #64] @ (8004d50 ) + 8004d10: 4313 orrs r3, r2 + 8004d12: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8004d16: 4b0f ldr r3, [pc, #60] @ (8004d54 ) + 8004d18: 2201 movs r2, #1 + 8004d1a: 601a str r2, [r3, #0] + 8004d1c: f7fd f904 bl 8001f28 + 8004d20: 6278 str r0, [r7, #36] @ 0x24 + 8004d22: e008 b.n 8004d36 + 8004d24: f7fd f900 bl 8001f28 + 8004d28: 4602 mov r2, r0 + 8004d2a: 6a7b ldr r3, [r7, #36] @ 0x24 + 8004d2c: 1ad3 subs r3, r2, r3 + 8004d2e: 2b02 cmp r3, #2 + 8004d30: d901 bls.n 8004d36 + 8004d32: 2303 movs r3, #3 + 8004d34: e007 b.n 8004d46 + 8004d36: 4b06 ldr r3, [pc, #24] @ (8004d50 ) + 8004d38: 681b ldr r3, [r3, #0] + 8004d3a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 + 8004d3e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 8004d42: d1ef bne.n 8004d24 + 8004d44: 2300 movs r3, #0 + 8004d46: 4618 mov r0, r3 + 8004d48: 3730 adds r7, #48 @ 0x30 + 8004d4a: 46bd mov sp, r7 + 8004d4c: bd80 pop {r7, pc} + 8004d4e: bf00 nop + 8004d50: 40023800 .word 0x40023800 + 8004d54: 42470070 .word 0x42470070 + +08004d58 : + 8004d58: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8004d5c: b0ae sub sp, #184 @ 0xb8 + 8004d5e: af00 add r7, sp, #0 + 8004d60: 2300 movs r3, #0 + 8004d62: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 8004d66: 2300 movs r3, #0 + 8004d68: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 8004d6c: 2300 movs r3, #0 + 8004d6e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 + 8004d72: 2300 movs r3, #0 + 8004d74: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 + 8004d78: 2300 movs r3, #0 + 8004d7a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 8004d7e: 4bcb ldr r3, [pc, #812] @ (80050ac ) + 8004d80: 689b ldr r3, [r3, #8] + 8004d82: f003 030c and.w r3, r3, #12 + 8004d86: 2b0c cmp r3, #12 + 8004d88: f200 8206 bhi.w 8005198 + 8004d8c: a201 add r2, pc, #4 @ (adr r2, 8004d94 ) + 8004d8e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004d92: bf00 nop + 8004d94: 08004dc9 .word 0x08004dc9 + 8004d98: 08005199 .word 0x08005199 + 8004d9c: 08005199 .word 0x08005199 + 8004da0: 08005199 .word 0x08005199 + 8004da4: 08004dd1 .word 0x08004dd1 + 8004da8: 08005199 .word 0x08005199 + 8004dac: 08005199 .word 0x08005199 + 8004db0: 08005199 .word 0x08005199 + 8004db4: 08004dd9 .word 0x08004dd9 + 8004db8: 08005199 .word 0x08005199 + 8004dbc: 08005199 .word 0x08005199 + 8004dc0: 08005199 .word 0x08005199 + 8004dc4: 08004fc9 .word 0x08004fc9 + 8004dc8: 4bb9 ldr r3, [pc, #740] @ (80050b0 ) + 8004dca: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 8004dce: e1e7 b.n 80051a0 + 8004dd0: 4bb8 ldr r3, [pc, #736] @ (80050b4 ) + 8004dd2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 8004dd6: e1e3 b.n 80051a0 + 8004dd8: 4bb4 ldr r3, [pc, #720] @ (80050ac ) + 8004dda: 685b ldr r3, [r3, #4] + 8004ddc: f003 033f and.w r3, r3, #63 @ 0x3f + 8004de0: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 8004de4: 4bb1 ldr r3, [pc, #708] @ (80050ac ) + 8004de6: 685b ldr r3, [r3, #4] + 8004de8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8004dec: 2b00 cmp r3, #0 + 8004dee: d071 beq.n 8004ed4 + 8004df0: 4bae ldr r3, [pc, #696] @ (80050ac ) + 8004df2: 685b ldr r3, [r3, #4] + 8004df4: 099b lsrs r3, r3, #6 + 8004df6: 2200 movs r2, #0 + 8004df8: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + 8004dfc: f8c7 209c str.w r2, [r7, #156] @ 0x9c + 8004e00: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 + 8004e04: f3c3 0308 ubfx r3, r3, #0, #9 + 8004e08: f8c7 3090 str.w r3, [r7, #144] @ 0x90 + 8004e0c: 2300 movs r3, #0 + 8004e0e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 + 8004e12: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 + 8004e16: 4622 mov r2, r4 + 8004e18: 462b mov r3, r5 + 8004e1a: f04f 0000 mov.w r0, #0 + 8004e1e: f04f 0100 mov.w r1, #0 + 8004e22: 0159 lsls r1, r3, #5 + 8004e24: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8004e28: 0150 lsls r0, r2, #5 + 8004e2a: 4602 mov r2, r0 + 8004e2c: 460b mov r3, r1 + 8004e2e: 4621 mov r1, r4 + 8004e30: 1a51 subs r1, r2, r1 + 8004e32: 6439 str r1, [r7, #64] @ 0x40 + 8004e34: 4629 mov r1, r5 + 8004e36: eb63 0301 sbc.w r3, r3, r1 + 8004e3a: 647b str r3, [r7, #68] @ 0x44 + 8004e3c: f04f 0200 mov.w r2, #0 + 8004e40: f04f 0300 mov.w r3, #0 + 8004e44: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40 + 8004e48: 4649 mov r1, r9 + 8004e4a: 018b lsls r3, r1, #6 + 8004e4c: 4641 mov r1, r8 + 8004e4e: ea43 6391 orr.w r3, r3, r1, lsr #26 + 8004e52: 4641 mov r1, r8 + 8004e54: 018a lsls r2, r1, #6 + 8004e56: 4641 mov r1, r8 + 8004e58: 1a51 subs r1, r2, r1 + 8004e5a: 63b9 str r1, [r7, #56] @ 0x38 + 8004e5c: 4649 mov r1, r9 + 8004e5e: eb63 0301 sbc.w r3, r3, r1 + 8004e62: 63fb str r3, [r7, #60] @ 0x3c + 8004e64: f04f 0200 mov.w r2, #0 + 8004e68: f04f 0300 mov.w r3, #0 + 8004e6c: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38 + 8004e70: 4649 mov r1, r9 + 8004e72: 00cb lsls r3, r1, #3 + 8004e74: 4641 mov r1, r8 + 8004e76: ea43 7351 orr.w r3, r3, r1, lsr #29 + 8004e7a: 4641 mov r1, r8 + 8004e7c: 00ca lsls r2, r1, #3 + 8004e7e: 4610 mov r0, r2 + 8004e80: 4619 mov r1, r3 + 8004e82: 4603 mov r3, r0 + 8004e84: 4622 mov r2, r4 + 8004e86: 189b adds r3, r3, r2 + 8004e88: 633b str r3, [r7, #48] @ 0x30 + 8004e8a: 462b mov r3, r5 + 8004e8c: 460a mov r2, r1 + 8004e8e: eb42 0303 adc.w r3, r2, r3 + 8004e92: 637b str r3, [r7, #52] @ 0x34 + 8004e94: f04f 0200 mov.w r2, #0 + 8004e98: f04f 0300 mov.w r3, #0 + 8004e9c: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 + 8004ea0: 4629 mov r1, r5 + 8004ea2: 024b lsls r3, r1, #9 + 8004ea4: 4621 mov r1, r4 + 8004ea6: ea43 53d1 orr.w r3, r3, r1, lsr #23 + 8004eaa: 4621 mov r1, r4 + 8004eac: 024a lsls r2, r1, #9 + 8004eae: 4610 mov r0, r2 + 8004eb0: 4619 mov r1, r3 + 8004eb2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8004eb6: 2200 movs r2, #0 + 8004eb8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 + 8004ebc: f8c7 208c str.w r2, [r7, #140] @ 0x8c + 8004ec0: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88 + 8004ec4: f7fb f99e bl 8000204 <__aeabi_uldivmod> + 8004ec8: 4602 mov r2, r0 + 8004eca: 460b mov r3, r1 + 8004ecc: 4613 mov r3, r2 + 8004ece: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 8004ed2: e067 b.n 8004fa4 + 8004ed4: 4b75 ldr r3, [pc, #468] @ (80050ac ) + 8004ed6: 685b ldr r3, [r3, #4] + 8004ed8: 099b lsrs r3, r3, #6 + 8004eda: 2200 movs r2, #0 + 8004edc: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 8004ee0: f8c7 2084 str.w r2, [r7, #132] @ 0x84 + 8004ee4: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 + 8004ee8: f3c3 0308 ubfx r3, r3, #0, #9 + 8004eec: 67bb str r3, [r7, #120] @ 0x78 + 8004eee: 2300 movs r3, #0 + 8004ef0: 67fb str r3, [r7, #124] @ 0x7c + 8004ef2: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78 + 8004ef6: 4622 mov r2, r4 + 8004ef8: 462b mov r3, r5 + 8004efa: f04f 0000 mov.w r0, #0 + 8004efe: f04f 0100 mov.w r1, #0 + 8004f02: 0159 lsls r1, r3, #5 + 8004f04: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8004f08: 0150 lsls r0, r2, #5 + 8004f0a: 4602 mov r2, r0 + 8004f0c: 460b mov r3, r1 + 8004f0e: 4621 mov r1, r4 + 8004f10: 1a51 subs r1, r2, r1 + 8004f12: 62b9 str r1, [r7, #40] @ 0x28 + 8004f14: 4629 mov r1, r5 + 8004f16: eb63 0301 sbc.w r3, r3, r1 + 8004f1a: 62fb str r3, [r7, #44] @ 0x2c + 8004f1c: f04f 0200 mov.w r2, #0 + 8004f20: f04f 0300 mov.w r3, #0 + 8004f24: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28 + 8004f28: 4649 mov r1, r9 + 8004f2a: 018b lsls r3, r1, #6 + 8004f2c: 4641 mov r1, r8 + 8004f2e: ea43 6391 orr.w r3, r3, r1, lsr #26 + 8004f32: 4641 mov r1, r8 + 8004f34: 018a lsls r2, r1, #6 + 8004f36: 4641 mov r1, r8 + 8004f38: ebb2 0a01 subs.w sl, r2, r1 + 8004f3c: 4649 mov r1, r9 + 8004f3e: eb63 0b01 sbc.w fp, r3, r1 + 8004f42: f04f 0200 mov.w r2, #0 + 8004f46: f04f 0300 mov.w r3, #0 + 8004f4a: ea4f 03cb mov.w r3, fp, lsl #3 + 8004f4e: ea43 735a orr.w r3, r3, sl, lsr #29 + 8004f52: ea4f 02ca mov.w r2, sl, lsl #3 + 8004f56: 4692 mov sl, r2 + 8004f58: 469b mov fp, r3 + 8004f5a: 4623 mov r3, r4 + 8004f5c: eb1a 0303 adds.w r3, sl, r3 + 8004f60: 623b str r3, [r7, #32] + 8004f62: 462b mov r3, r5 + 8004f64: eb4b 0303 adc.w r3, fp, r3 + 8004f68: 627b str r3, [r7, #36] @ 0x24 + 8004f6a: f04f 0200 mov.w r2, #0 + 8004f6e: f04f 0300 mov.w r3, #0 + 8004f72: e9d7 4508 ldrd r4, r5, [r7, #32] + 8004f76: 4629 mov r1, r5 + 8004f78: 028b lsls r3, r1, #10 + 8004f7a: 4621 mov r1, r4 + 8004f7c: ea43 5391 orr.w r3, r3, r1, lsr #22 + 8004f80: 4621 mov r1, r4 + 8004f82: 028a lsls r2, r1, #10 + 8004f84: 4610 mov r0, r2 + 8004f86: 4619 mov r1, r3 + 8004f88: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8004f8c: 2200 movs r2, #0 + 8004f8e: 673b str r3, [r7, #112] @ 0x70 + 8004f90: 677a str r2, [r7, #116] @ 0x74 + 8004f92: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70 + 8004f96: f7fb f935 bl 8000204 <__aeabi_uldivmod> + 8004f9a: 4602 mov r2, r0 + 8004f9c: 460b mov r3, r1 + 8004f9e: 4613 mov r3, r2 + 8004fa0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 8004fa4: 4b41 ldr r3, [pc, #260] @ (80050ac ) + 8004fa6: 685b ldr r3, [r3, #4] + 8004fa8: 0c1b lsrs r3, r3, #16 + 8004faa: f003 0303 and.w r3, r3, #3 + 8004fae: 3301 adds r3, #1 + 8004fb0: 005b lsls r3, r3, #1 + 8004fb2: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 + 8004fb6: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 + 8004fba: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 + 8004fbe: fbb2 f3f3 udiv r3, r2, r3 + 8004fc2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 8004fc6: e0eb b.n 80051a0 + 8004fc8: 4b38 ldr r3, [pc, #224] @ (80050ac ) + 8004fca: 685b ldr r3, [r3, #4] + 8004fcc: f003 033f and.w r3, r3, #63 @ 0x3f + 8004fd0: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 8004fd4: 4b35 ldr r3, [pc, #212] @ (80050ac ) + 8004fd6: 685b ldr r3, [r3, #4] + 8004fd8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8004fdc: 2b00 cmp r3, #0 + 8004fde: d06b beq.n 80050b8 + 8004fe0: 4b32 ldr r3, [pc, #200] @ (80050ac ) + 8004fe2: 685b ldr r3, [r3, #4] + 8004fe4: 099b lsrs r3, r3, #6 + 8004fe6: 2200 movs r2, #0 + 8004fe8: 66bb str r3, [r7, #104] @ 0x68 + 8004fea: 66fa str r2, [r7, #108] @ 0x6c + 8004fec: 6ebb ldr r3, [r7, #104] @ 0x68 + 8004fee: f3c3 0308 ubfx r3, r3, #0, #9 + 8004ff2: 663b str r3, [r7, #96] @ 0x60 + 8004ff4: 2300 movs r3, #0 + 8004ff6: 667b str r3, [r7, #100] @ 0x64 + 8004ff8: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60 + 8004ffc: 4622 mov r2, r4 + 8004ffe: 462b mov r3, r5 + 8005000: f04f 0000 mov.w r0, #0 + 8005004: f04f 0100 mov.w r1, #0 + 8005008: 0159 lsls r1, r3, #5 + 800500a: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 800500e: 0150 lsls r0, r2, #5 + 8005010: 4602 mov r2, r0 + 8005012: 460b mov r3, r1 + 8005014: 4621 mov r1, r4 + 8005016: 1a51 subs r1, r2, r1 + 8005018: 61b9 str r1, [r7, #24] + 800501a: 4629 mov r1, r5 + 800501c: eb63 0301 sbc.w r3, r3, r1 + 8005020: 61fb str r3, [r7, #28] + 8005022: f04f 0200 mov.w r2, #0 + 8005026: f04f 0300 mov.w r3, #0 + 800502a: e9d7 ab06 ldrd sl, fp, [r7, #24] + 800502e: 4659 mov r1, fp + 8005030: 018b lsls r3, r1, #6 + 8005032: 4651 mov r1, sl + 8005034: ea43 6391 orr.w r3, r3, r1, lsr #26 + 8005038: 4651 mov r1, sl + 800503a: 018a lsls r2, r1, #6 + 800503c: 4651 mov r1, sl + 800503e: ebb2 0801 subs.w r8, r2, r1 + 8005042: 4659 mov r1, fp + 8005044: eb63 0901 sbc.w r9, r3, r1 + 8005048: f04f 0200 mov.w r2, #0 + 800504c: f04f 0300 mov.w r3, #0 + 8005050: ea4f 03c9 mov.w r3, r9, lsl #3 + 8005054: ea43 7358 orr.w r3, r3, r8, lsr #29 + 8005058: ea4f 02c8 mov.w r2, r8, lsl #3 + 800505c: 4690 mov r8, r2 + 800505e: 4699 mov r9, r3 + 8005060: 4623 mov r3, r4 + 8005062: eb18 0303 adds.w r3, r8, r3 + 8005066: 613b str r3, [r7, #16] + 8005068: 462b mov r3, r5 + 800506a: eb49 0303 adc.w r3, r9, r3 + 800506e: 617b str r3, [r7, #20] + 8005070: f04f 0200 mov.w r2, #0 + 8005074: f04f 0300 mov.w r3, #0 + 8005078: e9d7 4504 ldrd r4, r5, [r7, #16] + 800507c: 4629 mov r1, r5 + 800507e: 024b lsls r3, r1, #9 + 8005080: 4621 mov r1, r4 + 8005082: ea43 53d1 orr.w r3, r3, r1, lsr #23 + 8005086: 4621 mov r1, r4 + 8005088: 024a lsls r2, r1, #9 + 800508a: 4610 mov r0, r2 + 800508c: 4619 mov r1, r3 + 800508e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8005092: 2200 movs r2, #0 + 8005094: 65bb str r3, [r7, #88] @ 0x58 + 8005096: 65fa str r2, [r7, #92] @ 0x5c + 8005098: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 + 800509c: f7fb f8b2 bl 8000204 <__aeabi_uldivmod> + 80050a0: 4602 mov r2, r0 + 80050a2: 460b mov r3, r1 + 80050a4: 4613 mov r3, r2 + 80050a6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 80050aa: e065 b.n 8005178 + 80050ac: 40023800 .word 0x40023800 + 80050b0: 00f42400 .word 0x00f42400 + 80050b4: 007a1200 .word 0x007a1200 + 80050b8: 4b3d ldr r3, [pc, #244] @ (80051b0 ) + 80050ba: 685b ldr r3, [r3, #4] + 80050bc: 099b lsrs r3, r3, #6 + 80050be: 2200 movs r2, #0 + 80050c0: 4618 mov r0, r3 + 80050c2: 4611 mov r1, r2 + 80050c4: f3c0 0308 ubfx r3, r0, #0, #9 + 80050c8: 653b str r3, [r7, #80] @ 0x50 + 80050ca: 2300 movs r3, #0 + 80050cc: 657b str r3, [r7, #84] @ 0x54 + 80050ce: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50 + 80050d2: 4642 mov r2, r8 + 80050d4: 464b mov r3, r9 + 80050d6: f04f 0000 mov.w r0, #0 + 80050da: f04f 0100 mov.w r1, #0 + 80050de: 0159 lsls r1, r3, #5 + 80050e0: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 80050e4: 0150 lsls r0, r2, #5 + 80050e6: 4602 mov r2, r0 + 80050e8: 460b mov r3, r1 + 80050ea: 4641 mov r1, r8 + 80050ec: 1a51 subs r1, r2, r1 + 80050ee: 60b9 str r1, [r7, #8] + 80050f0: 4649 mov r1, r9 + 80050f2: eb63 0301 sbc.w r3, r3, r1 + 80050f6: 60fb str r3, [r7, #12] + 80050f8: f04f 0200 mov.w r2, #0 + 80050fc: f04f 0300 mov.w r3, #0 + 8005100: e9d7 ab02 ldrd sl, fp, [r7, #8] + 8005104: 4659 mov r1, fp + 8005106: 018b lsls r3, r1, #6 + 8005108: 4651 mov r1, sl + 800510a: ea43 6391 orr.w r3, r3, r1, lsr #26 + 800510e: 4651 mov r1, sl + 8005110: 018a lsls r2, r1, #6 + 8005112: 4651 mov r1, sl + 8005114: 1a54 subs r4, r2, r1 + 8005116: 4659 mov r1, fp + 8005118: eb63 0501 sbc.w r5, r3, r1 + 800511c: f04f 0200 mov.w r2, #0 + 8005120: f04f 0300 mov.w r3, #0 + 8005124: 00eb lsls r3, r5, #3 + 8005126: ea43 7354 orr.w r3, r3, r4, lsr #29 + 800512a: 00e2 lsls r2, r4, #3 + 800512c: 4614 mov r4, r2 + 800512e: 461d mov r5, r3 + 8005130: 4643 mov r3, r8 + 8005132: 18e3 adds r3, r4, r3 + 8005134: 603b str r3, [r7, #0] + 8005136: 464b mov r3, r9 + 8005138: eb45 0303 adc.w r3, r5, r3 + 800513c: 607b str r3, [r7, #4] + 800513e: f04f 0200 mov.w r2, #0 + 8005142: f04f 0300 mov.w r3, #0 + 8005146: e9d7 4500 ldrd r4, r5, [r7] + 800514a: 4629 mov r1, r5 + 800514c: 028b lsls r3, r1, #10 + 800514e: 4621 mov r1, r4 + 8005150: ea43 5391 orr.w r3, r3, r1, lsr #22 + 8005154: 4621 mov r1, r4 + 8005156: 028a lsls r2, r1, #10 + 8005158: 4610 mov r0, r2 + 800515a: 4619 mov r1, r3 + 800515c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8005160: 2200 movs r2, #0 + 8005162: 64bb str r3, [r7, #72] @ 0x48 + 8005164: 64fa str r2, [r7, #76] @ 0x4c + 8005166: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 + 800516a: f7fb f84b bl 8000204 <__aeabi_uldivmod> + 800516e: 4602 mov r2, r0 + 8005170: 460b mov r3, r1 + 8005172: 4613 mov r3, r2 + 8005174: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 8005178: 4b0d ldr r3, [pc, #52] @ (80051b0 ) + 800517a: 685b ldr r3, [r3, #4] + 800517c: 0f1b lsrs r3, r3, #28 + 800517e: f003 0307 and.w r3, r3, #7 + 8005182: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 + 8005186: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 + 800518a: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 + 800518e: fbb2 f3f3 udiv r3, r2, r3 + 8005192: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 8005196: e003 b.n 80051a0 + 8005198: 4b06 ldr r3, [pc, #24] @ (80051b4 ) + 800519a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 800519e: bf00 nop + 80051a0: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 + 80051a4: 4618 mov r0, r3 + 80051a6: 37b8 adds r7, #184 @ 0xb8 + 80051a8: 46bd mov sp, r7 + 80051aa: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 80051ae: bf00 nop + 80051b0: 40023800 .word 0x40023800 + 80051b4: 00f42400 .word 0x00f42400 + +080051b8 : + 80051b8: b580 push {r7, lr} + 80051ba: b086 sub sp, #24 + 80051bc: af00 add r7, sp, #0 + 80051be: 6078 str r0, [r7, #4] + 80051c0: 687b ldr r3, [r7, #4] + 80051c2: 2b00 cmp r3, #0 + 80051c4: d101 bne.n 80051ca + 80051c6: 2301 movs r3, #1 + 80051c8: e28d b.n 80056e6 + 80051ca: 687b ldr r3, [r7, #4] + 80051cc: 681b ldr r3, [r3, #0] + 80051ce: f003 0301 and.w r3, r3, #1 + 80051d2: 2b00 cmp r3, #0 + 80051d4: f000 8083 beq.w 80052de + 80051d8: 4b94 ldr r3, [pc, #592] @ (800542c ) + 80051da: 689b ldr r3, [r3, #8] + 80051dc: f003 030c and.w r3, r3, #12 + 80051e0: 2b04 cmp r3, #4 + 80051e2: d019 beq.n 8005218 + 80051e4: 4b91 ldr r3, [pc, #580] @ (800542c ) + 80051e6: 689b ldr r3, [r3, #8] + 80051e8: f003 030c and.w r3, r3, #12 + 80051ec: 2b08 cmp r3, #8 + 80051ee: d106 bne.n 80051fe + 80051f0: 4b8e ldr r3, [pc, #568] @ (800542c ) + 80051f2: 685b ldr r3, [r3, #4] + 80051f4: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 80051f8: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 80051fc: d00c beq.n 8005218 + 80051fe: 4b8b ldr r3, [pc, #556] @ (800542c ) + 8005200: 689b ldr r3, [r3, #8] + 8005202: f003 030c and.w r3, r3, #12 + 8005206: 2b0c cmp r3, #12 + 8005208: d112 bne.n 8005230 + 800520a: 4b88 ldr r3, [pc, #544] @ (800542c ) + 800520c: 685b ldr r3, [r3, #4] + 800520e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8005212: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8005216: d10b bne.n 8005230 + 8005218: 4b84 ldr r3, [pc, #528] @ (800542c ) + 800521a: 681b ldr r3, [r3, #0] + 800521c: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8005220: 2b00 cmp r3, #0 + 8005222: d05b beq.n 80052dc + 8005224: 687b ldr r3, [r7, #4] + 8005226: 685b ldr r3, [r3, #4] + 8005228: 2b00 cmp r3, #0 + 800522a: d157 bne.n 80052dc + 800522c: 2301 movs r3, #1 + 800522e: e25a b.n 80056e6 + 8005230: 687b ldr r3, [r7, #4] + 8005232: 685b ldr r3, [r3, #4] + 8005234: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8005238: d106 bne.n 8005248 + 800523a: 4b7c ldr r3, [pc, #496] @ (800542c ) + 800523c: 681b ldr r3, [r3, #0] + 800523e: 4a7b ldr r2, [pc, #492] @ (800542c ) + 8005240: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8005244: 6013 str r3, [r2, #0] + 8005246: e01d b.n 8005284 + 8005248: 687b ldr r3, [r7, #4] + 800524a: 685b ldr r3, [r3, #4] + 800524c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 + 8005250: d10c bne.n 800526c + 8005252: 4b76 ldr r3, [pc, #472] @ (800542c ) + 8005254: 681b ldr r3, [r3, #0] + 8005256: 4a75 ldr r2, [pc, #468] @ (800542c ) + 8005258: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 800525c: 6013 str r3, [r2, #0] + 800525e: 4b73 ldr r3, [pc, #460] @ (800542c ) + 8005260: 681b ldr r3, [r3, #0] + 8005262: 4a72 ldr r2, [pc, #456] @ (800542c ) + 8005264: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8005268: 6013 str r3, [r2, #0] + 800526a: e00b b.n 8005284 + 800526c: 4b6f ldr r3, [pc, #444] @ (800542c ) + 800526e: 681b ldr r3, [r3, #0] + 8005270: 4a6e ldr r2, [pc, #440] @ (800542c ) + 8005272: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8005276: 6013 str r3, [r2, #0] + 8005278: 4b6c ldr r3, [pc, #432] @ (800542c ) + 800527a: 681b ldr r3, [r3, #0] + 800527c: 4a6b ldr r2, [pc, #428] @ (800542c ) + 800527e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8005282: 6013 str r3, [r2, #0] + 8005284: 687b ldr r3, [r7, #4] + 8005286: 685b ldr r3, [r3, #4] + 8005288: 2b00 cmp r3, #0 + 800528a: d013 beq.n 80052b4 + 800528c: f7fc fe4c bl 8001f28 + 8005290: 6138 str r0, [r7, #16] + 8005292: e008 b.n 80052a6 + 8005294: f7fc fe48 bl 8001f28 + 8005298: 4602 mov r2, r0 + 800529a: 693b ldr r3, [r7, #16] + 800529c: 1ad3 subs r3, r2, r3 + 800529e: 2b64 cmp r3, #100 @ 0x64 + 80052a0: d901 bls.n 80052a6 + 80052a2: 2303 movs r3, #3 + 80052a4: e21f b.n 80056e6 + 80052a6: 4b61 ldr r3, [pc, #388] @ (800542c ) + 80052a8: 681b ldr r3, [r3, #0] + 80052aa: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80052ae: 2b00 cmp r3, #0 + 80052b0: d0f0 beq.n 8005294 + 80052b2: e014 b.n 80052de + 80052b4: f7fc fe38 bl 8001f28 + 80052b8: 6138 str r0, [r7, #16] + 80052ba: e008 b.n 80052ce + 80052bc: f7fc fe34 bl 8001f28 + 80052c0: 4602 mov r2, r0 + 80052c2: 693b ldr r3, [r7, #16] + 80052c4: 1ad3 subs r3, r2, r3 + 80052c6: 2b64 cmp r3, #100 @ 0x64 + 80052c8: d901 bls.n 80052ce + 80052ca: 2303 movs r3, #3 + 80052cc: e20b b.n 80056e6 + 80052ce: 4b57 ldr r3, [pc, #348] @ (800542c ) + 80052d0: 681b ldr r3, [r3, #0] + 80052d2: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80052d6: 2b00 cmp r3, #0 + 80052d8: d1f0 bne.n 80052bc + 80052da: e000 b.n 80052de + 80052dc: bf00 nop + 80052de: 687b ldr r3, [r7, #4] + 80052e0: 681b ldr r3, [r3, #0] + 80052e2: f003 0302 and.w r3, r3, #2 + 80052e6: 2b00 cmp r3, #0 + 80052e8: d06f beq.n 80053ca + 80052ea: 4b50 ldr r3, [pc, #320] @ (800542c ) + 80052ec: 689b ldr r3, [r3, #8] + 80052ee: f003 030c and.w r3, r3, #12 + 80052f2: 2b00 cmp r3, #0 + 80052f4: d017 beq.n 8005326 + 80052f6: 4b4d ldr r3, [pc, #308] @ (800542c ) + 80052f8: 689b ldr r3, [r3, #8] + 80052fa: f003 030c and.w r3, r3, #12 + 80052fe: 2b08 cmp r3, #8 + 8005300: d105 bne.n 800530e + 8005302: 4b4a ldr r3, [pc, #296] @ (800542c ) + 8005304: 685b ldr r3, [r3, #4] + 8005306: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 800530a: 2b00 cmp r3, #0 + 800530c: d00b beq.n 8005326 + 800530e: 4b47 ldr r3, [pc, #284] @ (800542c ) + 8005310: 689b ldr r3, [r3, #8] + 8005312: f003 030c and.w r3, r3, #12 + 8005316: 2b0c cmp r3, #12 + 8005318: d11c bne.n 8005354 + 800531a: 4b44 ldr r3, [pc, #272] @ (800542c ) + 800531c: 685b ldr r3, [r3, #4] + 800531e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8005322: 2b00 cmp r3, #0 + 8005324: d116 bne.n 8005354 + 8005326: 4b41 ldr r3, [pc, #260] @ (800542c ) + 8005328: 681b ldr r3, [r3, #0] + 800532a: f003 0302 and.w r3, r3, #2 + 800532e: 2b00 cmp r3, #0 + 8005330: d005 beq.n 800533e + 8005332: 687b ldr r3, [r7, #4] + 8005334: 68db ldr r3, [r3, #12] + 8005336: 2b01 cmp r3, #1 + 8005338: d001 beq.n 800533e + 800533a: 2301 movs r3, #1 + 800533c: e1d3 b.n 80056e6 + 800533e: 4b3b ldr r3, [pc, #236] @ (800542c ) + 8005340: 681b ldr r3, [r3, #0] + 8005342: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 8005346: 687b ldr r3, [r7, #4] + 8005348: 691b ldr r3, [r3, #16] + 800534a: 00db lsls r3, r3, #3 + 800534c: 4937 ldr r1, [pc, #220] @ (800542c ) + 800534e: 4313 orrs r3, r2 + 8005350: 600b str r3, [r1, #0] + 8005352: e03a b.n 80053ca + 8005354: 687b ldr r3, [r7, #4] + 8005356: 68db ldr r3, [r3, #12] + 8005358: 2b00 cmp r3, #0 + 800535a: d020 beq.n 800539e + 800535c: 4b34 ldr r3, [pc, #208] @ (8005430 ) + 800535e: 2201 movs r2, #1 + 8005360: 601a str r2, [r3, #0] + 8005362: f7fc fde1 bl 8001f28 + 8005366: 6138 str r0, [r7, #16] + 8005368: e008 b.n 800537c + 800536a: f7fc fddd bl 8001f28 + 800536e: 4602 mov r2, r0 + 8005370: 693b ldr r3, [r7, #16] + 8005372: 1ad3 subs r3, r2, r3 + 8005374: 2b02 cmp r3, #2 + 8005376: d901 bls.n 800537c + 8005378: 2303 movs r3, #3 + 800537a: e1b4 b.n 80056e6 + 800537c: 4b2b ldr r3, [pc, #172] @ (800542c ) + 800537e: 681b ldr r3, [r3, #0] + 8005380: f003 0302 and.w r3, r3, #2 + 8005384: 2b00 cmp r3, #0 + 8005386: d0f0 beq.n 800536a + 8005388: 4b28 ldr r3, [pc, #160] @ (800542c ) + 800538a: 681b ldr r3, [r3, #0] + 800538c: f023 02f8 bic.w r2, r3, #248 @ 0xf8 + 8005390: 687b ldr r3, [r7, #4] + 8005392: 691b ldr r3, [r3, #16] + 8005394: 00db lsls r3, r3, #3 + 8005396: 4925 ldr r1, [pc, #148] @ (800542c ) + 8005398: 4313 orrs r3, r2 + 800539a: 600b str r3, [r1, #0] + 800539c: e015 b.n 80053ca + 800539e: 4b24 ldr r3, [pc, #144] @ (8005430 ) + 80053a0: 2200 movs r2, #0 + 80053a2: 601a str r2, [r3, #0] + 80053a4: f7fc fdc0 bl 8001f28 + 80053a8: 6138 str r0, [r7, #16] + 80053aa: e008 b.n 80053be + 80053ac: f7fc fdbc bl 8001f28 + 80053b0: 4602 mov r2, r0 + 80053b2: 693b ldr r3, [r7, #16] + 80053b4: 1ad3 subs r3, r2, r3 + 80053b6: 2b02 cmp r3, #2 + 80053b8: d901 bls.n 80053be + 80053ba: 2303 movs r3, #3 + 80053bc: e193 b.n 80056e6 + 80053be: 4b1b ldr r3, [pc, #108] @ (800542c ) + 80053c0: 681b ldr r3, [r3, #0] + 80053c2: f003 0302 and.w r3, r3, #2 + 80053c6: 2b00 cmp r3, #0 + 80053c8: d1f0 bne.n 80053ac + 80053ca: 687b ldr r3, [r7, #4] + 80053cc: 681b ldr r3, [r3, #0] + 80053ce: f003 0308 and.w r3, r3, #8 + 80053d2: 2b00 cmp r3, #0 + 80053d4: d036 beq.n 8005444 + 80053d6: 687b ldr r3, [r7, #4] + 80053d8: 695b ldr r3, [r3, #20] + 80053da: 2b00 cmp r3, #0 + 80053dc: d016 beq.n 800540c + 80053de: 4b15 ldr r3, [pc, #84] @ (8005434 ) + 80053e0: 2201 movs r2, #1 + 80053e2: 601a str r2, [r3, #0] + 80053e4: f7fc fda0 bl 8001f28 + 80053e8: 6138 str r0, [r7, #16] + 80053ea: e008 b.n 80053fe + 80053ec: f7fc fd9c bl 8001f28 + 80053f0: 4602 mov r2, r0 + 80053f2: 693b ldr r3, [r7, #16] + 80053f4: 1ad3 subs r3, r2, r3 + 80053f6: 2b02 cmp r3, #2 + 80053f8: d901 bls.n 80053fe + 80053fa: 2303 movs r3, #3 + 80053fc: e173 b.n 80056e6 + 80053fe: 4b0b ldr r3, [pc, #44] @ (800542c ) + 8005400: 6f5b ldr r3, [r3, #116] @ 0x74 + 8005402: f003 0302 and.w r3, r3, #2 + 8005406: 2b00 cmp r3, #0 + 8005408: d0f0 beq.n 80053ec + 800540a: e01b b.n 8005444 + 800540c: 4b09 ldr r3, [pc, #36] @ (8005434 ) + 800540e: 2200 movs r2, #0 + 8005410: 601a str r2, [r3, #0] + 8005412: f7fc fd89 bl 8001f28 + 8005416: 6138 str r0, [r7, #16] + 8005418: e00e b.n 8005438 + 800541a: f7fc fd85 bl 8001f28 + 800541e: 4602 mov r2, r0 + 8005420: 693b ldr r3, [r7, #16] + 8005422: 1ad3 subs r3, r2, r3 + 8005424: 2b02 cmp r3, #2 + 8005426: d907 bls.n 8005438 + 8005428: 2303 movs r3, #3 + 800542a: e15c b.n 80056e6 + 800542c: 40023800 .word 0x40023800 + 8005430: 42470000 .word 0x42470000 + 8005434: 42470e80 .word 0x42470e80 + 8005438: 4b8a ldr r3, [pc, #552] @ (8005664 ) + 800543a: 6f5b ldr r3, [r3, #116] @ 0x74 + 800543c: f003 0302 and.w r3, r3, #2 + 8005440: 2b00 cmp r3, #0 + 8005442: d1ea bne.n 800541a + 8005444: 687b ldr r3, [r7, #4] + 8005446: 681b ldr r3, [r3, #0] + 8005448: f003 0304 and.w r3, r3, #4 + 800544c: 2b00 cmp r3, #0 + 800544e: f000 8097 beq.w 8005580 + 8005452: 2300 movs r3, #0 + 8005454: 75fb strb r3, [r7, #23] + 8005456: 4b83 ldr r3, [pc, #524] @ (8005664 ) + 8005458: 6c1b ldr r3, [r3, #64] @ 0x40 + 800545a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800545e: 2b00 cmp r3, #0 + 8005460: d10f bne.n 8005482 + 8005462: 2300 movs r3, #0 + 8005464: 60bb str r3, [r7, #8] + 8005466: 4b7f ldr r3, [pc, #508] @ (8005664 ) + 8005468: 6c1b ldr r3, [r3, #64] @ 0x40 + 800546a: 4a7e ldr r2, [pc, #504] @ (8005664 ) + 800546c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8005470: 6413 str r3, [r2, #64] @ 0x40 + 8005472: 4b7c ldr r3, [pc, #496] @ (8005664 ) + 8005474: 6c1b ldr r3, [r3, #64] @ 0x40 + 8005476: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800547a: 60bb str r3, [r7, #8] + 800547c: 68bb ldr r3, [r7, #8] + 800547e: 2301 movs r3, #1 + 8005480: 75fb strb r3, [r7, #23] + 8005482: 4b79 ldr r3, [pc, #484] @ (8005668 ) + 8005484: 681b ldr r3, [r3, #0] + 8005486: f403 7380 and.w r3, r3, #256 @ 0x100 + 800548a: 2b00 cmp r3, #0 + 800548c: d118 bne.n 80054c0 + 800548e: 4b76 ldr r3, [pc, #472] @ (8005668 ) + 8005490: 681b ldr r3, [r3, #0] + 8005492: 4a75 ldr r2, [pc, #468] @ (8005668 ) + 8005494: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8005498: 6013 str r3, [r2, #0] + 800549a: f7fc fd45 bl 8001f28 + 800549e: 6138 str r0, [r7, #16] + 80054a0: e008 b.n 80054b4 + 80054a2: f7fc fd41 bl 8001f28 + 80054a6: 4602 mov r2, r0 + 80054a8: 693b ldr r3, [r7, #16] + 80054aa: 1ad3 subs r3, r2, r3 + 80054ac: 2b02 cmp r3, #2 + 80054ae: d901 bls.n 80054b4 + 80054b0: 2303 movs r3, #3 + 80054b2: e118 b.n 80056e6 + 80054b4: 4b6c ldr r3, [pc, #432] @ (8005668 ) + 80054b6: 681b ldr r3, [r3, #0] + 80054b8: f403 7380 and.w r3, r3, #256 @ 0x100 + 80054bc: 2b00 cmp r3, #0 + 80054be: d0f0 beq.n 80054a2 + 80054c0: 687b ldr r3, [r7, #4] + 80054c2: 689b ldr r3, [r3, #8] + 80054c4: 2b01 cmp r3, #1 + 80054c6: d106 bne.n 80054d6 + 80054c8: 4b66 ldr r3, [pc, #408] @ (8005664 ) + 80054ca: 6f1b ldr r3, [r3, #112] @ 0x70 + 80054cc: 4a65 ldr r2, [pc, #404] @ (8005664 ) + 80054ce: f043 0301 orr.w r3, r3, #1 + 80054d2: 6713 str r3, [r2, #112] @ 0x70 + 80054d4: e01c b.n 8005510 + 80054d6: 687b ldr r3, [r7, #4] + 80054d8: 689b ldr r3, [r3, #8] + 80054da: 2b05 cmp r3, #5 + 80054dc: d10c bne.n 80054f8 + 80054de: 4b61 ldr r3, [pc, #388] @ (8005664 ) + 80054e0: 6f1b ldr r3, [r3, #112] @ 0x70 + 80054e2: 4a60 ldr r2, [pc, #384] @ (8005664 ) + 80054e4: f043 0304 orr.w r3, r3, #4 + 80054e8: 6713 str r3, [r2, #112] @ 0x70 + 80054ea: 4b5e ldr r3, [pc, #376] @ (8005664 ) + 80054ec: 6f1b ldr r3, [r3, #112] @ 0x70 + 80054ee: 4a5d ldr r2, [pc, #372] @ (8005664 ) + 80054f0: f043 0301 orr.w r3, r3, #1 + 80054f4: 6713 str r3, [r2, #112] @ 0x70 + 80054f6: e00b b.n 8005510 + 80054f8: 4b5a ldr r3, [pc, #360] @ (8005664 ) + 80054fa: 6f1b ldr r3, [r3, #112] @ 0x70 + 80054fc: 4a59 ldr r2, [pc, #356] @ (8005664 ) + 80054fe: f023 0301 bic.w r3, r3, #1 + 8005502: 6713 str r3, [r2, #112] @ 0x70 + 8005504: 4b57 ldr r3, [pc, #348] @ (8005664 ) + 8005506: 6f1b ldr r3, [r3, #112] @ 0x70 + 8005508: 4a56 ldr r2, [pc, #344] @ (8005664 ) + 800550a: f023 0304 bic.w r3, r3, #4 + 800550e: 6713 str r3, [r2, #112] @ 0x70 + 8005510: 687b ldr r3, [r7, #4] + 8005512: 689b ldr r3, [r3, #8] + 8005514: 2b00 cmp r3, #0 + 8005516: d015 beq.n 8005544 + 8005518: f7fc fd06 bl 8001f28 + 800551c: 6138 str r0, [r7, #16] + 800551e: e00a b.n 8005536 + 8005520: f7fc fd02 bl 8001f28 + 8005524: 4602 mov r2, r0 + 8005526: 693b ldr r3, [r7, #16] + 8005528: 1ad3 subs r3, r2, r3 + 800552a: f241 3288 movw r2, #5000 @ 0x1388 + 800552e: 4293 cmp r3, r2 + 8005530: d901 bls.n 8005536 + 8005532: 2303 movs r3, #3 + 8005534: e0d7 b.n 80056e6 + 8005536: 4b4b ldr r3, [pc, #300] @ (8005664 ) + 8005538: 6f1b ldr r3, [r3, #112] @ 0x70 + 800553a: f003 0302 and.w r3, r3, #2 + 800553e: 2b00 cmp r3, #0 + 8005540: d0ee beq.n 8005520 + 8005542: e014 b.n 800556e + 8005544: f7fc fcf0 bl 8001f28 + 8005548: 6138 str r0, [r7, #16] + 800554a: e00a b.n 8005562 + 800554c: f7fc fcec bl 8001f28 + 8005550: 4602 mov r2, r0 + 8005552: 693b ldr r3, [r7, #16] + 8005554: 1ad3 subs r3, r2, r3 + 8005556: f241 3288 movw r2, #5000 @ 0x1388 + 800555a: 4293 cmp r3, r2 + 800555c: d901 bls.n 8005562 + 800555e: 2303 movs r3, #3 + 8005560: e0c1 b.n 80056e6 + 8005562: 4b40 ldr r3, [pc, #256] @ (8005664 ) + 8005564: 6f1b ldr r3, [r3, #112] @ 0x70 + 8005566: f003 0302 and.w r3, r3, #2 + 800556a: 2b00 cmp r3, #0 + 800556c: d1ee bne.n 800554c + 800556e: 7dfb ldrb r3, [r7, #23] + 8005570: 2b01 cmp r3, #1 + 8005572: d105 bne.n 8005580 + 8005574: 4b3b ldr r3, [pc, #236] @ (8005664 ) + 8005576: 6c1b ldr r3, [r3, #64] @ 0x40 + 8005578: 4a3a ldr r2, [pc, #232] @ (8005664 ) + 800557a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 800557e: 6413 str r3, [r2, #64] @ 0x40 + 8005580: 687b ldr r3, [r7, #4] + 8005582: 699b ldr r3, [r3, #24] + 8005584: 2b00 cmp r3, #0 + 8005586: f000 80ad beq.w 80056e4 + 800558a: 4b36 ldr r3, [pc, #216] @ (8005664 ) + 800558c: 689b ldr r3, [r3, #8] + 800558e: f003 030c and.w r3, r3, #12 + 8005592: 2b08 cmp r3, #8 + 8005594: d060 beq.n 8005658 + 8005596: 687b ldr r3, [r7, #4] + 8005598: 699b ldr r3, [r3, #24] + 800559a: 2b02 cmp r3, #2 + 800559c: d145 bne.n 800562a + 800559e: 4b33 ldr r3, [pc, #204] @ (800566c ) + 80055a0: 2200 movs r2, #0 + 80055a2: 601a str r2, [r3, #0] + 80055a4: f7fc fcc0 bl 8001f28 + 80055a8: 6138 str r0, [r7, #16] + 80055aa: e008 b.n 80055be + 80055ac: f7fc fcbc bl 8001f28 + 80055b0: 4602 mov r2, r0 + 80055b2: 693b ldr r3, [r7, #16] + 80055b4: 1ad3 subs r3, r2, r3 + 80055b6: 2b02 cmp r3, #2 + 80055b8: d901 bls.n 80055be + 80055ba: 2303 movs r3, #3 + 80055bc: e093 b.n 80056e6 + 80055be: 4b29 ldr r3, [pc, #164] @ (8005664 ) + 80055c0: 681b ldr r3, [r3, #0] + 80055c2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80055c6: 2b00 cmp r3, #0 + 80055c8: d1f0 bne.n 80055ac + 80055ca: 687b ldr r3, [r7, #4] + 80055cc: 69da ldr r2, [r3, #28] + 80055ce: 687b ldr r3, [r7, #4] + 80055d0: 6a1b ldr r3, [r3, #32] + 80055d2: 431a orrs r2, r3 + 80055d4: 687b ldr r3, [r7, #4] + 80055d6: 6a5b ldr r3, [r3, #36] @ 0x24 + 80055d8: 019b lsls r3, r3, #6 + 80055da: 431a orrs r2, r3 + 80055dc: 687b ldr r3, [r7, #4] + 80055de: 6a9b ldr r3, [r3, #40] @ 0x28 + 80055e0: 085b lsrs r3, r3, #1 + 80055e2: 3b01 subs r3, #1 + 80055e4: 041b lsls r3, r3, #16 + 80055e6: 431a orrs r2, r3 + 80055e8: 687b ldr r3, [r7, #4] + 80055ea: 6adb ldr r3, [r3, #44] @ 0x2c + 80055ec: 061b lsls r3, r3, #24 + 80055ee: 431a orrs r2, r3 + 80055f0: 687b ldr r3, [r7, #4] + 80055f2: 6b1b ldr r3, [r3, #48] @ 0x30 + 80055f4: 071b lsls r3, r3, #28 + 80055f6: 491b ldr r1, [pc, #108] @ (8005664 ) + 80055f8: 4313 orrs r3, r2 + 80055fa: 604b str r3, [r1, #4] + 80055fc: 4b1b ldr r3, [pc, #108] @ (800566c ) + 80055fe: 2201 movs r2, #1 + 8005600: 601a str r2, [r3, #0] + 8005602: f7fc fc91 bl 8001f28 + 8005606: 6138 str r0, [r7, #16] + 8005608: e008 b.n 800561c + 800560a: f7fc fc8d bl 8001f28 + 800560e: 4602 mov r2, r0 + 8005610: 693b ldr r3, [r7, #16] + 8005612: 1ad3 subs r3, r2, r3 + 8005614: 2b02 cmp r3, #2 + 8005616: d901 bls.n 800561c + 8005618: 2303 movs r3, #3 + 800561a: e064 b.n 80056e6 + 800561c: 4b11 ldr r3, [pc, #68] @ (8005664 ) + 800561e: 681b ldr r3, [r3, #0] + 8005620: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8005624: 2b00 cmp r3, #0 + 8005626: d0f0 beq.n 800560a + 8005628: e05c b.n 80056e4 + 800562a: 4b10 ldr r3, [pc, #64] @ (800566c ) + 800562c: 2200 movs r2, #0 + 800562e: 601a str r2, [r3, #0] + 8005630: f7fc fc7a bl 8001f28 + 8005634: 6138 str r0, [r7, #16] + 8005636: e008 b.n 800564a + 8005638: f7fc fc76 bl 8001f28 + 800563c: 4602 mov r2, r0 + 800563e: 693b ldr r3, [r7, #16] + 8005640: 1ad3 subs r3, r2, r3 + 8005642: 2b02 cmp r3, #2 + 8005644: d901 bls.n 800564a + 8005646: 2303 movs r3, #3 + 8005648: e04d b.n 80056e6 + 800564a: 4b06 ldr r3, [pc, #24] @ (8005664 ) + 800564c: 681b ldr r3, [r3, #0] + 800564e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8005652: 2b00 cmp r3, #0 + 8005654: d1f0 bne.n 8005638 + 8005656: e045 b.n 80056e4 + 8005658: 687b ldr r3, [r7, #4] + 800565a: 699b ldr r3, [r3, #24] + 800565c: 2b01 cmp r3, #1 + 800565e: d107 bne.n 8005670 + 8005660: 2301 movs r3, #1 + 8005662: e040 b.n 80056e6 + 8005664: 40023800 .word 0x40023800 + 8005668: 40007000 .word 0x40007000 + 800566c: 42470060 .word 0x42470060 + 8005670: 4b1f ldr r3, [pc, #124] @ (80056f0 ) + 8005672: 685b ldr r3, [r3, #4] + 8005674: 60fb str r3, [r7, #12] + 8005676: 687b ldr r3, [r7, #4] + 8005678: 699b ldr r3, [r3, #24] + 800567a: 2b01 cmp r3, #1 + 800567c: d030 beq.n 80056e0 + 800567e: 68fb ldr r3, [r7, #12] + 8005680: f403 0280 and.w r2, r3, #4194304 @ 0x400000 + 8005684: 687b ldr r3, [r7, #4] + 8005686: 69db ldr r3, [r3, #28] + 8005688: 429a cmp r2, r3 + 800568a: d129 bne.n 80056e0 + 800568c: 68fb ldr r3, [r7, #12] + 800568e: f003 023f and.w r2, r3, #63 @ 0x3f + 8005692: 687b ldr r3, [r7, #4] + 8005694: 6a1b ldr r3, [r3, #32] + 8005696: 429a cmp r2, r3 + 8005698: d122 bne.n 80056e0 + 800569a: 68fa ldr r2, [r7, #12] + 800569c: f647 73c0 movw r3, #32704 @ 0x7fc0 + 80056a0: 4013 ands r3, r2 + 80056a2: 687a ldr r2, [r7, #4] + 80056a4: 6a52 ldr r2, [r2, #36] @ 0x24 + 80056a6: 0192 lsls r2, r2, #6 + 80056a8: 4293 cmp r3, r2 + 80056aa: d119 bne.n 80056e0 + 80056ac: 68fb ldr r3, [r7, #12] + 80056ae: f403 3240 and.w r2, r3, #196608 @ 0x30000 + 80056b2: 687b ldr r3, [r7, #4] + 80056b4: 6a9b ldr r3, [r3, #40] @ 0x28 + 80056b6: 085b lsrs r3, r3, #1 + 80056b8: 3b01 subs r3, #1 + 80056ba: 041b lsls r3, r3, #16 + 80056bc: 429a cmp r2, r3 + 80056be: d10f bne.n 80056e0 + 80056c0: 68fb ldr r3, [r7, #12] + 80056c2: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 + 80056c6: 687b ldr r3, [r7, #4] + 80056c8: 6adb ldr r3, [r3, #44] @ 0x2c + 80056ca: 061b lsls r3, r3, #24 + 80056cc: 429a cmp r2, r3 + 80056ce: d107 bne.n 80056e0 + 80056d0: 68fb ldr r3, [r7, #12] + 80056d2: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000 + 80056d6: 687b ldr r3, [r7, #4] + 80056d8: 6b1b ldr r3, [r3, #48] @ 0x30 + 80056da: 071b lsls r3, r3, #28 + 80056dc: 429a cmp r2, r3 + 80056de: d001 beq.n 80056e4 + 80056e0: 2301 movs r3, #1 + 80056e2: e000 b.n 80056e6 + 80056e4: 2300 movs r3, #0 + 80056e6: 4618 mov r0, r3 + 80056e8: 3718 adds r7, #24 + 80056ea: 46bd mov sp, r7 + 80056ec: bd80 pop {r7, pc} + 80056ee: bf00 nop + 80056f0: 40023800 .word 0x40023800 + +080056f4 : + 80056f4: b580 push {r7, lr} + 80056f6: b082 sub sp, #8 + 80056f8: af00 add r7, sp, #0 + 80056fa: 6078 str r0, [r7, #4] + 80056fc: 687b ldr r3, [r7, #4] + 80056fe: 2b00 cmp r3, #0 + 8005700: d101 bne.n 8005706 + 8005702: 2301 movs r3, #1 + 8005704: e041 b.n 800578a + 8005706: 687b ldr r3, [r7, #4] + 8005708: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 800570c: b2db uxtb r3, r3 + 800570e: 2b00 cmp r3, #0 + 8005710: d106 bne.n 8005720 + 8005712: 687b ldr r3, [r7, #4] + 8005714: 2200 movs r2, #0 + 8005716: f883 203c strb.w r2, [r3, #60] @ 0x3c + 800571a: 6878 ldr r0, [r7, #4] + 800571c: f7fb ff6a bl 80015f4 + 8005720: 687b ldr r3, [r7, #4] + 8005722: 2202 movs r2, #2 + 8005724: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8005728: 687b ldr r3, [r7, #4] + 800572a: 681a ldr r2, [r3, #0] + 800572c: 687b ldr r3, [r7, #4] + 800572e: 3304 adds r3, #4 + 8005730: 4619 mov r1, r3 + 8005732: 4610 mov r0, r2 + 8005734: f000 fba0 bl 8005e78 + 8005738: 687b ldr r3, [r7, #4] + 800573a: 2201 movs r2, #1 + 800573c: f883 2046 strb.w r2, [r3, #70] @ 0x46 + 8005740: 687b ldr r3, [r7, #4] + 8005742: 2201 movs r2, #1 + 8005744: f883 203e strb.w r2, [r3, #62] @ 0x3e + 8005748: 687b ldr r3, [r7, #4] + 800574a: 2201 movs r2, #1 + 800574c: f883 203f strb.w r2, [r3, #63] @ 0x3f + 8005750: 687b ldr r3, [r7, #4] + 8005752: 2201 movs r2, #1 + 8005754: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 8005758: 687b ldr r3, [r7, #4] + 800575a: 2201 movs r2, #1 + 800575c: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 8005760: 687b ldr r3, [r7, #4] + 8005762: 2201 movs r2, #1 + 8005764: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8005768: 687b ldr r3, [r7, #4] + 800576a: 2201 movs r2, #1 + 800576c: f883 2043 strb.w r2, [r3, #67] @ 0x43 + 8005770: 687b ldr r3, [r7, #4] + 8005772: 2201 movs r2, #1 + 8005774: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 8005778: 687b ldr r3, [r7, #4] + 800577a: 2201 movs r2, #1 + 800577c: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 8005780: 687b ldr r3, [r7, #4] + 8005782: 2201 movs r2, #1 + 8005784: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8005788: 2300 movs r3, #0 + 800578a: 4618 mov r0, r3 + 800578c: 3708 adds r7, #8 + 800578e: 46bd mov sp, r7 + 8005790: bd80 pop {r7, pc} + +08005792 : + 8005792: b580 push {r7, lr} + 8005794: b082 sub sp, #8 + 8005796: af00 add r7, sp, #0 + 8005798: 6078 str r0, [r7, #4] + 800579a: 687b ldr r3, [r7, #4] + 800579c: 2b00 cmp r3, #0 + 800579e: d101 bne.n 80057a4 + 80057a0: 2301 movs r3, #1 + 80057a2: e041 b.n 8005828 + 80057a4: 687b ldr r3, [r7, #4] + 80057a6: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 80057aa: b2db uxtb r3, r3 + 80057ac: 2b00 cmp r3, #0 + 80057ae: d106 bne.n 80057be + 80057b0: 687b ldr r3, [r7, #4] + 80057b2: 2200 movs r2, #0 + 80057b4: f883 203c strb.w r2, [r3, #60] @ 0x3c + 80057b8: 6878 ldr r0, [r7, #4] + 80057ba: f000 f839 bl 8005830 + 80057be: 687b ldr r3, [r7, #4] + 80057c0: 2202 movs r2, #2 + 80057c2: f883 203d strb.w r2, [r3, #61] @ 0x3d + 80057c6: 687b ldr r3, [r7, #4] + 80057c8: 681a ldr r2, [r3, #0] + 80057ca: 687b ldr r3, [r7, #4] + 80057cc: 3304 adds r3, #4 + 80057ce: 4619 mov r1, r3 + 80057d0: 4610 mov r0, r2 + 80057d2: f000 fb51 bl 8005e78 + 80057d6: 687b ldr r3, [r7, #4] + 80057d8: 2201 movs r2, #1 + 80057da: f883 2046 strb.w r2, [r3, #70] @ 0x46 + 80057de: 687b ldr r3, [r7, #4] + 80057e0: 2201 movs r2, #1 + 80057e2: f883 203e strb.w r2, [r3, #62] @ 0x3e + 80057e6: 687b ldr r3, [r7, #4] + 80057e8: 2201 movs r2, #1 + 80057ea: f883 203f strb.w r2, [r3, #63] @ 0x3f + 80057ee: 687b ldr r3, [r7, #4] + 80057f0: 2201 movs r2, #1 + 80057f2: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 80057f6: 687b ldr r3, [r7, #4] + 80057f8: 2201 movs r2, #1 + 80057fa: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 80057fe: 687b ldr r3, [r7, #4] + 8005800: 2201 movs r2, #1 + 8005802: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8005806: 687b ldr r3, [r7, #4] + 8005808: 2201 movs r2, #1 + 800580a: f883 2043 strb.w r2, [r3, #67] @ 0x43 + 800580e: 687b ldr r3, [r7, #4] + 8005810: 2201 movs r2, #1 + 8005812: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 8005816: 687b ldr r3, [r7, #4] + 8005818: 2201 movs r2, #1 + 800581a: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 800581e: 687b ldr r3, [r7, #4] + 8005820: 2201 movs r2, #1 + 8005822: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8005826: 2300 movs r3, #0 + 8005828: 4618 mov r0, r3 + 800582a: 3708 adds r7, #8 + 800582c: 46bd mov sp, r7 + 800582e: bd80 pop {r7, pc} + +08005830 : + 8005830: b480 push {r7} + 8005832: b083 sub sp, #12 + 8005834: af00 add r7, sp, #0 + 8005836: 6078 str r0, [r7, #4] + 8005838: bf00 nop + 800583a: 370c adds r7, #12 + 800583c: 46bd mov sp, r7 + 800583e: f85d 7b04 ldr.w r7, [sp], #4 + 8005842: 4770 bx lr + +08005844 : + 8005844: b580 push {r7, lr} + 8005846: b084 sub sp, #16 + 8005848: af00 add r7, sp, #0 + 800584a: 6078 str r0, [r7, #4] + 800584c: 6039 str r1, [r7, #0] + 800584e: 683b ldr r3, [r7, #0] + 8005850: 2b00 cmp r3, #0 + 8005852: d109 bne.n 8005868 + 8005854: 687b ldr r3, [r7, #4] + 8005856: f893 303e ldrb.w r3, [r3, #62] @ 0x3e + 800585a: b2db uxtb r3, r3 + 800585c: 2b01 cmp r3, #1 + 800585e: bf14 ite ne + 8005860: 2301 movne r3, #1 + 8005862: 2300 moveq r3, #0 + 8005864: b2db uxtb r3, r3 + 8005866: e022 b.n 80058ae + 8005868: 683b ldr r3, [r7, #0] + 800586a: 2b04 cmp r3, #4 + 800586c: d109 bne.n 8005882 + 800586e: 687b ldr r3, [r7, #4] + 8005870: f893 303f ldrb.w r3, [r3, #63] @ 0x3f + 8005874: b2db uxtb r3, r3 + 8005876: 2b01 cmp r3, #1 + 8005878: bf14 ite ne + 800587a: 2301 movne r3, #1 + 800587c: 2300 moveq r3, #0 + 800587e: b2db uxtb r3, r3 + 8005880: e015 b.n 80058ae + 8005882: 683b ldr r3, [r7, #0] + 8005884: 2b08 cmp r3, #8 + 8005886: d109 bne.n 800589c + 8005888: 687b ldr r3, [r7, #4] + 800588a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 + 800588e: b2db uxtb r3, r3 + 8005890: 2b01 cmp r3, #1 + 8005892: bf14 ite ne + 8005894: 2301 movne r3, #1 + 8005896: 2300 moveq r3, #0 + 8005898: b2db uxtb r3, r3 + 800589a: e008 b.n 80058ae + 800589c: 687b ldr r3, [r7, #4] + 800589e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 80058a2: b2db uxtb r3, r3 + 80058a4: 2b01 cmp r3, #1 + 80058a6: bf14 ite ne + 80058a8: 2301 movne r3, #1 + 80058aa: 2300 moveq r3, #0 + 80058ac: b2db uxtb r3, r3 + 80058ae: 2b00 cmp r3, #0 + 80058b0: d001 beq.n 80058b6 + 80058b2: 2301 movs r3, #1 + 80058b4: e07c b.n 80059b0 + 80058b6: 683b ldr r3, [r7, #0] + 80058b8: 2b00 cmp r3, #0 + 80058ba: d104 bne.n 80058c6 + 80058bc: 687b ldr r3, [r7, #4] + 80058be: 2202 movs r2, #2 + 80058c0: f883 203e strb.w r2, [r3, #62] @ 0x3e + 80058c4: e013 b.n 80058ee + 80058c6: 683b ldr r3, [r7, #0] + 80058c8: 2b04 cmp r3, #4 + 80058ca: d104 bne.n 80058d6 + 80058cc: 687b ldr r3, [r7, #4] + 80058ce: 2202 movs r2, #2 + 80058d0: f883 203f strb.w r2, [r3, #63] @ 0x3f + 80058d4: e00b b.n 80058ee + 80058d6: 683b ldr r3, [r7, #0] + 80058d8: 2b08 cmp r3, #8 + 80058da: d104 bne.n 80058e6 + 80058dc: 687b ldr r3, [r7, #4] + 80058de: 2202 movs r2, #2 + 80058e0: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 80058e4: e003 b.n 80058ee + 80058e6: 687b ldr r3, [r7, #4] + 80058e8: 2202 movs r2, #2 + 80058ea: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 80058ee: 687b ldr r3, [r7, #4] + 80058f0: 681b ldr r3, [r3, #0] + 80058f2: 2201 movs r2, #1 + 80058f4: 6839 ldr r1, [r7, #0] + 80058f6: 4618 mov r0, r3 + 80058f8: f000 fd14 bl 8006324 + 80058fc: 687b ldr r3, [r7, #4] + 80058fe: 681b ldr r3, [r3, #0] + 8005900: 4a2d ldr r2, [pc, #180] @ (80059b8 ) + 8005902: 4293 cmp r3, r2 + 8005904: d004 beq.n 8005910 + 8005906: 687b ldr r3, [r7, #4] + 8005908: 681b ldr r3, [r3, #0] + 800590a: 4a2c ldr r2, [pc, #176] @ (80059bc ) + 800590c: 4293 cmp r3, r2 + 800590e: d101 bne.n 8005914 + 8005910: 2301 movs r3, #1 + 8005912: e000 b.n 8005916 + 8005914: 2300 movs r3, #0 + 8005916: 2b00 cmp r3, #0 + 8005918: d007 beq.n 800592a + 800591a: 687b ldr r3, [r7, #4] + 800591c: 681b ldr r3, [r3, #0] + 800591e: 6c5a ldr r2, [r3, #68] @ 0x44 + 8005920: 687b ldr r3, [r7, #4] + 8005922: 681b ldr r3, [r3, #0] + 8005924: f442 4200 orr.w r2, r2, #32768 @ 0x8000 + 8005928: 645a str r2, [r3, #68] @ 0x44 + 800592a: 687b ldr r3, [r7, #4] + 800592c: 681b ldr r3, [r3, #0] + 800592e: 4a22 ldr r2, [pc, #136] @ (80059b8 ) + 8005930: 4293 cmp r3, r2 + 8005932: d022 beq.n 800597a + 8005934: 687b ldr r3, [r7, #4] + 8005936: 681b ldr r3, [r3, #0] + 8005938: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 800593c: d01d beq.n 800597a + 800593e: 687b ldr r3, [r7, #4] + 8005940: 681b ldr r3, [r3, #0] + 8005942: 4a1f ldr r2, [pc, #124] @ (80059c0 ) + 8005944: 4293 cmp r3, r2 + 8005946: d018 beq.n 800597a + 8005948: 687b ldr r3, [r7, #4] + 800594a: 681b ldr r3, [r3, #0] + 800594c: 4a1d ldr r2, [pc, #116] @ (80059c4 ) + 800594e: 4293 cmp r3, r2 + 8005950: d013 beq.n 800597a + 8005952: 687b ldr r3, [r7, #4] + 8005954: 681b ldr r3, [r3, #0] + 8005956: 4a1c ldr r2, [pc, #112] @ (80059c8 ) + 8005958: 4293 cmp r3, r2 + 800595a: d00e beq.n 800597a + 800595c: 687b ldr r3, [r7, #4] + 800595e: 681b ldr r3, [r3, #0] + 8005960: 4a16 ldr r2, [pc, #88] @ (80059bc ) + 8005962: 4293 cmp r3, r2 + 8005964: d009 beq.n 800597a + 8005966: 687b ldr r3, [r7, #4] + 8005968: 681b ldr r3, [r3, #0] + 800596a: 4a18 ldr r2, [pc, #96] @ (80059cc ) + 800596c: 4293 cmp r3, r2 + 800596e: d004 beq.n 800597a + 8005970: 687b ldr r3, [r7, #4] + 8005972: 681b ldr r3, [r3, #0] + 8005974: 4a16 ldr r2, [pc, #88] @ (80059d0 ) + 8005976: 4293 cmp r3, r2 + 8005978: d111 bne.n 800599e + 800597a: 687b ldr r3, [r7, #4] + 800597c: 681b ldr r3, [r3, #0] + 800597e: 689b ldr r3, [r3, #8] + 8005980: f003 0307 and.w r3, r3, #7 + 8005984: 60fb str r3, [r7, #12] + 8005986: 68fb ldr r3, [r7, #12] + 8005988: 2b06 cmp r3, #6 + 800598a: d010 beq.n 80059ae + 800598c: 687b ldr r3, [r7, #4] + 800598e: 681b ldr r3, [r3, #0] + 8005990: 681a ldr r2, [r3, #0] + 8005992: 687b ldr r3, [r7, #4] + 8005994: 681b ldr r3, [r3, #0] + 8005996: f042 0201 orr.w r2, r2, #1 + 800599a: 601a str r2, [r3, #0] + 800599c: e007 b.n 80059ae + 800599e: 687b ldr r3, [r7, #4] + 80059a0: 681b ldr r3, [r3, #0] + 80059a2: 681a ldr r2, [r3, #0] + 80059a4: 687b ldr r3, [r7, #4] + 80059a6: 681b ldr r3, [r3, #0] + 80059a8: f042 0201 orr.w r2, r2, #1 + 80059ac: 601a str r2, [r3, #0] + 80059ae: 2300 movs r3, #0 + 80059b0: 4618 mov r0, r3 + 80059b2: 3710 adds r7, #16 + 80059b4: 46bd mov sp, r7 + 80059b6: bd80 pop {r7, pc} + 80059b8: 40010000 .word 0x40010000 + 80059bc: 40010400 .word 0x40010400 + 80059c0: 40000400 .word 0x40000400 + 80059c4: 40000800 .word 0x40000800 + 80059c8: 40000c00 .word 0x40000c00 + 80059cc: 40014000 .word 0x40014000 + 80059d0: 40001800 .word 0x40001800 + +080059d4 : + 80059d4: b580 push {r7, lr} + 80059d6: b086 sub sp, #24 + 80059d8: af00 add r7, sp, #0 + 80059da: 6078 str r0, [r7, #4] + 80059dc: 6039 str r1, [r7, #0] + 80059de: 687b ldr r3, [r7, #4] + 80059e0: 2b00 cmp r3, #0 + 80059e2: d101 bne.n 80059e8 + 80059e4: 2301 movs r3, #1 + 80059e6: e097 b.n 8005b18 + 80059e8: 687b ldr r3, [r7, #4] + 80059ea: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 80059ee: b2db uxtb r3, r3 + 80059f0: 2b00 cmp r3, #0 + 80059f2: d106 bne.n 8005a02 + 80059f4: 687b ldr r3, [r7, #4] + 80059f6: 2200 movs r2, #0 + 80059f8: f883 203c strb.w r2, [r3, #60] @ 0x3c + 80059fc: 6878 ldr r0, [r7, #4] + 80059fe: f7fb fe19 bl 8001634 + 8005a02: 687b ldr r3, [r7, #4] + 8005a04: 2202 movs r2, #2 + 8005a06: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8005a0a: 687b ldr r3, [r7, #4] + 8005a0c: 681b ldr r3, [r3, #0] + 8005a0e: 689b ldr r3, [r3, #8] + 8005a10: 687a ldr r2, [r7, #4] + 8005a12: 6812 ldr r2, [r2, #0] + 8005a14: f423 4380 bic.w r3, r3, #16384 @ 0x4000 + 8005a18: f023 0307 bic.w r3, r3, #7 + 8005a1c: 6093 str r3, [r2, #8] + 8005a1e: 687b ldr r3, [r7, #4] + 8005a20: 681a ldr r2, [r3, #0] + 8005a22: 687b ldr r3, [r7, #4] + 8005a24: 3304 adds r3, #4 + 8005a26: 4619 mov r1, r3 + 8005a28: 4610 mov r0, r2 + 8005a2a: f000 fa25 bl 8005e78 + 8005a2e: 687b ldr r3, [r7, #4] + 8005a30: 681b ldr r3, [r3, #0] + 8005a32: 689b ldr r3, [r3, #8] + 8005a34: 617b str r3, [r7, #20] + 8005a36: 687b ldr r3, [r7, #4] + 8005a38: 681b ldr r3, [r3, #0] + 8005a3a: 699b ldr r3, [r3, #24] + 8005a3c: 613b str r3, [r7, #16] + 8005a3e: 687b ldr r3, [r7, #4] + 8005a40: 681b ldr r3, [r3, #0] + 8005a42: 6a1b ldr r3, [r3, #32] + 8005a44: 60fb str r3, [r7, #12] + 8005a46: 683b ldr r3, [r7, #0] + 8005a48: 681b ldr r3, [r3, #0] + 8005a4a: 697a ldr r2, [r7, #20] + 8005a4c: 4313 orrs r3, r2 + 8005a4e: 617b str r3, [r7, #20] + 8005a50: 693b ldr r3, [r7, #16] + 8005a52: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8005a56: f023 0303 bic.w r3, r3, #3 + 8005a5a: 613b str r3, [r7, #16] + 8005a5c: 683b ldr r3, [r7, #0] + 8005a5e: 689a ldr r2, [r3, #8] + 8005a60: 683b ldr r3, [r7, #0] + 8005a62: 699b ldr r3, [r3, #24] + 8005a64: 021b lsls r3, r3, #8 + 8005a66: 4313 orrs r3, r2 + 8005a68: 693a ldr r2, [r7, #16] + 8005a6a: 4313 orrs r3, r2 + 8005a6c: 613b str r3, [r7, #16] + 8005a6e: 693b ldr r3, [r7, #16] + 8005a70: f423 6340 bic.w r3, r3, #3072 @ 0xc00 + 8005a74: f023 030c bic.w r3, r3, #12 + 8005a78: 613b str r3, [r7, #16] + 8005a7a: 693b ldr r3, [r7, #16] + 8005a7c: f423 4370 bic.w r3, r3, #61440 @ 0xf000 + 8005a80: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 8005a84: 613b str r3, [r7, #16] + 8005a86: 683b ldr r3, [r7, #0] + 8005a88: 68da ldr r2, [r3, #12] + 8005a8a: 683b ldr r3, [r7, #0] + 8005a8c: 69db ldr r3, [r3, #28] + 8005a8e: 021b lsls r3, r3, #8 + 8005a90: 4313 orrs r3, r2 + 8005a92: 693a ldr r2, [r7, #16] + 8005a94: 4313 orrs r3, r2 + 8005a96: 613b str r3, [r7, #16] + 8005a98: 683b ldr r3, [r7, #0] + 8005a9a: 691b ldr r3, [r3, #16] + 8005a9c: 011a lsls r2, r3, #4 + 8005a9e: 683b ldr r3, [r7, #0] + 8005aa0: 6a1b ldr r3, [r3, #32] + 8005aa2: 031b lsls r3, r3, #12 + 8005aa4: 4313 orrs r3, r2 + 8005aa6: 693a ldr r2, [r7, #16] + 8005aa8: 4313 orrs r3, r2 + 8005aaa: 613b str r3, [r7, #16] + 8005aac: 68fb ldr r3, [r7, #12] + 8005aae: f023 0322 bic.w r3, r3, #34 @ 0x22 + 8005ab2: 60fb str r3, [r7, #12] + 8005ab4: 68fb ldr r3, [r7, #12] + 8005ab6: f023 0388 bic.w r3, r3, #136 @ 0x88 + 8005aba: 60fb str r3, [r7, #12] + 8005abc: 683b ldr r3, [r7, #0] + 8005abe: 685a ldr r2, [r3, #4] + 8005ac0: 683b ldr r3, [r7, #0] + 8005ac2: 695b ldr r3, [r3, #20] + 8005ac4: 011b lsls r3, r3, #4 + 8005ac6: 4313 orrs r3, r2 + 8005ac8: 68fa ldr r2, [r7, #12] + 8005aca: 4313 orrs r3, r2 + 8005acc: 60fb str r3, [r7, #12] + 8005ace: 687b ldr r3, [r7, #4] + 8005ad0: 681b ldr r3, [r3, #0] + 8005ad2: 697a ldr r2, [r7, #20] + 8005ad4: 609a str r2, [r3, #8] + 8005ad6: 687b ldr r3, [r7, #4] + 8005ad8: 681b ldr r3, [r3, #0] + 8005ada: 693a ldr r2, [r7, #16] + 8005adc: 619a str r2, [r3, #24] + 8005ade: 687b ldr r3, [r7, #4] + 8005ae0: 681b ldr r3, [r3, #0] + 8005ae2: 68fa ldr r2, [r7, #12] + 8005ae4: 621a str r2, [r3, #32] + 8005ae6: 687b ldr r3, [r7, #4] + 8005ae8: 2201 movs r2, #1 + 8005aea: f883 2046 strb.w r2, [r3, #70] @ 0x46 + 8005aee: 687b ldr r3, [r7, #4] + 8005af0: 2201 movs r2, #1 + 8005af2: f883 203e strb.w r2, [r3, #62] @ 0x3e + 8005af6: 687b ldr r3, [r7, #4] + 8005af8: 2201 movs r2, #1 + 8005afa: f883 203f strb.w r2, [r3, #63] @ 0x3f + 8005afe: 687b ldr r3, [r7, #4] + 8005b00: 2201 movs r2, #1 + 8005b02: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8005b06: 687b ldr r3, [r7, #4] + 8005b08: 2201 movs r2, #1 + 8005b0a: f883 2043 strb.w r2, [r3, #67] @ 0x43 + 8005b0e: 687b ldr r3, [r7, #4] + 8005b10: 2201 movs r2, #1 + 8005b12: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8005b16: 2300 movs r3, #0 + 8005b18: 4618 mov r0, r3 + 8005b1a: 3718 adds r7, #24 + 8005b1c: 46bd mov sp, r7 + 8005b1e: bd80 pop {r7, pc} + +08005b20 : + 8005b20: b580 push {r7, lr} + 8005b22: b084 sub sp, #16 + 8005b24: af00 add r7, sp, #0 + 8005b26: 6078 str r0, [r7, #4] + 8005b28: 6039 str r1, [r7, #0] + 8005b2a: 687b ldr r3, [r7, #4] + 8005b2c: f893 303e ldrb.w r3, [r3, #62] @ 0x3e + 8005b30: 73fb strb r3, [r7, #15] + 8005b32: 687b ldr r3, [r7, #4] + 8005b34: f893 303f ldrb.w r3, [r3, #63] @ 0x3f + 8005b38: 73bb strb r3, [r7, #14] + 8005b3a: 687b ldr r3, [r7, #4] + 8005b3c: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 + 8005b40: 737b strb r3, [r7, #13] + 8005b42: 687b ldr r3, [r7, #4] + 8005b44: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 + 8005b48: 733b strb r3, [r7, #12] + 8005b4a: 683b ldr r3, [r7, #0] + 8005b4c: 2b00 cmp r3, #0 + 8005b4e: d110 bne.n 8005b72 + 8005b50: 7bfb ldrb r3, [r7, #15] + 8005b52: 2b01 cmp r3, #1 + 8005b54: d102 bne.n 8005b5c + 8005b56: 7b7b ldrb r3, [r7, #13] + 8005b58: 2b01 cmp r3, #1 + 8005b5a: d001 beq.n 8005b60 + 8005b5c: 2301 movs r3, #1 + 8005b5e: e069 b.n 8005c34 + 8005b60: 687b ldr r3, [r7, #4] + 8005b62: 2202 movs r2, #2 + 8005b64: f883 203e strb.w r2, [r3, #62] @ 0x3e + 8005b68: 687b ldr r3, [r7, #4] + 8005b6a: 2202 movs r2, #2 + 8005b6c: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8005b70: e031 b.n 8005bd6 + 8005b72: 683b ldr r3, [r7, #0] + 8005b74: 2b04 cmp r3, #4 + 8005b76: d110 bne.n 8005b9a + 8005b78: 7bbb ldrb r3, [r7, #14] + 8005b7a: 2b01 cmp r3, #1 + 8005b7c: d102 bne.n 8005b84 + 8005b7e: 7b3b ldrb r3, [r7, #12] + 8005b80: 2b01 cmp r3, #1 + 8005b82: d001 beq.n 8005b88 + 8005b84: 2301 movs r3, #1 + 8005b86: e055 b.n 8005c34 + 8005b88: 687b ldr r3, [r7, #4] + 8005b8a: 2202 movs r2, #2 + 8005b8c: f883 203f strb.w r2, [r3, #63] @ 0x3f + 8005b90: 687b ldr r3, [r7, #4] + 8005b92: 2202 movs r2, #2 + 8005b94: f883 2043 strb.w r2, [r3, #67] @ 0x43 + 8005b98: e01d b.n 8005bd6 + 8005b9a: 7bfb ldrb r3, [r7, #15] + 8005b9c: 2b01 cmp r3, #1 + 8005b9e: d108 bne.n 8005bb2 + 8005ba0: 7bbb ldrb r3, [r7, #14] + 8005ba2: 2b01 cmp r3, #1 + 8005ba4: d105 bne.n 8005bb2 + 8005ba6: 7b7b ldrb r3, [r7, #13] + 8005ba8: 2b01 cmp r3, #1 + 8005baa: d102 bne.n 8005bb2 + 8005bac: 7b3b ldrb r3, [r7, #12] + 8005bae: 2b01 cmp r3, #1 + 8005bb0: d001 beq.n 8005bb6 + 8005bb2: 2301 movs r3, #1 + 8005bb4: e03e b.n 8005c34 + 8005bb6: 687b ldr r3, [r7, #4] + 8005bb8: 2202 movs r2, #2 + 8005bba: f883 203e strb.w r2, [r3, #62] @ 0x3e + 8005bbe: 687b ldr r3, [r7, #4] + 8005bc0: 2202 movs r2, #2 + 8005bc2: f883 203f strb.w r2, [r3, #63] @ 0x3f + 8005bc6: 687b ldr r3, [r7, #4] + 8005bc8: 2202 movs r2, #2 + 8005bca: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8005bce: 687b ldr r3, [r7, #4] + 8005bd0: 2202 movs r2, #2 + 8005bd2: f883 2043 strb.w r2, [r3, #67] @ 0x43 + 8005bd6: 683b ldr r3, [r7, #0] + 8005bd8: 2b00 cmp r3, #0 + 8005bda: d003 beq.n 8005be4 + 8005bdc: 683b ldr r3, [r7, #0] + 8005bde: 2b04 cmp r3, #4 + 8005be0: d008 beq.n 8005bf4 + 8005be2: e00f b.n 8005c04 + 8005be4: 687b ldr r3, [r7, #4] + 8005be6: 681b ldr r3, [r3, #0] + 8005be8: 2201 movs r2, #1 + 8005bea: 2100 movs r1, #0 + 8005bec: 4618 mov r0, r3 + 8005bee: f000 fb99 bl 8006324 + 8005bf2: e016 b.n 8005c22 + 8005bf4: 687b ldr r3, [r7, #4] + 8005bf6: 681b ldr r3, [r3, #0] + 8005bf8: 2201 movs r2, #1 + 8005bfa: 2104 movs r1, #4 + 8005bfc: 4618 mov r0, r3 + 8005bfe: f000 fb91 bl 8006324 + 8005c02: e00e b.n 8005c22 + 8005c04: 687b ldr r3, [r7, #4] + 8005c06: 681b ldr r3, [r3, #0] + 8005c08: 2201 movs r2, #1 + 8005c0a: 2100 movs r1, #0 + 8005c0c: 4618 mov r0, r3 + 8005c0e: f000 fb89 bl 8006324 + 8005c12: 687b ldr r3, [r7, #4] + 8005c14: 681b ldr r3, [r3, #0] + 8005c16: 2201 movs r2, #1 + 8005c18: 2104 movs r1, #4 + 8005c1a: 4618 mov r0, r3 + 8005c1c: f000 fb82 bl 8006324 + 8005c20: bf00 nop + 8005c22: 687b ldr r3, [r7, #4] + 8005c24: 681b ldr r3, [r3, #0] + 8005c26: 681a ldr r2, [r3, #0] + 8005c28: 687b ldr r3, [r7, #4] + 8005c2a: 681b ldr r3, [r3, #0] + 8005c2c: f042 0201 orr.w r2, r2, #1 + 8005c30: 601a str r2, [r3, #0] + 8005c32: 2300 movs r3, #0 + 8005c34: 4618 mov r0, r3 + 8005c36: 3710 adds r7, #16 + 8005c38: 46bd mov sp, r7 + 8005c3a: bd80 pop {r7, pc} + +08005c3c : + 8005c3c: b580 push {r7, lr} + 8005c3e: b086 sub sp, #24 + 8005c40: af00 add r7, sp, #0 + 8005c42: 60f8 str r0, [r7, #12] + 8005c44: 60b9 str r1, [r7, #8] + 8005c46: 607a str r2, [r7, #4] + 8005c48: 2300 movs r3, #0 + 8005c4a: 75fb strb r3, [r7, #23] + 8005c4c: 68fb ldr r3, [r7, #12] + 8005c4e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8005c52: 2b01 cmp r3, #1 + 8005c54: d101 bne.n 8005c5a + 8005c56: 2302 movs r3, #2 + 8005c58: e048 b.n 8005cec + 8005c5a: 68fb ldr r3, [r7, #12] + 8005c5c: 2201 movs r2, #1 + 8005c5e: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8005c62: 687b ldr r3, [r7, #4] + 8005c64: 2b0c cmp r3, #12 + 8005c66: d839 bhi.n 8005cdc + 8005c68: a201 add r2, pc, #4 @ (adr r2, 8005c70 ) + 8005c6a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005c6e: bf00 nop + 8005c70: 08005ca5 .word 0x08005ca5 + 8005c74: 08005cdd .word 0x08005cdd + 8005c78: 08005cdd .word 0x08005cdd + 8005c7c: 08005cdd .word 0x08005cdd + 8005c80: 08005cb3 .word 0x08005cb3 + 8005c84: 08005cdd .word 0x08005cdd + 8005c88: 08005cdd .word 0x08005cdd + 8005c8c: 08005cdd .word 0x08005cdd + 8005c90: 08005cc1 .word 0x08005cc1 + 8005c94: 08005cdd .word 0x08005cdd + 8005c98: 08005cdd .word 0x08005cdd + 8005c9c: 08005cdd .word 0x08005cdd + 8005ca0: 08005ccf .word 0x08005ccf + 8005ca4: 68fb ldr r3, [r7, #12] + 8005ca6: 681b ldr r3, [r3, #0] + 8005ca8: 68b9 ldr r1, [r7, #8] + 8005caa: 4618 mov r0, r3 + 8005cac: f000 f98a bl 8005fc4 + 8005cb0: e017 b.n 8005ce2 + 8005cb2: 68fb ldr r3, [r7, #12] + 8005cb4: 681b ldr r3, [r3, #0] + 8005cb6: 68b9 ldr r1, [r7, #8] + 8005cb8: 4618 mov r0, r3 + 8005cba: f000 f9f3 bl 80060a4 + 8005cbe: e010 b.n 8005ce2 + 8005cc0: 68fb ldr r3, [r7, #12] + 8005cc2: 681b ldr r3, [r3, #0] + 8005cc4: 68b9 ldr r1, [r7, #8] + 8005cc6: 4618 mov r0, r3 + 8005cc8: f000 fa62 bl 8006190 + 8005ccc: e009 b.n 8005ce2 + 8005cce: 68fb ldr r3, [r7, #12] + 8005cd0: 681b ldr r3, [r3, #0] + 8005cd2: 68b9 ldr r1, [r7, #8] + 8005cd4: 4618 mov r0, r3 + 8005cd6: f000 facf bl 8006278 + 8005cda: e002 b.n 8005ce2 + 8005cdc: 2301 movs r3, #1 + 8005cde: 75fb strb r3, [r7, #23] + 8005ce0: bf00 nop + 8005ce2: 68fb ldr r3, [r7, #12] + 8005ce4: 2200 movs r2, #0 + 8005ce6: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8005cea: 7dfb ldrb r3, [r7, #23] + 8005cec: 4618 mov r0, r3 + 8005cee: 3718 adds r7, #24 + 8005cf0: 46bd mov sp, r7 + 8005cf2: bd80 pop {r7, pc} + +08005cf4 : + 8005cf4: b580 push {r7, lr} + 8005cf6: b086 sub sp, #24 + 8005cf8: af00 add r7, sp, #0 + 8005cfa: 60f8 str r0, [r7, #12] + 8005cfc: 60b9 str r1, [r7, #8] + 8005cfe: 607a str r2, [r7, #4] + 8005d00: 2300 movs r3, #0 + 8005d02: 75fb strb r3, [r7, #23] + 8005d04: 68fb ldr r3, [r7, #12] + 8005d06: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8005d0a: 2b01 cmp r3, #1 + 8005d0c: d101 bne.n 8005d12 + 8005d0e: 2302 movs r3, #2 + 8005d10: e0ae b.n 8005e70 + 8005d12: 68fb ldr r3, [r7, #12] + 8005d14: 2201 movs r2, #1 + 8005d16: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8005d1a: 687b ldr r3, [r7, #4] + 8005d1c: 2b0c cmp r3, #12 + 8005d1e: f200 809f bhi.w 8005e60 + 8005d22: a201 add r2, pc, #4 @ (adr r2, 8005d28 ) + 8005d24: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005d28: 08005d5d .word 0x08005d5d + 8005d2c: 08005e61 .word 0x08005e61 + 8005d30: 08005e61 .word 0x08005e61 + 8005d34: 08005e61 .word 0x08005e61 + 8005d38: 08005d9d .word 0x08005d9d + 8005d3c: 08005e61 .word 0x08005e61 + 8005d40: 08005e61 .word 0x08005e61 + 8005d44: 08005e61 .word 0x08005e61 + 8005d48: 08005ddf .word 0x08005ddf + 8005d4c: 08005e61 .word 0x08005e61 + 8005d50: 08005e61 .word 0x08005e61 + 8005d54: 08005e61 .word 0x08005e61 + 8005d58: 08005e1f .word 0x08005e1f + 8005d5c: 68fb ldr r3, [r7, #12] + 8005d5e: 681b ldr r3, [r3, #0] + 8005d60: 68b9 ldr r1, [r7, #8] + 8005d62: 4618 mov r0, r3 + 8005d64: f000 f92e bl 8005fc4 + 8005d68: 68fb ldr r3, [r7, #12] + 8005d6a: 681b ldr r3, [r3, #0] + 8005d6c: 699a ldr r2, [r3, #24] + 8005d6e: 68fb ldr r3, [r7, #12] + 8005d70: 681b ldr r3, [r3, #0] + 8005d72: f042 0208 orr.w r2, r2, #8 + 8005d76: 619a str r2, [r3, #24] + 8005d78: 68fb ldr r3, [r7, #12] + 8005d7a: 681b ldr r3, [r3, #0] + 8005d7c: 699a ldr r2, [r3, #24] + 8005d7e: 68fb ldr r3, [r7, #12] + 8005d80: 681b ldr r3, [r3, #0] + 8005d82: f022 0204 bic.w r2, r2, #4 + 8005d86: 619a str r2, [r3, #24] + 8005d88: 68fb ldr r3, [r7, #12] + 8005d8a: 681b ldr r3, [r3, #0] + 8005d8c: 6999 ldr r1, [r3, #24] + 8005d8e: 68bb ldr r3, [r7, #8] + 8005d90: 691a ldr r2, [r3, #16] + 8005d92: 68fb ldr r3, [r7, #12] + 8005d94: 681b ldr r3, [r3, #0] + 8005d96: 430a orrs r2, r1 + 8005d98: 619a str r2, [r3, #24] + 8005d9a: e064 b.n 8005e66 + 8005d9c: 68fb ldr r3, [r7, #12] + 8005d9e: 681b ldr r3, [r3, #0] + 8005da0: 68b9 ldr r1, [r7, #8] + 8005da2: 4618 mov r0, r3 + 8005da4: f000 f97e bl 80060a4 + 8005da8: 68fb ldr r3, [r7, #12] + 8005daa: 681b ldr r3, [r3, #0] + 8005dac: 699a ldr r2, [r3, #24] + 8005dae: 68fb ldr r3, [r7, #12] + 8005db0: 681b ldr r3, [r3, #0] + 8005db2: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 8005db6: 619a str r2, [r3, #24] + 8005db8: 68fb ldr r3, [r7, #12] + 8005dba: 681b ldr r3, [r3, #0] + 8005dbc: 699a ldr r2, [r3, #24] + 8005dbe: 68fb ldr r3, [r7, #12] + 8005dc0: 681b ldr r3, [r3, #0] + 8005dc2: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8005dc6: 619a str r2, [r3, #24] + 8005dc8: 68fb ldr r3, [r7, #12] + 8005dca: 681b ldr r3, [r3, #0] + 8005dcc: 6999 ldr r1, [r3, #24] + 8005dce: 68bb ldr r3, [r7, #8] + 8005dd0: 691b ldr r3, [r3, #16] + 8005dd2: 021a lsls r2, r3, #8 + 8005dd4: 68fb ldr r3, [r7, #12] + 8005dd6: 681b ldr r3, [r3, #0] + 8005dd8: 430a orrs r2, r1 + 8005dda: 619a str r2, [r3, #24] + 8005ddc: e043 b.n 8005e66 + 8005dde: 68fb ldr r3, [r7, #12] + 8005de0: 681b ldr r3, [r3, #0] + 8005de2: 68b9 ldr r1, [r7, #8] + 8005de4: 4618 mov r0, r3 + 8005de6: f000 f9d3 bl 8006190 + 8005dea: 68fb ldr r3, [r7, #12] + 8005dec: 681b ldr r3, [r3, #0] + 8005dee: 69da ldr r2, [r3, #28] + 8005df0: 68fb ldr r3, [r7, #12] + 8005df2: 681b ldr r3, [r3, #0] + 8005df4: f042 0208 orr.w r2, r2, #8 + 8005df8: 61da str r2, [r3, #28] + 8005dfa: 68fb ldr r3, [r7, #12] + 8005dfc: 681b ldr r3, [r3, #0] + 8005dfe: 69da ldr r2, [r3, #28] + 8005e00: 68fb ldr r3, [r7, #12] + 8005e02: 681b ldr r3, [r3, #0] + 8005e04: f022 0204 bic.w r2, r2, #4 + 8005e08: 61da str r2, [r3, #28] + 8005e0a: 68fb ldr r3, [r7, #12] + 8005e0c: 681b ldr r3, [r3, #0] + 8005e0e: 69d9 ldr r1, [r3, #28] + 8005e10: 68bb ldr r3, [r7, #8] + 8005e12: 691a ldr r2, [r3, #16] + 8005e14: 68fb ldr r3, [r7, #12] + 8005e16: 681b ldr r3, [r3, #0] + 8005e18: 430a orrs r2, r1 + 8005e1a: 61da str r2, [r3, #28] + 8005e1c: e023 b.n 8005e66 + 8005e1e: 68fb ldr r3, [r7, #12] + 8005e20: 681b ldr r3, [r3, #0] + 8005e22: 68b9 ldr r1, [r7, #8] + 8005e24: 4618 mov r0, r3 + 8005e26: f000 fa27 bl 8006278 + 8005e2a: 68fb ldr r3, [r7, #12] + 8005e2c: 681b ldr r3, [r3, #0] + 8005e2e: 69da ldr r2, [r3, #28] + 8005e30: 68fb ldr r3, [r7, #12] + 8005e32: 681b ldr r3, [r3, #0] + 8005e34: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 8005e38: 61da str r2, [r3, #28] + 8005e3a: 68fb ldr r3, [r7, #12] + 8005e3c: 681b ldr r3, [r3, #0] + 8005e3e: 69da ldr r2, [r3, #28] + 8005e40: 68fb ldr r3, [r7, #12] + 8005e42: 681b ldr r3, [r3, #0] + 8005e44: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8005e48: 61da str r2, [r3, #28] + 8005e4a: 68fb ldr r3, [r7, #12] + 8005e4c: 681b ldr r3, [r3, #0] + 8005e4e: 69d9 ldr r1, [r3, #28] + 8005e50: 68bb ldr r3, [r7, #8] + 8005e52: 691b ldr r3, [r3, #16] + 8005e54: 021a lsls r2, r3, #8 + 8005e56: 68fb ldr r3, [r7, #12] + 8005e58: 681b ldr r3, [r3, #0] + 8005e5a: 430a orrs r2, r1 + 8005e5c: 61da str r2, [r3, #28] + 8005e5e: e002 b.n 8005e66 + 8005e60: 2301 movs r3, #1 + 8005e62: 75fb strb r3, [r7, #23] + 8005e64: bf00 nop + 8005e66: 68fb ldr r3, [r7, #12] + 8005e68: 2200 movs r2, #0 + 8005e6a: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8005e6e: 7dfb ldrb r3, [r7, #23] + 8005e70: 4618 mov r0, r3 + 8005e72: 3718 adds r7, #24 + 8005e74: 46bd mov sp, r7 + 8005e76: bd80 pop {r7, pc} + +08005e78 : + 8005e78: b480 push {r7} + 8005e7a: b085 sub sp, #20 + 8005e7c: af00 add r7, sp, #0 + 8005e7e: 6078 str r0, [r7, #4] + 8005e80: 6039 str r1, [r7, #0] + 8005e82: 687b ldr r3, [r7, #4] + 8005e84: 681b ldr r3, [r3, #0] + 8005e86: 60fb str r3, [r7, #12] + 8005e88: 687b ldr r3, [r7, #4] + 8005e8a: 4a43 ldr r2, [pc, #268] @ (8005f98 ) + 8005e8c: 4293 cmp r3, r2 + 8005e8e: d013 beq.n 8005eb8 + 8005e90: 687b ldr r3, [r7, #4] + 8005e92: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8005e96: d00f beq.n 8005eb8 + 8005e98: 687b ldr r3, [r7, #4] + 8005e9a: 4a40 ldr r2, [pc, #256] @ (8005f9c ) + 8005e9c: 4293 cmp r3, r2 + 8005e9e: d00b beq.n 8005eb8 + 8005ea0: 687b ldr r3, [r7, #4] + 8005ea2: 4a3f ldr r2, [pc, #252] @ (8005fa0 ) + 8005ea4: 4293 cmp r3, r2 + 8005ea6: d007 beq.n 8005eb8 + 8005ea8: 687b ldr r3, [r7, #4] + 8005eaa: 4a3e ldr r2, [pc, #248] @ (8005fa4 ) + 8005eac: 4293 cmp r3, r2 + 8005eae: d003 beq.n 8005eb8 + 8005eb0: 687b ldr r3, [r7, #4] + 8005eb2: 4a3d ldr r2, [pc, #244] @ (8005fa8 ) + 8005eb4: 4293 cmp r3, r2 + 8005eb6: d108 bne.n 8005eca + 8005eb8: 68fb ldr r3, [r7, #12] + 8005eba: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8005ebe: 60fb str r3, [r7, #12] + 8005ec0: 683b ldr r3, [r7, #0] + 8005ec2: 685b ldr r3, [r3, #4] + 8005ec4: 68fa ldr r2, [r7, #12] + 8005ec6: 4313 orrs r3, r2 + 8005ec8: 60fb str r3, [r7, #12] + 8005eca: 687b ldr r3, [r7, #4] + 8005ecc: 4a32 ldr r2, [pc, #200] @ (8005f98 ) + 8005ece: 4293 cmp r3, r2 + 8005ed0: d02b beq.n 8005f2a + 8005ed2: 687b ldr r3, [r7, #4] + 8005ed4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8005ed8: d027 beq.n 8005f2a + 8005eda: 687b ldr r3, [r7, #4] + 8005edc: 4a2f ldr r2, [pc, #188] @ (8005f9c ) + 8005ede: 4293 cmp r3, r2 + 8005ee0: d023 beq.n 8005f2a + 8005ee2: 687b ldr r3, [r7, #4] + 8005ee4: 4a2e ldr r2, [pc, #184] @ (8005fa0 ) + 8005ee6: 4293 cmp r3, r2 + 8005ee8: d01f beq.n 8005f2a + 8005eea: 687b ldr r3, [r7, #4] + 8005eec: 4a2d ldr r2, [pc, #180] @ (8005fa4 ) + 8005eee: 4293 cmp r3, r2 + 8005ef0: d01b beq.n 8005f2a + 8005ef2: 687b ldr r3, [r7, #4] + 8005ef4: 4a2c ldr r2, [pc, #176] @ (8005fa8 ) + 8005ef6: 4293 cmp r3, r2 + 8005ef8: d017 beq.n 8005f2a + 8005efa: 687b ldr r3, [r7, #4] + 8005efc: 4a2b ldr r2, [pc, #172] @ (8005fac ) + 8005efe: 4293 cmp r3, r2 + 8005f00: d013 beq.n 8005f2a + 8005f02: 687b ldr r3, [r7, #4] + 8005f04: 4a2a ldr r2, [pc, #168] @ (8005fb0 ) + 8005f06: 4293 cmp r3, r2 + 8005f08: d00f beq.n 8005f2a + 8005f0a: 687b ldr r3, [r7, #4] + 8005f0c: 4a29 ldr r2, [pc, #164] @ (8005fb4 ) + 8005f0e: 4293 cmp r3, r2 + 8005f10: d00b beq.n 8005f2a + 8005f12: 687b ldr r3, [r7, #4] + 8005f14: 4a28 ldr r2, [pc, #160] @ (8005fb8 ) + 8005f16: 4293 cmp r3, r2 + 8005f18: d007 beq.n 8005f2a + 8005f1a: 687b ldr r3, [r7, #4] + 8005f1c: 4a27 ldr r2, [pc, #156] @ (8005fbc ) + 8005f1e: 4293 cmp r3, r2 + 8005f20: d003 beq.n 8005f2a + 8005f22: 687b ldr r3, [r7, #4] + 8005f24: 4a26 ldr r2, [pc, #152] @ (8005fc0 ) + 8005f26: 4293 cmp r3, r2 + 8005f28: d108 bne.n 8005f3c + 8005f2a: 68fb ldr r3, [r7, #12] + 8005f2c: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8005f30: 60fb str r3, [r7, #12] + 8005f32: 683b ldr r3, [r7, #0] + 8005f34: 68db ldr r3, [r3, #12] + 8005f36: 68fa ldr r2, [r7, #12] + 8005f38: 4313 orrs r3, r2 + 8005f3a: 60fb str r3, [r7, #12] + 8005f3c: 68fb ldr r3, [r7, #12] + 8005f3e: f023 0280 bic.w r2, r3, #128 @ 0x80 + 8005f42: 683b ldr r3, [r7, #0] + 8005f44: 695b ldr r3, [r3, #20] + 8005f46: 4313 orrs r3, r2 + 8005f48: 60fb str r3, [r7, #12] + 8005f4a: 683b ldr r3, [r7, #0] + 8005f4c: 689a ldr r2, [r3, #8] + 8005f4e: 687b ldr r3, [r7, #4] + 8005f50: 62da str r2, [r3, #44] @ 0x2c + 8005f52: 683b ldr r3, [r7, #0] + 8005f54: 681a ldr r2, [r3, #0] + 8005f56: 687b ldr r3, [r7, #4] + 8005f58: 629a str r2, [r3, #40] @ 0x28 + 8005f5a: 687b ldr r3, [r7, #4] + 8005f5c: 4a0e ldr r2, [pc, #56] @ (8005f98 ) + 8005f5e: 4293 cmp r3, r2 + 8005f60: d003 beq.n 8005f6a + 8005f62: 687b ldr r3, [r7, #4] + 8005f64: 4a10 ldr r2, [pc, #64] @ (8005fa8 ) + 8005f66: 4293 cmp r3, r2 + 8005f68: d103 bne.n 8005f72 + 8005f6a: 683b ldr r3, [r7, #0] + 8005f6c: 691a ldr r2, [r3, #16] + 8005f6e: 687b ldr r3, [r7, #4] + 8005f70: 631a str r2, [r3, #48] @ 0x30 + 8005f72: 687b ldr r3, [r7, #4] + 8005f74: 681b ldr r3, [r3, #0] + 8005f76: f043 0204 orr.w r2, r3, #4 + 8005f7a: 687b ldr r3, [r7, #4] + 8005f7c: 601a str r2, [r3, #0] + 8005f7e: 687b ldr r3, [r7, #4] + 8005f80: 2201 movs r2, #1 + 8005f82: 615a str r2, [r3, #20] + 8005f84: 687b ldr r3, [r7, #4] + 8005f86: 68fa ldr r2, [r7, #12] + 8005f88: 601a str r2, [r3, #0] + 8005f8a: bf00 nop + 8005f8c: 3714 adds r7, #20 + 8005f8e: 46bd mov sp, r7 + 8005f90: f85d 7b04 ldr.w r7, [sp], #4 + 8005f94: 4770 bx lr + 8005f96: bf00 nop + 8005f98: 40010000 .word 0x40010000 + 8005f9c: 40000400 .word 0x40000400 + 8005fa0: 40000800 .word 0x40000800 + 8005fa4: 40000c00 .word 0x40000c00 + 8005fa8: 40010400 .word 0x40010400 + 8005fac: 40014000 .word 0x40014000 + 8005fb0: 40014400 .word 0x40014400 + 8005fb4: 40014800 .word 0x40014800 + 8005fb8: 40001800 .word 0x40001800 + 8005fbc: 40001c00 .word 0x40001c00 + 8005fc0: 40002000 .word 0x40002000 + +08005fc4 : + 8005fc4: b480 push {r7} + 8005fc6: b087 sub sp, #28 + 8005fc8: af00 add r7, sp, #0 + 8005fca: 6078 str r0, [r7, #4] + 8005fcc: 6039 str r1, [r7, #0] + 8005fce: 687b ldr r3, [r7, #4] + 8005fd0: 6a1b ldr r3, [r3, #32] + 8005fd2: 617b str r3, [r7, #20] + 8005fd4: 687b ldr r3, [r7, #4] + 8005fd6: 6a1b ldr r3, [r3, #32] + 8005fd8: f023 0201 bic.w r2, r3, #1 + 8005fdc: 687b ldr r3, [r7, #4] + 8005fde: 621a str r2, [r3, #32] + 8005fe0: 687b ldr r3, [r7, #4] + 8005fe2: 685b ldr r3, [r3, #4] + 8005fe4: 613b str r3, [r7, #16] + 8005fe6: 687b ldr r3, [r7, #4] + 8005fe8: 699b ldr r3, [r3, #24] + 8005fea: 60fb str r3, [r7, #12] + 8005fec: 68fb ldr r3, [r7, #12] + 8005fee: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8005ff2: 60fb str r3, [r7, #12] + 8005ff4: 68fb ldr r3, [r7, #12] + 8005ff6: f023 0303 bic.w r3, r3, #3 + 8005ffa: 60fb str r3, [r7, #12] + 8005ffc: 683b ldr r3, [r7, #0] + 8005ffe: 681b ldr r3, [r3, #0] + 8006000: 68fa ldr r2, [r7, #12] + 8006002: 4313 orrs r3, r2 + 8006004: 60fb str r3, [r7, #12] + 8006006: 697b ldr r3, [r7, #20] + 8006008: f023 0302 bic.w r3, r3, #2 + 800600c: 617b str r3, [r7, #20] + 800600e: 683b ldr r3, [r7, #0] + 8006010: 689b ldr r3, [r3, #8] + 8006012: 697a ldr r2, [r7, #20] + 8006014: 4313 orrs r3, r2 + 8006016: 617b str r3, [r7, #20] + 8006018: 687b ldr r3, [r7, #4] + 800601a: 4a20 ldr r2, [pc, #128] @ (800609c ) + 800601c: 4293 cmp r3, r2 + 800601e: d003 beq.n 8006028 + 8006020: 687b ldr r3, [r7, #4] + 8006022: 4a1f ldr r2, [pc, #124] @ (80060a0 ) + 8006024: 4293 cmp r3, r2 + 8006026: d10c bne.n 8006042 + 8006028: 697b ldr r3, [r7, #20] + 800602a: f023 0308 bic.w r3, r3, #8 + 800602e: 617b str r3, [r7, #20] + 8006030: 683b ldr r3, [r7, #0] + 8006032: 68db ldr r3, [r3, #12] + 8006034: 697a ldr r2, [r7, #20] + 8006036: 4313 orrs r3, r2 + 8006038: 617b str r3, [r7, #20] + 800603a: 697b ldr r3, [r7, #20] + 800603c: f023 0304 bic.w r3, r3, #4 + 8006040: 617b str r3, [r7, #20] + 8006042: 687b ldr r3, [r7, #4] + 8006044: 4a15 ldr r2, [pc, #84] @ (800609c ) + 8006046: 4293 cmp r3, r2 + 8006048: d003 beq.n 8006052 + 800604a: 687b ldr r3, [r7, #4] + 800604c: 4a14 ldr r2, [pc, #80] @ (80060a0 ) + 800604e: 4293 cmp r3, r2 + 8006050: d111 bne.n 8006076 + 8006052: 693b ldr r3, [r7, #16] + 8006054: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8006058: 613b str r3, [r7, #16] + 800605a: 693b ldr r3, [r7, #16] + 800605c: f423 7300 bic.w r3, r3, #512 @ 0x200 + 8006060: 613b str r3, [r7, #16] + 8006062: 683b ldr r3, [r7, #0] + 8006064: 695b ldr r3, [r3, #20] + 8006066: 693a ldr r2, [r7, #16] + 8006068: 4313 orrs r3, r2 + 800606a: 613b str r3, [r7, #16] + 800606c: 683b ldr r3, [r7, #0] + 800606e: 699b ldr r3, [r3, #24] + 8006070: 693a ldr r2, [r7, #16] + 8006072: 4313 orrs r3, r2 + 8006074: 613b str r3, [r7, #16] + 8006076: 687b ldr r3, [r7, #4] + 8006078: 693a ldr r2, [r7, #16] + 800607a: 605a str r2, [r3, #4] + 800607c: 687b ldr r3, [r7, #4] + 800607e: 68fa ldr r2, [r7, #12] + 8006080: 619a str r2, [r3, #24] + 8006082: 683b ldr r3, [r7, #0] + 8006084: 685a ldr r2, [r3, #4] + 8006086: 687b ldr r3, [r7, #4] + 8006088: 635a str r2, [r3, #52] @ 0x34 + 800608a: 687b ldr r3, [r7, #4] + 800608c: 697a ldr r2, [r7, #20] + 800608e: 621a str r2, [r3, #32] + 8006090: bf00 nop + 8006092: 371c adds r7, #28 + 8006094: 46bd mov sp, r7 + 8006096: f85d 7b04 ldr.w r7, [sp], #4 + 800609a: 4770 bx lr + 800609c: 40010000 .word 0x40010000 + 80060a0: 40010400 .word 0x40010400 + +080060a4 : + 80060a4: b480 push {r7} + 80060a6: b087 sub sp, #28 + 80060a8: af00 add r7, sp, #0 + 80060aa: 6078 str r0, [r7, #4] + 80060ac: 6039 str r1, [r7, #0] + 80060ae: 687b ldr r3, [r7, #4] + 80060b0: 6a1b ldr r3, [r3, #32] + 80060b2: 617b str r3, [r7, #20] + 80060b4: 687b ldr r3, [r7, #4] + 80060b6: 6a1b ldr r3, [r3, #32] + 80060b8: f023 0210 bic.w r2, r3, #16 + 80060bc: 687b ldr r3, [r7, #4] + 80060be: 621a str r2, [r3, #32] + 80060c0: 687b ldr r3, [r7, #4] + 80060c2: 685b ldr r3, [r3, #4] + 80060c4: 613b str r3, [r7, #16] + 80060c6: 687b ldr r3, [r7, #4] + 80060c8: 699b ldr r3, [r3, #24] + 80060ca: 60fb str r3, [r7, #12] + 80060cc: 68fb ldr r3, [r7, #12] + 80060ce: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 80060d2: 60fb str r3, [r7, #12] + 80060d4: 68fb ldr r3, [r7, #12] + 80060d6: f423 7340 bic.w r3, r3, #768 @ 0x300 + 80060da: 60fb str r3, [r7, #12] + 80060dc: 683b ldr r3, [r7, #0] + 80060de: 681b ldr r3, [r3, #0] + 80060e0: 021b lsls r3, r3, #8 + 80060e2: 68fa ldr r2, [r7, #12] + 80060e4: 4313 orrs r3, r2 + 80060e6: 60fb str r3, [r7, #12] + 80060e8: 697b ldr r3, [r7, #20] + 80060ea: f023 0320 bic.w r3, r3, #32 + 80060ee: 617b str r3, [r7, #20] + 80060f0: 683b ldr r3, [r7, #0] + 80060f2: 689b ldr r3, [r3, #8] + 80060f4: 011b lsls r3, r3, #4 + 80060f6: 697a ldr r2, [r7, #20] + 80060f8: 4313 orrs r3, r2 + 80060fa: 617b str r3, [r7, #20] + 80060fc: 687b ldr r3, [r7, #4] + 80060fe: 4a22 ldr r2, [pc, #136] @ (8006188 ) + 8006100: 4293 cmp r3, r2 + 8006102: d003 beq.n 800610c + 8006104: 687b ldr r3, [r7, #4] + 8006106: 4a21 ldr r2, [pc, #132] @ (800618c ) + 8006108: 4293 cmp r3, r2 + 800610a: d10d bne.n 8006128 + 800610c: 697b ldr r3, [r7, #20] + 800610e: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8006112: 617b str r3, [r7, #20] + 8006114: 683b ldr r3, [r7, #0] + 8006116: 68db ldr r3, [r3, #12] + 8006118: 011b lsls r3, r3, #4 + 800611a: 697a ldr r2, [r7, #20] + 800611c: 4313 orrs r3, r2 + 800611e: 617b str r3, [r7, #20] + 8006120: 697b ldr r3, [r7, #20] + 8006122: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8006126: 617b str r3, [r7, #20] + 8006128: 687b ldr r3, [r7, #4] + 800612a: 4a17 ldr r2, [pc, #92] @ (8006188 ) + 800612c: 4293 cmp r3, r2 + 800612e: d003 beq.n 8006138 + 8006130: 687b ldr r3, [r7, #4] + 8006132: 4a16 ldr r2, [pc, #88] @ (800618c ) + 8006134: 4293 cmp r3, r2 + 8006136: d113 bne.n 8006160 + 8006138: 693b ldr r3, [r7, #16] + 800613a: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 800613e: 613b str r3, [r7, #16] + 8006140: 693b ldr r3, [r7, #16] + 8006142: f423 6300 bic.w r3, r3, #2048 @ 0x800 + 8006146: 613b str r3, [r7, #16] + 8006148: 683b ldr r3, [r7, #0] + 800614a: 695b ldr r3, [r3, #20] + 800614c: 009b lsls r3, r3, #2 + 800614e: 693a ldr r2, [r7, #16] + 8006150: 4313 orrs r3, r2 + 8006152: 613b str r3, [r7, #16] + 8006154: 683b ldr r3, [r7, #0] + 8006156: 699b ldr r3, [r3, #24] + 8006158: 009b lsls r3, r3, #2 + 800615a: 693a ldr r2, [r7, #16] + 800615c: 4313 orrs r3, r2 + 800615e: 613b str r3, [r7, #16] + 8006160: 687b ldr r3, [r7, #4] + 8006162: 693a ldr r2, [r7, #16] + 8006164: 605a str r2, [r3, #4] + 8006166: 687b ldr r3, [r7, #4] + 8006168: 68fa ldr r2, [r7, #12] + 800616a: 619a str r2, [r3, #24] + 800616c: 683b ldr r3, [r7, #0] + 800616e: 685a ldr r2, [r3, #4] + 8006170: 687b ldr r3, [r7, #4] + 8006172: 639a str r2, [r3, #56] @ 0x38 + 8006174: 687b ldr r3, [r7, #4] + 8006176: 697a ldr r2, [r7, #20] + 8006178: 621a str r2, [r3, #32] + 800617a: bf00 nop + 800617c: 371c adds r7, #28 + 800617e: 46bd mov sp, r7 + 8006180: f85d 7b04 ldr.w r7, [sp], #4 + 8006184: 4770 bx lr + 8006186: bf00 nop + 8006188: 40010000 .word 0x40010000 + 800618c: 40010400 .word 0x40010400 + +08006190 : + 8006190: b480 push {r7} + 8006192: b087 sub sp, #28 + 8006194: af00 add r7, sp, #0 + 8006196: 6078 str r0, [r7, #4] + 8006198: 6039 str r1, [r7, #0] + 800619a: 687b ldr r3, [r7, #4] + 800619c: 6a1b ldr r3, [r3, #32] + 800619e: 617b str r3, [r7, #20] + 80061a0: 687b ldr r3, [r7, #4] + 80061a2: 6a1b ldr r3, [r3, #32] + 80061a4: f423 7280 bic.w r2, r3, #256 @ 0x100 + 80061a8: 687b ldr r3, [r7, #4] + 80061aa: 621a str r2, [r3, #32] + 80061ac: 687b ldr r3, [r7, #4] + 80061ae: 685b ldr r3, [r3, #4] + 80061b0: 613b str r3, [r7, #16] + 80061b2: 687b ldr r3, [r7, #4] + 80061b4: 69db ldr r3, [r3, #28] + 80061b6: 60fb str r3, [r7, #12] + 80061b8: 68fb ldr r3, [r7, #12] + 80061ba: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80061be: 60fb str r3, [r7, #12] + 80061c0: 68fb ldr r3, [r7, #12] + 80061c2: f023 0303 bic.w r3, r3, #3 + 80061c6: 60fb str r3, [r7, #12] + 80061c8: 683b ldr r3, [r7, #0] + 80061ca: 681b ldr r3, [r3, #0] + 80061cc: 68fa ldr r2, [r7, #12] + 80061ce: 4313 orrs r3, r2 + 80061d0: 60fb str r3, [r7, #12] + 80061d2: 697b ldr r3, [r7, #20] + 80061d4: f423 7300 bic.w r3, r3, #512 @ 0x200 + 80061d8: 617b str r3, [r7, #20] + 80061da: 683b ldr r3, [r7, #0] + 80061dc: 689b ldr r3, [r3, #8] + 80061de: 021b lsls r3, r3, #8 + 80061e0: 697a ldr r2, [r7, #20] + 80061e2: 4313 orrs r3, r2 + 80061e4: 617b str r3, [r7, #20] + 80061e6: 687b ldr r3, [r7, #4] + 80061e8: 4a21 ldr r2, [pc, #132] @ (8006270 ) + 80061ea: 4293 cmp r3, r2 + 80061ec: d003 beq.n 80061f6 + 80061ee: 687b ldr r3, [r7, #4] + 80061f0: 4a20 ldr r2, [pc, #128] @ (8006274 ) + 80061f2: 4293 cmp r3, r2 + 80061f4: d10d bne.n 8006212 + 80061f6: 697b ldr r3, [r7, #20] + 80061f8: f423 6300 bic.w r3, r3, #2048 @ 0x800 + 80061fc: 617b str r3, [r7, #20] + 80061fe: 683b ldr r3, [r7, #0] + 8006200: 68db ldr r3, [r3, #12] + 8006202: 021b lsls r3, r3, #8 + 8006204: 697a ldr r2, [r7, #20] + 8006206: 4313 orrs r3, r2 + 8006208: 617b str r3, [r7, #20] + 800620a: 697b ldr r3, [r7, #20] + 800620c: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8006210: 617b str r3, [r7, #20] + 8006212: 687b ldr r3, [r7, #4] + 8006214: 4a16 ldr r2, [pc, #88] @ (8006270 ) + 8006216: 4293 cmp r3, r2 + 8006218: d003 beq.n 8006222 + 800621a: 687b ldr r3, [r7, #4] + 800621c: 4a15 ldr r2, [pc, #84] @ (8006274 ) + 800621e: 4293 cmp r3, r2 + 8006220: d113 bne.n 800624a + 8006222: 693b ldr r3, [r7, #16] + 8006224: f423 5380 bic.w r3, r3, #4096 @ 0x1000 + 8006228: 613b str r3, [r7, #16] + 800622a: 693b ldr r3, [r7, #16] + 800622c: f423 5300 bic.w r3, r3, #8192 @ 0x2000 + 8006230: 613b str r3, [r7, #16] + 8006232: 683b ldr r3, [r7, #0] + 8006234: 695b ldr r3, [r3, #20] + 8006236: 011b lsls r3, r3, #4 + 8006238: 693a ldr r2, [r7, #16] + 800623a: 4313 orrs r3, r2 + 800623c: 613b str r3, [r7, #16] + 800623e: 683b ldr r3, [r7, #0] + 8006240: 699b ldr r3, [r3, #24] + 8006242: 011b lsls r3, r3, #4 + 8006244: 693a ldr r2, [r7, #16] + 8006246: 4313 orrs r3, r2 + 8006248: 613b str r3, [r7, #16] + 800624a: 687b ldr r3, [r7, #4] + 800624c: 693a ldr r2, [r7, #16] + 800624e: 605a str r2, [r3, #4] + 8006250: 687b ldr r3, [r7, #4] + 8006252: 68fa ldr r2, [r7, #12] + 8006254: 61da str r2, [r3, #28] + 8006256: 683b ldr r3, [r7, #0] + 8006258: 685a ldr r2, [r3, #4] + 800625a: 687b ldr r3, [r7, #4] + 800625c: 63da str r2, [r3, #60] @ 0x3c + 800625e: 687b ldr r3, [r7, #4] + 8006260: 697a ldr r2, [r7, #20] + 8006262: 621a str r2, [r3, #32] + 8006264: bf00 nop + 8006266: 371c adds r7, #28 + 8006268: 46bd mov sp, r7 + 800626a: f85d 7b04 ldr.w r7, [sp], #4 + 800626e: 4770 bx lr + 8006270: 40010000 .word 0x40010000 + 8006274: 40010400 .word 0x40010400 + +08006278 : + 8006278: b480 push {r7} + 800627a: b087 sub sp, #28 + 800627c: af00 add r7, sp, #0 + 800627e: 6078 str r0, [r7, #4] + 8006280: 6039 str r1, [r7, #0] + 8006282: 687b ldr r3, [r7, #4] + 8006284: 6a1b ldr r3, [r3, #32] + 8006286: 613b str r3, [r7, #16] + 8006288: 687b ldr r3, [r7, #4] + 800628a: 6a1b ldr r3, [r3, #32] + 800628c: f423 5280 bic.w r2, r3, #4096 @ 0x1000 + 8006290: 687b ldr r3, [r7, #4] + 8006292: 621a str r2, [r3, #32] + 8006294: 687b ldr r3, [r7, #4] + 8006296: 685b ldr r3, [r3, #4] + 8006298: 617b str r3, [r7, #20] + 800629a: 687b ldr r3, [r7, #4] + 800629c: 69db ldr r3, [r3, #28] + 800629e: 60fb str r3, [r7, #12] + 80062a0: 68fb ldr r3, [r7, #12] + 80062a2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 80062a6: 60fb str r3, [r7, #12] + 80062a8: 68fb ldr r3, [r7, #12] + 80062aa: f423 7340 bic.w r3, r3, #768 @ 0x300 + 80062ae: 60fb str r3, [r7, #12] + 80062b0: 683b ldr r3, [r7, #0] + 80062b2: 681b ldr r3, [r3, #0] + 80062b4: 021b lsls r3, r3, #8 + 80062b6: 68fa ldr r2, [r7, #12] + 80062b8: 4313 orrs r3, r2 + 80062ba: 60fb str r3, [r7, #12] + 80062bc: 693b ldr r3, [r7, #16] + 80062be: f423 5300 bic.w r3, r3, #8192 @ 0x2000 + 80062c2: 613b str r3, [r7, #16] + 80062c4: 683b ldr r3, [r7, #0] + 80062c6: 689b ldr r3, [r3, #8] + 80062c8: 031b lsls r3, r3, #12 + 80062ca: 693a ldr r2, [r7, #16] + 80062cc: 4313 orrs r3, r2 + 80062ce: 613b str r3, [r7, #16] + 80062d0: 687b ldr r3, [r7, #4] + 80062d2: 4a12 ldr r2, [pc, #72] @ (800631c ) + 80062d4: 4293 cmp r3, r2 + 80062d6: d003 beq.n 80062e0 + 80062d8: 687b ldr r3, [r7, #4] + 80062da: 4a11 ldr r2, [pc, #68] @ (8006320 ) + 80062dc: 4293 cmp r3, r2 + 80062de: d109 bne.n 80062f4 + 80062e0: 697b ldr r3, [r7, #20] + 80062e2: f423 4380 bic.w r3, r3, #16384 @ 0x4000 + 80062e6: 617b str r3, [r7, #20] + 80062e8: 683b ldr r3, [r7, #0] + 80062ea: 695b ldr r3, [r3, #20] + 80062ec: 019b lsls r3, r3, #6 + 80062ee: 697a ldr r2, [r7, #20] + 80062f0: 4313 orrs r3, r2 + 80062f2: 617b str r3, [r7, #20] + 80062f4: 687b ldr r3, [r7, #4] + 80062f6: 697a ldr r2, [r7, #20] + 80062f8: 605a str r2, [r3, #4] + 80062fa: 687b ldr r3, [r7, #4] + 80062fc: 68fa ldr r2, [r7, #12] + 80062fe: 61da str r2, [r3, #28] + 8006300: 683b ldr r3, [r7, #0] + 8006302: 685a ldr r2, [r3, #4] + 8006304: 687b ldr r3, [r7, #4] + 8006306: 641a str r2, [r3, #64] @ 0x40 + 8006308: 687b ldr r3, [r7, #4] + 800630a: 693a ldr r2, [r7, #16] + 800630c: 621a str r2, [r3, #32] + 800630e: bf00 nop + 8006310: 371c adds r7, #28 + 8006312: 46bd mov sp, r7 + 8006314: f85d 7b04 ldr.w r7, [sp], #4 + 8006318: 4770 bx lr + 800631a: bf00 nop + 800631c: 40010000 .word 0x40010000 + 8006320: 40010400 .word 0x40010400 + +08006324 : + 8006324: b480 push {r7} + 8006326: b087 sub sp, #28 + 8006328: af00 add r7, sp, #0 + 800632a: 60f8 str r0, [r7, #12] + 800632c: 60b9 str r1, [r7, #8] + 800632e: 607a str r2, [r7, #4] + 8006330: 68bb ldr r3, [r7, #8] + 8006332: f003 031f and.w r3, r3, #31 + 8006336: 2201 movs r2, #1 + 8006338: fa02 f303 lsl.w r3, r2, r3 + 800633c: 617b str r3, [r7, #20] + 800633e: 68fb ldr r3, [r7, #12] + 8006340: 6a1a ldr r2, [r3, #32] + 8006342: 697b ldr r3, [r7, #20] + 8006344: 43db mvns r3, r3 + 8006346: 401a ands r2, r3 + 8006348: 68fb ldr r3, [r7, #12] + 800634a: 621a str r2, [r3, #32] + 800634c: 68fb ldr r3, [r7, #12] + 800634e: 6a1a ldr r2, [r3, #32] + 8006350: 68bb ldr r3, [r7, #8] + 8006352: f003 031f and.w r3, r3, #31 + 8006356: 6879 ldr r1, [r7, #4] + 8006358: fa01 f303 lsl.w r3, r1, r3 + 800635c: 431a orrs r2, r3 + 800635e: 68fb ldr r3, [r7, #12] + 8006360: 621a str r2, [r3, #32] + 8006362: bf00 nop + 8006364: 371c adds r7, #28 + 8006366: 46bd mov sp, r7 + 8006368: f85d 7b04 ldr.w r7, [sp], #4 + 800636c: 4770 bx lr + ... + +08006370 : + 8006370: b480 push {r7} + 8006372: b085 sub sp, #20 + 8006374: af00 add r7, sp, #0 + 8006376: 6078 str r0, [r7, #4] + 8006378: 6039 str r1, [r7, #0] + 800637a: 687b ldr r3, [r7, #4] + 800637c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8006380: 2b01 cmp r3, #1 + 8006382: d101 bne.n 8006388 + 8006384: 2302 movs r3, #2 + 8006386: e05a b.n 800643e + 8006388: 687b ldr r3, [r7, #4] + 800638a: 2201 movs r2, #1 + 800638c: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8006390: 687b ldr r3, [r7, #4] + 8006392: 2202 movs r2, #2 + 8006394: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8006398: 687b ldr r3, [r7, #4] + 800639a: 681b ldr r3, [r3, #0] + 800639c: 685b ldr r3, [r3, #4] + 800639e: 60fb str r3, [r7, #12] + 80063a0: 687b ldr r3, [r7, #4] + 80063a2: 681b ldr r3, [r3, #0] + 80063a4: 689b ldr r3, [r3, #8] + 80063a6: 60bb str r3, [r7, #8] + 80063a8: 68fb ldr r3, [r7, #12] + 80063aa: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80063ae: 60fb str r3, [r7, #12] + 80063b0: 683b ldr r3, [r7, #0] + 80063b2: 681b ldr r3, [r3, #0] + 80063b4: 68fa ldr r2, [r7, #12] + 80063b6: 4313 orrs r3, r2 + 80063b8: 60fb str r3, [r7, #12] + 80063ba: 687b ldr r3, [r7, #4] + 80063bc: 681b ldr r3, [r3, #0] + 80063be: 68fa ldr r2, [r7, #12] + 80063c0: 605a str r2, [r3, #4] + 80063c2: 687b ldr r3, [r7, #4] + 80063c4: 681b ldr r3, [r3, #0] + 80063c6: 4a21 ldr r2, [pc, #132] @ (800644c ) + 80063c8: 4293 cmp r3, r2 + 80063ca: d022 beq.n 8006412 + 80063cc: 687b ldr r3, [r7, #4] + 80063ce: 681b ldr r3, [r3, #0] + 80063d0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80063d4: d01d beq.n 8006412 + 80063d6: 687b ldr r3, [r7, #4] + 80063d8: 681b ldr r3, [r3, #0] + 80063da: 4a1d ldr r2, [pc, #116] @ (8006450 ) + 80063dc: 4293 cmp r3, r2 + 80063de: d018 beq.n 8006412 + 80063e0: 687b ldr r3, [r7, #4] + 80063e2: 681b ldr r3, [r3, #0] + 80063e4: 4a1b ldr r2, [pc, #108] @ (8006454 ) + 80063e6: 4293 cmp r3, r2 + 80063e8: d013 beq.n 8006412 + 80063ea: 687b ldr r3, [r7, #4] + 80063ec: 681b ldr r3, [r3, #0] + 80063ee: 4a1a ldr r2, [pc, #104] @ (8006458 ) + 80063f0: 4293 cmp r3, r2 + 80063f2: d00e beq.n 8006412 + 80063f4: 687b ldr r3, [r7, #4] + 80063f6: 681b ldr r3, [r3, #0] + 80063f8: 4a18 ldr r2, [pc, #96] @ (800645c ) + 80063fa: 4293 cmp r3, r2 + 80063fc: d009 beq.n 8006412 + 80063fe: 687b ldr r3, [r7, #4] + 8006400: 681b ldr r3, [r3, #0] + 8006402: 4a17 ldr r2, [pc, #92] @ (8006460 ) + 8006404: 4293 cmp r3, r2 + 8006406: d004 beq.n 8006412 + 8006408: 687b ldr r3, [r7, #4] + 800640a: 681b ldr r3, [r3, #0] + 800640c: 4a15 ldr r2, [pc, #84] @ (8006464 ) + 800640e: 4293 cmp r3, r2 + 8006410: d10c bne.n 800642c + 8006412: 68bb ldr r3, [r7, #8] + 8006414: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8006418: 60bb str r3, [r7, #8] + 800641a: 683b ldr r3, [r7, #0] + 800641c: 685b ldr r3, [r3, #4] + 800641e: 68ba ldr r2, [r7, #8] + 8006420: 4313 orrs r3, r2 + 8006422: 60bb str r3, [r7, #8] + 8006424: 687b ldr r3, [r7, #4] + 8006426: 681b ldr r3, [r3, #0] + 8006428: 68ba ldr r2, [r7, #8] + 800642a: 609a str r2, [r3, #8] + 800642c: 687b ldr r3, [r7, #4] + 800642e: 2201 movs r2, #1 + 8006430: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8006434: 687b ldr r3, [r7, #4] + 8006436: 2200 movs r2, #0 + 8006438: f883 203c strb.w r2, [r3, #60] @ 0x3c + 800643c: 2300 movs r3, #0 + 800643e: 4618 mov r0, r3 + 8006440: 3714 adds r7, #20 + 8006442: 46bd mov sp, r7 + 8006444: f85d 7b04 ldr.w r7, [sp], #4 + 8006448: 4770 bx lr + 800644a: bf00 nop + 800644c: 40010000 .word 0x40010000 + 8006450: 40000400 .word 0x40000400 + 8006454: 40000800 .word 0x40000800 + 8006458: 40000c00 .word 0x40000c00 + 800645c: 40010400 .word 0x40010400 + 8006460: 40014000 .word 0x40014000 + 8006464: 40001800 .word 0x40001800 + +08006468 : + 8006468: b580 push {r7, lr} + 800646a: b082 sub sp, #8 + 800646c: af00 add r7, sp, #0 + 800646e: 6078 str r0, [r7, #4] + 8006470: 687b ldr r3, [r7, #4] + 8006472: 2b00 cmp r3, #0 + 8006474: d101 bne.n 800647a + 8006476: 2301 movs r3, #1 + 8006478: e042 b.n 8006500 + 800647a: 687b ldr r3, [r7, #4] + 800647c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 8006480: b2db uxtb r3, r3 + 8006482: 2b00 cmp r3, #0 + 8006484: d106 bne.n 8006494 + 8006486: 687b ldr r3, [r7, #4] + 8006488: 2200 movs r2, #0 + 800648a: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 800648e: 6878 ldr r0, [r7, #4] + 8006490: f7fb f9f8 bl 8001884 + 8006494: 687b ldr r3, [r7, #4] + 8006496: 2224 movs r2, #36 @ 0x24 + 8006498: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 800649c: 687b ldr r3, [r7, #4] + 800649e: 681b ldr r3, [r3, #0] + 80064a0: 68da ldr r2, [r3, #12] + 80064a2: 687b ldr r3, [r7, #4] + 80064a4: 681b ldr r3, [r3, #0] + 80064a6: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 80064aa: 60da str r2, [r3, #12] + 80064ac: 6878 ldr r0, [r7, #4] + 80064ae: f000 ff63 bl 8007378 + 80064b2: 687b ldr r3, [r7, #4] + 80064b4: 681b ldr r3, [r3, #0] + 80064b6: 691a ldr r2, [r3, #16] + 80064b8: 687b ldr r3, [r7, #4] + 80064ba: 681b ldr r3, [r3, #0] + 80064bc: f422 4290 bic.w r2, r2, #18432 @ 0x4800 + 80064c0: 611a str r2, [r3, #16] + 80064c2: 687b ldr r3, [r7, #4] + 80064c4: 681b ldr r3, [r3, #0] + 80064c6: 695a ldr r2, [r3, #20] + 80064c8: 687b ldr r3, [r7, #4] + 80064ca: 681b ldr r3, [r3, #0] + 80064cc: f022 022a bic.w r2, r2, #42 @ 0x2a + 80064d0: 615a str r2, [r3, #20] + 80064d2: 687b ldr r3, [r7, #4] + 80064d4: 681b ldr r3, [r3, #0] + 80064d6: 68da ldr r2, [r3, #12] + 80064d8: 687b ldr r3, [r7, #4] + 80064da: 681b ldr r3, [r3, #0] + 80064dc: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 80064e0: 60da str r2, [r3, #12] + 80064e2: 687b ldr r3, [r7, #4] + 80064e4: 2200 movs r2, #0 + 80064e6: 645a str r2, [r3, #68] @ 0x44 + 80064e8: 687b ldr r3, [r7, #4] + 80064ea: 2220 movs r2, #32 + 80064ec: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 80064f0: 687b ldr r3, [r7, #4] + 80064f2: 2220 movs r2, #32 + 80064f4: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 80064f8: 687b ldr r3, [r7, #4] + 80064fa: 2200 movs r2, #0 + 80064fc: 635a str r2, [r3, #52] @ 0x34 + 80064fe: 2300 movs r3, #0 + 8006500: 4618 mov r0, r3 + 8006502: 3708 adds r7, #8 + 8006504: 46bd mov sp, r7 + 8006506: bd80 pop {r7, pc} + +08006508 : + 8006508: b580 push {r7, lr} + 800650a: b08c sub sp, #48 @ 0x30 + 800650c: af00 add r7, sp, #0 + 800650e: 60f8 str r0, [r7, #12] + 8006510: 60b9 str r1, [r7, #8] + 8006512: 4613 mov r3, r2 + 8006514: 80fb strh r3, [r7, #6] + 8006516: 68fb ldr r3, [r7, #12] + 8006518: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 800651c: b2db uxtb r3, r3 + 800651e: 2b20 cmp r3, #32 + 8006520: d162 bne.n 80065e8 + 8006522: 68bb ldr r3, [r7, #8] + 8006524: 2b00 cmp r3, #0 + 8006526: d002 beq.n 800652e + 8006528: 88fb ldrh r3, [r7, #6] + 800652a: 2b00 cmp r3, #0 + 800652c: d101 bne.n 8006532 + 800652e: 2301 movs r3, #1 + 8006530: e05b b.n 80065ea + 8006532: 68ba ldr r2, [r7, #8] + 8006534: 68fb ldr r3, [r7, #12] + 8006536: 621a str r2, [r3, #32] + 8006538: 68fb ldr r3, [r7, #12] + 800653a: 88fa ldrh r2, [r7, #6] + 800653c: 849a strh r2, [r3, #36] @ 0x24 + 800653e: 68fb ldr r3, [r7, #12] + 8006540: 88fa ldrh r2, [r7, #6] + 8006542: 84da strh r2, [r3, #38] @ 0x26 + 8006544: 68fb ldr r3, [r7, #12] + 8006546: 2200 movs r2, #0 + 8006548: 645a str r2, [r3, #68] @ 0x44 + 800654a: 68fb ldr r3, [r7, #12] + 800654c: 2221 movs r2, #33 @ 0x21 + 800654e: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 8006552: 68fb ldr r3, [r7, #12] + 8006554: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006556: 4a27 ldr r2, [pc, #156] @ (80065f4 ) + 8006558: 63da str r2, [r3, #60] @ 0x3c + 800655a: 68fb ldr r3, [r7, #12] + 800655c: 6b9b ldr r3, [r3, #56] @ 0x38 + 800655e: 4a26 ldr r2, [pc, #152] @ (80065f8 ) + 8006560: 641a str r2, [r3, #64] @ 0x40 + 8006562: 68fb ldr r3, [r7, #12] + 8006564: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006566: 4a25 ldr r2, [pc, #148] @ (80065fc ) + 8006568: 64da str r2, [r3, #76] @ 0x4c + 800656a: 68fb ldr r3, [r7, #12] + 800656c: 6b9b ldr r3, [r3, #56] @ 0x38 + 800656e: 2200 movs r2, #0 + 8006570: 651a str r2, [r3, #80] @ 0x50 + 8006572: f107 0308 add.w r3, r7, #8 + 8006576: 62fb str r3, [r7, #44] @ 0x2c + 8006578: 68fb ldr r3, [r7, #12] + 800657a: 6b98 ldr r0, [r3, #56] @ 0x38 + 800657c: 6afb ldr r3, [r7, #44] @ 0x2c + 800657e: 6819 ldr r1, [r3, #0] + 8006580: 68fb ldr r3, [r7, #12] + 8006582: 681b ldr r3, [r3, #0] + 8006584: 3304 adds r3, #4 + 8006586: 461a mov r2, r3 + 8006588: 88fb ldrh r3, [r7, #6] + 800658a: f7fb febd bl 8002308 + 800658e: 4603 mov r3, r0 + 8006590: 2b00 cmp r3, #0 + 8006592: d008 beq.n 80065a6 + 8006594: 68fb ldr r3, [r7, #12] + 8006596: 2210 movs r2, #16 + 8006598: 645a str r2, [r3, #68] @ 0x44 + 800659a: 68fb ldr r3, [r7, #12] + 800659c: 2220 movs r2, #32 + 800659e: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 80065a2: 2301 movs r3, #1 + 80065a4: e021 b.n 80065ea + 80065a6: 68fb ldr r3, [r7, #12] + 80065a8: 681b ldr r3, [r3, #0] + 80065aa: f06f 0240 mvn.w r2, #64 @ 0x40 + 80065ae: 601a str r2, [r3, #0] + 80065b0: 68fb ldr r3, [r7, #12] + 80065b2: 681b ldr r3, [r3, #0] + 80065b4: 3314 adds r3, #20 + 80065b6: 61bb str r3, [r7, #24] + 80065b8: 69bb ldr r3, [r7, #24] + 80065ba: e853 3f00 ldrex r3, [r3] + 80065be: 617b str r3, [r7, #20] + 80065c0: 697b ldr r3, [r7, #20] + 80065c2: f043 0380 orr.w r3, r3, #128 @ 0x80 + 80065c6: 62bb str r3, [r7, #40] @ 0x28 + 80065c8: 68fb ldr r3, [r7, #12] + 80065ca: 681b ldr r3, [r3, #0] + 80065cc: 3314 adds r3, #20 + 80065ce: 6aba ldr r2, [r7, #40] @ 0x28 + 80065d0: 627a str r2, [r7, #36] @ 0x24 + 80065d2: 623b str r3, [r7, #32] + 80065d4: 6a39 ldr r1, [r7, #32] + 80065d6: 6a7a ldr r2, [r7, #36] @ 0x24 + 80065d8: e841 2300 strex r3, r2, [r1] + 80065dc: 61fb str r3, [r7, #28] + 80065de: 69fb ldr r3, [r7, #28] + 80065e0: 2b00 cmp r3, #0 + 80065e2: d1e5 bne.n 80065b0 + 80065e4: 2300 movs r3, #0 + 80065e6: e000 b.n 80065ea + 80065e8: 2302 movs r3, #2 + 80065ea: 4618 mov r0, r3 + 80065ec: 3730 adds r7, #48 @ 0x30 + 80065ee: 46bd mov sp, r7 + 80065f0: bd80 pop {r7, pc} + 80065f2: bf00 nop + 80065f4: 08006bf5 .word 0x08006bf5 + 80065f8: 08006c8f .word 0x08006c8f + 80065fc: 08006e13 .word 0x08006e13 + +08006600 : + 8006600: b580 push {r7, lr} + 8006602: b084 sub sp, #16 + 8006604: af00 add r7, sp, #0 + 8006606: 60f8 str r0, [r7, #12] + 8006608: 60b9 str r1, [r7, #8] + 800660a: 4613 mov r3, r2 + 800660c: 80fb strh r3, [r7, #6] + 800660e: 68fb ldr r3, [r7, #12] + 8006610: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 + 8006614: b2db uxtb r3, r3 + 8006616: 2b20 cmp r3, #32 + 8006618: d112 bne.n 8006640 + 800661a: 68bb ldr r3, [r7, #8] + 800661c: 2b00 cmp r3, #0 + 800661e: d002 beq.n 8006626 + 8006620: 88fb ldrh r3, [r7, #6] + 8006622: 2b00 cmp r3, #0 + 8006624: d101 bne.n 800662a + 8006626: 2301 movs r3, #1 + 8006628: e00b b.n 8006642 + 800662a: 68fb ldr r3, [r7, #12] + 800662c: 2200 movs r2, #0 + 800662e: 631a str r2, [r3, #48] @ 0x30 + 8006630: 88fb ldrh r3, [r7, #6] + 8006632: 461a mov r2, r3 + 8006634: 68b9 ldr r1, [r7, #8] + 8006636: 68f8 ldr r0, [r7, #12] + 8006638: f000 fc36 bl 8006ea8 + 800663c: 4603 mov r3, r0 + 800663e: e000 b.n 8006642 + 8006640: 2302 movs r3, #2 + 8006642: 4618 mov r0, r3 + 8006644: 3710 adds r7, #16 + 8006646: 46bd mov sp, r7 + 8006648: bd80 pop {r7, pc} + ... + +0800664c : + 800664c: b580 push {r7, lr} + 800664e: b0ba sub sp, #232 @ 0xe8 + 8006650: af00 add r7, sp, #0 + 8006652: 6078 str r0, [r7, #4] + 8006654: 687b ldr r3, [r7, #4] + 8006656: 681b ldr r3, [r3, #0] + 8006658: 681b ldr r3, [r3, #0] + 800665a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 + 800665e: 687b ldr r3, [r7, #4] + 8006660: 681b ldr r3, [r3, #0] + 8006662: 68db ldr r3, [r3, #12] + 8006664: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 + 8006668: 687b ldr r3, [r7, #4] + 800666a: 681b ldr r3, [r3, #0] + 800666c: 695b ldr r3, [r3, #20] + 800666e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc + 8006672: 2300 movs r3, #0 + 8006674: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 + 8006678: 2300 movs r3, #0 + 800667a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 + 800667e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8006682: f003 030f and.w r3, r3, #15 + 8006686: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 + 800668a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 + 800668e: 2b00 cmp r3, #0 + 8006690: d10f bne.n 80066b2 + 8006692: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8006696: f003 0320 and.w r3, r3, #32 + 800669a: 2b00 cmp r3, #0 + 800669c: d009 beq.n 80066b2 + 800669e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80066a2: f003 0320 and.w r3, r3, #32 + 80066a6: 2b00 cmp r3, #0 + 80066a8: d003 beq.n 80066b2 + 80066aa: 6878 ldr r0, [r7, #4] + 80066ac: f000 fda6 bl 80071fc + 80066b0: e273 b.n 8006b9a + 80066b2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 + 80066b6: 2b00 cmp r3, #0 + 80066b8: f000 80de beq.w 8006878 + 80066bc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 80066c0: f003 0301 and.w r3, r3, #1 + 80066c4: 2b00 cmp r3, #0 + 80066c6: d106 bne.n 80066d6 + 80066c8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80066cc: f403 7390 and.w r3, r3, #288 @ 0x120 + 80066d0: 2b00 cmp r3, #0 + 80066d2: f000 80d1 beq.w 8006878 + 80066d6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80066da: f003 0301 and.w r3, r3, #1 + 80066de: 2b00 cmp r3, #0 + 80066e0: d00b beq.n 80066fa + 80066e2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80066e6: f403 7380 and.w r3, r3, #256 @ 0x100 + 80066ea: 2b00 cmp r3, #0 + 80066ec: d005 beq.n 80066fa + 80066ee: 687b ldr r3, [r7, #4] + 80066f0: 6c5b ldr r3, [r3, #68] @ 0x44 + 80066f2: f043 0201 orr.w r2, r3, #1 + 80066f6: 687b ldr r3, [r7, #4] + 80066f8: 645a str r2, [r3, #68] @ 0x44 + 80066fa: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80066fe: f003 0304 and.w r3, r3, #4 + 8006702: 2b00 cmp r3, #0 + 8006704: d00b beq.n 800671e + 8006706: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 800670a: f003 0301 and.w r3, r3, #1 + 800670e: 2b00 cmp r3, #0 + 8006710: d005 beq.n 800671e + 8006712: 687b ldr r3, [r7, #4] + 8006714: 6c5b ldr r3, [r3, #68] @ 0x44 + 8006716: f043 0202 orr.w r2, r3, #2 + 800671a: 687b ldr r3, [r7, #4] + 800671c: 645a str r2, [r3, #68] @ 0x44 + 800671e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8006722: f003 0302 and.w r3, r3, #2 + 8006726: 2b00 cmp r3, #0 + 8006728: d00b beq.n 8006742 + 800672a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 800672e: f003 0301 and.w r3, r3, #1 + 8006732: 2b00 cmp r3, #0 + 8006734: d005 beq.n 8006742 + 8006736: 687b ldr r3, [r7, #4] + 8006738: 6c5b ldr r3, [r3, #68] @ 0x44 + 800673a: f043 0204 orr.w r2, r3, #4 + 800673e: 687b ldr r3, [r7, #4] + 8006740: 645a str r2, [r3, #68] @ 0x44 + 8006742: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8006746: f003 0308 and.w r3, r3, #8 + 800674a: 2b00 cmp r3, #0 + 800674c: d011 beq.n 8006772 + 800674e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8006752: f003 0320 and.w r3, r3, #32 + 8006756: 2b00 cmp r3, #0 + 8006758: d105 bne.n 8006766 + 800675a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 800675e: f003 0301 and.w r3, r3, #1 + 8006762: 2b00 cmp r3, #0 + 8006764: d005 beq.n 8006772 + 8006766: 687b ldr r3, [r7, #4] + 8006768: 6c5b ldr r3, [r3, #68] @ 0x44 + 800676a: f043 0208 orr.w r2, r3, #8 + 800676e: 687b ldr r3, [r7, #4] + 8006770: 645a str r2, [r3, #68] @ 0x44 + 8006772: 687b ldr r3, [r7, #4] + 8006774: 6c5b ldr r3, [r3, #68] @ 0x44 + 8006776: 2b00 cmp r3, #0 + 8006778: f000 820a beq.w 8006b90 + 800677c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8006780: f003 0320 and.w r3, r3, #32 + 8006784: 2b00 cmp r3, #0 + 8006786: d008 beq.n 800679a + 8006788: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 800678c: f003 0320 and.w r3, r3, #32 + 8006790: 2b00 cmp r3, #0 + 8006792: d002 beq.n 800679a + 8006794: 6878 ldr r0, [r7, #4] + 8006796: f000 fd31 bl 80071fc + 800679a: 687b ldr r3, [r7, #4] + 800679c: 681b ldr r3, [r3, #0] + 800679e: 695b ldr r3, [r3, #20] + 80067a0: f003 0340 and.w r3, r3, #64 @ 0x40 + 80067a4: 2b40 cmp r3, #64 @ 0x40 + 80067a6: bf0c ite eq + 80067a8: 2301 moveq r3, #1 + 80067aa: 2300 movne r3, #0 + 80067ac: b2db uxtb r3, r3 + 80067ae: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 + 80067b2: 687b ldr r3, [r7, #4] + 80067b4: 6c5b ldr r3, [r3, #68] @ 0x44 + 80067b6: f003 0308 and.w r3, r3, #8 + 80067ba: 2b00 cmp r3, #0 + 80067bc: d103 bne.n 80067c6 + 80067be: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 + 80067c2: 2b00 cmp r3, #0 + 80067c4: d04f beq.n 8006866 + 80067c6: 6878 ldr r0, [r7, #4] + 80067c8: f000 fc3c bl 8007044 + 80067cc: 687b ldr r3, [r7, #4] + 80067ce: 681b ldr r3, [r3, #0] + 80067d0: 695b ldr r3, [r3, #20] + 80067d2: f003 0340 and.w r3, r3, #64 @ 0x40 + 80067d6: 2b40 cmp r3, #64 @ 0x40 + 80067d8: d141 bne.n 800685e + 80067da: 687b ldr r3, [r7, #4] + 80067dc: 681b ldr r3, [r3, #0] + 80067de: 3314 adds r3, #20 + 80067e0: f8c7 309c str.w r3, [r7, #156] @ 0x9c + 80067e4: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c + 80067e8: e853 3f00 ldrex r3, [r3] + 80067ec: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + 80067f0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 + 80067f4: f023 0340 bic.w r3, r3, #64 @ 0x40 + 80067f8: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 + 80067fc: 687b ldr r3, [r7, #4] + 80067fe: 681b ldr r3, [r3, #0] + 8006800: 3314 adds r3, #20 + 8006802: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 + 8006806: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 + 800680a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 + 800680e: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 + 8006812: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 + 8006816: e841 2300 strex r3, r2, [r1] + 800681a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + 800681e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 8006822: 2b00 cmp r3, #0 + 8006824: d1d9 bne.n 80067da + 8006826: 687b ldr r3, [r7, #4] + 8006828: 6bdb ldr r3, [r3, #60] @ 0x3c + 800682a: 2b00 cmp r3, #0 + 800682c: d013 beq.n 8006856 + 800682e: 687b ldr r3, [r7, #4] + 8006830: 6bdb ldr r3, [r3, #60] @ 0x3c + 8006832: 4a8a ldr r2, [pc, #552] @ (8006a5c ) + 8006834: 651a str r2, [r3, #80] @ 0x50 + 8006836: 687b ldr r3, [r7, #4] + 8006838: 6bdb ldr r3, [r3, #60] @ 0x3c + 800683a: 4618 mov r0, r3 + 800683c: f7fb fe2c bl 8002498 + 8006840: 4603 mov r3, r0 + 8006842: 2b00 cmp r3, #0 + 8006844: d016 beq.n 8006874 + 8006846: 687b ldr r3, [r7, #4] + 8006848: 6bdb ldr r3, [r3, #60] @ 0x3c + 800684a: 6d1b ldr r3, [r3, #80] @ 0x50 + 800684c: 687a ldr r2, [r7, #4] + 800684e: 6bd2 ldr r2, [r2, #60] @ 0x3c + 8006850: 4610 mov r0, r2 + 8006852: 4798 blx r3 + 8006854: e00e b.n 8006874 + 8006856: 6878 ldr r0, [r7, #4] + 8006858: f7fa fab0 bl 8000dbc + 800685c: e00a b.n 8006874 + 800685e: 6878 ldr r0, [r7, #4] + 8006860: f7fa faac bl 8000dbc + 8006864: e006 b.n 8006874 + 8006866: 6878 ldr r0, [r7, #4] + 8006868: f7fa faa8 bl 8000dbc + 800686c: 687b ldr r3, [r7, #4] + 800686e: 2200 movs r2, #0 + 8006870: 645a str r2, [r3, #68] @ 0x44 + 8006872: e18d b.n 8006b90 + 8006874: bf00 nop + 8006876: e18b b.n 8006b90 + 8006878: 687b ldr r3, [r7, #4] + 800687a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800687c: 2b01 cmp r3, #1 + 800687e: f040 8167 bne.w 8006b50 + 8006882: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8006886: f003 0310 and.w r3, r3, #16 + 800688a: 2b00 cmp r3, #0 + 800688c: f000 8160 beq.w 8006b50 + 8006890: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8006894: f003 0310 and.w r3, r3, #16 + 8006898: 2b00 cmp r3, #0 + 800689a: f000 8159 beq.w 8006b50 + 800689e: 2300 movs r3, #0 + 80068a0: 60bb str r3, [r7, #8] + 80068a2: 687b ldr r3, [r7, #4] + 80068a4: 681b ldr r3, [r3, #0] + 80068a6: 681b ldr r3, [r3, #0] + 80068a8: 60bb str r3, [r7, #8] + 80068aa: 687b ldr r3, [r7, #4] + 80068ac: 681b ldr r3, [r3, #0] + 80068ae: 685b ldr r3, [r3, #4] + 80068b0: 60bb str r3, [r7, #8] + 80068b2: 68bb ldr r3, [r7, #8] + 80068b4: 687b ldr r3, [r7, #4] + 80068b6: 681b ldr r3, [r3, #0] + 80068b8: 695b ldr r3, [r3, #20] + 80068ba: f003 0340 and.w r3, r3, #64 @ 0x40 + 80068be: 2b40 cmp r3, #64 @ 0x40 + 80068c0: f040 80ce bne.w 8006a60 + 80068c4: 687b ldr r3, [r7, #4] + 80068c6: 6bdb ldr r3, [r3, #60] @ 0x3c + 80068c8: 681b ldr r3, [r3, #0] + 80068ca: 685b ldr r3, [r3, #4] + 80068cc: f8a7 30be strh.w r3, [r7, #190] @ 0xbe + 80068d0: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe + 80068d4: 2b00 cmp r3, #0 + 80068d6: f000 80a9 beq.w 8006a2c + 80068da: 687b ldr r3, [r7, #4] + 80068dc: 8d9b ldrh r3, [r3, #44] @ 0x2c + 80068de: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 80068e2: 429a cmp r2, r3 + 80068e4: f080 80a2 bcs.w 8006a2c + 80068e8: 687b ldr r3, [r7, #4] + 80068ea: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 80068ee: 85da strh r2, [r3, #46] @ 0x2e + 80068f0: 687b ldr r3, [r7, #4] + 80068f2: 6bdb ldr r3, [r3, #60] @ 0x3c + 80068f4: 69db ldr r3, [r3, #28] + 80068f6: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 80068fa: f000 8088 beq.w 8006a0e + 80068fe: 687b ldr r3, [r7, #4] + 8006900: 681b ldr r3, [r3, #0] + 8006902: 330c adds r3, #12 + 8006904: f8c7 3088 str.w r3, [r7, #136] @ 0x88 + 8006908: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 + 800690c: e853 3f00 ldrex r3, [r3] + 8006910: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 8006914: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 8006918: f423 7380 bic.w r3, r3, #256 @ 0x100 + 800691c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 + 8006920: 687b ldr r3, [r7, #4] + 8006922: 681b ldr r3, [r3, #0] + 8006924: 330c adds r3, #12 + 8006926: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 + 800692a: f8c7 2094 str.w r2, [r7, #148] @ 0x94 + 800692e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 + 8006932: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 + 8006936: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 + 800693a: e841 2300 strex r3, r2, [r1] + 800693e: f8c7 308c str.w r3, [r7, #140] @ 0x8c + 8006942: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c + 8006946: 2b00 cmp r3, #0 + 8006948: d1d9 bne.n 80068fe + 800694a: 687b ldr r3, [r7, #4] + 800694c: 681b ldr r3, [r3, #0] + 800694e: 3314 adds r3, #20 + 8006950: 677b str r3, [r7, #116] @ 0x74 + 8006952: 6f7b ldr r3, [r7, #116] @ 0x74 + 8006954: e853 3f00 ldrex r3, [r3] + 8006958: 673b str r3, [r7, #112] @ 0x70 + 800695a: 6f3b ldr r3, [r7, #112] @ 0x70 + 800695c: f023 0301 bic.w r3, r3, #1 + 8006960: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 8006964: 687b ldr r3, [r7, #4] + 8006966: 681b ldr r3, [r3, #0] + 8006968: 3314 adds r3, #20 + 800696a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 + 800696e: f8c7 2080 str.w r2, [r7, #128] @ 0x80 + 8006972: 67fb str r3, [r7, #124] @ 0x7c + 8006974: 6ff9 ldr r1, [r7, #124] @ 0x7c + 8006976: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 + 800697a: e841 2300 strex r3, r2, [r1] + 800697e: 67bb str r3, [r7, #120] @ 0x78 + 8006980: 6fbb ldr r3, [r7, #120] @ 0x78 + 8006982: 2b00 cmp r3, #0 + 8006984: d1e1 bne.n 800694a + 8006986: 687b ldr r3, [r7, #4] + 8006988: 681b ldr r3, [r3, #0] + 800698a: 3314 adds r3, #20 + 800698c: 663b str r3, [r7, #96] @ 0x60 + 800698e: 6e3b ldr r3, [r7, #96] @ 0x60 + 8006990: e853 3f00 ldrex r3, [r3] + 8006994: 65fb str r3, [r7, #92] @ 0x5c + 8006996: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006998: f023 0340 bic.w r3, r3, #64 @ 0x40 + 800699c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 80069a0: 687b ldr r3, [r7, #4] + 80069a2: 681b ldr r3, [r3, #0] + 80069a4: 3314 adds r3, #20 + 80069a6: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 + 80069aa: 66fa str r2, [r7, #108] @ 0x6c + 80069ac: 66bb str r3, [r7, #104] @ 0x68 + 80069ae: 6eb9 ldr r1, [r7, #104] @ 0x68 + 80069b0: 6efa ldr r2, [r7, #108] @ 0x6c + 80069b2: e841 2300 strex r3, r2, [r1] + 80069b6: 667b str r3, [r7, #100] @ 0x64 + 80069b8: 6e7b ldr r3, [r7, #100] @ 0x64 + 80069ba: 2b00 cmp r3, #0 + 80069bc: d1e3 bne.n 8006986 + 80069be: 687b ldr r3, [r7, #4] + 80069c0: 2220 movs r2, #32 + 80069c2: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 80069c6: 687b ldr r3, [r7, #4] + 80069c8: 2200 movs r2, #0 + 80069ca: 631a str r2, [r3, #48] @ 0x30 + 80069cc: 687b ldr r3, [r7, #4] + 80069ce: 681b ldr r3, [r3, #0] + 80069d0: 330c adds r3, #12 + 80069d2: 64fb str r3, [r7, #76] @ 0x4c + 80069d4: 6cfb ldr r3, [r7, #76] @ 0x4c + 80069d6: e853 3f00 ldrex r3, [r3] + 80069da: 64bb str r3, [r7, #72] @ 0x48 + 80069dc: 6cbb ldr r3, [r7, #72] @ 0x48 + 80069de: f023 0310 bic.w r3, r3, #16 + 80069e2: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 80069e6: 687b ldr r3, [r7, #4] + 80069e8: 681b ldr r3, [r3, #0] + 80069ea: 330c adds r3, #12 + 80069ec: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac + 80069f0: 65ba str r2, [r7, #88] @ 0x58 + 80069f2: 657b str r3, [r7, #84] @ 0x54 + 80069f4: 6d79 ldr r1, [r7, #84] @ 0x54 + 80069f6: 6dba ldr r2, [r7, #88] @ 0x58 + 80069f8: e841 2300 strex r3, r2, [r1] + 80069fc: 653b str r3, [r7, #80] @ 0x50 + 80069fe: 6d3b ldr r3, [r7, #80] @ 0x50 + 8006a00: 2b00 cmp r3, #0 + 8006a02: d1e3 bne.n 80069cc + 8006a04: 687b ldr r3, [r7, #4] + 8006a06: 6bdb ldr r3, [r3, #60] @ 0x3c + 8006a08: 4618 mov r0, r3 + 8006a0a: f7fb fcd5 bl 80023b8 + 8006a0e: 687b ldr r3, [r7, #4] + 8006a10: 2202 movs r2, #2 + 8006a12: 635a str r2, [r3, #52] @ 0x34 + 8006a14: 687b ldr r3, [r7, #4] + 8006a16: 8d9a ldrh r2, [r3, #44] @ 0x2c + 8006a18: 687b ldr r3, [r7, #4] + 8006a1a: 8ddb ldrh r3, [r3, #46] @ 0x2e + 8006a1c: b29b uxth r3, r3 + 8006a1e: 1ad3 subs r3, r2, r3 + 8006a20: b29b uxth r3, r3 + 8006a22: 4619 mov r1, r3 + 8006a24: 6878 ldr r0, [r7, #4] + 8006a26: f000 f8d9 bl 8006bdc + 8006a2a: e0b3 b.n 8006b94 + 8006a2c: 687b ldr r3, [r7, #4] + 8006a2e: 8d9b ldrh r3, [r3, #44] @ 0x2c + 8006a30: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 8006a34: 429a cmp r2, r3 + 8006a36: f040 80ad bne.w 8006b94 + 8006a3a: 687b ldr r3, [r7, #4] + 8006a3c: 6bdb ldr r3, [r3, #60] @ 0x3c + 8006a3e: 69db ldr r3, [r3, #28] + 8006a40: f5b3 7f80 cmp.w r3, #256 @ 0x100 + 8006a44: f040 80a6 bne.w 8006b94 + 8006a48: 687b ldr r3, [r7, #4] + 8006a4a: 2202 movs r2, #2 + 8006a4c: 635a str r2, [r3, #52] @ 0x34 + 8006a4e: 687b ldr r3, [r7, #4] + 8006a50: 8d9b ldrh r3, [r3, #44] @ 0x2c + 8006a52: 4619 mov r1, r3 + 8006a54: 6878 ldr r0, [r7, #4] + 8006a56: f000 f8c1 bl 8006bdc + 8006a5a: e09b b.n 8006b94 + 8006a5c: 0800710b .word 0x0800710b + 8006a60: 687b ldr r3, [r7, #4] + 8006a62: 8d9a ldrh r2, [r3, #44] @ 0x2c + 8006a64: 687b ldr r3, [r7, #4] + 8006a66: 8ddb ldrh r3, [r3, #46] @ 0x2e + 8006a68: b29b uxth r3, r3 + 8006a6a: 1ad3 subs r3, r2, r3 + 8006a6c: f8a7 30ce strh.w r3, [r7, #206] @ 0xce + 8006a70: 687b ldr r3, [r7, #4] + 8006a72: 8ddb ldrh r3, [r3, #46] @ 0x2e + 8006a74: b29b uxth r3, r3 + 8006a76: 2b00 cmp r3, #0 + 8006a78: f000 808e beq.w 8006b98 + 8006a7c: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce + 8006a80: 2b00 cmp r3, #0 + 8006a82: f000 8089 beq.w 8006b98 + 8006a86: 687b ldr r3, [r7, #4] + 8006a88: 681b ldr r3, [r3, #0] + 8006a8a: 330c adds r3, #12 + 8006a8c: 63bb str r3, [r7, #56] @ 0x38 + 8006a8e: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006a90: e853 3f00 ldrex r3, [r3] + 8006a94: 637b str r3, [r7, #52] @ 0x34 + 8006a96: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006a98: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8006a9c: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 + 8006aa0: 687b ldr r3, [r7, #4] + 8006aa2: 681b ldr r3, [r3, #0] + 8006aa4: 330c adds r3, #12 + 8006aa6: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 + 8006aaa: 647a str r2, [r7, #68] @ 0x44 + 8006aac: 643b str r3, [r7, #64] @ 0x40 + 8006aae: 6c39 ldr r1, [r7, #64] @ 0x40 + 8006ab0: 6c7a ldr r2, [r7, #68] @ 0x44 + 8006ab2: e841 2300 strex r3, r2, [r1] + 8006ab6: 63fb str r3, [r7, #60] @ 0x3c + 8006ab8: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006aba: 2b00 cmp r3, #0 + 8006abc: d1e3 bne.n 8006a86 + 8006abe: 687b ldr r3, [r7, #4] + 8006ac0: 681b ldr r3, [r3, #0] + 8006ac2: 3314 adds r3, #20 + 8006ac4: 627b str r3, [r7, #36] @ 0x24 + 8006ac6: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006ac8: e853 3f00 ldrex r3, [r3] + 8006acc: 623b str r3, [r7, #32] + 8006ace: 6a3b ldr r3, [r7, #32] + 8006ad0: f023 0301 bic.w r3, r3, #1 + 8006ad4: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 + 8006ad8: 687b ldr r3, [r7, #4] + 8006ada: 681b ldr r3, [r3, #0] + 8006adc: 3314 adds r3, #20 + 8006ade: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 + 8006ae2: 633a str r2, [r7, #48] @ 0x30 + 8006ae4: 62fb str r3, [r7, #44] @ 0x2c + 8006ae6: 6af9 ldr r1, [r7, #44] @ 0x2c + 8006ae8: 6b3a ldr r2, [r7, #48] @ 0x30 + 8006aea: e841 2300 strex r3, r2, [r1] + 8006aee: 62bb str r3, [r7, #40] @ 0x28 + 8006af0: 6abb ldr r3, [r7, #40] @ 0x28 + 8006af2: 2b00 cmp r3, #0 + 8006af4: d1e3 bne.n 8006abe + 8006af6: 687b ldr r3, [r7, #4] + 8006af8: 2220 movs r2, #32 + 8006afa: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8006afe: 687b ldr r3, [r7, #4] + 8006b00: 2200 movs r2, #0 + 8006b02: 631a str r2, [r3, #48] @ 0x30 + 8006b04: 687b ldr r3, [r7, #4] + 8006b06: 681b ldr r3, [r3, #0] + 8006b08: 330c adds r3, #12 + 8006b0a: 613b str r3, [r7, #16] + 8006b0c: 693b ldr r3, [r7, #16] + 8006b0e: e853 3f00 ldrex r3, [r3] + 8006b12: 60fb str r3, [r7, #12] + 8006b14: 68fb ldr r3, [r7, #12] + 8006b16: f023 0310 bic.w r3, r3, #16 + 8006b1a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 + 8006b1e: 687b ldr r3, [r7, #4] + 8006b20: 681b ldr r3, [r3, #0] + 8006b22: 330c adds r3, #12 + 8006b24: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 + 8006b28: 61fa str r2, [r7, #28] + 8006b2a: 61bb str r3, [r7, #24] + 8006b2c: 69b9 ldr r1, [r7, #24] + 8006b2e: 69fa ldr r2, [r7, #28] + 8006b30: e841 2300 strex r3, r2, [r1] + 8006b34: 617b str r3, [r7, #20] + 8006b36: 697b ldr r3, [r7, #20] + 8006b38: 2b00 cmp r3, #0 + 8006b3a: d1e3 bne.n 8006b04 + 8006b3c: 687b ldr r3, [r7, #4] + 8006b3e: 2202 movs r2, #2 + 8006b40: 635a str r2, [r3, #52] @ 0x34 + 8006b42: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce + 8006b46: 4619 mov r1, r3 + 8006b48: 6878 ldr r0, [r7, #4] + 8006b4a: f000 f847 bl 8006bdc + 8006b4e: e023 b.n 8006b98 + 8006b50: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8006b54: f003 0380 and.w r3, r3, #128 @ 0x80 + 8006b58: 2b00 cmp r3, #0 + 8006b5a: d009 beq.n 8006b70 + 8006b5c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8006b60: f003 0380 and.w r3, r3, #128 @ 0x80 + 8006b64: 2b00 cmp r3, #0 + 8006b66: d003 beq.n 8006b70 + 8006b68: 6878 ldr r0, [r7, #4] + 8006b6a: f000 fadf bl 800712c + 8006b6e: e014 b.n 8006b9a + 8006b70: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8006b74: f003 0340 and.w r3, r3, #64 @ 0x40 + 8006b78: 2b00 cmp r3, #0 + 8006b7a: d00e beq.n 8006b9a + 8006b7c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8006b80: f003 0340 and.w r3, r3, #64 @ 0x40 + 8006b84: 2b00 cmp r3, #0 + 8006b86: d008 beq.n 8006b9a + 8006b88: 6878 ldr r0, [r7, #4] + 8006b8a: f000 fb1f bl 80071cc + 8006b8e: e004 b.n 8006b9a + 8006b90: bf00 nop + 8006b92: e002 b.n 8006b9a + 8006b94: bf00 nop + 8006b96: e000 b.n 8006b9a + 8006b98: bf00 nop + 8006b9a: 37e8 adds r7, #232 @ 0xe8 + 8006b9c: 46bd mov sp, r7 + 8006b9e: bd80 pop {r7, pc} + +08006ba0 : + 8006ba0: b480 push {r7} + 8006ba2: b083 sub sp, #12 + 8006ba4: af00 add r7, sp, #0 + 8006ba6: 6078 str r0, [r7, #4] + 8006ba8: bf00 nop + 8006baa: 370c adds r7, #12 + 8006bac: 46bd mov sp, r7 + 8006bae: f85d 7b04 ldr.w r7, [sp], #4 + 8006bb2: 4770 bx lr + +08006bb4 : + 8006bb4: b480 push {r7} + 8006bb6: b083 sub sp, #12 + 8006bb8: af00 add r7, sp, #0 + 8006bba: 6078 str r0, [r7, #4] + 8006bbc: bf00 nop + 8006bbe: 370c adds r7, #12 + 8006bc0: 46bd mov sp, r7 + 8006bc2: f85d 7b04 ldr.w r7, [sp], #4 + 8006bc6: 4770 bx lr + +08006bc8 : + 8006bc8: b480 push {r7} + 8006bca: b083 sub sp, #12 + 8006bcc: af00 add r7, sp, #0 + 8006bce: 6078 str r0, [r7, #4] + 8006bd0: bf00 nop + 8006bd2: 370c adds r7, #12 + 8006bd4: 46bd mov sp, r7 + 8006bd6: f85d 7b04 ldr.w r7, [sp], #4 + 8006bda: 4770 bx lr + +08006bdc : + 8006bdc: b480 push {r7} + 8006bde: b083 sub sp, #12 + 8006be0: af00 add r7, sp, #0 + 8006be2: 6078 str r0, [r7, #4] + 8006be4: 460b mov r3, r1 + 8006be6: 807b strh r3, [r7, #2] + 8006be8: bf00 nop + 8006bea: 370c adds r7, #12 + 8006bec: 46bd mov sp, r7 + 8006bee: f85d 7b04 ldr.w r7, [sp], #4 + 8006bf2: 4770 bx lr + +08006bf4 : + 8006bf4: b580 push {r7, lr} + 8006bf6: b090 sub sp, #64 @ 0x40 + 8006bf8: af00 add r7, sp, #0 + 8006bfa: 6078 str r0, [r7, #4] + 8006bfc: 687b ldr r3, [r7, #4] + 8006bfe: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006c00: 63fb str r3, [r7, #60] @ 0x3c + 8006c02: 687b ldr r3, [r7, #4] + 8006c04: 681b ldr r3, [r3, #0] + 8006c06: 681b ldr r3, [r3, #0] + 8006c08: f403 7380 and.w r3, r3, #256 @ 0x100 + 8006c0c: 2b00 cmp r3, #0 + 8006c0e: d137 bne.n 8006c80 + 8006c10: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006c12: 2200 movs r2, #0 + 8006c14: 84da strh r2, [r3, #38] @ 0x26 + 8006c16: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006c18: 681b ldr r3, [r3, #0] + 8006c1a: 3314 adds r3, #20 + 8006c1c: 627b str r3, [r7, #36] @ 0x24 + 8006c1e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006c20: e853 3f00 ldrex r3, [r3] + 8006c24: 623b str r3, [r7, #32] + 8006c26: 6a3b ldr r3, [r7, #32] + 8006c28: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8006c2c: 63bb str r3, [r7, #56] @ 0x38 + 8006c2e: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006c30: 681b ldr r3, [r3, #0] + 8006c32: 3314 adds r3, #20 + 8006c34: 6bba ldr r2, [r7, #56] @ 0x38 + 8006c36: 633a str r2, [r7, #48] @ 0x30 + 8006c38: 62fb str r3, [r7, #44] @ 0x2c + 8006c3a: 6af9 ldr r1, [r7, #44] @ 0x2c + 8006c3c: 6b3a ldr r2, [r7, #48] @ 0x30 + 8006c3e: e841 2300 strex r3, r2, [r1] + 8006c42: 62bb str r3, [r7, #40] @ 0x28 + 8006c44: 6abb ldr r3, [r7, #40] @ 0x28 + 8006c46: 2b00 cmp r3, #0 + 8006c48: d1e5 bne.n 8006c16 + 8006c4a: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006c4c: 681b ldr r3, [r3, #0] + 8006c4e: 330c adds r3, #12 + 8006c50: 613b str r3, [r7, #16] + 8006c52: 693b ldr r3, [r7, #16] + 8006c54: e853 3f00 ldrex r3, [r3] + 8006c58: 60fb str r3, [r7, #12] + 8006c5a: 68fb ldr r3, [r7, #12] + 8006c5c: f043 0340 orr.w r3, r3, #64 @ 0x40 + 8006c60: 637b str r3, [r7, #52] @ 0x34 + 8006c62: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006c64: 681b ldr r3, [r3, #0] + 8006c66: 330c adds r3, #12 + 8006c68: 6b7a ldr r2, [r7, #52] @ 0x34 + 8006c6a: 61fa str r2, [r7, #28] + 8006c6c: 61bb str r3, [r7, #24] + 8006c6e: 69b9 ldr r1, [r7, #24] + 8006c70: 69fa ldr r2, [r7, #28] + 8006c72: e841 2300 strex r3, r2, [r1] + 8006c76: 617b str r3, [r7, #20] + 8006c78: 697b ldr r3, [r7, #20] + 8006c7a: 2b00 cmp r3, #0 + 8006c7c: d1e5 bne.n 8006c4a + 8006c7e: e002 b.n 8006c86 + 8006c80: 6bf8 ldr r0, [r7, #60] @ 0x3c + 8006c82: f7ff ff8d bl 8006ba0 + 8006c86: bf00 nop + 8006c88: 3740 adds r7, #64 @ 0x40 + 8006c8a: 46bd mov sp, r7 + 8006c8c: bd80 pop {r7, pc} + +08006c8e : + 8006c8e: b580 push {r7, lr} + 8006c90: b084 sub sp, #16 + 8006c92: af00 add r7, sp, #0 + 8006c94: 6078 str r0, [r7, #4] + 8006c96: 687b ldr r3, [r7, #4] + 8006c98: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006c9a: 60fb str r3, [r7, #12] + 8006c9c: 68f8 ldr r0, [r7, #12] + 8006c9e: f7ff ff89 bl 8006bb4 + 8006ca2: bf00 nop + 8006ca4: 3710 adds r7, #16 + 8006ca6: 46bd mov sp, r7 + 8006ca8: bd80 pop {r7, pc} + +08006caa : + 8006caa: b580 push {r7, lr} + 8006cac: b09c sub sp, #112 @ 0x70 + 8006cae: af00 add r7, sp, #0 + 8006cb0: 6078 str r0, [r7, #4] + 8006cb2: 687b ldr r3, [r7, #4] + 8006cb4: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006cb6: 66fb str r3, [r7, #108] @ 0x6c + 8006cb8: 687b ldr r3, [r7, #4] + 8006cba: 681b ldr r3, [r3, #0] + 8006cbc: 681b ldr r3, [r3, #0] + 8006cbe: f403 7380 and.w r3, r3, #256 @ 0x100 + 8006cc2: 2b00 cmp r3, #0 + 8006cc4: d172 bne.n 8006dac + 8006cc6: 6efb ldr r3, [r7, #108] @ 0x6c + 8006cc8: 2200 movs r2, #0 + 8006cca: 85da strh r2, [r3, #46] @ 0x2e + 8006ccc: 6efb ldr r3, [r7, #108] @ 0x6c + 8006cce: 681b ldr r3, [r3, #0] + 8006cd0: 330c adds r3, #12 + 8006cd2: 64fb str r3, [r7, #76] @ 0x4c + 8006cd4: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006cd6: e853 3f00 ldrex r3, [r3] + 8006cda: 64bb str r3, [r7, #72] @ 0x48 + 8006cdc: 6cbb ldr r3, [r7, #72] @ 0x48 + 8006cde: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8006ce2: 66bb str r3, [r7, #104] @ 0x68 + 8006ce4: 6efb ldr r3, [r7, #108] @ 0x6c + 8006ce6: 681b ldr r3, [r3, #0] + 8006ce8: 330c adds r3, #12 + 8006cea: 6eba ldr r2, [r7, #104] @ 0x68 + 8006cec: 65ba str r2, [r7, #88] @ 0x58 + 8006cee: 657b str r3, [r7, #84] @ 0x54 + 8006cf0: 6d79 ldr r1, [r7, #84] @ 0x54 + 8006cf2: 6dba ldr r2, [r7, #88] @ 0x58 + 8006cf4: e841 2300 strex r3, r2, [r1] + 8006cf8: 653b str r3, [r7, #80] @ 0x50 + 8006cfa: 6d3b ldr r3, [r7, #80] @ 0x50 + 8006cfc: 2b00 cmp r3, #0 + 8006cfe: d1e5 bne.n 8006ccc + 8006d00: 6efb ldr r3, [r7, #108] @ 0x6c + 8006d02: 681b ldr r3, [r3, #0] + 8006d04: 3314 adds r3, #20 + 8006d06: 63bb str r3, [r7, #56] @ 0x38 + 8006d08: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006d0a: e853 3f00 ldrex r3, [r3] + 8006d0e: 637b str r3, [r7, #52] @ 0x34 + 8006d10: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006d12: f023 0301 bic.w r3, r3, #1 + 8006d16: 667b str r3, [r7, #100] @ 0x64 + 8006d18: 6efb ldr r3, [r7, #108] @ 0x6c + 8006d1a: 681b ldr r3, [r3, #0] + 8006d1c: 3314 adds r3, #20 + 8006d1e: 6e7a ldr r2, [r7, #100] @ 0x64 + 8006d20: 647a str r2, [r7, #68] @ 0x44 + 8006d22: 643b str r3, [r7, #64] @ 0x40 + 8006d24: 6c39 ldr r1, [r7, #64] @ 0x40 + 8006d26: 6c7a ldr r2, [r7, #68] @ 0x44 + 8006d28: e841 2300 strex r3, r2, [r1] + 8006d2c: 63fb str r3, [r7, #60] @ 0x3c + 8006d2e: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006d30: 2b00 cmp r3, #0 + 8006d32: d1e5 bne.n 8006d00 + 8006d34: 6efb ldr r3, [r7, #108] @ 0x6c + 8006d36: 681b ldr r3, [r3, #0] + 8006d38: 3314 adds r3, #20 + 8006d3a: 627b str r3, [r7, #36] @ 0x24 + 8006d3c: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006d3e: e853 3f00 ldrex r3, [r3] + 8006d42: 623b str r3, [r7, #32] + 8006d44: 6a3b ldr r3, [r7, #32] + 8006d46: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8006d4a: 663b str r3, [r7, #96] @ 0x60 + 8006d4c: 6efb ldr r3, [r7, #108] @ 0x6c + 8006d4e: 681b ldr r3, [r3, #0] + 8006d50: 3314 adds r3, #20 + 8006d52: 6e3a ldr r2, [r7, #96] @ 0x60 + 8006d54: 633a str r2, [r7, #48] @ 0x30 + 8006d56: 62fb str r3, [r7, #44] @ 0x2c + 8006d58: 6af9 ldr r1, [r7, #44] @ 0x2c + 8006d5a: 6b3a ldr r2, [r7, #48] @ 0x30 + 8006d5c: e841 2300 strex r3, r2, [r1] + 8006d60: 62bb str r3, [r7, #40] @ 0x28 + 8006d62: 6abb ldr r3, [r7, #40] @ 0x28 + 8006d64: 2b00 cmp r3, #0 + 8006d66: d1e5 bne.n 8006d34 + 8006d68: 6efb ldr r3, [r7, #108] @ 0x6c + 8006d6a: 2220 movs r2, #32 + 8006d6c: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8006d70: 6efb ldr r3, [r7, #108] @ 0x6c + 8006d72: 6b1b ldr r3, [r3, #48] @ 0x30 + 8006d74: 2b01 cmp r3, #1 + 8006d76: d119 bne.n 8006dac + 8006d78: 6efb ldr r3, [r7, #108] @ 0x6c + 8006d7a: 681b ldr r3, [r3, #0] + 8006d7c: 330c adds r3, #12 + 8006d7e: 613b str r3, [r7, #16] + 8006d80: 693b ldr r3, [r7, #16] + 8006d82: e853 3f00 ldrex r3, [r3] + 8006d86: 60fb str r3, [r7, #12] + 8006d88: 68fb ldr r3, [r7, #12] + 8006d8a: f023 0310 bic.w r3, r3, #16 + 8006d8e: 65fb str r3, [r7, #92] @ 0x5c + 8006d90: 6efb ldr r3, [r7, #108] @ 0x6c + 8006d92: 681b ldr r3, [r3, #0] + 8006d94: 330c adds r3, #12 + 8006d96: 6dfa ldr r2, [r7, #92] @ 0x5c + 8006d98: 61fa str r2, [r7, #28] + 8006d9a: 61bb str r3, [r7, #24] + 8006d9c: 69b9 ldr r1, [r7, #24] + 8006d9e: 69fa ldr r2, [r7, #28] + 8006da0: e841 2300 strex r3, r2, [r1] + 8006da4: 617b str r3, [r7, #20] + 8006da6: 697b ldr r3, [r7, #20] + 8006da8: 2b00 cmp r3, #0 + 8006daa: d1e5 bne.n 8006d78 + 8006dac: 6efb ldr r3, [r7, #108] @ 0x6c + 8006dae: 2200 movs r2, #0 + 8006db0: 635a str r2, [r3, #52] @ 0x34 + 8006db2: 6efb ldr r3, [r7, #108] @ 0x6c + 8006db4: 6b1b ldr r3, [r3, #48] @ 0x30 + 8006db6: 2b01 cmp r3, #1 + 8006db8: d106 bne.n 8006dc8 + 8006dba: 6efb ldr r3, [r7, #108] @ 0x6c + 8006dbc: 8d9b ldrh r3, [r3, #44] @ 0x2c + 8006dbe: 4619 mov r1, r3 + 8006dc0: 6ef8 ldr r0, [r7, #108] @ 0x6c + 8006dc2: f7ff ff0b bl 8006bdc + 8006dc6: e002 b.n 8006dce + 8006dc8: 6ef8 ldr r0, [r7, #108] @ 0x6c + 8006dca: f7f9 ff9b bl 8000d04 + 8006dce: bf00 nop + 8006dd0: 3770 adds r7, #112 @ 0x70 + 8006dd2: 46bd mov sp, r7 + 8006dd4: bd80 pop {r7, pc} + +08006dd6 : + 8006dd6: b580 push {r7, lr} + 8006dd8: b084 sub sp, #16 + 8006dda: af00 add r7, sp, #0 + 8006ddc: 6078 str r0, [r7, #4] + 8006dde: 687b ldr r3, [r7, #4] + 8006de0: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006de2: 60fb str r3, [r7, #12] + 8006de4: 68fb ldr r3, [r7, #12] + 8006de6: 2201 movs r2, #1 + 8006de8: 635a str r2, [r3, #52] @ 0x34 + 8006dea: 68fb ldr r3, [r7, #12] + 8006dec: 6b1b ldr r3, [r3, #48] @ 0x30 + 8006dee: 2b01 cmp r3, #1 + 8006df0: d108 bne.n 8006e04 + 8006df2: 68fb ldr r3, [r7, #12] + 8006df4: 8d9b ldrh r3, [r3, #44] @ 0x2c + 8006df6: 085b lsrs r3, r3, #1 + 8006df8: b29b uxth r3, r3 + 8006dfa: 4619 mov r1, r3 + 8006dfc: 68f8 ldr r0, [r7, #12] + 8006dfe: f7ff feed bl 8006bdc + 8006e02: e002 b.n 8006e0a + 8006e04: 68f8 ldr r0, [r7, #12] + 8006e06: f7ff fedf bl 8006bc8 + 8006e0a: bf00 nop + 8006e0c: 3710 adds r7, #16 + 8006e0e: 46bd mov sp, r7 + 8006e10: bd80 pop {r7, pc} + +08006e12 : + 8006e12: b580 push {r7, lr} + 8006e14: b084 sub sp, #16 + 8006e16: af00 add r7, sp, #0 + 8006e18: 6078 str r0, [r7, #4] + 8006e1a: 2300 movs r3, #0 + 8006e1c: 60fb str r3, [r7, #12] + 8006e1e: 687b ldr r3, [r7, #4] + 8006e20: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006e22: 60bb str r3, [r7, #8] + 8006e24: 68bb ldr r3, [r7, #8] + 8006e26: 681b ldr r3, [r3, #0] + 8006e28: 695b ldr r3, [r3, #20] + 8006e2a: f003 0380 and.w r3, r3, #128 @ 0x80 + 8006e2e: 2b80 cmp r3, #128 @ 0x80 + 8006e30: bf0c ite eq + 8006e32: 2301 moveq r3, #1 + 8006e34: 2300 movne r3, #0 + 8006e36: b2db uxtb r3, r3 + 8006e38: 60fb str r3, [r7, #12] + 8006e3a: 68bb ldr r3, [r7, #8] + 8006e3c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 8006e40: b2db uxtb r3, r3 + 8006e42: 2b21 cmp r3, #33 @ 0x21 + 8006e44: d108 bne.n 8006e58 + 8006e46: 68fb ldr r3, [r7, #12] + 8006e48: 2b00 cmp r3, #0 + 8006e4a: d005 beq.n 8006e58 + 8006e4c: 68bb ldr r3, [r7, #8] + 8006e4e: 2200 movs r2, #0 + 8006e50: 84da strh r2, [r3, #38] @ 0x26 + 8006e52: 68b8 ldr r0, [r7, #8] + 8006e54: f000 f8ce bl 8006ff4 + 8006e58: 68bb ldr r3, [r7, #8] + 8006e5a: 681b ldr r3, [r3, #0] + 8006e5c: 695b ldr r3, [r3, #20] + 8006e5e: f003 0340 and.w r3, r3, #64 @ 0x40 + 8006e62: 2b40 cmp r3, #64 @ 0x40 + 8006e64: bf0c ite eq + 8006e66: 2301 moveq r3, #1 + 8006e68: 2300 movne r3, #0 + 8006e6a: b2db uxtb r3, r3 + 8006e6c: 60fb str r3, [r7, #12] + 8006e6e: 68bb ldr r3, [r7, #8] + 8006e70: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 + 8006e74: b2db uxtb r3, r3 + 8006e76: 2b22 cmp r3, #34 @ 0x22 + 8006e78: d108 bne.n 8006e8c + 8006e7a: 68fb ldr r3, [r7, #12] + 8006e7c: 2b00 cmp r3, #0 + 8006e7e: d005 beq.n 8006e8c + 8006e80: 68bb ldr r3, [r7, #8] + 8006e82: 2200 movs r2, #0 + 8006e84: 85da strh r2, [r3, #46] @ 0x2e + 8006e86: 68b8 ldr r0, [r7, #8] + 8006e88: f000 f8dc bl 8007044 + 8006e8c: 68bb ldr r3, [r7, #8] + 8006e8e: 6c5b ldr r3, [r3, #68] @ 0x44 + 8006e90: f043 0210 orr.w r2, r3, #16 + 8006e94: 68bb ldr r3, [r7, #8] + 8006e96: 645a str r2, [r3, #68] @ 0x44 + 8006e98: 68b8 ldr r0, [r7, #8] + 8006e9a: f7f9 ff8f bl 8000dbc + 8006e9e: bf00 nop + 8006ea0: 3710 adds r7, #16 + 8006ea2: 46bd mov sp, r7 + 8006ea4: bd80 pop {r7, pc} + ... + +08006ea8 : + 8006ea8: b580 push {r7, lr} + 8006eaa: b098 sub sp, #96 @ 0x60 + 8006eac: af00 add r7, sp, #0 + 8006eae: 60f8 str r0, [r7, #12] + 8006eb0: 60b9 str r1, [r7, #8] + 8006eb2: 4613 mov r3, r2 + 8006eb4: 80fb strh r3, [r7, #6] + 8006eb6: 68ba ldr r2, [r7, #8] + 8006eb8: 68fb ldr r3, [r7, #12] + 8006eba: 629a str r2, [r3, #40] @ 0x28 + 8006ebc: 68fb ldr r3, [r7, #12] + 8006ebe: 88fa ldrh r2, [r7, #6] + 8006ec0: 859a strh r2, [r3, #44] @ 0x2c + 8006ec2: 68fb ldr r3, [r7, #12] + 8006ec4: 2200 movs r2, #0 + 8006ec6: 645a str r2, [r3, #68] @ 0x44 + 8006ec8: 68fb ldr r3, [r7, #12] + 8006eca: 2222 movs r2, #34 @ 0x22 + 8006ecc: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8006ed0: 68fb ldr r3, [r7, #12] + 8006ed2: 6bdb ldr r3, [r3, #60] @ 0x3c + 8006ed4: 4a44 ldr r2, [pc, #272] @ (8006fe8 ) + 8006ed6: 63da str r2, [r3, #60] @ 0x3c + 8006ed8: 68fb ldr r3, [r7, #12] + 8006eda: 6bdb ldr r3, [r3, #60] @ 0x3c + 8006edc: 4a43 ldr r2, [pc, #268] @ (8006fec ) + 8006ede: 641a str r2, [r3, #64] @ 0x40 + 8006ee0: 68fb ldr r3, [r7, #12] + 8006ee2: 6bdb ldr r3, [r3, #60] @ 0x3c + 8006ee4: 4a42 ldr r2, [pc, #264] @ (8006ff0 ) + 8006ee6: 64da str r2, [r3, #76] @ 0x4c + 8006ee8: 68fb ldr r3, [r7, #12] + 8006eea: 6bdb ldr r3, [r3, #60] @ 0x3c + 8006eec: 2200 movs r2, #0 + 8006eee: 651a str r2, [r3, #80] @ 0x50 + 8006ef0: f107 0308 add.w r3, r7, #8 + 8006ef4: 65fb str r3, [r7, #92] @ 0x5c + 8006ef6: 68fb ldr r3, [r7, #12] + 8006ef8: 6bd8 ldr r0, [r3, #60] @ 0x3c + 8006efa: 68fb ldr r3, [r7, #12] + 8006efc: 681b ldr r3, [r3, #0] + 8006efe: 3304 adds r3, #4 + 8006f00: 4619 mov r1, r3 + 8006f02: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006f04: 681a ldr r2, [r3, #0] + 8006f06: 88fb ldrh r3, [r7, #6] + 8006f08: f7fb f9fe bl 8002308 + 8006f0c: 4603 mov r3, r0 + 8006f0e: 2b00 cmp r3, #0 + 8006f10: d008 beq.n 8006f24 + 8006f12: 68fb ldr r3, [r7, #12] + 8006f14: 2210 movs r2, #16 + 8006f16: 645a str r2, [r3, #68] @ 0x44 + 8006f18: 68fb ldr r3, [r7, #12] + 8006f1a: 2220 movs r2, #32 + 8006f1c: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8006f20: 2301 movs r3, #1 + 8006f22: e05d b.n 8006fe0 + 8006f24: 2300 movs r3, #0 + 8006f26: 613b str r3, [r7, #16] + 8006f28: 68fb ldr r3, [r7, #12] + 8006f2a: 681b ldr r3, [r3, #0] + 8006f2c: 681b ldr r3, [r3, #0] + 8006f2e: 613b str r3, [r7, #16] + 8006f30: 68fb ldr r3, [r7, #12] + 8006f32: 681b ldr r3, [r3, #0] + 8006f34: 685b ldr r3, [r3, #4] + 8006f36: 613b str r3, [r7, #16] + 8006f38: 693b ldr r3, [r7, #16] + 8006f3a: 68fb ldr r3, [r7, #12] + 8006f3c: 691b ldr r3, [r3, #16] + 8006f3e: 2b00 cmp r3, #0 + 8006f40: d019 beq.n 8006f76 + 8006f42: 68fb ldr r3, [r7, #12] + 8006f44: 681b ldr r3, [r3, #0] + 8006f46: 330c adds r3, #12 + 8006f48: 643b str r3, [r7, #64] @ 0x40 + 8006f4a: 6c3b ldr r3, [r7, #64] @ 0x40 + 8006f4c: e853 3f00 ldrex r3, [r3] + 8006f50: 63fb str r3, [r7, #60] @ 0x3c + 8006f52: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006f54: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8006f58: 65bb str r3, [r7, #88] @ 0x58 + 8006f5a: 68fb ldr r3, [r7, #12] + 8006f5c: 681b ldr r3, [r3, #0] + 8006f5e: 330c adds r3, #12 + 8006f60: 6dba ldr r2, [r7, #88] @ 0x58 + 8006f62: 64fa str r2, [r7, #76] @ 0x4c + 8006f64: 64bb str r3, [r7, #72] @ 0x48 + 8006f66: 6cb9 ldr r1, [r7, #72] @ 0x48 + 8006f68: 6cfa ldr r2, [r7, #76] @ 0x4c + 8006f6a: e841 2300 strex r3, r2, [r1] + 8006f6e: 647b str r3, [r7, #68] @ 0x44 + 8006f70: 6c7b ldr r3, [r7, #68] @ 0x44 + 8006f72: 2b00 cmp r3, #0 + 8006f74: d1e5 bne.n 8006f42 + 8006f76: 68fb ldr r3, [r7, #12] + 8006f78: 681b ldr r3, [r3, #0] + 8006f7a: 3314 adds r3, #20 + 8006f7c: 62fb str r3, [r7, #44] @ 0x2c + 8006f7e: 6afb ldr r3, [r7, #44] @ 0x2c + 8006f80: e853 3f00 ldrex r3, [r3] + 8006f84: 62bb str r3, [r7, #40] @ 0x28 + 8006f86: 6abb ldr r3, [r7, #40] @ 0x28 + 8006f88: f043 0301 orr.w r3, r3, #1 + 8006f8c: 657b str r3, [r7, #84] @ 0x54 + 8006f8e: 68fb ldr r3, [r7, #12] + 8006f90: 681b ldr r3, [r3, #0] + 8006f92: 3314 adds r3, #20 + 8006f94: 6d7a ldr r2, [r7, #84] @ 0x54 + 8006f96: 63ba str r2, [r7, #56] @ 0x38 + 8006f98: 637b str r3, [r7, #52] @ 0x34 + 8006f9a: 6b79 ldr r1, [r7, #52] @ 0x34 + 8006f9c: 6bba ldr r2, [r7, #56] @ 0x38 + 8006f9e: e841 2300 strex r3, r2, [r1] + 8006fa2: 633b str r3, [r7, #48] @ 0x30 + 8006fa4: 6b3b ldr r3, [r7, #48] @ 0x30 + 8006fa6: 2b00 cmp r3, #0 + 8006fa8: d1e5 bne.n 8006f76 + 8006faa: 68fb ldr r3, [r7, #12] + 8006fac: 681b ldr r3, [r3, #0] + 8006fae: 3314 adds r3, #20 + 8006fb0: 61bb str r3, [r7, #24] + 8006fb2: 69bb ldr r3, [r7, #24] + 8006fb4: e853 3f00 ldrex r3, [r3] + 8006fb8: 617b str r3, [r7, #20] + 8006fba: 697b ldr r3, [r7, #20] + 8006fbc: f043 0340 orr.w r3, r3, #64 @ 0x40 + 8006fc0: 653b str r3, [r7, #80] @ 0x50 + 8006fc2: 68fb ldr r3, [r7, #12] + 8006fc4: 681b ldr r3, [r3, #0] + 8006fc6: 3314 adds r3, #20 + 8006fc8: 6d3a ldr r2, [r7, #80] @ 0x50 + 8006fca: 627a str r2, [r7, #36] @ 0x24 + 8006fcc: 623b str r3, [r7, #32] + 8006fce: 6a39 ldr r1, [r7, #32] + 8006fd0: 6a7a ldr r2, [r7, #36] @ 0x24 + 8006fd2: e841 2300 strex r3, r2, [r1] + 8006fd6: 61fb str r3, [r7, #28] + 8006fd8: 69fb ldr r3, [r7, #28] + 8006fda: 2b00 cmp r3, #0 + 8006fdc: d1e5 bne.n 8006faa + 8006fde: 2300 movs r3, #0 + 8006fe0: 4618 mov r0, r3 + 8006fe2: 3760 adds r7, #96 @ 0x60 + 8006fe4: 46bd mov sp, r7 + 8006fe6: bd80 pop {r7, pc} + 8006fe8: 08006cab .word 0x08006cab + 8006fec: 08006dd7 .word 0x08006dd7 + 8006ff0: 08006e13 .word 0x08006e13 + +08006ff4 : + 8006ff4: b480 push {r7} + 8006ff6: b089 sub sp, #36 @ 0x24 + 8006ff8: af00 add r7, sp, #0 + 8006ffa: 6078 str r0, [r7, #4] + 8006ffc: 687b ldr r3, [r7, #4] + 8006ffe: 681b ldr r3, [r3, #0] + 8007000: 330c adds r3, #12 + 8007002: 60fb str r3, [r7, #12] + 8007004: 68fb ldr r3, [r7, #12] + 8007006: e853 3f00 ldrex r3, [r3] + 800700a: 60bb str r3, [r7, #8] + 800700c: 68bb ldr r3, [r7, #8] + 800700e: f023 03c0 bic.w r3, r3, #192 @ 0xc0 + 8007012: 61fb str r3, [r7, #28] + 8007014: 687b ldr r3, [r7, #4] + 8007016: 681b ldr r3, [r3, #0] + 8007018: 330c adds r3, #12 + 800701a: 69fa ldr r2, [r7, #28] + 800701c: 61ba str r2, [r7, #24] + 800701e: 617b str r3, [r7, #20] + 8007020: 6979 ldr r1, [r7, #20] + 8007022: 69ba ldr r2, [r7, #24] + 8007024: e841 2300 strex r3, r2, [r1] + 8007028: 613b str r3, [r7, #16] + 800702a: 693b ldr r3, [r7, #16] + 800702c: 2b00 cmp r3, #0 + 800702e: d1e5 bne.n 8006ffc + 8007030: 687b ldr r3, [r7, #4] + 8007032: 2220 movs r2, #32 + 8007034: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 8007038: bf00 nop + 800703a: 3724 adds r7, #36 @ 0x24 + 800703c: 46bd mov sp, r7 + 800703e: f85d 7b04 ldr.w r7, [sp], #4 + 8007042: 4770 bx lr + +08007044 : + 8007044: b480 push {r7} + 8007046: b095 sub sp, #84 @ 0x54 + 8007048: af00 add r7, sp, #0 + 800704a: 6078 str r0, [r7, #4] + 800704c: 687b ldr r3, [r7, #4] + 800704e: 681b ldr r3, [r3, #0] + 8007050: 330c adds r3, #12 + 8007052: 637b str r3, [r7, #52] @ 0x34 + 8007054: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007056: e853 3f00 ldrex r3, [r3] + 800705a: 633b str r3, [r7, #48] @ 0x30 + 800705c: 6b3b ldr r3, [r7, #48] @ 0x30 + 800705e: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8007062: 64fb str r3, [r7, #76] @ 0x4c + 8007064: 687b ldr r3, [r7, #4] + 8007066: 681b ldr r3, [r3, #0] + 8007068: 330c adds r3, #12 + 800706a: 6cfa ldr r2, [r7, #76] @ 0x4c + 800706c: 643a str r2, [r7, #64] @ 0x40 + 800706e: 63fb str r3, [r7, #60] @ 0x3c + 8007070: 6bf9 ldr r1, [r7, #60] @ 0x3c + 8007072: 6c3a ldr r2, [r7, #64] @ 0x40 + 8007074: e841 2300 strex r3, r2, [r1] + 8007078: 63bb str r3, [r7, #56] @ 0x38 + 800707a: 6bbb ldr r3, [r7, #56] @ 0x38 + 800707c: 2b00 cmp r3, #0 + 800707e: d1e5 bne.n 800704c + 8007080: 687b ldr r3, [r7, #4] + 8007082: 681b ldr r3, [r3, #0] + 8007084: 3314 adds r3, #20 + 8007086: 623b str r3, [r7, #32] + 8007088: 6a3b ldr r3, [r7, #32] + 800708a: e853 3f00 ldrex r3, [r3] + 800708e: 61fb str r3, [r7, #28] + 8007090: 69fb ldr r3, [r7, #28] + 8007092: f023 0301 bic.w r3, r3, #1 + 8007096: 64bb str r3, [r7, #72] @ 0x48 + 8007098: 687b ldr r3, [r7, #4] + 800709a: 681b ldr r3, [r3, #0] + 800709c: 3314 adds r3, #20 + 800709e: 6cba ldr r2, [r7, #72] @ 0x48 + 80070a0: 62fa str r2, [r7, #44] @ 0x2c + 80070a2: 62bb str r3, [r7, #40] @ 0x28 + 80070a4: 6ab9 ldr r1, [r7, #40] @ 0x28 + 80070a6: 6afa ldr r2, [r7, #44] @ 0x2c + 80070a8: e841 2300 strex r3, r2, [r1] + 80070ac: 627b str r3, [r7, #36] @ 0x24 + 80070ae: 6a7b ldr r3, [r7, #36] @ 0x24 + 80070b0: 2b00 cmp r3, #0 + 80070b2: d1e5 bne.n 8007080 + 80070b4: 687b ldr r3, [r7, #4] + 80070b6: 6b1b ldr r3, [r3, #48] @ 0x30 + 80070b8: 2b01 cmp r3, #1 + 80070ba: d119 bne.n 80070f0 + 80070bc: 687b ldr r3, [r7, #4] + 80070be: 681b ldr r3, [r3, #0] + 80070c0: 330c adds r3, #12 + 80070c2: 60fb str r3, [r7, #12] + 80070c4: 68fb ldr r3, [r7, #12] + 80070c6: e853 3f00 ldrex r3, [r3] + 80070ca: 60bb str r3, [r7, #8] + 80070cc: 68bb ldr r3, [r7, #8] + 80070ce: f023 0310 bic.w r3, r3, #16 + 80070d2: 647b str r3, [r7, #68] @ 0x44 + 80070d4: 687b ldr r3, [r7, #4] + 80070d6: 681b ldr r3, [r3, #0] + 80070d8: 330c adds r3, #12 + 80070da: 6c7a ldr r2, [r7, #68] @ 0x44 + 80070dc: 61ba str r2, [r7, #24] + 80070de: 617b str r3, [r7, #20] + 80070e0: 6979 ldr r1, [r7, #20] + 80070e2: 69ba ldr r2, [r7, #24] + 80070e4: e841 2300 strex r3, r2, [r1] + 80070e8: 613b str r3, [r7, #16] + 80070ea: 693b ldr r3, [r7, #16] + 80070ec: 2b00 cmp r3, #0 + 80070ee: d1e5 bne.n 80070bc + 80070f0: 687b ldr r3, [r7, #4] + 80070f2: 2220 movs r2, #32 + 80070f4: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 80070f8: 687b ldr r3, [r7, #4] + 80070fa: 2200 movs r2, #0 + 80070fc: 631a str r2, [r3, #48] @ 0x30 + 80070fe: bf00 nop + 8007100: 3754 adds r7, #84 @ 0x54 + 8007102: 46bd mov sp, r7 + 8007104: f85d 7b04 ldr.w r7, [sp], #4 + 8007108: 4770 bx lr + +0800710a : + 800710a: b580 push {r7, lr} + 800710c: b084 sub sp, #16 + 800710e: af00 add r7, sp, #0 + 8007110: 6078 str r0, [r7, #4] + 8007112: 687b ldr r3, [r7, #4] + 8007114: 6b9b ldr r3, [r3, #56] @ 0x38 + 8007116: 60fb str r3, [r7, #12] + 8007118: 68fb ldr r3, [r7, #12] + 800711a: 2200 movs r2, #0 + 800711c: 85da strh r2, [r3, #46] @ 0x2e + 800711e: 68f8 ldr r0, [r7, #12] + 8007120: f7f9 fe4c bl 8000dbc + 8007124: bf00 nop + 8007126: 3710 adds r7, #16 + 8007128: 46bd mov sp, r7 + 800712a: bd80 pop {r7, pc} + +0800712c : + 800712c: b480 push {r7} + 800712e: b085 sub sp, #20 + 8007130: af00 add r7, sp, #0 + 8007132: 6078 str r0, [r7, #4] + 8007134: 687b ldr r3, [r7, #4] + 8007136: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 + 800713a: b2db uxtb r3, r3 + 800713c: 2b21 cmp r3, #33 @ 0x21 + 800713e: d13e bne.n 80071be + 8007140: 687b ldr r3, [r7, #4] + 8007142: 689b ldr r3, [r3, #8] + 8007144: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8007148: d114 bne.n 8007174 + 800714a: 687b ldr r3, [r7, #4] + 800714c: 691b ldr r3, [r3, #16] + 800714e: 2b00 cmp r3, #0 + 8007150: d110 bne.n 8007174 + 8007152: 687b ldr r3, [r7, #4] + 8007154: 6a1b ldr r3, [r3, #32] + 8007156: 60fb str r3, [r7, #12] + 8007158: 68fb ldr r3, [r7, #12] + 800715a: 881b ldrh r3, [r3, #0] + 800715c: 461a mov r2, r3 + 800715e: 687b ldr r3, [r7, #4] + 8007160: 681b ldr r3, [r3, #0] + 8007162: f3c2 0208 ubfx r2, r2, #0, #9 + 8007166: 605a str r2, [r3, #4] + 8007168: 687b ldr r3, [r7, #4] + 800716a: 6a1b ldr r3, [r3, #32] + 800716c: 1c9a adds r2, r3, #2 + 800716e: 687b ldr r3, [r7, #4] + 8007170: 621a str r2, [r3, #32] + 8007172: e008 b.n 8007186 + 8007174: 687b ldr r3, [r7, #4] + 8007176: 6a1b ldr r3, [r3, #32] + 8007178: 1c59 adds r1, r3, #1 + 800717a: 687a ldr r2, [r7, #4] + 800717c: 6211 str r1, [r2, #32] + 800717e: 781a ldrb r2, [r3, #0] + 8007180: 687b ldr r3, [r7, #4] + 8007182: 681b ldr r3, [r3, #0] + 8007184: 605a str r2, [r3, #4] + 8007186: 687b ldr r3, [r7, #4] + 8007188: 8cdb ldrh r3, [r3, #38] @ 0x26 + 800718a: b29b uxth r3, r3 + 800718c: 3b01 subs r3, #1 + 800718e: b29b uxth r3, r3 + 8007190: 687a ldr r2, [r7, #4] + 8007192: 4619 mov r1, r3 + 8007194: 84d1 strh r1, [r2, #38] @ 0x26 + 8007196: 2b00 cmp r3, #0 + 8007198: d10f bne.n 80071ba + 800719a: 687b ldr r3, [r7, #4] + 800719c: 681b ldr r3, [r3, #0] + 800719e: 68da ldr r2, [r3, #12] + 80071a0: 687b ldr r3, [r7, #4] + 80071a2: 681b ldr r3, [r3, #0] + 80071a4: f022 0280 bic.w r2, r2, #128 @ 0x80 + 80071a8: 60da str r2, [r3, #12] + 80071aa: 687b ldr r3, [r7, #4] + 80071ac: 681b ldr r3, [r3, #0] + 80071ae: 68da ldr r2, [r3, #12] + 80071b0: 687b ldr r3, [r7, #4] + 80071b2: 681b ldr r3, [r3, #0] + 80071b4: f042 0240 orr.w r2, r2, #64 @ 0x40 + 80071b8: 60da str r2, [r3, #12] + 80071ba: 2300 movs r3, #0 + 80071bc: e000 b.n 80071c0 + 80071be: 2302 movs r3, #2 + 80071c0: 4618 mov r0, r3 + 80071c2: 3714 adds r7, #20 + 80071c4: 46bd mov sp, r7 + 80071c6: f85d 7b04 ldr.w r7, [sp], #4 + 80071ca: 4770 bx lr + +080071cc : + 80071cc: b580 push {r7, lr} + 80071ce: b082 sub sp, #8 + 80071d0: af00 add r7, sp, #0 + 80071d2: 6078 str r0, [r7, #4] + 80071d4: 687b ldr r3, [r7, #4] + 80071d6: 681b ldr r3, [r3, #0] + 80071d8: 68da ldr r2, [r3, #12] + 80071da: 687b ldr r3, [r7, #4] + 80071dc: 681b ldr r3, [r3, #0] + 80071de: f022 0240 bic.w r2, r2, #64 @ 0x40 + 80071e2: 60da str r2, [r3, #12] + 80071e4: 687b ldr r3, [r7, #4] + 80071e6: 2220 movs r2, #32 + 80071e8: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 80071ec: 6878 ldr r0, [r7, #4] + 80071ee: f7ff fcd7 bl 8006ba0 + 80071f2: 2300 movs r3, #0 + 80071f4: 4618 mov r0, r3 + 80071f6: 3708 adds r7, #8 + 80071f8: 46bd mov sp, r7 + 80071fa: bd80 pop {r7, pc} + +080071fc : + 80071fc: b580 push {r7, lr} + 80071fe: b08c sub sp, #48 @ 0x30 + 8007200: af00 add r7, sp, #0 + 8007202: 6078 str r0, [r7, #4] + 8007204: 2300 movs r3, #0 + 8007206: 62fb str r3, [r7, #44] @ 0x2c + 8007208: 2300 movs r3, #0 + 800720a: 62bb str r3, [r7, #40] @ 0x28 + 800720c: 687b ldr r3, [r7, #4] + 800720e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 + 8007212: b2db uxtb r3, r3 + 8007214: 2b22 cmp r3, #34 @ 0x22 + 8007216: f040 80aa bne.w 800736e + 800721a: 687b ldr r3, [r7, #4] + 800721c: 689b ldr r3, [r3, #8] + 800721e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8007222: d115 bne.n 8007250 + 8007224: 687b ldr r3, [r7, #4] + 8007226: 691b ldr r3, [r3, #16] + 8007228: 2b00 cmp r3, #0 + 800722a: d111 bne.n 8007250 + 800722c: 687b ldr r3, [r7, #4] + 800722e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8007230: 62bb str r3, [r7, #40] @ 0x28 + 8007232: 687b ldr r3, [r7, #4] + 8007234: 681b ldr r3, [r3, #0] + 8007236: 685b ldr r3, [r3, #4] + 8007238: b29b uxth r3, r3 + 800723a: f3c3 0308 ubfx r3, r3, #0, #9 + 800723e: b29a uxth r2, r3 + 8007240: 6abb ldr r3, [r7, #40] @ 0x28 + 8007242: 801a strh r2, [r3, #0] + 8007244: 687b ldr r3, [r7, #4] + 8007246: 6a9b ldr r3, [r3, #40] @ 0x28 + 8007248: 1c9a adds r2, r3, #2 + 800724a: 687b ldr r3, [r7, #4] + 800724c: 629a str r2, [r3, #40] @ 0x28 + 800724e: e024 b.n 800729a + 8007250: 687b ldr r3, [r7, #4] + 8007252: 6a9b ldr r3, [r3, #40] @ 0x28 + 8007254: 62fb str r3, [r7, #44] @ 0x2c + 8007256: 687b ldr r3, [r7, #4] + 8007258: 689b ldr r3, [r3, #8] + 800725a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 800725e: d007 beq.n 8007270 + 8007260: 687b ldr r3, [r7, #4] + 8007262: 689b ldr r3, [r3, #8] + 8007264: 2b00 cmp r3, #0 + 8007266: d10a bne.n 800727e + 8007268: 687b ldr r3, [r7, #4] + 800726a: 691b ldr r3, [r3, #16] + 800726c: 2b00 cmp r3, #0 + 800726e: d106 bne.n 800727e + 8007270: 687b ldr r3, [r7, #4] + 8007272: 681b ldr r3, [r3, #0] + 8007274: 685b ldr r3, [r3, #4] + 8007276: b2da uxtb r2, r3 + 8007278: 6afb ldr r3, [r7, #44] @ 0x2c + 800727a: 701a strb r2, [r3, #0] + 800727c: e008 b.n 8007290 + 800727e: 687b ldr r3, [r7, #4] + 8007280: 681b ldr r3, [r3, #0] + 8007282: 685b ldr r3, [r3, #4] + 8007284: b2db uxtb r3, r3 + 8007286: f003 037f and.w r3, r3, #127 @ 0x7f + 800728a: b2da uxtb r2, r3 + 800728c: 6afb ldr r3, [r7, #44] @ 0x2c + 800728e: 701a strb r2, [r3, #0] + 8007290: 687b ldr r3, [r7, #4] + 8007292: 6a9b ldr r3, [r3, #40] @ 0x28 + 8007294: 1c5a adds r2, r3, #1 + 8007296: 687b ldr r3, [r7, #4] + 8007298: 629a str r2, [r3, #40] @ 0x28 + 800729a: 687b ldr r3, [r7, #4] + 800729c: 8ddb ldrh r3, [r3, #46] @ 0x2e + 800729e: b29b uxth r3, r3 + 80072a0: 3b01 subs r3, #1 + 80072a2: b29b uxth r3, r3 + 80072a4: 687a ldr r2, [r7, #4] + 80072a6: 4619 mov r1, r3 + 80072a8: 85d1 strh r1, [r2, #46] @ 0x2e + 80072aa: 2b00 cmp r3, #0 + 80072ac: d15d bne.n 800736a + 80072ae: 687b ldr r3, [r7, #4] + 80072b0: 681b ldr r3, [r3, #0] + 80072b2: 68da ldr r2, [r3, #12] + 80072b4: 687b ldr r3, [r7, #4] + 80072b6: 681b ldr r3, [r3, #0] + 80072b8: f022 0220 bic.w r2, r2, #32 + 80072bc: 60da str r2, [r3, #12] + 80072be: 687b ldr r3, [r7, #4] + 80072c0: 681b ldr r3, [r3, #0] + 80072c2: 68da ldr r2, [r3, #12] + 80072c4: 687b ldr r3, [r7, #4] + 80072c6: 681b ldr r3, [r3, #0] + 80072c8: f422 7280 bic.w r2, r2, #256 @ 0x100 + 80072cc: 60da str r2, [r3, #12] + 80072ce: 687b ldr r3, [r7, #4] + 80072d0: 681b ldr r3, [r3, #0] + 80072d2: 695a ldr r2, [r3, #20] + 80072d4: 687b ldr r3, [r7, #4] + 80072d6: 681b ldr r3, [r3, #0] + 80072d8: f022 0201 bic.w r2, r2, #1 + 80072dc: 615a str r2, [r3, #20] + 80072de: 687b ldr r3, [r7, #4] + 80072e0: 2220 movs r2, #32 + 80072e2: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 80072e6: 687b ldr r3, [r7, #4] + 80072e8: 2200 movs r2, #0 + 80072ea: 635a str r2, [r3, #52] @ 0x34 + 80072ec: 687b ldr r3, [r7, #4] + 80072ee: 6b1b ldr r3, [r3, #48] @ 0x30 + 80072f0: 2b01 cmp r3, #1 + 80072f2: d135 bne.n 8007360 + 80072f4: 687b ldr r3, [r7, #4] + 80072f6: 2200 movs r2, #0 + 80072f8: 631a str r2, [r3, #48] @ 0x30 + 80072fa: 687b ldr r3, [r7, #4] + 80072fc: 681b ldr r3, [r3, #0] + 80072fe: 330c adds r3, #12 + 8007300: 617b str r3, [r7, #20] + 8007302: 697b ldr r3, [r7, #20] + 8007304: e853 3f00 ldrex r3, [r3] + 8007308: 613b str r3, [r7, #16] + 800730a: 693b ldr r3, [r7, #16] + 800730c: f023 0310 bic.w r3, r3, #16 + 8007310: 627b str r3, [r7, #36] @ 0x24 + 8007312: 687b ldr r3, [r7, #4] + 8007314: 681b ldr r3, [r3, #0] + 8007316: 330c adds r3, #12 + 8007318: 6a7a ldr r2, [r7, #36] @ 0x24 + 800731a: 623a str r2, [r7, #32] + 800731c: 61fb str r3, [r7, #28] + 800731e: 69f9 ldr r1, [r7, #28] + 8007320: 6a3a ldr r2, [r7, #32] + 8007322: e841 2300 strex r3, r2, [r1] + 8007326: 61bb str r3, [r7, #24] + 8007328: 69bb ldr r3, [r7, #24] + 800732a: 2b00 cmp r3, #0 + 800732c: d1e5 bne.n 80072fa + 800732e: 687b ldr r3, [r7, #4] + 8007330: 681b ldr r3, [r3, #0] + 8007332: 681b ldr r3, [r3, #0] + 8007334: f003 0310 and.w r3, r3, #16 + 8007338: 2b10 cmp r3, #16 + 800733a: d10a bne.n 8007352 + 800733c: 2300 movs r3, #0 + 800733e: 60fb str r3, [r7, #12] + 8007340: 687b ldr r3, [r7, #4] + 8007342: 681b ldr r3, [r3, #0] + 8007344: 681b ldr r3, [r3, #0] + 8007346: 60fb str r3, [r7, #12] + 8007348: 687b ldr r3, [r7, #4] + 800734a: 681b ldr r3, [r3, #0] + 800734c: 685b ldr r3, [r3, #4] + 800734e: 60fb str r3, [r7, #12] + 8007350: 68fb ldr r3, [r7, #12] + 8007352: 687b ldr r3, [r7, #4] + 8007354: 8d9b ldrh r3, [r3, #44] @ 0x2c + 8007356: 4619 mov r1, r3 + 8007358: 6878 ldr r0, [r7, #4] + 800735a: f7ff fc3f bl 8006bdc + 800735e: e002 b.n 8007366 + 8007360: 6878 ldr r0, [r7, #4] + 8007362: f7f9 fccf bl 8000d04 + 8007366: 2300 movs r3, #0 + 8007368: e002 b.n 8007370 + 800736a: 2300 movs r3, #0 + 800736c: e000 b.n 8007370 + 800736e: 2302 movs r3, #2 + 8007370: 4618 mov r0, r3 + 8007372: 3730 adds r7, #48 @ 0x30 + 8007374: 46bd mov sp, r7 + 8007376: bd80 pop {r7, pc} + +08007378 : + 8007378: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 800737c: b0c0 sub sp, #256 @ 0x100 + 800737e: af00 add r7, sp, #0 + 8007380: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 + 8007384: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 8007388: 681b ldr r3, [r3, #0] + 800738a: 691b ldr r3, [r3, #16] + 800738c: f423 5040 bic.w r0, r3, #12288 @ 0x3000 + 8007390: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 8007394: 68d9 ldr r1, [r3, #12] + 8007396: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 800739a: 681a ldr r2, [r3, #0] + 800739c: ea40 0301 orr.w r3, r0, r1 + 80073a0: 6113 str r3, [r2, #16] + 80073a2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80073a6: 689a ldr r2, [r3, #8] + 80073a8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80073ac: 691b ldr r3, [r3, #16] + 80073ae: 431a orrs r2, r3 + 80073b0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80073b4: 695b ldr r3, [r3, #20] + 80073b6: 431a orrs r2, r3 + 80073b8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80073bc: 69db ldr r3, [r3, #28] + 80073be: 4313 orrs r3, r2 + 80073c0: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 + 80073c4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80073c8: 681b ldr r3, [r3, #0] + 80073ca: 68db ldr r3, [r3, #12] + 80073cc: f423 4116 bic.w r1, r3, #38400 @ 0x9600 + 80073d0: f021 010c bic.w r1, r1, #12 + 80073d4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80073d8: 681a ldr r2, [r3, #0] + 80073da: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 + 80073de: 430b orrs r3, r1 + 80073e0: 60d3 str r3, [r2, #12] + 80073e2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80073e6: 681b ldr r3, [r3, #0] + 80073e8: 695b ldr r3, [r3, #20] + 80073ea: f423 7040 bic.w r0, r3, #768 @ 0x300 + 80073ee: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80073f2: 6999 ldr r1, [r3, #24] + 80073f4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80073f8: 681a ldr r2, [r3, #0] + 80073fa: ea40 0301 orr.w r3, r0, r1 + 80073fe: 6153 str r3, [r2, #20] + 8007400: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 8007404: 681a ldr r2, [r3, #0] + 8007406: 4b8f ldr r3, [pc, #572] @ (8007644 ) + 8007408: 429a cmp r2, r3 + 800740a: d005 beq.n 8007418 + 800740c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 8007410: 681a ldr r2, [r3, #0] + 8007412: 4b8d ldr r3, [pc, #564] @ (8007648 ) + 8007414: 429a cmp r2, r3 + 8007416: d104 bne.n 8007422 + 8007418: f7fd f960 bl 80046dc + 800741c: f8c7 00fc str.w r0, [r7, #252] @ 0xfc + 8007420: e003 b.n 800742a + 8007422: f7fd f947 bl 80046b4 + 8007426: f8c7 00fc str.w r0, [r7, #252] @ 0xfc + 800742a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 800742e: 69db ldr r3, [r3, #28] + 8007430: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8007434: f040 810c bne.w 8007650 + 8007438: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc + 800743c: 2200 movs r2, #0 + 800743e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 + 8007442: f8c7 20ec str.w r2, [r7, #236] @ 0xec + 8007446: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 + 800744a: 4622 mov r2, r4 + 800744c: 462b mov r3, r5 + 800744e: 1891 adds r1, r2, r2 + 8007450: 65b9 str r1, [r7, #88] @ 0x58 + 8007452: 415b adcs r3, r3 + 8007454: 65fb str r3, [r7, #92] @ 0x5c + 8007456: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 + 800745a: 4621 mov r1, r4 + 800745c: eb12 0801 adds.w r8, r2, r1 + 8007460: 4629 mov r1, r5 + 8007462: eb43 0901 adc.w r9, r3, r1 + 8007466: f04f 0200 mov.w r2, #0 + 800746a: f04f 0300 mov.w r3, #0 + 800746e: ea4f 03c9 mov.w r3, r9, lsl #3 + 8007472: ea43 7358 orr.w r3, r3, r8, lsr #29 + 8007476: ea4f 02c8 mov.w r2, r8, lsl #3 + 800747a: 4690 mov r8, r2 + 800747c: 4699 mov r9, r3 + 800747e: 4623 mov r3, r4 + 8007480: eb18 0303 adds.w r3, r8, r3 + 8007484: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 + 8007488: 462b mov r3, r5 + 800748a: eb49 0303 adc.w r3, r9, r3 + 800748e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 + 8007492: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 8007496: 685b ldr r3, [r3, #4] + 8007498: 2200 movs r2, #0 + 800749a: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 + 800749e: f8c7 20dc str.w r2, [r7, #220] @ 0xdc + 80074a2: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 + 80074a6: 460b mov r3, r1 + 80074a8: 18db adds r3, r3, r3 + 80074aa: 653b str r3, [r7, #80] @ 0x50 + 80074ac: 4613 mov r3, r2 + 80074ae: eb42 0303 adc.w r3, r2, r3 + 80074b2: 657b str r3, [r7, #84] @ 0x54 + 80074b4: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 + 80074b8: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 + 80074bc: f7f8 fea2 bl 8000204 <__aeabi_uldivmod> + 80074c0: 4602 mov r2, r0 + 80074c2: 460b mov r3, r1 + 80074c4: 4b61 ldr r3, [pc, #388] @ (800764c ) + 80074c6: fba3 2302 umull r2, r3, r3, r2 + 80074ca: 095b lsrs r3, r3, #5 + 80074cc: 011c lsls r4, r3, #4 + 80074ce: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc + 80074d2: 2200 movs r2, #0 + 80074d4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 + 80074d8: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 + 80074dc: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 + 80074e0: 4642 mov r2, r8 + 80074e2: 464b mov r3, r9 + 80074e4: 1891 adds r1, r2, r2 + 80074e6: 64b9 str r1, [r7, #72] @ 0x48 + 80074e8: 415b adcs r3, r3 + 80074ea: 64fb str r3, [r7, #76] @ 0x4c + 80074ec: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 + 80074f0: 4641 mov r1, r8 + 80074f2: eb12 0a01 adds.w sl, r2, r1 + 80074f6: 4649 mov r1, r9 + 80074f8: eb43 0b01 adc.w fp, r3, r1 + 80074fc: f04f 0200 mov.w r2, #0 + 8007500: f04f 0300 mov.w r3, #0 + 8007504: ea4f 03cb mov.w r3, fp, lsl #3 + 8007508: ea43 735a orr.w r3, r3, sl, lsr #29 + 800750c: ea4f 02ca mov.w r2, sl, lsl #3 + 8007510: 4692 mov sl, r2 + 8007512: 469b mov fp, r3 + 8007514: 4643 mov r3, r8 + 8007516: eb1a 0303 adds.w r3, sl, r3 + 800751a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 + 800751e: 464b mov r3, r9 + 8007520: eb4b 0303 adc.w r3, fp, r3 + 8007524: f8c7 30cc str.w r3, [r7, #204] @ 0xcc + 8007528: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 800752c: 685b ldr r3, [r3, #4] + 800752e: 2200 movs r2, #0 + 8007530: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 + 8007534: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 + 8007538: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 + 800753c: 460b mov r3, r1 + 800753e: 18db adds r3, r3, r3 + 8007540: 643b str r3, [r7, #64] @ 0x40 + 8007542: 4613 mov r3, r2 + 8007544: eb42 0303 adc.w r3, r2, r3 + 8007548: 647b str r3, [r7, #68] @ 0x44 + 800754a: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 + 800754e: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 + 8007552: f7f8 fe57 bl 8000204 <__aeabi_uldivmod> + 8007556: 4602 mov r2, r0 + 8007558: 460b mov r3, r1 + 800755a: 4611 mov r1, r2 + 800755c: 4b3b ldr r3, [pc, #236] @ (800764c ) + 800755e: fba3 2301 umull r2, r3, r3, r1 + 8007562: 095b lsrs r3, r3, #5 + 8007564: 2264 movs r2, #100 @ 0x64 + 8007566: fb02 f303 mul.w r3, r2, r3 + 800756a: 1acb subs r3, r1, r3 + 800756c: 00db lsls r3, r3, #3 + 800756e: f103 0232 add.w r2, r3, #50 @ 0x32 + 8007572: 4b36 ldr r3, [pc, #216] @ (800764c ) + 8007574: fba3 2302 umull r2, r3, r3, r2 + 8007578: 095b lsrs r3, r3, #5 + 800757a: 005b lsls r3, r3, #1 + 800757c: f403 73f8 and.w r3, r3, #496 @ 0x1f0 + 8007580: 441c add r4, r3 + 8007582: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc + 8007586: 2200 movs r2, #0 + 8007588: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 + 800758c: f8c7 20bc str.w r2, [r7, #188] @ 0xbc + 8007590: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 + 8007594: 4642 mov r2, r8 + 8007596: 464b mov r3, r9 + 8007598: 1891 adds r1, r2, r2 + 800759a: 63b9 str r1, [r7, #56] @ 0x38 + 800759c: 415b adcs r3, r3 + 800759e: 63fb str r3, [r7, #60] @ 0x3c + 80075a0: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 + 80075a4: 4641 mov r1, r8 + 80075a6: 1851 adds r1, r2, r1 + 80075a8: 6339 str r1, [r7, #48] @ 0x30 + 80075aa: 4649 mov r1, r9 + 80075ac: 414b adcs r3, r1 + 80075ae: 637b str r3, [r7, #52] @ 0x34 + 80075b0: f04f 0200 mov.w r2, #0 + 80075b4: f04f 0300 mov.w r3, #0 + 80075b8: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 + 80075bc: 4659 mov r1, fp + 80075be: 00cb lsls r3, r1, #3 + 80075c0: 4651 mov r1, sl + 80075c2: ea43 7351 orr.w r3, r3, r1, lsr #29 + 80075c6: 4651 mov r1, sl + 80075c8: 00ca lsls r2, r1, #3 + 80075ca: 4610 mov r0, r2 + 80075cc: 4619 mov r1, r3 + 80075ce: 4603 mov r3, r0 + 80075d0: 4642 mov r2, r8 + 80075d2: 189b adds r3, r3, r2 + 80075d4: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 80075d8: 464b mov r3, r9 + 80075da: 460a mov r2, r1 + 80075dc: eb42 0303 adc.w r3, r2, r3 + 80075e0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 80075e4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80075e8: 685b ldr r3, [r3, #4] + 80075ea: 2200 movs r2, #0 + 80075ec: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 + 80075f0: f8c7 20ac str.w r2, [r7, #172] @ 0xac + 80075f4: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 + 80075f8: 460b mov r3, r1 + 80075fa: 18db adds r3, r3, r3 + 80075fc: 62bb str r3, [r7, #40] @ 0x28 + 80075fe: 4613 mov r3, r2 + 8007600: eb42 0303 adc.w r3, r2, r3 + 8007604: 62fb str r3, [r7, #44] @ 0x2c + 8007606: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 + 800760a: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 + 800760e: f7f8 fdf9 bl 8000204 <__aeabi_uldivmod> + 8007612: 4602 mov r2, r0 + 8007614: 460b mov r3, r1 + 8007616: 4b0d ldr r3, [pc, #52] @ (800764c ) + 8007618: fba3 1302 umull r1, r3, r3, r2 + 800761c: 095b lsrs r3, r3, #5 + 800761e: 2164 movs r1, #100 @ 0x64 + 8007620: fb01 f303 mul.w r3, r1, r3 + 8007624: 1ad3 subs r3, r2, r3 + 8007626: 00db lsls r3, r3, #3 + 8007628: 3332 adds r3, #50 @ 0x32 + 800762a: 4a08 ldr r2, [pc, #32] @ (800764c ) + 800762c: fba2 2303 umull r2, r3, r2, r3 + 8007630: 095b lsrs r3, r3, #5 + 8007632: f003 0207 and.w r2, r3, #7 + 8007636: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 800763a: 681b ldr r3, [r3, #0] + 800763c: 4422 add r2, r4 + 800763e: 609a str r2, [r3, #8] + 8007640: e106 b.n 8007850 + 8007642: bf00 nop + 8007644: 40011000 .word 0x40011000 + 8007648: 40011400 .word 0x40011400 + 800764c: 51eb851f .word 0x51eb851f + 8007650: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc + 8007654: 2200 movs r2, #0 + 8007656: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + 800765a: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 + 800765e: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 + 8007662: 4642 mov r2, r8 + 8007664: 464b mov r3, r9 + 8007666: 1891 adds r1, r2, r2 + 8007668: 6239 str r1, [r7, #32] + 800766a: 415b adcs r3, r3 + 800766c: 627b str r3, [r7, #36] @ 0x24 + 800766e: e9d7 2308 ldrd r2, r3, [r7, #32] + 8007672: 4641 mov r1, r8 + 8007674: 1854 adds r4, r2, r1 + 8007676: 4649 mov r1, r9 + 8007678: eb43 0501 adc.w r5, r3, r1 + 800767c: f04f 0200 mov.w r2, #0 + 8007680: f04f 0300 mov.w r3, #0 + 8007684: 00eb lsls r3, r5, #3 + 8007686: ea43 7354 orr.w r3, r3, r4, lsr #29 + 800768a: 00e2 lsls r2, r4, #3 + 800768c: 4614 mov r4, r2 + 800768e: 461d mov r5, r3 + 8007690: 4643 mov r3, r8 + 8007692: 18e3 adds r3, r4, r3 + 8007694: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + 8007698: 464b mov r3, r9 + 800769a: eb45 0303 adc.w r3, r5, r3 + 800769e: f8c7 309c str.w r3, [r7, #156] @ 0x9c + 80076a2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80076a6: 685b ldr r3, [r3, #4] + 80076a8: 2200 movs r2, #0 + 80076aa: f8c7 3090 str.w r3, [r7, #144] @ 0x90 + 80076ae: f8c7 2094 str.w r2, [r7, #148] @ 0x94 + 80076b2: f04f 0200 mov.w r2, #0 + 80076b6: f04f 0300 mov.w r3, #0 + 80076ba: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 + 80076be: 4629 mov r1, r5 + 80076c0: 008b lsls r3, r1, #2 + 80076c2: 4621 mov r1, r4 + 80076c4: ea43 7391 orr.w r3, r3, r1, lsr #30 + 80076c8: 4621 mov r1, r4 + 80076ca: 008a lsls r2, r1, #2 + 80076cc: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 + 80076d0: f7f8 fd98 bl 8000204 <__aeabi_uldivmod> + 80076d4: 4602 mov r2, r0 + 80076d6: 460b mov r3, r1 + 80076d8: 4b60 ldr r3, [pc, #384] @ (800785c ) + 80076da: fba3 2302 umull r2, r3, r3, r2 + 80076de: 095b lsrs r3, r3, #5 + 80076e0: 011c lsls r4, r3, #4 + 80076e2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc + 80076e6: 2200 movs r2, #0 + 80076e8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 + 80076ec: f8c7 208c str.w r2, [r7, #140] @ 0x8c + 80076f0: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 + 80076f4: 4642 mov r2, r8 + 80076f6: 464b mov r3, r9 + 80076f8: 1891 adds r1, r2, r2 + 80076fa: 61b9 str r1, [r7, #24] + 80076fc: 415b adcs r3, r3 + 80076fe: 61fb str r3, [r7, #28] + 8007700: e9d7 2306 ldrd r2, r3, [r7, #24] + 8007704: 4641 mov r1, r8 + 8007706: 1851 adds r1, r2, r1 + 8007708: 6139 str r1, [r7, #16] + 800770a: 4649 mov r1, r9 + 800770c: 414b adcs r3, r1 + 800770e: 617b str r3, [r7, #20] + 8007710: f04f 0200 mov.w r2, #0 + 8007714: f04f 0300 mov.w r3, #0 + 8007718: e9d7 ab04 ldrd sl, fp, [r7, #16] + 800771c: 4659 mov r1, fp + 800771e: 00cb lsls r3, r1, #3 + 8007720: 4651 mov r1, sl + 8007722: ea43 7351 orr.w r3, r3, r1, lsr #29 + 8007726: 4651 mov r1, sl + 8007728: 00ca lsls r2, r1, #3 + 800772a: 4610 mov r0, r2 + 800772c: 4619 mov r1, r3 + 800772e: 4603 mov r3, r0 + 8007730: 4642 mov r2, r8 + 8007732: 189b adds r3, r3, r2 + 8007734: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 8007738: 464b mov r3, r9 + 800773a: 460a mov r2, r1 + 800773c: eb42 0303 adc.w r3, r2, r3 + 8007740: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 8007744: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 8007748: 685b ldr r3, [r3, #4] + 800774a: 2200 movs r2, #0 + 800774c: 67bb str r3, [r7, #120] @ 0x78 + 800774e: 67fa str r2, [r7, #124] @ 0x7c + 8007750: f04f 0200 mov.w r2, #0 + 8007754: f04f 0300 mov.w r3, #0 + 8007758: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 + 800775c: 4649 mov r1, r9 + 800775e: 008b lsls r3, r1, #2 + 8007760: 4641 mov r1, r8 + 8007762: ea43 7391 orr.w r3, r3, r1, lsr #30 + 8007766: 4641 mov r1, r8 + 8007768: 008a lsls r2, r1, #2 + 800776a: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 + 800776e: f7f8 fd49 bl 8000204 <__aeabi_uldivmod> + 8007772: 4602 mov r2, r0 + 8007774: 460b mov r3, r1 + 8007776: 4611 mov r1, r2 + 8007778: 4b38 ldr r3, [pc, #224] @ (800785c ) + 800777a: fba3 2301 umull r2, r3, r3, r1 + 800777e: 095b lsrs r3, r3, #5 + 8007780: 2264 movs r2, #100 @ 0x64 + 8007782: fb02 f303 mul.w r3, r2, r3 + 8007786: 1acb subs r3, r1, r3 + 8007788: 011b lsls r3, r3, #4 + 800778a: 3332 adds r3, #50 @ 0x32 + 800778c: 4a33 ldr r2, [pc, #204] @ (800785c ) + 800778e: fba2 2303 umull r2, r3, r2, r3 + 8007792: 095b lsrs r3, r3, #5 + 8007794: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8007798: 441c add r4, r3 + 800779a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc + 800779e: 2200 movs r2, #0 + 80077a0: 673b str r3, [r7, #112] @ 0x70 + 80077a2: 677a str r2, [r7, #116] @ 0x74 + 80077a4: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 + 80077a8: 4642 mov r2, r8 + 80077aa: 464b mov r3, r9 + 80077ac: 1891 adds r1, r2, r2 + 80077ae: 60b9 str r1, [r7, #8] + 80077b0: 415b adcs r3, r3 + 80077b2: 60fb str r3, [r7, #12] + 80077b4: e9d7 2302 ldrd r2, r3, [r7, #8] + 80077b8: 4641 mov r1, r8 + 80077ba: 1851 adds r1, r2, r1 + 80077bc: 6039 str r1, [r7, #0] + 80077be: 4649 mov r1, r9 + 80077c0: 414b adcs r3, r1 + 80077c2: 607b str r3, [r7, #4] + 80077c4: f04f 0200 mov.w r2, #0 + 80077c8: f04f 0300 mov.w r3, #0 + 80077cc: e9d7 ab00 ldrd sl, fp, [r7] + 80077d0: 4659 mov r1, fp + 80077d2: 00cb lsls r3, r1, #3 + 80077d4: 4651 mov r1, sl + 80077d6: ea43 7351 orr.w r3, r3, r1, lsr #29 + 80077da: 4651 mov r1, sl + 80077dc: 00ca lsls r2, r1, #3 + 80077de: 4610 mov r0, r2 + 80077e0: 4619 mov r1, r3 + 80077e2: 4603 mov r3, r0 + 80077e4: 4642 mov r2, r8 + 80077e6: 189b adds r3, r3, r2 + 80077e8: 66bb str r3, [r7, #104] @ 0x68 + 80077ea: 464b mov r3, r9 + 80077ec: 460a mov r2, r1 + 80077ee: eb42 0303 adc.w r3, r2, r3 + 80077f2: 66fb str r3, [r7, #108] @ 0x6c + 80077f4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 80077f8: 685b ldr r3, [r3, #4] + 80077fa: 2200 movs r2, #0 + 80077fc: 663b str r3, [r7, #96] @ 0x60 + 80077fe: 667a str r2, [r7, #100] @ 0x64 + 8007800: f04f 0200 mov.w r2, #0 + 8007804: f04f 0300 mov.w r3, #0 + 8007808: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 + 800780c: 4649 mov r1, r9 + 800780e: 008b lsls r3, r1, #2 + 8007810: 4641 mov r1, r8 + 8007812: ea43 7391 orr.w r3, r3, r1, lsr #30 + 8007816: 4641 mov r1, r8 + 8007818: 008a lsls r2, r1, #2 + 800781a: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 + 800781e: f7f8 fcf1 bl 8000204 <__aeabi_uldivmod> + 8007822: 4602 mov r2, r0 + 8007824: 460b mov r3, r1 + 8007826: 4b0d ldr r3, [pc, #52] @ (800785c ) + 8007828: fba3 1302 umull r1, r3, r3, r2 + 800782c: 095b lsrs r3, r3, #5 + 800782e: 2164 movs r1, #100 @ 0x64 + 8007830: fb01 f303 mul.w r3, r1, r3 + 8007834: 1ad3 subs r3, r2, r3 + 8007836: 011b lsls r3, r3, #4 + 8007838: 3332 adds r3, #50 @ 0x32 + 800783a: 4a08 ldr r2, [pc, #32] @ (800785c ) + 800783c: fba2 2303 umull r2, r3, r2, r3 + 8007840: 095b lsrs r3, r3, #5 + 8007842: f003 020f and.w r2, r3, #15 + 8007846: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 + 800784a: 681b ldr r3, [r3, #0] + 800784c: 4422 add r2, r4 + 800784e: 609a str r2, [r3, #8] + 8007850: bf00 nop + 8007852: f507 7780 add.w r7, r7, #256 @ 0x100 + 8007856: 46bd mov sp, r7 + 8007858: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 800785c: 51eb851f .word 0x51eb851f + +08007860 : + 8007860: b084 sub sp, #16 + 8007862: b580 push {r7, lr} + 8007864: b084 sub sp, #16 + 8007866: af00 add r7, sp, #0 + 8007868: 6078 str r0, [r7, #4] + 800786a: f107 001c add.w r0, r7, #28 + 800786e: e880 000e stmia.w r0, {r1, r2, r3} + 8007872: f897 3021 ldrb.w r3, [r7, #33] @ 0x21 + 8007876: 2b01 cmp r3, #1 + 8007878: d123 bne.n 80078c2 + 800787a: 687b ldr r3, [r7, #4] + 800787c: 6b9b ldr r3, [r3, #56] @ 0x38 + 800787e: f423 3280 bic.w r2, r3, #65536 @ 0x10000 + 8007882: 687b ldr r3, [r7, #4] + 8007884: 639a str r2, [r3, #56] @ 0x38 + 8007886: 687b ldr r3, [r7, #4] + 8007888: 68db ldr r3, [r3, #12] + 800788a: f423 0384 bic.w r3, r3, #4325376 @ 0x420000 + 800788e: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8007892: 687a ldr r2, [r7, #4] + 8007894: 60d3 str r3, [r2, #12] + 8007896: 687b ldr r3, [r7, #4] + 8007898: 68db ldr r3, [r3, #12] + 800789a: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 + 800789e: 687b ldr r3, [r7, #4] + 80078a0: 60da str r2, [r3, #12] + 80078a2: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 + 80078a6: 2b01 cmp r3, #1 + 80078a8: d105 bne.n 80078b6 + 80078aa: 687b ldr r3, [r7, #4] + 80078ac: 68db ldr r3, [r3, #12] + 80078ae: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 + 80078b2: 687b ldr r3, [r7, #4] + 80078b4: 60da str r2, [r3, #12] + 80078b6: 6878 ldr r0, [r7, #4] + 80078b8: f001 fae2 bl 8008e80 + 80078bc: 4603 mov r3, r0 + 80078be: 73fb strb r3, [r7, #15] + 80078c0: e01b b.n 80078fa + 80078c2: 687b ldr r3, [r7, #4] + 80078c4: 68db ldr r3, [r3, #12] + 80078c6: f043 0240 orr.w r2, r3, #64 @ 0x40 + 80078ca: 687b ldr r3, [r7, #4] + 80078cc: 60da str r2, [r3, #12] + 80078ce: 6878 ldr r0, [r7, #4] + 80078d0: f001 fad6 bl 8008e80 + 80078d4: 4603 mov r3, r0 + 80078d6: 73fb strb r3, [r7, #15] + 80078d8: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 + 80078dc: 2b00 cmp r3, #0 + 80078de: d106 bne.n 80078ee + 80078e0: 687b ldr r3, [r7, #4] + 80078e2: 6b9b ldr r3, [r3, #56] @ 0x38 + 80078e4: f443 3280 orr.w r2, r3, #65536 @ 0x10000 + 80078e8: 687b ldr r3, [r7, #4] + 80078ea: 639a str r2, [r3, #56] @ 0x38 + 80078ec: e005 b.n 80078fa + 80078ee: 687b ldr r3, [r7, #4] + 80078f0: 6b9b ldr r3, [r3, #56] @ 0x38 + 80078f2: f423 3280 bic.w r2, r3, #65536 @ 0x10000 + 80078f6: 687b ldr r3, [r7, #4] + 80078f8: 639a str r2, [r3, #56] @ 0x38 + 80078fa: 7fbb ldrb r3, [r7, #30] + 80078fc: 2b01 cmp r3, #1 + 80078fe: d10b bne.n 8007918 + 8007900: 687b ldr r3, [r7, #4] + 8007902: 689b ldr r3, [r3, #8] + 8007904: f043 0206 orr.w r2, r3, #6 + 8007908: 687b ldr r3, [r7, #4] + 800790a: 609a str r2, [r3, #8] + 800790c: 687b ldr r3, [r7, #4] + 800790e: 689b ldr r3, [r3, #8] + 8007910: f043 0220 orr.w r2, r3, #32 + 8007914: 687b ldr r3, [r7, #4] + 8007916: 609a str r2, [r3, #8] + 8007918: 7bfb ldrb r3, [r7, #15] + 800791a: 4618 mov r0, r3 + 800791c: 3710 adds r7, #16 + 800791e: 46bd mov sp, r7 + 8007920: e8bd 4080 ldmia.w sp!, {r7, lr} + 8007924: b004 add sp, #16 + 8007926: 4770 bx lr + +08007928 : + 8007928: b480 push {r7} + 800792a: b087 sub sp, #28 + 800792c: af00 add r7, sp, #0 + 800792e: 60f8 str r0, [r7, #12] + 8007930: 60b9 str r1, [r7, #8] + 8007932: 4613 mov r3, r2 + 8007934: 71fb strb r3, [r7, #7] + 8007936: 79fb ldrb r3, [r7, #7] + 8007938: 2b02 cmp r3, #2 + 800793a: d165 bne.n 8007a08 + 800793c: 68bb ldr r3, [r7, #8] + 800793e: 4a41 ldr r2, [pc, #260] @ (8007a44 ) + 8007940: 4293 cmp r3, r2 + 8007942: d906 bls.n 8007952 + 8007944: 68bb ldr r3, [r7, #8] + 8007946: 4a40 ldr r2, [pc, #256] @ (8007a48 ) + 8007948: 4293 cmp r3, r2 + 800794a: d202 bcs.n 8007952 + 800794c: 230f movs r3, #15 + 800794e: 617b str r3, [r7, #20] + 8007950: e062 b.n 8007a18 + 8007952: 68bb ldr r3, [r7, #8] + 8007954: 4a3c ldr r2, [pc, #240] @ (8007a48 ) + 8007956: 4293 cmp r3, r2 + 8007958: d306 bcc.n 8007968 + 800795a: 68bb ldr r3, [r7, #8] + 800795c: 4a3b ldr r2, [pc, #236] @ (8007a4c ) + 800795e: 4293 cmp r3, r2 + 8007960: d202 bcs.n 8007968 + 8007962: 230e movs r3, #14 + 8007964: 617b str r3, [r7, #20] + 8007966: e057 b.n 8007a18 + 8007968: 68bb ldr r3, [r7, #8] + 800796a: 4a38 ldr r2, [pc, #224] @ (8007a4c ) + 800796c: 4293 cmp r3, r2 + 800796e: d306 bcc.n 800797e + 8007970: 68bb ldr r3, [r7, #8] + 8007972: 4a37 ldr r2, [pc, #220] @ (8007a50 ) + 8007974: 4293 cmp r3, r2 + 8007976: d202 bcs.n 800797e + 8007978: 230d movs r3, #13 + 800797a: 617b str r3, [r7, #20] + 800797c: e04c b.n 8007a18 + 800797e: 68bb ldr r3, [r7, #8] + 8007980: 4a33 ldr r2, [pc, #204] @ (8007a50 ) + 8007982: 4293 cmp r3, r2 + 8007984: d306 bcc.n 8007994 + 8007986: 68bb ldr r3, [r7, #8] + 8007988: 4a32 ldr r2, [pc, #200] @ (8007a54 ) + 800798a: 4293 cmp r3, r2 + 800798c: d802 bhi.n 8007994 + 800798e: 230c movs r3, #12 + 8007990: 617b str r3, [r7, #20] + 8007992: e041 b.n 8007a18 + 8007994: 68bb ldr r3, [r7, #8] + 8007996: 4a2f ldr r2, [pc, #188] @ (8007a54 ) + 8007998: 4293 cmp r3, r2 + 800799a: d906 bls.n 80079aa + 800799c: 68bb ldr r3, [r7, #8] + 800799e: 4a2e ldr r2, [pc, #184] @ (8007a58 ) + 80079a0: 4293 cmp r3, r2 + 80079a2: d802 bhi.n 80079aa + 80079a4: 230b movs r3, #11 + 80079a6: 617b str r3, [r7, #20] + 80079a8: e036 b.n 8007a18 + 80079aa: 68bb ldr r3, [r7, #8] + 80079ac: 4a2a ldr r2, [pc, #168] @ (8007a58 ) + 80079ae: 4293 cmp r3, r2 + 80079b0: d906 bls.n 80079c0 + 80079b2: 68bb ldr r3, [r7, #8] + 80079b4: 4a29 ldr r2, [pc, #164] @ (8007a5c ) + 80079b6: 4293 cmp r3, r2 + 80079b8: d802 bhi.n 80079c0 + 80079ba: 230a movs r3, #10 + 80079bc: 617b str r3, [r7, #20] + 80079be: e02b b.n 8007a18 + 80079c0: 68bb ldr r3, [r7, #8] + 80079c2: 4a26 ldr r2, [pc, #152] @ (8007a5c ) + 80079c4: 4293 cmp r3, r2 + 80079c6: d906 bls.n 80079d6 + 80079c8: 68bb ldr r3, [r7, #8] + 80079ca: 4a25 ldr r2, [pc, #148] @ (8007a60 ) + 80079cc: 4293 cmp r3, r2 + 80079ce: d202 bcs.n 80079d6 + 80079d0: 2309 movs r3, #9 + 80079d2: 617b str r3, [r7, #20] + 80079d4: e020 b.n 8007a18 + 80079d6: 68bb ldr r3, [r7, #8] + 80079d8: 4a21 ldr r2, [pc, #132] @ (8007a60 ) + 80079da: 4293 cmp r3, r2 + 80079dc: d306 bcc.n 80079ec + 80079de: 68bb ldr r3, [r7, #8] + 80079e0: 4a20 ldr r2, [pc, #128] @ (8007a64 ) + 80079e2: 4293 cmp r3, r2 + 80079e4: d802 bhi.n 80079ec + 80079e6: 2308 movs r3, #8 + 80079e8: 617b str r3, [r7, #20] + 80079ea: e015 b.n 8007a18 + 80079ec: 68bb ldr r3, [r7, #8] + 80079ee: 4a1d ldr r2, [pc, #116] @ (8007a64 ) + 80079f0: 4293 cmp r3, r2 + 80079f2: d906 bls.n 8007a02 + 80079f4: 68bb ldr r3, [r7, #8] + 80079f6: 4a1c ldr r2, [pc, #112] @ (8007a68 ) + 80079f8: 4293 cmp r3, r2 + 80079fa: d202 bcs.n 8007a02 + 80079fc: 2307 movs r3, #7 + 80079fe: 617b str r3, [r7, #20] + 8007a00: e00a b.n 8007a18 + 8007a02: 2306 movs r3, #6 + 8007a04: 617b str r3, [r7, #20] + 8007a06: e007 b.n 8007a18 + 8007a08: 79fb ldrb r3, [r7, #7] + 8007a0a: 2b00 cmp r3, #0 + 8007a0c: d102 bne.n 8007a14 + 8007a0e: 2309 movs r3, #9 + 8007a10: 617b str r3, [r7, #20] + 8007a12: e001 b.n 8007a18 + 8007a14: 2309 movs r3, #9 + 8007a16: 617b str r3, [r7, #20] + 8007a18: 68fb ldr r3, [r7, #12] + 8007a1a: 68db ldr r3, [r3, #12] + 8007a1c: f423 5270 bic.w r2, r3, #15360 @ 0x3c00 + 8007a20: 68fb ldr r3, [r7, #12] + 8007a22: 60da str r2, [r3, #12] + 8007a24: 68fb ldr r3, [r7, #12] + 8007a26: 68da ldr r2, [r3, #12] + 8007a28: 697b ldr r3, [r7, #20] + 8007a2a: 029b lsls r3, r3, #10 + 8007a2c: f403 5370 and.w r3, r3, #15360 @ 0x3c00 + 8007a30: 431a orrs r2, r3 + 8007a32: 68fb ldr r3, [r7, #12] + 8007a34: 60da str r2, [r3, #12] + 8007a36: 2300 movs r3, #0 + 8007a38: 4618 mov r0, r3 + 8007a3a: 371c adds r7, #28 + 8007a3c: 46bd mov sp, r7 + 8007a3e: f85d 7b04 ldr.w r7, [sp], #4 + 8007a42: 4770 bx lr + 8007a44: 00d8acbf .word 0x00d8acbf + 8007a48: 00e4e1c0 .word 0x00e4e1c0 + 8007a4c: 00f42400 .word 0x00f42400 + 8007a50: 01067380 .word 0x01067380 + 8007a54: 011a499f .word 0x011a499f + 8007a58: 01312cff .word 0x01312cff + 8007a5c: 014ca43f .word 0x014ca43f + 8007a60: 016e3600 .word 0x016e3600 + 8007a64: 01a6ab1f .word 0x01a6ab1f + 8007a68: 01e84800 .word 0x01e84800 + +08007a6c : + 8007a6c: b480 push {r7} + 8007a6e: b083 sub sp, #12 + 8007a70: af00 add r7, sp, #0 + 8007a72: 6078 str r0, [r7, #4] + 8007a74: 687b ldr r3, [r7, #4] + 8007a76: 689b ldr r3, [r3, #8] + 8007a78: f043 0201 orr.w r2, r3, #1 + 8007a7c: 687b ldr r3, [r7, #4] + 8007a7e: 609a str r2, [r3, #8] + 8007a80: 2300 movs r3, #0 + 8007a82: 4618 mov r0, r3 + 8007a84: 370c adds r7, #12 + 8007a86: 46bd mov sp, r7 + 8007a88: f85d 7b04 ldr.w r7, [sp], #4 + 8007a8c: 4770 bx lr + +08007a8e : + 8007a8e: b480 push {r7} + 8007a90: b083 sub sp, #12 + 8007a92: af00 add r7, sp, #0 + 8007a94: 6078 str r0, [r7, #4] + 8007a96: 687b ldr r3, [r7, #4] + 8007a98: 689b ldr r3, [r3, #8] + 8007a9a: f023 0201 bic.w r2, r3, #1 + 8007a9e: 687b ldr r3, [r7, #4] + 8007aa0: 609a str r2, [r3, #8] + 8007aa2: 2300 movs r3, #0 + 8007aa4: 4618 mov r0, r3 + 8007aa6: 370c adds r7, #12 + 8007aa8: 46bd mov sp, r7 + 8007aaa: f85d 7b04 ldr.w r7, [sp], #4 + 8007aae: 4770 bx lr + +08007ab0 : + 8007ab0: b580 push {r7, lr} + 8007ab2: b084 sub sp, #16 + 8007ab4: af00 add r7, sp, #0 + 8007ab6: 6078 str r0, [r7, #4] + 8007ab8: 460b mov r3, r1 + 8007aba: 70fb strb r3, [r7, #3] + 8007abc: 2300 movs r3, #0 + 8007abe: 60fb str r3, [r7, #12] + 8007ac0: 687b ldr r3, [r7, #4] + 8007ac2: 68db ldr r3, [r3, #12] + 8007ac4: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000 + 8007ac8: 687b ldr r3, [r7, #4] + 8007aca: 60da str r2, [r3, #12] + 8007acc: 78fb ldrb r3, [r7, #3] + 8007ace: 2b01 cmp r3, #1 + 8007ad0: d115 bne.n 8007afe + 8007ad2: 687b ldr r3, [r7, #4] + 8007ad4: 68db ldr r3, [r3, #12] + 8007ad6: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 + 8007ada: 687b ldr r3, [r7, #4] + 8007adc: 60da str r2, [r3, #12] + 8007ade: 200a movs r0, #10 + 8007ae0: f7fa fa2e bl 8001f40 + 8007ae4: 68fb ldr r3, [r7, #12] + 8007ae6: 330a adds r3, #10 + 8007ae8: 60fb str r3, [r7, #12] + 8007aea: 6878 ldr r0, [r7, #4] + 8007aec: f001 f939 bl 8008d62 + 8007af0: 4603 mov r3, r0 + 8007af2: 2b01 cmp r3, #1 + 8007af4: d01e beq.n 8007b34 + 8007af6: 68fb ldr r3, [r7, #12] + 8007af8: 2bc7 cmp r3, #199 @ 0xc7 + 8007afa: d9f0 bls.n 8007ade + 8007afc: e01a b.n 8007b34 + 8007afe: 78fb ldrb r3, [r7, #3] + 8007b00: 2b00 cmp r3, #0 + 8007b02: d115 bne.n 8007b30 + 8007b04: 687b ldr r3, [r7, #4] + 8007b06: 68db ldr r3, [r3, #12] + 8007b08: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000 + 8007b0c: 687b ldr r3, [r7, #4] + 8007b0e: 60da str r2, [r3, #12] + 8007b10: 200a movs r0, #10 + 8007b12: f7fa fa15 bl 8001f40 + 8007b16: 68fb ldr r3, [r7, #12] + 8007b18: 330a adds r3, #10 + 8007b1a: 60fb str r3, [r7, #12] + 8007b1c: 6878 ldr r0, [r7, #4] + 8007b1e: f001 f920 bl 8008d62 + 8007b22: 4603 mov r3, r0 + 8007b24: 2b00 cmp r3, #0 + 8007b26: d005 beq.n 8007b34 + 8007b28: 68fb ldr r3, [r7, #12] + 8007b2a: 2bc7 cmp r3, #199 @ 0xc7 + 8007b2c: d9f0 bls.n 8007b10 + 8007b2e: e001 b.n 8007b34 + 8007b30: 2301 movs r3, #1 + 8007b32: e005 b.n 8007b40 + 8007b34: 68fb ldr r3, [r7, #12] + 8007b36: 2bc8 cmp r3, #200 @ 0xc8 + 8007b38: d101 bne.n 8007b3e + 8007b3a: 2301 movs r3, #1 + 8007b3c: e000 b.n 8007b40 + 8007b3e: 2300 movs r3, #0 + 8007b40: 4618 mov r0, r3 + 8007b42: 3710 adds r7, #16 + 8007b44: 46bd mov sp, r7 + 8007b46: bd80 pop {r7, pc} + +08007b48 : + 8007b48: b084 sub sp, #16 + 8007b4a: b580 push {r7, lr} + 8007b4c: b086 sub sp, #24 + 8007b4e: af00 add r7, sp, #0 + 8007b50: 6078 str r0, [r7, #4] + 8007b52: f107 0024 add.w r0, r7, #36 @ 0x24 + 8007b56: e880 000e stmia.w r0, {r1, r2, r3} + 8007b5a: 2300 movs r3, #0 + 8007b5c: 75fb strb r3, [r7, #23] + 8007b5e: 687b ldr r3, [r7, #4] + 8007b60: 60fb str r3, [r7, #12] + 8007b62: 2300 movs r3, #0 + 8007b64: 613b str r3, [r7, #16] + 8007b66: e009 b.n 8007b7c + 8007b68: 687a ldr r2, [r7, #4] + 8007b6a: 693b ldr r3, [r7, #16] + 8007b6c: 3340 adds r3, #64 @ 0x40 + 8007b6e: 009b lsls r3, r3, #2 + 8007b70: 4413 add r3, r2 + 8007b72: 2200 movs r2, #0 + 8007b74: 605a str r2, [r3, #4] + 8007b76: 693b ldr r3, [r7, #16] + 8007b78: 3301 adds r3, #1 + 8007b7a: 613b str r3, [r7, #16] + 8007b7c: 693b ldr r3, [r7, #16] + 8007b7e: 2b0e cmp r3, #14 + 8007b80: d9f2 bls.n 8007b68 + 8007b82: f897 302e ldrb.w r3, [r7, #46] @ 0x2e + 8007b86: 2b00 cmp r3, #0 + 8007b88: d11c bne.n 8007bc4 + 8007b8a: 68fb ldr r3, [r7, #12] + 8007b8c: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8007b90: 685b ldr r3, [r3, #4] + 8007b92: 68fa ldr r2, [r7, #12] + 8007b94: f502 6200 add.w r2, r2, #2048 @ 0x800 + 8007b98: f043 0302 orr.w r3, r3, #2 + 8007b9c: 6053 str r3, [r2, #4] + 8007b9e: 687b ldr r3, [r7, #4] + 8007ba0: 6b9b ldr r3, [r3, #56] @ 0x38 + 8007ba2: f423 1200 bic.w r2, r3, #2097152 @ 0x200000 + 8007ba6: 687b ldr r3, [r7, #4] + 8007ba8: 639a str r2, [r3, #56] @ 0x38 + 8007baa: 687b ldr r3, [r7, #4] + 8007bac: 681b ldr r3, [r3, #0] + 8007bae: f043 0240 orr.w r2, r3, #64 @ 0x40 + 8007bb2: 687b ldr r3, [r7, #4] + 8007bb4: 601a str r2, [r3, #0] + 8007bb6: 687b ldr r3, [r7, #4] + 8007bb8: 681b ldr r3, [r3, #0] + 8007bba: f043 0280 orr.w r2, r3, #128 @ 0x80 + 8007bbe: 687b ldr r3, [r7, #4] + 8007bc0: 601a str r2, [r3, #0] + 8007bc2: e005 b.n 8007bd0 + 8007bc4: 687b ldr r3, [r7, #4] + 8007bc6: 6b9b ldr r3, [r3, #56] @ 0x38 + 8007bc8: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 + 8007bcc: 687b ldr r3, [r7, #4] + 8007bce: 639a str r2, [r3, #56] @ 0x38 + 8007bd0: 68fb ldr r3, [r7, #12] + 8007bd2: f503 6360 add.w r3, r3, #3584 @ 0xe00 + 8007bd6: 461a mov r2, r3 + 8007bd8: 2300 movs r3, #0 + 8007bda: 6013 str r3, [r2, #0] + 8007bdc: f897 3029 ldrb.w r3, [r7, #41] @ 0x29 + 8007be0: 2b01 cmp r3, #1 + 8007be2: d10d bne.n 8007c00 + 8007be4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 + 8007be8: 2b00 cmp r3, #0 + 8007bea: d104 bne.n 8007bf6 + 8007bec: 2100 movs r1, #0 + 8007bee: 6878 ldr r0, [r7, #4] + 8007bf0: f000 f968 bl 8007ec4 + 8007bf4: e008 b.n 8007c08 + 8007bf6: 2101 movs r1, #1 + 8007bf8: 6878 ldr r0, [r7, #4] + 8007bfa: f000 f963 bl 8007ec4 + 8007bfe: e003 b.n 8007c08 + 8007c00: 2103 movs r1, #3 + 8007c02: 6878 ldr r0, [r7, #4] + 8007c04: f000 f95e bl 8007ec4 + 8007c08: 2110 movs r1, #16 + 8007c0a: 6878 ldr r0, [r7, #4] + 8007c0c: f000 f8fa bl 8007e04 + 8007c10: 4603 mov r3, r0 + 8007c12: 2b00 cmp r3, #0 + 8007c14: d001 beq.n 8007c1a + 8007c16: 2301 movs r3, #1 + 8007c18: 75fb strb r3, [r7, #23] + 8007c1a: 6878 ldr r0, [r7, #4] + 8007c1c: f000 f924 bl 8007e68 + 8007c20: 4603 mov r3, r0 + 8007c22: 2b00 cmp r3, #0 + 8007c24: d001 beq.n 8007c2a + 8007c26: 2301 movs r3, #1 + 8007c28: 75fb strb r3, [r7, #23] + 8007c2a: 68fb ldr r3, [r7, #12] + 8007c2c: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8007c30: 461a mov r2, r3 + 8007c32: 2300 movs r3, #0 + 8007c34: 6113 str r3, [r2, #16] + 8007c36: 68fb ldr r3, [r7, #12] + 8007c38: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8007c3c: 461a mov r2, r3 + 8007c3e: 2300 movs r3, #0 + 8007c40: 6153 str r3, [r2, #20] + 8007c42: 68fb ldr r3, [r7, #12] + 8007c44: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8007c48: 461a mov r2, r3 + 8007c4a: 2300 movs r3, #0 + 8007c4c: 61d3 str r3, [r2, #28] + 8007c4e: 2300 movs r3, #0 + 8007c50: 613b str r3, [r7, #16] + 8007c52: e043 b.n 8007cdc + 8007c54: 693b ldr r3, [r7, #16] + 8007c56: 015a lsls r2, r3, #5 + 8007c58: 68fb ldr r3, [r7, #12] + 8007c5a: 4413 add r3, r2 + 8007c5c: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8007c60: 681b ldr r3, [r3, #0] + 8007c62: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 8007c66: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 8007c6a: d118 bne.n 8007c9e + 8007c6c: 693b ldr r3, [r7, #16] + 8007c6e: 2b00 cmp r3, #0 + 8007c70: d10a bne.n 8007c88 + 8007c72: 693b ldr r3, [r7, #16] + 8007c74: 015a lsls r2, r3, #5 + 8007c76: 68fb ldr r3, [r7, #12] + 8007c78: 4413 add r3, r2 + 8007c7a: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8007c7e: 461a mov r2, r3 + 8007c80: f04f 6300 mov.w r3, #134217728 @ 0x8000000 + 8007c84: 6013 str r3, [r2, #0] + 8007c86: e013 b.n 8007cb0 + 8007c88: 693b ldr r3, [r7, #16] + 8007c8a: 015a lsls r2, r3, #5 + 8007c8c: 68fb ldr r3, [r7, #12] + 8007c8e: 4413 add r3, r2 + 8007c90: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8007c94: 461a mov r2, r3 + 8007c96: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 + 8007c9a: 6013 str r3, [r2, #0] + 8007c9c: e008 b.n 8007cb0 + 8007c9e: 693b ldr r3, [r7, #16] + 8007ca0: 015a lsls r2, r3, #5 + 8007ca2: 68fb ldr r3, [r7, #12] + 8007ca4: 4413 add r3, r2 + 8007ca6: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8007caa: 461a mov r2, r3 + 8007cac: 2300 movs r3, #0 + 8007cae: 6013 str r3, [r2, #0] + 8007cb0: 693b ldr r3, [r7, #16] + 8007cb2: 015a lsls r2, r3, #5 + 8007cb4: 68fb ldr r3, [r7, #12] + 8007cb6: 4413 add r3, r2 + 8007cb8: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8007cbc: 461a mov r2, r3 + 8007cbe: 2300 movs r3, #0 + 8007cc0: 6113 str r3, [r2, #16] + 8007cc2: 693b ldr r3, [r7, #16] + 8007cc4: 015a lsls r2, r3, #5 + 8007cc6: 68fb ldr r3, [r7, #12] + 8007cc8: 4413 add r3, r2 + 8007cca: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8007cce: 461a mov r2, r3 + 8007cd0: f64f 337f movw r3, #64383 @ 0xfb7f + 8007cd4: 6093 str r3, [r2, #8] + 8007cd6: 693b ldr r3, [r7, #16] + 8007cd8: 3301 adds r3, #1 + 8007cda: 613b str r3, [r7, #16] + 8007cdc: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 8007ce0: 461a mov r2, r3 + 8007ce2: 693b ldr r3, [r7, #16] + 8007ce4: 4293 cmp r3, r2 + 8007ce6: d3b5 bcc.n 8007c54 + 8007ce8: 2300 movs r3, #0 + 8007cea: 613b str r3, [r7, #16] + 8007cec: e043 b.n 8007d76 + 8007cee: 693b ldr r3, [r7, #16] + 8007cf0: 015a lsls r2, r3, #5 + 8007cf2: 68fb ldr r3, [r7, #12] + 8007cf4: 4413 add r3, r2 + 8007cf6: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8007cfa: 681b ldr r3, [r3, #0] + 8007cfc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 8007d00: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 8007d04: d118 bne.n 8007d38 + 8007d06: 693b ldr r3, [r7, #16] + 8007d08: 2b00 cmp r3, #0 + 8007d0a: d10a bne.n 8007d22 + 8007d0c: 693b ldr r3, [r7, #16] + 8007d0e: 015a lsls r2, r3, #5 + 8007d10: 68fb ldr r3, [r7, #12] + 8007d12: 4413 add r3, r2 + 8007d14: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8007d18: 461a mov r2, r3 + 8007d1a: f04f 6300 mov.w r3, #134217728 @ 0x8000000 + 8007d1e: 6013 str r3, [r2, #0] + 8007d20: e013 b.n 8007d4a + 8007d22: 693b ldr r3, [r7, #16] + 8007d24: 015a lsls r2, r3, #5 + 8007d26: 68fb ldr r3, [r7, #12] + 8007d28: 4413 add r3, r2 + 8007d2a: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8007d2e: 461a mov r2, r3 + 8007d30: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 + 8007d34: 6013 str r3, [r2, #0] + 8007d36: e008 b.n 8007d4a + 8007d38: 693b ldr r3, [r7, #16] + 8007d3a: 015a lsls r2, r3, #5 + 8007d3c: 68fb ldr r3, [r7, #12] + 8007d3e: 4413 add r3, r2 + 8007d40: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8007d44: 461a mov r2, r3 + 8007d46: 2300 movs r3, #0 + 8007d48: 6013 str r3, [r2, #0] + 8007d4a: 693b ldr r3, [r7, #16] + 8007d4c: 015a lsls r2, r3, #5 + 8007d4e: 68fb ldr r3, [r7, #12] + 8007d50: 4413 add r3, r2 + 8007d52: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8007d56: 461a mov r2, r3 + 8007d58: 2300 movs r3, #0 + 8007d5a: 6113 str r3, [r2, #16] + 8007d5c: 693b ldr r3, [r7, #16] + 8007d5e: 015a lsls r2, r3, #5 + 8007d60: 68fb ldr r3, [r7, #12] + 8007d62: 4413 add r3, r2 + 8007d64: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8007d68: 461a mov r2, r3 + 8007d6a: f64f 337f movw r3, #64383 @ 0xfb7f + 8007d6e: 6093 str r3, [r2, #8] + 8007d70: 693b ldr r3, [r7, #16] + 8007d72: 3301 adds r3, #1 + 8007d74: 613b str r3, [r7, #16] + 8007d76: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 8007d7a: 461a mov r2, r3 + 8007d7c: 693b ldr r3, [r7, #16] + 8007d7e: 4293 cmp r3, r2 + 8007d80: d3b5 bcc.n 8007cee + 8007d82: 68fb ldr r3, [r7, #12] + 8007d84: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8007d88: 691b ldr r3, [r3, #16] + 8007d8a: 68fa ldr r2, [r7, #12] + 8007d8c: f502 6200 add.w r2, r2, #2048 @ 0x800 + 8007d90: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8007d94: 6113 str r3, [r2, #16] + 8007d96: 687b ldr r3, [r7, #4] + 8007d98: 2200 movs r2, #0 + 8007d9a: 619a str r2, [r3, #24] + 8007d9c: 687b ldr r3, [r7, #4] + 8007d9e: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000 + 8007da2: 615a str r2, [r3, #20] + 8007da4: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 + 8007da8: 2b00 cmp r3, #0 + 8007daa: d105 bne.n 8007db8 + 8007dac: 687b ldr r3, [r7, #4] + 8007dae: 699b ldr r3, [r3, #24] + 8007db0: f043 0210 orr.w r2, r3, #16 + 8007db4: 687b ldr r3, [r7, #4] + 8007db6: 619a str r2, [r3, #24] + 8007db8: 687b ldr r3, [r7, #4] + 8007dba: 699a ldr r2, [r3, #24] + 8007dbc: 4b10 ldr r3, [pc, #64] @ (8007e00 ) + 8007dbe: 4313 orrs r3, r2 + 8007dc0: 687a ldr r2, [r7, #4] + 8007dc2: 6193 str r3, [r2, #24] + 8007dc4: f897 302a ldrb.w r3, [r7, #42] @ 0x2a + 8007dc8: 2b00 cmp r3, #0 + 8007dca: d005 beq.n 8007dd8 + 8007dcc: 687b ldr r3, [r7, #4] + 8007dce: 699b ldr r3, [r3, #24] + 8007dd0: f043 0208 orr.w r2, r3, #8 + 8007dd4: 687b ldr r3, [r7, #4] + 8007dd6: 619a str r2, [r3, #24] + 8007dd8: f897 302e ldrb.w r3, [r7, #46] @ 0x2e + 8007ddc: 2b01 cmp r3, #1 + 8007dde: d107 bne.n 8007df0 + 8007de0: 687b ldr r3, [r7, #4] + 8007de2: 699b ldr r3, [r3, #24] + 8007de4: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 + 8007de8: f043 0304 orr.w r3, r3, #4 + 8007dec: 687a ldr r2, [r7, #4] + 8007dee: 6193 str r3, [r2, #24] + 8007df0: 7dfb ldrb r3, [r7, #23] + 8007df2: 4618 mov r0, r3 + 8007df4: 3718 adds r7, #24 + 8007df6: 46bd mov sp, r7 + 8007df8: e8bd 4080 ldmia.w sp!, {r7, lr} + 8007dfc: b004 add sp, #16 + 8007dfe: 4770 bx lr + 8007e00: 803c3800 .word 0x803c3800 + +08007e04 : + 8007e04: b480 push {r7} + 8007e06: b085 sub sp, #20 + 8007e08: af00 add r7, sp, #0 + 8007e0a: 6078 str r0, [r7, #4] + 8007e0c: 6039 str r1, [r7, #0] + 8007e0e: 2300 movs r3, #0 + 8007e10: 60fb str r3, [r7, #12] + 8007e12: 68fb ldr r3, [r7, #12] + 8007e14: 3301 adds r3, #1 + 8007e16: 60fb str r3, [r7, #12] + 8007e18: 68fb ldr r3, [r7, #12] + 8007e1a: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 8007e1e: d901 bls.n 8007e24 + 8007e20: 2303 movs r3, #3 + 8007e22: e01b b.n 8007e5c + 8007e24: 687b ldr r3, [r7, #4] + 8007e26: 691b ldr r3, [r3, #16] + 8007e28: 2b00 cmp r3, #0 + 8007e2a: daf2 bge.n 8007e12 + 8007e2c: 2300 movs r3, #0 + 8007e2e: 60fb str r3, [r7, #12] + 8007e30: 683b ldr r3, [r7, #0] + 8007e32: 019b lsls r3, r3, #6 + 8007e34: f043 0220 orr.w r2, r3, #32 + 8007e38: 687b ldr r3, [r7, #4] + 8007e3a: 611a str r2, [r3, #16] + 8007e3c: 68fb ldr r3, [r7, #12] + 8007e3e: 3301 adds r3, #1 + 8007e40: 60fb str r3, [r7, #12] + 8007e42: 68fb ldr r3, [r7, #12] + 8007e44: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 8007e48: d901 bls.n 8007e4e + 8007e4a: 2303 movs r3, #3 + 8007e4c: e006 b.n 8007e5c + 8007e4e: 687b ldr r3, [r7, #4] + 8007e50: 691b ldr r3, [r3, #16] + 8007e52: f003 0320 and.w r3, r3, #32 + 8007e56: 2b20 cmp r3, #32 + 8007e58: d0f0 beq.n 8007e3c + 8007e5a: 2300 movs r3, #0 + 8007e5c: 4618 mov r0, r3 + 8007e5e: 3714 adds r7, #20 + 8007e60: 46bd mov sp, r7 + 8007e62: f85d 7b04 ldr.w r7, [sp], #4 + 8007e66: 4770 bx lr + +08007e68 : + 8007e68: b480 push {r7} + 8007e6a: b085 sub sp, #20 + 8007e6c: af00 add r7, sp, #0 + 8007e6e: 6078 str r0, [r7, #4] + 8007e70: 2300 movs r3, #0 + 8007e72: 60fb str r3, [r7, #12] + 8007e74: 68fb ldr r3, [r7, #12] + 8007e76: 3301 adds r3, #1 + 8007e78: 60fb str r3, [r7, #12] + 8007e7a: 68fb ldr r3, [r7, #12] + 8007e7c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 8007e80: d901 bls.n 8007e86 + 8007e82: 2303 movs r3, #3 + 8007e84: e018 b.n 8007eb8 + 8007e86: 687b ldr r3, [r7, #4] + 8007e88: 691b ldr r3, [r3, #16] + 8007e8a: 2b00 cmp r3, #0 + 8007e8c: daf2 bge.n 8007e74 + 8007e8e: 2300 movs r3, #0 + 8007e90: 60fb str r3, [r7, #12] + 8007e92: 687b ldr r3, [r7, #4] + 8007e94: 2210 movs r2, #16 + 8007e96: 611a str r2, [r3, #16] + 8007e98: 68fb ldr r3, [r7, #12] + 8007e9a: 3301 adds r3, #1 + 8007e9c: 60fb str r3, [r7, #12] + 8007e9e: 68fb ldr r3, [r7, #12] + 8007ea0: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 8007ea4: d901 bls.n 8007eaa + 8007ea6: 2303 movs r3, #3 + 8007ea8: e006 b.n 8007eb8 + 8007eaa: 687b ldr r3, [r7, #4] + 8007eac: 691b ldr r3, [r3, #16] + 8007eae: f003 0310 and.w r3, r3, #16 + 8007eb2: 2b10 cmp r3, #16 + 8007eb4: d0f0 beq.n 8007e98 + 8007eb6: 2300 movs r3, #0 + 8007eb8: 4618 mov r0, r3 + 8007eba: 3714 adds r7, #20 + 8007ebc: 46bd mov sp, r7 + 8007ebe: f85d 7b04 ldr.w r7, [sp], #4 + 8007ec2: 4770 bx lr + +08007ec4 : + 8007ec4: b480 push {r7} + 8007ec6: b085 sub sp, #20 + 8007ec8: af00 add r7, sp, #0 + 8007eca: 6078 str r0, [r7, #4] + 8007ecc: 460b mov r3, r1 + 8007ece: 70fb strb r3, [r7, #3] + 8007ed0: 687b ldr r3, [r7, #4] + 8007ed2: 60fb str r3, [r7, #12] + 8007ed4: 68fb ldr r3, [r7, #12] + 8007ed6: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8007eda: 681a ldr r2, [r3, #0] + 8007edc: 78fb ldrb r3, [r7, #3] + 8007ede: 68f9 ldr r1, [r7, #12] + 8007ee0: f501 6100 add.w r1, r1, #2048 @ 0x800 + 8007ee4: 4313 orrs r3, r2 + 8007ee6: 600b str r3, [r1, #0] + 8007ee8: 2300 movs r3, #0 + 8007eea: 4618 mov r0, r3 + 8007eec: 3714 adds r7, #20 + 8007eee: 46bd mov sp, r7 + 8007ef0: f85d 7b04 ldr.w r7, [sp], #4 + 8007ef4: 4770 bx lr + +08007ef6 : + 8007ef6: b480 push {r7} + 8007ef8: b087 sub sp, #28 + 8007efa: af00 add r7, sp, #0 + 8007efc: 6078 str r0, [r7, #4] + 8007efe: 687b ldr r3, [r7, #4] + 8007f00: 613b str r3, [r7, #16] + 8007f02: 693b ldr r3, [r7, #16] + 8007f04: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8007f08: 689b ldr r3, [r3, #8] + 8007f0a: f003 0306 and.w r3, r3, #6 + 8007f0e: 60fb str r3, [r7, #12] + 8007f10: 68fb ldr r3, [r7, #12] + 8007f12: 2b00 cmp r3, #0 + 8007f14: d102 bne.n 8007f1c + 8007f16: 2300 movs r3, #0 + 8007f18: 75fb strb r3, [r7, #23] + 8007f1a: e00a b.n 8007f32 + 8007f1c: 68fb ldr r3, [r7, #12] + 8007f1e: 2b02 cmp r3, #2 + 8007f20: d002 beq.n 8007f28 + 8007f22: 68fb ldr r3, [r7, #12] + 8007f24: 2b06 cmp r3, #6 + 8007f26: d102 bne.n 8007f2e + 8007f28: 2302 movs r3, #2 + 8007f2a: 75fb strb r3, [r7, #23] + 8007f2c: e001 b.n 8007f32 + 8007f2e: 230f movs r3, #15 + 8007f30: 75fb strb r3, [r7, #23] + 8007f32: 7dfb ldrb r3, [r7, #23] + 8007f34: 4618 mov r0, r3 + 8007f36: 371c adds r7, #28 + 8007f38: 46bd mov sp, r7 + 8007f3a: f85d 7b04 ldr.w r7, [sp], #4 + 8007f3e: 4770 bx lr + +08007f40 : + 8007f40: b480 push {r7} + 8007f42: b085 sub sp, #20 + 8007f44: af00 add r7, sp, #0 + 8007f46: 6078 str r0, [r7, #4] + 8007f48: 6039 str r1, [r7, #0] + 8007f4a: 687b ldr r3, [r7, #4] + 8007f4c: 60fb str r3, [r7, #12] + 8007f4e: 683b ldr r3, [r7, #0] + 8007f50: 781b ldrb r3, [r3, #0] + 8007f52: 60bb str r3, [r7, #8] + 8007f54: 683b ldr r3, [r7, #0] + 8007f56: 785b ldrb r3, [r3, #1] + 8007f58: 2b01 cmp r3, #1 + 8007f5a: d13a bne.n 8007fd2 + 8007f5c: 68fb ldr r3, [r7, #12] + 8007f5e: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8007f62: 69da ldr r2, [r3, #28] + 8007f64: 683b ldr r3, [r7, #0] + 8007f66: 781b ldrb r3, [r3, #0] + 8007f68: f003 030f and.w r3, r3, #15 + 8007f6c: 2101 movs r1, #1 + 8007f6e: fa01 f303 lsl.w r3, r1, r3 + 8007f72: b29b uxth r3, r3 + 8007f74: 68f9 ldr r1, [r7, #12] + 8007f76: f501 6100 add.w r1, r1, #2048 @ 0x800 + 8007f7a: 4313 orrs r3, r2 + 8007f7c: 61cb str r3, [r1, #28] + 8007f7e: 68bb ldr r3, [r7, #8] + 8007f80: 015a lsls r2, r3, #5 + 8007f82: 68fb ldr r3, [r7, #12] + 8007f84: 4413 add r3, r2 + 8007f86: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8007f8a: 681b ldr r3, [r3, #0] + 8007f8c: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 8007f90: 2b00 cmp r3, #0 + 8007f92: d155 bne.n 8008040 + 8007f94: 68bb ldr r3, [r7, #8] + 8007f96: 015a lsls r2, r3, #5 + 8007f98: 68fb ldr r3, [r7, #12] + 8007f9a: 4413 add r3, r2 + 8007f9c: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8007fa0: 681a ldr r2, [r3, #0] + 8007fa2: 683b ldr r3, [r7, #0] + 8007fa4: 689b ldr r3, [r3, #8] + 8007fa6: f3c3 010a ubfx r1, r3, #0, #11 + 8007faa: 683b ldr r3, [r7, #0] + 8007fac: 791b ldrb r3, [r3, #4] + 8007fae: 049b lsls r3, r3, #18 + 8007fb0: 4319 orrs r1, r3 + 8007fb2: 68bb ldr r3, [r7, #8] + 8007fb4: 059b lsls r3, r3, #22 + 8007fb6: 430b orrs r3, r1 + 8007fb8: 4313 orrs r3, r2 + 8007fba: 68ba ldr r2, [r7, #8] + 8007fbc: 0151 lsls r1, r2, #5 + 8007fbe: 68fa ldr r2, [r7, #12] + 8007fc0: 440a add r2, r1 + 8007fc2: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8007fc6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8007fca: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 8007fce: 6013 str r3, [r2, #0] + 8007fd0: e036 b.n 8008040 + 8007fd2: 68fb ldr r3, [r7, #12] + 8007fd4: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8007fd8: 69da ldr r2, [r3, #28] + 8007fda: 683b ldr r3, [r7, #0] + 8007fdc: 781b ldrb r3, [r3, #0] + 8007fde: f003 030f and.w r3, r3, #15 + 8007fe2: 2101 movs r1, #1 + 8007fe4: fa01 f303 lsl.w r3, r1, r3 + 8007fe8: 041b lsls r3, r3, #16 + 8007fea: 68f9 ldr r1, [r7, #12] + 8007fec: f501 6100 add.w r1, r1, #2048 @ 0x800 + 8007ff0: 4313 orrs r3, r2 + 8007ff2: 61cb str r3, [r1, #28] + 8007ff4: 68bb ldr r3, [r7, #8] + 8007ff6: 015a lsls r2, r3, #5 + 8007ff8: 68fb ldr r3, [r7, #12] + 8007ffa: 4413 add r3, r2 + 8007ffc: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008000: 681b ldr r3, [r3, #0] + 8008002: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 8008006: 2b00 cmp r3, #0 + 8008008: d11a bne.n 8008040 + 800800a: 68bb ldr r3, [r7, #8] + 800800c: 015a lsls r2, r3, #5 + 800800e: 68fb ldr r3, [r7, #12] + 8008010: 4413 add r3, r2 + 8008012: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008016: 681a ldr r2, [r3, #0] + 8008018: 683b ldr r3, [r7, #0] + 800801a: 689b ldr r3, [r3, #8] + 800801c: f3c3 010a ubfx r1, r3, #0, #11 + 8008020: 683b ldr r3, [r7, #0] + 8008022: 791b ldrb r3, [r3, #4] + 8008024: 049b lsls r3, r3, #18 + 8008026: 430b orrs r3, r1 + 8008028: 4313 orrs r3, r2 + 800802a: 68ba ldr r2, [r7, #8] + 800802c: 0151 lsls r1, r2, #5 + 800802e: 68fa ldr r2, [r7, #12] + 8008030: 440a add r2, r1 + 8008032: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008036: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800803a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 800803e: 6013 str r3, [r2, #0] + 8008040: 2300 movs r3, #0 + 8008042: 4618 mov r0, r3 + 8008044: 3714 adds r7, #20 + 8008046: 46bd mov sp, r7 + 8008048: f85d 7b04 ldr.w r7, [sp], #4 + 800804c: 4770 bx lr + ... + +08008050 : + 8008050: b480 push {r7} + 8008052: b085 sub sp, #20 + 8008054: af00 add r7, sp, #0 + 8008056: 6078 str r0, [r7, #4] + 8008058: 6039 str r1, [r7, #0] + 800805a: 687b ldr r3, [r7, #4] + 800805c: 60fb str r3, [r7, #12] + 800805e: 683b ldr r3, [r7, #0] + 8008060: 781b ldrb r3, [r3, #0] + 8008062: 60bb str r3, [r7, #8] + 8008064: 683b ldr r3, [r7, #0] + 8008066: 785b ldrb r3, [r3, #1] + 8008068: 2b01 cmp r3, #1 + 800806a: d161 bne.n 8008130 + 800806c: 68bb ldr r3, [r7, #8] + 800806e: 015a lsls r2, r3, #5 + 8008070: 68fb ldr r3, [r7, #12] + 8008072: 4413 add r3, r2 + 8008074: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008078: 681b ldr r3, [r3, #0] + 800807a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 800807e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 8008082: d11f bne.n 80080c4 + 8008084: 68bb ldr r3, [r7, #8] + 8008086: 015a lsls r2, r3, #5 + 8008088: 68fb ldr r3, [r7, #12] + 800808a: 4413 add r3, r2 + 800808c: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008090: 681b ldr r3, [r3, #0] + 8008092: 68ba ldr r2, [r7, #8] + 8008094: 0151 lsls r1, r2, #5 + 8008096: 68fa ldr r2, [r7, #12] + 8008098: 440a add r2, r1 + 800809a: f502 6210 add.w r2, r2, #2304 @ 0x900 + 800809e: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 + 80080a2: 6013 str r3, [r2, #0] + 80080a4: 68bb ldr r3, [r7, #8] + 80080a6: 015a lsls r2, r3, #5 + 80080a8: 68fb ldr r3, [r7, #12] + 80080aa: 4413 add r3, r2 + 80080ac: f503 6310 add.w r3, r3, #2304 @ 0x900 + 80080b0: 681b ldr r3, [r3, #0] + 80080b2: 68ba ldr r2, [r7, #8] + 80080b4: 0151 lsls r1, r2, #5 + 80080b6: 68fa ldr r2, [r7, #12] + 80080b8: 440a add r2, r1 + 80080ba: f502 6210 add.w r2, r2, #2304 @ 0x900 + 80080be: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 + 80080c2: 6013 str r3, [r2, #0] + 80080c4: 68fb ldr r3, [r7, #12] + 80080c6: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80080ca: 6bda ldr r2, [r3, #60] @ 0x3c + 80080cc: 683b ldr r3, [r7, #0] + 80080ce: 781b ldrb r3, [r3, #0] + 80080d0: f003 030f and.w r3, r3, #15 + 80080d4: 2101 movs r1, #1 + 80080d6: fa01 f303 lsl.w r3, r1, r3 + 80080da: b29b uxth r3, r3 + 80080dc: 43db mvns r3, r3 + 80080de: 68f9 ldr r1, [r7, #12] + 80080e0: f501 6100 add.w r1, r1, #2048 @ 0x800 + 80080e4: 4013 ands r3, r2 + 80080e6: 63cb str r3, [r1, #60] @ 0x3c + 80080e8: 68fb ldr r3, [r7, #12] + 80080ea: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80080ee: 69da ldr r2, [r3, #28] + 80080f0: 683b ldr r3, [r7, #0] + 80080f2: 781b ldrb r3, [r3, #0] + 80080f4: f003 030f and.w r3, r3, #15 + 80080f8: 2101 movs r1, #1 + 80080fa: fa01 f303 lsl.w r3, r1, r3 + 80080fe: b29b uxth r3, r3 + 8008100: 43db mvns r3, r3 + 8008102: 68f9 ldr r1, [r7, #12] + 8008104: f501 6100 add.w r1, r1, #2048 @ 0x800 + 8008108: 4013 ands r3, r2 + 800810a: 61cb str r3, [r1, #28] + 800810c: 68bb ldr r3, [r7, #8] + 800810e: 015a lsls r2, r3, #5 + 8008110: 68fb ldr r3, [r7, #12] + 8008112: 4413 add r3, r2 + 8008114: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008118: 681a ldr r2, [r3, #0] + 800811a: 68bb ldr r3, [r7, #8] + 800811c: 0159 lsls r1, r3, #5 + 800811e: 68fb ldr r3, [r7, #12] + 8008120: 440b add r3, r1 + 8008122: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008126: 4619 mov r1, r3 + 8008128: 4b35 ldr r3, [pc, #212] @ (8008200 ) + 800812a: 4013 ands r3, r2 + 800812c: 600b str r3, [r1, #0] + 800812e: e060 b.n 80081f2 + 8008130: 68bb ldr r3, [r7, #8] + 8008132: 015a lsls r2, r3, #5 + 8008134: 68fb ldr r3, [r7, #12] + 8008136: 4413 add r3, r2 + 8008138: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 800813c: 681b ldr r3, [r3, #0] + 800813e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 8008142: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 8008146: d11f bne.n 8008188 + 8008148: 68bb ldr r3, [r7, #8] + 800814a: 015a lsls r2, r3, #5 + 800814c: 68fb ldr r3, [r7, #12] + 800814e: 4413 add r3, r2 + 8008150: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008154: 681b ldr r3, [r3, #0] + 8008156: 68ba ldr r2, [r7, #8] + 8008158: 0151 lsls r1, r2, #5 + 800815a: 68fa ldr r2, [r7, #12] + 800815c: 440a add r2, r1 + 800815e: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008162: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 + 8008166: 6013 str r3, [r2, #0] + 8008168: 68bb ldr r3, [r7, #8] + 800816a: 015a lsls r2, r3, #5 + 800816c: 68fb ldr r3, [r7, #12] + 800816e: 4413 add r3, r2 + 8008170: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008174: 681b ldr r3, [r3, #0] + 8008176: 68ba ldr r2, [r7, #8] + 8008178: 0151 lsls r1, r2, #5 + 800817a: 68fa ldr r2, [r7, #12] + 800817c: 440a add r2, r1 + 800817e: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008182: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 + 8008186: 6013 str r3, [r2, #0] + 8008188: 68fb ldr r3, [r7, #12] + 800818a: f503 6300 add.w r3, r3, #2048 @ 0x800 + 800818e: 6bda ldr r2, [r3, #60] @ 0x3c + 8008190: 683b ldr r3, [r7, #0] + 8008192: 781b ldrb r3, [r3, #0] + 8008194: f003 030f and.w r3, r3, #15 + 8008198: 2101 movs r1, #1 + 800819a: fa01 f303 lsl.w r3, r1, r3 + 800819e: 041b lsls r3, r3, #16 + 80081a0: 43db mvns r3, r3 + 80081a2: 68f9 ldr r1, [r7, #12] + 80081a4: f501 6100 add.w r1, r1, #2048 @ 0x800 + 80081a8: 4013 ands r3, r2 + 80081aa: 63cb str r3, [r1, #60] @ 0x3c + 80081ac: 68fb ldr r3, [r7, #12] + 80081ae: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80081b2: 69da ldr r2, [r3, #28] + 80081b4: 683b ldr r3, [r7, #0] + 80081b6: 781b ldrb r3, [r3, #0] + 80081b8: f003 030f and.w r3, r3, #15 + 80081bc: 2101 movs r1, #1 + 80081be: fa01 f303 lsl.w r3, r1, r3 + 80081c2: 041b lsls r3, r3, #16 + 80081c4: 43db mvns r3, r3 + 80081c6: 68f9 ldr r1, [r7, #12] + 80081c8: f501 6100 add.w r1, r1, #2048 @ 0x800 + 80081cc: 4013 ands r3, r2 + 80081ce: 61cb str r3, [r1, #28] + 80081d0: 68bb ldr r3, [r7, #8] + 80081d2: 015a lsls r2, r3, #5 + 80081d4: 68fb ldr r3, [r7, #12] + 80081d6: 4413 add r3, r2 + 80081d8: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80081dc: 681a ldr r2, [r3, #0] + 80081de: 68bb ldr r3, [r7, #8] + 80081e0: 0159 lsls r1, r3, #5 + 80081e2: 68fb ldr r3, [r7, #12] + 80081e4: 440b add r3, r1 + 80081e6: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80081ea: 4619 mov r1, r3 + 80081ec: 4b05 ldr r3, [pc, #20] @ (8008204 ) + 80081ee: 4013 ands r3, r2 + 80081f0: 600b str r3, [r1, #0] + 80081f2: 2300 movs r3, #0 + 80081f4: 4618 mov r0, r3 + 80081f6: 3714 adds r7, #20 + 80081f8: 46bd mov sp, r7 + 80081fa: f85d 7b04 ldr.w r7, [sp], #4 + 80081fe: 4770 bx lr + 8008200: ec337800 .word 0xec337800 + 8008204: eff37800 .word 0xeff37800 + +08008208 : + 8008208: b580 push {r7, lr} + 800820a: b08a sub sp, #40 @ 0x28 + 800820c: af02 add r7, sp, #8 + 800820e: 60f8 str r0, [r7, #12] + 8008210: 60b9 str r1, [r7, #8] + 8008212: 4613 mov r3, r2 + 8008214: 71fb strb r3, [r7, #7] + 8008216: 68fb ldr r3, [r7, #12] + 8008218: 61fb str r3, [r7, #28] + 800821a: 68bb ldr r3, [r7, #8] + 800821c: 781b ldrb r3, [r3, #0] + 800821e: 61bb str r3, [r7, #24] + 8008220: 68bb ldr r3, [r7, #8] + 8008222: 785b ldrb r3, [r3, #1] + 8008224: 2b01 cmp r3, #1 + 8008226: f040 817f bne.w 8008528 + 800822a: 68bb ldr r3, [r7, #8] + 800822c: 691b ldr r3, [r3, #16] + 800822e: 2b00 cmp r3, #0 + 8008230: d132 bne.n 8008298 + 8008232: 69bb ldr r3, [r7, #24] + 8008234: 015a lsls r2, r3, #5 + 8008236: 69fb ldr r3, [r7, #28] + 8008238: 4413 add r3, r2 + 800823a: f503 6310 add.w r3, r3, #2304 @ 0x900 + 800823e: 691b ldr r3, [r3, #16] + 8008240: 69ba ldr r2, [r7, #24] + 8008242: 0151 lsls r1, r2, #5 + 8008244: 69fa ldr r2, [r7, #28] + 8008246: 440a add r2, r1 + 8008248: f502 6210 add.w r2, r2, #2304 @ 0x900 + 800824c: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 + 8008250: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 + 8008254: 6113 str r3, [r2, #16] + 8008256: 69bb ldr r3, [r7, #24] + 8008258: 015a lsls r2, r3, #5 + 800825a: 69fb ldr r3, [r7, #28] + 800825c: 4413 add r3, r2 + 800825e: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008262: 691b ldr r3, [r3, #16] + 8008264: 69ba ldr r2, [r7, #24] + 8008266: 0151 lsls r1, r2, #5 + 8008268: 69fa ldr r2, [r7, #28] + 800826a: 440a add r2, r1 + 800826c: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8008270: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8008274: 6113 str r3, [r2, #16] + 8008276: 69bb ldr r3, [r7, #24] + 8008278: 015a lsls r2, r3, #5 + 800827a: 69fb ldr r3, [r7, #28] + 800827c: 4413 add r3, r2 + 800827e: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008282: 691b ldr r3, [r3, #16] + 8008284: 69ba ldr r2, [r7, #24] + 8008286: 0151 lsls r1, r2, #5 + 8008288: 69fa ldr r2, [r7, #28] + 800828a: 440a add r2, r1 + 800828c: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8008290: 0cdb lsrs r3, r3, #19 + 8008292: 04db lsls r3, r3, #19 + 8008294: 6113 str r3, [r2, #16] + 8008296: e097 b.n 80083c8 + 8008298: 69bb ldr r3, [r7, #24] + 800829a: 015a lsls r2, r3, #5 + 800829c: 69fb ldr r3, [r7, #28] + 800829e: 4413 add r3, r2 + 80082a0: f503 6310 add.w r3, r3, #2304 @ 0x900 + 80082a4: 691b ldr r3, [r3, #16] + 80082a6: 69ba ldr r2, [r7, #24] + 80082a8: 0151 lsls r1, r2, #5 + 80082aa: 69fa ldr r2, [r7, #28] + 80082ac: 440a add r2, r1 + 80082ae: f502 6210 add.w r2, r2, #2304 @ 0x900 + 80082b2: 0cdb lsrs r3, r3, #19 + 80082b4: 04db lsls r3, r3, #19 + 80082b6: 6113 str r3, [r2, #16] + 80082b8: 69bb ldr r3, [r7, #24] + 80082ba: 015a lsls r2, r3, #5 + 80082bc: 69fb ldr r3, [r7, #28] + 80082be: 4413 add r3, r2 + 80082c0: f503 6310 add.w r3, r3, #2304 @ 0x900 + 80082c4: 691b ldr r3, [r3, #16] + 80082c6: 69ba ldr r2, [r7, #24] + 80082c8: 0151 lsls r1, r2, #5 + 80082ca: 69fa ldr r2, [r7, #28] + 80082cc: 440a add r2, r1 + 80082ce: f502 6210 add.w r2, r2, #2304 @ 0x900 + 80082d2: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 + 80082d6: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 + 80082da: 6113 str r3, [r2, #16] + 80082dc: 69bb ldr r3, [r7, #24] + 80082de: 2b00 cmp r3, #0 + 80082e0: d11a bne.n 8008318 + 80082e2: 68bb ldr r3, [r7, #8] + 80082e4: 691a ldr r2, [r3, #16] + 80082e6: 68bb ldr r3, [r7, #8] + 80082e8: 689b ldr r3, [r3, #8] + 80082ea: 429a cmp r2, r3 + 80082ec: d903 bls.n 80082f6 + 80082ee: 68bb ldr r3, [r7, #8] + 80082f0: 689a ldr r2, [r3, #8] + 80082f2: 68bb ldr r3, [r7, #8] + 80082f4: 611a str r2, [r3, #16] + 80082f6: 69bb ldr r3, [r7, #24] + 80082f8: 015a lsls r2, r3, #5 + 80082fa: 69fb ldr r3, [r7, #28] + 80082fc: 4413 add r3, r2 + 80082fe: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008302: 691b ldr r3, [r3, #16] + 8008304: 69ba ldr r2, [r7, #24] + 8008306: 0151 lsls r1, r2, #5 + 8008308: 69fa ldr r2, [r7, #28] + 800830a: 440a add r2, r1 + 800830c: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8008310: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8008314: 6113 str r3, [r2, #16] + 8008316: e044 b.n 80083a2 + 8008318: 68bb ldr r3, [r7, #8] + 800831a: 691a ldr r2, [r3, #16] + 800831c: 68bb ldr r3, [r7, #8] + 800831e: 689b ldr r3, [r3, #8] + 8008320: 4413 add r3, r2 + 8008322: 1e5a subs r2, r3, #1 + 8008324: 68bb ldr r3, [r7, #8] + 8008326: 689b ldr r3, [r3, #8] + 8008328: fbb2 f3f3 udiv r3, r2, r3 + 800832c: 82fb strh r3, [r7, #22] + 800832e: 69bb ldr r3, [r7, #24] + 8008330: 015a lsls r2, r3, #5 + 8008332: 69fb ldr r3, [r7, #28] + 8008334: 4413 add r3, r2 + 8008336: f503 6310 add.w r3, r3, #2304 @ 0x900 + 800833a: 691a ldr r2, [r3, #16] + 800833c: 8afb ldrh r3, [r7, #22] + 800833e: 04d9 lsls r1, r3, #19 + 8008340: 4ba4 ldr r3, [pc, #656] @ (80085d4 ) + 8008342: 400b ands r3, r1 + 8008344: 69b9 ldr r1, [r7, #24] + 8008346: 0148 lsls r0, r1, #5 + 8008348: 69f9 ldr r1, [r7, #28] + 800834a: 4401 add r1, r0 + 800834c: f501 6110 add.w r1, r1, #2304 @ 0x900 + 8008350: 4313 orrs r3, r2 + 8008352: 610b str r3, [r1, #16] + 8008354: 68bb ldr r3, [r7, #8] + 8008356: 791b ldrb r3, [r3, #4] + 8008358: 2b01 cmp r3, #1 + 800835a: d122 bne.n 80083a2 + 800835c: 69bb ldr r3, [r7, #24] + 800835e: 015a lsls r2, r3, #5 + 8008360: 69fb ldr r3, [r7, #28] + 8008362: 4413 add r3, r2 + 8008364: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008368: 691b ldr r3, [r3, #16] + 800836a: 69ba ldr r2, [r7, #24] + 800836c: 0151 lsls r1, r2, #5 + 800836e: 69fa ldr r2, [r7, #28] + 8008370: 440a add r2, r1 + 8008372: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8008376: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 + 800837a: 6113 str r3, [r2, #16] + 800837c: 69bb ldr r3, [r7, #24] + 800837e: 015a lsls r2, r3, #5 + 8008380: 69fb ldr r3, [r7, #28] + 8008382: 4413 add r3, r2 + 8008384: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008388: 691a ldr r2, [r3, #16] + 800838a: 8afb ldrh r3, [r7, #22] + 800838c: 075b lsls r3, r3, #29 + 800838e: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000 + 8008392: 69b9 ldr r1, [r7, #24] + 8008394: 0148 lsls r0, r1, #5 + 8008396: 69f9 ldr r1, [r7, #28] + 8008398: 4401 add r1, r0 + 800839a: f501 6110 add.w r1, r1, #2304 @ 0x900 + 800839e: 4313 orrs r3, r2 + 80083a0: 610b str r3, [r1, #16] + 80083a2: 69bb ldr r3, [r7, #24] + 80083a4: 015a lsls r2, r3, #5 + 80083a6: 69fb ldr r3, [r7, #28] + 80083a8: 4413 add r3, r2 + 80083aa: f503 6310 add.w r3, r3, #2304 @ 0x900 + 80083ae: 691a ldr r2, [r3, #16] + 80083b0: 68bb ldr r3, [r7, #8] + 80083b2: 691b ldr r3, [r3, #16] + 80083b4: f3c3 0312 ubfx r3, r3, #0, #19 + 80083b8: 69b9 ldr r1, [r7, #24] + 80083ba: 0148 lsls r0, r1, #5 + 80083bc: 69f9 ldr r1, [r7, #28] + 80083be: 4401 add r1, r0 + 80083c0: f501 6110 add.w r1, r1, #2304 @ 0x900 + 80083c4: 4313 orrs r3, r2 + 80083c6: 610b str r3, [r1, #16] + 80083c8: 79fb ldrb r3, [r7, #7] + 80083ca: 2b01 cmp r3, #1 + 80083cc: d14b bne.n 8008466 + 80083ce: 68bb ldr r3, [r7, #8] + 80083d0: 69db ldr r3, [r3, #28] + 80083d2: 2b00 cmp r3, #0 + 80083d4: d009 beq.n 80083ea + 80083d6: 69bb ldr r3, [r7, #24] + 80083d8: 015a lsls r2, r3, #5 + 80083da: 69fb ldr r3, [r7, #28] + 80083dc: 4413 add r3, r2 + 80083de: f503 6310 add.w r3, r3, #2304 @ 0x900 + 80083e2: 461a mov r2, r3 + 80083e4: 68bb ldr r3, [r7, #8] + 80083e6: 69db ldr r3, [r3, #28] + 80083e8: 6153 str r3, [r2, #20] + 80083ea: 68bb ldr r3, [r7, #8] + 80083ec: 791b ldrb r3, [r3, #4] + 80083ee: 2b01 cmp r3, #1 + 80083f0: d128 bne.n 8008444 + 80083f2: 69fb ldr r3, [r7, #28] + 80083f4: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80083f8: 689b ldr r3, [r3, #8] + 80083fa: f403 7380 and.w r3, r3, #256 @ 0x100 + 80083fe: 2b00 cmp r3, #0 + 8008400: d110 bne.n 8008424 + 8008402: 69bb ldr r3, [r7, #24] + 8008404: 015a lsls r2, r3, #5 + 8008406: 69fb ldr r3, [r7, #28] + 8008408: 4413 add r3, r2 + 800840a: f503 6310 add.w r3, r3, #2304 @ 0x900 + 800840e: 681b ldr r3, [r3, #0] + 8008410: 69ba ldr r2, [r7, #24] + 8008412: 0151 lsls r1, r2, #5 + 8008414: 69fa ldr r2, [r7, #28] + 8008416: 440a add r2, r1 + 8008418: f502 6210 add.w r2, r2, #2304 @ 0x900 + 800841c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 + 8008420: 6013 str r3, [r2, #0] + 8008422: e00f b.n 8008444 + 8008424: 69bb ldr r3, [r7, #24] + 8008426: 015a lsls r2, r3, #5 + 8008428: 69fb ldr r3, [r7, #28] + 800842a: 4413 add r3, r2 + 800842c: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008430: 681b ldr r3, [r3, #0] + 8008432: 69ba ldr r2, [r7, #24] + 8008434: 0151 lsls r1, r2, #5 + 8008436: 69fa ldr r2, [r7, #28] + 8008438: 440a add r2, r1 + 800843a: f502 6210 add.w r2, r2, #2304 @ 0x900 + 800843e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8008442: 6013 str r3, [r2, #0] + 8008444: 69bb ldr r3, [r7, #24] + 8008446: 015a lsls r2, r3, #5 + 8008448: 69fb ldr r3, [r7, #28] + 800844a: 4413 add r3, r2 + 800844c: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008450: 681b ldr r3, [r3, #0] + 8008452: 69ba ldr r2, [r7, #24] + 8008454: 0151 lsls r1, r2, #5 + 8008456: 69fa ldr r2, [r7, #28] + 8008458: 440a add r2, r1 + 800845a: f502 6210 add.w r2, r2, #2304 @ 0x900 + 800845e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 + 8008462: 6013 str r3, [r2, #0] + 8008464: e166 b.n 8008734 + 8008466: 69bb ldr r3, [r7, #24] + 8008468: 015a lsls r2, r3, #5 + 800846a: 69fb ldr r3, [r7, #28] + 800846c: 4413 add r3, r2 + 800846e: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008472: 681b ldr r3, [r3, #0] + 8008474: 69ba ldr r2, [r7, #24] + 8008476: 0151 lsls r1, r2, #5 + 8008478: 69fa ldr r2, [r7, #28] + 800847a: 440a add r2, r1 + 800847c: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8008480: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 + 8008484: 6013 str r3, [r2, #0] + 8008486: 68bb ldr r3, [r7, #8] + 8008488: 791b ldrb r3, [r3, #4] + 800848a: 2b01 cmp r3, #1 + 800848c: d015 beq.n 80084ba + 800848e: 68bb ldr r3, [r7, #8] + 8008490: 691b ldr r3, [r3, #16] + 8008492: 2b00 cmp r3, #0 + 8008494: f000 814e beq.w 8008734 + 8008498: 69fb ldr r3, [r7, #28] + 800849a: f503 6300 add.w r3, r3, #2048 @ 0x800 + 800849e: 6b5a ldr r2, [r3, #52] @ 0x34 + 80084a0: 68bb ldr r3, [r7, #8] + 80084a2: 781b ldrb r3, [r3, #0] + 80084a4: f003 030f and.w r3, r3, #15 + 80084a8: 2101 movs r1, #1 + 80084aa: fa01 f303 lsl.w r3, r1, r3 + 80084ae: 69f9 ldr r1, [r7, #28] + 80084b0: f501 6100 add.w r1, r1, #2048 @ 0x800 + 80084b4: 4313 orrs r3, r2 + 80084b6: 634b str r3, [r1, #52] @ 0x34 + 80084b8: e13c b.n 8008734 + 80084ba: 69fb ldr r3, [r7, #28] + 80084bc: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80084c0: 689b ldr r3, [r3, #8] + 80084c2: f403 7380 and.w r3, r3, #256 @ 0x100 + 80084c6: 2b00 cmp r3, #0 + 80084c8: d110 bne.n 80084ec + 80084ca: 69bb ldr r3, [r7, #24] + 80084cc: 015a lsls r2, r3, #5 + 80084ce: 69fb ldr r3, [r7, #28] + 80084d0: 4413 add r3, r2 + 80084d2: f503 6310 add.w r3, r3, #2304 @ 0x900 + 80084d6: 681b ldr r3, [r3, #0] + 80084d8: 69ba ldr r2, [r7, #24] + 80084da: 0151 lsls r1, r2, #5 + 80084dc: 69fa ldr r2, [r7, #28] + 80084de: 440a add r2, r1 + 80084e0: f502 6210 add.w r2, r2, #2304 @ 0x900 + 80084e4: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 + 80084e8: 6013 str r3, [r2, #0] + 80084ea: e00f b.n 800850c + 80084ec: 69bb ldr r3, [r7, #24] + 80084ee: 015a lsls r2, r3, #5 + 80084f0: 69fb ldr r3, [r7, #28] + 80084f2: 4413 add r3, r2 + 80084f4: f503 6310 add.w r3, r3, #2304 @ 0x900 + 80084f8: 681b ldr r3, [r3, #0] + 80084fa: 69ba ldr r2, [r7, #24] + 80084fc: 0151 lsls r1, r2, #5 + 80084fe: 69fa ldr r2, [r7, #28] + 8008500: 440a add r2, r1 + 8008502: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8008506: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800850a: 6013 str r3, [r2, #0] + 800850c: 68bb ldr r3, [r7, #8] + 800850e: 68d9 ldr r1, [r3, #12] + 8008510: 68bb ldr r3, [r7, #8] + 8008512: 781a ldrb r2, [r3, #0] + 8008514: 68bb ldr r3, [r7, #8] + 8008516: 691b ldr r3, [r3, #16] + 8008518: b298 uxth r0, r3 + 800851a: 79fb ldrb r3, [r7, #7] + 800851c: 9300 str r3, [sp, #0] + 800851e: 4603 mov r3, r0 + 8008520: 68f8 ldr r0, [r7, #12] + 8008522: f000 f9b9 bl 8008898 + 8008526: e105 b.n 8008734 + 8008528: 69bb ldr r3, [r7, #24] + 800852a: 015a lsls r2, r3, #5 + 800852c: 69fb ldr r3, [r7, #28] + 800852e: 4413 add r3, r2 + 8008530: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008534: 691b ldr r3, [r3, #16] + 8008536: 69ba ldr r2, [r7, #24] + 8008538: 0151 lsls r1, r2, #5 + 800853a: 69fa ldr r2, [r7, #28] + 800853c: 440a add r2, r1 + 800853e: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008542: 0cdb lsrs r3, r3, #19 + 8008544: 04db lsls r3, r3, #19 + 8008546: 6113 str r3, [r2, #16] + 8008548: 69bb ldr r3, [r7, #24] + 800854a: 015a lsls r2, r3, #5 + 800854c: 69fb ldr r3, [r7, #28] + 800854e: 4413 add r3, r2 + 8008550: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008554: 691b ldr r3, [r3, #16] + 8008556: 69ba ldr r2, [r7, #24] + 8008558: 0151 lsls r1, r2, #5 + 800855a: 69fa ldr r2, [r7, #28] + 800855c: 440a add r2, r1 + 800855e: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008562: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 + 8008566: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 + 800856a: 6113 str r3, [r2, #16] + 800856c: 69bb ldr r3, [r7, #24] + 800856e: 2b00 cmp r3, #0 + 8008570: d132 bne.n 80085d8 + 8008572: 68bb ldr r3, [r7, #8] + 8008574: 691b ldr r3, [r3, #16] + 8008576: 2b00 cmp r3, #0 + 8008578: d003 beq.n 8008582 + 800857a: 68bb ldr r3, [r7, #8] + 800857c: 689a ldr r2, [r3, #8] + 800857e: 68bb ldr r3, [r7, #8] + 8008580: 611a str r2, [r3, #16] + 8008582: 68bb ldr r3, [r7, #8] + 8008584: 689a ldr r2, [r3, #8] + 8008586: 68bb ldr r3, [r7, #8] + 8008588: 621a str r2, [r3, #32] + 800858a: 69bb ldr r3, [r7, #24] + 800858c: 015a lsls r2, r3, #5 + 800858e: 69fb ldr r3, [r7, #28] + 8008590: 4413 add r3, r2 + 8008592: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008596: 691a ldr r2, [r3, #16] + 8008598: 68bb ldr r3, [r7, #8] + 800859a: 6a1b ldr r3, [r3, #32] + 800859c: f3c3 0312 ubfx r3, r3, #0, #19 + 80085a0: 69b9 ldr r1, [r7, #24] + 80085a2: 0148 lsls r0, r1, #5 + 80085a4: 69f9 ldr r1, [r7, #28] + 80085a6: 4401 add r1, r0 + 80085a8: f501 6130 add.w r1, r1, #2816 @ 0xb00 + 80085ac: 4313 orrs r3, r2 + 80085ae: 610b str r3, [r1, #16] + 80085b0: 69bb ldr r3, [r7, #24] + 80085b2: 015a lsls r2, r3, #5 + 80085b4: 69fb ldr r3, [r7, #28] + 80085b6: 4413 add r3, r2 + 80085b8: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80085bc: 691b ldr r3, [r3, #16] + 80085be: 69ba ldr r2, [r7, #24] + 80085c0: 0151 lsls r1, r2, #5 + 80085c2: 69fa ldr r2, [r7, #28] + 80085c4: 440a add r2, r1 + 80085c6: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 80085ca: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 80085ce: 6113 str r3, [r2, #16] + 80085d0: e062 b.n 8008698 + 80085d2: bf00 nop + 80085d4: 1ff80000 .word 0x1ff80000 + 80085d8: 68bb ldr r3, [r7, #8] + 80085da: 691b ldr r3, [r3, #16] + 80085dc: 2b00 cmp r3, #0 + 80085de: d123 bne.n 8008628 + 80085e0: 69bb ldr r3, [r7, #24] + 80085e2: 015a lsls r2, r3, #5 + 80085e4: 69fb ldr r3, [r7, #28] + 80085e6: 4413 add r3, r2 + 80085e8: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80085ec: 691a ldr r2, [r3, #16] + 80085ee: 68bb ldr r3, [r7, #8] + 80085f0: 689b ldr r3, [r3, #8] + 80085f2: f3c3 0312 ubfx r3, r3, #0, #19 + 80085f6: 69b9 ldr r1, [r7, #24] + 80085f8: 0148 lsls r0, r1, #5 + 80085fa: 69f9 ldr r1, [r7, #28] + 80085fc: 4401 add r1, r0 + 80085fe: f501 6130 add.w r1, r1, #2816 @ 0xb00 + 8008602: 4313 orrs r3, r2 + 8008604: 610b str r3, [r1, #16] + 8008606: 69bb ldr r3, [r7, #24] + 8008608: 015a lsls r2, r3, #5 + 800860a: 69fb ldr r3, [r7, #28] + 800860c: 4413 add r3, r2 + 800860e: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008612: 691b ldr r3, [r3, #16] + 8008614: 69ba ldr r2, [r7, #24] + 8008616: 0151 lsls r1, r2, #5 + 8008618: 69fa ldr r2, [r7, #28] + 800861a: 440a add r2, r1 + 800861c: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008620: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8008624: 6113 str r3, [r2, #16] + 8008626: e037 b.n 8008698 + 8008628: 68bb ldr r3, [r7, #8] + 800862a: 691a ldr r2, [r3, #16] + 800862c: 68bb ldr r3, [r7, #8] + 800862e: 689b ldr r3, [r3, #8] + 8008630: 4413 add r3, r2 + 8008632: 1e5a subs r2, r3, #1 + 8008634: 68bb ldr r3, [r7, #8] + 8008636: 689b ldr r3, [r3, #8] + 8008638: fbb2 f3f3 udiv r3, r2, r3 + 800863c: 82fb strh r3, [r7, #22] + 800863e: 68bb ldr r3, [r7, #8] + 8008640: 689b ldr r3, [r3, #8] + 8008642: 8afa ldrh r2, [r7, #22] + 8008644: fb03 f202 mul.w r2, r3, r2 + 8008648: 68bb ldr r3, [r7, #8] + 800864a: 621a str r2, [r3, #32] + 800864c: 69bb ldr r3, [r7, #24] + 800864e: 015a lsls r2, r3, #5 + 8008650: 69fb ldr r3, [r7, #28] + 8008652: 4413 add r3, r2 + 8008654: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008658: 691a ldr r2, [r3, #16] + 800865a: 8afb ldrh r3, [r7, #22] + 800865c: 04d9 lsls r1, r3, #19 + 800865e: 4b38 ldr r3, [pc, #224] @ (8008740 ) + 8008660: 400b ands r3, r1 + 8008662: 69b9 ldr r1, [r7, #24] + 8008664: 0148 lsls r0, r1, #5 + 8008666: 69f9 ldr r1, [r7, #28] + 8008668: 4401 add r1, r0 + 800866a: f501 6130 add.w r1, r1, #2816 @ 0xb00 + 800866e: 4313 orrs r3, r2 + 8008670: 610b str r3, [r1, #16] + 8008672: 69bb ldr r3, [r7, #24] + 8008674: 015a lsls r2, r3, #5 + 8008676: 69fb ldr r3, [r7, #28] + 8008678: 4413 add r3, r2 + 800867a: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 800867e: 691a ldr r2, [r3, #16] + 8008680: 68bb ldr r3, [r7, #8] + 8008682: 6a1b ldr r3, [r3, #32] + 8008684: f3c3 0312 ubfx r3, r3, #0, #19 + 8008688: 69b9 ldr r1, [r7, #24] + 800868a: 0148 lsls r0, r1, #5 + 800868c: 69f9 ldr r1, [r7, #28] + 800868e: 4401 add r1, r0 + 8008690: f501 6130 add.w r1, r1, #2816 @ 0xb00 + 8008694: 4313 orrs r3, r2 + 8008696: 610b str r3, [r1, #16] + 8008698: 79fb ldrb r3, [r7, #7] + 800869a: 2b01 cmp r3, #1 + 800869c: d10d bne.n 80086ba + 800869e: 68bb ldr r3, [r7, #8] + 80086a0: 68db ldr r3, [r3, #12] + 80086a2: 2b00 cmp r3, #0 + 80086a4: d009 beq.n 80086ba + 80086a6: 68bb ldr r3, [r7, #8] + 80086a8: 68d9 ldr r1, [r3, #12] + 80086aa: 69bb ldr r3, [r7, #24] + 80086ac: 015a lsls r2, r3, #5 + 80086ae: 69fb ldr r3, [r7, #28] + 80086b0: 4413 add r3, r2 + 80086b2: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80086b6: 460a mov r2, r1 + 80086b8: 615a str r2, [r3, #20] + 80086ba: 68bb ldr r3, [r7, #8] + 80086bc: 791b ldrb r3, [r3, #4] + 80086be: 2b01 cmp r3, #1 + 80086c0: d128 bne.n 8008714 + 80086c2: 69fb ldr r3, [r7, #28] + 80086c4: f503 6300 add.w r3, r3, #2048 @ 0x800 + 80086c8: 689b ldr r3, [r3, #8] + 80086ca: f403 7380 and.w r3, r3, #256 @ 0x100 + 80086ce: 2b00 cmp r3, #0 + 80086d0: d110 bne.n 80086f4 + 80086d2: 69bb ldr r3, [r7, #24] + 80086d4: 015a lsls r2, r3, #5 + 80086d6: 69fb ldr r3, [r7, #28] + 80086d8: 4413 add r3, r2 + 80086da: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 80086de: 681b ldr r3, [r3, #0] + 80086e0: 69ba ldr r2, [r7, #24] + 80086e2: 0151 lsls r1, r2, #5 + 80086e4: 69fa ldr r2, [r7, #28] + 80086e6: 440a add r2, r1 + 80086e8: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 80086ec: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 + 80086f0: 6013 str r3, [r2, #0] + 80086f2: e00f b.n 8008714 + 80086f4: 69bb ldr r3, [r7, #24] + 80086f6: 015a lsls r2, r3, #5 + 80086f8: 69fb ldr r3, [r7, #28] + 80086fa: 4413 add r3, r2 + 80086fc: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008700: 681b ldr r3, [r3, #0] + 8008702: 69ba ldr r2, [r7, #24] + 8008704: 0151 lsls r1, r2, #5 + 8008706: 69fa ldr r2, [r7, #28] + 8008708: 440a add r2, r1 + 800870a: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 800870e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8008712: 6013 str r3, [r2, #0] + 8008714: 69bb ldr r3, [r7, #24] + 8008716: 015a lsls r2, r3, #5 + 8008718: 69fb ldr r3, [r7, #28] + 800871a: 4413 add r3, r2 + 800871c: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008720: 681b ldr r3, [r3, #0] + 8008722: 69ba ldr r2, [r7, #24] + 8008724: 0151 lsls r1, r2, #5 + 8008726: 69fa ldr r2, [r7, #28] + 8008728: 440a add r2, r1 + 800872a: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 800872e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 + 8008732: 6013 str r3, [r2, #0] + 8008734: 2300 movs r3, #0 + 8008736: 4618 mov r0, r3 + 8008738: 3720 adds r7, #32 + 800873a: 46bd mov sp, r7 + 800873c: bd80 pop {r7, pc} + 800873e: bf00 nop + 8008740: 1ff80000 .word 0x1ff80000 + +08008744 : + 8008744: b480 push {r7} + 8008746: b087 sub sp, #28 + 8008748: af00 add r7, sp, #0 + 800874a: 6078 str r0, [r7, #4] + 800874c: 6039 str r1, [r7, #0] + 800874e: 2300 movs r3, #0 + 8008750: 60fb str r3, [r7, #12] + 8008752: 2300 movs r3, #0 + 8008754: 75fb strb r3, [r7, #23] + 8008756: 687b ldr r3, [r7, #4] + 8008758: 613b str r3, [r7, #16] + 800875a: 683b ldr r3, [r7, #0] + 800875c: 785b ldrb r3, [r3, #1] + 800875e: 2b01 cmp r3, #1 + 8008760: d14a bne.n 80087f8 + 8008762: 683b ldr r3, [r7, #0] + 8008764: 781b ldrb r3, [r3, #0] + 8008766: 015a lsls r2, r3, #5 + 8008768: 693b ldr r3, [r7, #16] + 800876a: 4413 add r3, r2 + 800876c: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008770: 681b ldr r3, [r3, #0] + 8008772: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 8008776: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 800877a: f040 8086 bne.w 800888a + 800877e: 683b ldr r3, [r7, #0] + 8008780: 781b ldrb r3, [r3, #0] + 8008782: 015a lsls r2, r3, #5 + 8008784: 693b ldr r3, [r7, #16] + 8008786: 4413 add r3, r2 + 8008788: f503 6310 add.w r3, r3, #2304 @ 0x900 + 800878c: 681b ldr r3, [r3, #0] + 800878e: 683a ldr r2, [r7, #0] + 8008790: 7812 ldrb r2, [r2, #0] + 8008792: 0151 lsls r1, r2, #5 + 8008794: 693a ldr r2, [r7, #16] + 8008796: 440a add r2, r1 + 8008798: f502 6210 add.w r2, r2, #2304 @ 0x900 + 800879c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 + 80087a0: 6013 str r3, [r2, #0] + 80087a2: 683b ldr r3, [r7, #0] + 80087a4: 781b ldrb r3, [r3, #0] + 80087a6: 015a lsls r2, r3, #5 + 80087a8: 693b ldr r3, [r7, #16] + 80087aa: 4413 add r3, r2 + 80087ac: f503 6310 add.w r3, r3, #2304 @ 0x900 + 80087b0: 681b ldr r3, [r3, #0] + 80087b2: 683a ldr r2, [r7, #0] + 80087b4: 7812 ldrb r2, [r2, #0] + 80087b6: 0151 lsls r1, r2, #5 + 80087b8: 693a ldr r2, [r7, #16] + 80087ba: 440a add r2, r1 + 80087bc: f502 6210 add.w r2, r2, #2304 @ 0x900 + 80087c0: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 + 80087c4: 6013 str r3, [r2, #0] + 80087c6: 68fb ldr r3, [r7, #12] + 80087c8: 3301 adds r3, #1 + 80087ca: 60fb str r3, [r7, #12] + 80087cc: 68fb ldr r3, [r7, #12] + 80087ce: f242 7210 movw r2, #10000 @ 0x2710 + 80087d2: 4293 cmp r3, r2 + 80087d4: d902 bls.n 80087dc + 80087d6: 2301 movs r3, #1 + 80087d8: 75fb strb r3, [r7, #23] + 80087da: e056 b.n 800888a + 80087dc: 683b ldr r3, [r7, #0] + 80087de: 781b ldrb r3, [r3, #0] + 80087e0: 015a lsls r2, r3, #5 + 80087e2: 693b ldr r3, [r7, #16] + 80087e4: 4413 add r3, r2 + 80087e6: f503 6310 add.w r3, r3, #2304 @ 0x900 + 80087ea: 681b ldr r3, [r3, #0] + 80087ec: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 80087f0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 80087f4: d0e7 beq.n 80087c6 + 80087f6: e048 b.n 800888a + 80087f8: 683b ldr r3, [r7, #0] + 80087fa: 781b ldrb r3, [r3, #0] + 80087fc: 015a lsls r2, r3, #5 + 80087fe: 693b ldr r3, [r7, #16] + 8008800: 4413 add r3, r2 + 8008802: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008806: 681b ldr r3, [r3, #0] + 8008808: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 800880c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 8008810: d13b bne.n 800888a + 8008812: 683b ldr r3, [r7, #0] + 8008814: 781b ldrb r3, [r3, #0] + 8008816: 015a lsls r2, r3, #5 + 8008818: 693b ldr r3, [r7, #16] + 800881a: 4413 add r3, r2 + 800881c: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008820: 681b ldr r3, [r3, #0] + 8008822: 683a ldr r2, [r7, #0] + 8008824: 7812 ldrb r2, [r2, #0] + 8008826: 0151 lsls r1, r2, #5 + 8008828: 693a ldr r2, [r7, #16] + 800882a: 440a add r2, r1 + 800882c: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008830: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 + 8008834: 6013 str r3, [r2, #0] + 8008836: 683b ldr r3, [r7, #0] + 8008838: 781b ldrb r3, [r3, #0] + 800883a: 015a lsls r2, r3, #5 + 800883c: 693b ldr r3, [r7, #16] + 800883e: 4413 add r3, r2 + 8008840: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008844: 681b ldr r3, [r3, #0] + 8008846: 683a ldr r2, [r7, #0] + 8008848: 7812 ldrb r2, [r2, #0] + 800884a: 0151 lsls r1, r2, #5 + 800884c: 693a ldr r2, [r7, #16] + 800884e: 440a add r2, r1 + 8008850: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008854: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 + 8008858: 6013 str r3, [r2, #0] + 800885a: 68fb ldr r3, [r7, #12] + 800885c: 3301 adds r3, #1 + 800885e: 60fb str r3, [r7, #12] + 8008860: 68fb ldr r3, [r7, #12] + 8008862: f242 7210 movw r2, #10000 @ 0x2710 + 8008866: 4293 cmp r3, r2 + 8008868: d902 bls.n 8008870 + 800886a: 2301 movs r3, #1 + 800886c: 75fb strb r3, [r7, #23] + 800886e: e00c b.n 800888a + 8008870: 683b ldr r3, [r7, #0] + 8008872: 781b ldrb r3, [r3, #0] + 8008874: 015a lsls r2, r3, #5 + 8008876: 693b ldr r3, [r7, #16] + 8008878: 4413 add r3, r2 + 800887a: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 800887e: 681b ldr r3, [r3, #0] + 8008880: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 8008884: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 8008888: d0e7 beq.n 800885a + 800888a: 7dfb ldrb r3, [r7, #23] + 800888c: 4618 mov r0, r3 + 800888e: 371c adds r7, #28 + 8008890: 46bd mov sp, r7 + 8008892: f85d 7b04 ldr.w r7, [sp], #4 + 8008896: 4770 bx lr + +08008898 : + 8008898: b480 push {r7} + 800889a: b089 sub sp, #36 @ 0x24 + 800889c: af00 add r7, sp, #0 + 800889e: 60f8 str r0, [r7, #12] + 80088a0: 60b9 str r1, [r7, #8] + 80088a2: 4611 mov r1, r2 + 80088a4: 461a mov r2, r3 + 80088a6: 460b mov r3, r1 + 80088a8: 71fb strb r3, [r7, #7] + 80088aa: 4613 mov r3, r2 + 80088ac: 80bb strh r3, [r7, #4] + 80088ae: 68fb ldr r3, [r7, #12] + 80088b0: 617b str r3, [r7, #20] + 80088b2: 68bb ldr r3, [r7, #8] + 80088b4: 61fb str r3, [r7, #28] + 80088b6: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 + 80088ba: 2b00 cmp r3, #0 + 80088bc: d123 bne.n 8008906 + 80088be: 88bb ldrh r3, [r7, #4] + 80088c0: 3303 adds r3, #3 + 80088c2: 089b lsrs r3, r3, #2 + 80088c4: 613b str r3, [r7, #16] + 80088c6: 2300 movs r3, #0 + 80088c8: 61bb str r3, [r7, #24] + 80088ca: e018 b.n 80088fe + 80088cc: 79fb ldrb r3, [r7, #7] + 80088ce: 031a lsls r2, r3, #12 + 80088d0: 697b ldr r3, [r7, #20] + 80088d2: 4413 add r3, r2 + 80088d4: f503 5380 add.w r3, r3, #4096 @ 0x1000 + 80088d8: 461a mov r2, r3 + 80088da: 69fb ldr r3, [r7, #28] + 80088dc: 681b ldr r3, [r3, #0] + 80088de: 6013 str r3, [r2, #0] + 80088e0: 69fb ldr r3, [r7, #28] + 80088e2: 3301 adds r3, #1 + 80088e4: 61fb str r3, [r7, #28] + 80088e6: 69fb ldr r3, [r7, #28] + 80088e8: 3301 adds r3, #1 + 80088ea: 61fb str r3, [r7, #28] + 80088ec: 69fb ldr r3, [r7, #28] + 80088ee: 3301 adds r3, #1 + 80088f0: 61fb str r3, [r7, #28] + 80088f2: 69fb ldr r3, [r7, #28] + 80088f4: 3301 adds r3, #1 + 80088f6: 61fb str r3, [r7, #28] + 80088f8: 69bb ldr r3, [r7, #24] + 80088fa: 3301 adds r3, #1 + 80088fc: 61bb str r3, [r7, #24] + 80088fe: 69ba ldr r2, [r7, #24] + 8008900: 693b ldr r3, [r7, #16] + 8008902: 429a cmp r2, r3 + 8008904: d3e2 bcc.n 80088cc + 8008906: 2300 movs r3, #0 + 8008908: 4618 mov r0, r3 + 800890a: 3724 adds r7, #36 @ 0x24 + 800890c: 46bd mov sp, r7 + 800890e: f85d 7b04 ldr.w r7, [sp], #4 + 8008912: 4770 bx lr + +08008914 : + 8008914: b480 push {r7} + 8008916: b08b sub sp, #44 @ 0x2c + 8008918: af00 add r7, sp, #0 + 800891a: 60f8 str r0, [r7, #12] + 800891c: 60b9 str r1, [r7, #8] + 800891e: 4613 mov r3, r2 + 8008920: 80fb strh r3, [r7, #6] + 8008922: 68fb ldr r3, [r7, #12] + 8008924: 61bb str r3, [r7, #24] + 8008926: 68bb ldr r3, [r7, #8] + 8008928: 627b str r3, [r7, #36] @ 0x24 + 800892a: 88fb ldrh r3, [r7, #6] + 800892c: 089b lsrs r3, r3, #2 + 800892e: b29b uxth r3, r3 + 8008930: 617b str r3, [r7, #20] + 8008932: 88fb ldrh r3, [r7, #6] + 8008934: f003 0303 and.w r3, r3, #3 + 8008938: 83fb strh r3, [r7, #30] + 800893a: 2300 movs r3, #0 + 800893c: 623b str r3, [r7, #32] + 800893e: e014 b.n 800896a + 8008940: 69bb ldr r3, [r7, #24] + 8008942: f503 5380 add.w r3, r3, #4096 @ 0x1000 + 8008946: 681a ldr r2, [r3, #0] + 8008948: 6a7b ldr r3, [r7, #36] @ 0x24 + 800894a: 601a str r2, [r3, #0] + 800894c: 6a7b ldr r3, [r7, #36] @ 0x24 + 800894e: 3301 adds r3, #1 + 8008950: 627b str r3, [r7, #36] @ 0x24 + 8008952: 6a7b ldr r3, [r7, #36] @ 0x24 + 8008954: 3301 adds r3, #1 + 8008956: 627b str r3, [r7, #36] @ 0x24 + 8008958: 6a7b ldr r3, [r7, #36] @ 0x24 + 800895a: 3301 adds r3, #1 + 800895c: 627b str r3, [r7, #36] @ 0x24 + 800895e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8008960: 3301 adds r3, #1 + 8008962: 627b str r3, [r7, #36] @ 0x24 + 8008964: 6a3b ldr r3, [r7, #32] + 8008966: 3301 adds r3, #1 + 8008968: 623b str r3, [r7, #32] + 800896a: 6a3a ldr r2, [r7, #32] + 800896c: 697b ldr r3, [r7, #20] + 800896e: 429a cmp r2, r3 + 8008970: d3e6 bcc.n 8008940 + 8008972: 8bfb ldrh r3, [r7, #30] + 8008974: 2b00 cmp r3, #0 + 8008976: d01e beq.n 80089b6 + 8008978: 2300 movs r3, #0 + 800897a: 623b str r3, [r7, #32] + 800897c: 69bb ldr r3, [r7, #24] + 800897e: f503 5380 add.w r3, r3, #4096 @ 0x1000 + 8008982: 461a mov r2, r3 + 8008984: f107 0310 add.w r3, r7, #16 + 8008988: 6812 ldr r2, [r2, #0] + 800898a: 601a str r2, [r3, #0] + 800898c: 693a ldr r2, [r7, #16] + 800898e: 6a3b ldr r3, [r7, #32] + 8008990: b2db uxtb r3, r3 + 8008992: 00db lsls r3, r3, #3 + 8008994: fa22 f303 lsr.w r3, r2, r3 + 8008998: b2da uxtb r2, r3 + 800899a: 6a7b ldr r3, [r7, #36] @ 0x24 + 800899c: 701a strb r2, [r3, #0] + 800899e: 6a3b ldr r3, [r7, #32] + 80089a0: 3301 adds r3, #1 + 80089a2: 623b str r3, [r7, #32] + 80089a4: 6a7b ldr r3, [r7, #36] @ 0x24 + 80089a6: 3301 adds r3, #1 + 80089a8: 627b str r3, [r7, #36] @ 0x24 + 80089aa: 8bfb ldrh r3, [r7, #30] + 80089ac: 3b01 subs r3, #1 + 80089ae: 83fb strh r3, [r7, #30] + 80089b0: 8bfb ldrh r3, [r7, #30] + 80089b2: 2b00 cmp r3, #0 + 80089b4: d1ea bne.n 800898c + 80089b6: 6a7b ldr r3, [r7, #36] @ 0x24 + 80089b8: 4618 mov r0, r3 + 80089ba: 372c adds r7, #44 @ 0x2c + 80089bc: 46bd mov sp, r7 + 80089be: f85d 7b04 ldr.w r7, [sp], #4 + 80089c2: 4770 bx lr + +080089c4 : + 80089c4: b480 push {r7} + 80089c6: b085 sub sp, #20 + 80089c8: af00 add r7, sp, #0 + 80089ca: 6078 str r0, [r7, #4] + 80089cc: 6039 str r1, [r7, #0] + 80089ce: 687b ldr r3, [r7, #4] + 80089d0: 60fb str r3, [r7, #12] + 80089d2: 683b ldr r3, [r7, #0] + 80089d4: 781b ldrb r3, [r3, #0] + 80089d6: 60bb str r3, [r7, #8] + 80089d8: 683b ldr r3, [r7, #0] + 80089da: 785b ldrb r3, [r3, #1] + 80089dc: 2b01 cmp r3, #1 + 80089de: d12c bne.n 8008a3a + 80089e0: 68bb ldr r3, [r7, #8] + 80089e2: 015a lsls r2, r3, #5 + 80089e4: 68fb ldr r3, [r7, #12] + 80089e6: 4413 add r3, r2 + 80089e8: f503 6310 add.w r3, r3, #2304 @ 0x900 + 80089ec: 681b ldr r3, [r3, #0] + 80089ee: 2b00 cmp r3, #0 + 80089f0: db12 blt.n 8008a18 + 80089f2: 68bb ldr r3, [r7, #8] + 80089f4: 2b00 cmp r3, #0 + 80089f6: d00f beq.n 8008a18 + 80089f8: 68bb ldr r3, [r7, #8] + 80089fa: 015a lsls r2, r3, #5 + 80089fc: 68fb ldr r3, [r7, #12] + 80089fe: 4413 add r3, r2 + 8008a00: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008a04: 681b ldr r3, [r3, #0] + 8008a06: 68ba ldr r2, [r7, #8] + 8008a08: 0151 lsls r1, r2, #5 + 8008a0a: 68fa ldr r2, [r7, #12] + 8008a0c: 440a add r2, r1 + 8008a0e: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8008a12: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 + 8008a16: 6013 str r3, [r2, #0] + 8008a18: 68bb ldr r3, [r7, #8] + 8008a1a: 015a lsls r2, r3, #5 + 8008a1c: 68fb ldr r3, [r7, #12] + 8008a1e: 4413 add r3, r2 + 8008a20: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008a24: 681b ldr r3, [r3, #0] + 8008a26: 68ba ldr r2, [r7, #8] + 8008a28: 0151 lsls r1, r2, #5 + 8008a2a: 68fa ldr r2, [r7, #12] + 8008a2c: 440a add r2, r1 + 8008a2e: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8008a32: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 + 8008a36: 6013 str r3, [r2, #0] + 8008a38: e02b b.n 8008a92 + 8008a3a: 68bb ldr r3, [r7, #8] + 8008a3c: 015a lsls r2, r3, #5 + 8008a3e: 68fb ldr r3, [r7, #12] + 8008a40: 4413 add r3, r2 + 8008a42: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008a46: 681b ldr r3, [r3, #0] + 8008a48: 2b00 cmp r3, #0 + 8008a4a: db12 blt.n 8008a72 + 8008a4c: 68bb ldr r3, [r7, #8] + 8008a4e: 2b00 cmp r3, #0 + 8008a50: d00f beq.n 8008a72 + 8008a52: 68bb ldr r3, [r7, #8] + 8008a54: 015a lsls r2, r3, #5 + 8008a56: 68fb ldr r3, [r7, #12] + 8008a58: 4413 add r3, r2 + 8008a5a: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008a5e: 681b ldr r3, [r3, #0] + 8008a60: 68ba ldr r2, [r7, #8] + 8008a62: 0151 lsls r1, r2, #5 + 8008a64: 68fa ldr r2, [r7, #12] + 8008a66: 440a add r2, r1 + 8008a68: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008a6c: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 + 8008a70: 6013 str r3, [r2, #0] + 8008a72: 68bb ldr r3, [r7, #8] + 8008a74: 015a lsls r2, r3, #5 + 8008a76: 68fb ldr r3, [r7, #12] + 8008a78: 4413 add r3, r2 + 8008a7a: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008a7e: 681b ldr r3, [r3, #0] + 8008a80: 68ba ldr r2, [r7, #8] + 8008a82: 0151 lsls r1, r2, #5 + 8008a84: 68fa ldr r2, [r7, #12] + 8008a86: 440a add r2, r1 + 8008a88: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008a8c: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 + 8008a90: 6013 str r3, [r2, #0] + 8008a92: 2300 movs r3, #0 + 8008a94: 4618 mov r0, r3 + 8008a96: 3714 adds r7, #20 + 8008a98: 46bd mov sp, r7 + 8008a9a: f85d 7b04 ldr.w r7, [sp], #4 + 8008a9e: 4770 bx lr + +08008aa0 : + 8008aa0: b480 push {r7} + 8008aa2: b085 sub sp, #20 + 8008aa4: af00 add r7, sp, #0 + 8008aa6: 6078 str r0, [r7, #4] + 8008aa8: 6039 str r1, [r7, #0] + 8008aaa: 687b ldr r3, [r7, #4] + 8008aac: 60fb str r3, [r7, #12] + 8008aae: 683b ldr r3, [r7, #0] + 8008ab0: 781b ldrb r3, [r3, #0] + 8008ab2: 60bb str r3, [r7, #8] + 8008ab4: 683b ldr r3, [r7, #0] + 8008ab6: 785b ldrb r3, [r3, #1] + 8008ab8: 2b01 cmp r3, #1 + 8008aba: d128 bne.n 8008b0e + 8008abc: 68bb ldr r3, [r7, #8] + 8008abe: 015a lsls r2, r3, #5 + 8008ac0: 68fb ldr r3, [r7, #12] + 8008ac2: 4413 add r3, r2 + 8008ac4: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008ac8: 681b ldr r3, [r3, #0] + 8008aca: 68ba ldr r2, [r7, #8] + 8008acc: 0151 lsls r1, r2, #5 + 8008ace: 68fa ldr r2, [r7, #12] + 8008ad0: 440a add r2, r1 + 8008ad2: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8008ad6: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 + 8008ada: 6013 str r3, [r2, #0] + 8008adc: 683b ldr r3, [r7, #0] + 8008ade: 791b ldrb r3, [r3, #4] + 8008ae0: 2b03 cmp r3, #3 + 8008ae2: d003 beq.n 8008aec + 8008ae4: 683b ldr r3, [r7, #0] + 8008ae6: 791b ldrb r3, [r3, #4] + 8008ae8: 2b02 cmp r3, #2 + 8008aea: d138 bne.n 8008b5e + 8008aec: 68bb ldr r3, [r7, #8] + 8008aee: 015a lsls r2, r3, #5 + 8008af0: 68fb ldr r3, [r7, #12] + 8008af2: 4413 add r3, r2 + 8008af4: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008af8: 681b ldr r3, [r3, #0] + 8008afa: 68ba ldr r2, [r7, #8] + 8008afc: 0151 lsls r1, r2, #5 + 8008afe: 68fa ldr r2, [r7, #12] + 8008b00: 440a add r2, r1 + 8008b02: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8008b06: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8008b0a: 6013 str r3, [r2, #0] + 8008b0c: e027 b.n 8008b5e + 8008b0e: 68bb ldr r3, [r7, #8] + 8008b10: 015a lsls r2, r3, #5 + 8008b12: 68fb ldr r3, [r7, #12] + 8008b14: 4413 add r3, r2 + 8008b16: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008b1a: 681b ldr r3, [r3, #0] + 8008b1c: 68ba ldr r2, [r7, #8] + 8008b1e: 0151 lsls r1, r2, #5 + 8008b20: 68fa ldr r2, [r7, #12] + 8008b22: 440a add r2, r1 + 8008b24: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008b28: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 + 8008b2c: 6013 str r3, [r2, #0] + 8008b2e: 683b ldr r3, [r7, #0] + 8008b30: 791b ldrb r3, [r3, #4] + 8008b32: 2b03 cmp r3, #3 + 8008b34: d003 beq.n 8008b3e + 8008b36: 683b ldr r3, [r7, #0] + 8008b38: 791b ldrb r3, [r3, #4] + 8008b3a: 2b02 cmp r3, #2 + 8008b3c: d10f bne.n 8008b5e + 8008b3e: 68bb ldr r3, [r7, #8] + 8008b40: 015a lsls r2, r3, #5 + 8008b42: 68fb ldr r3, [r7, #12] + 8008b44: 4413 add r3, r2 + 8008b46: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008b4a: 681b ldr r3, [r3, #0] + 8008b4c: 68ba ldr r2, [r7, #8] + 8008b4e: 0151 lsls r1, r2, #5 + 8008b50: 68fa ldr r2, [r7, #12] + 8008b52: 440a add r2, r1 + 8008b54: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008b58: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8008b5c: 6013 str r3, [r2, #0] + 8008b5e: 2300 movs r3, #0 + 8008b60: 4618 mov r0, r3 + 8008b62: 3714 adds r7, #20 + 8008b64: 46bd mov sp, r7 + 8008b66: f85d 7b04 ldr.w r7, [sp], #4 + 8008b6a: 4770 bx lr + +08008b6c : + 8008b6c: b480 push {r7} + 8008b6e: b085 sub sp, #20 + 8008b70: af00 add r7, sp, #0 + 8008b72: 6078 str r0, [r7, #4] + 8008b74: 460b mov r3, r1 + 8008b76: 70fb strb r3, [r7, #3] + 8008b78: 687b ldr r3, [r7, #4] + 8008b7a: 60fb str r3, [r7, #12] + 8008b7c: 68fb ldr r3, [r7, #12] + 8008b7e: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008b82: 681b ldr r3, [r3, #0] + 8008b84: 68fa ldr r2, [r7, #12] + 8008b86: f502 6200 add.w r2, r2, #2048 @ 0x800 + 8008b8a: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 + 8008b8e: 6013 str r3, [r2, #0] + 8008b90: 68fb ldr r3, [r7, #12] + 8008b92: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008b96: 681a ldr r2, [r3, #0] + 8008b98: 78fb ldrb r3, [r7, #3] + 8008b9a: 011b lsls r3, r3, #4 + 8008b9c: f403 63fe and.w r3, r3, #2032 @ 0x7f0 + 8008ba0: 68f9 ldr r1, [r7, #12] + 8008ba2: f501 6100 add.w r1, r1, #2048 @ 0x800 + 8008ba6: 4313 orrs r3, r2 + 8008ba8: 600b str r3, [r1, #0] + 8008baa: 2300 movs r3, #0 + 8008bac: 4618 mov r0, r3 + 8008bae: 3714 adds r7, #20 + 8008bb0: 46bd mov sp, r7 + 8008bb2: f85d 7b04 ldr.w r7, [sp], #4 + 8008bb6: 4770 bx lr + +08008bb8 : + 8008bb8: b480 push {r7} + 8008bba: b085 sub sp, #20 + 8008bbc: af00 add r7, sp, #0 + 8008bbe: 6078 str r0, [r7, #4] + 8008bc0: 687b ldr r3, [r7, #4] + 8008bc2: 60fb str r3, [r7, #12] + 8008bc4: 68fb ldr r3, [r7, #12] + 8008bc6: f503 6360 add.w r3, r3, #3584 @ 0xe00 + 8008bca: 681b ldr r3, [r3, #0] + 8008bcc: 68fa ldr r2, [r7, #12] + 8008bce: f502 6260 add.w r2, r2, #3584 @ 0xe00 + 8008bd2: f023 0303 bic.w r3, r3, #3 + 8008bd6: 6013 str r3, [r2, #0] + 8008bd8: 68fb ldr r3, [r7, #12] + 8008bda: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008bde: 685b ldr r3, [r3, #4] + 8008be0: 68fa ldr r2, [r7, #12] + 8008be2: f502 6200 add.w r2, r2, #2048 @ 0x800 + 8008be6: f023 0302 bic.w r3, r3, #2 + 8008bea: 6053 str r3, [r2, #4] + 8008bec: 2300 movs r3, #0 + 8008bee: 4618 mov r0, r3 + 8008bf0: 3714 adds r7, #20 + 8008bf2: 46bd mov sp, r7 + 8008bf4: f85d 7b04 ldr.w r7, [sp], #4 + 8008bf8: 4770 bx lr + +08008bfa : + 8008bfa: b480 push {r7} + 8008bfc: b085 sub sp, #20 + 8008bfe: af00 add r7, sp, #0 + 8008c00: 6078 str r0, [r7, #4] + 8008c02: 687b ldr r3, [r7, #4] + 8008c04: 60fb str r3, [r7, #12] + 8008c06: 68fb ldr r3, [r7, #12] + 8008c08: f503 6360 add.w r3, r3, #3584 @ 0xe00 + 8008c0c: 681b ldr r3, [r3, #0] + 8008c0e: 68fa ldr r2, [r7, #12] + 8008c10: f502 6260 add.w r2, r2, #3584 @ 0xe00 + 8008c14: f023 0303 bic.w r3, r3, #3 + 8008c18: 6013 str r3, [r2, #0] + 8008c1a: 68fb ldr r3, [r7, #12] + 8008c1c: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008c20: 685b ldr r3, [r3, #4] + 8008c22: 68fa ldr r2, [r7, #12] + 8008c24: f502 6200 add.w r2, r2, #2048 @ 0x800 + 8008c28: f043 0302 orr.w r3, r3, #2 + 8008c2c: 6053 str r3, [r2, #4] + 8008c2e: 2300 movs r3, #0 + 8008c30: 4618 mov r0, r3 + 8008c32: 3714 adds r7, #20 + 8008c34: 46bd mov sp, r7 + 8008c36: f85d 7b04 ldr.w r7, [sp], #4 + 8008c3a: 4770 bx lr + +08008c3c : + 8008c3c: b480 push {r7} + 8008c3e: b085 sub sp, #20 + 8008c40: af00 add r7, sp, #0 + 8008c42: 6078 str r0, [r7, #4] + 8008c44: 687b ldr r3, [r7, #4] + 8008c46: 695b ldr r3, [r3, #20] + 8008c48: 60fb str r3, [r7, #12] + 8008c4a: 687b ldr r3, [r7, #4] + 8008c4c: 699b ldr r3, [r3, #24] + 8008c4e: 68fa ldr r2, [r7, #12] + 8008c50: 4013 ands r3, r2 + 8008c52: 60fb str r3, [r7, #12] + 8008c54: 68fb ldr r3, [r7, #12] + 8008c56: 4618 mov r0, r3 + 8008c58: 3714 adds r7, #20 + 8008c5a: 46bd mov sp, r7 + 8008c5c: f85d 7b04 ldr.w r7, [sp], #4 + 8008c60: 4770 bx lr + +08008c62 : + 8008c62: b480 push {r7} + 8008c64: b085 sub sp, #20 + 8008c66: af00 add r7, sp, #0 + 8008c68: 6078 str r0, [r7, #4] + 8008c6a: 687b ldr r3, [r7, #4] + 8008c6c: 60fb str r3, [r7, #12] + 8008c6e: 68fb ldr r3, [r7, #12] + 8008c70: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008c74: 699b ldr r3, [r3, #24] + 8008c76: 60bb str r3, [r7, #8] + 8008c78: 68fb ldr r3, [r7, #12] + 8008c7a: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008c7e: 69db ldr r3, [r3, #28] + 8008c80: 68ba ldr r2, [r7, #8] + 8008c82: 4013 ands r3, r2 + 8008c84: 60bb str r3, [r7, #8] + 8008c86: 68bb ldr r3, [r7, #8] + 8008c88: 0c1b lsrs r3, r3, #16 + 8008c8a: 4618 mov r0, r3 + 8008c8c: 3714 adds r7, #20 + 8008c8e: 46bd mov sp, r7 + 8008c90: f85d 7b04 ldr.w r7, [sp], #4 + 8008c94: 4770 bx lr + +08008c96 : + 8008c96: b480 push {r7} + 8008c98: b085 sub sp, #20 + 8008c9a: af00 add r7, sp, #0 + 8008c9c: 6078 str r0, [r7, #4] + 8008c9e: 687b ldr r3, [r7, #4] + 8008ca0: 60fb str r3, [r7, #12] + 8008ca2: 68fb ldr r3, [r7, #12] + 8008ca4: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008ca8: 699b ldr r3, [r3, #24] + 8008caa: 60bb str r3, [r7, #8] + 8008cac: 68fb ldr r3, [r7, #12] + 8008cae: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008cb2: 69db ldr r3, [r3, #28] + 8008cb4: 68ba ldr r2, [r7, #8] + 8008cb6: 4013 ands r3, r2 + 8008cb8: 60bb str r3, [r7, #8] + 8008cba: 68bb ldr r3, [r7, #8] + 8008cbc: b29b uxth r3, r3 + 8008cbe: 4618 mov r0, r3 + 8008cc0: 3714 adds r7, #20 + 8008cc2: 46bd mov sp, r7 + 8008cc4: f85d 7b04 ldr.w r7, [sp], #4 + 8008cc8: 4770 bx lr + +08008cca : + 8008cca: b480 push {r7} + 8008ccc: b085 sub sp, #20 + 8008cce: af00 add r7, sp, #0 + 8008cd0: 6078 str r0, [r7, #4] + 8008cd2: 460b mov r3, r1 + 8008cd4: 70fb strb r3, [r7, #3] + 8008cd6: 687b ldr r3, [r7, #4] + 8008cd8: 60fb str r3, [r7, #12] + 8008cda: 78fb ldrb r3, [r7, #3] + 8008cdc: 015a lsls r2, r3, #5 + 8008cde: 68fb ldr r3, [r7, #12] + 8008ce0: 4413 add r3, r2 + 8008ce2: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008ce6: 689b ldr r3, [r3, #8] + 8008ce8: 60bb str r3, [r7, #8] + 8008cea: 68fb ldr r3, [r7, #12] + 8008cec: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008cf0: 695b ldr r3, [r3, #20] + 8008cf2: 68ba ldr r2, [r7, #8] + 8008cf4: 4013 ands r3, r2 + 8008cf6: 60bb str r3, [r7, #8] + 8008cf8: 68bb ldr r3, [r7, #8] + 8008cfa: 4618 mov r0, r3 + 8008cfc: 3714 adds r7, #20 + 8008cfe: 46bd mov sp, r7 + 8008d00: f85d 7b04 ldr.w r7, [sp], #4 + 8008d04: 4770 bx lr + +08008d06 : + 8008d06: b480 push {r7} + 8008d08: b087 sub sp, #28 + 8008d0a: af00 add r7, sp, #0 + 8008d0c: 6078 str r0, [r7, #4] + 8008d0e: 460b mov r3, r1 + 8008d10: 70fb strb r3, [r7, #3] + 8008d12: 687b ldr r3, [r7, #4] + 8008d14: 617b str r3, [r7, #20] + 8008d16: 697b ldr r3, [r7, #20] + 8008d18: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008d1c: 691b ldr r3, [r3, #16] + 8008d1e: 613b str r3, [r7, #16] + 8008d20: 697b ldr r3, [r7, #20] + 8008d22: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008d26: 6b5b ldr r3, [r3, #52] @ 0x34 + 8008d28: 60fb str r3, [r7, #12] + 8008d2a: 78fb ldrb r3, [r7, #3] + 8008d2c: f003 030f and.w r3, r3, #15 + 8008d30: 68fa ldr r2, [r7, #12] + 8008d32: fa22 f303 lsr.w r3, r2, r3 + 8008d36: 01db lsls r3, r3, #7 + 8008d38: b2db uxtb r3, r3 + 8008d3a: 693a ldr r2, [r7, #16] + 8008d3c: 4313 orrs r3, r2 + 8008d3e: 613b str r3, [r7, #16] + 8008d40: 78fb ldrb r3, [r7, #3] + 8008d42: 015a lsls r2, r3, #5 + 8008d44: 697b ldr r3, [r7, #20] + 8008d46: 4413 add r3, r2 + 8008d48: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008d4c: 689b ldr r3, [r3, #8] + 8008d4e: 693a ldr r2, [r7, #16] + 8008d50: 4013 ands r3, r2 + 8008d52: 60bb str r3, [r7, #8] + 8008d54: 68bb ldr r3, [r7, #8] + 8008d56: 4618 mov r0, r3 + 8008d58: 371c adds r7, #28 + 8008d5a: 46bd mov sp, r7 + 8008d5c: f85d 7b04 ldr.w r7, [sp], #4 + 8008d60: 4770 bx lr + +08008d62 : + 8008d62: b480 push {r7} + 8008d64: b083 sub sp, #12 + 8008d66: af00 add r7, sp, #0 + 8008d68: 6078 str r0, [r7, #4] + 8008d6a: 687b ldr r3, [r7, #4] + 8008d6c: 695b ldr r3, [r3, #20] + 8008d6e: f003 0301 and.w r3, r3, #1 + 8008d72: 4618 mov r0, r3 + 8008d74: 370c adds r7, #12 + 8008d76: 46bd mov sp, r7 + 8008d78: f85d 7b04 ldr.w r7, [sp], #4 + 8008d7c: 4770 bx lr + +08008d7e : + 8008d7e: b480 push {r7} + 8008d80: b085 sub sp, #20 + 8008d82: af00 add r7, sp, #0 + 8008d84: 6078 str r0, [r7, #4] + 8008d86: 687b ldr r3, [r7, #4] + 8008d88: 60fb str r3, [r7, #12] + 8008d8a: 68fb ldr r3, [r7, #12] + 8008d8c: f503 6310 add.w r3, r3, #2304 @ 0x900 + 8008d90: 681b ldr r3, [r3, #0] + 8008d92: 68fa ldr r2, [r7, #12] + 8008d94: f502 6210 add.w r2, r2, #2304 @ 0x900 + 8008d98: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 + 8008d9c: f023 0307 bic.w r3, r3, #7 + 8008da0: 6013 str r3, [r2, #0] + 8008da2: 68fb ldr r3, [r7, #12] + 8008da4: f503 6300 add.w r3, r3, #2048 @ 0x800 + 8008da8: 685b ldr r3, [r3, #4] + 8008daa: 68fa ldr r2, [r7, #12] + 8008dac: f502 6200 add.w r2, r2, #2048 @ 0x800 + 8008db0: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8008db4: 6053 str r3, [r2, #4] + 8008db6: 2300 movs r3, #0 + 8008db8: 4618 mov r0, r3 + 8008dba: 3714 adds r7, #20 + 8008dbc: 46bd mov sp, r7 + 8008dbe: f85d 7b04 ldr.w r7, [sp], #4 + 8008dc2: 4770 bx lr + +08008dc4 : + 8008dc4: b480 push {r7} + 8008dc6: b087 sub sp, #28 + 8008dc8: af00 add r7, sp, #0 + 8008dca: 60f8 str r0, [r7, #12] + 8008dcc: 460b mov r3, r1 + 8008dce: 607a str r2, [r7, #4] + 8008dd0: 72fb strb r3, [r7, #11] + 8008dd2: 68fb ldr r3, [r7, #12] + 8008dd4: 617b str r3, [r7, #20] + 8008dd6: 68fb ldr r3, [r7, #12] + 8008dd8: 333c adds r3, #60 @ 0x3c + 8008dda: 3304 adds r3, #4 + 8008ddc: 681b ldr r3, [r3, #0] + 8008dde: 613b str r3, [r7, #16] + 8008de0: 693b ldr r3, [r7, #16] + 8008de2: 4a26 ldr r2, [pc, #152] @ (8008e7c ) + 8008de4: 4293 cmp r3, r2 + 8008de6: d90a bls.n 8008dfe + 8008de8: 697b ldr r3, [r7, #20] + 8008dea: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008dee: 681b ldr r3, [r3, #0] + 8008df0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 8008df4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 8008df8: d101 bne.n 8008dfe + 8008dfa: 2300 movs r3, #0 + 8008dfc: e037 b.n 8008e6e + 8008dfe: 697b ldr r3, [r7, #20] + 8008e00: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008e04: 461a mov r2, r3 + 8008e06: 2300 movs r3, #0 + 8008e08: 6113 str r3, [r2, #16] + 8008e0a: 697b ldr r3, [r7, #20] + 8008e0c: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008e10: 691b ldr r3, [r3, #16] + 8008e12: 697a ldr r2, [r7, #20] + 8008e14: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008e18: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8008e1c: 6113 str r3, [r2, #16] + 8008e1e: 697b ldr r3, [r7, #20] + 8008e20: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008e24: 691b ldr r3, [r3, #16] + 8008e26: 697a ldr r2, [r7, #20] + 8008e28: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008e2c: f043 0318 orr.w r3, r3, #24 + 8008e30: 6113 str r3, [r2, #16] + 8008e32: 697b ldr r3, [r7, #20] + 8008e34: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008e38: 691b ldr r3, [r3, #16] + 8008e3a: 697a ldr r2, [r7, #20] + 8008e3c: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008e40: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000 + 8008e44: 6113 str r3, [r2, #16] + 8008e46: 7afb ldrb r3, [r7, #11] + 8008e48: 2b01 cmp r3, #1 + 8008e4a: d10f bne.n 8008e6c + 8008e4c: 697b ldr r3, [r7, #20] + 8008e4e: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008e52: 461a mov r2, r3 + 8008e54: 687b ldr r3, [r7, #4] + 8008e56: 6153 str r3, [r2, #20] + 8008e58: 697b ldr r3, [r7, #20] + 8008e5a: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8008e5e: 681b ldr r3, [r3, #0] + 8008e60: 697a ldr r2, [r7, #20] + 8008e62: f502 6230 add.w r2, r2, #2816 @ 0xb00 + 8008e66: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000 + 8008e6a: 6013 str r3, [r2, #0] + 8008e6c: 2300 movs r3, #0 + 8008e6e: 4618 mov r0, r3 + 8008e70: 371c adds r7, #28 + 8008e72: 46bd mov sp, r7 + 8008e74: f85d 7b04 ldr.w r7, [sp], #4 + 8008e78: 4770 bx lr + 8008e7a: bf00 nop + 8008e7c: 4f54300a .word 0x4f54300a + +08008e80 : + 8008e80: b480 push {r7} + 8008e82: b085 sub sp, #20 + 8008e84: af00 add r7, sp, #0 + 8008e86: 6078 str r0, [r7, #4] + 8008e88: 2300 movs r3, #0 + 8008e8a: 60fb str r3, [r7, #12] + 8008e8c: 68fb ldr r3, [r7, #12] + 8008e8e: 3301 adds r3, #1 + 8008e90: 60fb str r3, [r7, #12] + 8008e92: 68fb ldr r3, [r7, #12] + 8008e94: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 8008e98: d901 bls.n 8008e9e + 8008e9a: 2303 movs r3, #3 + 8008e9c: e022 b.n 8008ee4 + 8008e9e: 687b ldr r3, [r7, #4] + 8008ea0: 691b ldr r3, [r3, #16] + 8008ea2: 2b00 cmp r3, #0 + 8008ea4: daf2 bge.n 8008e8c + 8008ea6: 230a movs r3, #10 + 8008ea8: 60fb str r3, [r7, #12] + 8008eaa: e002 b.n 8008eb2 + 8008eac: 68fb ldr r3, [r7, #12] + 8008eae: 3b01 subs r3, #1 + 8008eb0: 60fb str r3, [r7, #12] + 8008eb2: 68fb ldr r3, [r7, #12] + 8008eb4: 2b00 cmp r3, #0 + 8008eb6: d1f9 bne.n 8008eac + 8008eb8: 687b ldr r3, [r7, #4] + 8008eba: 691b ldr r3, [r3, #16] + 8008ebc: f043 0201 orr.w r2, r3, #1 + 8008ec0: 687b ldr r3, [r7, #4] + 8008ec2: 611a str r2, [r3, #16] + 8008ec4: 68fb ldr r3, [r7, #12] + 8008ec6: 3301 adds r3, #1 + 8008ec8: 60fb str r3, [r7, #12] + 8008eca: 68fb ldr r3, [r7, #12] + 8008ecc: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 8008ed0: d901 bls.n 8008ed6 + 8008ed2: 2303 movs r3, #3 + 8008ed4: e006 b.n 8008ee4 + 8008ed6: 687b ldr r3, [r7, #4] + 8008ed8: 691b ldr r3, [r3, #16] + 8008eda: f003 0301 and.w r3, r3, #1 + 8008ede: 2b01 cmp r3, #1 + 8008ee0: d0f0 beq.n 8008ec4 + 8008ee2: 2300 movs r3, #0 + 8008ee4: 4618 mov r0, r3 + 8008ee6: 3714 adds r7, #20 + 8008ee8: 46bd mov sp, r7 + 8008eea: f85d 7b04 ldr.w r7, [sp], #4 + 8008eee: 4770 bx lr + +08008ef0 : + 8008ef0: b580 push {r7, lr} + 8008ef2: b084 sub sp, #16 + 8008ef4: af00 add r7, sp, #0 + 8008ef6: 6078 str r0, [r7, #4] + 8008ef8: 460b mov r3, r1 + 8008efa: 70fb strb r3, [r7, #3] + 8008efc: 2010 movs r0, #16 + 8008efe: f002 f9e3 bl 800b2c8 + 8008f02: 60f8 str r0, [r7, #12] + 8008f04: 68fb ldr r3, [r7, #12] + 8008f06: 2b00 cmp r3, #0 + 8008f08: d109 bne.n 8008f1e + 8008f0a: 687b ldr r3, [r7, #4] + 8008f0c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8008f10: 687b ldr r3, [r7, #4] + 8008f12: 32b0 adds r2, #176 @ 0xb0 + 8008f14: 2100 movs r1, #0 + 8008f16: f843 1022 str.w r1, [r3, r2, lsl #2] + 8008f1a: 2302 movs r3, #2 + 8008f1c: e048 b.n 8008fb0 + 8008f1e: 687b ldr r3, [r7, #4] + 8008f20: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8008f24: 687b ldr r3, [r7, #4] + 8008f26: 32b0 adds r2, #176 @ 0xb0 + 8008f28: 68f9 ldr r1, [r7, #12] + 8008f2a: f843 1022 str.w r1, [r3, r2, lsl #2] + 8008f2e: 687b ldr r3, [r7, #4] + 8008f30: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8008f34: 687b ldr r3, [r7, #4] + 8008f36: 32b0 adds r2, #176 @ 0xb0 + 8008f38: f853 2022 ldr.w r2, [r3, r2, lsl #2] + 8008f3c: 687b ldr r3, [r7, #4] + 8008f3e: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc + 8008f42: 687b ldr r3, [r7, #4] + 8008f44: 7c1b ldrb r3, [r3, #16] + 8008f46: 2b00 cmp r3, #0 + 8008f48: d10d bne.n 8008f66 + 8008f4a: 4b1b ldr r3, [pc, #108] @ (8008fb8 ) + 8008f4c: 781b ldrb r3, [r3, #0] + 8008f4e: f003 020f and.w r2, r3, #15 + 8008f52: 6879 ldr r1, [r7, #4] + 8008f54: 4613 mov r3, r2 + 8008f56: 009b lsls r3, r3, #2 + 8008f58: 4413 add r3, r2 + 8008f5a: 009b lsls r3, r3, #2 + 8008f5c: 440b add r3, r1 + 8008f5e: 331c adds r3, #28 + 8008f60: 2207 movs r2, #7 + 8008f62: 601a str r2, [r3, #0] + 8008f64: e00c b.n 8008f80 + 8008f66: 4b14 ldr r3, [pc, #80] @ (8008fb8 ) + 8008f68: 781b ldrb r3, [r3, #0] + 8008f6a: f003 020f and.w r2, r3, #15 + 8008f6e: 6879 ldr r1, [r7, #4] + 8008f70: 4613 mov r3, r2 + 8008f72: 009b lsls r3, r3, #2 + 8008f74: 4413 add r3, r2 + 8008f76: 009b lsls r3, r3, #2 + 8008f78: 440b add r3, r1 + 8008f7a: 331c adds r3, #28 + 8008f7c: 220a movs r2, #10 + 8008f7e: 601a str r2, [r3, #0] + 8008f80: 4b0d ldr r3, [pc, #52] @ (8008fb8 ) + 8008f82: 7819 ldrb r1, [r3, #0] + 8008f84: 230e movs r3, #14 + 8008f86: 2203 movs r2, #3 + 8008f88: 6878 ldr r0, [r7, #4] + 8008f8a: f002 f83e bl 800b00a + 8008f8e: 4b0a ldr r3, [pc, #40] @ (8008fb8 ) + 8008f90: 781b ldrb r3, [r3, #0] + 8008f92: f003 020f and.w r2, r3, #15 + 8008f96: 6879 ldr r1, [r7, #4] + 8008f98: 4613 mov r3, r2 + 8008f9a: 009b lsls r3, r3, #2 + 8008f9c: 4413 add r3, r2 + 8008f9e: 009b lsls r3, r3, #2 + 8008fa0: 440b add r3, r1 + 8008fa2: 3323 adds r3, #35 @ 0x23 + 8008fa4: 2201 movs r2, #1 + 8008fa6: 701a strb r2, [r3, #0] + 8008fa8: 68fb ldr r3, [r7, #12] + 8008faa: 2200 movs r2, #0 + 8008fac: 731a strb r2, [r3, #12] + 8008fae: 2300 movs r3, #0 + 8008fb0: 4618 mov r0, r3 + 8008fb2: 3710 adds r7, #16 + 8008fb4: 46bd mov sp, r7 + 8008fb6: bd80 pop {r7, pc} + 8008fb8: 2000013d .word 0x2000013d + +08008fbc : + 8008fbc: b580 push {r7, lr} + 8008fbe: b082 sub sp, #8 + 8008fc0: af00 add r7, sp, #0 + 8008fc2: 6078 str r0, [r7, #4] + 8008fc4: 460b mov r3, r1 + 8008fc6: 70fb strb r3, [r7, #3] + 8008fc8: 4b1f ldr r3, [pc, #124] @ (8009048 ) + 8008fca: 781b ldrb r3, [r3, #0] + 8008fcc: 4619 mov r1, r3 + 8008fce: 6878 ldr r0, [r7, #4] + 8008fd0: f002 f841 bl 800b056 + 8008fd4: 4b1c ldr r3, [pc, #112] @ (8009048 ) + 8008fd6: 781b ldrb r3, [r3, #0] + 8008fd8: f003 020f and.w r2, r3, #15 + 8008fdc: 6879 ldr r1, [r7, #4] + 8008fde: 4613 mov r3, r2 + 8008fe0: 009b lsls r3, r3, #2 + 8008fe2: 4413 add r3, r2 + 8008fe4: 009b lsls r3, r3, #2 + 8008fe6: 440b add r3, r1 + 8008fe8: 3323 adds r3, #35 @ 0x23 + 8008fea: 2200 movs r2, #0 + 8008fec: 701a strb r2, [r3, #0] + 8008fee: 4b16 ldr r3, [pc, #88] @ (8009048 ) + 8008ff0: 781b ldrb r3, [r3, #0] + 8008ff2: f003 020f and.w r2, r3, #15 + 8008ff6: 6879 ldr r1, [r7, #4] + 8008ff8: 4613 mov r3, r2 + 8008ffa: 009b lsls r3, r3, #2 + 8008ffc: 4413 add r3, r2 + 8008ffe: 009b lsls r3, r3, #2 + 8009000: 440b add r3, r1 + 8009002: 331c adds r3, #28 + 8009004: 2200 movs r2, #0 + 8009006: 601a str r2, [r3, #0] + 8009008: 687b ldr r3, [r7, #4] + 800900a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 800900e: 687b ldr r3, [r7, #4] + 8009010: 32b0 adds r2, #176 @ 0xb0 + 8009012: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009016: 2b00 cmp r3, #0 + 8009018: d011 beq.n 800903e + 800901a: 687b ldr r3, [r7, #4] + 800901c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8009020: 687b ldr r3, [r7, #4] + 8009022: 32b0 adds r2, #176 @ 0xb0 + 8009024: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009028: 4618 mov r0, r3 + 800902a: f002 f95b bl 800b2e4 + 800902e: 687b ldr r3, [r7, #4] + 8009030: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8009034: 687b ldr r3, [r7, #4] + 8009036: 32b0 adds r2, #176 @ 0xb0 + 8009038: 2100 movs r1, #0 + 800903a: f843 1022 str.w r1, [r3, r2, lsl #2] + 800903e: 2300 movs r3, #0 + 8009040: 4618 mov r0, r3 + 8009042: 3708 adds r7, #8 + 8009044: 46bd mov sp, r7 + 8009046: bd80 pop {r7, pc} + 8009048: 2000013d .word 0x2000013d + +0800904c : + 800904c: b580 push {r7, lr} + 800904e: b086 sub sp, #24 + 8009050: af00 add r7, sp, #0 + 8009052: 6078 str r0, [r7, #4] + 8009054: 6039 str r1, [r7, #0] + 8009056: 687b ldr r3, [r7, #4] + 8009058: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 800905c: 687b ldr r3, [r7, #4] + 800905e: 32b0 adds r2, #176 @ 0xb0 + 8009060: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009064: 60fb str r3, [r7, #12] + 8009066: 2300 movs r3, #0 + 8009068: 75fb strb r3, [r7, #23] + 800906a: 2300 movs r3, #0 + 800906c: 817b strh r3, [r7, #10] + 800906e: 68fb ldr r3, [r7, #12] + 8009070: 2b00 cmp r3, #0 + 8009072: d101 bne.n 8009078 + 8009074: 2303 movs r3, #3 + 8009076: e0e8 b.n 800924a + 8009078: 683b ldr r3, [r7, #0] + 800907a: 781b ldrb r3, [r3, #0] + 800907c: f003 0360 and.w r3, r3, #96 @ 0x60 + 8009080: 2b00 cmp r3, #0 + 8009082: d046 beq.n 8009112 + 8009084: 2b20 cmp r3, #32 + 8009086: f040 80d8 bne.w 800923a + 800908a: 683b ldr r3, [r7, #0] + 800908c: 785b ldrb r3, [r3, #1] + 800908e: 3b02 subs r3, #2 + 8009090: 2b09 cmp r3, #9 + 8009092: d836 bhi.n 8009102 + 8009094: a201 add r2, pc, #4 @ (adr r2, 800909c ) + 8009096: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800909a: bf00 nop + 800909c: 080090f3 .word 0x080090f3 + 80090a0: 080090d3 .word 0x080090d3 + 80090a4: 08009103 .word 0x08009103 + 80090a8: 08009103 .word 0x08009103 + 80090ac: 08009103 .word 0x08009103 + 80090b0: 08009103 .word 0x08009103 + 80090b4: 08009103 .word 0x08009103 + 80090b8: 08009103 .word 0x08009103 + 80090bc: 080090e1 .word 0x080090e1 + 80090c0: 080090c5 .word 0x080090c5 + 80090c4: 683b ldr r3, [r7, #0] + 80090c6: 885b ldrh r3, [r3, #2] + 80090c8: b2db uxtb r3, r3 + 80090ca: 461a mov r2, r3 + 80090cc: 68fb ldr r3, [r7, #12] + 80090ce: 601a str r2, [r3, #0] + 80090d0: e01e b.n 8009110 + 80090d2: 68fb ldr r3, [r7, #12] + 80090d4: 2201 movs r2, #1 + 80090d6: 4619 mov r1, r3 + 80090d8: 6878 ldr r0, [r7, #4] + 80090da: f001 fc25 bl 800a928 + 80090de: e017 b.n 8009110 + 80090e0: 683b ldr r3, [r7, #0] + 80090e2: 885b ldrh r3, [r3, #2] + 80090e4: 0a1b lsrs r3, r3, #8 + 80090e6: b29b uxth r3, r3 + 80090e8: b2db uxtb r3, r3 + 80090ea: 461a mov r2, r3 + 80090ec: 68fb ldr r3, [r7, #12] + 80090ee: 605a str r2, [r3, #4] + 80090f0: e00e b.n 8009110 + 80090f2: 68fb ldr r3, [r7, #12] + 80090f4: 3304 adds r3, #4 + 80090f6: 2201 movs r2, #1 + 80090f8: 4619 mov r1, r3 + 80090fa: 6878 ldr r0, [r7, #4] + 80090fc: f001 fc14 bl 800a928 + 8009100: e006 b.n 8009110 + 8009102: 6839 ldr r1, [r7, #0] + 8009104: 6878 ldr r0, [r7, #4] + 8009106: f001 fb92 bl 800a82e + 800910a: 2303 movs r3, #3 + 800910c: 75fb strb r3, [r7, #23] + 800910e: bf00 nop + 8009110: e09a b.n 8009248 + 8009112: 683b ldr r3, [r7, #0] + 8009114: 785b ldrb r3, [r3, #1] + 8009116: 2b0b cmp r3, #11 + 8009118: f200 8086 bhi.w 8009228 + 800911c: a201 add r2, pc, #4 @ (adr r2, 8009124 ) + 800911e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009122: bf00 nop + 8009124: 08009155 .word 0x08009155 + 8009128: 08009237 .word 0x08009237 + 800912c: 08009229 .word 0x08009229 + 8009130: 08009229 .word 0x08009229 + 8009134: 08009229 .word 0x08009229 + 8009138: 08009229 .word 0x08009229 + 800913c: 0800917f .word 0x0800917f + 8009140: 08009229 .word 0x08009229 + 8009144: 08009229 .word 0x08009229 + 8009148: 08009229 .word 0x08009229 + 800914c: 080091d7 .word 0x080091d7 + 8009150: 08009201 .word 0x08009201 + 8009154: 687b ldr r3, [r7, #4] + 8009156: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 800915a: b2db uxtb r3, r3 + 800915c: 2b03 cmp r3, #3 + 800915e: d107 bne.n 8009170 + 8009160: f107 030a add.w r3, r7, #10 + 8009164: 2202 movs r2, #2 + 8009166: 4619 mov r1, r3 + 8009168: 6878 ldr r0, [r7, #4] + 800916a: f001 fbdd bl 800a928 + 800916e: e063 b.n 8009238 + 8009170: 6839 ldr r1, [r7, #0] + 8009172: 6878 ldr r0, [r7, #4] + 8009174: f001 fb5b bl 800a82e + 8009178: 2303 movs r3, #3 + 800917a: 75fb strb r3, [r7, #23] + 800917c: e05c b.n 8009238 + 800917e: 683b ldr r3, [r7, #0] + 8009180: 885b ldrh r3, [r3, #2] + 8009182: 0a1b lsrs r3, r3, #8 + 8009184: b29b uxth r3, r3 + 8009186: 2b22 cmp r3, #34 @ 0x22 + 8009188: d108 bne.n 800919c + 800918a: 683b ldr r3, [r7, #0] + 800918c: 88db ldrh r3, [r3, #6] + 800918e: 2b2d cmp r3, #45 @ 0x2d + 8009190: bf28 it cs + 8009192: 232d movcs r3, #45 @ 0x2d + 8009194: 82bb strh r3, [r7, #20] + 8009196: 4b2f ldr r3, [pc, #188] @ (8009254 ) + 8009198: 613b str r3, [r7, #16] + 800919a: e015 b.n 80091c8 + 800919c: 683b ldr r3, [r7, #0] + 800919e: 885b ldrh r3, [r3, #2] + 80091a0: 0a1b lsrs r3, r3, #8 + 80091a2: b29b uxth r3, r3 + 80091a4: 2b21 cmp r3, #33 @ 0x21 + 80091a6: d108 bne.n 80091ba + 80091a8: 4b2b ldr r3, [pc, #172] @ (8009258 ) + 80091aa: 613b str r3, [r7, #16] + 80091ac: 683b ldr r3, [r7, #0] + 80091ae: 88db ldrh r3, [r3, #6] + 80091b0: 2b09 cmp r3, #9 + 80091b2: bf28 it cs + 80091b4: 2309 movcs r3, #9 + 80091b6: 82bb strh r3, [r7, #20] + 80091b8: e006 b.n 80091c8 + 80091ba: 6839 ldr r1, [r7, #0] + 80091bc: 6878 ldr r0, [r7, #4] + 80091be: f001 fb36 bl 800a82e + 80091c2: 2303 movs r3, #3 + 80091c4: 75fb strb r3, [r7, #23] + 80091c6: e037 b.n 8009238 + 80091c8: 8abb ldrh r3, [r7, #20] + 80091ca: 461a mov r2, r3 + 80091cc: 6939 ldr r1, [r7, #16] + 80091ce: 6878 ldr r0, [r7, #4] + 80091d0: f001 fbaa bl 800a928 + 80091d4: e030 b.n 8009238 + 80091d6: 687b ldr r3, [r7, #4] + 80091d8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 80091dc: b2db uxtb r3, r3 + 80091de: 2b03 cmp r3, #3 + 80091e0: d107 bne.n 80091f2 + 80091e2: 68fb ldr r3, [r7, #12] + 80091e4: 3308 adds r3, #8 + 80091e6: 2201 movs r2, #1 + 80091e8: 4619 mov r1, r3 + 80091ea: 6878 ldr r0, [r7, #4] + 80091ec: f001 fb9c bl 800a928 + 80091f0: e022 b.n 8009238 + 80091f2: 6839 ldr r1, [r7, #0] + 80091f4: 6878 ldr r0, [r7, #4] + 80091f6: f001 fb1a bl 800a82e + 80091fa: 2303 movs r3, #3 + 80091fc: 75fb strb r3, [r7, #23] + 80091fe: e01b b.n 8009238 + 8009200: 687b ldr r3, [r7, #4] + 8009202: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8009206: b2db uxtb r3, r3 + 8009208: 2b03 cmp r3, #3 + 800920a: d106 bne.n 800921a + 800920c: 683b ldr r3, [r7, #0] + 800920e: 885b ldrh r3, [r3, #2] + 8009210: b2db uxtb r3, r3 + 8009212: 461a mov r2, r3 + 8009214: 68fb ldr r3, [r7, #12] + 8009216: 609a str r2, [r3, #8] + 8009218: e00e b.n 8009238 + 800921a: 6839 ldr r1, [r7, #0] + 800921c: 6878 ldr r0, [r7, #4] + 800921e: f001 fb06 bl 800a82e + 8009222: 2303 movs r3, #3 + 8009224: 75fb strb r3, [r7, #23] + 8009226: e007 b.n 8009238 + 8009228: 6839 ldr r1, [r7, #0] + 800922a: 6878 ldr r0, [r7, #4] + 800922c: f001 faff bl 800a82e + 8009230: 2303 movs r3, #3 + 8009232: 75fb strb r3, [r7, #23] + 8009234: e000 b.n 8009238 + 8009236: bf00 nop + 8009238: e006 b.n 8009248 + 800923a: 6839 ldr r1, [r7, #0] + 800923c: 6878 ldr r0, [r7, #4] + 800923e: f001 faf6 bl 800a82e + 8009242: 2303 movs r3, #3 + 8009244: 75fb strb r3, [r7, #23] + 8009246: bf00 nop + 8009248: 7dfb ldrb r3, [r7, #23] + 800924a: 4618 mov r0, r3 + 800924c: 3718 adds r7, #24 + 800924e: 46bd mov sp, r7 + 8009250: bd80 pop {r7, pc} + 8009252: bf00 nop + 8009254: 20000110 .word 0x20000110 + 8009258: 200000f8 .word 0x200000f8 + +0800925c : + 800925c: b580 push {r7, lr} + 800925e: b086 sub sp, #24 + 8009260: af00 add r7, sp, #0 + 8009262: 60f8 str r0, [r7, #12] + 8009264: 60b9 str r1, [r7, #8] + 8009266: 4613 mov r3, r2 + 8009268: 80fb strh r3, [r7, #6] + 800926a: 68fb ldr r3, [r7, #12] + 800926c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8009270: 68fb ldr r3, [r7, #12] + 8009272: 32b0 adds r2, #176 @ 0xb0 + 8009274: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009278: 617b str r3, [r7, #20] + 800927a: 697b ldr r3, [r7, #20] + 800927c: 2b00 cmp r3, #0 + 800927e: d101 bne.n 8009284 + 8009280: 2303 movs r3, #3 + 8009282: e014 b.n 80092ae + 8009284: 68fb ldr r3, [r7, #12] + 8009286: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 800928a: b2db uxtb r3, r3 + 800928c: 2b03 cmp r3, #3 + 800928e: d10d bne.n 80092ac + 8009290: 697b ldr r3, [r7, #20] + 8009292: 7b1b ldrb r3, [r3, #12] + 8009294: 2b00 cmp r3, #0 + 8009296: d109 bne.n 80092ac + 8009298: 697b ldr r3, [r7, #20] + 800929a: 2201 movs r2, #1 + 800929c: 731a strb r2, [r3, #12] + 800929e: 4b06 ldr r3, [pc, #24] @ (80092b8 ) + 80092a0: 7819 ldrb r1, [r3, #0] + 80092a2: 88fb ldrh r3, [r7, #6] + 80092a4: 68ba ldr r2, [r7, #8] + 80092a6: 68f8 ldr r0, [r7, #12] + 80092a8: f001 ff7d bl 800b1a6 + 80092ac: 2300 movs r3, #0 + 80092ae: 4618 mov r0, r3 + 80092b0: 3718 adds r7, #24 + 80092b2: 46bd mov sp, r7 + 80092b4: bd80 pop {r7, pc} + 80092b6: bf00 nop + 80092b8: 2000013d .word 0x2000013d + +080092bc : + 80092bc: b580 push {r7, lr} + 80092be: b084 sub sp, #16 + 80092c0: af00 add r7, sp, #0 + 80092c2: 6078 str r0, [r7, #4] + 80092c4: 2181 movs r1, #129 @ 0x81 + 80092c6: 4809 ldr r0, [pc, #36] @ (80092ec ) + 80092c8: f000 fc4e bl 8009b68 + 80092cc: 60f8 str r0, [r7, #12] + 80092ce: 68fb ldr r3, [r7, #12] + 80092d0: 2b00 cmp r3, #0 + 80092d2: d002 beq.n 80092da + 80092d4: 68fb ldr r3, [r7, #12] + 80092d6: 220a movs r2, #10 + 80092d8: 719a strb r2, [r3, #6] + 80092da: 687b ldr r3, [r7, #4] + 80092dc: 2222 movs r2, #34 @ 0x22 + 80092de: 801a strh r2, [r3, #0] + 80092e0: 4b02 ldr r3, [pc, #8] @ (80092ec ) + 80092e2: 4618 mov r0, r3 + 80092e4: 3710 adds r7, #16 + 80092e6: 46bd mov sp, r7 + 80092e8: bd80 pop {r7, pc} + 80092ea: bf00 nop + 80092ec: 200000d4 .word 0x200000d4 + +080092f0 : + 80092f0: b580 push {r7, lr} + 80092f2: b084 sub sp, #16 + 80092f4: af00 add r7, sp, #0 + 80092f6: 6078 str r0, [r7, #4] + 80092f8: 2181 movs r1, #129 @ 0x81 + 80092fa: 4809 ldr r0, [pc, #36] @ (8009320 ) + 80092fc: f000 fc34 bl 8009b68 + 8009300: 60f8 str r0, [r7, #12] + 8009302: 68fb ldr r3, [r7, #12] + 8009304: 2b00 cmp r3, #0 + 8009306: d002 beq.n 800930e + 8009308: 68fb ldr r3, [r7, #12] + 800930a: 2207 movs r2, #7 + 800930c: 719a strb r2, [r3, #6] + 800930e: 687b ldr r3, [r7, #4] + 8009310: 2222 movs r2, #34 @ 0x22 + 8009312: 801a strh r2, [r3, #0] + 8009314: 4b02 ldr r3, [pc, #8] @ (8009320 ) + 8009316: 4618 mov r0, r3 + 8009318: 3710 adds r7, #16 + 800931a: 46bd mov sp, r7 + 800931c: bd80 pop {r7, pc} + 800931e: bf00 nop + 8009320: 200000d4 .word 0x200000d4 + +08009324 : + 8009324: b580 push {r7, lr} + 8009326: b084 sub sp, #16 + 8009328: af00 add r7, sp, #0 + 800932a: 6078 str r0, [r7, #4] + 800932c: 2181 movs r1, #129 @ 0x81 + 800932e: 4809 ldr r0, [pc, #36] @ (8009354 ) + 8009330: f000 fc1a bl 8009b68 + 8009334: 60f8 str r0, [r7, #12] + 8009336: 68fb ldr r3, [r7, #12] + 8009338: 2b00 cmp r3, #0 + 800933a: d002 beq.n 8009342 + 800933c: 68fb ldr r3, [r7, #12] + 800933e: 220a movs r2, #10 + 8009340: 719a strb r2, [r3, #6] + 8009342: 687b ldr r3, [r7, #4] + 8009344: 2222 movs r2, #34 @ 0x22 + 8009346: 801a strh r2, [r3, #0] + 8009348: 4b02 ldr r3, [pc, #8] @ (8009354 ) + 800934a: 4618 mov r0, r3 + 800934c: 3710 adds r7, #16 + 800934e: 46bd mov sp, r7 + 8009350: bd80 pop {r7, pc} + 8009352: bf00 nop + 8009354: 200000d4 .word 0x200000d4 + +08009358 : + 8009358: b480 push {r7} + 800935a: b083 sub sp, #12 + 800935c: af00 add r7, sp, #0 + 800935e: 6078 str r0, [r7, #4] + 8009360: 460b mov r3, r1 + 8009362: 70fb strb r3, [r7, #3] + 8009364: 687b ldr r3, [r7, #4] + 8009366: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 800936a: 687b ldr r3, [r7, #4] + 800936c: 32b0 adds r2, #176 @ 0xb0 + 800936e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009372: 2200 movs r2, #0 + 8009374: 731a strb r2, [r3, #12] + 8009376: 2300 movs r3, #0 + 8009378: 4618 mov r0, r3 + 800937a: 370c adds r7, #12 + 800937c: 46bd mov sp, r7 + 800937e: f85d 7b04 ldr.w r7, [sp], #4 + 8009382: 4770 bx lr + +08009384 : + 8009384: b480 push {r7} + 8009386: b083 sub sp, #12 + 8009388: af00 add r7, sp, #0 + 800938a: 6078 str r0, [r7, #4] + 800938c: 687b ldr r3, [r7, #4] + 800938e: 220a movs r2, #10 + 8009390: 801a strh r2, [r3, #0] + 8009392: 4b03 ldr r3, [pc, #12] @ (80093a0 ) + 8009394: 4618 mov r0, r3 + 8009396: 370c adds r7, #12 + 8009398: 46bd mov sp, r7 + 800939a: f85d 7b04 ldr.w r7, [sp], #4 + 800939e: 4770 bx lr + 80093a0: 20000104 .word 0x20000104 + +080093a4 : + 80093a4: b580 push {r7, lr} + 80093a6: b086 sub sp, #24 + 80093a8: af00 add r7, sp, #0 + 80093aa: 60f8 str r0, [r7, #12] + 80093ac: 60b9 str r1, [r7, #8] + 80093ae: 4613 mov r3, r2 + 80093b0: 71fb strb r3, [r7, #7] + 80093b2: 68fb ldr r3, [r7, #12] + 80093b4: 2b00 cmp r3, #0 + 80093b6: d101 bne.n 80093bc + 80093b8: 2303 movs r3, #3 + 80093ba: e01f b.n 80093fc + 80093bc: 68fb ldr r3, [r7, #12] + 80093be: 2200 movs r2, #0 + 80093c0: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 + 80093c4: 68fb ldr r3, [r7, #12] + 80093c6: 2200 movs r2, #0 + 80093c8: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 + 80093cc: 68fb ldr r3, [r7, #12] + 80093ce: 2200 movs r2, #0 + 80093d0: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 + 80093d4: 68bb ldr r3, [r7, #8] + 80093d6: 2b00 cmp r3, #0 + 80093d8: d003 beq.n 80093e2 + 80093da: 68fb ldr r3, [r7, #12] + 80093dc: 68ba ldr r2, [r7, #8] + 80093de: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 + 80093e2: 68fb ldr r3, [r7, #12] + 80093e4: 2201 movs r2, #1 + 80093e6: f883 229c strb.w r2, [r3, #668] @ 0x29c + 80093ea: 68fb ldr r3, [r7, #12] + 80093ec: 79fa ldrb r2, [r7, #7] + 80093ee: 701a strb r2, [r3, #0] + 80093f0: 68f8 ldr r0, [r7, #12] + 80093f2: f001 fda3 bl 800af3c + 80093f6: 4603 mov r3, r0 + 80093f8: 75fb strb r3, [r7, #23] + 80093fa: 7dfb ldrb r3, [r7, #23] + 80093fc: 4618 mov r0, r3 + 80093fe: 3718 adds r7, #24 + 8009400: 46bd mov sp, r7 + 8009402: bd80 pop {r7, pc} + +08009404 : + 8009404: b580 push {r7, lr} + 8009406: b084 sub sp, #16 + 8009408: af00 add r7, sp, #0 + 800940a: 6078 str r0, [r7, #4] + 800940c: 6039 str r1, [r7, #0] + 800940e: 2300 movs r3, #0 + 8009410: 81fb strh r3, [r7, #14] + 8009412: 683b ldr r3, [r7, #0] + 8009414: 2b00 cmp r3, #0 + 8009416: d101 bne.n 800941c + 8009418: 2303 movs r3, #3 + 800941a: e025 b.n 8009468 + 800941c: 687b ldr r3, [r7, #4] + 800941e: 683a ldr r2, [r7, #0] + 8009420: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 + 8009424: 687b ldr r3, [r7, #4] + 8009426: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 800942a: 687b ldr r3, [r7, #4] + 800942c: 32ae adds r2, #174 @ 0xae + 800942e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009432: 6adb ldr r3, [r3, #44] @ 0x2c + 8009434: 2b00 cmp r3, #0 + 8009436: d00f beq.n 8009458 + 8009438: 687b ldr r3, [r7, #4] + 800943a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 800943e: 687b ldr r3, [r7, #4] + 8009440: 32ae adds r2, #174 @ 0xae + 8009442: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009446: 6adb ldr r3, [r3, #44] @ 0x2c + 8009448: f107 020e add.w r2, r7, #14 + 800944c: 4610 mov r0, r2 + 800944e: 4798 blx r3 + 8009450: 4602 mov r2, r0 + 8009452: 687b ldr r3, [r7, #4] + 8009454: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 + 8009458: 687b ldr r3, [r7, #4] + 800945a: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 + 800945e: 1c5a adds r2, r3, #1 + 8009460: 687b ldr r3, [r7, #4] + 8009462: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 + 8009466: 2300 movs r3, #0 + 8009468: 4618 mov r0, r3 + 800946a: 3710 adds r7, #16 + 800946c: 46bd mov sp, r7 + 800946e: bd80 pop {r7, pc} + +08009470 : + 8009470: b580 push {r7, lr} + 8009472: b082 sub sp, #8 + 8009474: af00 add r7, sp, #0 + 8009476: 6078 str r0, [r7, #4] + 8009478: 6878 ldr r0, [r7, #4] + 800947a: f001 fdab bl 800afd4 + 800947e: 4603 mov r3, r0 + 8009480: 4618 mov r0, r3 + 8009482: 3708 adds r7, #8 + 8009484: 46bd mov sp, r7 + 8009486: bd80 pop {r7, pc} + +08009488 : + 8009488: b480 push {r7} + 800948a: b083 sub sp, #12 + 800948c: af00 add r7, sp, #0 + 800948e: 6078 str r0, [r7, #4] + 8009490: 2300 movs r3, #0 + 8009492: 4618 mov r0, r3 + 8009494: 370c adds r7, #12 + 8009496: 46bd mov sp, r7 + 8009498: f85d 7b04 ldr.w r7, [sp], #4 + 800949c: 4770 bx lr + +0800949e : + 800949e: b580 push {r7, lr} + 80094a0: b084 sub sp, #16 + 80094a2: af00 add r7, sp, #0 + 80094a4: 6078 str r0, [r7, #4] + 80094a6: 460b mov r3, r1 + 80094a8: 70fb strb r3, [r7, #3] + 80094aa: 2300 movs r3, #0 + 80094ac: 73fb strb r3, [r7, #15] + 80094ae: 687b ldr r3, [r7, #4] + 80094b0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 80094b4: 2b00 cmp r3, #0 + 80094b6: d009 beq.n 80094cc + 80094b8: 687b ldr r3, [r7, #4] + 80094ba: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 80094be: 681b ldr r3, [r3, #0] + 80094c0: 78fa ldrb r2, [r7, #3] + 80094c2: 4611 mov r1, r2 + 80094c4: 6878 ldr r0, [r7, #4] + 80094c6: 4798 blx r3 + 80094c8: 4603 mov r3, r0 + 80094ca: 73fb strb r3, [r7, #15] + 80094cc: 7bfb ldrb r3, [r7, #15] + 80094ce: 4618 mov r0, r3 + 80094d0: 3710 adds r7, #16 + 80094d2: 46bd mov sp, r7 + 80094d4: bd80 pop {r7, pc} + +080094d6 : + 80094d6: b580 push {r7, lr} + 80094d8: b084 sub sp, #16 + 80094da: af00 add r7, sp, #0 + 80094dc: 6078 str r0, [r7, #4] + 80094de: 460b mov r3, r1 + 80094e0: 70fb strb r3, [r7, #3] + 80094e2: 2300 movs r3, #0 + 80094e4: 73fb strb r3, [r7, #15] + 80094e6: 687b ldr r3, [r7, #4] + 80094e8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 80094ec: 685b ldr r3, [r3, #4] + 80094ee: 78fa ldrb r2, [r7, #3] + 80094f0: 4611 mov r1, r2 + 80094f2: 6878 ldr r0, [r7, #4] + 80094f4: 4798 blx r3 + 80094f6: 4603 mov r3, r0 + 80094f8: 2b00 cmp r3, #0 + 80094fa: d001 beq.n 8009500 + 80094fc: 2303 movs r3, #3 + 80094fe: 73fb strb r3, [r7, #15] + 8009500: 7bfb ldrb r3, [r7, #15] + 8009502: 4618 mov r0, r3 + 8009504: 3710 adds r7, #16 + 8009506: 46bd mov sp, r7 + 8009508: bd80 pop {r7, pc} + +0800950a : + 800950a: b580 push {r7, lr} + 800950c: b084 sub sp, #16 + 800950e: af00 add r7, sp, #0 + 8009510: 6078 str r0, [r7, #4] + 8009512: 6039 str r1, [r7, #0] + 8009514: 687b ldr r3, [r7, #4] + 8009516: f203 23aa addw r3, r3, #682 @ 0x2aa + 800951a: 6839 ldr r1, [r7, #0] + 800951c: 4618 mov r0, r3 + 800951e: f001 f94c bl 800a7ba + 8009522: 687b ldr r3, [r7, #4] + 8009524: 2201 movs r2, #1 + 8009526: f8c3 2294 str.w r2, [r3, #660] @ 0x294 + 800952a: 687b ldr r3, [r7, #4] + 800952c: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 + 8009530: 461a mov r2, r3 + 8009532: 687b ldr r3, [r7, #4] + 8009534: f8c3 2298 str.w r2, [r3, #664] @ 0x298 + 8009538: 687b ldr r3, [r7, #4] + 800953a: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa + 800953e: f003 031f and.w r3, r3, #31 + 8009542: 2b02 cmp r3, #2 + 8009544: d01a beq.n 800957c + 8009546: 2b02 cmp r3, #2 + 8009548: d822 bhi.n 8009590 + 800954a: 2b00 cmp r3, #0 + 800954c: d002 beq.n 8009554 + 800954e: 2b01 cmp r3, #1 + 8009550: d00a beq.n 8009568 + 8009552: e01d b.n 8009590 + 8009554: 687b ldr r3, [r7, #4] + 8009556: f203 23aa addw r3, r3, #682 @ 0x2aa + 800955a: 4619 mov r1, r3 + 800955c: 6878 ldr r0, [r7, #4] + 800955e: f000 fb77 bl 8009c50 + 8009562: 4603 mov r3, r0 + 8009564: 73fb strb r3, [r7, #15] + 8009566: e020 b.n 80095aa + 8009568: 687b ldr r3, [r7, #4] + 800956a: f203 23aa addw r3, r3, #682 @ 0x2aa + 800956e: 4619 mov r1, r3 + 8009570: 6878 ldr r0, [r7, #4] + 8009572: f000 fbdf bl 8009d34 + 8009576: 4603 mov r3, r0 + 8009578: 73fb strb r3, [r7, #15] + 800957a: e016 b.n 80095aa + 800957c: 687b ldr r3, [r7, #4] + 800957e: f203 23aa addw r3, r3, #682 @ 0x2aa + 8009582: 4619 mov r1, r3 + 8009584: 6878 ldr r0, [r7, #4] + 8009586: f000 fc41 bl 8009e0c + 800958a: 4603 mov r3, r0 + 800958c: 73fb strb r3, [r7, #15] + 800958e: e00c b.n 80095aa + 8009590: 687b ldr r3, [r7, #4] + 8009592: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa + 8009596: f023 037f bic.w r3, r3, #127 @ 0x7f + 800959a: b2db uxtb r3, r3 + 800959c: 4619 mov r1, r3 + 800959e: 6878 ldr r0, [r7, #4] + 80095a0: f001 fd78 bl 800b094 + 80095a4: 4603 mov r3, r0 + 80095a6: 73fb strb r3, [r7, #15] + 80095a8: bf00 nop + 80095aa: 7bfb ldrb r3, [r7, #15] + 80095ac: 4618 mov r0, r3 + 80095ae: 3710 adds r7, #16 + 80095b0: 46bd mov sp, r7 + 80095b2: bd80 pop {r7, pc} + +080095b4 : + 80095b4: b580 push {r7, lr} + 80095b6: b086 sub sp, #24 + 80095b8: af00 add r7, sp, #0 + 80095ba: 60f8 str r0, [r7, #12] + 80095bc: 460b mov r3, r1 + 80095be: 607a str r2, [r7, #4] + 80095c0: 72fb strb r3, [r7, #11] + 80095c2: 2300 movs r3, #0 + 80095c4: 75fb strb r3, [r7, #23] + 80095c6: 7afb ldrb r3, [r7, #11] + 80095c8: 2b00 cmp r3, #0 + 80095ca: d177 bne.n 80096bc + 80095cc: 68fb ldr r3, [r7, #12] + 80095ce: f503 73aa add.w r3, r3, #340 @ 0x154 + 80095d2: 613b str r3, [r7, #16] + 80095d4: 68fb ldr r3, [r7, #12] + 80095d6: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 + 80095da: 2b03 cmp r3, #3 + 80095dc: f040 80a1 bne.w 8009722 + 80095e0: 693b ldr r3, [r7, #16] + 80095e2: 685b ldr r3, [r3, #4] + 80095e4: 693a ldr r2, [r7, #16] + 80095e6: 8992 ldrh r2, [r2, #12] + 80095e8: 4293 cmp r3, r2 + 80095ea: d91c bls.n 8009626 + 80095ec: 693b ldr r3, [r7, #16] + 80095ee: 685b ldr r3, [r3, #4] + 80095f0: 693a ldr r2, [r7, #16] + 80095f2: 8992 ldrh r2, [r2, #12] + 80095f4: 1a9a subs r2, r3, r2 + 80095f6: 693b ldr r3, [r7, #16] + 80095f8: 605a str r2, [r3, #4] + 80095fa: 693b ldr r3, [r7, #16] + 80095fc: 691b ldr r3, [r3, #16] + 80095fe: 693a ldr r2, [r7, #16] + 8009600: 8992 ldrh r2, [r2, #12] + 8009602: 441a add r2, r3 + 8009604: 693b ldr r3, [r7, #16] + 8009606: 611a str r2, [r3, #16] + 8009608: 693b ldr r3, [r7, #16] + 800960a: 6919 ldr r1, [r3, #16] + 800960c: 693b ldr r3, [r7, #16] + 800960e: 899b ldrh r3, [r3, #12] + 8009610: 461a mov r2, r3 + 8009612: 693b ldr r3, [r7, #16] + 8009614: 685b ldr r3, [r3, #4] + 8009616: 4293 cmp r3, r2 + 8009618: bf38 it cc + 800961a: 4613 movcc r3, r2 + 800961c: 461a mov r2, r3 + 800961e: 68f8 ldr r0, [r7, #12] + 8009620: f001 f9b1 bl 800a986 + 8009624: e07d b.n 8009722 + 8009626: 68fb ldr r3, [r7, #12] + 8009628: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa + 800962c: f003 031f and.w r3, r3, #31 + 8009630: 2b02 cmp r3, #2 + 8009632: d014 beq.n 800965e + 8009634: 2b02 cmp r3, #2 + 8009636: d81d bhi.n 8009674 + 8009638: 2b00 cmp r3, #0 + 800963a: d002 beq.n 8009642 + 800963c: 2b01 cmp r3, #1 + 800963e: d003 beq.n 8009648 + 8009640: e018 b.n 8009674 + 8009642: 2300 movs r3, #0 + 8009644: 75bb strb r3, [r7, #22] + 8009646: e018 b.n 800967a + 8009648: 68fb ldr r3, [r7, #12] + 800964a: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae + 800964e: b2db uxtb r3, r3 + 8009650: 4619 mov r1, r3 + 8009652: 68f8 ldr r0, [r7, #12] + 8009654: f000 fa6e bl 8009b34 + 8009658: 4603 mov r3, r0 + 800965a: 75bb strb r3, [r7, #22] + 800965c: e00d b.n 800967a + 800965e: 68fb ldr r3, [r7, #12] + 8009660: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae + 8009664: b2db uxtb r3, r3 + 8009666: 4619 mov r1, r3 + 8009668: 68f8 ldr r0, [r7, #12] + 800966a: f000 fa70 bl 8009b4e + 800966e: 4603 mov r3, r0 + 8009670: 75bb strb r3, [r7, #22] + 8009672: e002 b.n 800967a + 8009674: 2300 movs r3, #0 + 8009676: 75bb strb r3, [r7, #22] + 8009678: bf00 nop + 800967a: 7dbb ldrb r3, [r7, #22] + 800967c: 2b00 cmp r3, #0 + 800967e: d119 bne.n 80096b4 + 8009680: 68fb ldr r3, [r7, #12] + 8009682: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8009686: b2db uxtb r3, r3 + 8009688: 2b03 cmp r3, #3 + 800968a: d113 bne.n 80096b4 + 800968c: 7dba ldrb r2, [r7, #22] + 800968e: 68fb ldr r3, [r7, #12] + 8009690: 32ae adds r2, #174 @ 0xae + 8009692: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009696: 691b ldr r3, [r3, #16] + 8009698: 2b00 cmp r3, #0 + 800969a: d00b beq.n 80096b4 + 800969c: 7dba ldrb r2, [r7, #22] + 800969e: 68fb ldr r3, [r7, #12] + 80096a0: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 + 80096a4: 7dba ldrb r2, [r7, #22] + 80096a6: 68fb ldr r3, [r7, #12] + 80096a8: 32ae adds r2, #174 @ 0xae + 80096aa: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80096ae: 691b ldr r3, [r3, #16] + 80096b0: 68f8 ldr r0, [r7, #12] + 80096b2: 4798 blx r3 + 80096b4: 68f8 ldr r0, [r7, #12] + 80096b6: f001 f977 bl 800a9a8 + 80096ba: e032 b.n 8009722 + 80096bc: 7afb ldrb r3, [r7, #11] + 80096be: f003 037f and.w r3, r3, #127 @ 0x7f + 80096c2: b2db uxtb r3, r3 + 80096c4: 4619 mov r1, r3 + 80096c6: 68f8 ldr r0, [r7, #12] + 80096c8: f000 fa41 bl 8009b4e + 80096cc: 4603 mov r3, r0 + 80096ce: 75bb strb r3, [r7, #22] + 80096d0: 7dbb ldrb r3, [r7, #22] + 80096d2: 2bff cmp r3, #255 @ 0xff + 80096d4: d025 beq.n 8009722 + 80096d6: 7dbb ldrb r3, [r7, #22] + 80096d8: 2b00 cmp r3, #0 + 80096da: d122 bne.n 8009722 + 80096dc: 68fb ldr r3, [r7, #12] + 80096de: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 80096e2: b2db uxtb r3, r3 + 80096e4: 2b03 cmp r3, #3 + 80096e6: d117 bne.n 8009718 + 80096e8: 7dba ldrb r2, [r7, #22] + 80096ea: 68fb ldr r3, [r7, #12] + 80096ec: 32ae adds r2, #174 @ 0xae + 80096ee: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80096f2: 699b ldr r3, [r3, #24] + 80096f4: 2b00 cmp r3, #0 + 80096f6: d00f beq.n 8009718 + 80096f8: 7dba ldrb r2, [r7, #22] + 80096fa: 68fb ldr r3, [r7, #12] + 80096fc: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 + 8009700: 7dba ldrb r2, [r7, #22] + 8009702: 68fb ldr r3, [r7, #12] + 8009704: 32ae adds r2, #174 @ 0xae + 8009706: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800970a: 699b ldr r3, [r3, #24] + 800970c: 7afa ldrb r2, [r7, #11] + 800970e: 4611 mov r1, r2 + 8009710: 68f8 ldr r0, [r7, #12] + 8009712: 4798 blx r3 + 8009714: 4603 mov r3, r0 + 8009716: 75fb strb r3, [r7, #23] + 8009718: 7dfb ldrb r3, [r7, #23] + 800971a: 2b00 cmp r3, #0 + 800971c: d001 beq.n 8009722 + 800971e: 7dfb ldrb r3, [r7, #23] + 8009720: e000 b.n 8009724 + 8009722: 2300 movs r3, #0 + 8009724: 4618 mov r0, r3 + 8009726: 3718 adds r7, #24 + 8009728: 46bd mov sp, r7 + 800972a: bd80 pop {r7, pc} + +0800972c : + 800972c: b580 push {r7, lr} + 800972e: b086 sub sp, #24 + 8009730: af00 add r7, sp, #0 + 8009732: 60f8 str r0, [r7, #12] + 8009734: 460b mov r3, r1 + 8009736: 607a str r2, [r7, #4] + 8009738: 72fb strb r3, [r7, #11] + 800973a: 7afb ldrb r3, [r7, #11] + 800973c: 2b00 cmp r3, #0 + 800973e: d178 bne.n 8009832 + 8009740: 68fb ldr r3, [r7, #12] + 8009742: 3314 adds r3, #20 + 8009744: 613b str r3, [r7, #16] + 8009746: 68fb ldr r3, [r7, #12] + 8009748: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 + 800974c: 2b02 cmp r3, #2 + 800974e: d163 bne.n 8009818 + 8009750: 693b ldr r3, [r7, #16] + 8009752: 685b ldr r3, [r3, #4] + 8009754: 693a ldr r2, [r7, #16] + 8009756: 8992 ldrh r2, [r2, #12] + 8009758: 4293 cmp r3, r2 + 800975a: d91c bls.n 8009796 + 800975c: 693b ldr r3, [r7, #16] + 800975e: 685b ldr r3, [r3, #4] + 8009760: 693a ldr r2, [r7, #16] + 8009762: 8992 ldrh r2, [r2, #12] + 8009764: 1a9a subs r2, r3, r2 + 8009766: 693b ldr r3, [r7, #16] + 8009768: 605a str r2, [r3, #4] + 800976a: 693b ldr r3, [r7, #16] + 800976c: 691b ldr r3, [r3, #16] + 800976e: 693a ldr r2, [r7, #16] + 8009770: 8992 ldrh r2, [r2, #12] + 8009772: 441a add r2, r3 + 8009774: 693b ldr r3, [r7, #16] + 8009776: 611a str r2, [r3, #16] + 8009778: 693b ldr r3, [r7, #16] + 800977a: 6919 ldr r1, [r3, #16] + 800977c: 693b ldr r3, [r7, #16] + 800977e: 685b ldr r3, [r3, #4] + 8009780: 461a mov r2, r3 + 8009782: 68f8 ldr r0, [r7, #12] + 8009784: f001 f8ee bl 800a964 + 8009788: 2300 movs r3, #0 + 800978a: 2200 movs r2, #0 + 800978c: 2100 movs r1, #0 + 800978e: 68f8 ldr r0, [r7, #12] + 8009790: f001 fd2a bl 800b1e8 + 8009794: e040 b.n 8009818 + 8009796: 693b ldr r3, [r7, #16] + 8009798: 899b ldrh r3, [r3, #12] + 800979a: 461a mov r2, r3 + 800979c: 693b ldr r3, [r7, #16] + 800979e: 685b ldr r3, [r3, #4] + 80097a0: 429a cmp r2, r3 + 80097a2: d11c bne.n 80097de + 80097a4: 693b ldr r3, [r7, #16] + 80097a6: 681b ldr r3, [r3, #0] + 80097a8: 693a ldr r2, [r7, #16] + 80097aa: 8992 ldrh r2, [r2, #12] + 80097ac: 4293 cmp r3, r2 + 80097ae: d316 bcc.n 80097de + 80097b0: 693b ldr r3, [r7, #16] + 80097b2: 681a ldr r2, [r3, #0] + 80097b4: 68fb ldr r3, [r7, #12] + 80097b6: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 + 80097ba: 429a cmp r2, r3 + 80097bc: d20f bcs.n 80097de + 80097be: 2200 movs r2, #0 + 80097c0: 2100 movs r1, #0 + 80097c2: 68f8 ldr r0, [r7, #12] + 80097c4: f001 f8ce bl 800a964 + 80097c8: 68fb ldr r3, [r7, #12] + 80097ca: 2200 movs r2, #0 + 80097cc: f8c3 2298 str.w r2, [r3, #664] @ 0x298 + 80097d0: 2300 movs r3, #0 + 80097d2: 2200 movs r2, #0 + 80097d4: 2100 movs r1, #0 + 80097d6: 68f8 ldr r0, [r7, #12] + 80097d8: f001 fd06 bl 800b1e8 + 80097dc: e01c b.n 8009818 + 80097de: 68fb ldr r3, [r7, #12] + 80097e0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 80097e4: b2db uxtb r3, r3 + 80097e6: 2b03 cmp r3, #3 + 80097e8: d10f bne.n 800980a + 80097ea: 68fb ldr r3, [r7, #12] + 80097ec: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 80097f0: 68db ldr r3, [r3, #12] + 80097f2: 2b00 cmp r3, #0 + 80097f4: d009 beq.n 800980a + 80097f6: 68fb ldr r3, [r7, #12] + 80097f8: 2200 movs r2, #0 + 80097fa: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 + 80097fe: 68fb ldr r3, [r7, #12] + 8009800: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 8009804: 68db ldr r3, [r3, #12] + 8009806: 68f8 ldr r0, [r7, #12] + 8009808: 4798 blx r3 + 800980a: 2180 movs r1, #128 @ 0x80 + 800980c: 68f8 ldr r0, [r7, #12] + 800980e: f001 fc41 bl 800b094 + 8009812: 68f8 ldr r0, [r7, #12] + 8009814: f001 f8db bl 800a9ce + 8009818: 68fb ldr r3, [r7, #12] + 800981a: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 + 800981e: 2b00 cmp r3, #0 + 8009820: d03a beq.n 8009898 + 8009822: 68f8 ldr r0, [r7, #12] + 8009824: f7ff fe30 bl 8009488 + 8009828: 68fb ldr r3, [r7, #12] + 800982a: 2200 movs r2, #0 + 800982c: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 + 8009830: e032 b.n 8009898 + 8009832: 7afb ldrb r3, [r7, #11] + 8009834: f063 037f orn r3, r3, #127 @ 0x7f + 8009838: b2db uxtb r3, r3 + 800983a: 4619 mov r1, r3 + 800983c: 68f8 ldr r0, [r7, #12] + 800983e: f000 f986 bl 8009b4e + 8009842: 4603 mov r3, r0 + 8009844: 75fb strb r3, [r7, #23] + 8009846: 7dfb ldrb r3, [r7, #23] + 8009848: 2bff cmp r3, #255 @ 0xff + 800984a: d025 beq.n 8009898 + 800984c: 7dfb ldrb r3, [r7, #23] + 800984e: 2b00 cmp r3, #0 + 8009850: d122 bne.n 8009898 + 8009852: 68fb ldr r3, [r7, #12] + 8009854: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8009858: b2db uxtb r3, r3 + 800985a: 2b03 cmp r3, #3 + 800985c: d11c bne.n 8009898 + 800985e: 7dfa ldrb r2, [r7, #23] + 8009860: 68fb ldr r3, [r7, #12] + 8009862: 32ae adds r2, #174 @ 0xae + 8009864: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009868: 695b ldr r3, [r3, #20] + 800986a: 2b00 cmp r3, #0 + 800986c: d014 beq.n 8009898 + 800986e: 7dfa ldrb r2, [r7, #23] + 8009870: 68fb ldr r3, [r7, #12] + 8009872: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 + 8009876: 7dfa ldrb r2, [r7, #23] + 8009878: 68fb ldr r3, [r7, #12] + 800987a: 32ae adds r2, #174 @ 0xae + 800987c: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009880: 695b ldr r3, [r3, #20] + 8009882: 7afa ldrb r2, [r7, #11] + 8009884: 4611 mov r1, r2 + 8009886: 68f8 ldr r0, [r7, #12] + 8009888: 4798 blx r3 + 800988a: 4603 mov r3, r0 + 800988c: 75bb strb r3, [r7, #22] + 800988e: 7dbb ldrb r3, [r7, #22] + 8009890: 2b00 cmp r3, #0 + 8009892: d001 beq.n 8009898 + 8009894: 7dbb ldrb r3, [r7, #22] + 8009896: e000 b.n 800989a + 8009898: 2300 movs r3, #0 + 800989a: 4618 mov r0, r3 + 800989c: 3718 adds r7, #24 + 800989e: 46bd mov sp, r7 + 80098a0: bd80 pop {r7, pc} + +080098a2 : + 80098a2: b580 push {r7, lr} + 80098a4: b084 sub sp, #16 + 80098a6: af00 add r7, sp, #0 + 80098a8: 6078 str r0, [r7, #4] + 80098aa: 2300 movs r3, #0 + 80098ac: 73fb strb r3, [r7, #15] + 80098ae: 687b ldr r3, [r7, #4] + 80098b0: 2201 movs r2, #1 + 80098b2: f883 229c strb.w r2, [r3, #668] @ 0x29c + 80098b6: 687b ldr r3, [r7, #4] + 80098b8: 2200 movs r2, #0 + 80098ba: f8c3 2294 str.w r2, [r3, #660] @ 0x294 + 80098be: 687b ldr r3, [r7, #4] + 80098c0: 2200 movs r2, #0 + 80098c2: 605a str r2, [r3, #4] + 80098c4: 687b ldr r3, [r7, #4] + 80098c6: 2200 movs r2, #0 + 80098c8: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 + 80098cc: 687b ldr r3, [r7, #4] + 80098ce: 2200 movs r2, #0 + 80098d0: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 + 80098d4: 687b ldr r3, [r7, #4] + 80098d6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 80098da: 2b00 cmp r3, #0 + 80098dc: d014 beq.n 8009908 + 80098de: 687b ldr r3, [r7, #4] + 80098e0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 80098e4: 685b ldr r3, [r3, #4] + 80098e6: 2b00 cmp r3, #0 + 80098e8: d00e beq.n 8009908 + 80098ea: 687b ldr r3, [r7, #4] + 80098ec: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 80098f0: 685b ldr r3, [r3, #4] + 80098f2: 687a ldr r2, [r7, #4] + 80098f4: 6852 ldr r2, [r2, #4] + 80098f6: b2d2 uxtb r2, r2 + 80098f8: 4611 mov r1, r2 + 80098fa: 6878 ldr r0, [r7, #4] + 80098fc: 4798 blx r3 + 80098fe: 4603 mov r3, r0 + 8009900: 2b00 cmp r3, #0 + 8009902: d001 beq.n 8009908 + 8009904: 2303 movs r3, #3 + 8009906: 73fb strb r3, [r7, #15] + 8009908: 2340 movs r3, #64 @ 0x40 + 800990a: 2200 movs r2, #0 + 800990c: 2100 movs r1, #0 + 800990e: 6878 ldr r0, [r7, #4] + 8009910: f001 fb7b bl 800b00a + 8009914: 687b ldr r3, [r7, #4] + 8009916: 2201 movs r2, #1 + 8009918: f883 2163 strb.w r2, [r3, #355] @ 0x163 + 800991c: 687b ldr r3, [r7, #4] + 800991e: 2240 movs r2, #64 @ 0x40 + 8009920: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 + 8009924: 2340 movs r3, #64 @ 0x40 + 8009926: 2200 movs r2, #0 + 8009928: 2180 movs r1, #128 @ 0x80 + 800992a: 6878 ldr r0, [r7, #4] + 800992c: f001 fb6d bl 800b00a + 8009930: 687b ldr r3, [r7, #4] + 8009932: 2201 movs r2, #1 + 8009934: f883 2023 strb.w r2, [r3, #35] @ 0x23 + 8009938: 687b ldr r3, [r7, #4] + 800993a: 2240 movs r2, #64 @ 0x40 + 800993c: 841a strh r2, [r3, #32] + 800993e: 7bfb ldrb r3, [r7, #15] + 8009940: 4618 mov r0, r3 + 8009942: 3710 adds r7, #16 + 8009944: 46bd mov sp, r7 + 8009946: bd80 pop {r7, pc} + +08009948 : + 8009948: b480 push {r7} + 800994a: b083 sub sp, #12 + 800994c: af00 add r7, sp, #0 + 800994e: 6078 str r0, [r7, #4] + 8009950: 460b mov r3, r1 + 8009952: 70fb strb r3, [r7, #3] + 8009954: 687b ldr r3, [r7, #4] + 8009956: 78fa ldrb r2, [r7, #3] + 8009958: 741a strb r2, [r3, #16] + 800995a: 2300 movs r3, #0 + 800995c: 4618 mov r0, r3 + 800995e: 370c adds r7, #12 + 8009960: 46bd mov sp, r7 + 8009962: f85d 7b04 ldr.w r7, [sp], #4 + 8009966: 4770 bx lr + +08009968 : + 8009968: b480 push {r7} + 800996a: b083 sub sp, #12 + 800996c: af00 add r7, sp, #0 + 800996e: 6078 str r0, [r7, #4] + 8009970: 687b ldr r3, [r7, #4] + 8009972: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8009976: b2db uxtb r3, r3 + 8009978: 2b04 cmp r3, #4 + 800997a: d006 beq.n 800998a + 800997c: 687b ldr r3, [r7, #4] + 800997e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8009982: b2da uxtb r2, r3 + 8009984: 687b ldr r3, [r7, #4] + 8009986: f883 229d strb.w r2, [r3, #669] @ 0x29d + 800998a: 687b ldr r3, [r7, #4] + 800998c: 2204 movs r2, #4 + 800998e: f883 229c strb.w r2, [r3, #668] @ 0x29c + 8009992: 2300 movs r3, #0 + 8009994: 4618 mov r0, r3 + 8009996: 370c adds r7, #12 + 8009998: 46bd mov sp, r7 + 800999a: f85d 7b04 ldr.w r7, [sp], #4 + 800999e: 4770 bx lr + +080099a0 : + 80099a0: b480 push {r7} + 80099a2: b083 sub sp, #12 + 80099a4: af00 add r7, sp, #0 + 80099a6: 6078 str r0, [r7, #4] + 80099a8: 687b ldr r3, [r7, #4] + 80099aa: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 80099ae: b2db uxtb r3, r3 + 80099b0: 2b04 cmp r3, #4 + 80099b2: d106 bne.n 80099c2 + 80099b4: 687b ldr r3, [r7, #4] + 80099b6: f893 329d ldrb.w r3, [r3, #669] @ 0x29d + 80099ba: b2da uxtb r2, r3 + 80099bc: 687b ldr r3, [r7, #4] + 80099be: f883 229c strb.w r2, [r3, #668] @ 0x29c + 80099c2: 2300 movs r3, #0 + 80099c4: 4618 mov r0, r3 + 80099c6: 370c adds r7, #12 + 80099c8: 46bd mov sp, r7 + 80099ca: f85d 7b04 ldr.w r7, [sp], #4 + 80099ce: 4770 bx lr + +080099d0 : + 80099d0: b580 push {r7, lr} + 80099d2: b082 sub sp, #8 + 80099d4: af00 add r7, sp, #0 + 80099d6: 6078 str r0, [r7, #4] + 80099d8: 687b ldr r3, [r7, #4] + 80099da: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 80099de: b2db uxtb r3, r3 + 80099e0: 2b03 cmp r3, #3 + 80099e2: d110 bne.n 8009a06 + 80099e4: 687b ldr r3, [r7, #4] + 80099e6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 80099ea: 2b00 cmp r3, #0 + 80099ec: d00b beq.n 8009a06 + 80099ee: 687b ldr r3, [r7, #4] + 80099f0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 80099f4: 69db ldr r3, [r3, #28] + 80099f6: 2b00 cmp r3, #0 + 80099f8: d005 beq.n 8009a06 + 80099fa: 687b ldr r3, [r7, #4] + 80099fc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 8009a00: 69db ldr r3, [r3, #28] + 8009a02: 6878 ldr r0, [r7, #4] + 8009a04: 4798 blx r3 + 8009a06: 2300 movs r3, #0 + 8009a08: 4618 mov r0, r3 + 8009a0a: 3708 adds r7, #8 + 8009a0c: 46bd mov sp, r7 + 8009a0e: bd80 pop {r7, pc} + +08009a10 : + 8009a10: b580 push {r7, lr} + 8009a12: b082 sub sp, #8 + 8009a14: af00 add r7, sp, #0 + 8009a16: 6078 str r0, [r7, #4] + 8009a18: 460b mov r3, r1 + 8009a1a: 70fb strb r3, [r7, #3] + 8009a1c: 687b ldr r3, [r7, #4] + 8009a1e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8009a22: 687b ldr r3, [r7, #4] + 8009a24: 32ae adds r2, #174 @ 0xae + 8009a26: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009a2a: 2b00 cmp r3, #0 + 8009a2c: d101 bne.n 8009a32 + 8009a2e: 2303 movs r3, #3 + 8009a30: e01c b.n 8009a6c + 8009a32: 687b ldr r3, [r7, #4] + 8009a34: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8009a38: b2db uxtb r3, r3 + 8009a3a: 2b03 cmp r3, #3 + 8009a3c: d115 bne.n 8009a6a + 8009a3e: 687b ldr r3, [r7, #4] + 8009a40: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8009a44: 687b ldr r3, [r7, #4] + 8009a46: 32ae adds r2, #174 @ 0xae + 8009a48: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009a4c: 6a1b ldr r3, [r3, #32] + 8009a4e: 2b00 cmp r3, #0 + 8009a50: d00b beq.n 8009a6a + 8009a52: 687b ldr r3, [r7, #4] + 8009a54: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8009a58: 687b ldr r3, [r7, #4] + 8009a5a: 32ae adds r2, #174 @ 0xae + 8009a5c: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009a60: 6a1b ldr r3, [r3, #32] + 8009a62: 78fa ldrb r2, [r7, #3] + 8009a64: 4611 mov r1, r2 + 8009a66: 6878 ldr r0, [r7, #4] + 8009a68: 4798 blx r3 + 8009a6a: 2300 movs r3, #0 + 8009a6c: 4618 mov r0, r3 + 8009a6e: 3708 adds r7, #8 + 8009a70: 46bd mov sp, r7 + 8009a72: bd80 pop {r7, pc} + +08009a74 : + 8009a74: b580 push {r7, lr} + 8009a76: b082 sub sp, #8 + 8009a78: af00 add r7, sp, #0 + 8009a7a: 6078 str r0, [r7, #4] + 8009a7c: 460b mov r3, r1 + 8009a7e: 70fb strb r3, [r7, #3] + 8009a80: 687b ldr r3, [r7, #4] + 8009a82: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8009a86: 687b ldr r3, [r7, #4] + 8009a88: 32ae adds r2, #174 @ 0xae + 8009a8a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009a8e: 2b00 cmp r3, #0 + 8009a90: d101 bne.n 8009a96 + 8009a92: 2303 movs r3, #3 + 8009a94: e01c b.n 8009ad0 + 8009a96: 687b ldr r3, [r7, #4] + 8009a98: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8009a9c: b2db uxtb r3, r3 + 8009a9e: 2b03 cmp r3, #3 + 8009aa0: d115 bne.n 8009ace + 8009aa2: 687b ldr r3, [r7, #4] + 8009aa4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8009aa8: 687b ldr r3, [r7, #4] + 8009aaa: 32ae adds r2, #174 @ 0xae + 8009aac: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009ab0: 6a5b ldr r3, [r3, #36] @ 0x24 + 8009ab2: 2b00 cmp r3, #0 + 8009ab4: d00b beq.n 8009ace + 8009ab6: 687b ldr r3, [r7, #4] + 8009ab8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8009abc: 687b ldr r3, [r7, #4] + 8009abe: 32ae adds r2, #174 @ 0xae + 8009ac0: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009ac4: 6a5b ldr r3, [r3, #36] @ 0x24 + 8009ac6: 78fa ldrb r2, [r7, #3] + 8009ac8: 4611 mov r1, r2 + 8009aca: 6878 ldr r0, [r7, #4] + 8009acc: 4798 blx r3 + 8009ace: 2300 movs r3, #0 + 8009ad0: 4618 mov r0, r3 + 8009ad2: 3708 adds r7, #8 + 8009ad4: 46bd mov sp, r7 + 8009ad6: bd80 pop {r7, pc} + +08009ad8 : + 8009ad8: b480 push {r7} + 8009ada: b083 sub sp, #12 + 8009adc: af00 add r7, sp, #0 + 8009ade: 6078 str r0, [r7, #4] + 8009ae0: 2300 movs r3, #0 + 8009ae2: 4618 mov r0, r3 + 8009ae4: 370c adds r7, #12 + 8009ae6: 46bd mov sp, r7 + 8009ae8: f85d 7b04 ldr.w r7, [sp], #4 + 8009aec: 4770 bx lr + +08009aee : + 8009aee: b580 push {r7, lr} + 8009af0: b084 sub sp, #16 + 8009af2: af00 add r7, sp, #0 + 8009af4: 6078 str r0, [r7, #4] + 8009af6: 2300 movs r3, #0 + 8009af8: 73fb strb r3, [r7, #15] + 8009afa: 687b ldr r3, [r7, #4] + 8009afc: 2201 movs r2, #1 + 8009afe: f883 229c strb.w r2, [r3, #668] @ 0x29c + 8009b02: 687b ldr r3, [r7, #4] + 8009b04: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 8009b08: 2b00 cmp r3, #0 + 8009b0a: d00e beq.n 8009b2a + 8009b0c: 687b ldr r3, [r7, #4] + 8009b0e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 8009b12: 685b ldr r3, [r3, #4] + 8009b14: 687a ldr r2, [r7, #4] + 8009b16: 6852 ldr r2, [r2, #4] + 8009b18: b2d2 uxtb r2, r2 + 8009b1a: 4611 mov r1, r2 + 8009b1c: 6878 ldr r0, [r7, #4] + 8009b1e: 4798 blx r3 + 8009b20: 4603 mov r3, r0 + 8009b22: 2b00 cmp r3, #0 + 8009b24: d001 beq.n 8009b2a + 8009b26: 2303 movs r3, #3 + 8009b28: 73fb strb r3, [r7, #15] + 8009b2a: 7bfb ldrb r3, [r7, #15] + 8009b2c: 4618 mov r0, r3 + 8009b2e: 3710 adds r7, #16 + 8009b30: 46bd mov sp, r7 + 8009b32: bd80 pop {r7, pc} + +08009b34 : + 8009b34: b480 push {r7} + 8009b36: b083 sub sp, #12 + 8009b38: af00 add r7, sp, #0 + 8009b3a: 6078 str r0, [r7, #4] + 8009b3c: 460b mov r3, r1 + 8009b3e: 70fb strb r3, [r7, #3] + 8009b40: 2300 movs r3, #0 + 8009b42: 4618 mov r0, r3 + 8009b44: 370c adds r7, #12 + 8009b46: 46bd mov sp, r7 + 8009b48: f85d 7b04 ldr.w r7, [sp], #4 + 8009b4c: 4770 bx lr + +08009b4e : + 8009b4e: b480 push {r7} + 8009b50: b083 sub sp, #12 + 8009b52: af00 add r7, sp, #0 + 8009b54: 6078 str r0, [r7, #4] + 8009b56: 460b mov r3, r1 + 8009b58: 70fb strb r3, [r7, #3] + 8009b5a: 2300 movs r3, #0 + 8009b5c: 4618 mov r0, r3 + 8009b5e: 370c adds r7, #12 + 8009b60: 46bd mov sp, r7 + 8009b62: f85d 7b04 ldr.w r7, [sp], #4 + 8009b66: 4770 bx lr + +08009b68 : + 8009b68: b580 push {r7, lr} + 8009b6a: b086 sub sp, #24 + 8009b6c: af00 add r7, sp, #0 + 8009b6e: 6078 str r0, [r7, #4] + 8009b70: 460b mov r3, r1 + 8009b72: 70fb strb r3, [r7, #3] + 8009b74: 687b ldr r3, [r7, #4] + 8009b76: 617b str r3, [r7, #20] + 8009b78: 687b ldr r3, [r7, #4] + 8009b7a: 60fb str r3, [r7, #12] + 8009b7c: 2300 movs r3, #0 + 8009b7e: 613b str r3, [r7, #16] + 8009b80: 68fb ldr r3, [r7, #12] + 8009b82: 885b ldrh r3, [r3, #2] + 8009b84: b29b uxth r3, r3 + 8009b86: 68fa ldr r2, [r7, #12] + 8009b88: 7812 ldrb r2, [r2, #0] + 8009b8a: 4293 cmp r3, r2 + 8009b8c: d91f bls.n 8009bce + 8009b8e: 68fb ldr r3, [r7, #12] + 8009b90: 781b ldrb r3, [r3, #0] + 8009b92: 817b strh r3, [r7, #10] + 8009b94: e013 b.n 8009bbe + 8009b96: f107 030a add.w r3, r7, #10 + 8009b9a: 4619 mov r1, r3 + 8009b9c: 6978 ldr r0, [r7, #20] + 8009b9e: f000 f81b bl 8009bd8 + 8009ba2: 6178 str r0, [r7, #20] + 8009ba4: 697b ldr r3, [r7, #20] + 8009ba6: 785b ldrb r3, [r3, #1] + 8009ba8: 2b05 cmp r3, #5 + 8009baa: d108 bne.n 8009bbe + 8009bac: 697b ldr r3, [r7, #20] + 8009bae: 613b str r3, [r7, #16] + 8009bb0: 693b ldr r3, [r7, #16] + 8009bb2: 789b ldrb r3, [r3, #2] + 8009bb4: 78fa ldrb r2, [r7, #3] + 8009bb6: 429a cmp r2, r3 + 8009bb8: d008 beq.n 8009bcc + 8009bba: 2300 movs r3, #0 + 8009bbc: 613b str r3, [r7, #16] + 8009bbe: 68fb ldr r3, [r7, #12] + 8009bc0: 885b ldrh r3, [r3, #2] + 8009bc2: b29a uxth r2, r3 + 8009bc4: 897b ldrh r3, [r7, #10] + 8009bc6: 429a cmp r2, r3 + 8009bc8: d8e5 bhi.n 8009b96 + 8009bca: e000 b.n 8009bce + 8009bcc: bf00 nop + 8009bce: 693b ldr r3, [r7, #16] + 8009bd0: 4618 mov r0, r3 + 8009bd2: 3718 adds r7, #24 + 8009bd4: 46bd mov sp, r7 + 8009bd6: bd80 pop {r7, pc} + +08009bd8 : + 8009bd8: b480 push {r7} + 8009bda: b085 sub sp, #20 + 8009bdc: af00 add r7, sp, #0 + 8009bde: 6078 str r0, [r7, #4] + 8009be0: 6039 str r1, [r7, #0] + 8009be2: 687b ldr r3, [r7, #4] + 8009be4: 60fb str r3, [r7, #12] + 8009be6: 683b ldr r3, [r7, #0] + 8009be8: 881b ldrh r3, [r3, #0] + 8009bea: 68fa ldr r2, [r7, #12] + 8009bec: 7812 ldrb r2, [r2, #0] + 8009bee: 4413 add r3, r2 + 8009bf0: b29a uxth r2, r3 + 8009bf2: 683b ldr r3, [r7, #0] + 8009bf4: 801a strh r2, [r3, #0] + 8009bf6: 68fb ldr r3, [r7, #12] + 8009bf8: 781b ldrb r3, [r3, #0] + 8009bfa: 461a mov r2, r3 + 8009bfc: 687b ldr r3, [r7, #4] + 8009bfe: 4413 add r3, r2 + 8009c00: 60fb str r3, [r7, #12] + 8009c02: 68fb ldr r3, [r7, #12] + 8009c04: 4618 mov r0, r3 + 8009c06: 3714 adds r7, #20 + 8009c08: 46bd mov sp, r7 + 8009c0a: f85d 7b04 ldr.w r7, [sp], #4 + 8009c0e: 4770 bx lr + +08009c10 : + 8009c10: b480 push {r7} + 8009c12: b087 sub sp, #28 + 8009c14: af00 add r7, sp, #0 + 8009c16: 6078 str r0, [r7, #4] + 8009c18: 687b ldr r3, [r7, #4] + 8009c1a: 617b str r3, [r7, #20] + 8009c1c: 697b ldr r3, [r7, #20] + 8009c1e: 781b ldrb r3, [r3, #0] + 8009c20: 827b strh r3, [r7, #18] + 8009c22: 697b ldr r3, [r7, #20] + 8009c24: 3301 adds r3, #1 + 8009c26: 617b str r3, [r7, #20] + 8009c28: 697b ldr r3, [r7, #20] + 8009c2a: 781b ldrb r3, [r3, #0] + 8009c2c: 823b strh r3, [r7, #16] + 8009c2e: f9b7 3010 ldrsh.w r3, [r7, #16] + 8009c32: 021b lsls r3, r3, #8 + 8009c34: b21a sxth r2, r3 + 8009c36: f9b7 3012 ldrsh.w r3, [r7, #18] + 8009c3a: 4313 orrs r3, r2 + 8009c3c: b21b sxth r3, r3 + 8009c3e: 81fb strh r3, [r7, #14] + 8009c40: 89fb ldrh r3, [r7, #14] + 8009c42: 4618 mov r0, r3 + 8009c44: 371c adds r7, #28 + 8009c46: 46bd mov sp, r7 + 8009c48: f85d 7b04 ldr.w r7, [sp], #4 + 8009c4c: 4770 bx lr + ... + +08009c50 : + 8009c50: b580 push {r7, lr} + 8009c52: b084 sub sp, #16 + 8009c54: af00 add r7, sp, #0 + 8009c56: 6078 str r0, [r7, #4] + 8009c58: 6039 str r1, [r7, #0] + 8009c5a: 2300 movs r3, #0 + 8009c5c: 73fb strb r3, [r7, #15] + 8009c5e: 683b ldr r3, [r7, #0] + 8009c60: 781b ldrb r3, [r3, #0] + 8009c62: f003 0360 and.w r3, r3, #96 @ 0x60 + 8009c66: 2b40 cmp r3, #64 @ 0x40 + 8009c68: d005 beq.n 8009c76 + 8009c6a: 2b40 cmp r3, #64 @ 0x40 + 8009c6c: d857 bhi.n 8009d1e + 8009c6e: 2b00 cmp r3, #0 + 8009c70: d00f beq.n 8009c92 + 8009c72: 2b20 cmp r3, #32 + 8009c74: d153 bne.n 8009d1e + 8009c76: 687b ldr r3, [r7, #4] + 8009c78: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 + 8009c7c: 687b ldr r3, [r7, #4] + 8009c7e: 32ae adds r2, #174 @ 0xae + 8009c80: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009c84: 689b ldr r3, [r3, #8] + 8009c86: 6839 ldr r1, [r7, #0] + 8009c88: 6878 ldr r0, [r7, #4] + 8009c8a: 4798 blx r3 + 8009c8c: 4603 mov r3, r0 + 8009c8e: 73fb strb r3, [r7, #15] + 8009c90: e04a b.n 8009d28 + 8009c92: 683b ldr r3, [r7, #0] + 8009c94: 785b ldrb r3, [r3, #1] + 8009c96: 2b09 cmp r3, #9 + 8009c98: d83b bhi.n 8009d12 + 8009c9a: a201 add r2, pc, #4 @ (adr r2, 8009ca0 ) + 8009c9c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009ca0: 08009cf5 .word 0x08009cf5 + 8009ca4: 08009d09 .word 0x08009d09 + 8009ca8: 08009d13 .word 0x08009d13 + 8009cac: 08009cff .word 0x08009cff + 8009cb0: 08009d13 .word 0x08009d13 + 8009cb4: 08009cd3 .word 0x08009cd3 + 8009cb8: 08009cc9 .word 0x08009cc9 + 8009cbc: 08009d13 .word 0x08009d13 + 8009cc0: 08009ceb .word 0x08009ceb + 8009cc4: 08009cdd .word 0x08009cdd + 8009cc8: 6839 ldr r1, [r7, #0] + 8009cca: 6878 ldr r0, [r7, #4] + 8009ccc: f000 fa3e bl 800a14c + 8009cd0: e024 b.n 8009d1c + 8009cd2: 6839 ldr r1, [r7, #0] + 8009cd4: 6878 ldr r0, [r7, #4] + 8009cd6: f000 fbcd bl 800a474 + 8009cda: e01f b.n 8009d1c + 8009cdc: 6839 ldr r1, [r7, #0] + 8009cde: 6878 ldr r0, [r7, #4] + 8009ce0: f000 fc0c bl 800a4fc + 8009ce4: 4603 mov r3, r0 + 8009ce6: 73fb strb r3, [r7, #15] + 8009ce8: e018 b.n 8009d1c + 8009cea: 6839 ldr r1, [r7, #0] + 8009cec: 6878 ldr r0, [r7, #4] + 8009cee: f000 fcaf bl 800a650 + 8009cf2: e013 b.n 8009d1c + 8009cf4: 6839 ldr r1, [r7, #0] + 8009cf6: 6878 ldr r0, [r7, #4] + 8009cf8: f000 fce0 bl 800a6bc + 8009cfc: e00e b.n 8009d1c + 8009cfe: 6839 ldr r1, [r7, #0] + 8009d00: 6878 ldr r0, [r7, #4] + 8009d02: f000 fd0f bl 800a724 + 8009d06: e009 b.n 8009d1c + 8009d08: 6839 ldr r1, [r7, #0] + 8009d0a: 6878 ldr r0, [r7, #4] + 8009d0c: f000 fd33 bl 800a776 + 8009d10: e004 b.n 8009d1c + 8009d12: 6839 ldr r1, [r7, #0] + 8009d14: 6878 ldr r0, [r7, #4] + 8009d16: f000 fd8a bl 800a82e + 8009d1a: bf00 nop + 8009d1c: e004 b.n 8009d28 + 8009d1e: 6839 ldr r1, [r7, #0] + 8009d20: 6878 ldr r0, [r7, #4] + 8009d22: f000 fd84 bl 800a82e + 8009d26: bf00 nop + 8009d28: 7bfb ldrb r3, [r7, #15] + 8009d2a: 4618 mov r0, r3 + 8009d2c: 3710 adds r7, #16 + 8009d2e: 46bd mov sp, r7 + 8009d30: bd80 pop {r7, pc} + 8009d32: bf00 nop + +08009d34 : + 8009d34: b580 push {r7, lr} + 8009d36: b084 sub sp, #16 + 8009d38: af00 add r7, sp, #0 + 8009d3a: 6078 str r0, [r7, #4] + 8009d3c: 6039 str r1, [r7, #0] + 8009d3e: 2300 movs r3, #0 + 8009d40: 73fb strb r3, [r7, #15] + 8009d42: 683b ldr r3, [r7, #0] + 8009d44: 781b ldrb r3, [r3, #0] + 8009d46: f003 0360 and.w r3, r3, #96 @ 0x60 + 8009d4a: 2b40 cmp r3, #64 @ 0x40 + 8009d4c: d005 beq.n 8009d5a + 8009d4e: 2b40 cmp r3, #64 @ 0x40 + 8009d50: d852 bhi.n 8009df8 + 8009d52: 2b00 cmp r3, #0 + 8009d54: d001 beq.n 8009d5a + 8009d56: 2b20 cmp r3, #32 + 8009d58: d14e bne.n 8009df8 + 8009d5a: 687b ldr r3, [r7, #4] + 8009d5c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8009d60: b2db uxtb r3, r3 + 8009d62: 3b01 subs r3, #1 + 8009d64: 2b02 cmp r3, #2 + 8009d66: d840 bhi.n 8009dea + 8009d68: 683b ldr r3, [r7, #0] + 8009d6a: 889b ldrh r3, [r3, #4] + 8009d6c: b2db uxtb r3, r3 + 8009d6e: 2b01 cmp r3, #1 + 8009d70: d836 bhi.n 8009de0 + 8009d72: 683b ldr r3, [r7, #0] + 8009d74: 889b ldrh r3, [r3, #4] + 8009d76: b2db uxtb r3, r3 + 8009d78: 4619 mov r1, r3 + 8009d7a: 6878 ldr r0, [r7, #4] + 8009d7c: f7ff feda bl 8009b34 + 8009d80: 4603 mov r3, r0 + 8009d82: 73bb strb r3, [r7, #14] + 8009d84: 7bbb ldrb r3, [r7, #14] + 8009d86: 2bff cmp r3, #255 @ 0xff + 8009d88: d01d beq.n 8009dc6 + 8009d8a: 7bbb ldrb r3, [r7, #14] + 8009d8c: 2b00 cmp r3, #0 + 8009d8e: d11a bne.n 8009dc6 + 8009d90: 7bba ldrb r2, [r7, #14] + 8009d92: 687b ldr r3, [r7, #4] + 8009d94: 32ae adds r2, #174 @ 0xae + 8009d96: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009d9a: 689b ldr r3, [r3, #8] + 8009d9c: 2b00 cmp r3, #0 + 8009d9e: d00f beq.n 8009dc0 + 8009da0: 7bba ldrb r2, [r7, #14] + 8009da2: 687b ldr r3, [r7, #4] + 8009da4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 + 8009da8: 7bba ldrb r2, [r7, #14] + 8009daa: 687b ldr r3, [r7, #4] + 8009dac: 32ae adds r2, #174 @ 0xae + 8009dae: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009db2: 689b ldr r3, [r3, #8] + 8009db4: 6839 ldr r1, [r7, #0] + 8009db6: 6878 ldr r0, [r7, #4] + 8009db8: 4798 blx r3 + 8009dba: 4603 mov r3, r0 + 8009dbc: 73fb strb r3, [r7, #15] + 8009dbe: e004 b.n 8009dca + 8009dc0: 2303 movs r3, #3 + 8009dc2: 73fb strb r3, [r7, #15] + 8009dc4: e001 b.n 8009dca + 8009dc6: 2303 movs r3, #3 + 8009dc8: 73fb strb r3, [r7, #15] + 8009dca: 683b ldr r3, [r7, #0] + 8009dcc: 88db ldrh r3, [r3, #6] + 8009dce: 2b00 cmp r3, #0 + 8009dd0: d110 bne.n 8009df4 + 8009dd2: 7bfb ldrb r3, [r7, #15] + 8009dd4: 2b00 cmp r3, #0 + 8009dd6: d10d bne.n 8009df4 + 8009dd8: 6878 ldr r0, [r7, #4] + 8009dda: f000 fde5 bl 800a9a8 + 8009dde: e009 b.n 8009df4 + 8009de0: 6839 ldr r1, [r7, #0] + 8009de2: 6878 ldr r0, [r7, #4] + 8009de4: f000 fd23 bl 800a82e + 8009de8: e004 b.n 8009df4 + 8009dea: 6839 ldr r1, [r7, #0] + 8009dec: 6878 ldr r0, [r7, #4] + 8009dee: f000 fd1e bl 800a82e + 8009df2: e000 b.n 8009df6 + 8009df4: bf00 nop + 8009df6: e004 b.n 8009e02 + 8009df8: 6839 ldr r1, [r7, #0] + 8009dfa: 6878 ldr r0, [r7, #4] + 8009dfc: f000 fd17 bl 800a82e + 8009e00: bf00 nop + 8009e02: 7bfb ldrb r3, [r7, #15] + 8009e04: 4618 mov r0, r3 + 8009e06: 3710 adds r7, #16 + 8009e08: 46bd mov sp, r7 + 8009e0a: bd80 pop {r7, pc} + +08009e0c : + 8009e0c: b580 push {r7, lr} + 8009e0e: b084 sub sp, #16 + 8009e10: af00 add r7, sp, #0 + 8009e12: 6078 str r0, [r7, #4] + 8009e14: 6039 str r1, [r7, #0] + 8009e16: 2300 movs r3, #0 + 8009e18: 73fb strb r3, [r7, #15] + 8009e1a: 683b ldr r3, [r7, #0] + 8009e1c: 889b ldrh r3, [r3, #4] + 8009e1e: 73bb strb r3, [r7, #14] + 8009e20: 683b ldr r3, [r7, #0] + 8009e22: 781b ldrb r3, [r3, #0] + 8009e24: f003 0360 and.w r3, r3, #96 @ 0x60 + 8009e28: 2b40 cmp r3, #64 @ 0x40 + 8009e2a: d007 beq.n 8009e3c + 8009e2c: 2b40 cmp r3, #64 @ 0x40 + 8009e2e: f200 8181 bhi.w 800a134 + 8009e32: 2b00 cmp r3, #0 + 8009e34: d02a beq.n 8009e8c + 8009e36: 2b20 cmp r3, #32 + 8009e38: f040 817c bne.w 800a134 + 8009e3c: 7bbb ldrb r3, [r7, #14] + 8009e3e: 4619 mov r1, r3 + 8009e40: 6878 ldr r0, [r7, #4] + 8009e42: f7ff fe84 bl 8009b4e + 8009e46: 4603 mov r3, r0 + 8009e48: 737b strb r3, [r7, #13] + 8009e4a: 7b7b ldrb r3, [r7, #13] + 8009e4c: 2bff cmp r3, #255 @ 0xff + 8009e4e: f000 8176 beq.w 800a13e + 8009e52: 7b7b ldrb r3, [r7, #13] + 8009e54: 2b00 cmp r3, #0 + 8009e56: f040 8172 bne.w 800a13e + 8009e5a: 7b7a ldrb r2, [r7, #13] + 8009e5c: 687b ldr r3, [r7, #4] + 8009e5e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 + 8009e62: 7b7a ldrb r2, [r7, #13] + 8009e64: 687b ldr r3, [r7, #4] + 8009e66: 32ae adds r2, #174 @ 0xae + 8009e68: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009e6c: 689b ldr r3, [r3, #8] + 8009e6e: 2b00 cmp r3, #0 + 8009e70: f000 8165 beq.w 800a13e + 8009e74: 7b7a ldrb r2, [r7, #13] + 8009e76: 687b ldr r3, [r7, #4] + 8009e78: 32ae adds r2, #174 @ 0xae + 8009e7a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009e7e: 689b ldr r3, [r3, #8] + 8009e80: 6839 ldr r1, [r7, #0] + 8009e82: 6878 ldr r0, [r7, #4] + 8009e84: 4798 blx r3 + 8009e86: 4603 mov r3, r0 + 8009e88: 73fb strb r3, [r7, #15] + 8009e8a: e158 b.n 800a13e + 8009e8c: 683b ldr r3, [r7, #0] + 8009e8e: 785b ldrb r3, [r3, #1] + 8009e90: 2b03 cmp r3, #3 + 8009e92: d008 beq.n 8009ea6 + 8009e94: 2b03 cmp r3, #3 + 8009e96: f300 8147 bgt.w 800a128 + 8009e9a: 2b00 cmp r3, #0 + 8009e9c: f000 809b beq.w 8009fd6 + 8009ea0: 2b01 cmp r3, #1 + 8009ea2: d03c beq.n 8009f1e + 8009ea4: e140 b.n 800a128 + 8009ea6: 687b ldr r3, [r7, #4] + 8009ea8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8009eac: b2db uxtb r3, r3 + 8009eae: 2b02 cmp r3, #2 + 8009eb0: d002 beq.n 8009eb8 + 8009eb2: 2b03 cmp r3, #3 + 8009eb4: d016 beq.n 8009ee4 + 8009eb6: e02c b.n 8009f12 + 8009eb8: 7bbb ldrb r3, [r7, #14] + 8009eba: 2b00 cmp r3, #0 + 8009ebc: d00d beq.n 8009eda + 8009ebe: 7bbb ldrb r3, [r7, #14] + 8009ec0: 2b80 cmp r3, #128 @ 0x80 + 8009ec2: d00a beq.n 8009eda + 8009ec4: 7bbb ldrb r3, [r7, #14] + 8009ec6: 4619 mov r1, r3 + 8009ec8: 6878 ldr r0, [r7, #4] + 8009eca: f001 f8e3 bl 800b094 + 8009ece: 2180 movs r1, #128 @ 0x80 + 8009ed0: 6878 ldr r0, [r7, #4] + 8009ed2: f001 f8df bl 800b094 + 8009ed6: bf00 nop + 8009ed8: e020 b.n 8009f1c + 8009eda: 6839 ldr r1, [r7, #0] + 8009edc: 6878 ldr r0, [r7, #4] + 8009ede: f000 fca6 bl 800a82e + 8009ee2: e01b b.n 8009f1c + 8009ee4: 683b ldr r3, [r7, #0] + 8009ee6: 885b ldrh r3, [r3, #2] + 8009ee8: 2b00 cmp r3, #0 + 8009eea: d10e bne.n 8009f0a + 8009eec: 7bbb ldrb r3, [r7, #14] + 8009eee: 2b00 cmp r3, #0 + 8009ef0: d00b beq.n 8009f0a + 8009ef2: 7bbb ldrb r3, [r7, #14] + 8009ef4: 2b80 cmp r3, #128 @ 0x80 + 8009ef6: d008 beq.n 8009f0a + 8009ef8: 683b ldr r3, [r7, #0] + 8009efa: 88db ldrh r3, [r3, #6] + 8009efc: 2b00 cmp r3, #0 + 8009efe: d104 bne.n 8009f0a + 8009f00: 7bbb ldrb r3, [r7, #14] + 8009f02: 4619 mov r1, r3 + 8009f04: 6878 ldr r0, [r7, #4] + 8009f06: f001 f8c5 bl 800b094 + 8009f0a: 6878 ldr r0, [r7, #4] + 8009f0c: f000 fd4c bl 800a9a8 + 8009f10: e004 b.n 8009f1c + 8009f12: 6839 ldr r1, [r7, #0] + 8009f14: 6878 ldr r0, [r7, #4] + 8009f16: f000 fc8a bl 800a82e + 8009f1a: bf00 nop + 8009f1c: e109 b.n 800a132 + 8009f1e: 687b ldr r3, [r7, #4] + 8009f20: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8009f24: b2db uxtb r3, r3 + 8009f26: 2b02 cmp r3, #2 + 8009f28: d002 beq.n 8009f30 + 8009f2a: 2b03 cmp r3, #3 + 8009f2c: d016 beq.n 8009f5c + 8009f2e: e04b b.n 8009fc8 + 8009f30: 7bbb ldrb r3, [r7, #14] + 8009f32: 2b00 cmp r3, #0 + 8009f34: d00d beq.n 8009f52 + 8009f36: 7bbb ldrb r3, [r7, #14] + 8009f38: 2b80 cmp r3, #128 @ 0x80 + 8009f3a: d00a beq.n 8009f52 + 8009f3c: 7bbb ldrb r3, [r7, #14] + 8009f3e: 4619 mov r1, r3 + 8009f40: 6878 ldr r0, [r7, #4] + 8009f42: f001 f8a7 bl 800b094 + 8009f46: 2180 movs r1, #128 @ 0x80 + 8009f48: 6878 ldr r0, [r7, #4] + 8009f4a: f001 f8a3 bl 800b094 + 8009f4e: bf00 nop + 8009f50: e040 b.n 8009fd4 + 8009f52: 6839 ldr r1, [r7, #0] + 8009f54: 6878 ldr r0, [r7, #4] + 8009f56: f000 fc6a bl 800a82e + 8009f5a: e03b b.n 8009fd4 + 8009f5c: 683b ldr r3, [r7, #0] + 8009f5e: 885b ldrh r3, [r3, #2] + 8009f60: 2b00 cmp r3, #0 + 8009f62: d136 bne.n 8009fd2 + 8009f64: 7bbb ldrb r3, [r7, #14] + 8009f66: f003 037f and.w r3, r3, #127 @ 0x7f + 8009f6a: 2b00 cmp r3, #0 + 8009f6c: d004 beq.n 8009f78 + 8009f6e: 7bbb ldrb r3, [r7, #14] + 8009f70: 4619 mov r1, r3 + 8009f72: 6878 ldr r0, [r7, #4] + 8009f74: f001 f8ad bl 800b0d2 + 8009f78: 6878 ldr r0, [r7, #4] + 8009f7a: f000 fd15 bl 800a9a8 + 8009f7e: 7bbb ldrb r3, [r7, #14] + 8009f80: 4619 mov r1, r3 + 8009f82: 6878 ldr r0, [r7, #4] + 8009f84: f7ff fde3 bl 8009b4e + 8009f88: 4603 mov r3, r0 + 8009f8a: 737b strb r3, [r7, #13] + 8009f8c: 7b7b ldrb r3, [r7, #13] + 8009f8e: 2bff cmp r3, #255 @ 0xff + 8009f90: d01f beq.n 8009fd2 + 8009f92: 7b7b ldrb r3, [r7, #13] + 8009f94: 2b00 cmp r3, #0 + 8009f96: d11c bne.n 8009fd2 + 8009f98: 7b7a ldrb r2, [r7, #13] + 8009f9a: 687b ldr r3, [r7, #4] + 8009f9c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 + 8009fa0: 7b7a ldrb r2, [r7, #13] + 8009fa2: 687b ldr r3, [r7, #4] + 8009fa4: 32ae adds r2, #174 @ 0xae + 8009fa6: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009faa: 689b ldr r3, [r3, #8] + 8009fac: 2b00 cmp r3, #0 + 8009fae: d010 beq.n 8009fd2 + 8009fb0: 7b7a ldrb r2, [r7, #13] + 8009fb2: 687b ldr r3, [r7, #4] + 8009fb4: 32ae adds r2, #174 @ 0xae + 8009fb6: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8009fba: 689b ldr r3, [r3, #8] + 8009fbc: 6839 ldr r1, [r7, #0] + 8009fbe: 6878 ldr r0, [r7, #4] + 8009fc0: 4798 blx r3 + 8009fc2: 4603 mov r3, r0 + 8009fc4: 73fb strb r3, [r7, #15] + 8009fc6: e004 b.n 8009fd2 + 8009fc8: 6839 ldr r1, [r7, #0] + 8009fca: 6878 ldr r0, [r7, #4] + 8009fcc: f000 fc2f bl 800a82e + 8009fd0: e000 b.n 8009fd4 + 8009fd2: bf00 nop + 8009fd4: e0ad b.n 800a132 + 8009fd6: 687b ldr r3, [r7, #4] + 8009fd8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 8009fdc: b2db uxtb r3, r3 + 8009fde: 2b02 cmp r3, #2 + 8009fe0: d002 beq.n 8009fe8 + 8009fe2: 2b03 cmp r3, #3 + 8009fe4: d033 beq.n 800a04e + 8009fe6: e099 b.n 800a11c + 8009fe8: 7bbb ldrb r3, [r7, #14] + 8009fea: 2b00 cmp r3, #0 + 8009fec: d007 beq.n 8009ffe + 8009fee: 7bbb ldrb r3, [r7, #14] + 8009ff0: 2b80 cmp r3, #128 @ 0x80 + 8009ff2: d004 beq.n 8009ffe + 8009ff4: 6839 ldr r1, [r7, #0] + 8009ff6: 6878 ldr r0, [r7, #4] + 8009ff8: f000 fc19 bl 800a82e + 8009ffc: e093 b.n 800a126 + 8009ffe: f997 300e ldrsb.w r3, [r7, #14] + 800a002: 2b00 cmp r3, #0 + 800a004: da0b bge.n 800a01e + 800a006: 7bbb ldrb r3, [r7, #14] + 800a008: f003 027f and.w r2, r3, #127 @ 0x7f + 800a00c: 4613 mov r3, r2 + 800a00e: 009b lsls r3, r3, #2 + 800a010: 4413 add r3, r2 + 800a012: 009b lsls r3, r3, #2 + 800a014: 3310 adds r3, #16 + 800a016: 687a ldr r2, [r7, #4] + 800a018: 4413 add r3, r2 + 800a01a: 3304 adds r3, #4 + 800a01c: e00b b.n 800a036 + 800a01e: 7bbb ldrb r3, [r7, #14] + 800a020: f003 027f and.w r2, r3, #127 @ 0x7f + 800a024: 4613 mov r3, r2 + 800a026: 009b lsls r3, r3, #2 + 800a028: 4413 add r3, r2 + 800a02a: 009b lsls r3, r3, #2 + 800a02c: f503 73a8 add.w r3, r3, #336 @ 0x150 + 800a030: 687a ldr r2, [r7, #4] + 800a032: 4413 add r3, r2 + 800a034: 3304 adds r3, #4 + 800a036: 60bb str r3, [r7, #8] + 800a038: 68bb ldr r3, [r7, #8] + 800a03a: 2200 movs r2, #0 + 800a03c: 739a strb r2, [r3, #14] + 800a03e: 68bb ldr r3, [r7, #8] + 800a040: 330e adds r3, #14 + 800a042: 2202 movs r2, #2 + 800a044: 4619 mov r1, r3 + 800a046: 6878 ldr r0, [r7, #4] + 800a048: f000 fc6e bl 800a928 + 800a04c: e06b b.n 800a126 + 800a04e: f997 300e ldrsb.w r3, [r7, #14] + 800a052: 2b00 cmp r3, #0 + 800a054: da11 bge.n 800a07a + 800a056: 7bbb ldrb r3, [r7, #14] + 800a058: f003 020f and.w r2, r3, #15 + 800a05c: 6879 ldr r1, [r7, #4] + 800a05e: 4613 mov r3, r2 + 800a060: 009b lsls r3, r3, #2 + 800a062: 4413 add r3, r2 + 800a064: 009b lsls r3, r3, #2 + 800a066: 440b add r3, r1 + 800a068: 3323 adds r3, #35 @ 0x23 + 800a06a: 781b ldrb r3, [r3, #0] + 800a06c: 2b00 cmp r3, #0 + 800a06e: d117 bne.n 800a0a0 + 800a070: 6839 ldr r1, [r7, #0] + 800a072: 6878 ldr r0, [r7, #4] + 800a074: f000 fbdb bl 800a82e + 800a078: e055 b.n 800a126 + 800a07a: 7bbb ldrb r3, [r7, #14] + 800a07c: f003 020f and.w r2, r3, #15 + 800a080: 6879 ldr r1, [r7, #4] + 800a082: 4613 mov r3, r2 + 800a084: 009b lsls r3, r3, #2 + 800a086: 4413 add r3, r2 + 800a088: 009b lsls r3, r3, #2 + 800a08a: 440b add r3, r1 + 800a08c: f203 1363 addw r3, r3, #355 @ 0x163 + 800a090: 781b ldrb r3, [r3, #0] + 800a092: 2b00 cmp r3, #0 + 800a094: d104 bne.n 800a0a0 + 800a096: 6839 ldr r1, [r7, #0] + 800a098: 6878 ldr r0, [r7, #4] + 800a09a: f000 fbc8 bl 800a82e + 800a09e: e042 b.n 800a126 + 800a0a0: f997 300e ldrsb.w r3, [r7, #14] + 800a0a4: 2b00 cmp r3, #0 + 800a0a6: da0b bge.n 800a0c0 + 800a0a8: 7bbb ldrb r3, [r7, #14] + 800a0aa: f003 027f and.w r2, r3, #127 @ 0x7f + 800a0ae: 4613 mov r3, r2 + 800a0b0: 009b lsls r3, r3, #2 + 800a0b2: 4413 add r3, r2 + 800a0b4: 009b lsls r3, r3, #2 + 800a0b6: 3310 adds r3, #16 + 800a0b8: 687a ldr r2, [r7, #4] + 800a0ba: 4413 add r3, r2 + 800a0bc: 3304 adds r3, #4 + 800a0be: e00b b.n 800a0d8 + 800a0c0: 7bbb ldrb r3, [r7, #14] + 800a0c2: f003 027f and.w r2, r3, #127 @ 0x7f + 800a0c6: 4613 mov r3, r2 + 800a0c8: 009b lsls r3, r3, #2 + 800a0ca: 4413 add r3, r2 + 800a0cc: 009b lsls r3, r3, #2 + 800a0ce: f503 73a8 add.w r3, r3, #336 @ 0x150 + 800a0d2: 687a ldr r2, [r7, #4] + 800a0d4: 4413 add r3, r2 + 800a0d6: 3304 adds r3, #4 + 800a0d8: 60bb str r3, [r7, #8] + 800a0da: 7bbb ldrb r3, [r7, #14] + 800a0dc: 2b00 cmp r3, #0 + 800a0de: d002 beq.n 800a0e6 + 800a0e0: 7bbb ldrb r3, [r7, #14] + 800a0e2: 2b80 cmp r3, #128 @ 0x80 + 800a0e4: d103 bne.n 800a0ee + 800a0e6: 68bb ldr r3, [r7, #8] + 800a0e8: 2200 movs r2, #0 + 800a0ea: 739a strb r2, [r3, #14] + 800a0ec: e00e b.n 800a10c + 800a0ee: 7bbb ldrb r3, [r7, #14] + 800a0f0: 4619 mov r1, r3 + 800a0f2: 6878 ldr r0, [r7, #4] + 800a0f4: f001 f80c bl 800b110 + 800a0f8: 4603 mov r3, r0 + 800a0fa: 2b00 cmp r3, #0 + 800a0fc: d003 beq.n 800a106 + 800a0fe: 68bb ldr r3, [r7, #8] + 800a100: 2201 movs r2, #1 + 800a102: 739a strb r2, [r3, #14] + 800a104: e002 b.n 800a10c + 800a106: 68bb ldr r3, [r7, #8] + 800a108: 2200 movs r2, #0 + 800a10a: 739a strb r2, [r3, #14] + 800a10c: 68bb ldr r3, [r7, #8] + 800a10e: 330e adds r3, #14 + 800a110: 2202 movs r2, #2 + 800a112: 4619 mov r1, r3 + 800a114: 6878 ldr r0, [r7, #4] + 800a116: f000 fc07 bl 800a928 + 800a11a: e004 b.n 800a126 + 800a11c: 6839 ldr r1, [r7, #0] + 800a11e: 6878 ldr r0, [r7, #4] + 800a120: f000 fb85 bl 800a82e + 800a124: bf00 nop + 800a126: e004 b.n 800a132 + 800a128: 6839 ldr r1, [r7, #0] + 800a12a: 6878 ldr r0, [r7, #4] + 800a12c: f000 fb7f bl 800a82e + 800a130: bf00 nop + 800a132: e005 b.n 800a140 + 800a134: 6839 ldr r1, [r7, #0] + 800a136: 6878 ldr r0, [r7, #4] + 800a138: f000 fb79 bl 800a82e + 800a13c: e000 b.n 800a140 + 800a13e: bf00 nop + 800a140: 7bfb ldrb r3, [r7, #15] + 800a142: 4618 mov r0, r3 + 800a144: 3710 adds r7, #16 + 800a146: 46bd mov sp, r7 + 800a148: bd80 pop {r7, pc} + ... + +0800a14c : + 800a14c: b580 push {r7, lr} + 800a14e: b084 sub sp, #16 + 800a150: af00 add r7, sp, #0 + 800a152: 6078 str r0, [r7, #4] + 800a154: 6039 str r1, [r7, #0] + 800a156: 2300 movs r3, #0 + 800a158: 813b strh r3, [r7, #8] + 800a15a: 2300 movs r3, #0 + 800a15c: 60fb str r3, [r7, #12] + 800a15e: 2300 movs r3, #0 + 800a160: 72fb strb r3, [r7, #11] + 800a162: 683b ldr r3, [r7, #0] + 800a164: 885b ldrh r3, [r3, #2] + 800a166: 0a1b lsrs r3, r3, #8 + 800a168: b29b uxth r3, r3 + 800a16a: 3b01 subs r3, #1 + 800a16c: 2b0e cmp r3, #14 + 800a16e: f200 8152 bhi.w 800a416 + 800a172: a201 add r2, pc, #4 @ (adr r2, 800a178 ) + 800a174: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a178: 0800a1e9 .word 0x0800a1e9 + 800a17c: 0800a201 .word 0x0800a201 + 800a180: 0800a241 .word 0x0800a241 + 800a184: 0800a417 .word 0x0800a417 + 800a188: 0800a417 .word 0x0800a417 + 800a18c: 0800a3b7 .word 0x0800a3b7 + 800a190: 0800a3e3 .word 0x0800a3e3 + 800a194: 0800a417 .word 0x0800a417 + 800a198: 0800a417 .word 0x0800a417 + 800a19c: 0800a417 .word 0x0800a417 + 800a1a0: 0800a417 .word 0x0800a417 + 800a1a4: 0800a417 .word 0x0800a417 + 800a1a8: 0800a417 .word 0x0800a417 + 800a1ac: 0800a417 .word 0x0800a417 + 800a1b0: 0800a1b5 .word 0x0800a1b5 + 800a1b4: 687b ldr r3, [r7, #4] + 800a1b6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a1ba: 69db ldr r3, [r3, #28] + 800a1bc: 2b00 cmp r3, #0 + 800a1be: d00b beq.n 800a1d8 + 800a1c0: 687b ldr r3, [r7, #4] + 800a1c2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a1c6: 69db ldr r3, [r3, #28] + 800a1c8: 687a ldr r2, [r7, #4] + 800a1ca: 7c12 ldrb r2, [r2, #16] + 800a1cc: f107 0108 add.w r1, r7, #8 + 800a1d0: 4610 mov r0, r2 + 800a1d2: 4798 blx r3 + 800a1d4: 60f8 str r0, [r7, #12] + 800a1d6: e126 b.n 800a426 + 800a1d8: 6839 ldr r1, [r7, #0] + 800a1da: 6878 ldr r0, [r7, #4] + 800a1dc: f000 fb27 bl 800a82e + 800a1e0: 7afb ldrb r3, [r7, #11] + 800a1e2: 3301 adds r3, #1 + 800a1e4: 72fb strb r3, [r7, #11] + 800a1e6: e11e b.n 800a426 + 800a1e8: 687b ldr r3, [r7, #4] + 800a1ea: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a1ee: 681b ldr r3, [r3, #0] + 800a1f0: 687a ldr r2, [r7, #4] + 800a1f2: 7c12 ldrb r2, [r2, #16] + 800a1f4: f107 0108 add.w r1, r7, #8 + 800a1f8: 4610 mov r0, r2 + 800a1fa: 4798 blx r3 + 800a1fc: 60f8 str r0, [r7, #12] + 800a1fe: e112 b.n 800a426 + 800a200: 687b ldr r3, [r7, #4] + 800a202: 7c1b ldrb r3, [r3, #16] + 800a204: 2b00 cmp r3, #0 + 800a206: d10d bne.n 800a224 + 800a208: 687b ldr r3, [r7, #4] + 800a20a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 800a20e: 6a9b ldr r3, [r3, #40] @ 0x28 + 800a210: f107 0208 add.w r2, r7, #8 + 800a214: 4610 mov r0, r2 + 800a216: 4798 blx r3 + 800a218: 60f8 str r0, [r7, #12] + 800a21a: 68fb ldr r3, [r7, #12] + 800a21c: 3301 adds r3, #1 + 800a21e: 2202 movs r2, #2 + 800a220: 701a strb r2, [r3, #0] + 800a222: e100 b.n 800a426 + 800a224: 687b ldr r3, [r7, #4] + 800a226: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 800a22a: 6adb ldr r3, [r3, #44] @ 0x2c + 800a22c: f107 0208 add.w r2, r7, #8 + 800a230: 4610 mov r0, r2 + 800a232: 4798 blx r3 + 800a234: 60f8 str r0, [r7, #12] + 800a236: 68fb ldr r3, [r7, #12] + 800a238: 3301 adds r3, #1 + 800a23a: 2202 movs r2, #2 + 800a23c: 701a strb r2, [r3, #0] + 800a23e: e0f2 b.n 800a426 + 800a240: 683b ldr r3, [r7, #0] + 800a242: 885b ldrh r3, [r3, #2] + 800a244: b2db uxtb r3, r3 + 800a246: 2b05 cmp r3, #5 + 800a248: f200 80ac bhi.w 800a3a4 + 800a24c: a201 add r2, pc, #4 @ (adr r2, 800a254 ) + 800a24e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a252: bf00 nop + 800a254: 0800a26d .word 0x0800a26d + 800a258: 0800a2a1 .word 0x0800a2a1 + 800a25c: 0800a2d5 .word 0x0800a2d5 + 800a260: 0800a309 .word 0x0800a309 + 800a264: 0800a33d .word 0x0800a33d + 800a268: 0800a371 .word 0x0800a371 + 800a26c: 687b ldr r3, [r7, #4] + 800a26e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a272: 685b ldr r3, [r3, #4] + 800a274: 2b00 cmp r3, #0 + 800a276: d00b beq.n 800a290 + 800a278: 687b ldr r3, [r7, #4] + 800a27a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a27e: 685b ldr r3, [r3, #4] + 800a280: 687a ldr r2, [r7, #4] + 800a282: 7c12 ldrb r2, [r2, #16] + 800a284: f107 0108 add.w r1, r7, #8 + 800a288: 4610 mov r0, r2 + 800a28a: 4798 blx r3 + 800a28c: 60f8 str r0, [r7, #12] + 800a28e: e091 b.n 800a3b4 + 800a290: 6839 ldr r1, [r7, #0] + 800a292: 6878 ldr r0, [r7, #4] + 800a294: f000 facb bl 800a82e + 800a298: 7afb ldrb r3, [r7, #11] + 800a29a: 3301 adds r3, #1 + 800a29c: 72fb strb r3, [r7, #11] + 800a29e: e089 b.n 800a3b4 + 800a2a0: 687b ldr r3, [r7, #4] + 800a2a2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a2a6: 689b ldr r3, [r3, #8] + 800a2a8: 2b00 cmp r3, #0 + 800a2aa: d00b beq.n 800a2c4 + 800a2ac: 687b ldr r3, [r7, #4] + 800a2ae: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a2b2: 689b ldr r3, [r3, #8] + 800a2b4: 687a ldr r2, [r7, #4] + 800a2b6: 7c12 ldrb r2, [r2, #16] + 800a2b8: f107 0108 add.w r1, r7, #8 + 800a2bc: 4610 mov r0, r2 + 800a2be: 4798 blx r3 + 800a2c0: 60f8 str r0, [r7, #12] + 800a2c2: e077 b.n 800a3b4 + 800a2c4: 6839 ldr r1, [r7, #0] + 800a2c6: 6878 ldr r0, [r7, #4] + 800a2c8: f000 fab1 bl 800a82e + 800a2cc: 7afb ldrb r3, [r7, #11] + 800a2ce: 3301 adds r3, #1 + 800a2d0: 72fb strb r3, [r7, #11] + 800a2d2: e06f b.n 800a3b4 + 800a2d4: 687b ldr r3, [r7, #4] + 800a2d6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a2da: 68db ldr r3, [r3, #12] + 800a2dc: 2b00 cmp r3, #0 + 800a2de: d00b beq.n 800a2f8 + 800a2e0: 687b ldr r3, [r7, #4] + 800a2e2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a2e6: 68db ldr r3, [r3, #12] + 800a2e8: 687a ldr r2, [r7, #4] + 800a2ea: 7c12 ldrb r2, [r2, #16] + 800a2ec: f107 0108 add.w r1, r7, #8 + 800a2f0: 4610 mov r0, r2 + 800a2f2: 4798 blx r3 + 800a2f4: 60f8 str r0, [r7, #12] + 800a2f6: e05d b.n 800a3b4 + 800a2f8: 6839 ldr r1, [r7, #0] + 800a2fa: 6878 ldr r0, [r7, #4] + 800a2fc: f000 fa97 bl 800a82e + 800a300: 7afb ldrb r3, [r7, #11] + 800a302: 3301 adds r3, #1 + 800a304: 72fb strb r3, [r7, #11] + 800a306: e055 b.n 800a3b4 + 800a308: 687b ldr r3, [r7, #4] + 800a30a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a30e: 691b ldr r3, [r3, #16] + 800a310: 2b00 cmp r3, #0 + 800a312: d00b beq.n 800a32c + 800a314: 687b ldr r3, [r7, #4] + 800a316: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a31a: 691b ldr r3, [r3, #16] + 800a31c: 687a ldr r2, [r7, #4] + 800a31e: 7c12 ldrb r2, [r2, #16] + 800a320: f107 0108 add.w r1, r7, #8 + 800a324: 4610 mov r0, r2 + 800a326: 4798 blx r3 + 800a328: 60f8 str r0, [r7, #12] + 800a32a: e043 b.n 800a3b4 + 800a32c: 6839 ldr r1, [r7, #0] + 800a32e: 6878 ldr r0, [r7, #4] + 800a330: f000 fa7d bl 800a82e + 800a334: 7afb ldrb r3, [r7, #11] + 800a336: 3301 adds r3, #1 + 800a338: 72fb strb r3, [r7, #11] + 800a33a: e03b b.n 800a3b4 + 800a33c: 687b ldr r3, [r7, #4] + 800a33e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a342: 695b ldr r3, [r3, #20] + 800a344: 2b00 cmp r3, #0 + 800a346: d00b beq.n 800a360 + 800a348: 687b ldr r3, [r7, #4] + 800a34a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a34e: 695b ldr r3, [r3, #20] + 800a350: 687a ldr r2, [r7, #4] + 800a352: 7c12 ldrb r2, [r2, #16] + 800a354: f107 0108 add.w r1, r7, #8 + 800a358: 4610 mov r0, r2 + 800a35a: 4798 blx r3 + 800a35c: 60f8 str r0, [r7, #12] + 800a35e: e029 b.n 800a3b4 + 800a360: 6839 ldr r1, [r7, #0] + 800a362: 6878 ldr r0, [r7, #4] + 800a364: f000 fa63 bl 800a82e + 800a368: 7afb ldrb r3, [r7, #11] + 800a36a: 3301 adds r3, #1 + 800a36c: 72fb strb r3, [r7, #11] + 800a36e: e021 b.n 800a3b4 + 800a370: 687b ldr r3, [r7, #4] + 800a372: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a376: 699b ldr r3, [r3, #24] + 800a378: 2b00 cmp r3, #0 + 800a37a: d00b beq.n 800a394 + 800a37c: 687b ldr r3, [r7, #4] + 800a37e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 + 800a382: 699b ldr r3, [r3, #24] + 800a384: 687a ldr r2, [r7, #4] + 800a386: 7c12 ldrb r2, [r2, #16] + 800a388: f107 0108 add.w r1, r7, #8 + 800a38c: 4610 mov r0, r2 + 800a38e: 4798 blx r3 + 800a390: 60f8 str r0, [r7, #12] + 800a392: e00f b.n 800a3b4 + 800a394: 6839 ldr r1, [r7, #0] + 800a396: 6878 ldr r0, [r7, #4] + 800a398: f000 fa49 bl 800a82e + 800a39c: 7afb ldrb r3, [r7, #11] + 800a39e: 3301 adds r3, #1 + 800a3a0: 72fb strb r3, [r7, #11] + 800a3a2: e007 b.n 800a3b4 + 800a3a4: 6839 ldr r1, [r7, #0] + 800a3a6: 6878 ldr r0, [r7, #4] + 800a3a8: f000 fa41 bl 800a82e + 800a3ac: 7afb ldrb r3, [r7, #11] + 800a3ae: 3301 adds r3, #1 + 800a3b0: 72fb strb r3, [r7, #11] + 800a3b2: bf00 nop + 800a3b4: e037 b.n 800a426 + 800a3b6: 687b ldr r3, [r7, #4] + 800a3b8: 7c1b ldrb r3, [r3, #16] + 800a3ba: 2b00 cmp r3, #0 + 800a3bc: d109 bne.n 800a3d2 + 800a3be: 687b ldr r3, [r7, #4] + 800a3c0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 800a3c4: 6b5b ldr r3, [r3, #52] @ 0x34 + 800a3c6: f107 0208 add.w r2, r7, #8 + 800a3ca: 4610 mov r0, r2 + 800a3cc: 4798 blx r3 + 800a3ce: 60f8 str r0, [r7, #12] + 800a3d0: e029 b.n 800a426 + 800a3d2: 6839 ldr r1, [r7, #0] + 800a3d4: 6878 ldr r0, [r7, #4] + 800a3d6: f000 fa2a bl 800a82e + 800a3da: 7afb ldrb r3, [r7, #11] + 800a3dc: 3301 adds r3, #1 + 800a3de: 72fb strb r3, [r7, #11] + 800a3e0: e021 b.n 800a426 + 800a3e2: 687b ldr r3, [r7, #4] + 800a3e4: 7c1b ldrb r3, [r3, #16] + 800a3e6: 2b00 cmp r3, #0 + 800a3e8: d10d bne.n 800a406 + 800a3ea: 687b ldr r3, [r7, #4] + 800a3ec: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 + 800a3f0: 6b1b ldr r3, [r3, #48] @ 0x30 + 800a3f2: f107 0208 add.w r2, r7, #8 + 800a3f6: 4610 mov r0, r2 + 800a3f8: 4798 blx r3 + 800a3fa: 60f8 str r0, [r7, #12] + 800a3fc: 68fb ldr r3, [r7, #12] + 800a3fe: 3301 adds r3, #1 + 800a400: 2207 movs r2, #7 + 800a402: 701a strb r2, [r3, #0] + 800a404: e00f b.n 800a426 + 800a406: 6839 ldr r1, [r7, #0] + 800a408: 6878 ldr r0, [r7, #4] + 800a40a: f000 fa10 bl 800a82e + 800a40e: 7afb ldrb r3, [r7, #11] + 800a410: 3301 adds r3, #1 + 800a412: 72fb strb r3, [r7, #11] + 800a414: e007 b.n 800a426 + 800a416: 6839 ldr r1, [r7, #0] + 800a418: 6878 ldr r0, [r7, #4] + 800a41a: f000 fa08 bl 800a82e + 800a41e: 7afb ldrb r3, [r7, #11] + 800a420: 3301 adds r3, #1 + 800a422: 72fb strb r3, [r7, #11] + 800a424: bf00 nop + 800a426: 7afb ldrb r3, [r7, #11] + 800a428: 2b00 cmp r3, #0 + 800a42a: d11e bne.n 800a46a + 800a42c: 683b ldr r3, [r7, #0] + 800a42e: 88db ldrh r3, [r3, #6] + 800a430: 2b00 cmp r3, #0 + 800a432: d016 beq.n 800a462 + 800a434: 893b ldrh r3, [r7, #8] + 800a436: 2b00 cmp r3, #0 + 800a438: d00e beq.n 800a458 + 800a43a: 683b ldr r3, [r7, #0] + 800a43c: 88da ldrh r2, [r3, #6] + 800a43e: 893b ldrh r3, [r7, #8] + 800a440: 4293 cmp r3, r2 + 800a442: bf28 it cs + 800a444: 4613 movcs r3, r2 + 800a446: b29b uxth r3, r3 + 800a448: 813b strh r3, [r7, #8] + 800a44a: 893b ldrh r3, [r7, #8] + 800a44c: 461a mov r2, r3 + 800a44e: 68f9 ldr r1, [r7, #12] + 800a450: 6878 ldr r0, [r7, #4] + 800a452: f000 fa69 bl 800a928 + 800a456: e009 b.n 800a46c + 800a458: 6839 ldr r1, [r7, #0] + 800a45a: 6878 ldr r0, [r7, #4] + 800a45c: f000 f9e7 bl 800a82e + 800a460: e004 b.n 800a46c + 800a462: 6878 ldr r0, [r7, #4] + 800a464: f000 faa0 bl 800a9a8 + 800a468: e000 b.n 800a46c + 800a46a: bf00 nop + 800a46c: 3710 adds r7, #16 + 800a46e: 46bd mov sp, r7 + 800a470: bd80 pop {r7, pc} + 800a472: bf00 nop + +0800a474 : + 800a474: b580 push {r7, lr} + 800a476: b084 sub sp, #16 + 800a478: af00 add r7, sp, #0 + 800a47a: 6078 str r0, [r7, #4] + 800a47c: 6039 str r1, [r7, #0] + 800a47e: 683b ldr r3, [r7, #0] + 800a480: 889b ldrh r3, [r3, #4] + 800a482: 2b00 cmp r3, #0 + 800a484: d131 bne.n 800a4ea + 800a486: 683b ldr r3, [r7, #0] + 800a488: 88db ldrh r3, [r3, #6] + 800a48a: 2b00 cmp r3, #0 + 800a48c: d12d bne.n 800a4ea + 800a48e: 683b ldr r3, [r7, #0] + 800a490: 885b ldrh r3, [r3, #2] + 800a492: 2b7f cmp r3, #127 @ 0x7f + 800a494: d829 bhi.n 800a4ea + 800a496: 683b ldr r3, [r7, #0] + 800a498: 885b ldrh r3, [r3, #2] + 800a49a: b2db uxtb r3, r3 + 800a49c: f003 037f and.w r3, r3, #127 @ 0x7f + 800a4a0: 73fb strb r3, [r7, #15] + 800a4a2: 687b ldr r3, [r7, #4] + 800a4a4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 800a4a8: b2db uxtb r3, r3 + 800a4aa: 2b03 cmp r3, #3 + 800a4ac: d104 bne.n 800a4b8 + 800a4ae: 6839 ldr r1, [r7, #0] + 800a4b0: 6878 ldr r0, [r7, #4] + 800a4b2: f000 f9bc bl 800a82e + 800a4b6: e01d b.n 800a4f4 + 800a4b8: 687b ldr r3, [r7, #4] + 800a4ba: 7bfa ldrb r2, [r7, #15] + 800a4bc: f883 229e strb.w r2, [r3, #670] @ 0x29e + 800a4c0: 7bfb ldrb r3, [r7, #15] + 800a4c2: 4619 mov r1, r3 + 800a4c4: 6878 ldr r0, [r7, #4] + 800a4c6: f000 fe4f bl 800b168 + 800a4ca: 6878 ldr r0, [r7, #4] + 800a4cc: f000 fa6c bl 800a9a8 + 800a4d0: 7bfb ldrb r3, [r7, #15] + 800a4d2: 2b00 cmp r3, #0 + 800a4d4: d004 beq.n 800a4e0 + 800a4d6: 687b ldr r3, [r7, #4] + 800a4d8: 2202 movs r2, #2 + 800a4da: f883 229c strb.w r2, [r3, #668] @ 0x29c + 800a4de: e009 b.n 800a4f4 + 800a4e0: 687b ldr r3, [r7, #4] + 800a4e2: 2201 movs r2, #1 + 800a4e4: f883 229c strb.w r2, [r3, #668] @ 0x29c + 800a4e8: e004 b.n 800a4f4 + 800a4ea: 6839 ldr r1, [r7, #0] + 800a4ec: 6878 ldr r0, [r7, #4] + 800a4ee: f000 f99e bl 800a82e + 800a4f2: bf00 nop + 800a4f4: bf00 nop + 800a4f6: 3710 adds r7, #16 + 800a4f8: 46bd mov sp, r7 + 800a4fa: bd80 pop {r7, pc} + +0800a4fc : + 800a4fc: b580 push {r7, lr} + 800a4fe: b084 sub sp, #16 + 800a500: af00 add r7, sp, #0 + 800a502: 6078 str r0, [r7, #4] + 800a504: 6039 str r1, [r7, #0] + 800a506: 2300 movs r3, #0 + 800a508: 73fb strb r3, [r7, #15] + 800a50a: 683b ldr r3, [r7, #0] + 800a50c: 885b ldrh r3, [r3, #2] + 800a50e: b2da uxtb r2, r3 + 800a510: 4b4e ldr r3, [pc, #312] @ (800a64c ) + 800a512: 701a strb r2, [r3, #0] + 800a514: 4b4d ldr r3, [pc, #308] @ (800a64c ) + 800a516: 781b ldrb r3, [r3, #0] + 800a518: 2b01 cmp r3, #1 + 800a51a: d905 bls.n 800a528 + 800a51c: 6839 ldr r1, [r7, #0] + 800a51e: 6878 ldr r0, [r7, #4] + 800a520: f000 f985 bl 800a82e + 800a524: 2303 movs r3, #3 + 800a526: e08c b.n 800a642 + 800a528: 687b ldr r3, [r7, #4] + 800a52a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 800a52e: b2db uxtb r3, r3 + 800a530: 2b02 cmp r3, #2 + 800a532: d002 beq.n 800a53a + 800a534: 2b03 cmp r3, #3 + 800a536: d029 beq.n 800a58c + 800a538: e075 b.n 800a626 + 800a53a: 4b44 ldr r3, [pc, #272] @ (800a64c ) + 800a53c: 781b ldrb r3, [r3, #0] + 800a53e: 2b00 cmp r3, #0 + 800a540: d020 beq.n 800a584 + 800a542: 4b42 ldr r3, [pc, #264] @ (800a64c ) + 800a544: 781b ldrb r3, [r3, #0] + 800a546: 461a mov r2, r3 + 800a548: 687b ldr r3, [r7, #4] + 800a54a: 605a str r2, [r3, #4] + 800a54c: 4b3f ldr r3, [pc, #252] @ (800a64c ) + 800a54e: 781b ldrb r3, [r3, #0] + 800a550: 4619 mov r1, r3 + 800a552: 6878 ldr r0, [r7, #4] + 800a554: f7fe ffa3 bl 800949e + 800a558: 4603 mov r3, r0 + 800a55a: 73fb strb r3, [r7, #15] + 800a55c: 7bfb ldrb r3, [r7, #15] + 800a55e: 2b00 cmp r3, #0 + 800a560: d008 beq.n 800a574 + 800a562: 6839 ldr r1, [r7, #0] + 800a564: 6878 ldr r0, [r7, #4] + 800a566: f000 f962 bl 800a82e + 800a56a: 687b ldr r3, [r7, #4] + 800a56c: 2202 movs r2, #2 + 800a56e: f883 229c strb.w r2, [r3, #668] @ 0x29c + 800a572: e065 b.n 800a640 + 800a574: 6878 ldr r0, [r7, #4] + 800a576: f000 fa17 bl 800a9a8 + 800a57a: 687b ldr r3, [r7, #4] + 800a57c: 2203 movs r2, #3 + 800a57e: f883 229c strb.w r2, [r3, #668] @ 0x29c + 800a582: e05d b.n 800a640 + 800a584: 6878 ldr r0, [r7, #4] + 800a586: f000 fa0f bl 800a9a8 + 800a58a: e059 b.n 800a640 + 800a58c: 4b2f ldr r3, [pc, #188] @ (800a64c ) + 800a58e: 781b ldrb r3, [r3, #0] + 800a590: 2b00 cmp r3, #0 + 800a592: d112 bne.n 800a5ba + 800a594: 687b ldr r3, [r7, #4] + 800a596: 2202 movs r2, #2 + 800a598: f883 229c strb.w r2, [r3, #668] @ 0x29c + 800a59c: 4b2b ldr r3, [pc, #172] @ (800a64c ) + 800a59e: 781b ldrb r3, [r3, #0] + 800a5a0: 461a mov r2, r3 + 800a5a2: 687b ldr r3, [r7, #4] + 800a5a4: 605a str r2, [r3, #4] + 800a5a6: 4b29 ldr r3, [pc, #164] @ (800a64c ) + 800a5a8: 781b ldrb r3, [r3, #0] + 800a5aa: 4619 mov r1, r3 + 800a5ac: 6878 ldr r0, [r7, #4] + 800a5ae: f7fe ff92 bl 80094d6 + 800a5b2: 6878 ldr r0, [r7, #4] + 800a5b4: f000 f9f8 bl 800a9a8 + 800a5b8: e042 b.n 800a640 + 800a5ba: 4b24 ldr r3, [pc, #144] @ (800a64c ) + 800a5bc: 781b ldrb r3, [r3, #0] + 800a5be: 461a mov r2, r3 + 800a5c0: 687b ldr r3, [r7, #4] + 800a5c2: 685b ldr r3, [r3, #4] + 800a5c4: 429a cmp r2, r3 + 800a5c6: d02a beq.n 800a61e + 800a5c8: 687b ldr r3, [r7, #4] + 800a5ca: 685b ldr r3, [r3, #4] + 800a5cc: b2db uxtb r3, r3 + 800a5ce: 4619 mov r1, r3 + 800a5d0: 6878 ldr r0, [r7, #4] + 800a5d2: f7fe ff80 bl 80094d6 + 800a5d6: 4b1d ldr r3, [pc, #116] @ (800a64c ) + 800a5d8: 781b ldrb r3, [r3, #0] + 800a5da: 461a mov r2, r3 + 800a5dc: 687b ldr r3, [r7, #4] + 800a5de: 605a str r2, [r3, #4] + 800a5e0: 4b1a ldr r3, [pc, #104] @ (800a64c ) + 800a5e2: 781b ldrb r3, [r3, #0] + 800a5e4: 4619 mov r1, r3 + 800a5e6: 6878 ldr r0, [r7, #4] + 800a5e8: f7fe ff59 bl 800949e + 800a5ec: 4603 mov r3, r0 + 800a5ee: 73fb strb r3, [r7, #15] + 800a5f0: 7bfb ldrb r3, [r7, #15] + 800a5f2: 2b00 cmp r3, #0 + 800a5f4: d00f beq.n 800a616 + 800a5f6: 6839 ldr r1, [r7, #0] + 800a5f8: 6878 ldr r0, [r7, #4] + 800a5fa: f000 f918 bl 800a82e + 800a5fe: 687b ldr r3, [r7, #4] + 800a600: 685b ldr r3, [r3, #4] + 800a602: b2db uxtb r3, r3 + 800a604: 4619 mov r1, r3 + 800a606: 6878 ldr r0, [r7, #4] + 800a608: f7fe ff65 bl 80094d6 + 800a60c: 687b ldr r3, [r7, #4] + 800a60e: 2202 movs r2, #2 + 800a610: f883 229c strb.w r2, [r3, #668] @ 0x29c + 800a614: e014 b.n 800a640 + 800a616: 6878 ldr r0, [r7, #4] + 800a618: f000 f9c6 bl 800a9a8 + 800a61c: e010 b.n 800a640 + 800a61e: 6878 ldr r0, [r7, #4] + 800a620: f000 f9c2 bl 800a9a8 + 800a624: e00c b.n 800a640 + 800a626: 6839 ldr r1, [r7, #0] + 800a628: 6878 ldr r0, [r7, #4] + 800a62a: f000 f900 bl 800a82e + 800a62e: 4b07 ldr r3, [pc, #28] @ (800a64c ) + 800a630: 781b ldrb r3, [r3, #0] + 800a632: 4619 mov r1, r3 + 800a634: 6878 ldr r0, [r7, #4] + 800a636: f7fe ff4e bl 80094d6 + 800a63a: 2303 movs r3, #3 + 800a63c: 73fb strb r3, [r7, #15] + 800a63e: bf00 nop + 800a640: 7bfb ldrb r3, [r7, #15] + 800a642: 4618 mov r0, r3 + 800a644: 3710 adds r7, #16 + 800a646: 46bd mov sp, r7 + 800a648: bd80 pop {r7, pc} + 800a64a: bf00 nop + 800a64c: 20000d84 .word 0x20000d84 + +0800a650 : + 800a650: b580 push {r7, lr} + 800a652: b082 sub sp, #8 + 800a654: af00 add r7, sp, #0 + 800a656: 6078 str r0, [r7, #4] + 800a658: 6039 str r1, [r7, #0] + 800a65a: 683b ldr r3, [r7, #0] + 800a65c: 88db ldrh r3, [r3, #6] + 800a65e: 2b01 cmp r3, #1 + 800a660: d004 beq.n 800a66c + 800a662: 6839 ldr r1, [r7, #0] + 800a664: 6878 ldr r0, [r7, #4] + 800a666: f000 f8e2 bl 800a82e + 800a66a: e023 b.n 800a6b4 + 800a66c: 687b ldr r3, [r7, #4] + 800a66e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 800a672: b2db uxtb r3, r3 + 800a674: 2b02 cmp r3, #2 + 800a676: dc02 bgt.n 800a67e + 800a678: 2b00 cmp r3, #0 + 800a67a: dc03 bgt.n 800a684 + 800a67c: e015 b.n 800a6aa + 800a67e: 2b03 cmp r3, #3 + 800a680: d00b beq.n 800a69a + 800a682: e012 b.n 800a6aa + 800a684: 687b ldr r3, [r7, #4] + 800a686: 2200 movs r2, #0 + 800a688: 609a str r2, [r3, #8] + 800a68a: 687b ldr r3, [r7, #4] + 800a68c: 3308 adds r3, #8 + 800a68e: 2201 movs r2, #1 + 800a690: 4619 mov r1, r3 + 800a692: 6878 ldr r0, [r7, #4] + 800a694: f000 f948 bl 800a928 + 800a698: e00c b.n 800a6b4 + 800a69a: 687b ldr r3, [r7, #4] + 800a69c: 3304 adds r3, #4 + 800a69e: 2201 movs r2, #1 + 800a6a0: 4619 mov r1, r3 + 800a6a2: 6878 ldr r0, [r7, #4] + 800a6a4: f000 f940 bl 800a928 + 800a6a8: e004 b.n 800a6b4 + 800a6aa: 6839 ldr r1, [r7, #0] + 800a6ac: 6878 ldr r0, [r7, #4] + 800a6ae: f000 f8be bl 800a82e + 800a6b2: bf00 nop + 800a6b4: bf00 nop + 800a6b6: 3708 adds r7, #8 + 800a6b8: 46bd mov sp, r7 + 800a6ba: bd80 pop {r7, pc} + +0800a6bc : + 800a6bc: b580 push {r7, lr} + 800a6be: b082 sub sp, #8 + 800a6c0: af00 add r7, sp, #0 + 800a6c2: 6078 str r0, [r7, #4] + 800a6c4: 6039 str r1, [r7, #0] + 800a6c6: 687b ldr r3, [r7, #4] + 800a6c8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 800a6cc: b2db uxtb r3, r3 + 800a6ce: 3b01 subs r3, #1 + 800a6d0: 2b02 cmp r3, #2 + 800a6d2: d81e bhi.n 800a712 + 800a6d4: 683b ldr r3, [r7, #0] + 800a6d6: 88db ldrh r3, [r3, #6] + 800a6d8: 2b02 cmp r3, #2 + 800a6da: d004 beq.n 800a6e6 + 800a6dc: 6839 ldr r1, [r7, #0] + 800a6de: 6878 ldr r0, [r7, #4] + 800a6e0: f000 f8a5 bl 800a82e + 800a6e4: e01a b.n 800a71c + 800a6e6: 687b ldr r3, [r7, #4] + 800a6e8: 2201 movs r2, #1 + 800a6ea: 60da str r2, [r3, #12] + 800a6ec: 687b ldr r3, [r7, #4] + 800a6ee: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 + 800a6f2: 2b00 cmp r3, #0 + 800a6f4: d005 beq.n 800a702 + 800a6f6: 687b ldr r3, [r7, #4] + 800a6f8: 68db ldr r3, [r3, #12] + 800a6fa: f043 0202 orr.w r2, r3, #2 + 800a6fe: 687b ldr r3, [r7, #4] + 800a700: 60da str r2, [r3, #12] + 800a702: 687b ldr r3, [r7, #4] + 800a704: 330c adds r3, #12 + 800a706: 2202 movs r2, #2 + 800a708: 4619 mov r1, r3 + 800a70a: 6878 ldr r0, [r7, #4] + 800a70c: f000 f90c bl 800a928 + 800a710: e004 b.n 800a71c + 800a712: 6839 ldr r1, [r7, #0] + 800a714: 6878 ldr r0, [r7, #4] + 800a716: f000 f88a bl 800a82e + 800a71a: bf00 nop + 800a71c: bf00 nop + 800a71e: 3708 adds r7, #8 + 800a720: 46bd mov sp, r7 + 800a722: bd80 pop {r7, pc} + +0800a724 : + 800a724: b580 push {r7, lr} + 800a726: b082 sub sp, #8 + 800a728: af00 add r7, sp, #0 + 800a72a: 6078 str r0, [r7, #4] + 800a72c: 6039 str r1, [r7, #0] + 800a72e: 683b ldr r3, [r7, #0] + 800a730: 885b ldrh r3, [r3, #2] + 800a732: 2b01 cmp r3, #1 + 800a734: d107 bne.n 800a746 + 800a736: 687b ldr r3, [r7, #4] + 800a738: 2201 movs r2, #1 + 800a73a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 + 800a73e: 6878 ldr r0, [r7, #4] + 800a740: f000 f932 bl 800a9a8 + 800a744: e013 b.n 800a76e + 800a746: 683b ldr r3, [r7, #0] + 800a748: 885b ldrh r3, [r3, #2] + 800a74a: 2b02 cmp r3, #2 + 800a74c: d10b bne.n 800a766 + 800a74e: 683b ldr r3, [r7, #0] + 800a750: 889b ldrh r3, [r3, #4] + 800a752: 0a1b lsrs r3, r3, #8 + 800a754: b29b uxth r3, r3 + 800a756: b2da uxtb r2, r3 + 800a758: 687b ldr r3, [r7, #4] + 800a75a: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 + 800a75e: 6878 ldr r0, [r7, #4] + 800a760: f000 f922 bl 800a9a8 + 800a764: e003 b.n 800a76e + 800a766: 6839 ldr r1, [r7, #0] + 800a768: 6878 ldr r0, [r7, #4] + 800a76a: f000 f860 bl 800a82e + 800a76e: bf00 nop + 800a770: 3708 adds r7, #8 + 800a772: 46bd mov sp, r7 + 800a774: bd80 pop {r7, pc} + +0800a776 : + 800a776: b580 push {r7, lr} + 800a778: b082 sub sp, #8 + 800a77a: af00 add r7, sp, #0 + 800a77c: 6078 str r0, [r7, #4] + 800a77e: 6039 str r1, [r7, #0] + 800a780: 687b ldr r3, [r7, #4] + 800a782: f893 329c ldrb.w r3, [r3, #668] @ 0x29c + 800a786: b2db uxtb r3, r3 + 800a788: 3b01 subs r3, #1 + 800a78a: 2b02 cmp r3, #2 + 800a78c: d80b bhi.n 800a7a6 + 800a78e: 683b ldr r3, [r7, #0] + 800a790: 885b ldrh r3, [r3, #2] + 800a792: 2b01 cmp r3, #1 + 800a794: d10c bne.n 800a7b0 + 800a796: 687b ldr r3, [r7, #4] + 800a798: 2200 movs r2, #0 + 800a79a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 + 800a79e: 6878 ldr r0, [r7, #4] + 800a7a0: f000 f902 bl 800a9a8 + 800a7a4: e004 b.n 800a7b0 + 800a7a6: 6839 ldr r1, [r7, #0] + 800a7a8: 6878 ldr r0, [r7, #4] + 800a7aa: f000 f840 bl 800a82e + 800a7ae: e000 b.n 800a7b2 + 800a7b0: bf00 nop + 800a7b2: bf00 nop + 800a7b4: 3708 adds r7, #8 + 800a7b6: 46bd mov sp, r7 + 800a7b8: bd80 pop {r7, pc} + +0800a7ba : + 800a7ba: b580 push {r7, lr} + 800a7bc: b084 sub sp, #16 + 800a7be: af00 add r7, sp, #0 + 800a7c0: 6078 str r0, [r7, #4] + 800a7c2: 6039 str r1, [r7, #0] + 800a7c4: 683b ldr r3, [r7, #0] + 800a7c6: 60fb str r3, [r7, #12] + 800a7c8: 68fb ldr r3, [r7, #12] + 800a7ca: 781a ldrb r2, [r3, #0] + 800a7cc: 687b ldr r3, [r7, #4] + 800a7ce: 701a strb r2, [r3, #0] + 800a7d0: 68fb ldr r3, [r7, #12] + 800a7d2: 3301 adds r3, #1 + 800a7d4: 60fb str r3, [r7, #12] + 800a7d6: 68fb ldr r3, [r7, #12] + 800a7d8: 781a ldrb r2, [r3, #0] + 800a7da: 687b ldr r3, [r7, #4] + 800a7dc: 705a strb r2, [r3, #1] + 800a7de: 68fb ldr r3, [r7, #12] + 800a7e0: 3301 adds r3, #1 + 800a7e2: 60fb str r3, [r7, #12] + 800a7e4: 68f8 ldr r0, [r7, #12] + 800a7e6: f7ff fa13 bl 8009c10 + 800a7ea: 4603 mov r3, r0 + 800a7ec: 461a mov r2, r3 + 800a7ee: 687b ldr r3, [r7, #4] + 800a7f0: 805a strh r2, [r3, #2] + 800a7f2: 68fb ldr r3, [r7, #12] + 800a7f4: 3301 adds r3, #1 + 800a7f6: 60fb str r3, [r7, #12] + 800a7f8: 68fb ldr r3, [r7, #12] + 800a7fa: 3301 adds r3, #1 + 800a7fc: 60fb str r3, [r7, #12] + 800a7fe: 68f8 ldr r0, [r7, #12] + 800a800: f7ff fa06 bl 8009c10 + 800a804: 4603 mov r3, r0 + 800a806: 461a mov r2, r3 + 800a808: 687b ldr r3, [r7, #4] + 800a80a: 809a strh r2, [r3, #4] + 800a80c: 68fb ldr r3, [r7, #12] + 800a80e: 3301 adds r3, #1 + 800a810: 60fb str r3, [r7, #12] + 800a812: 68fb ldr r3, [r7, #12] + 800a814: 3301 adds r3, #1 + 800a816: 60fb str r3, [r7, #12] + 800a818: 68f8 ldr r0, [r7, #12] + 800a81a: f7ff f9f9 bl 8009c10 + 800a81e: 4603 mov r3, r0 + 800a820: 461a mov r2, r3 + 800a822: 687b ldr r3, [r7, #4] + 800a824: 80da strh r2, [r3, #6] + 800a826: bf00 nop + 800a828: 3710 adds r7, #16 + 800a82a: 46bd mov sp, r7 + 800a82c: bd80 pop {r7, pc} + +0800a82e : + 800a82e: b580 push {r7, lr} + 800a830: b082 sub sp, #8 + 800a832: af00 add r7, sp, #0 + 800a834: 6078 str r0, [r7, #4] + 800a836: 6039 str r1, [r7, #0] + 800a838: 2180 movs r1, #128 @ 0x80 + 800a83a: 6878 ldr r0, [r7, #4] + 800a83c: f000 fc2a bl 800b094 + 800a840: 2100 movs r1, #0 + 800a842: 6878 ldr r0, [r7, #4] + 800a844: f000 fc26 bl 800b094 + 800a848: bf00 nop + 800a84a: 3708 adds r7, #8 + 800a84c: 46bd mov sp, r7 + 800a84e: bd80 pop {r7, pc} + +0800a850 : + 800a850: b580 push {r7, lr} + 800a852: b086 sub sp, #24 + 800a854: af00 add r7, sp, #0 + 800a856: 60f8 str r0, [r7, #12] + 800a858: 60b9 str r1, [r7, #8] + 800a85a: 607a str r2, [r7, #4] + 800a85c: 2300 movs r3, #0 + 800a85e: 75fb strb r3, [r7, #23] + 800a860: 68fb ldr r3, [r7, #12] + 800a862: 2b00 cmp r3, #0 + 800a864: d042 beq.n 800a8ec + 800a866: 68fb ldr r3, [r7, #12] + 800a868: 613b str r3, [r7, #16] + 800a86a: 6938 ldr r0, [r7, #16] + 800a86c: f000 f842 bl 800a8f4 + 800a870: 4603 mov r3, r0 + 800a872: 3301 adds r3, #1 + 800a874: 005b lsls r3, r3, #1 + 800a876: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 800a87a: d808 bhi.n 800a88e + 800a87c: 6938 ldr r0, [r7, #16] + 800a87e: f000 f839 bl 800a8f4 + 800a882: 4603 mov r3, r0 + 800a884: 3301 adds r3, #1 + 800a886: b29b uxth r3, r3 + 800a888: 005b lsls r3, r3, #1 + 800a88a: b29a uxth r2, r3 + 800a88c: e001 b.n 800a892 + 800a88e: f44f 7200 mov.w r2, #512 @ 0x200 + 800a892: 687b ldr r3, [r7, #4] + 800a894: 801a strh r2, [r3, #0] + 800a896: 7dfb ldrb r3, [r7, #23] + 800a898: 68ba ldr r2, [r7, #8] + 800a89a: 4413 add r3, r2 + 800a89c: 687a ldr r2, [r7, #4] + 800a89e: 7812 ldrb r2, [r2, #0] + 800a8a0: 701a strb r2, [r3, #0] + 800a8a2: 7dfb ldrb r3, [r7, #23] + 800a8a4: 3301 adds r3, #1 + 800a8a6: 75fb strb r3, [r7, #23] + 800a8a8: 7dfb ldrb r3, [r7, #23] + 800a8aa: 68ba ldr r2, [r7, #8] + 800a8ac: 4413 add r3, r2 + 800a8ae: 2203 movs r2, #3 + 800a8b0: 701a strb r2, [r3, #0] + 800a8b2: 7dfb ldrb r3, [r7, #23] + 800a8b4: 3301 adds r3, #1 + 800a8b6: 75fb strb r3, [r7, #23] + 800a8b8: e013 b.n 800a8e2 + 800a8ba: 7dfb ldrb r3, [r7, #23] + 800a8bc: 68ba ldr r2, [r7, #8] + 800a8be: 4413 add r3, r2 + 800a8c0: 693a ldr r2, [r7, #16] + 800a8c2: 7812 ldrb r2, [r2, #0] + 800a8c4: 701a strb r2, [r3, #0] + 800a8c6: 693b ldr r3, [r7, #16] + 800a8c8: 3301 adds r3, #1 + 800a8ca: 613b str r3, [r7, #16] + 800a8cc: 7dfb ldrb r3, [r7, #23] + 800a8ce: 3301 adds r3, #1 + 800a8d0: 75fb strb r3, [r7, #23] + 800a8d2: 7dfb ldrb r3, [r7, #23] + 800a8d4: 68ba ldr r2, [r7, #8] + 800a8d6: 4413 add r3, r2 + 800a8d8: 2200 movs r2, #0 + 800a8da: 701a strb r2, [r3, #0] + 800a8dc: 7dfb ldrb r3, [r7, #23] + 800a8de: 3301 adds r3, #1 + 800a8e0: 75fb strb r3, [r7, #23] + 800a8e2: 693b ldr r3, [r7, #16] + 800a8e4: 781b ldrb r3, [r3, #0] + 800a8e6: 2b00 cmp r3, #0 + 800a8e8: d1e7 bne.n 800a8ba + 800a8ea: e000 b.n 800a8ee + 800a8ec: bf00 nop + 800a8ee: 3718 adds r7, #24 + 800a8f0: 46bd mov sp, r7 + 800a8f2: bd80 pop {r7, pc} + +0800a8f4 : + 800a8f4: b480 push {r7} + 800a8f6: b085 sub sp, #20 + 800a8f8: af00 add r7, sp, #0 + 800a8fa: 6078 str r0, [r7, #4] + 800a8fc: 2300 movs r3, #0 + 800a8fe: 73fb strb r3, [r7, #15] + 800a900: 687b ldr r3, [r7, #4] + 800a902: 60bb str r3, [r7, #8] + 800a904: e005 b.n 800a912 + 800a906: 7bfb ldrb r3, [r7, #15] + 800a908: 3301 adds r3, #1 + 800a90a: 73fb strb r3, [r7, #15] + 800a90c: 68bb ldr r3, [r7, #8] + 800a90e: 3301 adds r3, #1 + 800a910: 60bb str r3, [r7, #8] + 800a912: 68bb ldr r3, [r7, #8] + 800a914: 781b ldrb r3, [r3, #0] + 800a916: 2b00 cmp r3, #0 + 800a918: d1f5 bne.n 800a906 + 800a91a: 7bfb ldrb r3, [r7, #15] + 800a91c: 4618 mov r0, r3 + 800a91e: 3714 adds r7, #20 + 800a920: 46bd mov sp, r7 + 800a922: f85d 7b04 ldr.w r7, [sp], #4 + 800a926: 4770 bx lr + +0800a928 : + 800a928: b580 push {r7, lr} + 800a92a: b084 sub sp, #16 + 800a92c: af00 add r7, sp, #0 + 800a92e: 60f8 str r0, [r7, #12] + 800a930: 60b9 str r1, [r7, #8] + 800a932: 607a str r2, [r7, #4] + 800a934: 68fb ldr r3, [r7, #12] + 800a936: 2202 movs r2, #2 + 800a938: f8c3 2294 str.w r2, [r3, #660] @ 0x294 + 800a93c: 68fb ldr r3, [r7, #12] + 800a93e: 687a ldr r2, [r7, #4] + 800a940: 615a str r2, [r3, #20] + 800a942: 68fb ldr r3, [r7, #12] + 800a944: 68ba ldr r2, [r7, #8] + 800a946: 625a str r2, [r3, #36] @ 0x24 + 800a948: 68fb ldr r3, [r7, #12] + 800a94a: 687a ldr r2, [r7, #4] + 800a94c: 619a str r2, [r3, #24] + 800a94e: 687b ldr r3, [r7, #4] + 800a950: 68ba ldr r2, [r7, #8] + 800a952: 2100 movs r1, #0 + 800a954: 68f8 ldr r0, [r7, #12] + 800a956: f000 fc26 bl 800b1a6 + 800a95a: 2300 movs r3, #0 + 800a95c: 4618 mov r0, r3 + 800a95e: 3710 adds r7, #16 + 800a960: 46bd mov sp, r7 + 800a962: bd80 pop {r7, pc} + +0800a964 : + 800a964: b580 push {r7, lr} + 800a966: b084 sub sp, #16 + 800a968: af00 add r7, sp, #0 + 800a96a: 60f8 str r0, [r7, #12] + 800a96c: 60b9 str r1, [r7, #8] + 800a96e: 607a str r2, [r7, #4] + 800a970: 687b ldr r3, [r7, #4] + 800a972: 68ba ldr r2, [r7, #8] + 800a974: 2100 movs r1, #0 + 800a976: 68f8 ldr r0, [r7, #12] + 800a978: f000 fc15 bl 800b1a6 + 800a97c: 2300 movs r3, #0 + 800a97e: 4618 mov r0, r3 + 800a980: 3710 adds r7, #16 + 800a982: 46bd mov sp, r7 + 800a984: bd80 pop {r7, pc} + +0800a986 : + 800a986: b580 push {r7, lr} + 800a988: b084 sub sp, #16 + 800a98a: af00 add r7, sp, #0 + 800a98c: 60f8 str r0, [r7, #12] + 800a98e: 60b9 str r1, [r7, #8] + 800a990: 607a str r2, [r7, #4] + 800a992: 687b ldr r3, [r7, #4] + 800a994: 68ba ldr r2, [r7, #8] + 800a996: 2100 movs r1, #0 + 800a998: 68f8 ldr r0, [r7, #12] + 800a99a: f000 fc25 bl 800b1e8 + 800a99e: 2300 movs r3, #0 + 800a9a0: 4618 mov r0, r3 + 800a9a2: 3710 adds r7, #16 + 800a9a4: 46bd mov sp, r7 + 800a9a6: bd80 pop {r7, pc} + +0800a9a8 : + 800a9a8: b580 push {r7, lr} + 800a9aa: b082 sub sp, #8 + 800a9ac: af00 add r7, sp, #0 + 800a9ae: 6078 str r0, [r7, #4] + 800a9b0: 687b ldr r3, [r7, #4] + 800a9b2: 2204 movs r2, #4 + 800a9b4: f8c3 2294 str.w r2, [r3, #660] @ 0x294 + 800a9b8: 2300 movs r3, #0 + 800a9ba: 2200 movs r2, #0 + 800a9bc: 2100 movs r1, #0 + 800a9be: 6878 ldr r0, [r7, #4] + 800a9c0: f000 fbf1 bl 800b1a6 + 800a9c4: 2300 movs r3, #0 + 800a9c6: 4618 mov r0, r3 + 800a9c8: 3708 adds r7, #8 + 800a9ca: 46bd mov sp, r7 + 800a9cc: bd80 pop {r7, pc} + +0800a9ce : + 800a9ce: b580 push {r7, lr} + 800a9d0: b082 sub sp, #8 + 800a9d2: af00 add r7, sp, #0 + 800a9d4: 6078 str r0, [r7, #4] + 800a9d6: 687b ldr r3, [r7, #4] + 800a9d8: 2205 movs r2, #5 + 800a9da: f8c3 2294 str.w r2, [r3, #660] @ 0x294 + 800a9de: 2300 movs r3, #0 + 800a9e0: 2200 movs r2, #0 + 800a9e2: 2100 movs r1, #0 + 800a9e4: 6878 ldr r0, [r7, #4] + 800a9e6: f000 fbff bl 800b1e8 + 800a9ea: 2300 movs r3, #0 + 800a9ec: 4618 mov r0, r3 + 800a9ee: 3708 adds r7, #8 + 800a9f0: 46bd mov sp, r7 + 800a9f2: bd80 pop {r7, pc} + +0800a9f4 : + 800a9f4: b580 push {r7, lr} + 800a9f6: af00 add r7, sp, #0 + 800a9f8: 2200 movs r2, #0 + 800a9fa: 490e ldr r1, [pc, #56] @ (800aa34 ) + 800a9fc: 480e ldr r0, [pc, #56] @ (800aa38 ) + 800a9fe: f7fe fcd1 bl 80093a4 + 800aa02: 4603 mov r3, r0 + 800aa04: 2b00 cmp r3, #0 + 800aa06: d001 beq.n 800aa0c + 800aa08: f7f6 fc1e bl 8001248 + 800aa0c: 490b ldr r1, [pc, #44] @ (800aa3c ) + 800aa0e: 480a ldr r0, [pc, #40] @ (800aa38 ) + 800aa10: f7fe fcf8 bl 8009404 + 800aa14: 4603 mov r3, r0 + 800aa16: 2b00 cmp r3, #0 + 800aa18: d001 beq.n 800aa1e + 800aa1a: f7f6 fc15 bl 8001248 + 800aa1e: 4806 ldr r0, [pc, #24] @ (800aa38 ) + 800aa20: f7fe fd26 bl 8009470 + 800aa24: 4603 mov r3, r0 + 800aa26: 2b00 cmp r3, #0 + 800aa28: d001 beq.n 800aa2e + 800aa2a: f7f6 fc0d bl 8001248 + 800aa2e: bf00 nop + 800aa30: bd80 pop {r7, pc} + 800aa32: bf00 nop + 800aa34: 20000140 .word 0x20000140 + 800aa38: 20000d88 .word 0x20000d88 + 800aa3c: 2000009c .word 0x2000009c + +0800aa40 : + 800aa40: b480 push {r7} + 800aa42: b083 sub sp, #12 + 800aa44: af00 add r7, sp, #0 + 800aa46: 4603 mov r3, r0 + 800aa48: 6039 str r1, [r7, #0] + 800aa4a: 71fb strb r3, [r7, #7] + 800aa4c: 683b ldr r3, [r7, #0] + 800aa4e: 2212 movs r2, #18 + 800aa50: 801a strh r2, [r3, #0] + 800aa52: 4b03 ldr r3, [pc, #12] @ (800aa60 ) + 800aa54: 4618 mov r0, r3 + 800aa56: 370c adds r7, #12 + 800aa58: 46bd mov sp, r7 + 800aa5a: f85d 7b04 ldr.w r7, [sp], #4 + 800aa5e: 4770 bx lr + 800aa60: 20000160 .word 0x20000160 + +0800aa64 : + 800aa64: b480 push {r7} + 800aa66: b083 sub sp, #12 + 800aa68: af00 add r7, sp, #0 + 800aa6a: 4603 mov r3, r0 + 800aa6c: 6039 str r1, [r7, #0] + 800aa6e: 71fb strb r3, [r7, #7] + 800aa70: 683b ldr r3, [r7, #0] + 800aa72: 2204 movs r2, #4 + 800aa74: 801a strh r2, [r3, #0] + 800aa76: 4b03 ldr r3, [pc, #12] @ (800aa84 ) + 800aa78: 4618 mov r0, r3 + 800aa7a: 370c adds r7, #12 + 800aa7c: 46bd mov sp, r7 + 800aa7e: f85d 7b04 ldr.w r7, [sp], #4 + 800aa82: 4770 bx lr + 800aa84: 20000180 .word 0x20000180 + +0800aa88 : + 800aa88: b580 push {r7, lr} + 800aa8a: b082 sub sp, #8 + 800aa8c: af00 add r7, sp, #0 + 800aa8e: 4603 mov r3, r0 + 800aa90: 6039 str r1, [r7, #0] + 800aa92: 71fb strb r3, [r7, #7] + 800aa94: 79fb ldrb r3, [r7, #7] + 800aa96: 2b00 cmp r3, #0 + 800aa98: d105 bne.n 800aaa6 + 800aa9a: 683a ldr r2, [r7, #0] + 800aa9c: 4907 ldr r1, [pc, #28] @ (800aabc ) + 800aa9e: 4808 ldr r0, [pc, #32] @ (800aac0 ) + 800aaa0: f7ff fed6 bl 800a850 + 800aaa4: e004 b.n 800aab0 + 800aaa6: 683a ldr r2, [r7, #0] + 800aaa8: 4904 ldr r1, [pc, #16] @ (800aabc ) + 800aaaa: 4805 ldr r0, [pc, #20] @ (800aac0 ) + 800aaac: f7ff fed0 bl 800a850 + 800aab0: 4b02 ldr r3, [pc, #8] @ (800aabc ) + 800aab2: 4618 mov r0, r3 + 800aab4: 3708 adds r7, #8 + 800aab6: 46bd mov sp, r7 + 800aab8: bd80 pop {r7, pc} + 800aaba: bf00 nop + 800aabc: 20001064 .word 0x20001064 + 800aac0: 0800b3dc .word 0x0800b3dc + +0800aac4 : + 800aac4: b580 push {r7, lr} + 800aac6: b082 sub sp, #8 + 800aac8: af00 add r7, sp, #0 + 800aaca: 4603 mov r3, r0 + 800aacc: 6039 str r1, [r7, #0] + 800aace: 71fb strb r3, [r7, #7] + 800aad0: 683a ldr r2, [r7, #0] + 800aad2: 4904 ldr r1, [pc, #16] @ (800aae4 ) + 800aad4: 4804 ldr r0, [pc, #16] @ (800aae8 ) + 800aad6: f7ff febb bl 800a850 + 800aada: 4b02 ldr r3, [pc, #8] @ (800aae4 ) + 800aadc: 4618 mov r0, r3 + 800aade: 3708 adds r7, #8 + 800aae0: 46bd mov sp, r7 + 800aae2: bd80 pop {r7, pc} + 800aae4: 20001064 .word 0x20001064 + 800aae8: 0800b3f0 .word 0x0800b3f0 + +0800aaec : + 800aaec: b580 push {r7, lr} + 800aaee: b082 sub sp, #8 + 800aaf0: af00 add r7, sp, #0 + 800aaf2: 4603 mov r3, r0 + 800aaf4: 6039 str r1, [r7, #0] + 800aaf6: 71fb strb r3, [r7, #7] + 800aaf8: 683b ldr r3, [r7, #0] + 800aafa: 221a movs r2, #26 + 800aafc: 801a strh r2, [r3, #0] + 800aafe: f000 f855 bl 800abac + 800ab02: 4b02 ldr r3, [pc, #8] @ (800ab0c ) + 800ab04: 4618 mov r0, r3 + 800ab06: 3708 adds r7, #8 + 800ab08: 46bd mov sp, r7 + 800ab0a: bd80 pop {r7, pc} + 800ab0c: 20000184 .word 0x20000184 + +0800ab10 : + 800ab10: b580 push {r7, lr} + 800ab12: b082 sub sp, #8 + 800ab14: af00 add r7, sp, #0 + 800ab16: 4603 mov r3, r0 + 800ab18: 6039 str r1, [r7, #0] + 800ab1a: 71fb strb r3, [r7, #7] + 800ab1c: 79fb ldrb r3, [r7, #7] + 800ab1e: 2b00 cmp r3, #0 + 800ab20: d105 bne.n 800ab2e + 800ab22: 683a ldr r2, [r7, #0] + 800ab24: 4907 ldr r1, [pc, #28] @ (800ab44 ) + 800ab26: 4808 ldr r0, [pc, #32] @ (800ab48 ) + 800ab28: f7ff fe92 bl 800a850 + 800ab2c: e004 b.n 800ab38 + 800ab2e: 683a ldr r2, [r7, #0] + 800ab30: 4904 ldr r1, [pc, #16] @ (800ab44 ) + 800ab32: 4805 ldr r0, [pc, #20] @ (800ab48 ) + 800ab34: f7ff fe8c bl 800a850 + 800ab38: 4b02 ldr r3, [pc, #8] @ (800ab44 ) + 800ab3a: 4618 mov r0, r3 + 800ab3c: 3708 adds r7, #8 + 800ab3e: 46bd mov sp, r7 + 800ab40: bd80 pop {r7, pc} + 800ab42: bf00 nop + 800ab44: 20001064 .word 0x20001064 + 800ab48: 0800b3fc .word 0x0800b3fc + +0800ab4c : + 800ab4c: b580 push {r7, lr} + 800ab4e: b082 sub sp, #8 + 800ab50: af00 add r7, sp, #0 + 800ab52: 4603 mov r3, r0 + 800ab54: 6039 str r1, [r7, #0] + 800ab56: 71fb strb r3, [r7, #7] + 800ab58: 79fb ldrb r3, [r7, #7] + 800ab5a: 2b00 cmp r3, #0 + 800ab5c: d105 bne.n 800ab6a + 800ab5e: 683a ldr r2, [r7, #0] + 800ab60: 4907 ldr r1, [pc, #28] @ (800ab80 ) + 800ab62: 4808 ldr r0, [pc, #32] @ (800ab84 ) + 800ab64: f7ff fe74 bl 800a850 + 800ab68: e004 b.n 800ab74 + 800ab6a: 683a ldr r2, [r7, #0] + 800ab6c: 4904 ldr r1, [pc, #16] @ (800ab80 ) + 800ab6e: 4805 ldr r0, [pc, #20] @ (800ab84 ) + 800ab70: f7ff fe6e bl 800a850 + 800ab74: 4b02 ldr r3, [pc, #8] @ (800ab80 ) + 800ab76: 4618 mov r0, r3 + 800ab78: 3708 adds r7, #8 + 800ab7a: 46bd mov sp, r7 + 800ab7c: bd80 pop {r7, pc} + 800ab7e: bf00 nop + 800ab80: 20001064 .word 0x20001064 + 800ab84: 0800b408 .word 0x0800b408 + +0800ab88 : + 800ab88: b480 push {r7} + 800ab8a: b083 sub sp, #12 + 800ab8c: af00 add r7, sp, #0 + 800ab8e: 4603 mov r3, r0 + 800ab90: 6039 str r1, [r7, #0] + 800ab92: 71fb strb r3, [r7, #7] + 800ab94: 683b ldr r3, [r7, #0] + 800ab96: 220c movs r2, #12 + 800ab98: 801a strh r2, [r3, #0] + 800ab9a: 4b03 ldr r3, [pc, #12] @ (800aba8 ) + 800ab9c: 4618 mov r0, r3 + 800ab9e: 370c adds r7, #12 + 800aba0: 46bd mov sp, r7 + 800aba2: f85d 7b04 ldr.w r7, [sp], #4 + 800aba6: 4770 bx lr + 800aba8: 20000174 .word 0x20000174 + +0800abac : + 800abac: b580 push {r7, lr} + 800abae: b084 sub sp, #16 + 800abb0: af00 add r7, sp, #0 + 800abb2: 4b0f ldr r3, [pc, #60] @ (800abf0 ) + 800abb4: 681b ldr r3, [r3, #0] + 800abb6: 60fb str r3, [r7, #12] + 800abb8: 4b0e ldr r3, [pc, #56] @ (800abf4 ) + 800abba: 681b ldr r3, [r3, #0] + 800abbc: 60bb str r3, [r7, #8] + 800abbe: 4b0e ldr r3, [pc, #56] @ (800abf8 ) + 800abc0: 681b ldr r3, [r3, #0] + 800abc2: 607b str r3, [r7, #4] + 800abc4: 68fa ldr r2, [r7, #12] + 800abc6: 687b ldr r3, [r7, #4] + 800abc8: 4413 add r3, r2 + 800abca: 60fb str r3, [r7, #12] + 800abcc: 68fb ldr r3, [r7, #12] + 800abce: 2b00 cmp r3, #0 + 800abd0: d009 beq.n 800abe6 + 800abd2: 2208 movs r2, #8 + 800abd4: 4909 ldr r1, [pc, #36] @ (800abfc ) + 800abd6: 68f8 ldr r0, [r7, #12] + 800abd8: f000 f814 bl 800ac04 + 800abdc: 2204 movs r2, #4 + 800abde: 4908 ldr r1, [pc, #32] @ (800ac00 ) + 800abe0: 68b8 ldr r0, [r7, #8] + 800abe2: f000 f80f bl 800ac04 + 800abe6: bf00 nop + 800abe8: 3710 adds r7, #16 + 800abea: 46bd mov sp, r7 + 800abec: bd80 pop {r7, pc} + 800abee: bf00 nop + 800abf0: 1fff7a10 .word 0x1fff7a10 + 800abf4: 1fff7a14 .word 0x1fff7a14 + 800abf8: 1fff7a18 .word 0x1fff7a18 + 800abfc: 20000186 .word 0x20000186 + 800ac00: 20000196 .word 0x20000196 + +0800ac04 : + 800ac04: b480 push {r7} + 800ac06: b087 sub sp, #28 + 800ac08: af00 add r7, sp, #0 + 800ac0a: 60f8 str r0, [r7, #12] + 800ac0c: 60b9 str r1, [r7, #8] + 800ac0e: 4613 mov r3, r2 + 800ac10: 71fb strb r3, [r7, #7] + 800ac12: 2300 movs r3, #0 + 800ac14: 75fb strb r3, [r7, #23] + 800ac16: 2300 movs r3, #0 + 800ac18: 75fb strb r3, [r7, #23] + 800ac1a: e027 b.n 800ac6c + 800ac1c: 68fb ldr r3, [r7, #12] + 800ac1e: 0f1b lsrs r3, r3, #28 + 800ac20: 2b09 cmp r3, #9 + 800ac22: d80b bhi.n 800ac3c + 800ac24: 68fb ldr r3, [r7, #12] + 800ac26: 0f1b lsrs r3, r3, #28 + 800ac28: b2da uxtb r2, r3 + 800ac2a: 7dfb ldrb r3, [r7, #23] + 800ac2c: 005b lsls r3, r3, #1 + 800ac2e: 4619 mov r1, r3 + 800ac30: 68bb ldr r3, [r7, #8] + 800ac32: 440b add r3, r1 + 800ac34: 3230 adds r2, #48 @ 0x30 + 800ac36: b2d2 uxtb r2, r2 + 800ac38: 701a strb r2, [r3, #0] + 800ac3a: e00a b.n 800ac52 + 800ac3c: 68fb ldr r3, [r7, #12] + 800ac3e: 0f1b lsrs r3, r3, #28 + 800ac40: b2da uxtb r2, r3 + 800ac42: 7dfb ldrb r3, [r7, #23] + 800ac44: 005b lsls r3, r3, #1 + 800ac46: 4619 mov r1, r3 + 800ac48: 68bb ldr r3, [r7, #8] + 800ac4a: 440b add r3, r1 + 800ac4c: 3237 adds r2, #55 @ 0x37 + 800ac4e: b2d2 uxtb r2, r2 + 800ac50: 701a strb r2, [r3, #0] + 800ac52: 68fb ldr r3, [r7, #12] + 800ac54: 011b lsls r3, r3, #4 + 800ac56: 60fb str r3, [r7, #12] + 800ac58: 7dfb ldrb r3, [r7, #23] + 800ac5a: 005b lsls r3, r3, #1 + 800ac5c: 3301 adds r3, #1 + 800ac5e: 68ba ldr r2, [r7, #8] + 800ac60: 4413 add r3, r2 + 800ac62: 2200 movs r2, #0 + 800ac64: 701a strb r2, [r3, #0] + 800ac66: 7dfb ldrb r3, [r7, #23] + 800ac68: 3301 adds r3, #1 + 800ac6a: 75fb strb r3, [r7, #23] + 800ac6c: 7dfa ldrb r2, [r7, #23] + 800ac6e: 79fb ldrb r3, [r7, #7] + 800ac70: 429a cmp r2, r3 + 800ac72: d3d3 bcc.n 800ac1c + 800ac74: bf00 nop + 800ac76: bf00 nop + 800ac78: 371c adds r7, #28 + 800ac7a: 46bd mov sp, r7 + 800ac7c: f85d 7b04 ldr.w r7, [sp], #4 + 800ac80: 4770 bx lr + ... + +0800ac84 : + 800ac84: b580 push {r7, lr} + 800ac86: b0a0 sub sp, #128 @ 0x80 + 800ac88: af00 add r7, sp, #0 + 800ac8a: 6078 str r0, [r7, #4] + 800ac8c: f107 036c add.w r3, r7, #108 @ 0x6c + 800ac90: 2200 movs r2, #0 + 800ac92: 601a str r2, [r3, #0] + 800ac94: 605a str r2, [r3, #4] + 800ac96: 609a str r2, [r3, #8] + 800ac98: 60da str r2, [r3, #12] + 800ac9a: 611a str r2, [r3, #16] + 800ac9c: f107 0310 add.w r3, r7, #16 + 800aca0: 225c movs r2, #92 @ 0x5c + 800aca2: 2100 movs r1, #0 + 800aca4: 4618 mov r0, r3 + 800aca6: f000 fb53 bl 800b350 + 800acaa: 687b ldr r3, [r7, #4] + 800acac: 681b ldr r3, [r3, #0] + 800acae: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 800acb2: d149 bne.n 800ad48 + 800acb4: f44f 7380 mov.w r3, #256 @ 0x100 + 800acb8: 613b str r3, [r7, #16] + 800acba: 2300 movs r3, #0 + 800acbc: 667b str r3, [r7, #100] @ 0x64 + 800acbe: f107 0310 add.w r3, r7, #16 + 800acc2: 4618 mov r0, r3 + 800acc4: f7f9 fd1e bl 8004704 + 800acc8: 4603 mov r3, r0 + 800acca: 2b00 cmp r3, #0 + 800accc: d001 beq.n 800acd2 + 800acce: f7f6 fabb bl 8001248 + 800acd2: 2300 movs r3, #0 + 800acd4: 60fb str r3, [r7, #12] + 800acd6: 4b1e ldr r3, [pc, #120] @ (800ad50 ) + 800acd8: 6b1b ldr r3, [r3, #48] @ 0x30 + 800acda: 4a1d ldr r2, [pc, #116] @ (800ad50 ) + 800acdc: f043 0301 orr.w r3, r3, #1 + 800ace0: 6313 str r3, [r2, #48] @ 0x30 + 800ace2: 4b1b ldr r3, [pc, #108] @ (800ad50 ) + 800ace4: 6b1b ldr r3, [r3, #48] @ 0x30 + 800ace6: f003 0301 and.w r3, r3, #1 + 800acea: 60fb str r3, [r7, #12] + 800acec: 68fb ldr r3, [r7, #12] + 800acee: f44f 53c0 mov.w r3, #6144 @ 0x1800 + 800acf2: 66fb str r3, [r7, #108] @ 0x6c + 800acf4: 2302 movs r3, #2 + 800acf6: 673b str r3, [r7, #112] @ 0x70 + 800acf8: 2300 movs r3, #0 + 800acfa: 677b str r3, [r7, #116] @ 0x74 + 800acfc: 2303 movs r3, #3 + 800acfe: 67bb str r3, [r7, #120] @ 0x78 + 800ad00: 230a movs r3, #10 + 800ad02: 67fb str r3, [r7, #124] @ 0x7c + 800ad04: f107 036c add.w r3, r7, #108 @ 0x6c + 800ad08: 4619 mov r1, r3 + 800ad0a: 4812 ldr r0, [pc, #72] @ (800ad54 ) + 800ad0c: f7f7 fe50 bl 80029b0 + 800ad10: 4b0f ldr r3, [pc, #60] @ (800ad50 ) + 800ad12: 6b5b ldr r3, [r3, #52] @ 0x34 + 800ad14: 4a0e ldr r2, [pc, #56] @ (800ad50 ) + 800ad16: f043 0380 orr.w r3, r3, #128 @ 0x80 + 800ad1a: 6353 str r3, [r2, #52] @ 0x34 + 800ad1c: 2300 movs r3, #0 + 800ad1e: 60bb str r3, [r7, #8] + 800ad20: 4b0b ldr r3, [pc, #44] @ (800ad50 ) + 800ad22: 6c5b ldr r3, [r3, #68] @ 0x44 + 800ad24: 4a0a ldr r2, [pc, #40] @ (800ad50 ) + 800ad26: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 800ad2a: 6453 str r3, [r2, #68] @ 0x44 + 800ad2c: 4b08 ldr r3, [pc, #32] @ (800ad50 ) + 800ad2e: 6c5b ldr r3, [r3, #68] @ 0x44 + 800ad30: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 800ad34: 60bb str r3, [r7, #8] + 800ad36: 68bb ldr r3, [r7, #8] + 800ad38: 2200 movs r2, #0 + 800ad3a: 2100 movs r1, #0 + 800ad3c: 2043 movs r0, #67 @ 0x43 + 800ad3e: f7f7 f9fe bl 800213e + 800ad42: 2043 movs r0, #67 @ 0x43 + 800ad44: f7f7 fa17 bl 8002176 + 800ad48: bf00 nop + 800ad4a: 3780 adds r7, #128 @ 0x80 + 800ad4c: 46bd mov sp, r7 + 800ad4e: bd80 pop {r7, pc} + 800ad50: 40023800 .word 0x40023800 + 800ad54: 40020000 .word 0x40020000 + +0800ad58 : + 800ad58: b580 push {r7, lr} + 800ad5a: b082 sub sp, #8 + 800ad5c: af00 add r7, sp, #0 + 800ad5e: 6078 str r0, [r7, #4] + 800ad60: 687b ldr r3, [r7, #4] + 800ad62: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0 + 800ad66: 687b ldr r3, [r7, #4] + 800ad68: f203 439c addw r3, r3, #1180 @ 0x49c + 800ad6c: 4619 mov r1, r3 + 800ad6e: 4610 mov r0, r2 + 800ad70: f7fe fbcb bl 800950a + 800ad74: bf00 nop + 800ad76: 3708 adds r7, #8 + 800ad78: 46bd mov sp, r7 + 800ad7a: bd80 pop {r7, pc} + +0800ad7c : + 800ad7c: b580 push {r7, lr} + 800ad7e: b082 sub sp, #8 + 800ad80: af00 add r7, sp, #0 + 800ad82: 6078 str r0, [r7, #4] + 800ad84: 460b mov r3, r1 + 800ad86: 70fb strb r3, [r7, #3] + 800ad88: 687b ldr r3, [r7, #4] + 800ad8a: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 + 800ad8e: 78fa ldrb r2, [r7, #3] + 800ad90: 6879 ldr r1, [r7, #4] + 800ad92: 4613 mov r3, r2 + 800ad94: 00db lsls r3, r3, #3 + 800ad96: 4413 add r3, r2 + 800ad98: 009b lsls r3, r3, #2 + 800ad9a: 440b add r3, r1 + 800ad9c: f503 7318 add.w r3, r3, #608 @ 0x260 + 800ada0: 681a ldr r2, [r3, #0] + 800ada2: 78fb ldrb r3, [r7, #3] + 800ada4: 4619 mov r1, r3 + 800ada6: f7fe fc05 bl 80095b4 + 800adaa: bf00 nop + 800adac: 3708 adds r7, #8 + 800adae: 46bd mov sp, r7 + 800adb0: bd80 pop {r7, pc} + +0800adb2 : + 800adb2: b580 push {r7, lr} + 800adb4: b082 sub sp, #8 + 800adb6: af00 add r7, sp, #0 + 800adb8: 6078 str r0, [r7, #4] + 800adba: 460b mov r3, r1 + 800adbc: 70fb strb r3, [r7, #3] + 800adbe: 687b ldr r3, [r7, #4] + 800adc0: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 + 800adc4: 78fa ldrb r2, [r7, #3] + 800adc6: 6879 ldr r1, [r7, #4] + 800adc8: 4613 mov r3, r2 + 800adca: 00db lsls r3, r3, #3 + 800adcc: 4413 add r3, r2 + 800adce: 009b lsls r3, r3, #2 + 800add0: 440b add r3, r1 + 800add2: 3320 adds r3, #32 + 800add4: 681a ldr r2, [r3, #0] + 800add6: 78fb ldrb r3, [r7, #3] + 800add8: 4619 mov r1, r3 + 800adda: f7fe fca7 bl 800972c + 800adde: bf00 nop + 800ade0: 3708 adds r7, #8 + 800ade2: 46bd mov sp, r7 + 800ade4: bd80 pop {r7, pc} + +0800ade6 : + 800ade6: b580 push {r7, lr} + 800ade8: b082 sub sp, #8 + 800adea: af00 add r7, sp, #0 + 800adec: 6078 str r0, [r7, #4] + 800adee: 687b ldr r3, [r7, #4] + 800adf0: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 + 800adf4: 4618 mov r0, r3 + 800adf6: f7fe fdeb bl 80099d0 + 800adfa: bf00 nop + 800adfc: 3708 adds r7, #8 + 800adfe: 46bd mov sp, r7 + 800ae00: bd80 pop {r7, pc} + +0800ae02 : + 800ae02: b580 push {r7, lr} + 800ae04: b084 sub sp, #16 + 800ae06: af00 add r7, sp, #0 + 800ae08: 6078 str r0, [r7, #4] + 800ae0a: 2301 movs r3, #1 + 800ae0c: 73fb strb r3, [r7, #15] + 800ae0e: 687b ldr r3, [r7, #4] + 800ae10: 79db ldrb r3, [r3, #7] + 800ae12: 2b00 cmp r3, #0 + 800ae14: d102 bne.n 800ae1c + 800ae16: 2300 movs r3, #0 + 800ae18: 73fb strb r3, [r7, #15] + 800ae1a: e008 b.n 800ae2e + 800ae1c: 687b ldr r3, [r7, #4] + 800ae1e: 79db ldrb r3, [r3, #7] + 800ae20: 2b02 cmp r3, #2 + 800ae22: d102 bne.n 800ae2a + 800ae24: 2301 movs r3, #1 + 800ae26: 73fb strb r3, [r7, #15] + 800ae28: e001 b.n 800ae2e + 800ae2a: f7f6 fa0d bl 8001248 + 800ae2e: 687b ldr r3, [r7, #4] + 800ae30: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 + 800ae34: 7bfa ldrb r2, [r7, #15] + 800ae36: 4611 mov r1, r2 + 800ae38: 4618 mov r0, r3 + 800ae3a: f7fe fd85 bl 8009948 + 800ae3e: 687b ldr r3, [r7, #4] + 800ae40: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 + 800ae44: 4618 mov r0, r3 + 800ae46: f7fe fd2c bl 80098a2 + 800ae4a: bf00 nop + 800ae4c: 3710 adds r7, #16 + 800ae4e: 46bd mov sp, r7 + 800ae50: bd80 pop {r7, pc} + ... + +0800ae54 : + 800ae54: b580 push {r7, lr} + 800ae56: b082 sub sp, #8 + 800ae58: af00 add r7, sp, #0 + 800ae5a: 6078 str r0, [r7, #4] + 800ae5c: 687b ldr r3, [r7, #4] + 800ae5e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 + 800ae62: 4618 mov r0, r3 + 800ae64: f7fe fd80 bl 8009968 + 800ae68: 687b ldr r3, [r7, #4] + 800ae6a: 681b ldr r3, [r3, #0] + 800ae6c: f503 6360 add.w r3, r3, #3584 @ 0xe00 + 800ae70: 681b ldr r3, [r3, #0] + 800ae72: 687a ldr r2, [r7, #4] + 800ae74: 6812 ldr r2, [r2, #0] + 800ae76: f502 6260 add.w r2, r2, #3584 @ 0xe00 + 800ae7a: f043 0301 orr.w r3, r3, #1 + 800ae7e: 6013 str r3, [r2, #0] + 800ae80: 687b ldr r3, [r7, #4] + 800ae82: 7adb ldrb r3, [r3, #11] + 800ae84: 2b00 cmp r3, #0 + 800ae86: d005 beq.n 800ae94 + 800ae88: 4b04 ldr r3, [pc, #16] @ (800ae9c ) + 800ae8a: 691b ldr r3, [r3, #16] + 800ae8c: 4a03 ldr r2, [pc, #12] @ (800ae9c ) + 800ae8e: f043 0306 orr.w r3, r3, #6 + 800ae92: 6113 str r3, [r2, #16] + 800ae94: bf00 nop + 800ae96: 3708 adds r7, #8 + 800ae98: 46bd mov sp, r7 + 800ae9a: bd80 pop {r7, pc} + 800ae9c: e000ed00 .word 0xe000ed00 + +0800aea0 : + 800aea0: b580 push {r7, lr} + 800aea2: b082 sub sp, #8 + 800aea4: af00 add r7, sp, #0 + 800aea6: 6078 str r0, [r7, #4] + 800aea8: 687b ldr r3, [r7, #4] + 800aeaa: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 + 800aeae: 4618 mov r0, r3 + 800aeb0: f7fe fd76 bl 80099a0 + 800aeb4: bf00 nop + 800aeb6: 3708 adds r7, #8 + 800aeb8: 46bd mov sp, r7 + 800aeba: bd80 pop {r7, pc} + +0800aebc : + 800aebc: b580 push {r7, lr} + 800aebe: b082 sub sp, #8 + 800aec0: af00 add r7, sp, #0 + 800aec2: 6078 str r0, [r7, #4] + 800aec4: 460b mov r3, r1 + 800aec6: 70fb strb r3, [r7, #3] + 800aec8: 687b ldr r3, [r7, #4] + 800aeca: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 + 800aece: 78fa ldrb r2, [r7, #3] + 800aed0: 4611 mov r1, r2 + 800aed2: 4618 mov r0, r3 + 800aed4: f7fe fdce bl 8009a74 + 800aed8: bf00 nop + 800aeda: 3708 adds r7, #8 + 800aedc: 46bd mov sp, r7 + 800aede: bd80 pop {r7, pc} + +0800aee0 : + 800aee0: b580 push {r7, lr} + 800aee2: b082 sub sp, #8 + 800aee4: af00 add r7, sp, #0 + 800aee6: 6078 str r0, [r7, #4] + 800aee8: 460b mov r3, r1 + 800aeea: 70fb strb r3, [r7, #3] + 800aeec: 687b ldr r3, [r7, #4] + 800aeee: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 + 800aef2: 78fa ldrb r2, [r7, #3] + 800aef4: 4611 mov r1, r2 + 800aef6: 4618 mov r0, r3 + 800aef8: f7fe fd8a bl 8009a10 + 800aefc: bf00 nop + 800aefe: 3708 adds r7, #8 + 800af00: 46bd mov sp, r7 + 800af02: bd80 pop {r7, pc} + +0800af04 : + 800af04: b580 push {r7, lr} + 800af06: b082 sub sp, #8 + 800af08: af00 add r7, sp, #0 + 800af0a: 6078 str r0, [r7, #4] + 800af0c: 687b ldr r3, [r7, #4] + 800af0e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 + 800af12: 4618 mov r0, r3 + 800af14: f7fe fde0 bl 8009ad8 + 800af18: bf00 nop + 800af1a: 3708 adds r7, #8 + 800af1c: 46bd mov sp, r7 + 800af1e: bd80 pop {r7, pc} + +0800af20 : + 800af20: b580 push {r7, lr} + 800af22: b082 sub sp, #8 + 800af24: af00 add r7, sp, #0 + 800af26: 6078 str r0, [r7, #4] + 800af28: 687b ldr r3, [r7, #4] + 800af2a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 + 800af2e: 4618 mov r0, r3 + 800af30: f7fe fddd bl 8009aee + 800af34: bf00 nop + 800af36: 3708 adds r7, #8 + 800af38: 46bd mov sp, r7 + 800af3a: bd80 pop {r7, pc} + +0800af3c : + 800af3c: b580 push {r7, lr} + 800af3e: b082 sub sp, #8 + 800af40: af00 add r7, sp, #0 + 800af42: 6078 str r0, [r7, #4] + 800af44: 687b ldr r3, [r7, #4] + 800af46: 781b ldrb r3, [r3, #0] + 800af48: 2b00 cmp r3, #0 + 800af4a: d13c bne.n 800afc6 + 800af4c: 4a20 ldr r2, [pc, #128] @ (800afd0 ) + 800af4e: 687b ldr r3, [r7, #4] + 800af50: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0 + 800af54: 687b ldr r3, [r7, #4] + 800af56: 4a1e ldr r2, [pc, #120] @ (800afd0 ) + 800af58: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 + 800af5c: 4b1c ldr r3, [pc, #112] @ (800afd0 ) + 800af5e: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 + 800af62: 601a str r2, [r3, #0] + 800af64: 4b1a ldr r3, [pc, #104] @ (800afd0 ) + 800af66: 2206 movs r2, #6 + 800af68: 711a strb r2, [r3, #4] + 800af6a: 4b19 ldr r3, [pc, #100] @ (800afd0 ) + 800af6c: 2202 movs r2, #2 + 800af6e: 71da strb r2, [r3, #7] + 800af70: 4b17 ldr r3, [pc, #92] @ (800afd0 ) + 800af72: 2200 movs r2, #0 + 800af74: 719a strb r2, [r3, #6] + 800af76: 4b16 ldr r3, [pc, #88] @ (800afd0 ) + 800af78: 2202 movs r2, #2 + 800af7a: 725a strb r2, [r3, #9] + 800af7c: 4b14 ldr r3, [pc, #80] @ (800afd0 ) + 800af7e: 2200 movs r2, #0 + 800af80: 729a strb r2, [r3, #10] + 800af82: 4b13 ldr r3, [pc, #76] @ (800afd0 ) + 800af84: 2200 movs r2, #0 + 800af86: 72da strb r2, [r3, #11] + 800af88: 4b11 ldr r3, [pc, #68] @ (800afd0 ) + 800af8a: 2200 movs r2, #0 + 800af8c: 731a strb r2, [r3, #12] + 800af8e: 4b10 ldr r3, [pc, #64] @ (800afd0 ) + 800af90: 2200 movs r2, #0 + 800af92: 739a strb r2, [r3, #14] + 800af94: 4b0e ldr r3, [pc, #56] @ (800afd0 ) + 800af96: 2200 movs r2, #0 + 800af98: 73da strb r2, [r3, #15] + 800af9a: 480d ldr r0, [pc, #52] @ (800afd0 ) + 800af9c: f7f8 f812 bl 8002fc4 + 800afa0: 4603 mov r3, r0 + 800afa2: 2b00 cmp r3, #0 + 800afa4: d001 beq.n 800afaa + 800afa6: f7f6 f94f bl 8001248 + 800afaa: 2180 movs r1, #128 @ 0x80 + 800afac: 4808 ldr r0, [pc, #32] @ (800afd0 ) + 800afae: f7f9 fa5a bl 8004466 + 800afb2: 2240 movs r2, #64 @ 0x40 + 800afb4: 2100 movs r1, #0 + 800afb6: 4806 ldr r0, [pc, #24] @ (800afd0 ) + 800afb8: f7f9 fa0e bl 80043d8 + 800afbc: 2280 movs r2, #128 @ 0x80 + 800afbe: 2101 movs r1, #1 + 800afc0: 4803 ldr r0, [pc, #12] @ (800afd0 ) + 800afc2: f7f9 fa09 bl 80043d8 + 800afc6: 2300 movs r3, #0 + 800afc8: 4618 mov r0, r3 + 800afca: 3708 adds r7, #8 + 800afcc: 46bd mov sp, r7 + 800afce: bd80 pop {r7, pc} + 800afd0: 20001264 .word 0x20001264 + +0800afd4 : + 800afd4: b580 push {r7, lr} + 800afd6: b084 sub sp, #16 + 800afd8: af00 add r7, sp, #0 + 800afda: 6078 str r0, [r7, #4] + 800afdc: 2300 movs r3, #0 + 800afde: 73fb strb r3, [r7, #15] + 800afe0: 2300 movs r3, #0 + 800afe2: 73bb strb r3, [r7, #14] + 800afe4: 687b ldr r3, [r7, #4] + 800afe6: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 + 800afea: 4618 mov r0, r3 + 800afec: f7f8 f900 bl 80031f0 + 800aff0: 4603 mov r3, r0 + 800aff2: 73fb strb r3, [r7, #15] + 800aff4: 7bfb ldrb r3, [r7, #15] + 800aff6: 4618 mov r0, r3 + 800aff8: f000 f97e bl 800b2f8 + 800affc: 4603 mov r3, r0 + 800affe: 73bb strb r3, [r7, #14] + 800b000: 7bbb ldrb r3, [r7, #14] + 800b002: 4618 mov r0, r3 + 800b004: 3710 adds r7, #16 + 800b006: 46bd mov sp, r7 + 800b008: bd80 pop {r7, pc} + +0800b00a : + 800b00a: b580 push {r7, lr} + 800b00c: b084 sub sp, #16 + 800b00e: af00 add r7, sp, #0 + 800b010: 6078 str r0, [r7, #4] + 800b012: 4608 mov r0, r1 + 800b014: 4611 mov r1, r2 + 800b016: 461a mov r2, r3 + 800b018: 4603 mov r3, r0 + 800b01a: 70fb strb r3, [r7, #3] + 800b01c: 460b mov r3, r1 + 800b01e: 70bb strb r3, [r7, #2] + 800b020: 4613 mov r3, r2 + 800b022: 803b strh r3, [r7, #0] + 800b024: 2300 movs r3, #0 + 800b026: 73fb strb r3, [r7, #15] + 800b028: 2300 movs r3, #0 + 800b02a: 73bb strb r3, [r7, #14] + 800b02c: 687b ldr r3, [r7, #4] + 800b02e: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 + 800b032: 78bb ldrb r3, [r7, #2] + 800b034: 883a ldrh r2, [r7, #0] + 800b036: 78f9 ldrb r1, [r7, #3] + 800b038: f7f8 fe01 bl 8003c3e + 800b03c: 4603 mov r3, r0 + 800b03e: 73fb strb r3, [r7, #15] + 800b040: 7bfb ldrb r3, [r7, #15] + 800b042: 4618 mov r0, r3 + 800b044: f000 f958 bl 800b2f8 + 800b048: 4603 mov r3, r0 + 800b04a: 73bb strb r3, [r7, #14] + 800b04c: 7bbb ldrb r3, [r7, #14] + 800b04e: 4618 mov r0, r3 + 800b050: 3710 adds r7, #16 + 800b052: 46bd mov sp, r7 + 800b054: bd80 pop {r7, pc} + +0800b056 : + 800b056: b580 push {r7, lr} + 800b058: b084 sub sp, #16 + 800b05a: af00 add r7, sp, #0 + 800b05c: 6078 str r0, [r7, #4] + 800b05e: 460b mov r3, r1 + 800b060: 70fb strb r3, [r7, #3] + 800b062: 2300 movs r3, #0 + 800b064: 73fb strb r3, [r7, #15] + 800b066: 2300 movs r3, #0 + 800b068: 73bb strb r3, [r7, #14] + 800b06a: 687b ldr r3, [r7, #4] + 800b06c: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 + 800b070: 78fa ldrb r2, [r7, #3] + 800b072: 4611 mov r1, r2 + 800b074: 4618 mov r0, r3 + 800b076: f7f8 fe4c bl 8003d12 + 800b07a: 4603 mov r3, r0 + 800b07c: 73fb strb r3, [r7, #15] + 800b07e: 7bfb ldrb r3, [r7, #15] + 800b080: 4618 mov r0, r3 + 800b082: f000 f939 bl 800b2f8 + 800b086: 4603 mov r3, r0 + 800b088: 73bb strb r3, [r7, #14] + 800b08a: 7bbb ldrb r3, [r7, #14] + 800b08c: 4618 mov r0, r3 + 800b08e: 3710 adds r7, #16 + 800b090: 46bd mov sp, r7 + 800b092: bd80 pop {r7, pc} + +0800b094 : + 800b094: b580 push {r7, lr} + 800b096: b084 sub sp, #16 + 800b098: af00 add r7, sp, #0 + 800b09a: 6078 str r0, [r7, #4] + 800b09c: 460b mov r3, r1 + 800b09e: 70fb strb r3, [r7, #3] + 800b0a0: 2300 movs r3, #0 + 800b0a2: 73fb strb r3, [r7, #15] + 800b0a4: 2300 movs r3, #0 + 800b0a6: 73bb strb r3, [r7, #14] + 800b0a8: 687b ldr r3, [r7, #4] + 800b0aa: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 + 800b0ae: 78fa ldrb r2, [r7, #3] + 800b0b0: 4611 mov r1, r2 + 800b0b2: 4618 mov r0, r3 + 800b0b4: f7f8 feec bl 8003e90 + 800b0b8: 4603 mov r3, r0 + 800b0ba: 73fb strb r3, [r7, #15] + 800b0bc: 7bfb ldrb r3, [r7, #15] + 800b0be: 4618 mov r0, r3 + 800b0c0: f000 f91a bl 800b2f8 + 800b0c4: 4603 mov r3, r0 + 800b0c6: 73bb strb r3, [r7, #14] + 800b0c8: 7bbb ldrb r3, [r7, #14] + 800b0ca: 4618 mov r0, r3 + 800b0cc: 3710 adds r7, #16 + 800b0ce: 46bd mov sp, r7 + 800b0d0: bd80 pop {r7, pc} + +0800b0d2 : + 800b0d2: b580 push {r7, lr} + 800b0d4: b084 sub sp, #16 + 800b0d6: af00 add r7, sp, #0 + 800b0d8: 6078 str r0, [r7, #4] + 800b0da: 460b mov r3, r1 + 800b0dc: 70fb strb r3, [r7, #3] + 800b0de: 2300 movs r3, #0 + 800b0e0: 73fb strb r3, [r7, #15] + 800b0e2: 2300 movs r3, #0 + 800b0e4: 73bb strb r3, [r7, #14] + 800b0e6: 687b ldr r3, [r7, #4] + 800b0e8: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 + 800b0ec: 78fa ldrb r2, [r7, #3] + 800b0ee: 4611 mov r1, r2 + 800b0f0: 4618 mov r0, r3 + 800b0f2: f7f8 ff30 bl 8003f56 + 800b0f6: 4603 mov r3, r0 + 800b0f8: 73fb strb r3, [r7, #15] + 800b0fa: 7bfb ldrb r3, [r7, #15] + 800b0fc: 4618 mov r0, r3 + 800b0fe: f000 f8fb bl 800b2f8 + 800b102: 4603 mov r3, r0 + 800b104: 73bb strb r3, [r7, #14] + 800b106: 7bbb ldrb r3, [r7, #14] + 800b108: 4618 mov r0, r3 + 800b10a: 3710 adds r7, #16 + 800b10c: 46bd mov sp, r7 + 800b10e: bd80 pop {r7, pc} + +0800b110 : + 800b110: b480 push {r7} + 800b112: b085 sub sp, #20 + 800b114: af00 add r7, sp, #0 + 800b116: 6078 str r0, [r7, #4] + 800b118: 460b mov r3, r1 + 800b11a: 70fb strb r3, [r7, #3] + 800b11c: 687b ldr r3, [r7, #4] + 800b11e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 + 800b122: 60fb str r3, [r7, #12] + 800b124: f997 3003 ldrsb.w r3, [r7, #3] + 800b128: 2b00 cmp r3, #0 + 800b12a: da0b bge.n 800b144 + 800b12c: 78fb ldrb r3, [r7, #3] + 800b12e: f003 027f and.w r2, r3, #127 @ 0x7f + 800b132: 68f9 ldr r1, [r7, #12] + 800b134: 4613 mov r3, r2 + 800b136: 00db lsls r3, r3, #3 + 800b138: 4413 add r3, r2 + 800b13a: 009b lsls r3, r3, #2 + 800b13c: 440b add r3, r1 + 800b13e: 3316 adds r3, #22 + 800b140: 781b ldrb r3, [r3, #0] + 800b142: e00b b.n 800b15c + 800b144: 78fb ldrb r3, [r7, #3] + 800b146: f003 027f and.w r2, r3, #127 @ 0x7f + 800b14a: 68f9 ldr r1, [r7, #12] + 800b14c: 4613 mov r3, r2 + 800b14e: 00db lsls r3, r3, #3 + 800b150: 4413 add r3, r2 + 800b152: 009b lsls r3, r3, #2 + 800b154: 440b add r3, r1 + 800b156: f203 2356 addw r3, r3, #598 @ 0x256 + 800b15a: 781b ldrb r3, [r3, #0] + 800b15c: 4618 mov r0, r3 + 800b15e: 3714 adds r7, #20 + 800b160: 46bd mov sp, r7 + 800b162: f85d 7b04 ldr.w r7, [sp], #4 + 800b166: 4770 bx lr + +0800b168 : + 800b168: b580 push {r7, lr} + 800b16a: b084 sub sp, #16 + 800b16c: af00 add r7, sp, #0 + 800b16e: 6078 str r0, [r7, #4] + 800b170: 460b mov r3, r1 + 800b172: 70fb strb r3, [r7, #3] + 800b174: 2300 movs r3, #0 + 800b176: 73fb strb r3, [r7, #15] + 800b178: 2300 movs r3, #0 + 800b17a: 73bb strb r3, [r7, #14] + 800b17c: 687b ldr r3, [r7, #4] + 800b17e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 + 800b182: 78fa ldrb r2, [r7, #3] + 800b184: 4611 mov r1, r2 + 800b186: 4618 mov r0, r3 + 800b188: f7f8 fd35 bl 8003bf6 + 800b18c: 4603 mov r3, r0 + 800b18e: 73fb strb r3, [r7, #15] + 800b190: 7bfb ldrb r3, [r7, #15] + 800b192: 4618 mov r0, r3 + 800b194: f000 f8b0 bl 800b2f8 + 800b198: 4603 mov r3, r0 + 800b19a: 73bb strb r3, [r7, #14] + 800b19c: 7bbb ldrb r3, [r7, #14] + 800b19e: 4618 mov r0, r3 + 800b1a0: 3710 adds r7, #16 + 800b1a2: 46bd mov sp, r7 + 800b1a4: bd80 pop {r7, pc} + +0800b1a6 : + 800b1a6: b580 push {r7, lr} + 800b1a8: b086 sub sp, #24 + 800b1aa: af00 add r7, sp, #0 + 800b1ac: 60f8 str r0, [r7, #12] + 800b1ae: 607a str r2, [r7, #4] + 800b1b0: 603b str r3, [r7, #0] + 800b1b2: 460b mov r3, r1 + 800b1b4: 72fb strb r3, [r7, #11] + 800b1b6: 2300 movs r3, #0 + 800b1b8: 75fb strb r3, [r7, #23] + 800b1ba: 2300 movs r3, #0 + 800b1bc: 75bb strb r3, [r7, #22] + 800b1be: 68fb ldr r3, [r7, #12] + 800b1c0: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 + 800b1c4: 7af9 ldrb r1, [r7, #11] + 800b1c6: 683b ldr r3, [r7, #0] + 800b1c8: 687a ldr r2, [r7, #4] + 800b1ca: f7f8 fe27 bl 8003e1c + 800b1ce: 4603 mov r3, r0 + 800b1d0: 75fb strb r3, [r7, #23] + 800b1d2: 7dfb ldrb r3, [r7, #23] + 800b1d4: 4618 mov r0, r3 + 800b1d6: f000 f88f bl 800b2f8 + 800b1da: 4603 mov r3, r0 + 800b1dc: 75bb strb r3, [r7, #22] + 800b1de: 7dbb ldrb r3, [r7, #22] + 800b1e0: 4618 mov r0, r3 + 800b1e2: 3718 adds r7, #24 + 800b1e4: 46bd mov sp, r7 + 800b1e6: bd80 pop {r7, pc} + +0800b1e8 : + 800b1e8: b580 push {r7, lr} + 800b1ea: b086 sub sp, #24 + 800b1ec: af00 add r7, sp, #0 + 800b1ee: 60f8 str r0, [r7, #12] + 800b1f0: 607a str r2, [r7, #4] + 800b1f2: 603b str r3, [r7, #0] + 800b1f4: 460b mov r3, r1 + 800b1f6: 72fb strb r3, [r7, #11] + 800b1f8: 2300 movs r3, #0 + 800b1fa: 75fb strb r3, [r7, #23] + 800b1fc: 2300 movs r3, #0 + 800b1fe: 75bb strb r3, [r7, #22] + 800b200: 68fb ldr r3, [r7, #12] + 800b202: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 + 800b206: 7af9 ldrb r1, [r7, #11] + 800b208: 683b ldr r3, [r7, #0] + 800b20a: 687a ldr r2, [r7, #4] + 800b20c: f7f8 fdcb bl 8003da6 + 800b210: 4603 mov r3, r0 + 800b212: 75fb strb r3, [r7, #23] + 800b214: 7dfb ldrb r3, [r7, #23] + 800b216: 4618 mov r0, r3 + 800b218: f000 f86e bl 800b2f8 + 800b21c: 4603 mov r3, r0 + 800b21e: 75bb strb r3, [r7, #22] + 800b220: 7dbb ldrb r3, [r7, #22] + 800b222: 4618 mov r0, r3 + 800b224: 3718 adds r7, #24 + 800b226: 46bd mov sp, r7 + 800b228: bd80 pop {r7, pc} + ... + +0800b22c : + 800b22c: b580 push {r7, lr} + 800b22e: b082 sub sp, #8 + 800b230: af00 add r7, sp, #0 + 800b232: 6078 str r0, [r7, #4] + 800b234: 460b mov r3, r1 + 800b236: 70fb strb r3, [r7, #3] + 800b238: 78fb ldrb r3, [r7, #3] + 800b23a: 2b00 cmp r3, #0 + 800b23c: d002 beq.n 800b244 + 800b23e: 2b01 cmp r3, #1 + 800b240: d01f beq.n 800b282 + 800b242: e03b b.n 800b2bc + 800b244: 687b ldr r3, [r7, #4] + 800b246: 7adb ldrb r3, [r3, #11] + 800b248: 2b00 cmp r3, #0 + 800b24a: d007 beq.n 800b25c + 800b24c: f7f5 fcee bl 8000c2c + 800b250: 4b1c ldr r3, [pc, #112] @ (800b2c4 ) + 800b252: 691b ldr r3, [r3, #16] + 800b254: 4a1b ldr r2, [pc, #108] @ (800b2c4 ) + 800b256: f023 0306 bic.w r3, r3, #6 + 800b25a: 6113 str r3, [r2, #16] + 800b25c: 687b ldr r3, [r7, #4] + 800b25e: 681b ldr r3, [r3, #0] + 800b260: f503 6360 add.w r3, r3, #3584 @ 0xe00 + 800b264: 681b ldr r3, [r3, #0] + 800b266: 687a ldr r2, [r7, #4] + 800b268: 6812 ldr r2, [r2, #0] + 800b26a: f502 6260 add.w r2, r2, #3584 @ 0xe00 + 800b26e: f023 0301 bic.w r3, r3, #1 + 800b272: 6013 str r3, [r2, #0] + 800b274: 687b ldr r3, [r7, #4] + 800b276: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 + 800b27a: 4618 mov r0, r3 + 800b27c: f7fe fb90 bl 80099a0 + 800b280: e01c b.n 800b2bc + 800b282: 687b ldr r3, [r7, #4] + 800b284: 681b ldr r3, [r3, #0] + 800b286: f503 6360 add.w r3, r3, #3584 @ 0xe00 + 800b28a: 681b ldr r3, [r3, #0] + 800b28c: 687a ldr r2, [r7, #4] + 800b28e: 6812 ldr r2, [r2, #0] + 800b290: f502 6260 add.w r2, r2, #3584 @ 0xe00 + 800b294: f043 0301 orr.w r3, r3, #1 + 800b298: 6013 str r3, [r2, #0] + 800b29a: 687b ldr r3, [r7, #4] + 800b29c: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 + 800b2a0: 4618 mov r0, r3 + 800b2a2: f7fe fb61 bl 8009968 + 800b2a6: 687b ldr r3, [r7, #4] + 800b2a8: 7adb ldrb r3, [r3, #11] + 800b2aa: 2b00 cmp r3, #0 + 800b2ac: d005 beq.n 800b2ba + 800b2ae: 4b05 ldr r3, [pc, #20] @ (800b2c4 ) + 800b2b0: 691b ldr r3, [r3, #16] + 800b2b2: 4a04 ldr r2, [pc, #16] @ (800b2c4 ) + 800b2b4: f043 0306 orr.w r3, r3, #6 + 800b2b8: 6113 str r3, [r2, #16] + 800b2ba: bf00 nop + 800b2bc: bf00 nop + 800b2be: 3708 adds r7, #8 + 800b2c0: 46bd mov sp, r7 + 800b2c2: bd80 pop {r7, pc} + 800b2c4: e000ed00 .word 0xe000ed00 + +0800b2c8 : + 800b2c8: b480 push {r7} + 800b2ca: b083 sub sp, #12 + 800b2cc: af00 add r7, sp, #0 + 800b2ce: 6078 str r0, [r7, #4] + 800b2d0: 4b03 ldr r3, [pc, #12] @ (800b2e0 ) + 800b2d2: 4618 mov r0, r3 + 800b2d4: 370c adds r7, #12 + 800b2d6: 46bd mov sp, r7 + 800b2d8: f85d 7b04 ldr.w r7, [sp], #4 + 800b2dc: 4770 bx lr + 800b2de: bf00 nop + 800b2e0: 20001748 .word 0x20001748 + +0800b2e4 : + 800b2e4: b480 push {r7} + 800b2e6: b083 sub sp, #12 + 800b2e8: af00 add r7, sp, #0 + 800b2ea: 6078 str r0, [r7, #4] + 800b2ec: bf00 nop + 800b2ee: 370c adds r7, #12 + 800b2f0: 46bd mov sp, r7 + 800b2f2: f85d 7b04 ldr.w r7, [sp], #4 + 800b2f6: 4770 bx lr + +0800b2f8 : + 800b2f8: b480 push {r7} + 800b2fa: b085 sub sp, #20 + 800b2fc: af00 add r7, sp, #0 + 800b2fe: 4603 mov r3, r0 + 800b300: 71fb strb r3, [r7, #7] + 800b302: 2300 movs r3, #0 + 800b304: 73fb strb r3, [r7, #15] + 800b306: 79fb ldrb r3, [r7, #7] + 800b308: 2b03 cmp r3, #3 + 800b30a: d817 bhi.n 800b33c + 800b30c: a201 add r2, pc, #4 @ (adr r2, 800b314 ) + 800b30e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800b312: bf00 nop + 800b314: 0800b325 .word 0x0800b325 + 800b318: 0800b32b .word 0x0800b32b + 800b31c: 0800b331 .word 0x0800b331 + 800b320: 0800b337 .word 0x0800b337 + 800b324: 2300 movs r3, #0 + 800b326: 73fb strb r3, [r7, #15] + 800b328: e00b b.n 800b342 + 800b32a: 2303 movs r3, #3 + 800b32c: 73fb strb r3, [r7, #15] + 800b32e: e008 b.n 800b342 + 800b330: 2301 movs r3, #1 + 800b332: 73fb strb r3, [r7, #15] + 800b334: e005 b.n 800b342 + 800b336: 2303 movs r3, #3 + 800b338: 73fb strb r3, [r7, #15] + 800b33a: e002 b.n 800b342 + 800b33c: 2303 movs r3, #3 + 800b33e: 73fb strb r3, [r7, #15] + 800b340: bf00 nop + 800b342: 7bfb ldrb r3, [r7, #15] + 800b344: 4618 mov r0, r3 + 800b346: 3714 adds r7, #20 + 800b348: 46bd mov sp, r7 + 800b34a: f85d 7b04 ldr.w r7, [sp], #4 + 800b34e: 4770 bx lr + +0800b350 : + 800b350: 4402 add r2, r0 + 800b352: 4603 mov r3, r0 + 800b354: 4293 cmp r3, r2 + 800b356: d100 bne.n 800b35a + 800b358: 4770 bx lr + 800b35a: f803 1b01 strb.w r1, [r3], #1 + 800b35e: e7f9 b.n 800b354 + +0800b360 <__libc_init_array>: + 800b360: b570 push {r4, r5, r6, lr} + 800b362: 4d0d ldr r5, [pc, #52] @ (800b398 <__libc_init_array+0x38>) + 800b364: 4c0d ldr r4, [pc, #52] @ (800b39c <__libc_init_array+0x3c>) + 800b366: 1b64 subs r4, r4, r5 + 800b368: 10a4 asrs r4, r4, #2 + 800b36a: 2600 movs r6, #0 + 800b36c: 42a6 cmp r6, r4 + 800b36e: d109 bne.n 800b384 <__libc_init_array+0x24> + 800b370: 4d0b ldr r5, [pc, #44] @ (800b3a0 <__libc_init_array+0x40>) + 800b372: 4c0c ldr r4, [pc, #48] @ (800b3a4 <__libc_init_array+0x44>) + 800b374: f000 f826 bl 800b3c4 <_init> + 800b378: 1b64 subs r4, r4, r5 + 800b37a: 10a4 asrs r4, r4, #2 + 800b37c: 2600 movs r6, #0 + 800b37e: 42a6 cmp r6, r4 + 800b380: d105 bne.n 800b38e <__libc_init_array+0x2e> + 800b382: bd70 pop {r4, r5, r6, pc} + 800b384: f855 3b04 ldr.w r3, [r5], #4 + 800b388: 4798 blx r3 + 800b38a: 3601 adds r6, #1 + 800b38c: e7ee b.n 800b36c <__libc_init_array+0xc> + 800b38e: f855 3b04 ldr.w r3, [r5], #4 + 800b392: 4798 blx r3 + 800b394: 3601 adds r6, #1 + 800b396: e7f2 b.n 800b37e <__libc_init_array+0x1e> + 800b398: 0800b440 .word 0x0800b440 + 800b39c: 0800b440 .word 0x0800b440 + 800b3a0: 0800b440 .word 0x0800b440 + 800b3a4: 0800b444 .word 0x0800b444 + +0800b3a8 : + 800b3a8: 440a add r2, r1 + 800b3aa: 4291 cmp r1, r2 + 800b3ac: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff + 800b3b0: d100 bne.n 800b3b4 + 800b3b2: 4770 bx lr + 800b3b4: b510 push {r4, lr} + 800b3b6: f811 4b01 ldrb.w r4, [r1], #1 + 800b3ba: f803 4f01 strb.w r4, [r3, #1]! + 800b3be: 4291 cmp r1, r2 + 800b3c0: d1f9 bne.n 800b3b6 + 800b3c2: bd10 pop {r4, pc} + +0800b3c4 <_init>: + 800b3c4: b5f8 push {r3, r4, r5, r6, r7, lr} + 800b3c6: bf00 nop + 800b3c8: bcf8 pop {r3, r4, r5, r6, r7} + 800b3ca: bc08 pop {r3} + 800b3cc: 469e mov lr, r3 + 800b3ce: 4770 bx lr + +0800b3d0 <_fini>: + 800b3d0: b5f8 push {r3, r4, r5, r6, r7, lr} + 800b3d2: bf00 nop + 800b3d4: bcf8 pop {r3, r4, r5, r6, r7} + 800b3d6: bc08 pop {r3} + 800b3d8: 469e mov lr, r3 + 800b3da: 4770 bx lr diff --git a/firmware/67percent/Debug/modularkbd.map b/firmware/67percent/Debug/modularkbd.map new file mode 100644 index 00000000..289ae007 --- /dev/null +++ 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./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x11f ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x1675e ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x6d ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x3693 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0xca5 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x9e9 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x115 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x1a0 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0xa5 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x16d ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x287 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x5f ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x236 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x132 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x29c ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x2e ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x1b5 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x22 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0xd6 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x127 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0xe8 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x89 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x8ed ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x53 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x2aa ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x293 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0xba ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x126 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x304 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x6b ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x20f ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00000000 0x5f ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text 0x00000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .data 0x00000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .bss 0x00000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_DeInit + 0x00000000 0x60 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .text.USBD_Stop + 0x00000000 0x36 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0xad8 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x22 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x5b ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x2a ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x94 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x43 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x57 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x9e ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x370 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x112 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x10 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x4a ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x10 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x58 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x8e ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x1c ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x185 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x146 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x3c ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x29 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x20 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x2a7 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x2e ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x28 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x103 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x6a ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x1df ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x1c ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x22 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0xfb ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x1011 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x11f ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x1675e ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x6d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x3693 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x56 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0xca5 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x9e9 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x115 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x1a0 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0xa5 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x16d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x287 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x5f ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x236 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x132 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x29c ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x2e ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00000000 0x1b5 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./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .group 0x00000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .text 0x00000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .data 0x00000000 0x0 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/home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-sbrkr.o) + .debug_frame 0x00000000 0x2c /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-sbrkr.o) + .ARM.attributes + 0x00000000 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-sbrkr.o) + .data 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) + .bss 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) + .data 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + .bss 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + .ARM.extab 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + .data 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o) + .bss 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o) + .text 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .data 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .bss 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .rodata 0x00000000 0x24 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .eh_frame 0x00000000 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .ARM.attributes + 0x00000000 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .text 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + .data 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + .bss 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x20000000 0x00020000 xrw +FLASH 0x08000000 0x00080000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crti.o +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +LOAD ./Core/Src/dma.o +LOAD ./Core/Src/gpio.o +LOAD ./Core/Src/hid_queue.o +LOAD ./Core/Src/i2c.o +LOAD ./Core/Src/main.o +LOAD ./Core/Src/pwm.o +LOAD ./Core/Src/stm32f4xx_hal_msp.o +LOAD ./Core/Src/stm32f4xx_it.o +LOAD ./Core/Src/syscalls.o +LOAD ./Core/Src/sysmem.o +LOAD ./Core/Src/system_stm32f4xx.o +LOAD ./Core/Src/tim.o +LOAD ./Core/Src/usart.o +LOAD ./Core/Startup/startup_stm32f446retx.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o +LOAD ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o +LOAD ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o +LOAD ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o +LOAD ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o +LOAD ./USB_DEVICE/App/usb_device.o +LOAD ./USB_DEVICE/App/usbd_desc.o +LOAD ./USB_DEVICE/Target/usbd_conf.o +START GROUP +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a +END GROUP +START GROUP +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +END GROUP +START GROUP +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a +END GROUP +START GROUP +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a +END GROUP +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + 0x20020000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x08000000 0x1c4 + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0x1c4 ./Core/Startup/startup_stm32f446retx.o + 0x08000000 g_pfnVectors + 0x080001c4 . = ALIGN (0x4) + +.text 0x080001c4 0xb218 + 0x080001c4 . = ALIGN (0x4) + *(.text) + .text 0x080001c4 0x40 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .text 0x08000204 0x30 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) + 0x08000204 __aeabi_uldivmod + .text 0x08000234 0x2f8 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + 0x08000234 __udivmoddi4 + .text 0x0800052c 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o) + 0x0800052c __aeabi_ldiv0 + 0x0800052c __aeabi_idiv0 + *(.text*) + .text.MX_DMA_Init + 0x08000530 0xcc ./Core/Src/dma.o + 0x08000530 MX_DMA_Init + .text.MX_GPIO_Init + 0x080005fc 0x140 ./Core/Src/gpio.o + 0x080005fc MX_GPIO_Init + .text.MX_I2C1_Init + 0x0800073c 0x5c ./Core/Src/i2c.o + 0x0800073c MX_I2C1_Init + .text.HAL_I2C_MspInit + 0x08000798 0x90 ./Core/Src/i2c.o + 0x08000798 HAL_I2C_MspInit + .text.pq_init 0x08000828 0x2c ./Core/Src/main.o + 0x08000828 pq_init + .text.pq_push 0x08000854 0x68 ./Core/Src/main.o + 0x08000854 pq_push + .text.pq_pop 0x080008bc 0x6c ./Core/Src/main.o + 0x080008bc pq_pop + .text.main 0x08000928 0x1fc ./Core/Src/main.o + 0x08000928 main + .text.mergeChild + 0x08000b24 0x108 ./Core/Src/main.o + 0x08000b24 mergeChild + .text.SystemClock_Config + 0x08000c2c 0xd8 ./Core/Src/main.o + 0x08000c2c SystemClock_Config + .text.HAL_UART_RxCpltCallback + 0x08000d04 0xb8 ./Core/Src/main.o + 0x08000d04 HAL_UART_RxCpltCallback + .text.HAL_UART_ErrorCallback + 0x08000dbc 0x98 ./Core/Src/main.o + 0x08000dbc HAL_UART_ErrorCallback + .text.findBestParent + 0x08000e54 0x84 ./Core/Src/main.o + 0x08000e54 findBestParent + .text.handleUARTMessages + 0x08000ed8 0x144 ./Core/Src/main.o + 0x08000ed8 handleUARTMessages + .text.addUSBReport + 0x0800101c 0x68 ./Core/Src/main.o + 0x0800101c addUSBReport + .text.matrixScan + 0x08001084 0xf0 ./Core/Src/main.o + 0x08001084 matrixScan + .text.encoderProcess + 0x08001174 0xbc ./Core/Src/main.o + 0x08001174 encoderProcess + .text.resetReport + 0x08001230 0x18 ./Core/Src/main.o + 0x08001230 resetReport + .text.Error_Handler + 0x08001248 0xc ./Core/Src/main.o + 0x08001248 Error_Handler + .text.MX_PWM_Init + 0x08001254 0x5c ./Core/Src/pwm.o + 0x08001254 MX_PWM_Init + .text.PWM_Start + 0x080012b0 0x14 ./Core/Src/pwm.o + 0x080012b0 PWM_Start + .text.HAL_MspInit + 0x080012c4 0x50 ./Core/Src/stm32f4xx_hal_msp.o + 0x080012c4 HAL_MspInit + .text.NMI_Handler + 0x08001314 0x8 ./Core/Src/stm32f4xx_it.o + 0x08001314 NMI_Handler + .text.HardFault_Handler + 0x0800131c 0x8 ./Core/Src/stm32f4xx_it.o + 0x0800131c HardFault_Handler + .text.MemManage_Handler + 0x08001324 0x8 ./Core/Src/stm32f4xx_it.o + 0x08001324 MemManage_Handler + .text.BusFault_Handler + 0x0800132c 0x8 ./Core/Src/stm32f4xx_it.o + 0x0800132c BusFault_Handler + .text.UsageFault_Handler + 0x08001334 0x8 ./Core/Src/stm32f4xx_it.o + 0x08001334 UsageFault_Handler + .text.SVC_Handler + 0x0800133c 0xe ./Core/Src/stm32f4xx_it.o + 0x0800133c SVC_Handler + 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.text.HAL_TIM_OC_MspInit + 0x080015f4 0x40 ./Core/Src/tim.o + 0x080015f4 HAL_TIM_OC_MspInit + .text.HAL_TIM_Encoder_MspInit + 0x08001634 0x90 ./Core/Src/tim.o + 0x08001634 HAL_TIM_Encoder_MspInit + .text.HAL_TIM_MspPostInit + 0x080016c4 0x70 ./Core/Src/tim.o + 0x080016c4 HAL_TIM_MspPostInit + .text.MX_UART4_Init + 0x08001734 0x54 ./Core/Src/usart.o + 0x08001734 MX_UART4_Init + .text.MX_UART5_Init + 0x08001788 0x54 ./Core/Src/usart.o + 0x08001788 MX_UART5_Init + .text.MX_USART1_UART_Init + 0x080017dc 0x54 ./Core/Src/usart.o + 0x080017dc MX_USART1_UART_Init + .text.MX_USART2_UART_Init + 0x08001830 0x54 ./Core/Src/usart.o + 0x08001830 MX_USART2_UART_Init + .text.HAL_UART_MspInit + 0x08001884 0x584 ./Core/Src/usart.o + 0x08001884 HAL_UART_MspInit + .text.Reset_Handler + 0x08001e08 0x50 ./Core/Startup/startup_stm32f446retx.o + 0x08001e08 Reset_Handler + .text.Default_Handler + 0x08001e58 0x2 ./Core/Startup/startup_stm32f446retx.o + 0x08001e58 RTC_Alarm_IRQHandler + 0x08001e58 EXTI2_IRQHandler + 0x08001e58 TIM8_CC_IRQHandler + 0x08001e58 FMPI2C1_EV_IRQHandler + 0x08001e58 SPI4_IRQHandler + 0x08001e58 TIM1_CC_IRQHandler + 0x08001e58 DMA2_Stream5_IRQHandler + 0x08001e58 PVD_IRQHandler + 0x08001e58 SDIO_IRQHandler + 0x08001e58 TAMP_STAMP_IRQHandler + 0x08001e58 CAN2_RX1_IRQHandler + 0x08001e58 EXTI3_IRQHandler + 0x08001e58 TIM8_TRG_COM_TIM14_IRQHandler + 0x08001e58 TIM1_UP_TIM10_IRQHandler + 0x08001e58 TIM8_UP_TIM13_IRQHandler + 0x08001e58 I2C3_ER_IRQHandler + 0x08001e58 EXTI0_IRQHandler + 0x08001e58 I2C2_EV_IRQHandler + 0x08001e58 CAN1_RX0_IRQHandler + 0x08001e58 FPU_IRQHandler + 0x08001e58 OTG_HS_WKUP_IRQHandler + 0x08001e58 CAN2_SCE_IRQHandler + 0x08001e58 SPI1_IRQHandler + 0x08001e58 TIM6_DAC_IRQHandler + 0x08001e58 TIM1_BRK_TIM9_IRQHandler + 0x08001e58 DCMI_IRQHandler + 0x08001e58 CAN2_RX0_IRQHandler + 0x08001e58 DMA2_Stream3_IRQHandler + 0x08001e58 SAI2_IRQHandler + 0x08001e58 USART6_IRQHandler + 0x08001e58 USART3_IRQHandler + 0x08001e58 CAN1_RX1_IRQHandler + 0x08001e58 DMA2_Stream0_IRQHandler + 0x08001e58 TIM4_IRQHandler + 0x08001e58 QUADSPI_IRQHandler + 0x08001e58 I2C1_EV_IRQHandler + 0x08001e58 DMA1_Stream1_IRQHandler + 0x08001e58 TIM3_IRQHandler + 0x08001e58 RCC_IRQHandler + 0x08001e58 TIM8_BRK_TIM12_IRQHandler + 0x08001e58 Default_Handler + 0x08001e58 CEC_IRQHandler + 0x08001e58 EXTI15_10_IRQHandler + 0x08001e58 ADC_IRQHandler + 0x08001e58 TIM7_IRQHandler + 0x08001e58 CAN2_TX_IRQHandler + 0x08001e58 TIM5_IRQHandler + 0x08001e58 I2C3_EV_IRQHandler + 0x08001e58 EXTI9_5_IRQHandler + 0x08001e58 RTC_WKUP_IRQHandler + 0x08001e58 SPDIF_RX_IRQHandler + 0x08001e58 SPI2_IRQHandler + 0x08001e58 OTG_HS_EP1_IN_IRQHandler + 0x08001e58 CAN1_TX_IRQHandler + 0x08001e58 FMPI2C1_ER_IRQHandler + 0x08001e58 EXTI4_IRQHandler + 0x08001e58 OTG_HS_EP1_OUT_IRQHandler + 0x08001e58 WWDG_IRQHandler + 0x08001e58 TIM2_IRQHandler + 0x08001e58 OTG_FS_WKUP_IRQHandler + 0x08001e58 TIM1_TRG_COM_TIM11_IRQHandler + 0x08001e58 OTG_HS_IRQHandler + 0x08001e58 EXTI1_IRQHandler + 0x08001e58 I2C2_ER_IRQHandler + 0x08001e58 DMA2_Stream1_IRQHandler + 0x08001e58 CAN1_SCE_IRQHandler + 0x08001e58 FLASH_IRQHandler + 0x08001e58 DMA2_Stream4_IRQHandler + 0x08001e58 SPI3_IRQHandler + 0x08001e58 I2C1_ER_IRQHandler + 0x08001e58 FMC_IRQHandler + 0x08001e58 DMA2_Stream6_IRQHandler + 0x08001e58 SAI1_IRQHandler + 0x08001e58 DMA1_Stream3_IRQHandler + *fill* 0x08001e5a 0x2 + .text.HAL_Init + 0x08001e5c 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x08001e5c HAL_Init + .text.HAL_InitTick + 0x08001ea0 0x60 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x08001ea0 HAL_InitTick + .text.HAL_IncTick + 0x08001f00 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x08001f00 HAL_IncTick + .text.HAL_GetTick + 0x08001f28 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x08001f28 HAL_GetTick + .text.HAL_Delay + 0x08001f40 0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x08001f40 HAL_Delay + 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HAL_UART_RxHalfCpltCallback + .text.HAL_UARTEx_RxEventCallback + 0x08006bdc 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + 0x08006bdc HAL_UARTEx_RxEventCallback + .text.UART_DMATransmitCplt + 0x08006bf4 0x9a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .text.UART_DMATxHalfCplt + 0x08006c8e 0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .text.UART_DMAReceiveCplt + 0x08006caa 0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .text.UART_DMARxHalfCplt + 0x08006dd6 0x3c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .text.UART_DMAError + 0x08006e12 0x94 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + *fill* 0x08006ea6 0x2 + .text.UART_Start_Receive_DMA + 0x08006ea8 0x14c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + 0x08006ea8 UART_Start_Receive_DMA + .text.UART_EndTxTransfer + 0x08006ff4 0x50 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .text.UART_EndRxTransfer + 0x08007044 0xc6 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./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0800a9a8 USBD_CtlSendStatus + .text.USBD_CtlReceiveStatus + 0x0800a9ce 0x26 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0800a9ce USBD_CtlReceiveStatus + .text.MX_USB_DEVICE_Init + 0x0800a9f4 0x4c ./USB_DEVICE/App/usb_device.o + 0x0800a9f4 MX_USB_DEVICE_Init + .text.USBD_FS_DeviceDescriptor + 0x0800aa40 0x24 ./USB_DEVICE/App/usbd_desc.o + 0x0800aa40 USBD_FS_DeviceDescriptor + .text.USBD_FS_LangIDStrDescriptor + 0x0800aa64 0x24 ./USB_DEVICE/App/usbd_desc.o + 0x0800aa64 USBD_FS_LangIDStrDescriptor + .text.USBD_FS_ProductStrDescriptor + 0x0800aa88 0x3c ./USB_DEVICE/App/usbd_desc.o + 0x0800aa88 USBD_FS_ProductStrDescriptor + .text.USBD_FS_ManufacturerStrDescriptor + 0x0800aac4 0x28 ./USB_DEVICE/App/usbd_desc.o + 0x0800aac4 USBD_FS_ManufacturerStrDescriptor + .text.USBD_FS_SerialStrDescriptor + 0x0800aaec 0x24 ./USB_DEVICE/App/usbd_desc.o + 0x0800aaec USBD_FS_SerialStrDescriptor + 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HAL_PCD_DataInStageCallback + .text.HAL_PCD_SOFCallback + 0x0800ade6 0x1c ./USB_DEVICE/Target/usbd_conf.o + 0x0800ade6 HAL_PCD_SOFCallback + .text.HAL_PCD_ResetCallback + 0x0800ae02 0x50 ./USB_DEVICE/Target/usbd_conf.o + 0x0800ae02 HAL_PCD_ResetCallback + *fill* 0x0800ae52 0x2 + .text.HAL_PCD_SuspendCallback + 0x0800ae54 0x4c ./USB_DEVICE/Target/usbd_conf.o + 0x0800ae54 HAL_PCD_SuspendCallback + .text.HAL_PCD_ResumeCallback + 0x0800aea0 0x1c ./USB_DEVICE/Target/usbd_conf.o + 0x0800aea0 HAL_PCD_ResumeCallback + .text.HAL_PCD_ISOOUTIncompleteCallback + 0x0800aebc 0x24 ./USB_DEVICE/Target/usbd_conf.o + 0x0800aebc HAL_PCD_ISOOUTIncompleteCallback + .text.HAL_PCD_ISOINIncompleteCallback + 0x0800aee0 0x24 ./USB_DEVICE/Target/usbd_conf.o + 0x0800aee0 HAL_PCD_ISOINIncompleteCallback + .text.HAL_PCD_ConnectCallback + 0x0800af04 0x1c ./USB_DEVICE/Target/usbd_conf.o + 0x0800af04 HAL_PCD_ConnectCallback + .text.HAL_PCD_DisconnectCallback + 0x0800af20 0x1c ./USB_DEVICE/Target/usbd_conf.o + 0x0800af20 HAL_PCD_DisconnectCallback + .text.USBD_LL_Init + 0x0800af3c 0x98 ./USB_DEVICE/Target/usbd_conf.o + 0x0800af3c USBD_LL_Init + .text.USBD_LL_Start + 0x0800afd4 0x36 ./USB_DEVICE/Target/usbd_conf.o + 0x0800afd4 USBD_LL_Start + .text.USBD_LL_OpenEP + 0x0800b00a 0x4c ./USB_DEVICE/Target/usbd_conf.o + 0x0800b00a USBD_LL_OpenEP + .text.USBD_LL_CloseEP + 0x0800b056 0x3e ./USB_DEVICE/Target/usbd_conf.o + 0x0800b056 USBD_LL_CloseEP + .text.USBD_LL_StallEP + 0x0800b094 0x3e ./USB_DEVICE/Target/usbd_conf.o + 0x0800b094 USBD_LL_StallEP + .text.USBD_LL_ClearStallEP + 0x0800b0d2 0x3e ./USB_DEVICE/Target/usbd_conf.o + 0x0800b0d2 USBD_LL_ClearStallEP + .text.USBD_LL_IsStallEP + 0x0800b110 0x58 ./USB_DEVICE/Target/usbd_conf.o + 0x0800b110 USBD_LL_IsStallEP + .text.USBD_LL_SetUSBAddress + 0x0800b168 0x3e ./USB_DEVICE/Target/usbd_conf.o + 0x0800b168 USBD_LL_SetUSBAddress + .text.USBD_LL_Transmit + 0x0800b1a6 0x42 ./USB_DEVICE/Target/usbd_conf.o + 0x0800b1a6 USBD_LL_Transmit + .text.USBD_LL_PrepareReceive + 0x0800b1e8 0x42 ./USB_DEVICE/Target/usbd_conf.o + 0x0800b1e8 USBD_LL_PrepareReceive + *fill* 0x0800b22a 0x2 + .text.HAL_PCDEx_LPM_Callback + 0x0800b22c 0x9c ./USB_DEVICE/Target/usbd_conf.o + 0x0800b22c HAL_PCDEx_LPM_Callback + .text.USBD_static_malloc + 0x0800b2c8 0x1c ./USB_DEVICE/Target/usbd_conf.o + 0x0800b2c8 USBD_static_malloc + .text.USBD_static_free + 0x0800b2e4 0x14 ./USB_DEVICE/Target/usbd_conf.o + 0x0800b2e4 USBD_static_free + .text.USBD_Get_USB_Status + 0x0800b2f8 0x58 ./USB_DEVICE/Target/usbd_conf.o + 0x0800b2f8 USBD_Get_USB_Status + .text.memset 0x0800b350 0x10 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memset.o) + 0x0800b350 memset + .text.__libc_init_array + 0x0800b360 0x48 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-init.o) + 0x0800b360 __libc_init_array + .text.memcpy 0x0800b3a8 0x1c /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memcpy-stub.o) + 0x0800b3a8 memcpy + *(.glue_7) + .glue_7 0x0800b3c4 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x0800b3c4 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x0800b3c4 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + *(.init) + .init 0x0800b3c4 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crti.o + 0x0800b3c4 _init + .init 0x0800b3c8 0x8 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + *(.fini) + .fini 0x0800b3d0 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crti.o + 0x0800b3d0 _fini + .fini 0x0800b3d4 0x8 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + 0x0800b3dc . = ALIGN (0x4) + 0x0800b3dc _etext = . + +.vfp11_veneer 0x0800b3dc 0x0 + .vfp11_veneer 0x0800b3dc 0x0 linker stubs + +.v4_bx 0x0800b3dc 0x0 + .v4_bx 0x0800b3dc 0x0 linker stubs + +.iplt 0x0800b3dc 0x0 + .iplt 0x0800b3dc 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + +.rodata 0x0800b3dc 0x5c + 0x0800b3dc . = ALIGN (0x4) + *(.rodata) + .rodata 0x0800b3dc 0x3a ./USB_DEVICE/App/usbd_desc.o + *(.rodata*) + *fill* 0x0800b416 0x2 + .rodata.AHBPrescTable + 0x0800b418 0x10 ./Core/Src/system_stm32f4xx.o + 0x0800b418 AHBPrescTable + .rodata.APBPrescTable + 0x0800b428 0x8 ./Core/Src/system_stm32f4xx.o + 0x0800b428 APBPrescTable + .rodata.flagBitshiftOffset.0 + 0x0800b430 0x8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + 0x0800b438 . = ALIGN (0x4) + +.ARM.extab 0x0800b438 0x0 + 0x0800b438 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x0800b438 . = ALIGN (0x4) + +.ARM 0x0800b438 0x8 + 0x0800b438 . = ALIGN (0x4) + 0x0800b438 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x0800b438 0x8 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + 0x0800b440 __exidx_end = . + 0x0800b440 . = ALIGN (0x4) + +.preinit_array 0x0800b440 0x0 + 0x0800b440 . = ALIGN (0x4) + 0x0800b440 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x0800b440 PROVIDE (__preinit_array_end = .) + 0x0800b440 . = ALIGN (0x4) + +.init_array 0x0800b440 0x4 + 0x0800b440 . = ALIGN (0x4) + 0x0800b440 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x0800b440 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x0800b444 PROVIDE (__init_array_end = .) + 0x0800b444 . = ALIGN (0x4) + +.fini_array 0x0800b444 0x4 + 0x0800b444 . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x0800b444 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x0800b448 . = ALIGN (0x4) + 0x0800b448 _sidata = LOADADDR (.data) + +.rel.dyn 0x0800b448 0x0 + .rel.iplt 0x0800b448 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + +.data 0x20000000 0x1a0 load address 0x0800b448 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.ROW_PINS + 0x20000000 0x30 ./Core/Src/main.o + 0x20000000 ROW_PINS + .data.COLUMN_PINS + 0x20000030 0x28 ./Core/Src/main.o + 0x20000030 COLUMN_PINS + .data.KEYCODES + 0x20000058 0x1e ./Core/Src/main.o + 0x20000058 KEYCODES + *fill* 0x20000076 0x2 + .data.PORT_DEPTH + 0x20000078 0x8 ./Core/Src/main.o + 0x20000078 PORT_DEPTH + .data.PORTS 0x20000080 0x10 ./Core/Src/main.o + 0x20000080 PORTS + .data.SystemCoreClock + 0x20000090 0x4 ./Core/Src/system_stm32f4xx.o + 0x20000090 SystemCoreClock + .data.uwTickPrio + 0x20000094 0x4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x20000094 uwTickPrio + .data.uwTickFreq + 0x20000098 0x1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x20000098 uwTickFreq + *fill* 0x20000099 0x3 + .data.USBD_HID + 0x2000009c 0x38 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + 0x2000009c USBD_HID + .data.USBD_HID_CfgDesc + 0x200000d4 0x22 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + *fill* 0x200000f6 0x2 + .data.USBD_HID_Desc + 0x200000f8 0x9 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + *fill* 0x20000101 0x3 + .data.USBD_HID_DeviceQualifierDesc + 0x20000104 0xa ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + *fill* 0x2000010e 0x2 + .data.HID_MOUSE_ReportDesc + 0x20000110 0x2d ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .data.HIDInEpAdd + 0x2000013d 0x1 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + *fill* 0x2000013e 0x2 + .data.FS_Desc 0x20000140 0x20 ./USB_DEVICE/App/usbd_desc.o + 0x20000140 FS_Desc + .data.USBD_FS_DeviceDesc + 0x20000160 0x12 ./USB_DEVICE/App/usbd_desc.o + 0x20000160 USBD_FS_DeviceDesc + *fill* 0x20000172 0x2 + .data.USBD_FS_BOSDesc + 0x20000174 0xc ./USB_DEVICE/App/usbd_desc.o + 0x20000174 USBD_FS_BOSDesc + .data.USBD_LangIDDesc + 0x20000180 0x4 ./USB_DEVICE/App/usbd_desc.o + 0x20000180 USBD_LangIDDesc + .data.USBD_StringSerial + 0x20000184 0x1a ./USB_DEVICE/App/usbd_desc.o + 0x20000184 USBD_StringSerial + *(.RamFunc) + *(.RamFunc*) + 0x200001a0 . = ALIGN (0x4) + *fill* 0x2000019e 0x2 + 0x200001a0 _edata = . + +.igot.plt 0x200001a0 0x0 load address 0x0800b5e8 + .igot.plt 0x200001a0 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x200001a0 . = ALIGN (0x4) + +.bss 0x200001a0 0x15bc load address 0x0800b5e8 + 0x200001a0 _sbss = . + 0x200001a0 __bss_start__ = _sbss + *(.bss) + .bss 0x200001a0 0x1c /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + *(.bss*) + .bss.hi2c1 0x200001bc 0x54 ./Core/Src/i2c.o + 0x200001bc hi2c1 + .bss.REPORT 0x20000210 0xe ./Core/Src/main.o + 0x20000210 REPORT + *fill* 0x2000021e 0x2 + .bss.RX5Msg 0x20000220 0x10 ./Core/Src/main.o + 0x20000220 RX5Msg + .bss.RX1Msg 0x20000230 0x10 ./Core/Src/main.o + 0x20000230 RX1Msg + .bss.RX2Msg 0x20000240 0x10 ./Core/Src/main.o + 0x20000240 RX2Msg + .bss.RX4Msg 0x20000250 0x10 ./Core/Src/main.o + 0x20000250 RX4Msg + .bss.DEPTH 0x20000260 0x2 ./Core/Src/main.o + 0x20000260 DEPTH + *fill* 0x20000262 0x2 + .bss.PARENT 0x20000264 0x4 ./Core/Src/main.o + 0x20000264 PARENT + .bss.KEYSTATE_CHANGED_FLAG + 0x20000268 0x1 ./Core/Src/main.o + 0x20000268 KEYSTATE_CHANGED_FLAG + *fill* 0x20000269 0x3 + .bss.KEYSTATE 0x2000026c 0x1e ./Core/Src/main.o + 0x2000026c KEYSTATE + .bss.MODE 0x2000028a 0x1 ./Core/Src/main.o + 0x2000028a MODE + *fill* 0x2000028b 0x1 + .bss.LAST_ENCODER_COUNT + 0x2000028c 0x4 ./Core/Src/main.o + 0x2000028c LAST_ENCODER_COUNT + .bss.UART_KEYSTATE + 0x20000290 0x30 ./Core/Src/main.o + 0x20000290 UART_KEYSTATE + .bss.huart1q 0x200002c0 0x183 ./Core/Src/main.o + 0x200002c0 huart1q + *fill* 0x20000443 0x1 + .bss.huart2q 0x20000444 0x183 ./Core/Src/main.o + 0x20000444 huart2q + *fill* 0x200005c7 0x1 + .bss.huart4q 0x200005c8 0x183 ./Core/Src/main.o + 0x200005c8 huart4q + *fill* 0x2000074b 0x1 + .bss.huart5q 0x2000074c 0x183 ./Core/Src/main.o + 0x2000074c huart5q + *fill* 0x200008cf 0x1 + .bss.htim2 0x200008d0 0x48 ./Core/Src/tim.o + 0x200008d0 htim2 + .bss.htim3 0x20000918 0x48 ./Core/Src/tim.o + 0x20000918 htim3 + .bss.huart4 0x20000960 0x48 ./Core/Src/usart.o + 0x20000960 huart4 + .bss.huart5 0x200009a8 0x48 ./Core/Src/usart.o + 0x200009a8 huart5 + .bss.huart1 0x200009f0 0x48 ./Core/Src/usart.o + 0x200009f0 huart1 + .bss.huart2 0x20000a38 0x48 ./Core/Src/usart.o + 0x20000a38 huart2 + .bss.hdma_uart4_rx + 0x20000a80 0x60 ./Core/Src/usart.o + 0x20000a80 hdma_uart4_rx + .bss.hdma_uart4_tx + 0x20000ae0 0x60 ./Core/Src/usart.o + 0x20000ae0 hdma_uart4_tx + .bss.hdma_uart5_rx + 0x20000b40 0x60 ./Core/Src/usart.o + 0x20000b40 hdma_uart5_rx + .bss.hdma_uart5_tx + 0x20000ba0 0x60 ./Core/Src/usart.o + 0x20000ba0 hdma_uart5_tx + .bss.hdma_usart1_rx + 0x20000c00 0x60 ./Core/Src/usart.o + 0x20000c00 hdma_usart1_rx + .bss.hdma_usart1_tx + 0x20000c60 0x60 ./Core/Src/usart.o + 0x20000c60 hdma_usart1_tx + .bss.hdma_usart2_rx + 0x20000cc0 0x60 ./Core/Src/usart.o + 0x20000cc0 hdma_usart2_rx + .bss.hdma_usart2_tx + 0x20000d20 0x60 ./Core/Src/usart.o + 0x20000d20 hdma_usart2_tx + .bss.uwTick 0x20000d80 0x4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x20000d80 uwTick + .bss.cfgidx.0 0x20000d84 0x1 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + *fill* 0x20000d85 0x3 + .bss.hUsbDeviceFS + 0x20000d88 0x2dc ./USB_DEVICE/App/usb_device.o + 0x20000d88 hUsbDeviceFS + .bss.USBD_StrDesc + 0x20001064 0x200 ./USB_DEVICE/App/usbd_desc.o + 0x20001064 USBD_StrDesc + .bss.hpcd_USB_OTG_FS + 0x20001264 0x4e4 ./USB_DEVICE/Target/usbd_conf.o + 0x20001264 hpcd_USB_OTG_FS + .bss.mem.0 0x20001748 0x14 ./USB_DEVICE/Target/usbd_conf.o + *(COMMON) + 0x2000175c . = ALIGN (0x4) + 0x2000175c _ebss = . + 0x2000175c __bss_end__ = _ebss + +._user_heap_stack + 0x2000175c 0x604 load address 0x0800b5e8 + 0x20001760 . = ALIGN (0x8) + *fill* 0x2000175c 0x4 + [!provide] PROVIDE (end = .) + 0x20001760 PROVIDE (_end = .) + 0x20001960 . = (. + _Min_Heap_Size) + *fill* 0x20001760 0x200 + 0x20001d60 . = (. + _Min_Stack_Size) + *fill* 0x20001960 0x400 + 0x20001d60 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x00000000 0x30 + *(.ARM.attributes) + .ARM.attributes + 0x00000000 0x22 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crti.o + .ARM.attributes + 0x00000022 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .ARM.attributes + 0x00000056 0x34 ./Core/Src/dma.o + .ARM.attributes + 0x0000008a 0x34 ./Core/Src/gpio.o + .ARM.attributes + 0x000000be 0x34 ./Core/Src/i2c.o + .ARM.attributes + 0x000000f2 0x34 ./Core/Src/main.o + .ARM.attributes + 0x00000126 0x34 ./Core/Src/pwm.o + .ARM.attributes + 0x0000015a 0x34 ./Core/Src/stm32f4xx_hal_msp.o + .ARM.attributes + 0x0000018e 0x34 ./Core/Src/stm32f4xx_it.o + .ARM.attributes + 0x000001c2 0x34 ./Core/Src/system_stm32f4xx.o + .ARM.attributes + 0x000001f6 0x34 ./Core/Src/tim.o + .ARM.attributes + 0x0000022a 0x34 ./Core/Src/usart.o + .ARM.attributes + 0x0000025e 0x21 ./Core/Startup/startup_stm32f446retx.o + .ARM.attributes + 0x0000027f 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .ARM.attributes + 0x000002b3 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .ARM.attributes + 0x000002e7 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .ARM.attributes + 0x0000031b 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .ARM.attributes + 0x0000034f 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o + .ARM.attributes + 0x00000383 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o + .ARM.attributes + 0x000003b7 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o + .ARM.attributes + 0x000003eb 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .ARM.attributes + 0x0000041f 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .ARM.attributes + 0x00000453 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .ARM.attributes + 0x00000487 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .ARM.attributes + 0x000004bb 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .ARM.attributes + 0x000004ef 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + .ARM.attributes + 0x00000523 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .ARM.attributes + 0x00000557 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .ARM.attributes + 0x0000058b 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .ARM.attributes + 0x000005bf 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .ARM.attributes + 0x000005f3 0x34 ./USB_DEVICE/App/usb_device.o + .ARM.attributes + 0x00000627 0x34 ./USB_DEVICE/App/usbd_desc.o + .ARM.attributes + 0x0000065b 0x34 ./USB_DEVICE/Target/usbd_conf.o + .ARM.attributes + 0x0000068f 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memset.o) + .ARM.attributes + 0x000006c3 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-init.o) + .ARM.attributes + 0x000006f7 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memcpy-stub.o) + .ARM.attributes + 0x0000072b 0x22 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x0000074d 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x00000781 0x22 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x000007a3 0x22 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o +OUTPUT(modularkbd.elf elf32-littlearm) +LOAD linker stubs +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a + +.debug_info 0x00000000 0x1be15 + .debug_info 0x00000000 0x514 ./Core/Src/dma.o + .debug_info 0x00000514 0x455 ./Core/Src/gpio.o + .debug_info 0x00000969 0x9a4 ./Core/Src/i2c.o + .debug_info 0x0000130d 0x1b60 ./Core/Src/main.o + .debug_info 0x00002e6d 0x80d ./Core/Src/pwm.o + .debug_info 0x0000367a 0x299 ./Core/Src/stm32f4xx_hal_msp.o + .debug_info 0x00003913 0xc7c ./Core/Src/stm32f4xx_it.o + .debug_info 0x0000458f 0x54a ./Core/Src/system_stm32f4xx.o + .debug_info 0x00004ad9 0xd18 ./Core/Src/tim.o + .debug_info 0x000057f1 0xdbf ./Core/Src/usart.o + .debug_info 0x000065b0 0x30 ./Core/Startup/startup_stm32f446retx.o + .debug_info 0x000065e0 0x99a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_info 0x00006f7a 0xdaa ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_info 0x00007d24 0x8e7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_info 0x0000860b 0x70b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_info 0x00008d16 0x2421 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o + .debug_info 0x0000b137 0x15e3 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o + .debug_info 0x0000c71a 0x7b4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o + .debug_info 0x0000cece 0x8ff ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_info 0x0000d7cd 0x960 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_info 0x0000e12d 0x299d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_info 0x00010aca 0x14db ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_info 0x00011fa5 0x2f4f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_info 0x00014ef4 0x19f1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + .debug_info 0x000168e5 0xa9e ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_info 0x00017383 0xe1f ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_info 0x000181a2 0xaf8 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .debug_info 0x00018c9a 0x76f ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .debug_info 0x00019409 0x609 ./USB_DEVICE/App/usb_device.o + .debug_info 0x00019a12 0x4ba ./USB_DEVICE/App/usbd_desc.o + .debug_info 0x00019ecc 0x1f49 ./USB_DEVICE/Target/usbd_conf.o + +.debug_abbrev 0x00000000 0x4285 + .debug_abbrev 0x00000000 0x11b ./Core/Src/dma.o + .debug_abbrev 0x0000011b 0x152 ./Core/Src/gpio.o + .debug_abbrev 0x0000026d 0x1f1 ./Core/Src/i2c.o + .debug_abbrev 0x0000045e 0x368 ./Core/Src/main.o + .debug_abbrev 0x000007c6 0x1f5 ./Core/Src/pwm.o + .debug_abbrev 0x000009bb 0xd8 ./Core/Src/stm32f4xx_hal_msp.o + .debug_abbrev 0x00000a93 0x1f6 ./Core/Src/stm32f4xx_it.o + .debug_abbrev 0x00000c89 0x11a ./Core/Src/system_stm32f4xx.o + .debug_abbrev 0x00000da3 0x22c ./Core/Src/tim.o + .debug_abbrev 0x00000fcf 0x270 ./Core/Src/usart.o + .debug_abbrev 0x0000123f 0x24 ./Core/Startup/startup_stm32f446retx.o + .debug_abbrev 0x00001263 0x214 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_abbrev 0x00001477 0x31d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_abbrev 0x00001794 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_abbrev 0x000019f8 0x1d4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_abbrev 0x00001bcc 0x2ad ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o + .debug_abbrev 0x00001e79 0x2d0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o + .debug_abbrev 0x00002149 0x1dd ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o + .debug_abbrev 0x00002326 0x2b7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_abbrev 0x000025dd 0x211 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_abbrev 0x000027ee 0x278 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_abbrev 0x00002a66 0x283 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_abbrev 0x00002ce9 0x30e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_abbrev 0x00002ff7 0x2b3 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + .debug_abbrev 0x000032aa 0x2a2 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_abbrev 0x0000354c 0x27c ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_abbrev 0x000037c8 0x26f ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .debug_abbrev 0x00003a37 0x19a ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .debug_abbrev 0x00003bd1 0x190 ./USB_DEVICE/App/usb_device.o + .debug_abbrev 0x00003d61 0x1e3 ./USB_DEVICE/App/usbd_desc.o + .debug_abbrev 0x00003f44 0x341 ./USB_DEVICE/Target/usbd_conf.o + +.debug_aranges 0x00000000 0x17f0 + .debug_aranges + 0x00000000 0x20 ./Core/Src/dma.o + .debug_aranges + 0x00000020 0x20 ./Core/Src/gpio.o + .debug_aranges + 0x00000040 0x30 ./Core/Src/i2c.o + .debug_aranges + 0x00000070 0x90 ./Core/Src/main.o + .debug_aranges + 0x00000100 0x40 ./Core/Src/pwm.o + .debug_aranges + 0x00000140 0x20 ./Core/Src/stm32f4xx_hal_msp.o + .debug_aranges + 0x00000160 0xc8 ./Core/Src/stm32f4xx_it.o + .debug_aranges + 0x00000228 0x28 ./Core/Src/system_stm32f4xx.o + .debug_aranges + 0x00000250 0x50 ./Core/Src/tim.o + .debug_aranges + 0x000002a0 0x48 ./Core/Src/usart.o + .debug_aranges + 0x000002e8 0x28 ./Core/Startup/startup_stm32f446retx.o + .debug_aranges + 0x00000310 0xf0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_aranges + 0x00000400 0x130 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_aranges + 0x00000530 0x90 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_aranges + 0x000005c0 0x58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_aranges + 0x00000618 0x2a8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o + .debug_aranges + 0x000008c0 0x148 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o + .debug_aranges + 0x00000a08 0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o + .debug_aranges + 0x00000a50 0x88 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_aranges + 0x00000ad8 0x78 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_aranges + 0x00000b50 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./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_rnglists + 0x000010c0 0x6e ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .debug_rnglists + 0x0000112e 0x37 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .debug_rnglists + 0x00001165 0x13 ./USB_DEVICE/App/usb_device.o + .debug_rnglists + 0x00001178 0x49 ./USB_DEVICE/App/usbd_desc.o + .debug_rnglists + 0x000011c1 0xd0 ./USB_DEVICE/Target/usbd_conf.o + +.debug_macro 0x00000000 0x262b3 + .debug_macro 0x00000000 0x224 ./Core/Src/dma.o + .debug_macro 0x00000224 0xad8 ./Core/Src/dma.o + .debug_macro 0x00000cfc 0x2a7 ./Core/Src/dma.o + .debug_macro 0x00000fa3 0x2e ./Core/Src/dma.o + .debug_macro 0x00000fd1 0x28 ./Core/Src/dma.o + .debug_macro 0x00000ff9 0x22 ./Core/Src/dma.o + .debug_macro 0x0000101b 0x8e ./Core/Src/dma.o + .debug_macro 0x000010a9 0x51 ./Core/Src/dma.o + .debug_macro 0x000010fa 0x103 ./Core/Src/dma.o + .debug_macro 0x000011fd 0x6a ./Core/Src/dma.o + .debug_macro 0x00001267 0x1df ./Core/Src/dma.o + .debug_macro 0x00001446 0x1c ./Core/Src/dma.o + .debug_macro 0x00001462 0x22 ./Core/Src/dma.o + .debug_macro 0x00001484 0xfb ./Core/Src/dma.o + .debug_macro 0x0000157f 0x1011 ./Core/Src/dma.o + .debug_macro 0x00002590 0x11f ./Core/Src/dma.o + .debug_macro 0x000026af 0x1675e ./Core/Src/dma.o + .debug_macro 0x00018e0d 0x6d ./Core/Src/dma.o + .debug_macro 0x00018e7a 0x3693 ./Core/Src/dma.o + .debug_macro 0x0001c50d 0x190 ./Core/Src/dma.o + .debug_macro 0x0001c69d 0x5c ./Core/Src/dma.o + .debug_macro 0x0001c6f9 0xca5 ./Core/Src/dma.o + .debug_macro 0x0001d39e 0x9e9 ./Core/Src/dma.o + .debug_macro 0x0001dd87 0x115 ./Core/Src/dma.o + .debug_macro 0x0001de9c 0x1a0 ./Core/Src/dma.o + .debug_macro 0x0001e03c 0xa5 ./Core/Src/dma.o + .debug_macro 0x0001e0e1 0x16d ./Core/Src/dma.o + .debug_macro 0x0001e24e 0x287 ./Core/Src/dma.o + .debug_macro 0x0001e4d5 0x5f ./Core/Src/dma.o + .debug_macro 0x0001e534 0x236 ./Core/Src/dma.o + .debug_macro 0x0001e76a 0x132 ./Core/Src/dma.o + .debug_macro 0x0001e89c 0x29c ./Core/Src/dma.o + .debug_macro 0x0001eb38 0x2e ./Core/Src/dma.o + .debug_macro 0x0001eb66 0x1b5 ./Core/Src/dma.o + .debug_macro 0x0001ed1b 0x22 ./Core/Src/dma.o + .debug_macro 0x0001ed3d 0xd6 ./Core/Src/dma.o + .debug_macro 0x0001ee13 0x127 ./Core/Src/dma.o + .debug_macro 0x0001ef3a 0xe8 ./Core/Src/dma.o + .debug_macro 0x0001f022 0x89 ./Core/Src/dma.o + .debug_macro 0x0001f0ab 0x8ed ./Core/Src/dma.o + .debug_macro 0x0001f998 0x53 ./Core/Src/dma.o + .debug_macro 0x0001f9eb 0x2aa ./Core/Src/dma.o + .debug_macro 0x0001fc95 0x293 ./Core/Src/dma.o + .debug_macro 0x0001ff28 0xba ./Core/Src/dma.o + .debug_macro 0x0001ffe2 0x126 ./Core/Src/dma.o + .debug_macro 0x00020108 0x304 ./Core/Src/dma.o + .debug_macro 0x0002040c 0x224 ./Core/Src/gpio.o + .debug_macro 0x00020630 0x224 ./Core/Src/i2c.o + .debug_macro 0x00020854 0x444 ./Core/Src/main.o + .debug_macro 0x00020c98 0x61 ./Core/Src/main.o + .debug_macro 0x00020cf9 0x2a ./Core/Src/main.o + .debug_macro 0x00020d23 0x43 ./Core/Src/main.o + .debug_macro 0x00020d66 0x34 ./Core/Src/main.o + .debug_macro 0x00020d9a 0x16 ./Core/Src/main.o + .debug_macro 0x00020db0 0x3c ./Core/Src/main.o + .debug_macro 0x00020dec 0x370 ./Core/Src/main.o + .debug_macro 0x0002115c 0x10 ./Core/Src/main.o + .debug_macro 0x0002116c 0x16 ./Core/Src/main.o + .debug_macro 0x00021182 0x4a ./Core/Src/main.o + .debug_macro 0x000211cc 0x34 ./Core/Src/main.o + .debug_macro 0x00021200 0x10 ./Core/Src/main.o + .debug_macro 0x00021210 0x58 ./Core/Src/main.o + .debug_macro 0x00021268 0x8e ./Core/Src/main.o + .debug_macro 0x000212f6 0x1c ./Core/Src/main.o + .debug_macro 0x00021312 0x185 ./Core/Src/main.o + .debug_macro 0x00021497 0x16 ./Core/Src/main.o + .debug_macro 0x000214ad 0x16 ./Core/Src/main.o + .debug_macro 0x000214c3 0x146 ./Core/Src/main.o + .debug_macro 0x00021609 0x16 ./Core/Src/main.o + .debug_macro 0x0002161f 0x16 ./Core/Src/main.o + .debug_macro 0x00021635 0x29 ./Core/Src/main.o + .debug_macro 0x0002165e 0x16 ./Core/Src/main.o + .debug_macro 0x00021674 0x20 ./Core/Src/main.o + .debug_macro 0x00021694 0x6b ./Core/Src/main.o + .debug_macro 0x000216ff 0x20f ./Core/Src/main.o + .debug_macro 0x0002190e 0x5f ./Core/Src/main.o + .debug_macro 0x0002196d 0x22e ./Core/Src/pwm.o + .debug_macro 0x00021b9b 0x21a ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x00021db5 0x224 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x00021fd9 0x20b ./Core/Src/system_stm32f4xx.o + .debug_macro 0x000221e4 0x224 ./Core/Src/tim.o + .debug_macro 0x00022408 0x224 ./Core/Src/usart.o + .debug_macro 0x0002262c 0x26b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x00022897 0x20b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x00022aa2 0x211 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x00022cb3 0x211 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x00022ec4 0x259 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o + .debug_macro 0x0002311d 0x217 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o + .debug_macro 0x00023334 0x20b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o + .debug_macro 0x0002353f 0x22f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0002376e 0x20b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x00023979 0x20c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x00023b85 0x20b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x00023d90 0x20c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x00023f9c 0x20b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + .debug_macro 0x000241a7 0x3a9 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00024550 0x9e ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x000245ee 0x112 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00024700 0x56 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_macro 0x00024756 0x390 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00024ae6 0x215 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x00024cfb 0x39a ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .debug_macro 0x00025095 0x396 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .debug_macro 0x0002542b 0x3c0 ./USB_DEVICE/App/usb_device.o + .debug_macro 0x000257eb 0x30a ./USB_DEVICE/App/usb_device.o + .debug_macro 0x00025af5 0x22 ./USB_DEVICE/App/usb_device.o + .debug_macro 0x00025b17 0x3d3 ./USB_DEVICE/App/usbd_desc.o + .debug_macro 0x00025eea 0x1c ./USB_DEVICE/App/usbd_desc.o + .debug_macro 0x00025f06 0x3ad ./USB_DEVICE/Target/usbd_conf.o + +.debug_line 0x00000000 0x1f083 + .debug_line 0x00000000 0x726 ./Core/Src/dma.o + .debug_line 0x00000726 0x74e ./Core/Src/gpio.o + .debug_line 0x00000e74 0x789 ./Core/Src/i2c.o + .debug_line 0x000015fd 0xede ./Core/Src/main.o + .debug_line 0x000024db 0x7bc ./Core/Src/pwm.o + .debug_line 0x00002c97 0x71b ./Core/Src/stm32f4xx_hal_msp.o + .debug_line 0x000033b2 0x902 ./Core/Src/stm32f4xx_it.o + .debug_line 0x00003cb4 0x791 ./Core/Src/system_stm32f4xx.o + .debug_line 0x00004445 0x878 ./Core/Src/tim.o + .debug_line 0x00004cbd 0xa52 ./Core/Src/usart.o + .debug_line 0x0000570f 0x7a ./Core/Startup/startup_stm32f446retx.o + .debug_line 0x00005789 0xa0d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_line 0x00006196 0xcdd ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_line 0x00006e73 0xf79 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_line 0x00007dec 0xb51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_line 0x0000893d 0x3aba ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o + .debug_line 0x0000c3f7 0x1488 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o + .debug_line 0x0000d87f 0x82d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o + .debug_line 0x0000e0ac 0xe28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_line 0x0000eed4 0x14d9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_line 0x000103ad 0x3782 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_line 0x00013b2f 0x196d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_line 0x0001549c 0x2555 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_line 0x000179f1 0x1d2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + .debug_line 0x00019720 0xc3e ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_line 0x0001a35e 0xf28 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_line 0x0001b286 0x1107 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .debug_line 0x0001c38d 0xa2f ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .debug_line 0x0001cdbc 0x9d6 ./USB_DEVICE/App/usb_device.o + .debug_line 0x0001d792 0xab9 ./USB_DEVICE/App/usbd_desc.o + .debug_line 0x0001e24b 0xe38 ./USB_DEVICE/Target/usbd_conf.o + +.debug_str 0x00000000 0xd80a4 + .debug_str 0x00000000 0xd80a4 ./Core/Src/dma.o + 0xcd194 (size before relaxing) + .debug_str 0x000d80a4 0xccd01 ./Core/Src/gpio.o + .debug_str 0x000d80a4 0xcd235 ./Core/Src/i2c.o + .debug_str 0x000d80a4 0xd23b5 ./Core/Src/main.o + .debug_str 0x000d80a4 0xcd18a ./Core/Src/pwm.o + .debug_str 0x000d80a4 0xccc36 ./Core/Src/stm32f4xx_hal_msp.o + .debug_str 0x000d80a4 0xcd5bc ./Core/Src/stm32f4xx_it.o + .debug_str 0x000d80a4 0xcc61e ./Core/Src/system_stm32f4xx.o + .debug_str 0x000d80a4 0xcd496 ./Core/Src/tim.o + .debug_str 0x000d80a4 0xcd808 ./Core/Src/usart.o + .debug_str 0x000d80a4 0x7e ./Core/Startup/startup_stm32f446retx.o + .debug_str 0x000d80a4 0xcd1e4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_str 0x000d80a4 0xccf3b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_str 0x000d80a4 0xcca14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_str 0x000d80a4 0xcc79a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_str 0x000d80a4 0xcd61d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o + .debug_str 0x000d80a4 0xcd130 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o + .debug_str 0x000d80a4 0xcca32 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o + .debug_str 0x000d80a4 0xcca58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_str 0x000d80a4 0xcca8b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_str 0x000d80a4 0xcd984 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_str 0x000d80a4 0xcd190 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_str 0x000d80a4 0xcd00f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_str 0x000d80a4 0xccfec ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + .debug_str 0x000d80a4 0xd1755 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_str 0x000d80a4 0xd16be ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_str 0x000d80a4 0xd14e9 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .debug_str 0x000d80a4 0xd13be ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .debug_str 0x000d80a4 0xd1553 ./USB_DEVICE/App/usb_device.o + .debug_str 0x000d80a4 0xd12d2 ./USB_DEVICE/App/usbd_desc.o + .debug_str 0x000d80a4 0xd271f ./USB_DEVICE/Target/usbd_conf.o + +.comment 0x00000000 0x43 + .comment 0x00000000 0x43 ./Core/Src/dma.o + 0x44 (size before relaxing) + .comment 0x00000043 0x44 ./Core/Src/gpio.o + .comment 0x00000043 0x44 ./Core/Src/i2c.o + .comment 0x00000043 0x44 ./Core/Src/main.o + .comment 0x00000043 0x44 ./Core/Src/pwm.o + .comment 0x00000043 0x44 ./Core/Src/stm32f4xx_hal_msp.o + .comment 0x00000043 0x44 ./Core/Src/stm32f4xx_it.o + .comment 0x00000043 0x44 ./Core/Src/system_stm32f4xx.o + .comment 0x00000043 0x44 ./Core/Src/tim.o + .comment 0x00000043 0x44 ./Core/Src/usart.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + .comment 0x00000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .comment 0x00000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .comment 0x00000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .comment 0x00000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .comment 0x00000043 0x44 ./USB_DEVICE/App/usb_device.o + .comment 0x00000043 0x44 ./USB_DEVICE/App/usbd_desc.o + .comment 0x00000043 0x44 ./USB_DEVICE/Target/usbd_conf.o + +.debug_frame 0x00000000 0x645c + .debug_frame 0x00000000 0x34 ./Core/Src/dma.o + .debug_frame 0x00000034 0x34 ./Core/Src/gpio.o + .debug_frame 0x00000068 0x74 ./Core/Src/i2c.o + .debug_frame 0x000000dc 0x224 ./Core/Src/main.o + .debug_frame 0x00000300 0xb8 ./Core/Src/pwm.o + .debug_frame 0x000003b8 0x38 ./Core/Src/stm32f4xx_hal_msp.o + .debug_frame 0x000003f0 0x270 ./Core/Src/stm32f4xx_it.o + .debug_frame 0x00000660 0x58 ./Core/Src/system_stm32f4xx.o + .debug_frame 0x000006b8 0x114 ./Core/Src/tim.o + .debug_frame 0x000007cc 0xcc ./Core/Src/usart.o + .debug_frame 0x00000898 0x374 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_frame 0x00000c0c 0x508 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_frame 0x00001114 0x250 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_frame 0x00001364 0x14c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_frame 0x000014b0 0xc84 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o + .debug_frame 0x00002134 0x5b8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o + .debug_frame 0x000026ec 0x100 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o + .debug_frame 0x000027ec 0x1f4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_frame 0x000029e0 0x1e8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_frame 0x00002bc8 0x11c0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_frame 0x00003d88 0x638 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_frame 0x000043c0 0x954 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_frame 0x00004d14 0x7c0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + .debug_frame 0x000054d4 0x184 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .debug_frame 0x00005658 0x390 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_frame 0x000059e8 0x23c ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .debug_frame 0x00005c24 0x10c ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .debug_frame 0x00005d30 0x2c ./USB_DEVICE/App/usb_device.o + .debug_frame 0x00005d5c 0x188 ./USB_DEVICE/App/usbd_desc.o + .debug_frame 0x00005ee4 0x4a4 ./USB_DEVICE/Target/usbd_conf.o + .debug_frame 0x00006388 0x20 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memset.o) + .debug_frame 0x000063a8 0x2c /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-init.o) + .debug_frame 0x000063d4 0x28 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memcpy-stub.o) + .debug_frame 0x000063fc 0x2c /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00006428 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + +.debug_line_str + 0x00000000 0x62 + .debug_line_str + 0x00000000 0x62 ./Core/Startup/startup_stm32f446retx.o diff --git a/firmware/67percent/Debug/objects.list b/firmware/67percent/Debug/objects.list new file mode 100644 index 00000000..ff97ac42 --- /dev/null +++ b/firmware/67percent/Debug/objects.list @@ -0,0 +1,42 @@ +"./Core/Src/dma.o" +"./Core/Src/gpio.o" +"./Core/Src/hid_queue.o" +"./Core/Src/i2c.o" +"./Core/Src/main.o" +"./Core/Src/pwm.o" +"./Core/Src/stm32f4xx_hal_msp.o" +"./Core/Src/stm32f4xx_it.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32f4xx.o" +"./Core/Src/tim.o" +"./Core/Src/usart.o" +"./Core/Startup/startup_stm32f446retx.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o" +"./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o" +"./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o" +"./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o" +"./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o" +"./USB_DEVICE/App/usb_device.o" +"./USB_DEVICE/App/usbd_desc.o" +"./USB_DEVICE/Target/usbd_conf.o" diff --git a/firmware/modularkbd/Debug/objects.mk b/firmware/67percent/Debug/objects.mk similarity index 100% rename from firmware/modularkbd/Debug/objects.mk rename to firmware/67percent/Debug/objects.mk diff --git a/firmware/modularkbd/Debug/sources.mk b/firmware/67percent/Debug/sources.mk similarity index 100% rename from firmware/modularkbd/Debug/sources.mk rename to firmware/67percent/Debug/sources.mk diff --git a/firmware/modularkbd/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h b/firmware/67percent/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h rename to firmware/67percent/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h b/firmware/67percent/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h rename to firmware/67percent/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h b/firmware/67percent/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h rename to firmware/67percent/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt b/firmware/67percent/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt rename to firmware/67percent/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/cachel1_armv7.h b/firmware/67percent/Drivers/CMSIS/Include/cachel1_armv7.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/cachel1_armv7.h rename to firmware/67percent/Drivers/CMSIS/Include/cachel1_armv7.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/cmsis_armcc.h b/firmware/67percent/Drivers/CMSIS/Include/cmsis_armcc.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/cmsis_armcc.h rename to firmware/67percent/Drivers/CMSIS/Include/cmsis_armcc.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/cmsis_armclang.h b/firmware/67percent/Drivers/CMSIS/Include/cmsis_armclang.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/cmsis_armclang.h rename to firmware/67percent/Drivers/CMSIS/Include/cmsis_armclang.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/firmware/67percent/Drivers/CMSIS/Include/cmsis_armclang_ltm.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/cmsis_armclang_ltm.h rename to firmware/67percent/Drivers/CMSIS/Include/cmsis_armclang_ltm.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/cmsis_compiler.h b/firmware/67percent/Drivers/CMSIS/Include/cmsis_compiler.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/cmsis_compiler.h rename to firmware/67percent/Drivers/CMSIS/Include/cmsis_compiler.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/cmsis_gcc.h b/firmware/67percent/Drivers/CMSIS/Include/cmsis_gcc.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/cmsis_gcc.h rename to firmware/67percent/Drivers/CMSIS/Include/cmsis_gcc.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/cmsis_iccarm.h b/firmware/67percent/Drivers/CMSIS/Include/cmsis_iccarm.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/cmsis_iccarm.h rename to firmware/67percent/Drivers/CMSIS/Include/cmsis_iccarm.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/cmsis_version.h b/firmware/67percent/Drivers/CMSIS/Include/cmsis_version.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/cmsis_version.h rename to firmware/67percent/Drivers/CMSIS/Include/cmsis_version.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_armv81mml.h b/firmware/67percent/Drivers/CMSIS/Include/core_armv81mml.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_armv81mml.h rename to firmware/67percent/Drivers/CMSIS/Include/core_armv81mml.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_armv8mbl.h b/firmware/67percent/Drivers/CMSIS/Include/core_armv8mbl.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_armv8mbl.h rename to firmware/67percent/Drivers/CMSIS/Include/core_armv8mbl.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_armv8mml.h b/firmware/67percent/Drivers/CMSIS/Include/core_armv8mml.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_armv8mml.h rename to firmware/67percent/Drivers/CMSIS/Include/core_armv8mml.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_cm0.h b/firmware/67percent/Drivers/CMSIS/Include/core_cm0.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_cm0.h rename to firmware/67percent/Drivers/CMSIS/Include/core_cm0.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_cm0plus.h b/firmware/67percent/Drivers/CMSIS/Include/core_cm0plus.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_cm0plus.h rename to firmware/67percent/Drivers/CMSIS/Include/core_cm0plus.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_cm1.h b/firmware/67percent/Drivers/CMSIS/Include/core_cm1.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_cm1.h rename to firmware/67percent/Drivers/CMSIS/Include/core_cm1.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_cm23.h b/firmware/67percent/Drivers/CMSIS/Include/core_cm23.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_cm23.h rename to firmware/67percent/Drivers/CMSIS/Include/core_cm23.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_cm3.h b/firmware/67percent/Drivers/CMSIS/Include/core_cm3.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_cm3.h rename to firmware/67percent/Drivers/CMSIS/Include/core_cm3.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_cm33.h b/firmware/67percent/Drivers/CMSIS/Include/core_cm33.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_cm33.h rename to firmware/67percent/Drivers/CMSIS/Include/core_cm33.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_cm35p.h b/firmware/67percent/Drivers/CMSIS/Include/core_cm35p.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_cm35p.h rename to firmware/67percent/Drivers/CMSIS/Include/core_cm35p.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_cm4.h b/firmware/67percent/Drivers/CMSIS/Include/core_cm4.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_cm4.h rename to firmware/67percent/Drivers/CMSIS/Include/core_cm4.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_cm55.h b/firmware/67percent/Drivers/CMSIS/Include/core_cm55.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_cm55.h rename to firmware/67percent/Drivers/CMSIS/Include/core_cm55.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_cm7.h b/firmware/67percent/Drivers/CMSIS/Include/core_cm7.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_cm7.h rename to firmware/67percent/Drivers/CMSIS/Include/core_cm7.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_cm85.h b/firmware/67percent/Drivers/CMSIS/Include/core_cm85.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_cm85.h rename to firmware/67percent/Drivers/CMSIS/Include/core_cm85.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_sc000.h b/firmware/67percent/Drivers/CMSIS/Include/core_sc000.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_sc000.h rename to firmware/67percent/Drivers/CMSIS/Include/core_sc000.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_sc300.h b/firmware/67percent/Drivers/CMSIS/Include/core_sc300.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_sc300.h rename to firmware/67percent/Drivers/CMSIS/Include/core_sc300.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/core_starmc1.h b/firmware/67percent/Drivers/CMSIS/Include/core_starmc1.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/core_starmc1.h rename to firmware/67percent/Drivers/CMSIS/Include/core_starmc1.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/mpu_armv7.h b/firmware/67percent/Drivers/CMSIS/Include/mpu_armv7.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/mpu_armv7.h rename to firmware/67percent/Drivers/CMSIS/Include/mpu_armv7.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/mpu_armv8.h b/firmware/67percent/Drivers/CMSIS/Include/mpu_armv8.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/mpu_armv8.h rename to firmware/67percent/Drivers/CMSIS/Include/mpu_armv8.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/pac_armv81.h b/firmware/67percent/Drivers/CMSIS/Include/pac_armv81.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/pac_armv81.h rename to firmware/67percent/Drivers/CMSIS/Include/pac_armv81.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/pmu_armv8.h b/firmware/67percent/Drivers/CMSIS/Include/pmu_armv8.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/pmu_armv8.h rename to firmware/67percent/Drivers/CMSIS/Include/pmu_armv8.h diff --git a/firmware/modularkbd/Drivers/CMSIS/Include/tz_context.h b/firmware/67percent/Drivers/CMSIS/Include/tz_context.h similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/Include/tz_context.h rename to firmware/67percent/Drivers/CMSIS/Include/tz_context.h diff --git a/firmware/modularkbd/Drivers/CMSIS/LICENSE.txt b/firmware/67percent/Drivers/CMSIS/LICENSE.txt similarity index 100% rename from firmware/modularkbd/Drivers/CMSIS/LICENSE.txt rename to firmware/67percent/Drivers/CMSIS/LICENSE.txt diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c diff --git a/firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c similarity index 100% rename from firmware/modularkbd/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c rename to firmware/67percent/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c diff --git a/firmware/modularkbd/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h 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rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo 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firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su rename to 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b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o rename to 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a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d similarity index 100% rename from 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a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo diff --git a/firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d b/firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d similarity index 100% rename from firmware/modularkbd/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d rename to firmware/67percent/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d diff --git 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firmware/67percent/Release/USB_DEVICE/App/subdir.mk diff --git a/firmware/modularkbd/Release/USB_DEVICE/App/usb_device.cyclo b/firmware/67percent/Release/USB_DEVICE/App/usb_device.cyclo similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/App/usb_device.cyclo rename to firmware/67percent/Release/USB_DEVICE/App/usb_device.cyclo diff --git a/firmware/modularkbd/Release/USB_DEVICE/App/usb_device.d b/firmware/67percent/Release/USB_DEVICE/App/usb_device.d similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/App/usb_device.d rename to firmware/67percent/Release/USB_DEVICE/App/usb_device.d diff --git a/firmware/modularkbd/Release/USB_DEVICE/App/usb_device.o b/firmware/67percent/Release/USB_DEVICE/App/usb_device.o similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/App/usb_device.o rename to firmware/67percent/Release/USB_DEVICE/App/usb_device.o diff --git a/firmware/modularkbd/Release/USB_DEVICE/App/usb_device.su b/firmware/67percent/Release/USB_DEVICE/App/usb_device.su similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/App/usb_device.su rename to firmware/67percent/Release/USB_DEVICE/App/usb_device.su diff --git a/firmware/modularkbd/Release/USB_DEVICE/App/usbd_desc.cyclo b/firmware/67percent/Release/USB_DEVICE/App/usbd_desc.cyclo similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/App/usbd_desc.cyclo rename to firmware/67percent/Release/USB_DEVICE/App/usbd_desc.cyclo diff --git a/firmware/modularkbd/Release/USB_DEVICE/App/usbd_desc.d b/firmware/67percent/Release/USB_DEVICE/App/usbd_desc.d similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/App/usbd_desc.d rename to firmware/67percent/Release/USB_DEVICE/App/usbd_desc.d diff --git a/firmware/modularkbd/Release/USB_DEVICE/App/usbd_desc.o b/firmware/67percent/Release/USB_DEVICE/App/usbd_desc.o similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/App/usbd_desc.o rename to firmware/67percent/Release/USB_DEVICE/App/usbd_desc.o diff --git a/firmware/modularkbd/Release/USB_DEVICE/App/usbd_desc.su b/firmware/67percent/Release/USB_DEVICE/App/usbd_desc.su similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/App/usbd_desc.su rename to firmware/67percent/Release/USB_DEVICE/App/usbd_desc.su diff --git a/firmware/modularkbd/Release/USB_DEVICE/Target/subdir.mk b/firmware/67percent/Release/USB_DEVICE/Target/subdir.mk similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/Target/subdir.mk rename to firmware/67percent/Release/USB_DEVICE/Target/subdir.mk diff --git a/firmware/modularkbd/Release/USB_DEVICE/Target/usbd_conf.cyclo b/firmware/67percent/Release/USB_DEVICE/Target/usbd_conf.cyclo similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/Target/usbd_conf.cyclo rename to firmware/67percent/Release/USB_DEVICE/Target/usbd_conf.cyclo diff --git a/firmware/modularkbd/Release/USB_DEVICE/Target/usbd_conf.d b/firmware/67percent/Release/USB_DEVICE/Target/usbd_conf.d similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/Target/usbd_conf.d rename to firmware/67percent/Release/USB_DEVICE/Target/usbd_conf.d diff --git a/firmware/modularkbd/Release/USB_DEVICE/Target/usbd_conf.o b/firmware/67percent/Release/USB_DEVICE/Target/usbd_conf.o similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/Target/usbd_conf.o rename to firmware/67percent/Release/USB_DEVICE/Target/usbd_conf.o diff --git a/firmware/modularkbd/Release/USB_DEVICE/Target/usbd_conf.su b/firmware/67percent/Release/USB_DEVICE/Target/usbd_conf.su similarity index 100% rename from firmware/modularkbd/Release/USB_DEVICE/Target/usbd_conf.su rename to firmware/67percent/Release/USB_DEVICE/Target/usbd_conf.su diff --git a/firmware/modularkbd/Release/makefile b/firmware/67percent/Release/makefile similarity index 100% rename from firmware/modularkbd/Release/makefile rename to firmware/67percent/Release/makefile diff --git a/firmware/modularkbd/Release/modularkbd.elf b/firmware/67percent/Release/modularkbd.elf similarity index 100% rename from firmware/modularkbd/Release/modularkbd.elf rename to firmware/67percent/Release/modularkbd.elf diff --git a/firmware/modularkbd/Release/modularkbd.list b/firmware/67percent/Release/modularkbd.list similarity index 100% rename from firmware/modularkbd/Release/modularkbd.list rename to firmware/67percent/Release/modularkbd.list diff --git a/firmware/modularkbd/Release/modularkbd.map b/firmware/67percent/Release/modularkbd.map similarity index 100% rename from firmware/modularkbd/Release/modularkbd.map rename to firmware/67percent/Release/modularkbd.map diff --git a/firmware/modularkbd/Release/objects.list b/firmware/67percent/Release/objects.list similarity index 100% rename from firmware/modularkbd/Release/objects.list rename to firmware/67percent/Release/objects.list diff --git a/firmware/modularkbd/Release/objects.mk b/firmware/67percent/Release/objects.mk similarity index 100% rename from firmware/modularkbd/Release/objects.mk rename to firmware/67percent/Release/objects.mk diff --git a/firmware/modularkbd/Release/sources.mk b/firmware/67percent/Release/sources.mk similarity index 100% rename from firmware/modularkbd/Release/sources.mk rename to firmware/67percent/Release/sources.mk diff --git a/firmware/modularkbd/STM32F446RETX_FLASH.ld b/firmware/67percent/STM32F446RETX_FLASH.ld similarity index 100% rename from firmware/modularkbd/STM32F446RETX_FLASH.ld rename to firmware/67percent/STM32F446RETX_FLASH.ld diff --git a/firmware/modularkbd/STM32F446RETX_RAM.ld b/firmware/67percent/STM32F446RETX_RAM.ld similarity index 100% rename from firmware/modularkbd/STM32F446RETX_RAM.ld rename to firmware/67percent/STM32F446RETX_RAM.ld diff --git a/firmware/modularkbd/USB_DEVICE/App/usb_device.c b/firmware/67percent/USB_DEVICE/App/usb_device.c similarity index 100% rename from firmware/modularkbd/USB_DEVICE/App/usb_device.c rename to firmware/67percent/USB_DEVICE/App/usb_device.c diff --git a/firmware/modularkbd/USB_DEVICE/App/usb_device.h b/firmware/67percent/USB_DEVICE/App/usb_device.h similarity index 100% rename from firmware/modularkbd/USB_DEVICE/App/usb_device.h rename to firmware/67percent/USB_DEVICE/App/usb_device.h diff --git a/firmware/modularkbd/USB_DEVICE/App/usbd_desc.c b/firmware/67percent/USB_DEVICE/App/usbd_desc.c similarity index 100% rename from firmware/modularkbd/USB_DEVICE/App/usbd_desc.c rename to firmware/67percent/USB_DEVICE/App/usbd_desc.c diff --git a/firmware/modularkbd/USB_DEVICE/App/usbd_desc.h b/firmware/67percent/USB_DEVICE/App/usbd_desc.h similarity index 100% rename from firmware/modularkbd/USB_DEVICE/App/usbd_desc.h rename to firmware/67percent/USB_DEVICE/App/usbd_desc.h diff --git a/firmware/modularkbd/USB_DEVICE/Target/usbd_conf.c b/firmware/67percent/USB_DEVICE/Target/usbd_conf.c similarity index 100% rename from firmware/modularkbd/USB_DEVICE/Target/usbd_conf.c rename to firmware/67percent/USB_DEVICE/Target/usbd_conf.c diff --git a/firmware/modularkbd/USB_DEVICE/Target/usbd_conf.h b/firmware/67percent/USB_DEVICE/Target/usbd_conf.h similarity index 100% rename from firmware/modularkbd/USB_DEVICE/Target/usbd_conf.h rename to firmware/67percent/USB_DEVICE/Target/usbd_conf.h diff --git a/firmware/modularkbd/modularkbd.ioc b/firmware/67percent/modularkbd.ioc similarity index 100% rename from firmware/modularkbd/modularkbd.ioc rename to firmware/67percent/modularkbd.ioc diff --git a/firmware/modularkbd/modularkbd.launch b/firmware/67percent/modularkbd.launch similarity index 100% rename from firmware/modularkbd/modularkbd.launch rename to firmware/67percent/modularkbd.launch diff --git a/firmware/numpad/.cproject b/firmware/numpad/.cproject new file mode 100644 index 00000000..81260053 --- /dev/null +++ b/firmware/numpad/.cproject @@ -0,0 +1,189 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/firmware/numpad/.mxproject b/firmware/numpad/.mxproject new file mode 100644 index 00000000..b071a477 --- /dev/null +++ b/firmware/numpad/.mxproject @@ -0,0 +1,45 @@ +[PreviousLibFiles] +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dmamux.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dmamux.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cachel1_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm55.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cm85.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_starmc1.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/pac_armv81.h;Drivers/CMSIS/Include/pmu_armv8.h;Drivers/CMSIS/Include/tz_context.h; + +[PreviousUsedCubeIDEFiles] +SourceFiles=Core/Src/main.c;Core/Src/gpio.c;Core/Src/dma.c;Core/Src/i2c.c;Core/Src/tim.c;Core/Src/usart.c;USB_DEVICE/App/usb_device.c;USB_DEVICE/Target/usbd_conf.c;USB_DEVICE/App/usbd_desc.c;Core/Src/stm32f4xx_it.c;Core/Src/stm32f4xx_hal_msp.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Core/Src/system_stm32f4xx.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Core/Src/system_stm32f4xx.c;;;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c; +HeaderPath=Drivers/STM32F4xx_HAL_Driver/Inc;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;Middlewares/ST/STM32_USB_Device_Library/Core/Inc;Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc;Drivers/CMSIS/Device/ST/STM32F4xx/Include;Drivers/CMSIS/Include;Core/Inc;USB_DEVICE/App;USB_DEVICE/Target; +CDefines=USE_HAL_DRIVER;STM32F446xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=11 +HeaderFiles#0=../Core/Inc/gpio.h +HeaderFiles#1=../Core/Inc/dma.h +HeaderFiles#2=../Core/Inc/i2c.h +HeaderFiles#3=../Core/Inc/tim.h +HeaderFiles#4=../Core/Inc/usart.h +HeaderFiles#5=../USB_DEVICE/App/usb_device.h +HeaderFiles#6=../USB_DEVICE/Target/usbd_conf.h +HeaderFiles#7=../USB_DEVICE/App/usbd_desc.h +HeaderFiles#8=../Core/Inc/stm32f4xx_it.h +HeaderFiles#9=../Core/Inc/stm32f4xx_hal_conf.h +HeaderFiles#10=../Core/Inc/main.h +HeaderFolderListSize=3 +HeaderPath#0=../Core/Inc +HeaderPath#1=../USB_DEVICE/App +HeaderPath#2=../USB_DEVICE/Target +HeaderFiles=; +SourceFileListSize=11 +SourceFiles#0=../Core/Src/gpio.c +SourceFiles#1=../Core/Src/dma.c +SourceFiles#2=../Core/Src/i2c.c +SourceFiles#3=../Core/Src/tim.c +SourceFiles#4=../Core/Src/usart.c +SourceFiles#5=../USB_DEVICE/App/usb_device.c +SourceFiles#6=../USB_DEVICE/Target/usbd_conf.c +SourceFiles#7=../USB_DEVICE/App/usbd_desc.c +SourceFiles#8=../Core/Src/stm32f4xx_it.c +SourceFiles#9=../Core/Src/stm32f4xx_hal_msp.c +SourceFiles#10=../Core/Src/main.c +SourceFolderListSize=3 +SourcePath#0=../Core/Src +SourcePath#1=../USB_DEVICE/App +SourcePath#2=../USB_DEVICE/Target +SourceFiles=; + diff --git a/firmware/numpad/.project b/firmware/numpad/.project new file mode 100644 index 00000000..3dcc683b --- /dev/null +++ b/firmware/numpad/.project @@ -0,0 +1,32 @@ + + + modularkbd + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/firmware/numpad/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/firmware/numpad/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs new file mode 100644 index 00000000..98a69fc7 --- /dev/null +++ b/firmware/numpad/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}} diff --git a/firmware/modularkbd/.settings/language.settings.xml b/firmware/numpad/.settings/language.settings.xml similarity index 100% rename from firmware/modularkbd/.settings/language.settings.xml rename to firmware/numpad/.settings/language.settings.xml diff --git a/firmware/numpad/.settings/org.eclipse.core.resources.prefs b/firmware/numpad/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..99f26c02 --- /dev/null +++ b/firmware/numpad/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 diff --git a/firmware/numpad/.settings/stm32cubeide.project.prefs b/firmware/numpad/.settings/stm32cubeide.project.prefs new file mode 100644 index 00000000..312ed386 --- /dev/null +++ b/firmware/numpad/.settings/stm32cubeide.project.prefs @@ -0,0 +1,5 @@ +635E684B79701B039C64EA45C3F84D30=995AAB8BA274295E2F8F7F317CB52865 +66BE74F758C12D739921AEA421D593D3=0 +8DF89ED150041C4CBC7CB9A9CAA90856=CFE0804C550E33C5B9DAB17F678FB68D +DC22A860405A8BF2F2C095E5B6529F12=CFE0804C550E33C5B9DAB17F678FB68D +eclipse.preferences.version=1 diff --git a/firmware/numpad/Core/Inc/Backup/dma.h.bak b/firmware/numpad/Core/Inc/Backup/dma.h.bak new file mode 100644 index 00000000..b8744950 --- /dev/null +++ b/firmware/numpad/Core/Inc/Backup/dma.h.bak @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H__ +#define __DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* DMA memory to memory transfer handles -------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_H__ */ + diff --git a/firmware/numpad/Core/Inc/Backup/gpio.h.bak b/firmware/numpad/Core/Inc/Backup/gpio.h.bak new file mode 100644 index 00000000..8ba7de1e --- /dev/null +++ b/firmware/numpad/Core/Inc/Backup/gpio.h.bak @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + diff --git a/firmware/numpad/Core/Inc/Backup/i2c.h.bak b/firmware/numpad/Core/Inc/Backup/i2c.h.bak new file mode 100644 index 00000000..4d3f631f --- /dev/null +++ b/firmware/numpad/Core/Inc/Backup/i2c.h.bak @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.h + * @brief This file contains all the function prototypes for + * the i2c.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern I2C_HandleTypeDef hi2c1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_I2C1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2C_H__ */ + diff --git a/firmware/numpad/Core/Inc/Backup/main.h.bak b/firmware/numpad/Core/Inc/Backup/main.h.bak new file mode 100644 index 00000000..0e09511f --- /dev/null +++ b/firmware/numpad/Core/Inc/Backup/main.h.bak @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +// Modifier Keys +#define KEY_LEFT_CTRL 0xE0 +#define KEY_LEFT_SHIFT 0xE1 +#define KEY_LEFT_ALT 0xE2 +#define KEY_LEFT_GUI 0xE3 +#define KEY_RIGHT_CTRL 0xE4 +#define KEY_RIGHT_SHIFT 0xE5 +#define KEY_RIGHT_ALT 0xE6 +#define KEY_RIGHT_GUI 0xE7 + +// Regular Keys (Usage ID 0x04–0x73) +#define KEY_A 0x04 +#define KEY_B 0x05 +#define KEY_C 0x06 +#define KEY_D 0x07 +#define KEY_E 0x08 +#define KEY_F 0x09 +#define KEY_G 0x0A +#define KEY_H 0x0B +#define KEY_I 0x0C +#define KEY_J 0x0D +#define KEY_K 0x0E +#define KEY_L 0x0F +#define KEY_M 0x10 +#define KEY_N 0x11 +#define KEY_O 0x12 +#define KEY_P 0x13 +#define KEY_Q 0x14 +#define KEY_R 0x15 +#define KEY_S 0x16 +#define KEY_T 0x17 +#define KEY_U 0x18 +#define KEY_V 0x19 +#define KEY_W 0x1A +#define KEY_X 0x1B +#define KEY_Y 0x1C +#define KEY_Z 0x1D + +#define KEY_1 0x1E +#define KEY_2 0x1F +#define KEY_3 0x20 +#define KEY_4 0x21 +#define KEY_5 0x22 +#define KEY_6 0x23 +#define KEY_7 0x24 +#define KEY_8 0x25 +#define KEY_9 0x26 +#define KEY_0 0x27 + +#define KEY_ENTER 0x28 +#define KEY_ESC 0x29 +#define KEY_BACKSPACE 0x2A +#define KEY_TAB 0x2B +#define KEY_SPACE 0x2C +#define KEY_MINUS 0x2D +#define KEY_EQUAL 0x2E +#define KEY_LEFT_BRACKET 0x2F +#define KEY_RIGHT_BRACKET 0x30 +#define KEY_BACKSLASH 0x31 +#define KEY_NON_US_HASH 0x32 +#define KEY_SEMICOLON 0x33 +#define KEY_APOSTROPHE 0x34 +#define KEY_GRAVE 0x35 +#define KEY_COMMA 0x36 +#define KEY_PERIOD 0x37 +#define KEY_SLASH 0x38 +#define KEY_CAPS_LOCK 0x39 + +// Function Keys +#define KEY_F1 0x3A +#define KEY_F2 0x3B +#define KEY_F3 0x3C +#define KEY_F4 0x3D +#define KEY_F5 0x3E +#define KEY_F6 0x3F +#define KEY_F7 0x40 +#define KEY_F8 0x41 +#define KEY_F9 0x42 +#define KEY_F10 0x43 +#define KEY_F11 0x44 +#define KEY_F12 0x45 + +#define KEY_PRINT_SCREEN 0x46 +#define KEY_SCROLL_LOCK 0x47 +#define KEY_PAUSE 0x48 + +// Navigation Keys +#define KEY_INSERT 0x49 +#define KEY_HOME 0x4A +#define KEY_PAGE_UP 0x4B +#define KEY_DELETE 0x4C +#define KEY_END 0x4D +#define KEY_PAGE_DOWN 0x4E + +#define KEY_RIGHT_ARROW 0x4F +#define KEY_LEFT_ARROW 0x50 +#define KEY_DOWN_ARROW 0x51 +#define KEY_UP_ARROW 0x52 + +// Keypad +#define NUM_LOCK 0x53 +#define KEYPAD_SLASH 0x54 +#define KEYPAD_ASTERISK 0x55 +#define KEYPAD_MINUS 0x56 +#define KEYPAD_PLUS 0x57 +#define KEYPAD_ENTER 0x58 +#define KEYPAD_1 0x59 +#define KEYPAD_2 0x5A +#define KEYPAD_3 0x5B +#define KEYPAD_4 0x5C +#define KEYPAD_5 0x5D +#define KEYPAD_6 0x5E +#define KEYPAD_7 0x5F +#define KEYPAD_8 0x60 +#define KEYPAD_9 0x61 +#define KEYPAD_0 0x62 +#define KEYPAD_DOT 0x63 + +// Misc/Non-US +#define KEY_NON_US_BACKSLASH 0x64 +#define KEY_APPLICATION 0x65 +#define KEY_POWER 0x66 +#define KEYPAD_EQUAL 0x67 +#define KEY_F13 0x68 +#define KEY_F14 0x69 +#define KEY_F15 0x6A +#define KEY_F16 0x6B +#define KEY_F17 0x6C +#define KEY_F18 0x6D +#define KEY_F19 0x6E +#define KEY_F20 0x6F +#define KEY_F21 0x70 +#define KEY_F22 0x71 +#define KEY_F23 0x72 +#define KEY_F24 0x73 +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/firmware/numpad/Core/Inc/Backup/stm32f4xx_hal_conf.h.bak b/firmware/numpad/Core/Inc/Backup/stm32f4xx_hal_conf.h.bak new file mode 100644 index 00000000..fac4fa4e --- /dev/null +++ b/firmware/numpad/Core/Inc/Backup/stm32f4xx_hal_conf.h.bak @@ -0,0 +1,495 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_FMPSMBUS_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ +#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY 0x000000FFU +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY 0x00000FFFU + +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_FMPSMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_fmpsmbus.h" +#endif /* HAL_FMPSMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ diff --git a/firmware/numpad/Core/Inc/Backup/stm32f4xx_it.h.bak b/firmware/numpad/Core/Inc/Backup/stm32f4xx_it.h.bak new file mode 100644 index 00000000..bfc8aa91 --- /dev/null +++ b/firmware/numpad/Core/Inc/Backup/stm32f4xx_it.h.bak @@ -0,0 +1,79 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void DMA1_Stream0_IRQHandler(void); +void DMA1_Stream2_IRQHandler(void); +void DMA1_Stream4_IRQHandler(void); +void DMA1_Stream5_IRQHandler(void); +void DMA1_Stream6_IRQHandler(void); +void USART1_IRQHandler(void); +void USART2_IRQHandler(void); +void DMA1_Stream7_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void DMA2_Stream2_IRQHandler(void); +void OTG_FS_IRQHandler(void); +void DMA2_Stream7_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ diff --git a/firmware/numpad/Core/Inc/Backup/tim.h.bak b/firmware/numpad/Core/Inc/Backup/tim.h.bak new file mode 100644 index 00000000..f689f344 --- /dev/null +++ b/firmware/numpad/Core/Inc/Backup/tim.h.bak @@ -0,0 +1,57 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern TIM_HandleTypeDef htim2; + +extern TIM_HandleTypeDef htim3; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_TIM2_Init(void); +void MX_TIM3_Init(void); + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ + diff --git a/firmware/numpad/Core/Inc/Backup/usart.h.bak b/firmware/numpad/Core/Inc/Backup/usart.h.bak new file mode 100644 index 00000000..b62ed639 --- /dev/null +++ b/firmware/numpad/Core/Inc/Backup/usart.h.bak @@ -0,0 +1,61 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.h + * @brief This file contains all the function prototypes for + * the usart.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern UART_HandleTypeDef huart4; + +extern UART_HandleTypeDef huart5; + +extern UART_HandleTypeDef huart1; + +extern UART_HandleTypeDef huart2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_UART4_Init(void); +void MX_UART5_Init(void); +void MX_USART1_UART_Init(void); +void MX_USART2_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_H__ */ + diff --git a/firmware/numpad/Core/Inc/dma.h b/firmware/numpad/Core/Inc/dma.h new file mode 100644 index 00000000..b8744950 --- /dev/null +++ b/firmware/numpad/Core/Inc/dma.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H__ +#define __DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* DMA memory to memory transfer handles -------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_H__ */ + diff --git a/firmware/numpad/Core/Inc/gpio.h b/firmware/numpad/Core/Inc/gpio.h new file mode 100644 index 00000000..8ba7de1e --- /dev/null +++ b/firmware/numpad/Core/Inc/gpio.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + diff --git a/firmware/numpad/Core/Inc/hid_queue.h b/firmware/numpad/Core/Inc/hid_queue.h new file mode 100644 index 00000000..8198b981 --- /dev/null +++ b/firmware/numpad/Core/Inc/hid_queue.h @@ -0,0 +1,33 @@ +#ifndef HID_QUEUE_H +#define HID_QUEUE_H + +#include +#include + +typedef struct { + uint8_t MODIFIER; // Modifier keys (Ctrl, Shift, Alt, Win) + uint8_t RESERVED; // Always 0 + uint8_t KEYPRESS[12]; // Up to 12 keycodes +} __attribute__((packed)) HIDReport; + +typedef struct { + HIDReport *buffer; + uint16_t capacity; + uint16_t head; + uint16_t tail; + uint16_t count; +} HIDQueue; + +// Init + reset +bool hid_queue_init(HIDQueue *q, HIDReport *buffer, uint16_t capacity); +void hid_queue_reset(HIDQueue *q); + +// FIFO Ops +bool hid_queue_push(HIDQueue *q, HIDReport item); +bool hid_queue_pop(HIDQueue *q, HIDReport *out); + +// Helpers +bool hid_queue_is_empty(HIDQueue *q); +bool hid_queue_is_full(HIDQueue *q); + +#endif diff --git a/firmware/numpad/Core/Inc/i2c.h b/firmware/numpad/Core/Inc/i2c.h new file mode 100644 index 00000000..4d3f631f --- /dev/null +++ b/firmware/numpad/Core/Inc/i2c.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.h + * @brief This file contains all the function prototypes for + * the i2c.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern I2C_HandleTypeDef hi2c1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_I2C1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2C_H__ */ + diff --git a/firmware/numpad/Core/Inc/main.h b/firmware/numpad/Core/Inc/main.h new file mode 100644 index 00000000..0e09511f --- /dev/null +++ b/firmware/numpad/Core/Inc/main.h @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ +// Modifier Keys +#define KEY_LEFT_CTRL 0xE0 +#define KEY_LEFT_SHIFT 0xE1 +#define KEY_LEFT_ALT 0xE2 +#define KEY_LEFT_GUI 0xE3 +#define KEY_RIGHT_CTRL 0xE4 +#define KEY_RIGHT_SHIFT 0xE5 +#define KEY_RIGHT_ALT 0xE6 +#define KEY_RIGHT_GUI 0xE7 + +// Regular Keys (Usage ID 0x04–0x73) +#define KEY_A 0x04 +#define KEY_B 0x05 +#define KEY_C 0x06 +#define KEY_D 0x07 +#define KEY_E 0x08 +#define KEY_F 0x09 +#define KEY_G 0x0A +#define KEY_H 0x0B +#define KEY_I 0x0C +#define KEY_J 0x0D +#define KEY_K 0x0E +#define KEY_L 0x0F +#define KEY_M 0x10 +#define KEY_N 0x11 +#define KEY_O 0x12 +#define KEY_P 0x13 +#define KEY_Q 0x14 +#define KEY_R 0x15 +#define KEY_S 0x16 +#define KEY_T 0x17 +#define KEY_U 0x18 +#define KEY_V 0x19 +#define KEY_W 0x1A +#define KEY_X 0x1B +#define KEY_Y 0x1C +#define KEY_Z 0x1D + +#define KEY_1 0x1E +#define KEY_2 0x1F +#define KEY_3 0x20 +#define KEY_4 0x21 +#define KEY_5 0x22 +#define KEY_6 0x23 +#define KEY_7 0x24 +#define KEY_8 0x25 +#define KEY_9 0x26 +#define KEY_0 0x27 + +#define KEY_ENTER 0x28 +#define KEY_ESC 0x29 +#define KEY_BACKSPACE 0x2A +#define KEY_TAB 0x2B +#define KEY_SPACE 0x2C +#define KEY_MINUS 0x2D +#define KEY_EQUAL 0x2E +#define KEY_LEFT_BRACKET 0x2F +#define KEY_RIGHT_BRACKET 0x30 +#define KEY_BACKSLASH 0x31 +#define KEY_NON_US_HASH 0x32 +#define KEY_SEMICOLON 0x33 +#define KEY_APOSTROPHE 0x34 +#define KEY_GRAVE 0x35 +#define KEY_COMMA 0x36 +#define KEY_PERIOD 0x37 +#define KEY_SLASH 0x38 +#define KEY_CAPS_LOCK 0x39 + +// Function Keys +#define KEY_F1 0x3A +#define KEY_F2 0x3B +#define KEY_F3 0x3C +#define KEY_F4 0x3D +#define KEY_F5 0x3E +#define KEY_F6 0x3F +#define KEY_F7 0x40 +#define KEY_F8 0x41 +#define KEY_F9 0x42 +#define KEY_F10 0x43 +#define KEY_F11 0x44 +#define KEY_F12 0x45 + +#define KEY_PRINT_SCREEN 0x46 +#define KEY_SCROLL_LOCK 0x47 +#define KEY_PAUSE 0x48 + +// Navigation Keys +#define KEY_INSERT 0x49 +#define KEY_HOME 0x4A +#define KEY_PAGE_UP 0x4B +#define KEY_DELETE 0x4C +#define KEY_END 0x4D +#define KEY_PAGE_DOWN 0x4E + +#define KEY_RIGHT_ARROW 0x4F +#define KEY_LEFT_ARROW 0x50 +#define KEY_DOWN_ARROW 0x51 +#define KEY_UP_ARROW 0x52 + +// Keypad +#define NUM_LOCK 0x53 +#define KEYPAD_SLASH 0x54 +#define KEYPAD_ASTERISK 0x55 +#define KEYPAD_MINUS 0x56 +#define KEYPAD_PLUS 0x57 +#define KEYPAD_ENTER 0x58 +#define KEYPAD_1 0x59 +#define KEYPAD_2 0x5A +#define KEYPAD_3 0x5B +#define KEYPAD_4 0x5C +#define KEYPAD_5 0x5D +#define KEYPAD_6 0x5E +#define KEYPAD_7 0x5F +#define KEYPAD_8 0x60 +#define KEYPAD_9 0x61 +#define KEYPAD_0 0x62 +#define KEYPAD_DOT 0x63 + +// Misc/Non-US +#define KEY_NON_US_BACKSLASH 0x64 +#define KEY_APPLICATION 0x65 +#define KEY_POWER 0x66 +#define KEYPAD_EQUAL 0x67 +#define KEY_F13 0x68 +#define KEY_F14 0x69 +#define KEY_F15 0x6A +#define KEY_F16 0x6B +#define KEY_F17 0x6C +#define KEY_F18 0x6D +#define KEY_F19 0x6E +#define KEY_F20 0x6F +#define KEY_F21 0x70 +#define KEY_F22 0x71 +#define KEY_F23 0x72 +#define KEY_F24 0x73 +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/firmware/numpad/Core/Inc/stm32f4xx_hal_conf.h b/firmware/numpad/Core/Inc/stm32f4xx_hal_conf.h new file mode 100644 index 00000000..fac4fa4e --- /dev/null +++ b/firmware/numpad/Core/Inc/stm32f4xx_hal_conf.h @@ -0,0 +1,495 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_FMPSMBUS_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ +#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY 0x000000FFU +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY 0x00000FFFU + +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_FMPSMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_fmpsmbus.h" +#endif /* HAL_FMPSMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ diff --git a/firmware/numpad/Core/Inc/stm32f4xx_it.h b/firmware/numpad/Core/Inc/stm32f4xx_it.h new file mode 100644 index 00000000..bfc8aa91 --- /dev/null +++ b/firmware/numpad/Core/Inc/stm32f4xx_it.h @@ -0,0 +1,79 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void DMA1_Stream0_IRQHandler(void); +void DMA1_Stream2_IRQHandler(void); +void DMA1_Stream4_IRQHandler(void); +void DMA1_Stream5_IRQHandler(void); +void DMA1_Stream6_IRQHandler(void); +void USART1_IRQHandler(void); +void USART2_IRQHandler(void); +void DMA1_Stream7_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void DMA2_Stream2_IRQHandler(void); +void OTG_FS_IRQHandler(void); +void DMA2_Stream7_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ diff --git a/firmware/numpad/Core/Inc/tim.h b/firmware/numpad/Core/Inc/tim.h new file mode 100644 index 00000000..f689f344 --- /dev/null +++ b/firmware/numpad/Core/Inc/tim.h @@ -0,0 +1,57 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern TIM_HandleTypeDef htim2; + +extern TIM_HandleTypeDef htim3; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_TIM2_Init(void); +void MX_TIM3_Init(void); + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ + diff --git a/firmware/numpad/Core/Inc/usart.h b/firmware/numpad/Core/Inc/usart.h new file mode 100644 index 00000000..b62ed639 --- /dev/null +++ b/firmware/numpad/Core/Inc/usart.h @@ -0,0 +1,61 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.h + * @brief This file contains all the function prototypes for + * the usart.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern UART_HandleTypeDef huart4; + +extern UART_HandleTypeDef huart5; + +extern UART_HandleTypeDef huart1; + +extern UART_HandleTypeDef huart2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_UART4_Init(void); +void MX_UART5_Init(void); +void MX_USART1_UART_Init(void); +void MX_USART2_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_H__ */ + diff --git a/firmware/numpad/Core/Src/Backup/dma.c.bak b/firmware/numpad/Core/Src/Backup/dma.c.bak new file mode 100644 index 00000000..ea28d29a --- /dev/null +++ b/firmware/numpad/Core/Src/Backup/dma.c.bak @@ -0,0 +1,77 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure DMA */ +/*----------------------------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + __HAL_RCC_DMA2_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Stream0_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); + /* DMA1_Stream2_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); + /* DMA1_Stream4_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); + /* DMA1_Stream5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); + /* DMA1_Stream6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); + /* DMA1_Stream7_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); + /* DMA2_Stream2_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); + /* DMA2_Stream7_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + diff --git a/firmware/numpad/Core/Src/Backup/gpio.c.bak b/firmware/numpad/Core/Src/Backup/gpio.c.bak new file mode 100644 index 00000000..1ac25202 --- /dev/null +++ b/firmware/numpad/Core/Src/Backup/gpio.c.bak @@ -0,0 +1,90 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); + + /*Configure GPIO pins : PC4 PC5 */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pin : PA8 */ + GPIO_InitStruct.Pin = GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/firmware/numpad/Core/Src/Backup/i2c.c.bak b/firmware/numpad/Core/Src/Backup/i2c.c.bak new file mode 100644 index 00000000..1bcb7ec1 --- /dev/null +++ b/firmware/numpad/Core/Src/Backup/i2c.c.bak @@ -0,0 +1,116 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.c + * @brief This file provides code for the configuration + * of the I2C instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "i2c.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +I2C_HandleTypeDef hi2c1; + +/* I2C1 init function */ +void MX_I2C1_Init(void) +{ + + /* USER CODE BEGIN I2C1_Init 0 */ + + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + hi2c1.Init.ClockSpeed = 100000; + hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; + hi2c1.Init.OwnAddress1 = 0; + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c1.Init.OwnAddress2 = 0; + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + +void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* I2C1 clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } +} + +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) +{ + + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7); + + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/firmware/numpad/Core/Src/Backup/main.c.bak b/firmware/numpad/Core/Src/Backup/main.c.bak new file mode 100644 index 00000000..344b7a56 --- /dev/null +++ b/firmware/numpad/Core/Src/Backup/main.c.bak @@ -0,0 +1,329 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "dma.h" +#include "i2c.h" +#include "tim.h" +#include "usart.h" +#include "usb_device.h" +#include "gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "usbd_hid.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +// HID (Human Interface Device) report structure +typedef struct { + uint8_t MODIFIER; // Modifier keys (e.g., Ctrl, Shift, Alt, GUI/Win) + uint8_t RESERVED; // Reserved for alignment, always set to 0 + uint8_t KEYPRESS[12]; // Array holding up to 12 keycodes being pressed +} HIDReport; + + +// Switch pin mapping structure +typedef struct { + GPIO_TypeDef* GPIOx; // Pointer to GPIO port (e.g., GPIOA, GPIOB) + uint16_t PIN; // Pin number on the GPIO port +} SwitchPins; + + +// UART message structure for sending/receiving key events +typedef struct { + uint16_t DEPTH; // Custom field: could represent queue depth, layer, or message size + uint16_t TYPE; // Message type identifier (defines what kind of message this is) + uint8_t KEYPRESS[12]; // Keypress data (similar to HIDReport, but for UART transmission) +} UARTMessage; + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +#define ROW 6 +#define COL 5 +#define MAXQUEUE 256 +#define MODE_INACTIVE 0 +#define MODE_MAINBOARD 1 +#define MODE_ACTIVE 2 +#define MODE_DEBUG 3 +#define UART_RX_BUFF_SIZE 64 +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +// Initialize HID report properly +HIDReport REPORT = {0, 0, {0}}; + +SwitchPins ROW_PINS[ROW] = { + {GPIOB, GPIO_PIN_10}, + {GPIOB, GPIO_PIN_2}, + {GPIOB, GPIO_PIN_1}, + {GPIOB, GPIO_PIN_0}, + {GPIOC, GPIO_PIN_5}, + {GPIOC, GPIO_PIN_4}, +}; + +SwitchPins COLUMN_PINS[COL] = { + {GPIOA, GPIO_PIN_8}, + {GPIOC, GPIO_PIN_9}, + {GPIOC, GPIO_PIN_8}, + {GPIOC, GPIO_PIN_7}, + {GPIOC, GPIO_PIN_5} +}; + +// Initialize keycodes array +uint8_t KEYCODES[ROW][COL] = { + {0x00, KEY_F13, KEY_F14, KEY_F15, KEY_F16}, + {KEY_F17, NUM_LOCK, KEYPAD_SLASH, KEYPAD_ASTERISK, KEYPAD_MINUS}, + {KEY_F18, KEYPAD_7, KEYPAD_8, KEYPAD_9, KEYPAD_PLUS}, + {KEY_F19, KEYPAD_4, KEYPAD_5, KEYPAD_6, 0x00}, + {KEY_F20, KEYPAD_1, KEYPAD_2, KEYPAD_3, KEYPAD_ENTER}, + {KEY_F21, KEYPAD_0, 0x00, KEYPAD_DOT, 0x00} +}; + +uint16_t DEPTH = 0; + +extern USBD_HandleTypeDef hUsbDeviceFS; +volatile uint8_t MODE = MODE_INACTIVE; + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +/* USER CODE BEGIN PFP */ +void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *huart); +void UART_DMA_SendReport(UART_HandleTypeDef *huart); +void addUSBReport(uint8_t usageID); +void matrixScan(void); +void resetReport(void); +void sendMessage(void); +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_DMA_Init(); + MX_TIM2_Init(); + MX_TIM3_Init(); + MX_UART4_Init(); + MX_UART5_Init(); + MX_USART1_UART_Init(); + MX_USART2_UART_Init(); + MX_I2C1_Init(); + MX_USB_DEVICE_Init(); + /* USER CODE BEGIN 2 */ + + UARTMessage REQ; + REQ.TYPE = 0xFF; //Message code for request is 0xFF + HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); + + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + switch (MODE){ + case MODE_ACTIVE: + resetReport(); + matrixScan(); + break; + + case MODE_INACTIVE: + //If the module is connected through the USB then mode is mainboard + if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ + MODE = MODE_MAINBOARD; + DEPTH = 0; + }else{ + //TODO: Look for a parent module... UARTMessage REQ; + } + break; + + case MODE_MAINBOARD: + resetReport(); + matrixScan(); + USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); + break; + } + HAL_Delay(50); + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 96; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ +//UART Message Requests Goes Here +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart){ + +} + +//TODO: A function that gets called by RX Interrupt to handle messages that get sent +void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender){ + //TODO: Handle messages coming from devices based on the message type... +} + +void addUSBReport(uint8_t usageID){ + if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds + uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit + uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array + uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset + REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); +} + +void matrixScan(void){ + for (uint8_t col = 0; col < COL; col++){ + HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); + HAL_Delay(1); + for(uint8_t row = 0; row < ROW; row++){ + if(HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN)){ + addUSBReport(KEYCODES[row][col]); + } + } + HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); + } +} + +void resetReport(void){ + REPORT.MODIFIER = 0; + memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); +} + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/firmware/numpad/Core/Src/Backup/stm32f4xx_hal_msp.c.bak b/firmware/numpad/Core/Src/Backup/stm32f4xx_hal_msp.c.bak new file mode 100644 index 00000000..00c02c33 --- /dev/null +++ b/firmware/numpad/Core/Src/Backup/stm32f4xx_hal_msp.c.bak @@ -0,0 +1,82 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/firmware/numpad/Core/Src/Backup/stm32f4xx_it.c.bak b/firmware/numpad/Core/Src/Backup/stm32f4xx_it.c.bak new file mode 100644 index 00000000..4b0a65d4 --- /dev/null +++ b/firmware/numpad/Core/Src/Backup/stm32f4xx_it.c.bak @@ -0,0 +1,397 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern PCD_HandleTypeDef hpcd_USB_OTG_FS; +extern DMA_HandleTypeDef hdma_uart4_rx; +extern DMA_HandleTypeDef hdma_uart4_tx; +extern DMA_HandleTypeDef hdma_uart5_rx; +extern DMA_HandleTypeDef hdma_uart5_tx; +extern DMA_HandleTypeDef hdma_usart1_rx; +extern DMA_HandleTypeDef hdma_usart1_tx; +extern DMA_HandleTypeDef hdma_usart2_rx; +extern DMA_HandleTypeDef hdma_usart2_tx; +extern UART_HandleTypeDef huart4; +extern UART_HandleTypeDef huart5; +extern UART_HandleTypeDef huart1; +extern UART_HandleTypeDef huart2; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles DMA1 stream0 global interrupt. + */ +void DMA1_Stream0_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ + + /* USER CODE END DMA1_Stream0_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart5_rx); + /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ + + /* USER CODE END DMA1_Stream0_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream2 global interrupt. + */ +void DMA1_Stream2_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ + + /* USER CODE END DMA1_Stream2_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart4_rx); + /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ + + /* USER CODE END DMA1_Stream2_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream4 global interrupt. + */ +void DMA1_Stream4_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ + + /* USER CODE END DMA1_Stream4_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart4_tx); + /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ + + /* USER CODE END DMA1_Stream4_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream5 global interrupt. + */ +void DMA1_Stream5_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ + + /* USER CODE END DMA1_Stream5_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_rx); + /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ + + /* USER CODE END DMA1_Stream5_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream6 global interrupt. + */ +void DMA1_Stream6_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ + + /* USER CODE END DMA1_Stream6_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_tx); + /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ + + /* USER CODE END DMA1_Stream6_IRQn 1 */ +} + +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + +/** + * @brief This function handles USART2 global interrupt. + */ +void USART2_IRQHandler(void) +{ + /* USER CODE BEGIN USART2_IRQn 0 */ + + /* USER CODE END USART2_IRQn 0 */ + HAL_UART_IRQHandler(&huart2); + /* USER CODE BEGIN USART2_IRQn 1 */ + + /* USER CODE END USART2_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream7 global interrupt. + */ +void DMA1_Stream7_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ + + /* USER CODE END DMA1_Stream7_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart5_tx); + /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ + + /* USER CODE END DMA1_Stream7_IRQn 1 */ +} + +/** + * @brief This function handles UART4 global interrupt. + */ +void UART4_IRQHandler(void) +{ + /* USER CODE BEGIN UART4_IRQn 0 */ + + /* USER CODE END UART4_IRQn 0 */ + HAL_UART_IRQHandler(&huart4); + /* USER CODE BEGIN UART4_IRQn 1 */ + + /* USER CODE END UART4_IRQn 1 */ +} + +/** + * @brief This function handles UART5 global interrupt. + */ +void UART5_IRQHandler(void) +{ + /* USER CODE BEGIN UART5_IRQn 0 */ + + /* USER CODE END UART5_IRQn 0 */ + HAL_UART_IRQHandler(&huart5); + /* USER CODE BEGIN UART5_IRQn 1 */ + + /* USER CODE END UART5_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream2 global interrupt. + */ +void DMA2_Stream2_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ + + /* USER CODE END DMA2_Stream2_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart1_rx); + /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ + + /* USER CODE END DMA2_Stream2_IRQn 1 */ +} + +/** + * @brief This function handles USB On The Go FS global interrupt. + */ +void OTG_FS_IRQHandler(void) +{ + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); + /* USER CODE BEGIN OTG_FS_IRQn 1 */ + + /* USER CODE END OTG_FS_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream7 global interrupt. + */ +void DMA2_Stream7_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ + + /* USER CODE END DMA2_Stream7_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart1_tx); + /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ + + /* USER CODE END DMA2_Stream7_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/firmware/numpad/Core/Src/Backup/syscalls.c.bak b/firmware/numpad/Core/Src/Backup/syscalls.c.bak new file mode 100644 index 00000000..8884b5aa --- /dev/null +++ b/firmware/numpad/Core/Src/Backup/syscalls.c.bak @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/firmware/numpad/Core/Src/Backup/sysmem.c.bak b/firmware/numpad/Core/Src/Backup/sysmem.c.bak new file mode 100644 index 00000000..5d9f7e67 --- /dev/null +++ b/firmware/numpad/Core/Src/Backup/sysmem.c.bak @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/firmware/numpad/Core/Src/Backup/system_stm32f4xx.c.bak b/firmware/numpad/Core/Src/Backup/system_stm32f4xx.c.bak new file mode 100644 index 00000000..7a61e9cf --- /dev/null +++ b/firmware/numpad/Core/Src/Backup/system_stm32f4xx.c.bak @@ -0,0 +1,747 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp, pllvco, pllp, pllsource, pllm; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/firmware/numpad/Core/Src/Backup/tim.c.bak b/firmware/numpad/Core/Src/Backup/tim.c.bak new file mode 100644 index 00000000..62b4ea70 --- /dev/null +++ b/firmware/numpad/Core/Src/Backup/tim.c.bak @@ -0,0 +1,233 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim3; + +/* TIM2 init function */ +void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 4294967295; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_OC_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + HAL_TIM_MspPostInit(&htim2); + +} +/* TIM3 init function */ +void MX_TIM3_Init(void) +{ + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + htim3.Init.Prescaler = 0; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.Period = 65535; + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + sConfig.EncoderMode = TIM_ENCODERMODE_TI1; + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + sConfig.IC1Filter = 0; + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + sConfig.IC2Filter = 0; + if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + +} + +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle) +{ + + if(tim_ocHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* TIM2 clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } +} + +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(tim_encoderHandle->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* TIM3 clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM3 GPIO Configuration + PA6 ------> TIM3_CH1 + PA7 ------> TIM3_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } +} +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(timHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspPostInit 0 */ + + /* USER CODE END TIM2_MspPostInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM2 GPIO Configuration + PA5 ------> TIM2_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM2_MspPostInit 1 */ + + /* USER CODE END TIM2_MspPostInit 1 */ + } + +} + +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef* tim_ocHandle) +{ + + if(tim_ocHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } +} + +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* tim_encoderHandle) +{ + + if(tim_encoderHandle->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + + /**TIM3 GPIO Configuration + PA6 ------> TIM3_CH1 + PA7 ------> TIM3_CH2 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6|GPIO_PIN_7); + + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/firmware/numpad/Core/Src/Backup/usart.c.bak b/firmware/numpad/Core/Src/Backup/usart.c.bak new file mode 100644 index 00000000..8cf0a4e4 --- /dev/null +++ b/firmware/numpad/Core/Src/Backup/usart.c.bak @@ -0,0 +1,530 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +UART_HandleTypeDef huart4; +UART_HandleTypeDef huart5; +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart2; +DMA_HandleTypeDef hdma_uart4_rx; +DMA_HandleTypeDef hdma_uart4_tx; +DMA_HandleTypeDef hdma_uart5_rx; +DMA_HandleTypeDef hdma_uart5_tx; +DMA_HandleTypeDef hdma_usart1_rx; +DMA_HandleTypeDef hdma_usart1_tx; +DMA_HandleTypeDef hdma_usart2_rx; +DMA_HandleTypeDef hdma_usart2_tx; + +/* UART4 init function */ +void MX_UART4_Init(void) +{ + + /* USER CODE BEGIN UART4_Init 0 */ + + /* USER CODE END UART4_Init 0 */ + + /* USER CODE BEGIN UART4_Init 1 */ + + /* USER CODE END UART4_Init 1 */ + huart4.Instance = UART4; + huart4.Init.BaudRate = 115200; + huart4.Init.WordLength = UART_WORDLENGTH_8B; + huart4.Init.StopBits = UART_STOPBITS_1; + huart4.Init.Parity = UART_PARITY_NONE; + huart4.Init.Mode = UART_MODE_TX_RX; + huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart4.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN UART4_Init 2 */ + + /* USER CODE END UART4_Init 2 */ + +} +/* UART5 init function */ +void MX_UART5_Init(void) +{ + + /* USER CODE BEGIN UART5_Init 0 */ + + /* USER CODE END UART5_Init 0 */ + + /* USER CODE BEGIN UART5_Init 1 */ + + /* USER CODE END UART5_Init 1 */ + huart5.Instance = UART5; + huart5.Init.BaudRate = 115200; + huart5.Init.WordLength = UART_WORDLENGTH_8B; + huart5.Init.StopBits = UART_STOPBITS_1; + huart5.Init.Parity = UART_PARITY_NONE; + huart5.Init.Mode = UART_MODE_TX_RX; + huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart5.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart5) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN UART5_Init 2 */ + + /* USER CODE END UART5_Init 2 */ + +} +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} +/* USART2 init function */ + +void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(uartHandle->Instance==UART4) + { + /* USER CODE BEGIN UART4_MspInit 0 */ + + /* USER CODE END UART4_MspInit 0 */ + /* UART4 clock enable */ + __HAL_RCC_UART4_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**UART4 GPIO Configuration + PA0-WKUP ------> UART4_TX + PA1 ------> UART4_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART4; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* UART4 DMA Init */ + /* UART4_RX Init */ + hdma_uart4_rx.Instance = DMA1_Stream2; + hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; + hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_uart4_rx.Init.Mode = DMA_CIRCULAR; + hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); + + /* UART4_TX Init */ + hdma_uart4_tx.Instance = DMA1_Stream4; + hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; + hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_uart4_tx.Init.Mode = DMA_CIRCULAR; + hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); + + /* UART4 interrupt Init */ + HAL_NVIC_SetPriority(UART4_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(UART4_IRQn); + /* USER CODE BEGIN UART4_MspInit 1 */ + + /* USER CODE END UART4_MspInit 1 */ + } + else if(uartHandle->Instance==UART5) + { + /* USER CODE BEGIN UART5_MspInit 0 */ + + /* USER CODE END UART5_MspInit 0 */ + /* UART5 clock enable */ + __HAL_RCC_UART5_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART5; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART5; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* UART5 DMA Init */ + /* UART5_RX Init */ + hdma_uart5_rx.Instance = DMA1_Stream0; + hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; + hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_uart5_rx.Init.Mode = DMA_CIRCULAR; + hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); + + /* UART5_TX Init */ + hdma_uart5_tx.Instance = DMA1_Stream7; + hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; + hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_uart5_tx.Init.Mode = DMA_CIRCULAR; + hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); + + /* UART5 interrupt Init */ + HAL_NVIC_SetPriority(UART5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(UART5_IRQn); + /* USER CODE BEGIN UART5_MspInit 1 */ + + /* USER CODE END UART5_MspInit 1 */ + } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART1 DMA Init */ + /* USART1_RX Init */ + hdma_usart1_rx.Instance = DMA2_Stream2; + hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; + hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart1_rx.Init.Mode = DMA_CIRCULAR; + hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); + + /* USART1_TX Init */ + hdma_usart1_tx.Instance = DMA2_Stream7; + hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; + hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart1_tx.Init.Mode = DMA_CIRCULAR; + hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); + + /* USART1 interrupt Init */ + HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* USART2 clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART2 DMA Init */ + /* USART2_RX Init */ + hdma_usart2_rx.Instance = DMA1_Stream5; + hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; + hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_rx.Init.Mode = DMA_CIRCULAR; + hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); + + /* USART2_TX Init */ + hdma_usart2_tx.Instance = DMA1_Stream6; + hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; + hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_tx.Init.Mode = DMA_CIRCULAR; + hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); + + /* USART2 interrupt Init */ + HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + + if(uartHandle->Instance==UART4) + { + /* USER CODE BEGIN UART4_MspDeInit 0 */ + + /* USER CODE END UART4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_UART4_CLK_DISABLE(); + + /**UART4 GPIO Configuration + PA0-WKUP ------> UART4_TX + PA1 ------> UART4_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1); + + /* UART4 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + HAL_DMA_DeInit(uartHandle->hdmatx); + + /* UART4 interrupt Deinit */ + HAL_NVIC_DisableIRQ(UART4_IRQn); + /* USER CODE BEGIN UART4_MspDeInit 1 */ + + /* USER CODE END UART4_MspDeInit 1 */ + } + else if(uartHandle->Instance==UART5) + { + /* USER CODE BEGIN UART5_MspDeInit 0 */ + + /* USER CODE END UART5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_UART5_CLK_DISABLE(); + + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* UART5 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + HAL_DMA_DeInit(uartHandle->hdmatx); + + /* UART5 interrupt Deinit */ + HAL_NVIC_DisableIRQ(UART5_IRQn); + /* USER CODE BEGIN UART5_MspDeInit 1 */ + + /* USER CODE END UART5_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USART1 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + HAL_DMA_DeInit(uartHandle->hdmatx); + + /* USART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USART2 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + HAL_DMA_DeInit(uartHandle->hdmatx); + + /* USART2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/firmware/numpad/Core/Src/dma.c b/firmware/numpad/Core/Src/dma.c new file mode 100644 index 00000000..ea28d29a --- /dev/null +++ b/firmware/numpad/Core/Src/dma.c @@ -0,0 +1,77 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure DMA */ +/*----------------------------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + __HAL_RCC_DMA2_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Stream0_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); + /* DMA1_Stream2_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); + /* DMA1_Stream4_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); + /* DMA1_Stream5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); + /* DMA1_Stream6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); + /* DMA1_Stream7_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); + /* DMA2_Stream2_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); + /* DMA2_Stream7_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + diff --git a/firmware/numpad/Core/Src/gpio.c b/firmware/numpad/Core/Src/gpio.c new file mode 100644 index 00000000..1ac25202 --- /dev/null +++ b/firmware/numpad/Core/Src/gpio.c @@ -0,0 +1,90 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); + + /*Configure GPIO pins : PC4 PC5 */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pin : PA8 */ + GPIO_InitStruct.Pin = GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/firmware/numpad/Core/Src/hid_queue.c b/firmware/numpad/Core/Src/hid_queue.c new file mode 100644 index 00000000..4662ee2b --- /dev/null +++ b/firmware/numpad/Core/Src/hid_queue.c @@ -0,0 +1,55 @@ +#include "hid_queue.h" + +bool hid_queue_init(HIDQueue *q, HIDReport *buffer, uint16_t capacity) { + if (!q || !buffer || capacity == 0) return false; + + q->buffer = buffer; + q->capacity = capacity; + q->head = 0; + q->tail = 0; + q->count = 0; + + return true; +} + +void hid_queue_reset(HIDQueue *q) { + if (!q) return; + q->head = 0; + q->tail = 0; + q->count = 0; +} + +bool hid_queue_is_empty(HIDQueue *q) { + return q->count == 0; +} + +bool hid_queue_is_full(HIDQueue *q) { + return q->count == q->capacity; +} + +bool hid_queue_push(HIDQueue *q, HIDReport item) { + if (hid_queue_is_full(q)) { + return false; // Queue full (no more shelves for potions!) (；ω；) + } + + q->buffer[q->tail] = item; + q->tail = (q->tail + 1) % q->capacity; + q->count++; + + return true; +} + +bool hid_queue_pop(HIDQueue *q, HIDReport *out) { + if (hid_queue_is_empty(q)) { + return false; // Nothing to dequeue + } + + if (out) { + *out = q->buffer[q->head]; + } + + q->head = (q->head + 1) % q->capacity; + q->count--; + + return true; +} diff --git a/firmware/numpad/Core/Src/i2c.c b/firmware/numpad/Core/Src/i2c.c new file mode 100644 index 00000000..1bcb7ec1 --- /dev/null +++ b/firmware/numpad/Core/Src/i2c.c @@ -0,0 +1,116 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.c + * @brief This file provides code for the configuration + * of the I2C instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "i2c.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +I2C_HandleTypeDef hi2c1; + +/* I2C1 init function */ +void MX_I2C1_Init(void) +{ + + /* USER CODE BEGIN I2C1_Init 0 */ + + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + hi2c1.Init.ClockSpeed = 100000; + hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; + hi2c1.Init.OwnAddress1 = 0; + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c1.Init.OwnAddress2 = 0; + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + +void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* I2C1 clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } +} + +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) +{ + + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7); + + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/firmware/modularkbd/Core/Src/main.c b/firmware/numpad/Core/Src/main.c similarity index 100% rename from firmware/modularkbd/Core/Src/main.c rename to firmware/numpad/Core/Src/main.c diff --git a/firmware/numpad/Core/Src/stm32f4xx_hal_msp.c b/firmware/numpad/Core/Src/stm32f4xx_hal_msp.c new file mode 100644 index 00000000..00c02c33 --- /dev/null +++ b/firmware/numpad/Core/Src/stm32f4xx_hal_msp.c @@ -0,0 +1,82 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/firmware/numpad/Core/Src/stm32f4xx_it.c b/firmware/numpad/Core/Src/stm32f4xx_it.c new file mode 100644 index 00000000..4b0a65d4 --- /dev/null +++ b/firmware/numpad/Core/Src/stm32f4xx_it.c @@ -0,0 +1,397 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern PCD_HandleTypeDef hpcd_USB_OTG_FS; +extern DMA_HandleTypeDef hdma_uart4_rx; +extern DMA_HandleTypeDef hdma_uart4_tx; +extern DMA_HandleTypeDef hdma_uart5_rx; +extern DMA_HandleTypeDef hdma_uart5_tx; +extern DMA_HandleTypeDef hdma_usart1_rx; +extern DMA_HandleTypeDef hdma_usart1_tx; +extern DMA_HandleTypeDef hdma_usart2_rx; +extern DMA_HandleTypeDef hdma_usart2_tx; +extern UART_HandleTypeDef huart4; +extern UART_HandleTypeDef huart5; +extern UART_HandleTypeDef huart1; +extern UART_HandleTypeDef huart2; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles DMA1 stream0 global interrupt. + */ +void DMA1_Stream0_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ + + /* USER CODE END DMA1_Stream0_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart5_rx); + /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ + + /* USER CODE END DMA1_Stream0_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream2 global interrupt. + */ +void DMA1_Stream2_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ + + /* USER CODE END DMA1_Stream2_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart4_rx); + /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ + + /* USER CODE END DMA1_Stream2_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream4 global interrupt. + */ +void DMA1_Stream4_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ + + /* USER CODE END DMA1_Stream4_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart4_tx); + /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ + + /* USER CODE END DMA1_Stream4_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream5 global interrupt. + */ +void DMA1_Stream5_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ + + /* USER CODE END DMA1_Stream5_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_rx); + /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ + + /* USER CODE END DMA1_Stream5_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream6 global interrupt. + */ +void DMA1_Stream6_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ + + /* USER CODE END DMA1_Stream6_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_tx); + /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ + + /* USER CODE END DMA1_Stream6_IRQn 1 */ +} + +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + +/** + * @brief This function handles USART2 global interrupt. + */ +void USART2_IRQHandler(void) +{ + /* USER CODE BEGIN USART2_IRQn 0 */ + + /* USER CODE END USART2_IRQn 0 */ + HAL_UART_IRQHandler(&huart2); + /* USER CODE BEGIN USART2_IRQn 1 */ + + /* USER CODE END USART2_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream7 global interrupt. + */ +void DMA1_Stream7_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ + + /* USER CODE END DMA1_Stream7_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_uart5_tx); + /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ + + /* USER CODE END DMA1_Stream7_IRQn 1 */ +} + +/** + * @brief This function handles UART4 global interrupt. + */ +void UART4_IRQHandler(void) +{ + /* USER CODE BEGIN UART4_IRQn 0 */ + + /* USER CODE END UART4_IRQn 0 */ + HAL_UART_IRQHandler(&huart4); + /* USER CODE BEGIN UART4_IRQn 1 */ + + /* USER CODE END UART4_IRQn 1 */ +} + +/** + * @brief This function handles UART5 global interrupt. + */ +void UART5_IRQHandler(void) +{ + /* USER CODE BEGIN UART5_IRQn 0 */ + + /* USER CODE END UART5_IRQn 0 */ + HAL_UART_IRQHandler(&huart5); + /* USER CODE BEGIN UART5_IRQn 1 */ + + /* USER CODE END UART5_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream2 global interrupt. + */ +void DMA2_Stream2_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ + + /* USER CODE END DMA2_Stream2_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart1_rx); + /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ + + /* USER CODE END DMA2_Stream2_IRQn 1 */ +} + +/** + * @brief This function handles USB On The Go FS global interrupt. + */ +void OTG_FS_IRQHandler(void) +{ + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); + /* USER CODE BEGIN OTG_FS_IRQn 1 */ + + /* USER CODE END OTG_FS_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream7 global interrupt. + */ +void DMA2_Stream7_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ + + /* USER CODE END DMA2_Stream7_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart1_tx); + /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ + + /* USER CODE END DMA2_Stream7_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/firmware/numpad/Core/Src/syscalls.c b/firmware/numpad/Core/Src/syscalls.c new file mode 100644 index 00000000..8884b5aa --- /dev/null +++ b/firmware/numpad/Core/Src/syscalls.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/firmware/numpad/Core/Src/sysmem.c b/firmware/numpad/Core/Src/sysmem.c new file mode 100644 index 00000000..5d9f7e67 --- /dev/null +++ b/firmware/numpad/Core/Src/sysmem.c @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/firmware/numpad/Core/Src/system_stm32f4xx.c b/firmware/numpad/Core/Src/system_stm32f4xx.c new file mode 100644 index 00000000..7a61e9cf --- /dev/null +++ b/firmware/numpad/Core/Src/system_stm32f4xx.c @@ -0,0 +1,747 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp, pllvco, pllp, pllsource, pllm; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/firmware/numpad/Core/Src/tim.c b/firmware/numpad/Core/Src/tim.c new file mode 100644 index 00000000..62b4ea70 --- /dev/null +++ b/firmware/numpad/Core/Src/tim.c @@ -0,0 +1,233 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim3; + +/* TIM2 init function */ +void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 4294967295; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_OC_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + HAL_TIM_MspPostInit(&htim2); + +} +/* TIM3 init function */ +void MX_TIM3_Init(void) +{ + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + htim3.Init.Prescaler = 0; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.Period = 65535; + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + sConfig.EncoderMode = TIM_ENCODERMODE_TI1; + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + sConfig.IC1Filter = 0; + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + sConfig.IC2Filter = 0; + if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + +} + +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle) +{ + + if(tim_ocHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* TIM2 clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } +} + +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(tim_encoderHandle->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* TIM3 clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM3 GPIO Configuration + PA6 ------> TIM3_CH1 + PA7 ------> TIM3_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } +} +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(timHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspPostInit 0 */ + + /* USER CODE END TIM2_MspPostInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM2 GPIO Configuration + PA5 ------> TIM2_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM2_MspPostInit 1 */ + + /* USER CODE END TIM2_MspPostInit 1 */ + } + +} + +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef* tim_ocHandle) +{ + + if(tim_ocHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } +} + +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* tim_encoderHandle) +{ + + if(tim_encoderHandle->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + + /**TIM3 GPIO Configuration + PA6 ------> TIM3_CH1 + PA7 ------> TIM3_CH2 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6|GPIO_PIN_7); + + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/firmware/numpad/Core/Src/usart.c b/firmware/numpad/Core/Src/usart.c new file mode 100644 index 00000000..ad15fee2 --- /dev/null +++ b/firmware/numpad/Core/Src/usart.c @@ -0,0 +1,530 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +UART_HandleTypeDef huart4; +UART_HandleTypeDef huart5; +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart2; +DMA_HandleTypeDef hdma_uart4_rx; +DMA_HandleTypeDef hdma_uart4_tx; +DMA_HandleTypeDef hdma_uart5_rx; +DMA_HandleTypeDef hdma_uart5_tx; +DMA_HandleTypeDef hdma_usart1_rx; +DMA_HandleTypeDef hdma_usart1_tx; +DMA_HandleTypeDef hdma_usart2_rx; +DMA_HandleTypeDef hdma_usart2_tx; + +/* UART4 init function */ +void MX_UART4_Init(void) +{ + + /* USER CODE BEGIN UART4_Init 0 */ + + /* USER CODE END UART4_Init 0 */ + + /* USER CODE BEGIN UART4_Init 1 */ + + /* USER CODE END UART4_Init 1 */ + huart4.Instance = UART4; + huart4.Init.BaudRate = 115200; + huart4.Init.WordLength = UART_WORDLENGTH_8B; + huart4.Init.StopBits = UART_STOPBITS_1; + huart4.Init.Parity = UART_PARITY_NONE; + huart4.Init.Mode = UART_MODE_TX_RX; + huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart4.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN UART4_Init 2 */ + + /* USER CODE END UART4_Init 2 */ + +} +/* UART5 init function */ +void MX_UART5_Init(void) +{ + + /* USER CODE BEGIN UART5_Init 0 */ + + /* USER CODE END UART5_Init 0 */ + + /* USER CODE BEGIN UART5_Init 1 */ + + /* USER CODE END UART5_Init 1 */ + huart5.Instance = UART5; + huart5.Init.BaudRate = 115200; + huart5.Init.WordLength = UART_WORDLENGTH_8B; + huart5.Init.StopBits = UART_STOPBITS_1; + huart5.Init.Parity = UART_PARITY_NONE; + huart5.Init.Mode = UART_MODE_TX_RX; + huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart5.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart5) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN UART5_Init 2 */ + + /* USER CODE END UART5_Init 2 */ + +} +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} +/* USART2 init function */ + +void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(uartHandle->Instance==UART4) + { + /* USER CODE BEGIN UART4_MspInit 0 */ + + /* USER CODE END UART4_MspInit 0 */ + /* UART4 clock enable */ + __HAL_RCC_UART4_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**UART4 GPIO Configuration + PA0-WKUP ------> UART4_TX + PA1 ------> UART4_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART4; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* UART4 DMA Init */ + /* UART4_RX Init */ + hdma_uart4_rx.Instance = DMA1_Stream2; + hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; + hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_uart4_rx.Init.Mode = DMA_NORMAL; + hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); + + /* UART4_TX Init */ + hdma_uart4_tx.Instance = DMA1_Stream4; + hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; + hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_uart4_tx.Init.Mode = DMA_NORMAL; + hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); + + /* UART4 interrupt Init */ + HAL_NVIC_SetPriority(UART4_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(UART4_IRQn); + /* USER CODE BEGIN UART4_MspInit 1 */ + + /* USER CODE END UART4_MspInit 1 */ + } + else if(uartHandle->Instance==UART5) + { + /* USER CODE BEGIN UART5_MspInit 0 */ + + /* USER CODE END UART5_MspInit 0 */ + /* UART5 clock enable */ + __HAL_RCC_UART5_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART5; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART5; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* UART5 DMA Init */ + /* UART5_RX Init */ + hdma_uart5_rx.Instance = DMA1_Stream0; + hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; + hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_uart5_rx.Init.Mode = DMA_NORMAL; + hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); + + /* UART5_TX Init */ + hdma_uart5_tx.Instance = DMA1_Stream7; + hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; + hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_uart5_tx.Init.Mode = DMA_NORMAL; + hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); + + /* UART5 interrupt Init */ + HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(UART5_IRQn); + /* USER CODE BEGIN UART5_MspInit 1 */ + + /* USER CODE END UART5_MspInit 1 */ + } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART1 DMA Init */ + /* USART1_RX Init */ + hdma_usart1_rx.Instance = DMA2_Stream2; + hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; + hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart1_rx.Init.Mode = DMA_NORMAL; + hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); + + /* USART1_TX Init */ + hdma_usart1_tx.Instance = DMA2_Stream7; + hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; + hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart1_tx.Init.Mode = DMA_NORMAL; + hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); + + /* USART1 interrupt Init */ + HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* USART2 clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART2 DMA Init */ + /* USART2_RX Init */ + hdma_usart2_rx.Instance = DMA1_Stream5; + hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; + hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_rx.Init.Mode = DMA_NORMAL; + hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); + + /* USART2_TX Init */ + hdma_usart2_tx.Instance = DMA1_Stream6; + hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; + hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_tx.Init.Mode = DMA_NORMAL; + hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); + + /* USART2 interrupt Init */ + HAL_NVIC_SetPriority(USART2_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + + if(uartHandle->Instance==UART4) + { + /* USER CODE BEGIN UART4_MspDeInit 0 */ + + /* USER CODE END UART4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_UART4_CLK_DISABLE(); + + /**UART4 GPIO Configuration + PA0-WKUP ------> UART4_TX + PA1 ------> UART4_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1); + + /* UART4 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + HAL_DMA_DeInit(uartHandle->hdmatx); + + /* UART4 interrupt Deinit */ + HAL_NVIC_DisableIRQ(UART4_IRQn); + /* USER CODE BEGIN UART4_MspDeInit 1 */ + + /* USER CODE END UART4_MspDeInit 1 */ + } + else if(uartHandle->Instance==UART5) + { + /* USER CODE BEGIN UART5_MspDeInit 0 */ + + /* USER CODE END UART5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_UART5_CLK_DISABLE(); + + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* UART5 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + HAL_DMA_DeInit(uartHandle->hdmatx); + + /* UART5 interrupt Deinit */ + HAL_NVIC_DisableIRQ(UART5_IRQn); + /* USER CODE BEGIN UART5_MspDeInit 1 */ + + /* USER CODE END UART5_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USART1 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + HAL_DMA_DeInit(uartHandle->hdmatx); + + /* USART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USART2 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + HAL_DMA_DeInit(uartHandle->hdmatx); + + /* USART2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/firmware/numpad/Core/Startup/startup_stm32f446retx.s b/firmware/numpad/Core/Startup/startup_stm32f446retx.s new file mode 100644 index 00000000..7040eafa --- /dev/null +++ b/firmware/numpad/Core/Startup/startup_stm32f446retx.s @@ -0,0 +1,538 @@ +/** + ****************************************************************************** + * @file startup_stm32f446xx.s + * @author MCD Application Team + * @brief STM32F446xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SAI1_IRQHandler /* SAI1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QuadSPI */ + .word CEC_IRQHandler /* CEC */ + .word SPDIF_RX_IRQHandler /* SPDIF RX */ + .word FMPI2C1_EV_IRQHandler /* FMPI2C 1 Event */ + .word FMPI2C1_ER_IRQHandler /* FMPI2C 1 Error */ + + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak FMPI2C1_EV_IRQHandler + .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler + + .weak FMPI2C1_ER_IRQHandler + .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler diff --git a/firmware/numpad/Debug/Core/Src/dma.cyclo b/firmware/numpad/Debug/Core/Src/dma.cyclo new file mode 100644 index 00000000..a9d9f425 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/dma.cyclo @@ -0,0 +1 @@ +../Core/Src/dma.c:39:6:MX_DMA_Init 1 diff --git a/firmware/numpad/Debug/Core/Src/dma.d b/firmware/numpad/Debug/Core/Src/dma.d new file mode 100644 index 00000000..872d4dbe --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/dma.d @@ -0,0 +1,69 @@ +Core/Src/dma.o: ../Core/Src/dma.c ../Core/Inc/dma.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Core/Inc/dma.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/modularkbd/Debug/Core/Src/dma.o b/firmware/numpad/Debug/Core/Src/dma.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/dma.o rename to firmware/numpad/Debug/Core/Src/dma.o diff --git a/firmware/numpad/Debug/Core/Src/dma.su b/firmware/numpad/Debug/Core/Src/dma.su new file mode 100644 index 00000000..802020b1 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/dma.su @@ -0,0 +1 @@ +../Core/Src/dma.c:39:6:MX_DMA_Init 16 static diff --git a/firmware/numpad/Debug/Core/Src/gpio.cyclo b/firmware/numpad/Debug/Core/Src/gpio.cyclo new file mode 100644 index 00000000..56b69583 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/gpio.cyclo @@ -0,0 +1 @@ +../Core/Src/gpio.c:42:6:MX_GPIO_Init 1 diff --git a/firmware/numpad/Debug/Core/Src/gpio.d b/firmware/numpad/Debug/Core/Src/gpio.d new file mode 100644 index 00000000..718c3608 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/gpio.d @@ -0,0 +1,69 @@ +Core/Src/gpio.o: ../Core/Src/gpio.c ../Core/Inc/gpio.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Core/Inc/gpio.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/modularkbd/Debug/Core/Src/gpio.o b/firmware/numpad/Debug/Core/Src/gpio.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/gpio.o rename to firmware/numpad/Debug/Core/Src/gpio.o diff --git a/firmware/numpad/Debug/Core/Src/gpio.su b/firmware/numpad/Debug/Core/Src/gpio.su new file mode 100644 index 00000000..87b765ef --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/gpio.su @@ -0,0 +1 @@ +../Core/Src/gpio.c:42:6:MX_GPIO_Init 48 static diff --git a/firmware/numpad/Debug/Core/Src/hid_queue.cyclo b/firmware/numpad/Debug/Core/Src/hid_queue.cyclo new file mode 100644 index 00000000..201ff0ba --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/hid_queue.cyclo @@ -0,0 +1,6 @@ +../Core/Src/hid_queue.c:3:6:hid_queue_init 4 +../Core/Src/hid_queue.c:15:6:hid_queue_reset 2 +../Core/Src/hid_queue.c:22:6:hid_queue_is_empty 1 +../Core/Src/hid_queue.c:26:6:hid_queue_is_full 1 +../Core/Src/hid_queue.c:30:6:hid_queue_push 2 +../Core/Src/hid_queue.c:42:6:hid_queue_pop 3 diff --git a/firmware/numpad/Debug/Core/Src/hid_queue.d b/firmware/numpad/Debug/Core/Src/hid_queue.d new file mode 100644 index 00000000..115dc54f --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/hid_queue.d @@ -0,0 +1,2 @@ +Core/Src/hid_queue.o: ../Core/Src/hid_queue.c ../Core/Inc/hid_queue.h +../Core/Inc/hid_queue.h: diff --git a/firmware/modularkbd/Debug/Core/Src/hid_queue.o b/firmware/numpad/Debug/Core/Src/hid_queue.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/hid_queue.o rename to firmware/numpad/Debug/Core/Src/hid_queue.o diff --git a/firmware/numpad/Debug/Core/Src/hid_queue.su b/firmware/numpad/Debug/Core/Src/hid_queue.su new file mode 100644 index 00000000..f204f562 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/hid_queue.su @@ -0,0 +1,6 @@ +../Core/Src/hid_queue.c:3:6:hid_queue_init 24 static +../Core/Src/hid_queue.c:15:6:hid_queue_reset 16 static +../Core/Src/hid_queue.c:22:6:hid_queue_is_empty 16 static +../Core/Src/hid_queue.c:26:6:hid_queue_is_full 16 static +../Core/Src/hid_queue.c:30:6:hid_queue_push 24 static +../Core/Src/hid_queue.c:42:6:hid_queue_pop 24 static diff --git a/firmware/numpad/Debug/Core/Src/i2c.cyclo b/firmware/numpad/Debug/Core/Src/i2c.cyclo new file mode 100644 index 00000000..7acaf9e1 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/i2c.cyclo @@ -0,0 +1,3 @@ +../Core/Src/i2c.c:30:6:MX_I2C1_Init 2 +../Core/Src/i2c.c:59:6:HAL_I2C_MspInit 2 +../Core/Src/i2c.c:89:6:HAL_I2C_MspDeInit 2 diff --git a/firmware/numpad/Debug/Core/Src/i2c.d b/firmware/numpad/Debug/Core/Src/i2c.d new file mode 100644 index 00000000..fc14089f --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/i2c.d @@ -0,0 +1,69 @@ +Core/Src/i2c.o: ../Core/Src/i2c.c ../Core/Inc/i2c.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Core/Inc/i2c.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/modularkbd/Debug/Core/Src/i2c.o b/firmware/numpad/Debug/Core/Src/i2c.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/i2c.o rename to firmware/numpad/Debug/Core/Src/i2c.o diff --git a/firmware/numpad/Debug/Core/Src/i2c.su b/firmware/numpad/Debug/Core/Src/i2c.su new file mode 100644 index 00000000..638b0578 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/i2c.su @@ -0,0 +1,3 @@ +../Core/Src/i2c.c:30:6:MX_I2C1_Init 8 static +../Core/Src/i2c.c:59:6:HAL_I2C_MspInit 48 static +../Core/Src/i2c.c:89:6:HAL_I2C_MspDeInit 16 static diff --git a/firmware/modularkbd/Debug/Core/Src/main.cyclo b/firmware/numpad/Debug/Core/Src/main.cyclo similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/main.cyclo rename to firmware/numpad/Debug/Core/Src/main.cyclo diff --git a/firmware/modularkbd/Debug/Core/Src/main.d b/firmware/numpad/Debug/Core/Src/main.d similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/main.d rename to firmware/numpad/Debug/Core/Src/main.d diff --git a/firmware/modularkbd/Debug/Core/Src/main.o b/firmware/numpad/Debug/Core/Src/main.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/main.o rename to firmware/numpad/Debug/Core/Src/main.o diff --git a/firmware/modularkbd/Debug/Core/Src/main.su b/firmware/numpad/Debug/Core/Src/main.su similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/main.su rename to firmware/numpad/Debug/Core/Src/main.su diff --git a/firmware/numpad/Debug/Core/Src/stm32f4xx_hal_msp.cyclo b/firmware/numpad/Debug/Core/Src/stm32f4xx_hal_msp.cyclo new file mode 100644 index 00000000..ae31cf96 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/stm32f4xx_hal_msp.cyclo @@ -0,0 +1 @@ +../Core/Src/stm32f4xx_hal_msp.c:63:6:HAL_MspInit 1 diff --git a/firmware/numpad/Debug/Core/Src/stm32f4xx_hal_msp.d b/firmware/numpad/Debug/Core/Src/stm32f4xx_hal_msp.d new file mode 100644 index 00000000..4b18fd24 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/stm32f4xx_hal_msp.d @@ -0,0 +1,68 @@ +Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/modularkbd/Debug/Core/Src/stm32f4xx_hal_msp.o b/firmware/numpad/Debug/Core/Src/stm32f4xx_hal_msp.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/stm32f4xx_hal_msp.o rename to firmware/numpad/Debug/Core/Src/stm32f4xx_hal_msp.o diff --git a/firmware/numpad/Debug/Core/Src/stm32f4xx_hal_msp.su b/firmware/numpad/Debug/Core/Src/stm32f4xx_hal_msp.su new file mode 100644 index 00000000..dbeb228c --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/stm32f4xx_hal_msp.su @@ -0,0 +1 @@ +../Core/Src/stm32f4xx_hal_msp.c:63:6:HAL_MspInit 16 static diff --git a/firmware/numpad/Debug/Core/Src/stm32f4xx_it.cyclo b/firmware/numpad/Debug/Core/Src/stm32f4xx_it.cyclo new file mode 100644 index 00000000..a5859a1a --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/stm32f4xx_it.cyclo @@ -0,0 +1,22 @@ +../Core/Src/stm32f4xx_it.c:81:6:NMI_Handler 1 +../Core/Src/stm32f4xx_it.c:96:6:HardFault_Handler 1 +../Core/Src/stm32f4xx_it.c:111:6:MemManage_Handler 1 +../Core/Src/stm32f4xx_it.c:126:6:BusFault_Handler 1 +../Core/Src/stm32f4xx_it.c:141:6:UsageFault_Handler 1 +../Core/Src/stm32f4xx_it.c:156:6:SVC_Handler 1 +../Core/Src/stm32f4xx_it.c:169:6:DebugMon_Handler 1 +../Core/Src/stm32f4xx_it.c:182:6:PendSV_Handler 1 +../Core/Src/stm32f4xx_it.c:195:6:SysTick_Handler 1 +../Core/Src/stm32f4xx_it.c:216:6:DMA1_Stream0_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:230:6:DMA1_Stream2_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:244:6:DMA1_Stream4_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:258:6:DMA1_Stream5_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:272:6:DMA1_Stream6_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:286:6:USART1_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:300:6:USART2_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:314:6:DMA1_Stream7_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:328:6:UART4_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:342:6:UART5_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:356:6:DMA2_Stream2_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:370:6:OTG_FS_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:384:6:DMA2_Stream7_IRQHandler 1 diff --git a/firmware/numpad/Debug/Core/Src/stm32f4xx_it.d b/firmware/numpad/Debug/Core/Src/stm32f4xx_it.d new file mode 100644 index 00000000..37eb467d --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/stm32f4xx_it.d @@ -0,0 +1,70 @@ +Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Core/Inc/stm32f4xx_it.h +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Core/Inc/stm32f4xx_it.h: diff --git a/firmware/modularkbd/Debug/Core/Src/stm32f4xx_it.o b/firmware/numpad/Debug/Core/Src/stm32f4xx_it.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/stm32f4xx_it.o rename to firmware/numpad/Debug/Core/Src/stm32f4xx_it.o diff --git a/firmware/numpad/Debug/Core/Src/stm32f4xx_it.su b/firmware/numpad/Debug/Core/Src/stm32f4xx_it.su new file mode 100644 index 00000000..2f984562 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/stm32f4xx_it.su @@ -0,0 +1,22 @@ +../Core/Src/stm32f4xx_it.c:81:6:NMI_Handler 4 static +../Core/Src/stm32f4xx_it.c:96:6:HardFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:111:6:MemManage_Handler 4 static +../Core/Src/stm32f4xx_it.c:126:6:BusFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:141:6:UsageFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:156:6:SVC_Handler 4 static +../Core/Src/stm32f4xx_it.c:169:6:DebugMon_Handler 4 static +../Core/Src/stm32f4xx_it.c:182:6:PendSV_Handler 4 static +../Core/Src/stm32f4xx_it.c:195:6:SysTick_Handler 8 static +../Core/Src/stm32f4xx_it.c:216:6:DMA1_Stream0_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:230:6:DMA1_Stream2_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:244:6:DMA1_Stream4_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:258:6:DMA1_Stream5_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:272:6:DMA1_Stream6_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:286:6:USART1_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:300:6:USART2_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:314:6:DMA1_Stream7_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:328:6:UART4_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:342:6:UART5_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:356:6:DMA2_Stream2_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:370:6:OTG_FS_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:384:6:DMA2_Stream7_IRQHandler 8 static diff --git a/firmware/modularkbd/Debug/Core/Src/subdir.mk b/firmware/numpad/Debug/Core/Src/subdir.mk similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/subdir.mk rename to firmware/numpad/Debug/Core/Src/subdir.mk diff --git a/firmware/numpad/Debug/Core/Src/syscalls.cyclo b/firmware/numpad/Debug/Core/Src/syscalls.cyclo new file mode 100644 index 00000000..6cbfdd05 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/syscalls.cyclo @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1 +../Core/Src/syscalls.c:48:5:_getpid 1 +../Core/Src/syscalls.c:53:5:_kill 1 +../Core/Src/syscalls.c:61:6:_exit 1 +../Core/Src/syscalls.c:67:27:_read 2 +../Core/Src/syscalls.c:80:27:_write 2 +../Core/Src/syscalls.c:92:5:_close 1 +../Core/Src/syscalls.c:99:5:_fstat 1 +../Core/Src/syscalls.c:106:5:_isatty 1 +../Core/Src/syscalls.c:112:5:_lseek 1 +../Core/Src/syscalls.c:120:5:_open 1 +../Core/Src/syscalls.c:128:5:_wait 1 +../Core/Src/syscalls.c:135:5:_unlink 1 +../Core/Src/syscalls.c:142:5:_times 1 +../Core/Src/syscalls.c:148:5:_stat 1 +../Core/Src/syscalls.c:155:5:_link 1 +../Core/Src/syscalls.c:163:5:_fork 1 +../Core/Src/syscalls.c:169:5:_execve 1 diff --git a/firmware/numpad/Debug/Core/Src/syscalls.d b/firmware/numpad/Debug/Core/Src/syscalls.d new file mode 100644 index 00000000..8667c708 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/syscalls.d @@ -0,0 +1 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c diff --git a/firmware/modularkbd/Debug/Core/Src/syscalls.o b/firmware/numpad/Debug/Core/Src/syscalls.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/syscalls.o rename to firmware/numpad/Debug/Core/Src/syscalls.o diff --git a/firmware/numpad/Debug/Core/Src/syscalls.su b/firmware/numpad/Debug/Core/Src/syscalls.su new file mode 100644 index 00000000..50b547ab --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 4 static +../Core/Src/syscalls.c:48:5:_getpid 4 static +../Core/Src/syscalls.c:53:5:_kill 16 static +../Core/Src/syscalls.c:61:6:_exit 16 static +../Core/Src/syscalls.c:67:27:_read 32 static +../Core/Src/syscalls.c:80:27:_write 32 static +../Core/Src/syscalls.c:92:5:_close 16 static +../Core/Src/syscalls.c:99:5:_fstat 16 static +../Core/Src/syscalls.c:106:5:_isatty 16 static +../Core/Src/syscalls.c:112:5:_lseek 24 static +../Core/Src/syscalls.c:120:5:_open 12 static +../Core/Src/syscalls.c:128:5:_wait 16 static +../Core/Src/syscalls.c:135:5:_unlink 16 static +../Core/Src/syscalls.c:142:5:_times 16 static +../Core/Src/syscalls.c:148:5:_stat 16 static +../Core/Src/syscalls.c:155:5:_link 16 static +../Core/Src/syscalls.c:163:5:_fork 8 static +../Core/Src/syscalls.c:169:5:_execve 24 static diff --git a/firmware/numpad/Debug/Core/Src/sysmem.cyclo b/firmware/numpad/Debug/Core/Src/sysmem.cyclo new file mode 100644 index 00000000..0090c10f --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/sysmem.cyclo @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 3 diff --git a/firmware/numpad/Debug/Core/Src/sysmem.d b/firmware/numpad/Debug/Core/Src/sysmem.d new file mode 100644 index 00000000..74fecf9b --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/sysmem.d @@ -0,0 +1 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c diff --git a/firmware/modularkbd/Debug/Core/Src/sysmem.o b/firmware/numpad/Debug/Core/Src/sysmem.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/sysmem.o rename to firmware/numpad/Debug/Core/Src/sysmem.o diff --git a/firmware/numpad/Debug/Core/Src/sysmem.su b/firmware/numpad/Debug/Core/Src/sysmem.su new file mode 100644 index 00000000..12d5f177 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 32 static diff --git a/firmware/numpad/Debug/Core/Src/system_stm32f4xx.cyclo b/firmware/numpad/Debug/Core/Src/system_stm32f4xx.cyclo new file mode 100644 index 00000000..4cc0df91 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/system_stm32f4xx.cyclo @@ -0,0 +1,2 @@ +../Core/Src/system_stm32f4xx.c:167:6:SystemInit 1 +../Core/Src/system_stm32f4xx.c:220:6:SystemCoreClockUpdate 6 diff --git a/firmware/numpad/Debug/Core/Src/system_stm32f4xx.d b/firmware/numpad/Debug/Core/Src/system_stm32f4xx.d new file mode 100644 index 00000000..8e525e44 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/system_stm32f4xx.d @@ -0,0 +1,67 @@ +Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/modularkbd/Debug/Core/Src/system_stm32f4xx.o b/firmware/numpad/Debug/Core/Src/system_stm32f4xx.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/system_stm32f4xx.o rename to firmware/numpad/Debug/Core/Src/system_stm32f4xx.o diff --git a/firmware/numpad/Debug/Core/Src/system_stm32f4xx.su b/firmware/numpad/Debug/Core/Src/system_stm32f4xx.su new file mode 100644 index 00000000..96f1cd43 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/system_stm32f4xx.su @@ -0,0 +1,2 @@ +../Core/Src/system_stm32f4xx.c:167:6:SystemInit 4 static +../Core/Src/system_stm32f4xx.c:220:6:SystemCoreClockUpdate 32 static diff --git a/firmware/numpad/Debug/Core/Src/tim.cyclo b/firmware/numpad/Debug/Core/Src/tim.cyclo new file mode 100644 index 00000000..21b599d4 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/tim.cyclo @@ -0,0 +1,7 @@ +../Core/Src/tim.c:31:6:MX_TIM2_Init 4 +../Core/Src/tim.c:75:6:MX_TIM3_Init 3 +../Core/Src/tim.c:119:6:HAL_TIM_OC_MspInit 2 +../Core/Src/tim.c:135:6:HAL_TIM_Encoder_MspInit 2 +../Core/Src/tim.c:164:6:HAL_TIM_MspPostInit 2 +../Core/Src/tim.c:192:6:HAL_TIM_OC_MspDeInit 2 +../Core/Src/tim.c:208:6:HAL_TIM_Encoder_MspDeInit 2 diff --git a/firmware/numpad/Debug/Core/Src/tim.d b/firmware/numpad/Debug/Core/Src/tim.d new file mode 100644 index 00000000..183b1212 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/tim.d @@ -0,0 +1,69 @@ +Core/Src/tim.o: ../Core/Src/tim.c ../Core/Inc/tim.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Core/Inc/tim.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/modularkbd/Debug/Core/Src/tim.o b/firmware/numpad/Debug/Core/Src/tim.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/tim.o rename to firmware/numpad/Debug/Core/Src/tim.o diff --git a/firmware/numpad/Debug/Core/Src/tim.su b/firmware/numpad/Debug/Core/Src/tim.su new file mode 100644 index 00000000..feb2927b --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/tim.su @@ -0,0 +1,7 @@ +../Core/Src/tim.c:31:6:MX_TIM2_Init 48 static +../Core/Src/tim.c:75:6:MX_TIM3_Init 56 static +../Core/Src/tim.c:119:6:HAL_TIM_OC_MspInit 24 static +../Core/Src/tim.c:135:6:HAL_TIM_Encoder_MspInit 48 static +../Core/Src/tim.c:164:6:HAL_TIM_MspPostInit 40 static +../Core/Src/tim.c:192:6:HAL_TIM_OC_MspDeInit 16 static +../Core/Src/tim.c:208:6:HAL_TIM_Encoder_MspDeInit 16 static diff --git a/firmware/numpad/Debug/Core/Src/usart.cyclo b/firmware/numpad/Debug/Core/Src/usart.cyclo new file mode 100644 index 00000000..cd4d8707 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/usart.cyclo @@ -0,0 +1,6 @@ +../Core/Src/usart.c:41:6:MX_UART4_Init 2 +../Core/Src/usart.c:69:6:MX_UART5_Init 2 +../Core/Src/usart.c:98:6:MX_USART1_UART_Init 2 +../Core/Src/usart.c:127:6:MX_USART2_UART_Init 2 +../Core/Src/usart.c:155:6:HAL_UART_MspInit 13 +../Core/Src/usart.c:425:6:HAL_UART_MspDeInit 5 diff --git a/firmware/numpad/Debug/Core/Src/usart.d b/firmware/numpad/Debug/Core/Src/usart.d new file mode 100644 index 00000000..fa958672 --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/usart.d @@ -0,0 +1,69 @@ +Core/Src/usart.o: ../Core/Src/usart.c ../Core/Inc/usart.h \ + ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Core/Inc/usart.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/modularkbd/Debug/Core/Src/usart.o b/firmware/numpad/Debug/Core/Src/usart.o similarity index 100% rename from firmware/modularkbd/Debug/Core/Src/usart.o rename to firmware/numpad/Debug/Core/Src/usart.o diff --git a/firmware/numpad/Debug/Core/Src/usart.su b/firmware/numpad/Debug/Core/Src/usart.su new file mode 100644 index 00000000..c66d3dfc --- /dev/null +++ b/firmware/numpad/Debug/Core/Src/usart.su @@ -0,0 +1,6 @@ +../Core/Src/usart.c:41:6:MX_UART4_Init 8 static +../Core/Src/usart.c:69:6:MX_UART5_Init 8 static +../Core/Src/usart.c:98:6:MX_USART1_UART_Init 8 static +../Core/Src/usart.c:127:6:MX_USART2_UART_Init 8 static +../Core/Src/usart.c:155:6:HAL_UART_MspInit 72 static +../Core/Src/usart.c:425:6:HAL_UART_MspDeInit 16 static diff --git a/firmware/numpad/Debug/Core/Startup/startup_stm32f446retx.d b/firmware/numpad/Debug/Core/Startup/startup_stm32f446retx.d new file mode 100644 index 00000000..168e9e87 --- /dev/null +++ b/firmware/numpad/Debug/Core/Startup/startup_stm32f446retx.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32f446retx.o: \ + ../Core/Startup/startup_stm32f446retx.s diff --git a/firmware/numpad/Debug/Core/Startup/startup_stm32f446retx.o b/firmware/numpad/Debug/Core/Startup/startup_stm32f446retx.o new file mode 100644 index 00000000..3635b8e1 Binary files /dev/null and b/firmware/numpad/Debug/Core/Startup/startup_stm32f446retx.o differ diff --git a/firmware/numpad/Debug/Core/Startup/subdir.mk b/firmware/numpad/Debug/Core/Startup/subdir.mk new file mode 100644 index 00000000..8e156ed0 --- /dev/null +++ b/firmware/numpad/Debug/Core/Startup/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f446retx.s + +OBJS += \ +./Core/Startup/startup_stm32f446retx.o + +S_DEPS += \ +./Core/Startup/startup_stm32f446retx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" + +clean: clean-Core-2f-Startup + +clean-Core-2f-Startup: + -$(RM) ./Core/Startup/startup_stm32f446retx.d ./Core/Startup/startup_stm32f446retx.o + +.PHONY: clean-Core-2f-Startup + diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo new file mode 100644 index 00000000..61b1bb12 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo @@ -0,0 +1,27 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:157:19:HAL_Init 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:190:19:HAL_DeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:219:13:HAL_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:230:13:HAL_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:253:26:HAL_InitTick 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:312:13:HAL_IncTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323:17:HAL_GetTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:332:10:HAL_GetTickPrio 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:341:19:HAL_SetTickFreq 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:374:21:HAL_GetTickFreq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:390:13:HAL_Delay 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:416:13:HAL_SuspendTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:432:13:HAL_ResumeTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:442:10:HAL_GetHalVersion 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:451:10:HAL_GetREVID 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:460:10:HAL_GetDEVID 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:469:6:HAL_DBGMCU_EnableDBGSleepMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:478:6:HAL_DBGMCU_DisableDBGSleepMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:487:6:HAL_DBGMCU_EnableDBGStopMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:496:6:HAL_DBGMCU_DisableDBGStopMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:505:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:514:6:HAL_DBGMCU_DisableDBGStandbyMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:525:6:HAL_EnableCompensationCell 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:536:6:HAL_DisableCompensationCell 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:545:10:HAL_GetUIDw0 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:554:10:HAL_GetUIDw1 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:563:10:HAL_GetUIDw2 1 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d new file mode 100644 index 00000000..4c8c5b86 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o new file mode 100644 index 00000000..bf8d83f5 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su new file mode 100644 index 00000000..fb2a723a --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su @@ -0,0 +1,27 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:157:19:HAL_Init 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:190:19:HAL_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:219:13:HAL_MspInit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:230:13:HAL_MspDeInit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:253:26:HAL_InitTick 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:312:13:HAL_IncTick 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323:17:HAL_GetTick 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:332:10:HAL_GetTickPrio 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:341:19:HAL_SetTickFreq 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:374:21:HAL_GetTickFreq 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:390:13:HAL_Delay 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:416:13:HAL_SuspendTick 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:432:13:HAL_ResumeTick 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:442:10:HAL_GetHalVersion 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:451:10:HAL_GetREVID 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:460:10:HAL_GetDEVID 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:469:6:HAL_DBGMCU_EnableDBGSleepMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:478:6:HAL_DBGMCU_DisableDBGSleepMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:487:6:HAL_DBGMCU_EnableDBGStopMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:496:6:HAL_DBGMCU_DisableDBGStopMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:505:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:514:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:525:6:HAL_EnableCompensationCell 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:536:6:HAL_DisableCompensationCell 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:545:10:HAL_GetUIDw0 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:554:10:HAL_GetUIDw1 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:563:10:HAL_GetUIDw2 4 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo new file mode 100644 index 00000000..04f992fd --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo @@ -0,0 +1,35 @@ +../Drivers/CMSIS/Include/core_cm4.h:1653:22:__NVIC_SetPriorityGrouping 1 +../Drivers/CMSIS/Include/core_cm4.h:1672:26:__NVIC_GetPriorityGrouping 1 +../Drivers/CMSIS/Include/core_cm4.h:1684:22:__NVIC_EnableIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1722:22:__NVIC_DisableIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1741:26:__NVIC_GetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1760:22:__NVIC_SetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1775:22:__NVIC_ClearPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1792:26:__NVIC_GetActive 2 +../Drivers/CMSIS/Include/core_cm4.h:1814:22:__NVIC_SetPriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1836:26:__NVIC_GetPriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1861:26:NVIC_EncodePriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1888:22:NVIC_DecodePriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1938:34:__NVIC_SystemReset 1 +../Drivers/CMSIS/Include/core_cm4.h:2022:26:SysTick_Config 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:141:6:HAL_NVIC_SetPriorityGrouping 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:163:6:HAL_NVIC_SetPriority 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:185:6:HAL_NVIC_EnableIRQ 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:201:6:HAL_NVIC_DisableIRQ 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:214:6:HAL_NVIC_SystemReset 0 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:227:10:HAL_SYSTICK_Config 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:256:6:HAL_MPU_Disable 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:279:6:HAL_MPU_Enable 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:296:6:HAL_MPU_EnableRegion 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:312:6:HAL_MPU_DisableRegion 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:330:6:HAL_MPU_ConfigRegion 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:368:6:HAL_CORTEX_ClearEvent 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:378:10:HAL_NVIC_GetPriorityGrouping 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:405:6:HAL_NVIC_GetPriority 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:420:6:HAL_NVIC_SetPendingIRQ 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:438:10:HAL_NVIC_GetPendingIRQ 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:454:6:HAL_NVIC_ClearPendingIRQ 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:471:10:HAL_NVIC_GetActive 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:488:6:HAL_SYSTICK_CLKSourceConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:506:6:HAL_SYSTICK_IRQHandler 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:515:13:HAL_SYSTICK_Callback 1 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d new file mode 100644 index 00000000..93b84ece --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o new file mode 100644 index 00000000..1e9a78e9 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su new file mode 100644 index 00000000..985c4808 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su @@ -0,0 +1,35 @@ +../Drivers/CMSIS/Include/core_cm4.h:1653:22:__NVIC_SetPriorityGrouping 24 static +../Drivers/CMSIS/Include/core_cm4.h:1672:26:__NVIC_GetPriorityGrouping 4 static +../Drivers/CMSIS/Include/core_cm4.h:1684:22:__NVIC_EnableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:1722:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:1741:26:__NVIC_GetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1760:22:__NVIC_SetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1775:22:__NVIC_ClearPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1792:26:__NVIC_GetActive 16 static +../Drivers/CMSIS/Include/core_cm4.h:1814:22:__NVIC_SetPriority 16 static +../Drivers/CMSIS/Include/core_cm4.h:1836:26:__NVIC_GetPriority 16 static +../Drivers/CMSIS/Include/core_cm4.h:1861:26:NVIC_EncodePriority 40 static +../Drivers/CMSIS/Include/core_cm4.h:1888:22:NVIC_DecodePriority 40 static +../Drivers/CMSIS/Include/core_cm4.h:1938:34:__NVIC_SystemReset 4 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:2022:26:SysTick_Config 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:141:6:HAL_NVIC_SetPriorityGrouping 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:163:6:HAL_NVIC_SetPriority 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:185:6:HAL_NVIC_EnableIRQ 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:201:6:HAL_NVIC_DisableIRQ 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:214:6:HAL_NVIC_SystemReset 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:227:10:HAL_SYSTICK_Config 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:256:6:HAL_MPU_Disable 4 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:279:6:HAL_MPU_Enable 16 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:296:6:HAL_MPU_EnableRegion 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:312:6:HAL_MPU_DisableRegion 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:330:6:HAL_MPU_ConfigRegion 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:368:6:HAL_CORTEX_ClearEvent 4 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:378:10:HAL_NVIC_GetPriorityGrouping 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:405:6:HAL_NVIC_GetPriority 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:420:6:HAL_NVIC_SetPendingIRQ 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:438:10:HAL_NVIC_GetPendingIRQ 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:454:6:HAL_NVIC_ClearPendingIRQ 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:471:10:HAL_NVIC_GetActive 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:488:6:HAL_SYSTICK_CLKSourceConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:506:6:HAL_SYSTICK_IRQHandler 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:515:13:HAL_SYSTICK_Callback 4 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo new file mode 100644 index 00000000..29a68e40 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo @@ -0,0 +1,15 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:170:19:HAL_DMA_Init 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:309:19:HAL_DMA_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:407:19:HAL_DMA_Start 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:451:19:HAL_DMA_Start_IT 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:513:19:HAL_DMA_Abort 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:580:19:HAL_DMA_Abort_IT 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:610:19:HAL_DMA_PollForTransfer 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:746:6:HAL_DMA_IRQHandler 32 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:967:19:HAL_DMA_RegisterCallback 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1029:19:HAL_DMA_UnRegisterCallback 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1114:22:HAL_DMA_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1125:10:HAL_DMA_GetError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1151:13:DMA_SetConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1185:17:DMA_CalcBaseAndBitshift 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1213:26:DMA_CheckFifoParam 15 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d new file mode 100644 index 00000000..44fd2965 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o new file mode 100644 index 00000000..88fd28bb Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su new file mode 100644 index 00000000..6c24b90d --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su @@ -0,0 +1,15 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:170:19:HAL_DMA_Init 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:309:19:HAL_DMA_DeInit 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:407:19:HAL_DMA_Start 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:451:19:HAL_DMA_Start_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:513:19:HAL_DMA_Abort 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:580:19:HAL_DMA_Abort_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:610:19:HAL_DMA_PollForTransfer 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:746:6:HAL_DMA_IRQHandler 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:967:19:HAL_DMA_RegisterCallback 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1029:19:HAL_DMA_UnRegisterCallback 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1114:22:HAL_DMA_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1125:10:HAL_DMA_GetError 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1151:13:DMA_SetConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1185:17:DMA_CalcBaseAndBitshift 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1213:26:DMA_CheckFifoParam 24 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo new file mode 100644 index 00000000..8080a4a9 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo @@ -0,0 +1,4 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:100:19:HAL_DMAEx_MultiBufferStart 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:154:19:HAL_DMAEx_MultiBufferStart_IT 264 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:239:19:HAL_DMAEx_ChangeMemory 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:276:13:DMA_MultiBufferSetConfig 2 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d new file mode 100644 index 00000000..a5b9ab6f --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o new file mode 100644 index 00000000..b357b0b1 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su new file mode 100644 index 00000000..9b2268bd --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su @@ -0,0 +1,4 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:100:19:HAL_DMAEx_MultiBufferStart 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:154:19:HAL_DMAEx_MultiBufferStart_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:239:19:HAL_DMAEx_ChangeMemory 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:276:13:DMA_MultiBufferSetConfig 24 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo new file mode 100644 index 00000000..65258b17 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:466:10:HAL_EXTI_GetPending 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:498:6:HAL_EXTI_ClearPending 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:522:6:HAL_EXTI_GenerateSWI 1 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d new file mode 100644 index 00000000..387a44c6 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o new file mode 100644 index 00000000..51552fb7 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su new file mode 100644 index 00000000..8a14ca59 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su @@ -0,0 +1,9 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:466:10:HAL_EXTI_GetPending 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:498:6:HAL_EXTI_ClearPending 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:522:6:HAL_EXTI_GenerateSWI 24 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo new file mode 100644 index 00000000..3035a468 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo @@ -0,0 +1,17 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:161:19:HAL_FLASH_Program 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:219:19:HAL_FLASH_Program_IT 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:263:6:HAL_FLASH_IRQHandler 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:383:13:HAL_FLASH_EndOfOperationCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:400:13:HAL_FLASH_OperationErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:432:19:HAL_FLASH_Unlock 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:456:19:HAL_FLASH_Lock 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:468:19:HAL_FLASH_OB_Unlock 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:488:19:HAL_FLASH_OB_Lock 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:500:19:HAL_FLASH_OB_Launch 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:537:10:HAL_FLASH_GetError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:551:19:FLASH_WaitForLastOperation 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:611:13:FLASH_Program_DoubleWord 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:645:13:FLASH_Program_Word 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:670:13:FLASH_Program_HalfWord 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:695:13:FLASH_Program_Byte 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:712:13:FLASH_SetErrorCode 7 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d new file mode 100644 index 00000000..bc34265a --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o new file mode 100644 index 00000000..9f1f473b Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su new file mode 100644 index 00000000..3f33f488 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su @@ -0,0 +1,17 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:161:19:HAL_FLASH_Program 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:219:19:HAL_FLASH_Program_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:263:6:HAL_FLASH_IRQHandler 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:383:13:HAL_FLASH_EndOfOperationCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:400:13:HAL_FLASH_OperationErrorCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:432:19:HAL_FLASH_Unlock 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:456:19:HAL_FLASH_Lock 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:468:19:HAL_FLASH_OB_Unlock 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:488:19:HAL_FLASH_OB_Lock 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:500:19:HAL_FLASH_OB_Launch 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:537:10:HAL_FLASH_GetError 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:551:19:FLASH_WaitForLastOperation 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:611:13:FLASH_Program_DoubleWord 24 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:645:13:FLASH_Program_Word 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:670:13:FLASH_Program_HalfWord 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:695:13:FLASH_Program_Byte 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:712:13:FLASH_SetErrorCode 4 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo new file mode 100644 index 00000000..7b06e0da --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo @@ -0,0 +1,22 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:160:19:HAL_FLASHEx_Erase 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:231:19:HAL_FLASHEx_Erase_IT 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:281:19:HAL_FLASHEx_OBProgram 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:340:6:HAL_FLASHEx_OBGetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:369:19:HAL_FLASHEx_AdvOBProgram 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:425:6:HAL_FLASHEx_AdvOBGetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:457:19:HAL_FLASHEx_OB_SelectPCROP 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:482:19:HAL_FLASHEx_OB_DeSelectPCROP 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:948:13:FLASH_MassErase 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:977:6:FLASH_Erase_Sector 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1027:26:FLASH_OB_EnableWRP 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1063:26:FLASH_OB_DisableWRP 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1096:26:FLASH_OB_EnablePCROP 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1124:26:FLASH_OB_DisablePCROP 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1157:26:FLASH_OB_RDP_LevelConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1191:26:FLASH_OB_UserConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1226:26:FLASH_OB_BOR_LevelConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1244:16:FLASH_OB_GetUser 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1254:17:FLASH_OB_GetWRP 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1268:16:FLASH_OB_GetRDP 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1296:16:FLASH_OB_GetBOR 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1306:6:FLASH_FlushCaches 3 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d new file mode 100644 index 00000000..db1c6529 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o new file mode 100644 index 00000000..50f581c4 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su new file mode 100644 index 00000000..76905bf7 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su @@ -0,0 +1,22 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:160:19:HAL_FLASHEx_Erase 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:231:19:HAL_FLASHEx_Erase_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:281:19:HAL_FLASHEx_OBProgram 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:340:6:HAL_FLASHEx_OBGetConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:369:19:HAL_FLASHEx_AdvOBProgram 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:425:6:HAL_FLASHEx_AdvOBGetConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:457:19:HAL_FLASHEx_OB_SelectPCROP 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:482:19:HAL_FLASHEx_OB_DeSelectPCROP 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:948:13:FLASH_MassErase 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:977:6:FLASH_Erase_Sector 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1027:26:FLASH_OB_EnableWRP 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1063:26:FLASH_OB_DisableWRP 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1096:26:FLASH_OB_EnablePCROP 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1124:26:FLASH_OB_DisablePCROP 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1157:26:FLASH_OB_RDP_LevelConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1191:26:FLASH_OB_UserConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1226:26:FLASH_OB_BOR_LevelConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1244:16:FLASH_OB_GetUser 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1254:17:FLASH_OB_GetWRP 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1268:16:FLASH_OB_GetRDP 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1296:16:FLASH_OB_GetBOR 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1306:6:FLASH_FlushCaches 4 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo new file mode 100644 index 00000000..bd716274 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo @@ -0,0 +1,4 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:94:30:HAL_FLASHEx_StopFlashInterfaceClk 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:111:30:HAL_FLASHEx_StartFlashInterfaceClk 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:128:30:HAL_FLASHEx_EnableFlashSleepMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:145:30:HAL_FLASHEx_DisableFlashSleepMode 1 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d new file mode 100644 index 00000000..141bd7f2 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o new file mode 100644 index 00000000..8c1bbf02 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su new file mode 100644 index 00000000..c37958f6 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su @@ -0,0 +1,4 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:94:30:HAL_FLASHEx_StopFlashInterfaceClk 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:111:30:HAL_FLASHEx_StartFlashInterfaceClk 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:128:30:HAL_FLASHEx_EnableFlashSleepMode 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:145:30:HAL_FLASHEx_DisableFlashSleepMode 16 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo new file mode 100644 index 00000000..bcef341b --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo @@ -0,0 +1,8 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:164:6:HAL_GPIO_Init 19 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:294:6:HAL_GPIO_DeInit 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:375:15:HAL_GPIO_ReadPin 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:410:6:HAL_GPIO_WritePin 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:433:6:HAL_GPIO_TogglePin 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:458:19:HAL_GPIO_LockPin 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:492:6:HAL_GPIO_EXTI_IRQHandler 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:507:13:HAL_GPIO_EXTI_Callback 1 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d new file mode 100644 index 00000000..12e17379 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o new file mode 100644 index 00000000..39067e22 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su new file mode 100644 index 00000000..2ae13210 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su @@ -0,0 +1,8 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:164:6:HAL_GPIO_Init 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:294:6:HAL_GPIO_DeInit 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:375:15:HAL_GPIO_ReadPin 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:410:6:HAL_GPIO_WritePin 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:433:6:HAL_GPIO_TogglePin 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:458:19:HAL_GPIO_LockPin 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:492:6:HAL_GPIO_EXTI_IRQHandler 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:507:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo new file mode 100644 index 00000000..d56c7657 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo @@ -0,0 +1,82 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:445:19:HAL_I2C_Init 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:560:19:HAL_I2C_DeInit 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:606:13:HAL_I2C_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:622:13:HAL_I2C_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:959:13:I2C_Flush_DR 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1056:19:HAL_I2C_Master_Transmit 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1177:19:HAL_I2C_Master_Receive 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1428:19:HAL_I2C_Slave_Transmit 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1558:19:HAL_I2C_Slave_Receive 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1679:19:HAL_I2C_Master_Transmit_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1756:19:HAL_I2C_Master_Receive_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1836:19:HAL_I2C_Slave_Transmit_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1898:19:HAL_I2C_Slave_Receive_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1962:19:HAL_I2C_Master_Transmit_DMA 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2117:19:HAL_I2C_Master_Receive_DMA 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2270:19:HAL_I2C_Slave_Transmit_DMA 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2384:19:HAL_I2C_Slave_Receive_DMA 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2503:19:HAL_I2C_Mem_Write 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2626:19:HAL_I2C_Mem_Read 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2878:19:HAL_I2C_Mem_Write_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2963:19:HAL_I2C_Mem_Read_IT 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3054:19:HAL_I2C_Mem_Write_DMA 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3236:19:HAL_I2C_Mem_Read_DMA 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3432:19:HAL_I2C_IsDeviceReady 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3568:19:HAL_I2C_Master_Seq_Transmit_IT 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3663:19:HAL_I2C_Master_Seq_Transmit_DMA 23 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3843:19:HAL_I2C_Master_Seq_Receive_IT 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3964:19:HAL_I2C_Master_Seq_Receive_DMA 30 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4179:19:HAL_I2C_Slave_Seq_Transmit_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4245:19:HAL_I2C_Slave_Seq_Transmit_DMA 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4419:19:HAL_I2C_Slave_Seq_Receive_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4485:19:HAL_I2C_Slave_Seq_Receive_DMA 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4655:19:HAL_I2C_EnableListen_IT 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4688:19:HAL_I2C_DisableListen_IT 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4723:19:HAL_I2C_Master_Abort_IT 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4783:6:HAL_I2C_EV_IRQHandler 46 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4952:6:HAL_I2C_ER_IRQHandler 18 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5032:13:HAL_I2C_MasterTxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5048:13:HAL_I2C_MasterRxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5063:13:HAL_I2C_SlaveTxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5079:13:HAL_I2C_SlaveRxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5097:13:HAL_I2C_AddrCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5115:13:HAL_I2C_ListenCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5131:13:HAL_I2C_MemTxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5147:13:HAL_I2C_MemRxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5163:13:HAL_I2C_ErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5179:13:HAL_I2C_AbortCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5214:22:HAL_I2C_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5226:21:HAL_I2C_GetMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5237:10:HAL_I2C_GetError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5260:13:I2C_MasterTransmit_TXE 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5354:13:I2C_MasterTransmit_BTF 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5433:13:I2C_MemoryTransmit_TXE_BTF 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5520:13:I2C_MasterReceive_RXNE 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5639:13:I2C_MasterReceive_BTF 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5768:13:I2C_Master_SB 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5829:13:I2C_Master_ADD10 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5848:13:I2C_Master_ADDR 33 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5993:13:I2C_SlaveTransmit_TXE 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6034:13:I2C_SlaveTransmit_BTF 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6055:13:I2C_SlaveReceive_RXNE 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6096:13:I2C_SlaveReceive_BTF 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6118:13:I2C_Slave_ADDR 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6169:13:I2C_Slave_STOPF 19 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6338:13:I2C_Slave_AF 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6407:13:I2C_ITError 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6573:26:I2C_MasterRequestWrite 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6643:26:I2C_MasterRequestRead 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6743:26:I2C_RequestMemoryWrite 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6823:26:I2C_RequestMemoryRead 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6932:13:I2C_DMAXferCplt 18 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7077:13:I2C_DMAError 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7118:13:I2C_DMAAbort 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7221:26:I2C_WaitOnFlagUntilTimeout 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7258:26:I2C_WaitOnMasterAddressFlagUntilTimeout 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7312:26:I2C_WaitOnTXEFlagUntilTimeout 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7353:26:I2C_WaitOnBTFFlagUntilTimeout 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7394:26:I2C_WaitOnSTOPFlagUntilTimeout 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7430:26:I2C_WaitOnSTOPRequestThroughIT 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7459:26:I2C_WaitOnRXNEFlagUntilTimeout 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7507:26:I2C_IsAcknowledgeFailed 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7532:13:I2C_ConvertOtherXferOptions 3 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d new file mode 100644 index 00000000..cfb11d36 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o new file mode 100644 index 00000000..af912a65 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su new file mode 100644 index 00000000..135aba49 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su @@ -0,0 +1,82 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:445:19:HAL_I2C_Init 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:560:19:HAL_I2C_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:606:13:HAL_I2C_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:622:13:HAL_I2C_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:959:13:I2C_Flush_DR 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1056:19:HAL_I2C_Master_Transmit 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1177:19:HAL_I2C_Master_Receive 56 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1428:19:HAL_I2C_Slave_Transmit 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1558:19:HAL_I2C_Slave_Receive 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1679:19:HAL_I2C_Master_Transmit_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1756:19:HAL_I2C_Master_Receive_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1836:19:HAL_I2C_Slave_Transmit_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1898:19:HAL_I2C_Slave_Receive_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1962:19:HAL_I2C_Master_Transmit_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2117:19:HAL_I2C_Master_Receive_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2270:19:HAL_I2C_Slave_Transmit_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2384:19:HAL_I2C_Slave_Receive_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2503:19:HAL_I2C_Mem_Write 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2626:19:HAL_I2C_Mem_Read 56 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2878:19:HAL_I2C_Mem_Write_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2963:19:HAL_I2C_Mem_Read_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3054:19:HAL_I2C_Mem_Write_DMA 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3236:19:HAL_I2C_Mem_Read_DMA 56 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3432:19:HAL_I2C_IsDeviceReady 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3568:19:HAL_I2C_Master_Seq_Transmit_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3663:19:HAL_I2C_Master_Seq_Transmit_DMA 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3843:19:HAL_I2C_Master_Seq_Receive_IT 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3964:19:HAL_I2C_Master_Seq_Receive_DMA 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4179:19:HAL_I2C_Slave_Seq_Transmit_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4245:19:HAL_I2C_Slave_Seq_Transmit_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4419:19:HAL_I2C_Slave_Seq_Receive_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4485:19:HAL_I2C_Slave_Seq_Receive_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4655:19:HAL_I2C_EnableListen_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4688:19:HAL_I2C_DisableListen_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4723:19:HAL_I2C_Master_Abort_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4783:6:HAL_I2C_EV_IRQHandler 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4952:6:HAL_I2C_ER_IRQHandler 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5032:13:HAL_I2C_MasterTxCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5048:13:HAL_I2C_MasterRxCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5063:13:HAL_I2C_SlaveTxCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5079:13:HAL_I2C_SlaveRxCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5097:13:HAL_I2C_AddrCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5115:13:HAL_I2C_ListenCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5131:13:HAL_I2C_MemTxCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5147:13:HAL_I2C_MemRxCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5163:13:HAL_I2C_ErrorCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5179:13:HAL_I2C_AbortCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5214:22:HAL_I2C_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5226:21:HAL_I2C_GetMode 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5237:10:HAL_I2C_GetError 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5260:13:I2C_MasterTransmit_TXE 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5354:13:I2C_MasterTransmit_BTF 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5433:13:I2C_MemoryTransmit_TXE_BTF 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5520:13:I2C_MasterReceive_RXNE 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5639:13:I2C_MasterReceive_BTF 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5768:13:I2C_Master_SB 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5829:13:I2C_Master_ADD10 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5848:13:I2C_Master_ADDR 72 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5993:13:I2C_SlaveTransmit_TXE 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6034:13:I2C_SlaveTransmit_BTF 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6055:13:I2C_SlaveReceive_RXNE 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6096:13:I2C_SlaveReceive_BTF 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6118:13:I2C_Slave_ADDR 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6169:13:I2C_Slave_STOPF 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6338:13:I2C_Slave_AF 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6407:13:I2C_ITError 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6573:26:I2C_MasterRequestWrite 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6643:26:I2C_MasterRequestRead 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6743:26:I2C_RequestMemoryWrite 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6823:26:I2C_RequestMemoryRead 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6932:13:I2C_DMAXferCplt 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7077:13:I2C_DMAError 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7118:13:I2C_DMAAbort 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7221:26:I2C_WaitOnFlagUntilTimeout 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7258:26:I2C_WaitOnMasterAddressFlagUntilTimeout 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7312:26:I2C_WaitOnTXEFlagUntilTimeout 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7353:26:I2C_WaitOnBTFFlagUntilTimeout 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7394:26:I2C_WaitOnSTOPFlagUntilTimeout 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7430:26:I2C_WaitOnSTOPRequestThroughIT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7459:26:I2C_WaitOnRXNEFlagUntilTimeout 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7507:26:I2C_IsAcknowledgeFailed 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7532:13:I2C_ConvertOtherXferOptions 16 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo new file mode 100644 index 00000000..84b11ba7 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo @@ -0,0 +1,2 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c:88:19:HAL_I2CEx_ConfigAnalogFilter 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c:126:19:HAL_I2CEx_ConfigDigitalFilter 2 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d new file mode 100644 index 00000000..2cffc3d7 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o new file mode 100644 index 00000000..c862940a Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su new file mode 100644 index 00000000..6fd02734 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su @@ -0,0 +1,2 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c:88:19:HAL_I2CEx_ConfigAnalogFilter 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c:126:19:HAL_I2CEx_ConfigDigitalFilter 24 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo new file mode 100644 index 00000000..94a32b46 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo @@ -0,0 +1,38 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:123:19:HAL_PCD_Init 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:258:19:HAL_PCD_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:297:13:HAL_PCD_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:312:13:HAL_PCD_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1015:19:HAL_PCD_Start 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1040:19:HAL_PCD_Stop 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1068:6:HAL_PCD_IRQHandler 59 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1532:6:HAL_PCD_WKUP_IRQHandler 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1559:13:HAL_PCD_DataOutStageCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1576:13:HAL_PCD_DataInStageCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1591:13:HAL_PCD_SetupStageCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1606:13:HAL_PCD_SOFCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1621:13:HAL_PCD_ResetCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1636:13:HAL_PCD_SuspendCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1651:13:HAL_PCD_ResumeCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1667:13:HAL_PCD_ISOOUTIncompleteCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1684:13:HAL_PCD_ISOINIncompleteCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1700:13:HAL_PCD_ConnectCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1715:13:HAL_PCD_DisconnectCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1749:19:HAL_PCD_DevConnect 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1772:19:HAL_PCD_DevDisconnect 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1797:19:HAL_PCD_SetAddress 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1814:19:HAL_PCD_EP_Open 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1860:19:HAL_PCD_EP_Close 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1891:19:HAL_PCD_EP_Receive 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1920:10:HAL_PCD_EP_GetRxCount 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1932:19:HAL_PCD_EP_Transmit 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1961:19:HAL_PCD_EP_SetStall 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2004:19:HAL_PCD_EP_ClrStall 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2040:19:HAL_PCD_EP_Abort 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2066:19:HAL_PCD_EP_Flush 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2089:19:HAL_PCD_ActivateRemoteWakeup 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2099:19:HAL_PCD_DeActivateRemoteWakeup 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2128:18:HAL_PCD_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2140:19:HAL_PCD_SetTestMode 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2182:26:PCD_WriteEmptyTxFifo 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2242:26:PCD_EP_OutXfrComplete_int 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2354:26:PCD_EP_OutSetupPacket_int 5 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d new file mode 100644 index 00000000..8ed93470 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o new file mode 100644 index 00000000..7cf67108 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su new file mode 100644 index 00000000..a609c8f4 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su @@ -0,0 +1,38 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:123:19:HAL_PCD_Init 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:258:19:HAL_PCD_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:297:13:HAL_PCD_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:312:13:HAL_PCD_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1015:19:HAL_PCD_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1040:19:HAL_PCD_Stop 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1068:6:HAL_PCD_IRQHandler 64 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1532:6:HAL_PCD_WKUP_IRQHandler 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1559:13:HAL_PCD_DataOutStageCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1576:13:HAL_PCD_DataInStageCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1591:13:HAL_PCD_SetupStageCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1606:13:HAL_PCD_SOFCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1621:13:HAL_PCD_ResetCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1636:13:HAL_PCD_SuspendCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1651:13:HAL_PCD_ResumeCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1667:13:HAL_PCD_ISOOUTIncompleteCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1684:13:HAL_PCD_ISOINIncompleteCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1700:13:HAL_PCD_ConnectCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1715:13:HAL_PCD_DisconnectCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1749:19:HAL_PCD_DevConnect 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1772:19:HAL_PCD_DevDisconnect 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1797:19:HAL_PCD_SetAddress 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1814:19:HAL_PCD_EP_Open 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1860:19:HAL_PCD_EP_Close 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1891:19:HAL_PCD_EP_Receive 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1920:10:HAL_PCD_EP_GetRxCount 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1932:19:HAL_PCD_EP_Transmit 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1961:19:HAL_PCD_EP_SetStall 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2004:19:HAL_PCD_EP_ClrStall 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2040:19:HAL_PCD_EP_Abort 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2066:19:HAL_PCD_EP_Flush 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2089:19:HAL_PCD_ActivateRemoteWakeup 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2099:19:HAL_PCD_DeActivateRemoteWakeup 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2128:18:HAL_PCD_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2140:19:HAL_PCD_SetTestMode 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2182:26:PCD_WriteEmptyTxFifo 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2242:26:PCD_EP_OutXfrComplete_int 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2354:26:PCD_EP_OutSetupPacket_int 32 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo new file mode 100644 index 00000000..f616ddf9 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo @@ -0,0 +1,6 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:70:19:HAL_PCDEx_SetTxFiFo 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:112:19:HAL_PCDEx_SetRxFiFo 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:126:19:HAL_PCDEx_ActivateLPM 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:143:19:HAL_PCDEx_DeActivateLPM 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:303:13:HAL_PCDEx_LPM_Callback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:320:13:HAL_PCDEx_BCD_Callback 1 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d new file mode 100644 index 00000000..a330b78f --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o new file mode 100644 index 00000000..a8fbea38 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su new file mode 100644 index 00000000..0574680f --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su @@ -0,0 +1,6 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:70:19:HAL_PCDEx_SetTxFiFo 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:112:19:HAL_PCDEx_SetRxFiFo 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:126:19:HAL_PCDEx_ActivateLPM 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:143:19:HAL_PCDEx_DeActivateLPM 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:303:13:HAL_PCDEx_LPM_Callback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:320:13:HAL_PCDEx_BCD_Callback 16 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo new file mode 100644 index 00000000..fcef8458 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo @@ -0,0 +1,17 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:90:6:HAL_PWR_DeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:108:6:HAL_PWR_EnableBkUpAccess 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:128:6:HAL_PWR_DisableBkUpAccess 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:275:6:HAL_PWR_ConfigPVD 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:318:6:HAL_PWR_EnablePVD 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:327:6:HAL_PWR_DisablePVD 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:341:6:HAL_PWR_EnableWakeUpPin 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:359:6:HAL_PWR_DisableWakeUpPin 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:391:6:HAL_PWR_EnterSLEEPMode 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:445:6:HAL_PWR_EnterSTOPMode 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:488:6:HAL_PWR_EnterSTANDBYMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:509:6:HAL_PWR_PVD_IRQHandler 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:526:13:HAL_PWR_PVDCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:541:6:HAL_PWR_EnableSleepOnExit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:553:6:HAL_PWR_DisableSleepOnExit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:565:6:HAL_PWR_EnableSEVOnPend 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:577:6:HAL_PWR_DisableSEVOnPend 1 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d new file mode 100644 index 00000000..75b77829 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o new file mode 100644 index 00000000..12392f23 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su new file mode 100644 index 00000000..4eb40e84 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su @@ -0,0 +1,17 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:90:6:HAL_PWR_DeInit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:108:6:HAL_PWR_EnableBkUpAccess 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:128:6:HAL_PWR_DisableBkUpAccess 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:275:6:HAL_PWR_ConfigPVD 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:318:6:HAL_PWR_EnablePVD 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:327:6:HAL_PWR_DisablePVD 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:341:6:HAL_PWR_EnableWakeUpPin 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:359:6:HAL_PWR_DisableWakeUpPin 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:391:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:445:6:HAL_PWR_EnterSTOPMode 16 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:488:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:509:6:HAL_PWR_PVD_IRQHandler 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:526:13:HAL_PWR_PVDCallback 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:541:6:HAL_PWR_EnableSleepOnExit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:553:6:HAL_PWR_DisableSleepOnExit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:565:6:HAL_PWR_EnableSEVOnPend 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:577:6:HAL_PWR_DisableSEVOnPend 4 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo new file mode 100644 index 00000000..970ac44e --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:141:19:HAL_PWREx_EnableBkUpReg 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:165:19:HAL_PWREx_DisableBkUpReg 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:189:6:HAL_PWREx_EnableFlashPowerDown 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:198:6:HAL_PWREx_DisableFlashPowerDown 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:211:10:HAL_PWREx_GetVoltageRange 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:288:19:HAL_PWREx_ControlVoltageScaling 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:413:19:HAL_PWREx_EnableOverDrive 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:460:19:HAL_PWREx_DisableOverDrive 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:536:19:HAL_PWREx_EnterUnderDriveSTOPMode 2 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d new file mode 100644 index 00000000..220344d7 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o new file mode 100644 index 00000000..6951152c Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su new file mode 100644 index 00000000..afdd0771 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su @@ -0,0 +1,9 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:141:19:HAL_PWREx_EnableBkUpReg 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:165:19:HAL_PWREx_DisableBkUpReg 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:189:6:HAL_PWREx_EnableFlashPowerDown 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:198:6:HAL_PWREx_DisableFlashPowerDown 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:211:10:HAL_PWREx_GetVoltageRange 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:288:19:HAL_PWREx_ControlVoltageScaling 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:413:19:HAL_PWREx_EnableOverDrive 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:460:19:HAL_PWREx_DisableOverDrive 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:536:19:HAL_PWREx_EnterUnderDriveSTOPMode 24 static,ignoring_inline_asm diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo new file mode 100644 index 00000000..a235e51e --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:200:26:HAL_RCC_DeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:219:26:HAL_RCC_OscConfig 62 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:591:19:HAL_RCC_ClockConfig 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:775:6:HAL_RCC_MCOConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:841:6:HAL_RCC_EnableCSS 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:850:6:HAL_RCC_DisableCSS 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:885:17:HAL_RCC_GetSysClockFreq 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:943:10:HAL_RCC_GetHCLKFreq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:954:10:HAL_RCC_GetPCLK1Freq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:966:10:HAL_RCC_GetPCLK2Freq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:979:13:HAL_RCC_GetOscConfig 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1058:6:HAL_RCC_GetClockConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1084:6:HAL_RCC_NMI_IRQHandler 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1101:13:HAL_RCC_CSSCallback 1 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d new file mode 100644 index 00000000..ed14ce03 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o new file mode 100644 index 00000000..13f63a55 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su new file mode 100644 index 00000000..7b240098 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su @@ -0,0 +1,14 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:200:26:HAL_RCC_DeInit 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:219:26:HAL_RCC_OscConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:591:19:HAL_RCC_ClockConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:775:6:HAL_RCC_MCOConfig 56 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:841:6:HAL_RCC_EnableCSS 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:850:6:HAL_RCC_DisableCSS 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:885:17:HAL_RCC_GetSysClockFreq 112 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:943:10:HAL_RCC_GetHCLKFreq 4 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:954:10:HAL_RCC_GetPCLK1Freq 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:966:10:HAL_RCC_GetPCLK2Freq 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:979:13:HAL_RCC_GetOscConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1058:6:HAL_RCC_GetClockConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1084:6:HAL_RCC_NMI_IRQHandler 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1101:13:HAL_RCC_CSSCallback 4 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo new file mode 100644 index 00000000..9b944148 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo @@ -0,0 +1,12 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:87:19:HAL_RCCEx_PeriphCLKConfig 56 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:500:6:HAL_RCCEx_GetPeriphCLKConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:580:10:HAL_RCCEx_GetPeriphCLKFreq 38 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2809:6:HAL_RCCEx_SelectLSEMode 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2846:19:HAL_RCCEx_EnablePLLI2S 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2929:19:HAL_RCCEx_DisablePLLI2S 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2959:19:HAL_RCCEx_EnablePLLSAI 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3033:19:HAL_RCCEx_DisablePLLSAI 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3094:10:HAL_RCC_GetSysClockFreq 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3186:19:HAL_RCC_DeInit 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3377:19:HAL_RCC_OscConfig 66 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3752:6:HAL_RCC_GetOscConfig 8 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d new file mode 100644 index 00000000..efb9c676 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o new file mode 100644 index 00000000..3f6d714e Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su new file mode 100644 index 00000000..534b848c --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su @@ -0,0 +1,12 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:87:19:HAL_RCCEx_PeriphCLKConfig 56 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:500:6:HAL_RCCEx_GetPeriphCLKConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:580:10:HAL_RCCEx_GetPeriphCLKFreq 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2809:6:HAL_RCCEx_SelectLSEMode 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2846:19:HAL_RCCEx_EnablePLLI2S 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2929:19:HAL_RCCEx_DisablePLLI2S 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2959:19:HAL_RCCEx_EnablePLLSAI 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3033:19:HAL_RCCEx_DisablePLLSAI 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3094:10:HAL_RCC_GetSysClockFreq 216 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3186:19:HAL_RCC_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3377:19:HAL_RCC_OscConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3752:6:HAL_RCC_GetOscConfig 16 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo new file mode 100644 index 00000000..673019de --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo @@ -0,0 +1,119 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:266:19:HAL_TIM_Base_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:326:19:HAL_TIM_Base_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:369:13:HAL_TIM_Base_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:384:13:HAL_TIM_Base_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:400:19:HAL_TIM_Base_Start 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:439:19:HAL_TIM_Base_Stop 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:459:19:HAL_TIM_Base_Start_IT 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:501:19:HAL_TIM_Base_Stop_IT 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:526:19:HAL_TIM_Base_Start_DMA 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:595:19:HAL_TIM_Base_Stop_DMA 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:650:19:HAL_TIM_OC_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:710:19:HAL_TIM_OC_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:753:13:HAL_TIM_OC_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:768:13:HAL_TIM_OC_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:789:19:HAL_TIM_OC_Start 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:843:19:HAL_TIM_OC_Stop 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:878:19:HAL_TIM_OC_Start_IT 25 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:971:19:HAL_TIM_OC_Stop_IT 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1048:19:HAL_TIM_OC_Start_DMA 35 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1212:19:HAL_TIM_OC_Stop_DMA 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1315:19:HAL_TIM_PWM_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1375:19:HAL_TIM_PWM_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1418:13:HAL_TIM_PWM_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1454:19:HAL_TIM_PWM_Start 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1508:19:HAL_TIM_PWM_Stop 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1543:19:HAL_TIM_PWM_Start_IT 25 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1636:19:HAL_TIM_PWM_Stop_IT 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1713:19:HAL_TIM_PWM_Start_DMA 35 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1876:19:HAL_TIM_PWM_Stop_DMA 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1979:19:HAL_TIM_IC_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2039:19:HAL_TIM_IC_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2082:13:HAL_TIM_IC_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2097:13:HAL_TIM_IC_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2118:19:HAL_TIM_IC_Start 24 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2170:19:HAL_TIM_IC_Stop 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2200:19:HAL_TIM_IC_Start_IT 29 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2292:19:HAL_TIM_IC_Stop_IT 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2364:19:HAL_TIM_IC_Start_DMA 36 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2523:19:HAL_TIM_IC_Stop_DMA 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2628:19:HAL_TIM_OnePulse_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2697:19:HAL_TIM_OnePulse_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2742:13:HAL_TIM_OnePulse_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2757:13:HAL_TIM_OnePulse_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2777:19:HAL_TIM_OnePulse_Start 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2834:19:HAL_TIM_OnePulse_Stop 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2877:19:HAL_TIM_OnePulse_Start_IT 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2940:19:HAL_TIM_OnePulse_Stop_IT 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3019:19:HAL_TIM_Encoder_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3134:19:HAL_TIM_Encoder_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3179:13:HAL_TIM_Encoder_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3194:13:HAL_TIM_Encoder_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3214:19:HAL_TIM_Encoder_Start 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3308:19:HAL_TIM_Encoder_Stop 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3368:19:HAL_TIM_Encoder_Start_IT 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3468:19:HAL_TIM_Encoder_Stop_IT 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3533:19:HAL_TIM_Encoder_Start_DMA 32 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3746:19:HAL_TIM_Encoder_Stop_DMA 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3823:6:HAL_TIM_IRQHandler 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4041:19:HAL_TIM_OC_ConfigChannel 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4120:19:HAL_TIM_IC_ConfigChannel 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4219:19:HAL_TIM_PWM_ConfigChannel 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4333:19:HAL_TIM_OnePulse_ConfigChannel 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4481:19:HAL_TIM_DMABurst_WriteStart 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4534:19:HAL_TIM_DMABurst_MultiWriteStart 25 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4718:19:HAL_TIM_DMABurst_WriteStop 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4819:19:HAL_TIM_DMABurst_ReadStart 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4870:19:HAL_TIM_DMABurst_MultiReadStart 25 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5054:19:HAL_TIM_DMABurst_ReadStop 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5137:19:HAL_TIM_GenerateEvent 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5174:19:HAL_TIM_ConfigOCrefClear 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5304:19:HAL_TIM_ConfigClockSource 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5458:19:HAL_TIM_ConfigTI1Input 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5490:19:HAL_TIM_SlaveConfigSynchro 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5530:19:HAL_TIM_SlaveConfigSynchro_IT 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5573:10:HAL_TIM_ReadCapturedValue 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5657:13:HAL_TIM_PeriodElapsedCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5672:13:HAL_TIM_PeriodElapsedHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5687:13:HAL_TIM_OC_DelayElapsedCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5702:13:HAL_TIM_IC_CaptureCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5717:13:HAL_TIM_IC_CaptureHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5732:13:HAL_TIM_PWM_PulseFinishedCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5747:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5762:13:HAL_TIM_TriggerCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5777:13:HAL_TIM_TriggerHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5792:13:HAL_TIM_ErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6339:22:HAL_TIM_Base_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6349:22:HAL_TIM_OC_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6359:22:HAL_TIM_PWM_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6369:22:HAL_TIM_IC_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6379:22:HAL_TIM_OnePulse_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6389:22:HAL_TIM_Encoder_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6399:23:HAL_TIM_GetActiveChannel 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6417:29:HAL_TIM_GetChannelState 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6434:30:HAL_TIM_DMABurstState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6459:6:TIM_DMAError 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6502:13:TIM_DMADelayPulseCplt 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6561:6:TIM_DMADelayPulseHalfCplt 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6600:6:TIM_DMACaptureCplt 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6663:6:TIM_DMACaptureHalfCplt 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6702:13:TIM_DMAPeriodElapsedCplt 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6723:13:TIM_DMAPeriodElapsedHalfCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6739:13:TIM_DMATriggerCplt 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6760:13:TIM_DMATriggerHalfCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6777:6:TIM_Base_SetConfig 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6829:13:TIM_OC1_SetConfig 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6905:6:TIM_OC2_SetConfig 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6981:13:TIM_OC3_SetConfig 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7056:13:TIM_OC4_SetConfig 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7117:26:TIM_SlaveTimer_SetConfig 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7251:6:TIM_TI1_SetConfig 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7298:13:TIM_TI1_ConfigInputStage 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7341:13:TIM_TI2_SetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7381:13:TIM_TI2_ConfigInputStage 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7424:13:TIM_TI3_SetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7472:13:TIM_TI4_SetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7515:13:TIM_ITRx_SetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7545:6:TIM_ETR_SetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7575:6:TIM_CCxChannelCmd 1 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d new file mode 100644 index 00000000..74d1f732 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o new file mode 100644 index 00000000..b6cfe38e Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su new file mode 100644 index 00000000..f4fb564a --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su @@ -0,0 +1,119 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:266:19:HAL_TIM_Base_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:326:19:HAL_TIM_Base_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:369:13:HAL_TIM_Base_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:384:13:HAL_TIM_Base_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:400:19:HAL_TIM_Base_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:439:19:HAL_TIM_Base_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:459:19:HAL_TIM_Base_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:501:19:HAL_TIM_Base_Stop_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:526:19:HAL_TIM_Base_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:595:19:HAL_TIM_Base_Stop_DMA 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:650:19:HAL_TIM_OC_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:710:19:HAL_TIM_OC_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:753:13:HAL_TIM_OC_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:768:13:HAL_TIM_OC_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:789:19:HAL_TIM_OC_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:843:19:HAL_TIM_OC_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:878:19:HAL_TIM_OC_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:971:19:HAL_TIM_OC_Stop_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1048:19:HAL_TIM_OC_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1212:19:HAL_TIM_OC_Stop_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1315:19:HAL_TIM_PWM_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1375:19:HAL_TIM_PWM_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1418:13:HAL_TIM_PWM_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1454:19:HAL_TIM_PWM_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1508:19:HAL_TIM_PWM_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1543:19:HAL_TIM_PWM_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1636:19:HAL_TIM_PWM_Stop_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1713:19:HAL_TIM_PWM_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1876:19:HAL_TIM_PWM_Stop_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1979:19:HAL_TIM_IC_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2039:19:HAL_TIM_IC_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2082:13:HAL_TIM_IC_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2097:13:HAL_TIM_IC_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2118:19:HAL_TIM_IC_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2170:19:HAL_TIM_IC_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2200:19:HAL_TIM_IC_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2292:19:HAL_TIM_IC_Stop_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2364:19:HAL_TIM_IC_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2523:19:HAL_TIM_IC_Stop_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2628:19:HAL_TIM_OnePulse_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2697:19:HAL_TIM_OnePulse_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2742:13:HAL_TIM_OnePulse_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2757:13:HAL_TIM_OnePulse_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2777:19:HAL_TIM_OnePulse_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2834:19:HAL_TIM_OnePulse_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2877:19:HAL_TIM_OnePulse_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2940:19:HAL_TIM_OnePulse_Stop_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3019:19:HAL_TIM_Encoder_Init 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3134:19:HAL_TIM_Encoder_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3179:13:HAL_TIM_Encoder_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3194:13:HAL_TIM_Encoder_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3214:19:HAL_TIM_Encoder_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3308:19:HAL_TIM_Encoder_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3368:19:HAL_TIM_Encoder_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3468:19:HAL_TIM_Encoder_Stop_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3533:19:HAL_TIM_Encoder_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3746:19:HAL_TIM_Encoder_Stop_DMA 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3823:6:HAL_TIM_IRQHandler 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4041:19:HAL_TIM_OC_ConfigChannel 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4120:19:HAL_TIM_IC_ConfigChannel 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4219:19:HAL_TIM_PWM_ConfigChannel 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4333:19:HAL_TIM_OnePulse_ConfigChannel 56 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4481:19:HAL_TIM_DMABurst_WriteStart 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4534:19:HAL_TIM_DMABurst_MultiWriteStart 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4718:19:HAL_TIM_DMABurst_WriteStop 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4819:19:HAL_TIM_DMABurst_ReadStart 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4870:19:HAL_TIM_DMABurst_MultiReadStart 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5054:19:HAL_TIM_DMABurst_ReadStop 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5137:19:HAL_TIM_GenerateEvent 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5174:19:HAL_TIM_ConfigOCrefClear 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5304:19:HAL_TIM_ConfigClockSource 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5458:19:HAL_TIM_ConfigTI1Input 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5490:19:HAL_TIM_SlaveConfigSynchro 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5530:19:HAL_TIM_SlaveConfigSynchro_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5573:10:HAL_TIM_ReadCapturedValue 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5657:13:HAL_TIM_PeriodElapsedCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5672:13:HAL_TIM_PeriodElapsedHalfCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5687:13:HAL_TIM_OC_DelayElapsedCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5702:13:HAL_TIM_IC_CaptureCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5717:13:HAL_TIM_IC_CaptureHalfCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5732:13:HAL_TIM_PWM_PulseFinishedCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5747:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5762:13:HAL_TIM_TriggerCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5777:13:HAL_TIM_TriggerHalfCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5792:13:HAL_TIM_ErrorCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6339:22:HAL_TIM_Base_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6349:22:HAL_TIM_OC_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6359:22:HAL_TIM_PWM_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6369:22:HAL_TIM_IC_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6379:22:HAL_TIM_OnePulse_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6389:22:HAL_TIM_Encoder_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6399:23:HAL_TIM_GetActiveChannel 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6417:29:HAL_TIM_GetChannelState 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6434:30:HAL_TIM_DMABurstState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6459:6:TIM_DMAError 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6502:13:TIM_DMADelayPulseCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6561:6:TIM_DMADelayPulseHalfCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6600:6:TIM_DMACaptureCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6663:6:TIM_DMACaptureHalfCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6702:13:TIM_DMAPeriodElapsedCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6723:13:TIM_DMAPeriodElapsedHalfCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6739:13:TIM_DMATriggerCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6760:13:TIM_DMATriggerHalfCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6777:6:TIM_Base_SetConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6829:13:TIM_OC1_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6905:6:TIM_OC2_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6981:13:TIM_OC3_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7056:13:TIM_OC4_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7117:26:TIM_SlaveTimer_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7251:6:TIM_TI1_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7298:13:TIM_TI1_ConfigInputStage 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7341:13:TIM_TI2_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7381:13:TIM_TI2_ConfigInputStage 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7424:13:TIM_TI3_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7472:13:TIM_TI4_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7515:13:TIM_ITRx_SetConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7545:6:TIM_ETR_SetConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7575:6:TIM_CCxChannelCmd 32 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo new file mode 100644 index 00000000..9bfdfb78 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo @@ -0,0 +1,42 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:138:19:HAL_TIMEx_HallSensor_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:240:19:HAL_TIMEx_HallSensor_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:285:13:HAL_TIMEx_HallSensor_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:300:13:HAL_TIMEx_HallSensor_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:315:19:HAL_TIMEx_HallSensor_Start 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:369:19:HAL_TIMEx_HallSensor_Stop 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:397:19:HAL_TIMEx_HallSensor_Start_IT 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:454:19:HAL_TIMEx_HallSensor_Stop_IT 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:487:19:HAL_TIMEx_HallSensor_Start_DMA 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:563:19:HAL_TIMEx_HallSensor_Stop_DMA 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:625:19:HAL_TIMEx_OCN_Start 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:676:19:HAL_TIMEx_OCN_Stop 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:708:19:HAL_TIMEx_OCN_Start_IT 22 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:795:19:HAL_TIMEx_OCN_Stop_IT 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:870:19:HAL_TIMEx_OCN_Start_DMA 31 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1008:19:HAL_TIMEx_OCN_Stop_DMA 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1098:19:HAL_TIMEx_PWMN_Start 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1148:19:HAL_TIMEx_PWMN_Stop 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1180:19:HAL_TIMEx_PWMN_Start_IT 22 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1266:19:HAL_TIMEx_PWMN_Stop_IT 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1341:19:HAL_TIMEx_PWMN_Start_DMA 31 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1479:19:HAL_TIMEx_PWMN_Stop_DMA 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1570:19:HAL_TIMEx_OnePulseN_Start 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1619:19:HAL_TIMEx_OnePulseN_Stop 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1658:19:HAL_TIMEx_OnePulseN_Start_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1713:19:HAL_TIMEx_OnePulseN_Stop_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1792:19:HAL_TIMEx_ConfigCommutEvent 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1848:19:HAL_TIMEx_ConfigCommutEvent_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1905:19:HAL_TIMEx_ConfigCommutEvent_DMA 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1954:19:HAL_TIMEx_MasterConfigSynchronization 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2015:19:HAL_TIMEx_ConfigBreakDeadTime 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2091:19:HAL_TIMEx_RemapConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2147:13:HAL_TIMEx_CommutCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2161:13:HAL_TIMEx_CommutHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2176:13:HAL_TIMEx_BreakCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2209:22:HAL_TIMEx_HallSensor_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2224:29:HAL_TIMEx_GetChannelNState 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2253:6:TIMEx_DMACommutationCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2272:6:TIMEx_DMACommutationHalfCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2292:13:TIM_DMADelayPulseNCplt 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2342:13:TIM_DMAErrorCCxN 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2387:13:TIM_CCxNChannelCmd 1 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d new file mode 100644 index 00000000..cf3ba16a --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o new file mode 100644 index 00000000..8cca8f3c Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su new file mode 100644 index 00000000..1dd929fe --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su @@ -0,0 +1,42 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:138:19:HAL_TIMEx_HallSensor_Init 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:240:19:HAL_TIMEx_HallSensor_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:285:13:HAL_TIMEx_HallSensor_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:300:13:HAL_TIMEx_HallSensor_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:315:19:HAL_TIMEx_HallSensor_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:369:19:HAL_TIMEx_HallSensor_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:397:19:HAL_TIMEx_HallSensor_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:454:19:HAL_TIMEx_HallSensor_Stop_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:487:19:HAL_TIMEx_HallSensor_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:563:19:HAL_TIMEx_HallSensor_Stop_DMA 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:625:19:HAL_TIMEx_OCN_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:676:19:HAL_TIMEx_OCN_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:708:19:HAL_TIMEx_OCN_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:795:19:HAL_TIMEx_OCN_Stop_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:870:19:HAL_TIMEx_OCN_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1008:19:HAL_TIMEx_OCN_Stop_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1098:19:HAL_TIMEx_PWMN_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1148:19:HAL_TIMEx_PWMN_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1180:19:HAL_TIMEx_PWMN_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1266:19:HAL_TIMEx_PWMN_Stop_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1341:19:HAL_TIMEx_PWMN_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1479:19:HAL_TIMEx_PWMN_Stop_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1570:19:HAL_TIMEx_OnePulseN_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1619:19:HAL_TIMEx_OnePulseN_Stop 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1658:19:HAL_TIMEx_OnePulseN_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1713:19:HAL_TIMEx_OnePulseN_Stop_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1792:19:HAL_TIMEx_ConfigCommutEvent 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1848:19:HAL_TIMEx_ConfigCommutEvent_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1905:19:HAL_TIMEx_ConfigCommutEvent_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1954:19:HAL_TIMEx_MasterConfigSynchronization 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2015:19:HAL_TIMEx_ConfigBreakDeadTime 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2091:19:HAL_TIMEx_RemapConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2147:13:HAL_TIMEx_CommutCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2161:13:HAL_TIMEx_CommutHalfCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2176:13:HAL_TIMEx_BreakCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2209:22:HAL_TIMEx_HallSensor_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2224:29:HAL_TIMEx_GetChannelNState 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2253:6:TIMEx_DMACommutationCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2272:6:TIMEx_DMACommutationHalfCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2292:13:TIM_DMADelayPulseNCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2342:13:TIM_DMAErrorCCxN 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2387:13:TIM_CCxNChannelCmd 32 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo new file mode 100644 index 00000000..8be37003 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo @@ -0,0 +1,62 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:357:19:HAL_UART_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:435:19:HAL_HalfDuplex_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:509:19:HAL_LIN_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:591:19:HAL_MultiProcessor_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:669:19:HAL_UART_DeInit 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:715:13:HAL_UART_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:730:13:HAL_UART_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1135:19:HAL_UART_Transmit 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1221:19:HAL_UART_Receive 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1308:19:HAL_UART_Transmit_IT 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1347:19:HAL_UART_Receive_IT 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1379:19:HAL_UART_Transmit_DMA 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1449:19:HAL_UART_Receive_DMA 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1476:19:HAL_UART_DMAPause 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1507:19:HAL_UART_DMAResume 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1541:19:HAL_UART_DMAStop 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1596:19:HAL_UARTEx_ReceiveToIdle 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1721:19:HAL_UARTEx_ReceiveToIdle_IT 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1781:19:HAL_UARTEx_ReceiveToIdle_DMA 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1846:29:HAL_UARTEx_GetRxEventType 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1864:19:HAL_UART_Abort 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1953:19:HAL_UART_AbortTransmit 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2004:19:HAL_UART_AbortReceive 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2065:19:HAL_UART_Abort_IT 18 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2200:19:HAL_UART_AbortTransmit_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2277:19:HAL_UART_AbortReceive_IT 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2355:6:HAL_UART_IRQHandler 47 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2619:13:HAL_UART_TxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2634:13:HAL_UART_TxHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2649:13:HAL_UART_RxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2664:13:HAL_UART_RxHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2679:13:HAL_UART_ErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2693:13:HAL_UART_AbortCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2708:13:HAL_UART_AbortTransmitCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2723:13:HAL_UART_AbortReceiveCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2740:13:HAL_UARTEx_RxEventCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2780:19:HAL_LIN_SendBreak 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2807:19:HAL_MultiProcessor_EnterMuteMode 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2835:19:HAL_MultiProcessor_ExitMuteMode 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2863:19:HAL_HalfDuplex_EnableTransmitter 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2898:19:HAL_HalfDuplex_EnableReceiver 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2955:23:HAL_UART_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2970:10:HAL_UART_GetError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3015:13:UART_DMATransmitCplt 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3050:13:UART_DMATxHalfCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3069:13:UART_DMAReceiveCplt 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3131:13:UART_DMARxHalfCplt 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3170:13:UART_DMAError 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3212:26:UART_WaitOnFlagUntilTimeout 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3263:19:UART_Start_Receive_IT 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3298:19:UART_Start_Receive_DMA 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3356:13:UART_EndTxTransfer 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3370:13:UART_EndRxTransfer 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3394:13:UART_DMAAbortOnError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3417:13:UART_DMATxAbortCallback 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3463:13:UART_DMARxAbortCallback 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3509:13:UART_DMATxOnlyAbortCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3537:13:UART_DMARxOnlyAbortCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3563:26:UART_Transmit_IT 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3603:26:UART_EndTransmit_IT 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3628:26:UART_Receive_IT 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3731:13:UART_SetConfig 4 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d new file mode 100644 index 00000000..180b2c9f --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o new file mode 100644 index 00000000..95c395c1 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su new file mode 100644 index 00000000..80e6f1c0 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su @@ -0,0 +1,62 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:357:19:HAL_UART_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:435:19:HAL_HalfDuplex_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:509:19:HAL_LIN_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:591:19:HAL_MultiProcessor_Init 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:669:19:HAL_UART_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:715:13:HAL_UART_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:730:13:HAL_UART_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1135:19:HAL_UART_Transmit 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1221:19:HAL_UART_Receive 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1308:19:HAL_UART_Transmit_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1347:19:HAL_UART_Receive_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1379:19:HAL_UART_Transmit_DMA 56 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1449:19:HAL_UART_Receive_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1476:19:HAL_UART_DMAPause 120 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1507:19:HAL_UART_DMAResume 120 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1541:19:HAL_UART_DMAStop 72 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1596:19:HAL_UARTEx_ReceiveToIdle 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1721:19:HAL_UARTEx_ReceiveToIdle_IT 56 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1781:19:HAL_UARTEx_ReceiveToIdle_DMA 56 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1846:29:HAL_UARTEx_GetRxEventType 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1864:19:HAL_UART_Abort 136 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1953:19:HAL_UART_AbortTransmit 64 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2004:19:HAL_UART_AbortReceive 112 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2065:19:HAL_UART_Abort_IT 144 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2200:19:HAL_UART_AbortTransmit_IT 64 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2277:19:HAL_UART_AbortReceive_IT 112 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2355:6:HAL_UART_IRQHandler 240 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2619:13:HAL_UART_TxCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2634:13:HAL_UART_TxHalfCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2649:13:HAL_UART_RxCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2664:13:HAL_UART_RxHalfCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2679:13:HAL_UART_ErrorCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2693:13:HAL_UART_AbortCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2708:13:HAL_UART_AbortTransmitCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2723:13:HAL_UART_AbortReceiveCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2740:13:HAL_UARTEx_RxEventCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2780:19:HAL_LIN_SendBreak 40 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2807:19:HAL_MultiProcessor_EnterMuteMode 40 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2835:19:HAL_MultiProcessor_ExitMuteMode 40 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2863:19:HAL_HalfDuplex_EnableTransmitter 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2898:19:HAL_HalfDuplex_EnableReceiver 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2955:23:HAL_UART_GetState 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2970:10:HAL_UART_GetError 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3015:13:UART_DMATransmitCplt 72 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3050:13:UART_DMATxHalfCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3069:13:UART_DMAReceiveCplt 120 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3131:13:UART_DMARxHalfCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3170:13:UART_DMAError 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3212:26:UART_WaitOnFlagUntilTimeout 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3263:19:UART_Start_Receive_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3298:19:UART_Start_Receive_DMA 104 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3356:13:UART_EndTxTransfer 40 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3370:13:UART_EndRxTransfer 88 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3394:13:UART_DMAAbortOnError 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3417:13:UART_DMATxAbortCallback 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3463:13:UART_DMARxAbortCallback 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3509:13:UART_DMATxOnlyAbortCallback 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3537:13:UART_DMARxOnlyAbortCallback 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3563:26:UART_Transmit_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3603:26:UART_EndTransmit_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3628:26:UART_Receive_IT 56 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3731:13:UART_SetConfig 288 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo new file mode 100644 index 00000000..65c0e417 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo @@ -0,0 +1,49 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:83:19:USB_CoreInit 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:139:19:USB_SetTurnaroundTime 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:222:19:USB_EnableGlobalInt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:234:19:USB_DisableGlobalInt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:249:19:USB_SetCurrentMode 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:296:19:USB_DevInit 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:473:19:USB_FlushTxFifo 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:510:19:USB_FlushRxFifo 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:553:19:USB_SetDevSpeed 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:569:9:USB_GetDevSpeed 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:598:19:USB_ActivateEndpoint 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:636:19:USB_ActivateDedicatedEndpoint 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:675:19:USB_DeactivateEndpoint 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:722:19:USB_DeactivateDedicatedEndpoint 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:764:19:USB_EPStartXfer 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:936:19:USB_EPStopXfer 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1000:19:USB_WritePacket 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1031:7:USB_ReadPacket 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1073:19:USB_EPSetStall 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1104:19:USB_EPClearStall 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1133:19:USB_StopDevice 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1174:19:USB_SetDevAddress 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1189:19:USB_DevConnect 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1206:19:USB_DevDisconnect 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1223:10:USB_ReadInterrupts 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1239:10:USB_ReadChInterrupts 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1255:10:USB_ReadDevAllOutEpInterrupt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1271:10:USB_ReadDevAllInEpInterrupt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1289:10:USB_ReadDevOutEPInterrupt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1307:10:USB_ReadDevInEPInterrupt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1328:7:USB_ClearInterrupts 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1341:10:USB_GetMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1351:19:USB_ActivateSetup 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1373:19:USB_EP0_OutStart 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1406:26:USB_CoreReset 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1453:19:USB_HostInit 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1568:19:USB_InitFSLSPClkSel 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1598:19:USB_ResetPort 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1625:19:USB_DriveVbus 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1655:10:USB_GetHostSpeed 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1669:10:USB_GetCurrentFrame 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1700:19:USB_HC_Init 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1832:19:USB_HC_StartXfer 44 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2095:10:USB_HC_ReadInterrupt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2109:19:USB_HC_Halt 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2193:19:USB_DoPing 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2217:19:USB_StopHost 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2282:19:USB_ActivateRemoteWakeup 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2300:19:USB_DeActivateRemoteWakeup 1 diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d new file mode 100644 index 00000000..1ed2e89c --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o new file mode 100644 index 00000000..e0744966 Binary files /dev/null and b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o differ diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su new file mode 100644 index 00000000..426b6415 --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su @@ -0,0 +1,49 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:83:19:USB_CoreInit 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:139:19:USB_SetTurnaroundTime 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:222:19:USB_EnableGlobalInt 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:234:19:USB_DisableGlobalInt 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:249:19:USB_SetCurrentMode 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:296:19:USB_DevInit 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:473:19:USB_FlushTxFifo 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:510:19:USB_FlushRxFifo 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:553:19:USB_SetDevSpeed 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:569:9:USB_GetDevSpeed 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:598:19:USB_ActivateEndpoint 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:636:19:USB_ActivateDedicatedEndpoint 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:675:19:USB_DeactivateEndpoint 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:722:19:USB_DeactivateDedicatedEndpoint 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:764:19:USB_EPStartXfer 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:936:19:USB_EPStopXfer 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1000:19:USB_WritePacket 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1031:7:USB_ReadPacket 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1073:19:USB_EPSetStall 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1104:19:USB_EPClearStall 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1133:19:USB_StopDevice 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1174:19:USB_SetDevAddress 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1189:19:USB_DevConnect 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1206:19:USB_DevDisconnect 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1223:10:USB_ReadInterrupts 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1239:10:USB_ReadChInterrupts 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1255:10:USB_ReadDevAllOutEpInterrupt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1271:10:USB_ReadDevAllInEpInterrupt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1289:10:USB_ReadDevOutEPInterrupt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1307:10:USB_ReadDevInEPInterrupt 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1328:7:USB_ClearInterrupts 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1341:10:USB_GetMode 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1351:19:USB_ActivateSetup 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1373:19:USB_EP0_OutStart 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1406:26:USB_CoreReset 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1453:19:USB_HostInit 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1568:19:USB_InitFSLSPClkSel 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1598:19:USB_ResetPort 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1625:19:USB_DriveVbus 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1655:10:USB_GetHostSpeed 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1669:10:USB_GetCurrentFrame 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1700:19:USB_HC_Init 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1832:19:USB_HC_StartXfer 56 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2095:10:USB_HC_ReadInterrupt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2109:19:USB_HC_Halt 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2193:19:USB_DoPing 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2217:19:USB_StopHost 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2282:19:USB_ActivateRemoteWakeup 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2300:19:USB_DeActivateRemoteWakeup 24 static diff --git a/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 00000000..fa9e3fdc --- /dev/null +++ b/firmware/numpad/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,87 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c + +OBJS += \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + +C_DEPS += \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F4xx_HAL_Driver/Src/%.o Drivers/STM32F4xx_HAL_Driver/Src/%.su Drivers/STM32F4xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32F4xx_HAL_Driver/Src/%.c Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src + +clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src: + -$(RM) ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su + +.PHONY: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src + diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk new file mode 100644 index 00000000..397659ef --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c + +OBJS += \ +./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + +C_DEPS += \ +./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.o Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.su Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.cyclo: ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.c Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Class-2f-HID-2f-Src + +clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Class-2f-HID-2f-Src: + -$(RM) ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su + +.PHONY: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Class-2f-HID-2f-Src + diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo new file mode 100644 index 00000000..546301b3 --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo @@ -0,0 +1,10 @@ +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:304:16:USBD_HID_Init 3 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:351:16:USBD_HID_DeInit 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:382:16:USBD_HID_Setup 18 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:514:9:USBD_HID_SendReport 4 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:547:10:USBD_HID_GetPollingInterval 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:577:17:USBD_HID_GetFSCfgDesc 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:597:17:USBD_HID_GetHSCfgDesc 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:617:17:USBD_HID_GetOtherSpeedCfgDesc 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:638:16:USBD_HID_DataIn 1 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:655:17:USBD_HID_GetDeviceQualifierDesc 1 diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d new file mode 100644 index 00000000..dbb7e592 --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d @@ -0,0 +1,85 @@ +Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o: \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o new file mode 100644 index 00000000..fd892965 Binary files /dev/null and b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o differ diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su new file mode 100644 index 00000000..fcd4edcf --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su @@ -0,0 +1,10 @@ +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:304:16:USBD_HID_Init 24 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:351:16:USBD_HID_DeInit 16 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:382:16:USBD_HID_Setup 32 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:514:9:USBD_HID_SendReport 32 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:547:10:USBD_HID_GetPollingInterval 24 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:577:17:USBD_HID_GetFSCfgDesc 24 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:597:17:USBD_HID_GetHSCfgDesc 24 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:617:17:USBD_HID_GetOtherSpeedCfgDesc 24 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:638:16:USBD_HID_DataIn 16 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:655:17:USBD_HID_GetDeviceQualifierDesc 16 static diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk new file mode 100644 index 00000000..40d355c1 --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c + +OBJS += \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + +C_DEPS += \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.o Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.su Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.cyclo: ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.c Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Core-2f-Src + +clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Core-2f-Src: + -$(RM) ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su + +.PHONY: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Core-2f-Src + diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo new file mode 100644 index 00000000..b10733b0 --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo @@ -0,0 +1,24 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:92:20:USBD_Init 3 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:149:20:USBD_DeInit 2 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:202:20:USBD_RegisterClass 3 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:384:20:USBD_Start 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:400:20:USBD_Stop 2 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:440:20:USBD_RunTestMode 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:465:20:USBD_SetClassConfig 2 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:505:20:USBD_ClrClassConfig 2 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:546:20:USBD_LL_SetupStage 5 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:586:20:USBD_LL_DataOutStage 16 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:684:20:USBD_LL_DataInStage 15 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:777:20:USBD_LL_Reset 4 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:845:20:USBD_LL_SetSpeed 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:859:20:USBD_LL_Suspend 2 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:877:20:USBD_LL_Resume 2 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:893:20:USBD_LL_SOF 4 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:936:20:USBD_LL_IsoINIncomplete 4 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:962:20:USBD_LL_IsoOUTIncomplete 4 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:987:20:USBD_LL_DevConnected 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1001:20:USBD_LL_DevDisconnected 3 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1046:9:USBD_CoreFindIF 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1086:9:USBD_CoreFindEP 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1157:7:USBD_GetEpDesc 5 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1198:25:USBD_GetNextDesc 1 diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d new file mode 100644 index 00000000..f6fb1ae9 --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d @@ -0,0 +1,81 @@ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o: \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o new file mode 100644 index 00000000..dadf3675 Binary files /dev/null and b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o differ diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su new file mode 100644 index 00000000..e5b5357a --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su @@ -0,0 +1,24 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:92:20:USBD_Init 32 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:149:20:USBD_DeInit 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:202:20:USBD_RegisterClass 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:384:20:USBD_Start 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:400:20:USBD_Stop 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:440:20:USBD_RunTestMode 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:465:20:USBD_SetClassConfig 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:505:20:USBD_ClrClassConfig 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:546:20:USBD_LL_SetupStage 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:586:20:USBD_LL_DataOutStage 32 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:684:20:USBD_LL_DataInStage 32 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:777:20:USBD_LL_Reset 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:845:20:USBD_LL_SetSpeed 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:859:20:USBD_LL_Suspend 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:877:20:USBD_LL_Resume 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:893:20:USBD_LL_SOF 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:936:20:USBD_LL_IsoINIncomplete 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:962:20:USBD_LL_IsoOUTIncomplete 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:987:20:USBD_LL_DevConnected 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1001:20:USBD_LL_DevDisconnected 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1046:9:USBD_CoreFindIF 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1086:9:USBD_CoreFindEP 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1157:7:USBD_GetEpDesc 32 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1198:25:USBD_GetNextDesc 24 static diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo new file mode 100644 index 00000000..5f2e56ac --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo @@ -0,0 +1,15 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:425:26:SWAPBYTE 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:104:20:USBD_StdDevReq 12 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:167:20:USBD_StdItfReq 12 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:239:20:USBD_StdEPReq 41 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:428:13:USBD_GetDescriptor 26 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:682:13:USBD_SetAddress 6 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:723:27:USBD_SetConfig 9 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:821:13:USBD_GetConfig 5 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:855:13:USBD_GetStatus 4 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:896:13:USBD_SetFeature 3 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:922:13:USBD_ClrFeature 3 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:950:6:USBD_ParseSetupRequest 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:979:6:USBD_CtlError 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:996:6:USBD_GetString 4 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:1032:16:USBD_GetLen 2 diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d new file mode 100644 index 00000000..692469a4 --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d @@ -0,0 +1,83 @@ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o: \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o new file mode 100644 index 00000000..11a34289 Binary files /dev/null and b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o differ diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su new file mode 100644 index 00000000..dd078244 --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su @@ -0,0 +1,15 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h:425:26:SWAPBYTE 32 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:104:20:USBD_StdDevReq 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:167:20:USBD_StdItfReq 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:239:20:USBD_StdEPReq 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:428:13:USBD_GetDescriptor 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:682:13:USBD_SetAddress 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:723:27:USBD_SetConfig 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:821:13:USBD_GetConfig 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:855:13:USBD_GetStatus 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:896:13:USBD_SetFeature 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:922:13:USBD_ClrFeature 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:950:6:USBD_ParseSetupRequest 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:979:6:USBD_CtlError 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:996:6:USBD_GetString 32 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:1032:16:USBD_GetLen 24 static diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo new file mode 100644 index 00000000..b8d45878 --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo @@ -0,0 +1,7 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:86:20:USBD_CtlSendData 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:114:20:USBD_CtlContinueSendData 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:131:20:USBD_CtlPrepareRx 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:159:20:USBD_CtlContinueRx 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:173:20:USBD_CtlSendStatus 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:190:20:USBD_CtlReceiveStatus 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:208:10:USBD_GetRxCount 1 diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d new file mode 100644 index 00000000..68758366 --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d @@ -0,0 +1,81 @@ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o: \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o new file mode 100644 index 00000000..95ab3498 Binary files /dev/null and b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o differ diff --git a/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su new file mode 100644 index 00000000..0788a965 --- /dev/null +++ b/firmware/numpad/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su @@ -0,0 +1,7 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:86:20:USBD_CtlSendData 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:114:20:USBD_CtlContinueSendData 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:131:20:USBD_CtlPrepareRx 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:159:20:USBD_CtlContinueRx 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:173:20:USBD_CtlSendStatus 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:190:20:USBD_CtlReceiveStatus 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:208:10:USBD_GetRxCount 16 static diff --git a/firmware/numpad/Debug/USB_DEVICE/App/subdir.mk b/firmware/numpad/Debug/USB_DEVICE/App/subdir.mk new file mode 100644 index 00000000..e1ea6907 --- /dev/null +++ b/firmware/numpad/Debug/USB_DEVICE/App/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../USB_DEVICE/App/usb_device.c \ +../USB_DEVICE/App/usbd_desc.c + +OBJS += \ +./USB_DEVICE/App/usb_device.o \ +./USB_DEVICE/App/usbd_desc.o + +C_DEPS += \ +./USB_DEVICE/App/usb_device.d \ +./USB_DEVICE/App/usbd_desc.d + + +# Each subdirectory must supply rules for building sources it contributes +USB_DEVICE/App/%.o USB_DEVICE/App/%.su USB_DEVICE/App/%.cyclo: ../USB_DEVICE/App/%.c USB_DEVICE/App/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-USB_DEVICE-2f-App + +clean-USB_DEVICE-2f-App: + -$(RM) ./USB_DEVICE/App/usb_device.cyclo ./USB_DEVICE/App/usb_device.d ./USB_DEVICE/App/usb_device.o ./USB_DEVICE/App/usb_device.su ./USB_DEVICE/App/usbd_desc.cyclo ./USB_DEVICE/App/usbd_desc.d ./USB_DEVICE/App/usbd_desc.o ./USB_DEVICE/App/usbd_desc.su + +.PHONY: clean-USB_DEVICE-2f-App + diff --git a/firmware/numpad/Debug/USB_DEVICE/App/usb_device.cyclo b/firmware/numpad/Debug/USB_DEVICE/App/usb_device.cyclo new file mode 100644 index 00000000..ff36f216 --- /dev/null +++ b/firmware/numpad/Debug/USB_DEVICE/App/usb_device.cyclo @@ -0,0 +1 @@ +../USB_DEVICE/App/usb_device.c:63:6:MX_USB_DEVICE_Init 4 diff --git a/firmware/numpad/Debug/USB_DEVICE/App/usb_device.d b/firmware/numpad/Debug/USB_DEVICE/App/usb_device.d new file mode 100644 index 00000000..f8cd5595 --- /dev/null +++ b/firmware/numpad/Debug/USB_DEVICE/App/usb_device.d @@ -0,0 +1,90 @@ +USB_DEVICE/App/usb_device.o: ../USB_DEVICE/App/usb_device.c \ + ../USB_DEVICE/App/usb_device.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + ../USB_DEVICE/App/usbd_desc.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h +../USB_DEVICE/App/usb_device.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +../USB_DEVICE/App/usbd_desc.h: +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: diff --git a/firmware/numpad/Debug/USB_DEVICE/App/usb_device.o b/firmware/numpad/Debug/USB_DEVICE/App/usb_device.o new file mode 100644 index 00000000..61f5504a Binary files /dev/null and b/firmware/numpad/Debug/USB_DEVICE/App/usb_device.o differ diff --git a/firmware/numpad/Debug/USB_DEVICE/App/usb_device.su b/firmware/numpad/Debug/USB_DEVICE/App/usb_device.su new file mode 100644 index 00000000..e29c600d --- /dev/null +++ b/firmware/numpad/Debug/USB_DEVICE/App/usb_device.su @@ -0,0 +1 @@ +../USB_DEVICE/App/usb_device.c:63:6:MX_USB_DEVICE_Init 8 static diff --git a/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.cyclo b/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.cyclo new file mode 100644 index 00000000..e715f1f3 --- /dev/null +++ b/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.cyclo @@ -0,0 +1,10 @@ +../USB_DEVICE/App/usbd_desc.c:258:11:USBD_FS_DeviceDescriptor 1 +../USB_DEVICE/App/usbd_desc.c:271:11:USBD_FS_LangIDStrDescriptor 1 +../USB_DEVICE/App/usbd_desc.c:284:11:USBD_FS_ProductStrDescriptor 2 +../USB_DEVICE/App/usbd_desc.c:303:11:USBD_FS_ManufacturerStrDescriptor 1 +../USB_DEVICE/App/usbd_desc.c:316:11:USBD_FS_SerialStrDescriptor 1 +../USB_DEVICE/App/usbd_desc.c:336:11:USBD_FS_ConfigStrDescriptor 2 +../USB_DEVICE/App/usbd_desc.c:355:11:USBD_FS_InterfaceStrDescriptor 2 +../USB_DEVICE/App/usbd_desc.c:375:11:USBD_FS_USR_BOSDescriptor 1 +../USB_DEVICE/App/usbd_desc.c:388:13:Get_SerialNum 2 +../USB_DEVICE/App/usbd_desc.c:414:13:IntToUnicode 3 diff --git a/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.d b/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.d new file mode 100644 index 00000000..e610db0b --- /dev/null +++ b/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.d @@ -0,0 +1,84 @@ +USB_DEVICE/App/usbd_desc.o: ../USB_DEVICE/App/usbd_desc.c \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + ../USB_DEVICE/App/usbd_desc.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +../USB_DEVICE/App/usbd_desc.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: diff --git a/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.o b/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.o new file mode 100644 index 00000000..11b6d2a3 Binary files /dev/null and b/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.o differ diff --git a/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.su b/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.su new file mode 100644 index 00000000..c360c904 --- /dev/null +++ b/firmware/numpad/Debug/USB_DEVICE/App/usbd_desc.su @@ -0,0 +1,10 @@ +../USB_DEVICE/App/usbd_desc.c:258:11:USBD_FS_DeviceDescriptor 16 static +../USB_DEVICE/App/usbd_desc.c:271:11:USBD_FS_LangIDStrDescriptor 16 static +../USB_DEVICE/App/usbd_desc.c:284:11:USBD_FS_ProductStrDescriptor 16 static +../USB_DEVICE/App/usbd_desc.c:303:11:USBD_FS_ManufacturerStrDescriptor 16 static +../USB_DEVICE/App/usbd_desc.c:316:11:USBD_FS_SerialStrDescriptor 16 static +../USB_DEVICE/App/usbd_desc.c:336:11:USBD_FS_ConfigStrDescriptor 16 static +../USB_DEVICE/App/usbd_desc.c:355:11:USBD_FS_InterfaceStrDescriptor 16 static +../USB_DEVICE/App/usbd_desc.c:375:11:USBD_FS_USR_BOSDescriptor 16 static +../USB_DEVICE/App/usbd_desc.c:388:13:Get_SerialNum 24 static +../USB_DEVICE/App/usbd_desc.c:414:13:IntToUnicode 32 static diff --git a/firmware/numpad/Debug/USB_DEVICE/Target/subdir.mk b/firmware/numpad/Debug/USB_DEVICE/Target/subdir.mk new file mode 100644 index 00000000..16b6991f --- /dev/null +++ b/firmware/numpad/Debug/USB_DEVICE/Target/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../USB_DEVICE/Target/usbd_conf.c + +OBJS += \ +./USB_DEVICE/Target/usbd_conf.o + +C_DEPS += \ +./USB_DEVICE/Target/usbd_conf.d + + +# Each subdirectory must supply rules for building sources it contributes +USB_DEVICE/Target/%.o USB_DEVICE/Target/%.su USB_DEVICE/Target/%.cyclo: ../USB_DEVICE/Target/%.c USB_DEVICE/Target/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-USB_DEVICE-2f-Target + +clean-USB_DEVICE-2f-Target: + -$(RM) ./USB_DEVICE/Target/usbd_conf.cyclo ./USB_DEVICE/Target/usbd_conf.d ./USB_DEVICE/Target/usbd_conf.o ./USB_DEVICE/Target/usbd_conf.su + +.PHONY: clean-USB_DEVICE-2f-Target + diff --git a/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.cyclo b/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.cyclo new file mode 100644 index 00000000..e780cf5d --- /dev/null +++ b/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.cyclo @@ -0,0 +1,32 @@ +../USB_DEVICE/Target/usbd_conf.c:69:6:HAL_PCD_MspInit 3 +../USB_DEVICE/Target/usbd_conf.c:112:6:HAL_PCD_MspDeInit 2 +../USB_DEVICE/Target/usbd_conf.c:145:6:HAL_PCD_SetupStageCallback 1 +../USB_DEVICE/Target/usbd_conf.c:160:6:HAL_PCD_DataOutStageCallback 1 +../USB_DEVICE/Target/usbd_conf.c:175:6:HAL_PCD_DataInStageCallback 1 +../USB_DEVICE/Target/usbd_conf.c:189:6:HAL_PCD_SOFCallback 1 +../USB_DEVICE/Target/usbd_conf.c:203:6:HAL_PCD_ResetCallback 3 +../USB_DEVICE/Target/usbd_conf.c:236:6:HAL_PCD_SuspendCallback 2 +../USB_DEVICE/Target/usbd_conf.c:261:6:HAL_PCD_ResumeCallback 1 +../USB_DEVICE/Target/usbd_conf.c:279:6:HAL_PCD_ISOOUTIncompleteCallback 1 +../USB_DEVICE/Target/usbd_conf.c:294:6:HAL_PCD_ISOINIncompleteCallback 1 +../USB_DEVICE/Target/usbd_conf.c:308:6:HAL_PCD_ConnectCallback 1 +../USB_DEVICE/Target/usbd_conf.c:322:6:HAL_PCD_DisconnectCallback 1 +../USB_DEVICE/Target/usbd_conf.c:337:20:USBD_LL_Init 3 +../USB_DEVICE/Target/usbd_conf.c:387:20:USBD_LL_DeInit 1 +../USB_DEVICE/Target/usbd_conf.c:404:20:USBD_LL_Start 1 +../USB_DEVICE/Target/usbd_conf.c:421:20:USBD_LL_Stop 1 +../USB_DEVICE/Target/usbd_conf.c:441:20:USBD_LL_OpenEP 1 +../USB_DEVICE/Target/usbd_conf.c:459:20:USBD_LL_CloseEP 1 +../USB_DEVICE/Target/usbd_conf.c:477:20:USBD_LL_FlushEP 1 +../USB_DEVICE/Target/usbd_conf.c:495:20:USBD_LL_StallEP 1 +../USB_DEVICE/Target/usbd_conf.c:513:20:USBD_LL_ClearStallEP 1 +../USB_DEVICE/Target/usbd_conf.c:531:9:USBD_LL_IsStallEP 2 +../USB_DEVICE/Target/usbd_conf.c:551:20:USBD_LL_SetUSBAddress 1 +../USB_DEVICE/Target/usbd_conf.c:571:20:USBD_LL_Transmit 1 +../USB_DEVICE/Target/usbd_conf.c:591:20:USBD_LL_PrepareReceive 1 +../USB_DEVICE/Target/usbd_conf.c:609:10:USBD_LL_GetRxDataSize 1 +../USB_DEVICE/Target/usbd_conf.c:620:6:HAL_PCDEx_LPM_Callback 5 +../USB_DEVICE/Target/usbd_conf.c:671:7:USBD_static_malloc 1 +../USB_DEVICE/Target/usbd_conf.c:682:6:USBD_static_free 1 +../USB_DEVICE/Target/usbd_conf.c:692:6:USBD_LL_Delay 1 +../USB_DEVICE/Target/usbd_conf.c:702:20:USBD_Get_USB_Status 5 diff --git a/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.d b/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.d new file mode 100644 index 00000000..5fb644c5 --- /dev/null +++ b/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.d @@ -0,0 +1,86 @@ +USB_DEVICE/Target/usbd_conf.o: ../USB_DEVICE/Target/usbd_conf.c \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: diff --git a/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.o b/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.o new file mode 100644 index 00000000..177f1296 Binary files /dev/null and b/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.o differ diff --git a/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.su b/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.su new file mode 100644 index 00000000..4d1df5c7 --- /dev/null +++ b/firmware/numpad/Debug/USB_DEVICE/Target/usbd_conf.su @@ -0,0 +1,32 @@ +../USB_DEVICE/Target/usbd_conf.c:69:6:HAL_PCD_MspInit 136 static +../USB_DEVICE/Target/usbd_conf.c:112:6:HAL_PCD_MspDeInit 16 static +../USB_DEVICE/Target/usbd_conf.c:145:6:HAL_PCD_SetupStageCallback 16 static +../USB_DEVICE/Target/usbd_conf.c:160:6:HAL_PCD_DataOutStageCallback 16 static +../USB_DEVICE/Target/usbd_conf.c:175:6:HAL_PCD_DataInStageCallback 16 static +../USB_DEVICE/Target/usbd_conf.c:189:6:HAL_PCD_SOFCallback 16 static +../USB_DEVICE/Target/usbd_conf.c:203:6:HAL_PCD_ResetCallback 24 static +../USB_DEVICE/Target/usbd_conf.c:236:6:HAL_PCD_SuspendCallback 16 static +../USB_DEVICE/Target/usbd_conf.c:261:6:HAL_PCD_ResumeCallback 16 static +../USB_DEVICE/Target/usbd_conf.c:279:6:HAL_PCD_ISOOUTIncompleteCallback 16 static +../USB_DEVICE/Target/usbd_conf.c:294:6:HAL_PCD_ISOINIncompleteCallback 16 static +../USB_DEVICE/Target/usbd_conf.c:308:6:HAL_PCD_ConnectCallback 16 static +../USB_DEVICE/Target/usbd_conf.c:322:6:HAL_PCD_DisconnectCallback 16 static +../USB_DEVICE/Target/usbd_conf.c:337:20:USBD_LL_Init 16 static +../USB_DEVICE/Target/usbd_conf.c:387:20:USBD_LL_DeInit 24 static +../USB_DEVICE/Target/usbd_conf.c:404:20:USBD_LL_Start 24 static +../USB_DEVICE/Target/usbd_conf.c:421:20:USBD_LL_Stop 24 static +../USB_DEVICE/Target/usbd_conf.c:441:20:USBD_LL_OpenEP 24 static +../USB_DEVICE/Target/usbd_conf.c:459:20:USBD_LL_CloseEP 24 static +../USB_DEVICE/Target/usbd_conf.c:477:20:USBD_LL_FlushEP 24 static +../USB_DEVICE/Target/usbd_conf.c:495:20:USBD_LL_StallEP 24 static +../USB_DEVICE/Target/usbd_conf.c:513:20:USBD_LL_ClearStallEP 24 static +../USB_DEVICE/Target/usbd_conf.c:531:9:USBD_LL_IsStallEP 24 static +../USB_DEVICE/Target/usbd_conf.c:551:20:USBD_LL_SetUSBAddress 24 static +../USB_DEVICE/Target/usbd_conf.c:571:20:USBD_LL_Transmit 32 static +../USB_DEVICE/Target/usbd_conf.c:591:20:USBD_LL_PrepareReceive 32 static +../USB_DEVICE/Target/usbd_conf.c:609:10:USBD_LL_GetRxDataSize 16 static +../USB_DEVICE/Target/usbd_conf.c:620:6:HAL_PCDEx_LPM_Callback 16 static +../USB_DEVICE/Target/usbd_conf.c:671:7:USBD_static_malloc 16 static +../USB_DEVICE/Target/usbd_conf.c:682:6:USBD_static_free 16 static +../USB_DEVICE/Target/usbd_conf.c:692:6:USBD_LL_Delay 16 static +../USB_DEVICE/Target/usbd_conf.c:702:20:USBD_Get_USB_Status 24 static diff --git a/firmware/modularkbd/Debug/makefile b/firmware/numpad/Debug/makefile similarity index 100% rename from firmware/modularkbd/Debug/makefile rename to firmware/numpad/Debug/makefile diff --git a/firmware/modularkbd/Debug/modularkbd.elf b/firmware/numpad/Debug/modularkbd.elf similarity index 100% rename from firmware/modularkbd/Debug/modularkbd.elf rename to firmware/numpad/Debug/modularkbd.elf diff --git a/firmware/modularkbd/Debug/modularkbd.list b/firmware/numpad/Debug/modularkbd.list similarity index 100% rename from firmware/modularkbd/Debug/modularkbd.list rename to firmware/numpad/Debug/modularkbd.list diff --git a/firmware/modularkbd/Debug/modularkbd.map b/firmware/numpad/Debug/modularkbd.map similarity index 100% rename from firmware/modularkbd/Debug/modularkbd.map rename to firmware/numpad/Debug/modularkbd.map diff --git a/firmware/modularkbd/Debug/objects.list b/firmware/numpad/Debug/objects.list similarity index 100% rename from firmware/modularkbd/Debug/objects.list rename to firmware/numpad/Debug/objects.list diff --git a/firmware/numpad/Debug/objects.mk b/firmware/numpad/Debug/objects.mk new file mode 100644 index 00000000..b471e98e --- /dev/null +++ b/firmware/numpad/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/firmware/numpad/Debug/sources.mk b/firmware/numpad/Debug/sources.mk new file mode 100644 index 00000000..083ab34c --- /dev/null +++ b/firmware/numpad/Debug/sources.mk @@ -0,0 +1,32 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +CYCLO_FILES := +SIZE_OUTPUT := +OBJDUMP_LIST := +SU_FILES := +EXECUTABLES := +OBJS := +MAP_FILES := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/STM32F4xx_HAL_Driver/Src \ +Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src \ +Middlewares/ST/STM32_USB_Device_Library/Core/Src \ +USB_DEVICE/App \ +USB_DEVICE/Target \ + diff --git a/firmware/numpad/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h b/firmware/numpad/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h new file mode 100644 index 00000000..0157f168 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h @@ -0,0 +1,15985 @@ +/** + ****************************************************************************** + * @file stm32f446xx.h + * @author MCD Application Team + * @brief CMSIS STM32F446xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - peripherals registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f446xx + * @{ + */ + +#ifndef __STM32F446xx_H +#define __STM32F446xx_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */ + CEC_IRQn = 93, /*!< CEC global Interrupt */ + SPDIF_RX_IRQn = 94, /*!< SPDIF-RX global Interrupt */ + FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */ + FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +} CEC_TypeDef; +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */ + __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */ +} FMPI2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ + __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief SPDIFRX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + uint16_t RESERVED0; /*!< Reserved, 0x06 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + uint16_t RESERVED1; /*!< Reserved, 0x0E */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint16_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + uint32_t Reserved; /*!< Reserved 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */ +#define SRAM1_BASE 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */ +#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FMC_R_BASE 0xA0000000UL /*!< FMC registers base address */ +#define QSPI_R_BASE 0xA0001000UL /*!< QuadSPI registers base address */ +#define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END 0x0807FFFFUL /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL) +#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL) +/* Legacy define */ +#define ADC_BASE ADC123_COMMON_BASE +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL) + +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000UL +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000UL +#define USB_OTG_FS_PERIPH_BASE 0x50000000UL + +#define USB_OTG_GLOBAL_BASE 0x000UL +#define USB_OTG_DEVICE_BASE 0x800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL +#define USB_OTG_EP_REG_SIZE 0x20UL +#define USB_OTG_HOST_BASE 0x400UL +#define USB_OTG_HOST_PORT_BASE 0x440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL +#define USB_OTG_PCGCCTL_BASE 0xE00UL +#define USB_OTG_FIFO_BASE 0x1000UL +#define USB_OTG_FIFO_SIZE 0x1000UL + +#define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0UL /*!< Package size register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) +/* Legacy define */ +#define ADC ADC123_COMMON +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) + */ +#define ADC_MULTIMODE_SUPPORT /*!> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/cmsis_armcc.h b/firmware/numpad/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 00000000..a955d471 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/cmsis_armclang.h b/firmware/numpad/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 00000000..69114177 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/firmware/numpad/Drivers/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000..1e255d59 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/cmsis_compiler.h b/firmware/numpad/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 00000000..adbf296f --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/firmware/numpad/Drivers/CMSIS/Include/cmsis_gcc.h b/firmware/numpad/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 00000000..67bda4ef --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/cmsis_iccarm.h b/firmware/numpad/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 00000000..65b824b0 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/cmsis_version.h b/firmware/numpad/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 00000000..8b4765f1 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_armv81mml.h b/firmware/numpad/Drivers/CMSIS/Include/core_armv81mml.h new file mode 100644 index 00000000..94128a1a --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_armv8mbl.h b/firmware/numpad/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 00000000..932d3d18 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_armv8mml.h b/firmware/numpad/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 00000000..c119fbf2 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_cm0.h b/firmware/numpad/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 00000000..6441ff34 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_cm0plus.h b/firmware/numpad/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 00000000..4e7179a6 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_cm1.h b/firmware/numpad/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 00000000..76b45697 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_cm23.h b/firmware/numpad/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 00000000..55fff995 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_cm3.h b/firmware/numpad/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 00000000..74fb87e5 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_cm33.h b/firmware/numpad/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 00000000..18a2e6fb --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_cm35p.h b/firmware/numpad/Drivers/CMSIS/Include/core_cm35p.h new file mode 100644 index 00000000..3843d954 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_cm4.h b/firmware/numpad/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 00000000..e21cd149 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_cm55.h b/firmware/numpad/Drivers/CMSIS/Include/core_cm55.h new file mode 100644 index 00000000..faa30ce3 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_cm55.h @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_cm7.h b/firmware/numpad/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 00000000..010506e9 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_cm85.h b/firmware/numpad/Drivers/CMSIS/Include/core_cm85.h new file mode 100644 index 00000000..60463111 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_cm85.h @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_sc000.h b/firmware/numpad/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 00000000..dbc755ff --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_sc300.h b/firmware/numpad/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 00000000..d6662103 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/core_starmc1.h b/firmware/numpad/Drivers/CMSIS/Include/core_starmc1.h new file mode 100644 index 00000000..d86c8d38 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/mpu_armv7.h b/firmware/numpad/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 00000000..d9eedf81 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/firmware/numpad/Drivers/CMSIS/Include/mpu_armv8.h b/firmware/numpad/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 00000000..3de16efc --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/firmware/numpad/Drivers/CMSIS/Include/pac_armv81.h b/firmware/numpad/Drivers/CMSIS/Include/pac_armv81.h new file mode 100644 index 00000000..854b60a2 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/firmware/numpad/Drivers/CMSIS/Include/pmu_armv8.h b/firmware/numpad/Drivers/CMSIS/Include/pmu_armv8.h new file mode 100644 index 00000000..f8f3d893 --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/firmware/numpad/Drivers/CMSIS/Include/tz_context.h b/firmware/numpad/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 00000000..0d09749f --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/firmware/numpad/Drivers/CMSIS/LICENSE.txt b/firmware/numpad/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 00000000..8dada3ed --- /dev/null +++ b/firmware/numpad/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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/dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,4422 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) +#define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) +#endif /* STM32F3 */ + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) || defined(STM32WB) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 || STM32WB */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || \ + defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h new file mode 100644 index 00000000..f7eb847b --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h @@ -0,0 +1,297 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_H +#define __STM32F4xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_conf.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + +#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + +/** @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE)) + +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\ + }while(0); + +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\ + }while(0); + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ + }while(0); +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ + }while(0); + +/** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\ + }while(0); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable + * @{ + */ +/** @brief SYSCFG Break Lockup lock + * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ + }while(0) +/** + * @} + */ + +/** @defgroup PVD_Lock_Enable PVD Lock + * @{ + */ +/** @brief SYSCFG Break PVD lock + * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions + * @{ + */ +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and Configuration functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +void HAL_EnableCompensationCell(void); +void HAL_DisableCompensationCell(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +void HAL_EnableMemorySwappingBank(void); +void HAL_DisableMemorySwappingBank(void); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_H */ + + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h new file mode 100644 index 00000000..76909305 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h @@ -0,0 +1,410 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CORTEX_H +#define __STM32F4xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk +#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) + +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +void HAL_CORTEX_ClearEvent(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1U) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CORTEX_H */ + + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h new file mode 100644 index 00000000..1df0d7d0 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_DEF +#define __STM32F4xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) + /* Reserved for future use */ + #error "USE_RTOS should be 0 in the current HAL release" +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif + #ifndef __packed + #define __packed __attribute__((packed)) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler V5*/ +#define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F4xx_HAL_DEF */ + + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h new file mode 100644 index 00000000..7ff3836b --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h @@ -0,0 +1,802 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_DMA_H +#define __STM32F4xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel used for the specified stream. + This parameter can be a value of @ref DMA_Channel_selection */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_Priority_level */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_FIFO_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_FIFO_threshold_level */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ + HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ + HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ + HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Stream_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ + + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ + + uint32_t StreamIndex; /*!< DMA Stream Index */ + +}DMA_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @brief DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ +#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Channel_selection DMA Channel selection + * @brief DMA channel selection + * @{ + */ +#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ +#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ +#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ +#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ +#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ +#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ +#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ +#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ +#if defined (DMA_SxCR_CHSEL_3) +#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ +#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ +#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */ +#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */ +#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */ +#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */ +#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */ +#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */ +#endif /* DMA_SxCR_CHSEL_3 */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @brief DMA data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @brief DMA peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @brief DMA memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @brief DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ +#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @brief DMA priority levels + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode + * @brief DMA FIFO direct mode + * @{ + */ +#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level + * @brief DMA FIFO level + * @{ + */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ +#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ +#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_Memory_burst DMA Memory burst + * @brief DMA memory burst + * @{ + */ +#define DMA_MBURST_SINGLE 0x00000000U +#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) +#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) +#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_burst DMA Peripheral burst + * @brief DMA peripheral burst + * @{ + */ +#define DMA_PBURST_SINGLE 0x00000000U +#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) +#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) +#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @brief DMA interrupts definition + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) +#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) +#define DMA_IT_FE 0x00000080U +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @brief DMA flag definitions + * @{ + */ +#define DMA_FLAG_FEIF0_4 0x00000001U +#define DMA_FLAG_DMEIF0_4 0x00000004U +#define DMA_FLAG_TEIF0_4 0x00000008U +#define DMA_FLAG_HTIF0_4 0x00000010U +#define DMA_FLAG_TCIF0_4 0x00000020U +#define DMA_FLAG_FEIF1_5 0x00000040U +#define DMA_FLAG_DMEIF1_5 0x00000100U +#define DMA_FLAG_TEIF1_5 0x00000200U +#define DMA_FLAG_HTIF1_5 0x00000400U +#define DMA_FLAG_TCIF1_5 0x00000800U +#define DMA_FLAG_FEIF2_6 0x00010000U +#define DMA_FLAG_DMEIF2_6 0x00040000U +#define DMA_FLAG_TEIF2_6 0x00080000U +#define DMA_FLAG_HTIF2_6 0x00100000U +#define DMA_FLAG_TCIF2_6 0x00200000U +#define DMA_FLAG_FEIF3_7 0x00400000U +#define DMA_FLAG_DMEIF3_7 0x01000000U +#define DMA_FLAG_TEIF3_7 0x02000000U +#define DMA_FLAG_HTIF3_7 0x04000000U +#define DMA_FLAG_TCIF3_7 0x08000000U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset DMA handle state + * @param __HANDLE__ specifies the DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Return the current DMA Stream FIFO filled level. + * @param __HANDLE__ DMA handle + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) + +/** + * @brief Enable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) + +/** + * @brief Disable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) + +/* Interrupt & Flag management */ + +/** + * @brief Return the current DMA Stream transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + DMA_FLAG_TCIF3_7) + +/** + * @brief Return the current DMA Stream half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + DMA_FLAG_HTIF3_7) + +/** + * @brief Return the current DMA Stream transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + DMA_FLAG_TEIF3_7) + +/** + * @brief Return the current DMA Stream FIFO error flag. + * @param __HANDLE__ DMA handle + * @retval The specified FIFO error flag index. + */ +#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ + DMA_FLAG_FEIF3_7) + +/** + * @brief Return the current DMA Stream direct mode error flag. + * @param __HANDLE__ DMA handle + * @retval The specified direct mode error flag index. + */ +#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ + DMA_FLAG_DMEIF3_7) + +/** + * @brief Get the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) + +/** + * @brief Clear the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) + +/** + * @brief Enable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval The state of DMA_IT. + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ + ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ + ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) + +/** + * @brief Writes the number of data units to be transferred on the DMA Stream. + * @param __HANDLE__ DMA handle + * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param __HANDLE__ DMA handle + * + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) + + +/* Include DMA HAL Extension module */ +#include "stm32f4xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ +/* Private Constants -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA private defines and constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA private macros + * @{ + */ +#if defined (DMA_SxCR_CHSEL_3) +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7) || \ + ((CHANNEL) == DMA_CHANNEL_8) || \ + ((CHANNEL) == DMA_CHANNEL_9) || \ + ((CHANNEL) == DMA_CHANNEL_10)|| \ + ((CHANNEL) == DMA_CHANNEL_11)|| \ + ((CHANNEL) == DMA_CHANNEL_12)|| \ + ((CHANNEL) == DMA_CHANNEL_13)|| \ + ((CHANNEL) == DMA_CHANNEL_14)|| \ + ((CHANNEL) == DMA_CHANNEL_15)) +#else +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7)) +#endif /* DMA_SxCR_CHSEL_3 */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR) || \ + ((MODE) == DMA_PFCTRL)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ + ((STATE) == DMA_FIFOMODE_ENABLE)) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ + ((BURST) == DMA_MBURST_INC4) || \ + ((BURST) == DMA_MBURST_INC8) || \ + ((BURST) == DMA_MBURST_INC16)) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ + ((BURST) == DMA_PBURST_INC4) || \ + ((BURST) == DMA_PBURST_INC8) || \ + ((BURST) == DMA_PBURST_INC16)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_DMA_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h new file mode 100644 index 00000000..9858c741 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h @@ -0,0 +1,102 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_DMA_EX_H +#define __STM32F4xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief HAL DMA Memory definition + */ +typedef enum +{ + MEMORY0 = 0x00U, /*!< Memory 0 */ + MEMORY1 = 0x01U /*!< Memory 1 */ +}HAL_DMA_MemoryTypeDef; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); + +/** + * @} + */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_HAL_DMA_EX_H*/ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h new file mode 100644 index 00000000..b18a2287 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h @@ -0,0 +1,366 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS.Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32f4xx_HAL_EXTI_H +#define STM32f4xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#if defined(EXTI_IMR_IM18) +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#else +#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM18 */ +#if defined(EXTI_IMR_IM19) +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#else +#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM19 */ +#if defined(EXTI_IMR_IM20) +#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#else +#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM20 */ +#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ +#if defined(EXTI_IMR_IM23) +#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */ +#endif /* EXTI_IMR_IM23 */ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ + +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#if defined (GPIOD) +#define EXTI_GPIOD 0x00000003u +#endif /* GPIOD */ +#if defined (GPIOE) +#define EXTI_GPIOE 0x00000004u +#endif /* GPIOE */ +#if defined (GPIOF) +#define EXTI_GPIOF 0x00000005u +#endif /* GPIOF */ +#if defined (GPIOG) +#define EXTI_GPIOG 0x00000006u +#endif /* GPIOG */ +#if defined (GPIOH) +#define EXTI_GPIOH 0x00000007u +#endif /* GPIOH */ +#if defined (GPIOI) +#define EXTI_GPIOI 0x00000008u +#endif /* GPIOI */ +#if defined (GPIOJ) +#define EXTI_GPIOJ 0x00000009u +#endif /* GPIOJ */ +#if defined (GPIOK) +#define EXTI_GPIOK 0x0000000Au +#endif /* GPIOK */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR_IM23) +#define EXTI_LINE_NB 24UL +#else +#define EXTI_LINE_NB 23UL +#endif /* EXTI_IMR_IM23 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) + +#if !defined (GPIOD) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOF) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOI) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOJ) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#endif /* GPIOD */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32f4xx_HAL_EXTI_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h new file mode 100644 index 00000000..41f77d28 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h @@ -0,0 +1,425 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_FLASH_H +#define __STM32F4xx_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_SECTERASE, + FLASH_PROC_MASSERASE, + FLASH_PROC_PROGRAM +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/ + + __IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/ + + __IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/ + + __IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/ + + __IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/ + + __IO uint32_t Address; /*Internal variable to save address selected for program*/ + + HAL_LockTypeDef Lock; /* FLASH locking object */ + + __IO uint32_t ErrorCode; /* FLASH error code */ + +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ +/** @defgroup FLASH_Error_Code FLASH Error Code + * @brief FLASH Error Code + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_FLASH_ERROR_RD 0x00000001U /*!< Read Protection error */ +#define HAL_FLASH_ERROR_PGS 0x00000002U /*!< Programming Sequence error */ +#define HAL_FLASH_ERROR_PGP 0x00000004U /*!< Programming Parallelism error */ +#define HAL_FLASH_ERROR_PGA 0x00000008U /*!< Programming Alignment error */ +#define HAL_FLASH_ERROR_WRP 0x00000010U /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPERATION 0x00000020U /*!< Operation Error */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_BYTE 0x00000000U /*!< Program byte (8-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_HALFWORD 0x00000001U /*!< Program a half-word (16-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_WORD 0x00000002U /*!< Program a word (32-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00000003U /*!< Program a double word (64-bit) at a specified address */ +/** + * @} + */ + +/** @defgroup FLASH_Flag_definition FLASH Flag definition + * @brief Flag definition + * @{ + */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */ +#if defined(FLASH_SR_RDERR) +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read Protection error flag (PCROP) */ +#endif /* FLASH_SR_RDERR */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */ +/** + * @} + */ + +/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE 0x00000000U +#define FLASH_PSIZE_HALF_WORD 0x00000100U +#define FLASH_PSIZE_WORD 0x00000200U +#define FLASH_PSIZE_DOUBLE_WORD 0x00000300U +#define CR_PSIZE_MASK 0xFFFFFCFFU +/** + * @} + */ + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define RDP_KEY ((uint16_t)0x00A5) +#define FLASH_KEY1 0x45670123U +#define FLASH_KEY2 0xCDEF89ABU +#define FLASH_OPT_KEY1 0x08192A3BU +#define FLASH_OPT_KEY2 0x4C5D6E7FU +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) + +/** + * @brief Enable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN) + +/** + * @brief Disable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN)) + +/** + * @brief Enable the FLASH data cache. + * @retval none + */ +#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN) + +/** + * @brief Disable the FLASH data cache. + * @retval none + */ +#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN)) + +/** + * @brief Resets the FLASH instruction Cache. + * @note This function must be used only when the Instruction Cache is disabled. + * @retval None + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \ + FLASH->ACR &= ~FLASH_ACR_ICRST; \ + }while(0U) + +/** + * @brief Resets the FLASH data Cache. + * @note This function must be used only when the data Cache is disabled. + * @retval None + */ +#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \ + FLASH->ACR &= ~FLASH_ACR_DCRST; \ + }while(0U) +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flags to check. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) + +/** + * @brief Clear the specified FLASH flags. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) + * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32f4xx_hal_flash_ex.h" +#include "stm32f4xx_hal_flash_ramfunc.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* Program operation functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +uint32_t HAL_FLASH_GetError(void); +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ + +/** + * @brief ACR register byte 0 (Bits[7:0]) base address + */ +#define ACR_BYTE0_ADDRESS 0x40023C00U +/** + * @brief OPTCR register byte 0 (Bits[7:0]) base address + */ +#define OPTCR_BYTE0_ADDRESS 0x40023C14U +/** + * @brief OPTCR register byte 1 (Bits[15:8]) base address + */ +#define OPTCR_BYTE1_ADDRESS 0x40023C15U +/** + * @brief OPTCR register byte 2 (Bits[23:16]) base address + */ +#define OPTCR_BYTE2_ADDRESS 0x40023C16U +/** + * @brief OPTCR register byte 3 (Bits[31:24]) base address + */ +#define OPTCR_BYTE3_ADDRESS 0x40023C17U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters + * @{ + */ +#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_FLASH_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h new file mode 100644 index 00000000..5fa89db5 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h @@ -0,0 +1,1063 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_FLASH_EX_H +#define __STM32F4xx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or sector Erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled + This parameter must be a value of @ref FLASHEx_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism + This parameter must be a value of @ref FLASHEx_Voltage_Range */ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ + + uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t RDPLevel; /*!< Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint32_t BORLevel; /*!< Set the BOR Level. + This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ + + uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH Advanced Option Bytes Program structure definition + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured for extension. + This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */ + + uint32_t PCROPState; /*!< PCROP activation or deactivation. + This parameter can be a value of @ref FLASHEx_PCROP_State */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + uint16_t Sectors; /*!< specifies the sector(s) set for PCROP. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\ + STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ + + uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ + + uint8_t BootConfig; /*!< Specifies Option bytes for boot config. + This parameter can be a value of @ref FLASHEx_Dual_Boot */ + +#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +} FLASH_AdvOBProgramInitTypeDef; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || + STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_SECTORS 0x00000000U /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE 0x00000001U /*!< Flash Mass erase activation */ +/** + * @} + */ + +/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range + * @{ + */ +#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Device operating range: 1.8V to 2.1V */ +#define FLASH_VOLTAGE_RANGE_2 0x00000001U /*!< Device operating range: 2.1V to 2.7V */ +#define FLASH_VOLTAGE_RANGE_3 0x00000002U /*!< Device operating range: 2.7V to 3.6V */ +#define FLASH_VOLTAGE_RANGE_4 0x00000003U /*!< Device operating range: 2.7V to 3.6V + External Vpp */ +/** + * @} + */ + +/** @defgroup FLASHEx_WRP_State FLASH WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Type FLASH Option Type + * @{ + */ +#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ +#define OPTIONBYTE_BOR 0x00000008U /*!< BOR option byte configuration */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 ((uint8_t)0xAA) +#define OB_RDP_LEVEL_1 ((uint8_t)0x55) +#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 + it s no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog + * @{ + */ +#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP + * @{ + */ +#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +/** + * @} + */ + + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY + * @{ + */ +#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +/** + * @} + */ + +/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level + * @{ + */ +#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +/** + * @} + */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup FLASHEx_PCROP_State FLASH PCROP State + * @{ + */ +#define OB_PCROP_STATE_DISABLE 0x00000000U /*!< Disable PCROP */ +#define OB_PCROP_STATE_ENABLE 0x00000001U /*!< Enable PCROP */ +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define OPTIONBYTE_PCROP 0x00000001U /*!< PCROP option byte configuration */ +#define OPTIONBYTE_BOOTCONFIG 0x00000002U /*!< BOOTConfig option byte configuration */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +#define OPTIONBYTE_PCROP 0x00000001U /*!= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ + (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END))) + +#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F401xC) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xC */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ + defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F401xC) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xC */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ + defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASH Private Functions + * @{ + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); +void FLASH_FlushCaches(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_FLASH_EX_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h new file mode 100644 index 00000000..2112e747 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h @@ -0,0 +1,76 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ramfunc.h + * @author MCD Application Team + * @brief Header file of FLASH RAMFUNC driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_FLASH_RAMFUNC_H +#define __STM32F4xx_FLASH_RAMFUNC_H + +#ifdef __cplusplus +extern "C" { +#endif +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH_RAMFUNC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_RAMFUNC_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 + * @{ + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_FLASH_RAMFUNC_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h new file mode 100644 index 00000000..5f3d749e --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h @@ -0,0 +1,325 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_GPIO_H +#define __STM32F4xx_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_Alternate_function_selection */ +}GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0, + GPIO_PIN_SET +}GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ + +/** + * @} + */ + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */ +/** + * @} + */ + + /** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32f4xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20U +#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_GPIO_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h new file mode 100644 index 00000000..5e0b7cc6 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h @@ -0,0 +1,1590 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_GPIO_EX_H +#define __STM32F4xx_HAL_GPIO_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection + * @{ + */ + +/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/ +#if defined(STM32F429xx) || defined(STM32F439xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F429xx || STM32F439xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F427xx/STM32F437xx------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +/** @brief GPIO_Legacy + */ +#define GPIO_AF5_I2S3ext GPIO_AF5_SPI3 /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F427xx || STM32F437xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F407xx/STM32F417xx------------------*/ +#if defined(STM32F407xx) || defined(STM32F417xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F407xx || STM32F417xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F405xx/STM32F415xx------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F405xx || STM32F415xx */ + +/*----------------------------------------------------------------------------*/ + +/*---------------------------------------- STM32F401xx------------------------*/ +#if defined(STM32F401xC) || defined(STM32F401xE) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ + + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F401xC || STM32F401xE */ +/*----------------------------------------------------------------------------*/ + +/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ +#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ +#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ +#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +/*----------------------------------------------------------------------------*/ + +/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_DFSDM2 ((uint8_t)0x03) /* DFSDM2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_SAI1 ((uint8_t)0x07) /* SAI1 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ +#define GPIO_AF7_DFSDM2 ((uint8_t)0x07) /* DFSDM2 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ +#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_SAI1 ((uint8_t)0x0A) /* SAI1 Alternate Function mapping */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_DFSDM2 ((uint8_t)0x0A) /* DFSDM2 Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ +#define GPIO_AF10_FSMC ((uint8_t)0x0A) /* FSMC Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_UART4 ((uint8_t)0x0B) /* UART4 Alternate Function mapping */ +#define GPIO_AF11_UART5 ((uint8_t)0x0B) /* UART5 Alternate Function mapping */ +#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */ +#define GPIO_AF11_UART10 ((uint8_t)0x0B) /* UART10 Alternate Function mapping */ +#define GPIO_AF11_CAN3 ((uint8_t)0x0B) /* CAN3 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_RNG ((uint8_t)0x0E) /* RNG Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F413xx || STM32F423xx */ + +/*---------------------------------------- STM32F411xx------------------------*/ +#if defined(STM32F411xE) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F411xE */ + +/*---------------------------------------- STM32F410xx------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#if defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#endif /* STM32F410Cx || STM32F410Rx */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ +#if defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#endif /* STM32F410Cx || STM32F410Rx */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/*---------------------------------------- STM32F446xx -----------------------*/ +#if defined(STM32F446xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ +#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIFRX Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPDIFRX Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#endif /* STM32F446xx */ +/*----------------------------------------------------------------------------*/ + +/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions + * @{ + */ +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Constants GPIO Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Macros GPIO Private Macros + * @{ + */ +/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index + * @{ + */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U :\ + ((__GPIOx__) == (GPIOI))? 8U :\ + ((__GPIOx__) == (GPIOJ))? 9U : 10U) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U : 7U) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 7U) +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + +#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U : 7U) +#endif /* STM32F446xx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 7U) +#endif /* STM32F412Vx */ +#if defined(STM32F412Rx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U : 7U) +#endif /* STM32F412Rx */ +#if defined(STM32F412Cx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U : 7U) +#endif /* STM32F412Cx */ + +/** + * @} + */ + +/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function + * @{ + */ +/*------------------------- STM32F429xx/STM32F439xx---------------------------*/ +#if defined(STM32F429xx) || defined(STM32F439xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF14_LTDC)) + +#endif /* STM32F429xx || STM32F439xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F427xx/STM32F437xx------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1)) + +#endif /* STM32F427xx || STM32F437xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F407xx/STM32F417xx------------------*/ +#if defined(STM32F407xx) || defined(STM32F417xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT)) + +#endif /* STM32F407xx || STM32F417xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F405xx/STM32F415xx------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \ + ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT)) + +#endif /* STM32F405xx || STM32F415xx */ + +/*----------------------------------------------------------------------------*/ + +/*---------------------------------------- STM32F401xx------------------------*/ +#if defined(STM32F401xC) || defined(STM32F401xE) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF12_SDIO) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM9) || \ + ((AF) == GPIO_AF3_TIM10) || ((AF) == GPIO_AF3_TIM11) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF7_USART1) || \ + ((AF) == GPIO_AF7_USART2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF15_EVENTOUT)) +#endif /* STM32F401xC || STM32F401xE */ +/*----------------------------------------------------------------------------*/ +/*---------------------------------------- STM32F410xx------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_GPIO_AF(AF) (((AF) < 10U) || ((AF) == 15U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/*---------------------------------------- STM32F411xx------------------------*/ +#if defined(STM32F411xE) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \ + ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI4) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF6_SPI5) || ((AF) == GPIO_AF7_SPI3) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT)) + +#endif /* STM32F411xE */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------- STM32F446xx ----------------*/ +#if defined(STM32F446xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI2) || \ + ((AF) == GPIO_AF6_SPI4) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPI2) || ((AF) == GPIO_AF7_SPI3) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF9_QSPI) || \ + ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QSPI)) + +#endif /* STM32F446xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------------------------- STM32F469xx/STM32F479xx --------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI) || \ + ((AF) == GPIO_AF9_QSPI) || ((AF) == GPIO_AF10_QSPI)) + +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +/*----------------------------------------------------------------------------*/ + +/*------------------STM32F413xx/STM32F423xx-----------------------------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 13U)) +#endif /* STM32F413xx || STM32F423xx */ +/*----------------------------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_GPIO_EX_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h new file mode 100644 index 00000000..b37126e3 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h @@ -0,0 +1,741 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_H +#define __STM32F4xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_general_call_addressing_mode */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_nostretch_mode */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : Abort (Abort user request on going) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called) + * b4 (not used) + * x : Should be set to 0 + * b3 + * 0 : Ready or Busy (No Listen mode ongoing) + * 1 : Listen (Peripheral in Address Listen Mode) + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ +#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ +#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ +#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ +#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */ +#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +typedef struct __I2C_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C transfer options */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode + context for internal usage */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + + __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ + + __IO uint32_t EventCount; /*!< I2C Event counter */ + + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode + * @{ + */ +#define I2C_DUTYCYCLE_2 0x00000000U +#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY +/** + * @} + */ + +/** @defgroup I2C_addressing_mode I2C addressing mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT 0x00004000U +#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) +/** + * @} + */ + +/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE 0x00000000U +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL +/** + * @} + */ + +/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE 0x00000000U +#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC +/** + * @} + */ + +/** @defgroup I2C_nostretch_mode I2C nostretch mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE 0x00000000U +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT 0x00000001U +#define I2C_MEMADD_SIZE_16BIT 0x00000010U +/** + * @} + */ + +/** @defgroup I2C_XferDirection_definition I2C XferDirection definition + * @{ + */ +#define I2C_DIRECTION_RECEIVE 0x00000000U +#define I2C_DIRECTION_TRANSMIT 0x00000001U +/** + * @} + */ + +/** @defgroup I2C_XferOptions_definition I2C XferOptions definition + * @{ + */ +#define I2C_FIRST_FRAME 0x00000001U +#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U +#define I2C_NEXT_FRAME 0x00000004U +#define I2C_FIRST_AND_LAST_FRAME 0x00000008U +#define I2C_LAST_FRAME_NO_STOP 0x00000010U +#define I2C_LAST_FRAME 0x00000020U + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x00AA0000U) +#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_BUF I2C_CR2_ITBUFEN +#define I2C_IT_EVT I2C_CR2_ITEVTEN +#define I2C_IT_ERR I2C_CR2_ITERREN +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ + +#define I2C_FLAG_OVR 0x00010800U +#define I2C_FLAG_AF 0x00010400U +#define I2C_FLAG_ARLO 0x00010200U +#define I2C_FLAG_BERR 0x00010100U +#define I2C_FLAG_TXE 0x00010080U +#define I2C_FLAG_RXNE 0x00010040U +#define I2C_FLAG_STOPF 0x00010010U +#define I2C_FLAG_ADD10 0x00010008U +#define I2C_FLAG_BTF 0x00010004U +#define I2C_FLAG_ADDR 0x00010002U +#define I2C_FLAG_SB 0x00010001U +#define I2C_FLAG_DUALF 0x00100080U +#define I2C_FLAG_GENCALL 0x00100010U +#define I2C_FLAG_TRA 0x00100004U +#define I2C_FLAG_BUSY 0x00100002U +#define I2C_FLAG_MSL 0x00100001U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif + +/** @brief Enable or disable the specified I2C interrupts. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Checks if the specified I2C interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag + * @arg I2C_FLAG_RXNE: Data register not empty flag + * @arg I2C_FLAG_STOPF: Stop detection flag + * @arg I2C_FLAG_ADD10: 10-bit header sent flag + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag + * Address matched flag + * @arg I2C_FLAG_SB: Start bit flag + * @arg I2C_FLAG_DUALF: Dual flag + * @arg I2C_FLAG_GENCALL: General call header flag + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \ + (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \ + (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)) + +/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) + +/** @brief Clears the I2C ADDR pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + tmpreg = (__HANDLE__)->Instance->SR2; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Clears the I2C STOPF pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) + +/** + * @} + */ + +/* Include I2C HAL Extension module */ +#include "stm32f4xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ +#define I2C_FLAG_MASK 0x0000FFFFU +#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */ +#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ + +#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST)) +#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR) +#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) +#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) +#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U)) +#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) + +#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0))) +#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) + +#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) +#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) +#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) + +/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters + * @{ + */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ + ((CYCLE) == I2C_DUTYCYCLE_16_9)) +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ + ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_I2C_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h new file mode 100644 index 00000000..e2ee7c80 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h @@ -0,0 +1,115 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_EX_H +#define __STM32F4xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macros I2C Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_I2C_EX_H */ + + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h new file mode 100644 index 00000000..de1ec241 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h @@ -0,0 +1,461 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pcd.h + * @author MCD Application Team + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_PCD_H +#define STM32F4xx_HAL_PCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_ll_usb.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types PCD Exported Types + * @{ + */ + +/** + * @brief PCD State structure definition + */ +typedef enum +{ + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 +} PCD_StateTypeDef; + +/* Device LPM suspend state */ +typedef enum +{ + LPM_L0 = 0x00, /* on */ + LPM_L1 = 0x01, /* LPM L1 sleep */ + LPM_L2 = 0x02, /* suspend */ + LPM_L3 = 0x03, /* off */ +} PCD_LPM_StateTypeDef; + +typedef enum +{ + PCD_LPM_L0_ACTIVE = 0x00, /* on */ + PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ +} PCD_LPM_MsgTypeDef; + +typedef enum +{ + PCD_BCD_ERROR = 0xFF, + PCD_BCD_CONTACT_DETECTION = 0xFE, + PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, + PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, + PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, + PCD_BCD_DISCOVERY_COMPLETED = 0x00, + +} PCD_BCD_MsgTypeDef; + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +typedef USB_OTG_GlobalTypeDef PCD_TypeDef; +typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; +typedef USB_OTG_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @brief PCD Handle Structure definition + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +typedef struct __PCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + uint32_t BESL; + uint32_t FrameNumber; /*!< Store Current Frame number */ + + + uint32_t lpm_active; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + + uint32_t battery_charging_active; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ + void *pData; /*!< Pointer to upper stack Handler */ + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ + void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ + void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ + void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ + void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ + void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ + void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ + + void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ + void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ + void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ + void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ + void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */ + void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */ + + void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +} PCD_HandleTypeDef; + +/** + * @} + */ + +/* Include PCD HAL Extended module */ +#include "stm32f4xx_hal_pcd_ex.h" + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup PCD_Speed PCD Speed + * @{ + */ +#define PCD_SPEED_HIGH USBD_HS_SPEED +#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED +#define PCD_SPEED_FULL USBD_FS_SPEED +/** + * @} + */ + +/** @defgroup PCD_PHY_Module PCD PHY Module + * @{ + */ +#define PCD_PHY_ULPI 1U +#define PCD_PHY_EMBEDDED 2U +#define PCD_PHY_UTMI 3U +/** + * @} + */ + +/** @defgroup PCD_Error_Code_definition PCD Error Code definition + * @brief PCD Error Code definition + * @{ + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ + ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) + +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK + +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ + ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) + +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) + +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ + } while(0U) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE + +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ + } while(0U) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition + * @brief HAL USB OTG PCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ + HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ + HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ + HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ + HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ + HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + + HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ + HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ + +} HAL_PCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition + * @brief HAL USB OTG PCD Callback pointer definition + * @{ + */ + +typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ +typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ +typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ +typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ +typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ +typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */ +typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */ + +/** + * @} + */ + +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/* Non-Blocking mode: Interrupt */ +/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); +void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @} + */ +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#ifndef USB_OTG_DOEPINT_OTEPSPR +#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ + +#ifndef USB_OTG_DOEPMSK_OTEPSPRM +#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ + +#ifndef USB_OTG_DOEPINT_NAK +#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ +#endif /* defined USB_OTG_DOEPINT_NAK */ + +#ifndef USB_OTG_DOEPMSK_NAKM +#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NAKM */ + +#ifndef USB_OTG_DOEPINT_STPKTRX +#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_STPKTRX */ + +#ifndef USB_OTG_DOEPMSK_NYETM +#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NYETM */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_HAL_PCD_H */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h new file mode 100644 index 00000000..284c9d56 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pcd_ex.h + * @author MCD Application Team + * @brief Header file of PCD HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_PCD_EX_H +#define STM32F4xx_HAL_PCD_EX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \ + || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); +#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); +void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32F4xx_HAL_PCD_EX_H */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h new file mode 100644 index 00000000..a7273d5e --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h @@ -0,0 +1,436 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_PWR_H +#define __STM32F4xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins + * @{ + */ +#define PWR_WAKEUP_PIN1 0x00000100U +/** + * @} + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage + (Compare internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON 0x00000000U +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03) + +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03) +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_BRR PWR_CSR_BRR +#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A + * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage + * scaling output selection is ready. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) + +/** + * @brief Enable the PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\ + }while(0U) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\ + }while(0U) + +/** + * @brief checks whether the specified PVD Exti interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD Exti flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32f4xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Power PVD IRQ Handler */ +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +/** + * @} + */ + +/** @defgroup PWR_register_alias_address PWR Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) +#define PWR_CR_OFFSET 0x00U +#define PWR_CSR_OFFSET 0x04U +#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) +#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) +/** + * @} + */ + +/** @defgroup PWR_CR_register_alias PWR CR Register alias address + * @{ + */ +/* --- CR Register ---*/ +/* Alias word address of DBP bit */ +#define DBP_BIT_NUMBER PWR_CR_DBP_Pos +#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)) + +/* Alias word address of PVDE bit */ +#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos +#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)) + +/* Alias word address of VOS bit */ +#define VOS_BIT_NUMBER PWR_CR_VOS_Pos +#define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U)) +/** + * @} + */ + +/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address + * @{ + */ +/* --- CSR Register ---*/ +/* Alias word address of EWUP bit */ +#define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos +#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || \ + ((ENTRY) == PWR_STOPENTRY_WFE) || \ + ((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_PWR_H */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h new file mode 100644 index 00000000..57fd4d93 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h @@ -0,0 +1,340 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_PWR_EX_H +#define __STM32F4xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode + * @{ + */ +#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS +#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) +/** + * @} + */ + +/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag + * @{ + */ +#define PWR_FLAG_ODRDY PWR_CSR_ODRDY +#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY +#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale + * @{ + */ +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 0x00000000U /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */ +#else +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to + 180 MHz by activating the over-drive mode. */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to + 168 MHz by activating the over-drive mode. */ +#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */ +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ +/** + * @} + */ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins + * @{ + */ +#define PWR_WAKEUP_PIN2 0x00000080U +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#define PWR_WAKEUP_PIN3 0x00000040U +#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \ + STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** + * @} + */ +#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ + +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__ specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ + UNUSED(tmpreg); \ + } while(0U) +#else +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__ specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macros to enable or disable the Over drive mode. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + */ +#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE) +#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE) + +/** @brief Macros to enable or disable the Over drive switching. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + */ +#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE) +#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE) + +/** @brief Macros to enable or disable the Under drive mode. + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + */ +#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN) +#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN)) + +/** @brief Check PWR flag is set or not. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode + * is ready + * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode + * switching is ready + * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode + * is enabled in Stop mode + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the Under-Drive Ready flag. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + */ +#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY) + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ +void HAL_PWREx_EnableFlashPowerDown(void); +void HAL_PWREx_DisableFlashPowerDown(void); +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ + defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +void HAL_PWREx_EnableMainRegulatorLowVoltage(void); +void HAL_PWREx_DisableMainRegulatorLowVoltage(void); +void HAL_PWREx_EnableLowRegulatorLowVoltage(void); +void HAL_PWREx_DisableLowRegulatorLowVoltage(void); +#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\ + STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWREx_Private_Constants PWREx Private Constants + * @{ + */ + +/** @defgroup PWREx_register_alias_address PWREx Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +/* --- CR Register ---*/ +/* Alias word address of FPDS bit */ +#define FPDS_BIT_NUMBER PWR_CR_FPDS_Pos +#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U)) + +/* Alias word address of ODEN bit */ +#define ODEN_BIT_NUMBER PWR_CR_ODEN_Pos +#define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U)) + +/* Alias word address of ODSWEN bit */ +#define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos +#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U)) + +/* Alias word address of MRLVDS bit */ +#define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos +#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U)) + +/* Alias word address of LPLVDS bit */ +#define LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos +#define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U)) + + /** + * @} + */ + +/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address + * @{ + */ +/* --- CSR Register ---*/ +/* Alias word address of BRE bit */ +#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos +#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U)) + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Macros PWREx Private Macros + * @{ + */ + +/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) +#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +#else +#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ + +#if defined(STM32F446xx) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2)) +#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3)) +#else +#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1) +#endif /* STM32F446xx */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_PWR_EX_H */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h new file mode 100644 index 00000000..2e3909ad --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h @@ -0,0 +1,1458 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_RCC_H +#define __STM32F4xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/* Include RCC HAL Extended module */ +/* (include on top of file since RCC structures are defined in extended file) */ +#include "stm32f4xx_hal_rcc_ex.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U +#define RCC_OSCILLATORTYPE_HSE 0x00000001U +#define RCC_OSCILLATORTYPE_HSI 0x00000002U +#define RCC_OSCILLATORTYPE_LSE 0x00000004U +#define RCC_OSCILLATORTYPE_LSI 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U +#define RCC_HSE_ON RCC_CR_HSEON +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0x00000000U +#define RCC_LSE_ON RCC_BDCR_LSEON +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF ((uint8_t)0x00) +#define RCC_HSI_ON ((uint8_t)0x01) + +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF ((uint8_t)0x00) +#define RCC_LSI_ON ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE ((uint8_t)0x00) +#define RCC_PLL_OFF ((uint8_t)0x01) +#define RCC_PLL_ON ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider + * @{ + */ +#define RCC_PLLP_DIV2 0x00000002U +#define RCC_PLLP_DIV4 0x00000004U +#define RCC_PLLP_DIV6 0x00000006U +#define RCC_PLLP_DIV8 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI +#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U +#define RCC_CLOCKTYPE_HCLK 0x00000002U +#define RCC_CLOCKTYPE_PCLK1 0x00000004U +#define RCC_CLOCKTYPE_PCLK2 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for + * STM32F446xx devices. + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL +#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for + * STM32F446xx devices. + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U +#define RCC_RTCCLKSOURCE_LSE 0x00000100U +#define RCC_RTCCLKSOURCE_LSI 0x00000200U +#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U +#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U +#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U +#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U +#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U +#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U +#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U +#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U +#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U +#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U +#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U +#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U +#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U +#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U +#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U +#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U +#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U +#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U +#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U +#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U +#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U +#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U +#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U +#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U +#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U +#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U +#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U +#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U +#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U +#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U +#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 0x00000000U +#define RCC_MCO2 0x00000001U +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_HSI 0x00000000U +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 +#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 0x00000000U +#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 +#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) +#define RCC_IT_CSS ((uint8_t)0x80) +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: 0XXYYYYYb + * - YYYYY : Flag position in the register + * - 0XX : Register index + * - 01: CR register + * - 10: BDCR register + * - 11: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)0x41) + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_BORRST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) + +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +/** + * @} + */ + +/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) +/** + * @} + */ + +/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) + +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wake-up from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) +#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICalibrationValue__ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\ + RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos)) +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) +#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. + * User should request a transition to HSE Off first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator. + * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0U) +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator. + * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0U) +/** + * @} + */ + +/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) +#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * a Power On Reset (POR). + * @param __RTCCLKSource__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wake-up source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) + +#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ + RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ + } while(0U) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** + * @brief Get the RTC and HSE clock divider (RTCPRE). + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) +#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) +#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) + +/** @brief Macro to configure the PLL clock source. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) + +/** @brief Macro to configure the PLL multiplication factor. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + */ +#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ +/** + * @brief Macro to configure the system clock source. + * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This + * parameter is available only for STM32F446xx devices. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter + * is available only for STM32F446xx devices. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have + * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5). + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U))); +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. + * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. + * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. + * @arg RCC_FLAG_PINRST: Pin reset. + * @arg RCC_FLAG_PORRST: POR/PDR reset. + * @arg RCC_FLAG_SFTRST: Software reset. + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. + * @arg RCC_FLAG_LPWRRST: Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define RCC_FLAG_MASK ((uint8_t)0x1FU) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U)\ + == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) &\ + (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); + +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ + +/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +/* --- CR Register --- */ +/* Alias word address of HSION bit */ +#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) +#define RCC_HSION_BIT_NUMBER 0x00U +#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U)) +/* Alias word address of CSSON bit */ +#define RCC_CSSON_BIT_NUMBER 0x13U +#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)) +/* Alias word address of PLLON bit */ +#define RCC_PLLON_BIT_NUMBER 0x18U +#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)) + +/* --- BDCR Register --- */ +/* Alias word address of RTCEN bit */ +#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U) +#define RCC_RTCEN_BIT_NUMBER 0x0FU +#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)) +/* Alias word address of BDRST bit */ +#define RCC_BDRST_BIT_NUMBER 0x10U +#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)) + +/* --- CSR Register --- */ +/* Alias word address of LSION bit */ +#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) +#define RCC_LSION_BIT_NUMBER 0x00U +#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U)) + +/* CR register byte 3 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS 0x40023802U + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U)) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U)) + +/* BDCR register base address */ +#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) + +#define RCC_DBP_TIMEOUT_VALUE 2U +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT + +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE 2U /* 2 ms */ +#define LSI_TIMEOUT_VALUE 2U /* 2 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U) + +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS)) + +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) + +#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) + +#define IS_RCC_PLLM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) + +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) + +#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ + ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ + ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ + ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ + ((HCLK) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U)) + +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ + ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ + ((PCLK) == RCC_HCLK_DIV16)) + +#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ + ((DIV) == RCC_MCODIV_5)) +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_RCC_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h new file mode 100644 index 00000000..3b621340 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h @@ -0,0 +1,7190 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_RCC_EX_H +#define __STM32F4xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 + except for STM32F411xE devices where the Min_Data = 192 */ + + uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. + This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) + uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. + This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx + and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. + This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ +#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +} RCC_PLLInitTypeDef; + +#if defined(STM32F446xx) +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock. + This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S */ +} RCC_PLLI2SInitTypeDef; + +/** + * @brief PLLSAI Clock structure definition + */ +typedef struct +{ + uint32_t PLLSAIM; /*!< Specifies division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks. + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ + + uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ +} RCC_PLLSAIInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ + + uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ + + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ + + uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection. + This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ + + uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ + + uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. + This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ + + uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection. + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ + + uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection. + This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ + + uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +} RCC_PeriphCLKInitTypeDef; +#endif /* STM32F446xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +} RCC_PeriphCLKInitTypeDef; +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S */ +} RCC_PLLI2SInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S */ + +#if defined(STM32F413xx) || defined(STM32F423xx) + uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLL is selected as Clock Source SAI */ + + uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ +#endif /* STM32F413xx || STM32F423xx */ + + uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ + + uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. + This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ + + uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ + + uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ + + uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ + +#if defined(STM32F413xx) || defined(STM32F423xx) + uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */ + + uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */ + + uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */ +#endif /* STM32F413xx || STM32F423xx */ + + uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection. + This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +} RCC_PeriphCLKInitTypeDef; +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ +} RCC_PLLI2SInitTypeDef; + +/** + * @brief PLLSAI Clock structure definition + */ +typedef struct +{ + uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ +#if defined(STM32F469xx) || defined(STM32F479xx) + uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks. + This parameter is only available in STM32F469xx/STM32F479xx devices. + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ +#endif /* STM32F469xx || STM32F479xx */ + + uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ + + uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ + +} RCC_PLLSAIInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ + + uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ + + uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. + This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +#if defined(STM32F469xx) || defined(STM32F479xx) + uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. + This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ +#endif /* STM32F469xx || STM32F479xx */ +} RCC_PeriphCLKInitTypeDef; + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ +#if defined(STM32F411xE) + uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ +#endif /* STM32F411xE */ + + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 + Except for STM32F411xE devices where the Min_Data = 192. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + +} RCC_PLLI2SInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +} RCC_PeriphCLKInitTypeDef; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection + * @{ + */ +/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +#define RCC_PERIPHCLK_I2S_APB1 0x00000001U +#define RCC_PERIPHCLK_I2S_APB2 0x00000002U +#define RCC_PERIPHCLK_TIM 0x00000004U +#define RCC_PERIPHCLK_RTC 0x00000008U +#define RCC_PERIPHCLK_FMPI2C1 0x00000010U +#define RCC_PERIPHCLK_CLK48 0x00000020U +#define RCC_PERIPHCLK_SDIO 0x00000040U +#define RCC_PERIPHCLK_PLLI2S 0x00000080U +#define RCC_PERIPHCLK_DFSDM1 0x00000100U +#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U +#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define RCC_PERIPHCLK_DFSDM2 0x00000400U +#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U +#define RCC_PERIPHCLK_LPTIM1 0x00001000U +#define RCC_PERIPHCLK_SAIA 0x00002000U +#define RCC_PERIPHCLK_SAIB 0x00004000U +#endif /* STM32F413xx || STM32F423xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------- Peripheral Clock source for STM32F410xx ----------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_TIM 0x00000002U +#define RCC_PERIPHCLK_RTC 0x00000004U +#define RCC_PERIPHCLK_FMPI2C1 0x00000008U +#define RCC_PERIPHCLK_LPTIM1 0x00000010U +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/*----------------------------------------------------------------------------*/ + +/*------------------- Peripheral Clock source for STM32F446xx ----------------*/ +#if defined(STM32F446xx) +#define RCC_PERIPHCLK_I2S_APB1 0x00000001U +#define RCC_PERIPHCLK_I2S_APB2 0x00000002U +#define RCC_PERIPHCLK_SAI1 0x00000004U +#define RCC_PERIPHCLK_SAI2 0x00000008U +#define RCC_PERIPHCLK_TIM 0x00000010U +#define RCC_PERIPHCLK_RTC 0x00000020U +#define RCC_PERIPHCLK_CEC 0x00000040U +#define RCC_PERIPHCLK_FMPI2C1 0x00000080U +#define RCC_PERIPHCLK_CLK48 0x00000100U +#define RCC_PERIPHCLK_SDIO 0x00000200U +#define RCC_PERIPHCLK_SPDIFRX 0x00000400U +#define RCC_PERIPHCLK_PLLI2S 0x00000800U +#endif /* STM32F446xx */ +/*-----------------------------------------------------------------------------*/ + +/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U +#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U +#define RCC_PERIPHCLK_LTDC 0x00000008U +#define RCC_PERIPHCLK_TIM 0x00000010U +#define RCC_PERIPHCLK_RTC 0x00000020U +#define RCC_PERIPHCLK_PLLI2S 0x00000040U +#define RCC_PERIPHCLK_CLK48 0x00000080U +#define RCC_PERIPHCLK_SDIO 0x00000100U +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U +#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U +#define RCC_PERIPHCLK_LTDC 0x00000008U +#define RCC_PERIPHCLK_TIM 0x00000010U +#define RCC_PERIPHCLK_RTC 0x00000020U +#define RCC_PERIPHCLK_PLLI2S 0x00000040U +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +/*----------------------------------------------------------------------------*/ + +/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_RTC 0x00000002U +#define RCC_PERIPHCLK_PLLI2S 0x00000004U +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define RCC_PERIPHCLK_TIM 0x00000008U +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +/*----------------------------------------------------------------------------*/ +/** + * @} + */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ + defined(STM32F479xx) +/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ + +/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define RCC_PLLSAIDIVR_2 0x00000000U +#define RCC_PLLSAIDIVR_4 0x00010000U +#define RCC_PLLSAIDIVR_8 0x00020000U +#define RCC_PLLSAIDIVR_16 0x00030000U +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider + * @{ + */ +#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) +#define RCC_PLLI2SP_DIV2 0x00000002U +#define RCC_PLLI2SP_DIV4 0x00000004U +#define RCC_PLLI2SP_DIV6 0x00000006U +#define RCC_PLLI2SP_DIV8 0x00000008U +#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +/** + * @} + */ + +/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider + * @{ + */ +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define RCC_PLLSAIP_DIV2 0x00000002U +#define RCC_PLLSAIP_DIV4 0x00000004U +#define RCC_PLLSAIP_DIV6 0x00000006U +#define RCC_PLLSAIP_DIV8 0x00000008U +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source + * @{ + */ +#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U +#define RCC_SAIACLKSOURCE_EXT 0x00200000U +/** + * @} + */ + +/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source + * @{ + */ +#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U +#define RCC_SAIBCLKSOURCE_EXT 0x00800000U +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source + * @{ + */ +#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U +#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source + * @{ + */ +#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U +#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL) +/** + * @} + */ + +/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL) +/** + * @} + */ +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F446xx) +/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source + * @{ + */ +#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) +#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) +#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC) +/** + * @} + */ + +/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source + * @{ + */ +#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0) +#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1) +#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source + * @{ + */ +#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) +#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) +#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source + * @{ + */ +#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) +#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) +#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) +/** + * @} + */ + +/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source + * @{ + */ +#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) +#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_HSI 0x00000000U +#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL) +/** + * @} + */ + +/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source + * @{ + */ +#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U +#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source + * @{ + */ +#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U +#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source + * @{ + */ +#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U +#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL) +/** + * @} + */ + +#endif /* STM32F446xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source + * @{ + */ +#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U +#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) +#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) +#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) +/** + * @} + */ + +/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source + * @{ + */ +#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U +#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) +#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) +#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U +#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) +#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) +#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) +/** + * @} + */ + + +/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source + * @{ + */ +#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U +#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U +#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) +/** + * @} + */ + +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source + * @{ + */ +#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U +#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC) +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U +#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U +#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source + * @{ + */ +#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) +#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) +#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source + * @{ + */ +#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) +#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) +#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) +/** + * @} + */ + +/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source + * @{ + */ +#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) +#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source + * @{ + */ +#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U +#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source + * @{ + */ +#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U +#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) +/** + * @} + */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) + +/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source + * @{ + */ +#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U +#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) +#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) +/** + * @} + */ + +/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source + * @{ + */ +#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) +#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U +#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) +#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) +#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection + * @{ + */ +#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) +#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection + * @{ + */ +#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) +#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) +/** + * @} + */ +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\ + STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK 0x00000000U +#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 +#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || + STM32F412Rx || STM32F413xx | STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK 0x00000000U +#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 +#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ +/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) +#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) +#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) +#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) + +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0U) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0U) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) +#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) +#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) + +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x22E017FFU) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) +#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) +#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F469xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C1U) +#endif /* STM32F427xx || STM32F429xx || STM32F469xx */ +#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000F1U) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) + +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000001U) +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) +#endif /* STM32F469xx || STM32F479xx */ +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xF6FEC9FFU) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x0C777933U) +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F429xx) || defined(STM32F439xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x04777933U) +#endif /* STM32F429xx || STM32F439xx */ +#if defined(STM32F427xx) || defined(STM32F437xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00777933U) +#endif /* STM32F427xx || STM32F437xx */ +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) +#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) +#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) +#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) + +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) + +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#if defined(STM32F407xx)|| defined(STM32F417xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0U) + +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) +#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0U) +#endif /* STM32F407xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#if defined(STM32F407xx)|| defined(STM32F417xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) +#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) +#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) +#endif /* STM32F407xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F415xx || STM32F417xx */ +/** + * @} + */ + + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) + +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) +#endif /* STM32F415xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) +#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#if defined (STM32F405xx) || defined (STM32F415xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x206011FFU) +#endif /* STM32F405xx || STM32F415xx */ +#if defined (STM32F407xx) || defined (STM32F417xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x226011FFU) +#endif /* STM32F407xx || STM32F417xx */ +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#if defined (STM32F415xx) || defined (STM32F417xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000F1U) +#endif /* STM32F415xx || STM32F417xx */ +#if defined (STM32F405xx) || defined (STM32F407xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C1U) +#endif /* STM32F405xx || STM32F407xx */ +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) + +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) +#endif /* STM32F415xx || STM32F417xx */ + +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000001U) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) + +#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) +#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xF6FEC9FFU) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x04777933U) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) + +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) +#endif /* STM32F415xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) +#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------- STM32F401xE/STM32F401xC --------------------------*/ +#if defined(STM32F401xC) || defined(STM32F401xE) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +/** + * @} + */ +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000080U) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x10E2C80FU) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00077931U) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +/** + * @} + */ +#endif /* STM32F401xC || STM32F401xE*/ +/*----------------------------------------------------------------------------*/ + +/*-------------------------------- STM32F410xx -------------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET) + +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB1) peripheral clock. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) + +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) +#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) + +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x80601087U) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() +#define __HAL_RCC_AHB2_RELEASE_RESET() +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() +#define __HAL_RCC_AHB3_RELEASE_RESET() +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#if defined (STM32F410Rx) || defined (STM32F410Cx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x31624A18U) +#endif /* STM32F410Rx || STM32F410Cx */ +#if defined (STM32F410Tx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x31620A18U) +#endif /* STM32F410Tx */ +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#if defined (STM32F410Rx) || defined (STM32F410Cx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00155131U) +#endif /* STM32F410Rx || STM32F410Cx */ +#if defined (STM32F410Tx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00055111U) +#endif /* STM32F410Tx */ +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) + +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) +/** + * @} + */ + +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/*----------------------------------------------------------------------------*/ + +/*-------------------------------- STM32F411xx -------------------------------*/ +#if defined(STM32F411xE) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000080U) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x10E2C80FU) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00177931U) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +/** + * @} + */ +#endif /* STM32F411xE */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F446xx -----------------------------*/ +#if defined(STM32F446xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) + +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) +#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x206010FFU) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000081U) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) + +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) + +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x3FFFC9FFU) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00C77933U) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) + +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) +/** + * @} + */ + +#endif /* STM32F446xx */ +/*----------------------------------------------------------------------------*/ + +/*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) + +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F423xx) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) +#endif /* STM32F423xx */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F423xx) +#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) +#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) +#endif /* STM32F423xx */ + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) + +#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) +#endif /* STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN)) +#define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET) +#define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) +#define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#if defined (STM32F412Zx) || defined(STM32F413xx) || defined (STM32F423xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x006010FFU) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined (STM32F412Cx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x00601087U) +#endif /* STM32F412Cx */ +#if defined (STM32F412Vx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) +#endif /* STM32F412Vx */ +#if defined (STM32F412Rx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060108FU) +#endif /* STM32F412Rx */ +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#if defined(STM32F423xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000D0U) +#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) +#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) +#else +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C0U) +#endif /* STM32F423xx */ +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) + +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) + +#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) + +#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Cx) +#define __HAL_RCC_AHB3_FORCE_RESET() +#define __HAL_RCC_AHB3_RELEASE_RESET() + +#define __HAL_RCC_FSMC_FORCE_RESET() +#define __HAL_RCC_QSPI_FORCE_RESET() + +#define __HAL_RCC_FSMC_RELEASE_RESET() +#define __HAL_RCC_QSPI_RELEASE_RESET() +#endif /* STM32F412Cx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFECBFFU) +#endif /* STM32F413xx || STM32F423xx */ +#if defined (STM32F412Zx) || defined (STM32F412Vx) || defined (STM32F412Rx) || defined (STM32F412Cx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x17E6C9FFU) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#if defined(STM32F413xx)|| defined(STM32F423xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x035779F3U) +#endif /* STM32F413xx || STM32F423xx */ +#if defined (STM32F412Zx) || defined (STM32F412Vx) || defined (STM32F412Rx) || defined (STM32F412Cx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x01177933U) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST)) +#define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST)) +#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(STM32F423xx) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) +#endif /* STM32F423xx */ + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) + +#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN)) +#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN)) +#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------------- PLL Configuration --------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ + STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ + (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) +#else +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432 + * Except for STM32F411xE devices where Min_Data = 192. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices + * where frequency is between 192 and 432 MHz. + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ + (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) +#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------PLLI2S Configuration ---------------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + +/** @brief Macros to enable or disable the PLLI2S. + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) +#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || + STM32F412Rx || STM32F412Cx */ +#if defined(STM32F446xx) +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 1 MHz to limit PLLI2S jitter. + * + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock. + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note the PLLI2SP parameter is only available with STM32F446xx Devices + * + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @param __PLLI2SQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 1 MHz to limit PLLI2S jitter. + * + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @param __PLLI2SQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#else +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#endif /* STM32F446xx */ + +#if defined(STM32F411xE) +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLLI2S jitter. + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 192 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#endif /* STM32F411xE */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SQ__ specifies the division factor for SAI1 clock. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx + * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\ + ((__PLLI2SQ__) << 24U) |\ + ((__PLLI2SR__) << 28U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------------ PLLSAI Configuration ------------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macros to Enable or Disable the PLLISAI. + * @note The PLLSAI is only available with STM32F429x/439x Devices. + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) +#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE) + +#if defined(STM32F446xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * + * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 1 MHz to limit PLLI2S jitter. + * @note The PLLSAIM parameter is only used with STM32F446xx Devices + * + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks. + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note the PLLSAIP parameter is only available with STM32F446xx Devices + * + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ + ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ + ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks. + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ + ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. + * @note This function must be called before enabling the PLLI2S. + * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock. + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ + */ +#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U)) + +/** @brief Macro to configure the SAI clock Divider coming from PLL. + * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock. + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLR) / __PLLDivR__ + */ +#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U)) +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. + * @note This function must be called before enabling the PLLI2S. + * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ + */ +#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U)) + +/** @brief Macro to configure the SAI clock Divider coming from PLLSAI. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . + * This parameter must be a number between Min_Data = 1 and Max_Data = 32. + * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. + * + * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . + * This parameter must be a number between Min_Data = 2 and Max_Data = 16. + * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------- Peripheral Clock selection -----------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ + defined(STM32F479xx) +/** @brief Macro to configure the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S APB clock. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. + * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin + * used as I2S clock source. + */ +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (__SOURCE__))) + + +/** @brief Macro to get the I2S clock source (I2SCLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. + * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin + * used as I2S clock source + */ +#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/** @brief Macro to configure SAI1BlockA clock source selection. + * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block A clock. + */ +#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) + +/** @brief Macro to configure SAI1BlockB clock source selection. + * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block B clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block B clock. + * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block B clock. + * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block B clock. + */ +#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F446xx) +/** @brief Macro to configure SAI1 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. + */ +#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__))) + +/** @brief Macro to Get SAI1 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. + */ +#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC)) + +/** @brief Macro to configure SAI2 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. + */ +#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__))) + +/** @brief Macro to Get SAI2 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. + */ +#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC)) + +/** @brief Macro to configure I2S APB1 clock source selection. + * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. + * @param __SOURCE__ specifies the I2S APB1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB1 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) + +/** @brief Macro to configure I2S APB2 clock source selection. + * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. + * @param __SOURCE__ specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB2 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) + +/** @brief Macro to configure the CEC clock. + * @param __SOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CEC clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) + +/** @brief Macro to configure the FMPI2C1 clock. + * @param __SOURCE__ specifies the FMPI2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the FMPI2C1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) + +/** @brief Macro to configure the CLK48 clock. + * @param __SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CLK48 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) + +/** @brief Macro to configure the SDIO clock. + * @param __SOURCE__ specifies the SDIO clock source. + * This parameter can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SDIO clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) + +/** @brief Macro to configure the SPDIFRX clock. + * @param __SOURCE__ specifies the SPDIFRX clock source. + * This parameter can be one of the following values: + * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. + * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. + */ +#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SPDIFRX clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. + * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. + */ +#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL)) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) + +/** @brief Macro to configure the CLK48 clock. + * @param __SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CLK48 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) + +/** @brief Macro to configure the SDIO clock. + * @param __SOURCE__ specifies the SDIO clock source. + * This parameter can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SDIO clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) + +/** @brief Macro to configure the DSI clock. + * @param __SOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the DSI clock. + * @retval The clock source can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL)) + +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the DFSDM1 clock. + * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. + * @retval None + */ +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. + */ +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) + +/** @brief Macro to configure DFSDM1 Audio clock source selection. + * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ + STM32F413xx/STM32F423xx Devices. + * @param __SOURCE__ specifies the DFSDM1 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__))) + +/** @brief Macro to Get DFSDM1 Audio clock source selection. + * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ + STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL)) + +#if defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the DFSDM2 clock. + * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. + * @retval None + */ +#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. + */ +#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) + +/** @brief Macro to configure DFSDM1 Audio clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @param __SOURCE__ specifies the DFSDM2 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__))) + +/** @brief Macro to Get DFSDM2 Audio clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL)) + +/** @brief Macro to configure SAI1BlockA clock source selection. + * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) + +/** @brief Macro to Get SAI1 BlockA clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC)) + +/** @brief Macro to configure SAI1 BlockB clock source selection. + * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block B clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) + +/** @brief Macro to Get SAI1 BlockB clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC)) + +/** @brief Macro to configure the LPTIM1 clock. + * @param __SOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the LPTIM1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) +#endif /* STM32F413xx || STM32F423xx */ + +/** @brief Macro to configure I2S APB1 clock source selection. + * @param __SOURCE__ specifies the I2S APB1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB1 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) + +/** @brief Macro to configure I2S APB2 clock source selection. + * @param __SOURCE__ specifies the I2S APB2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB2 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) + +/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK). + * @note This macro must be called before enabling the I2S APB clock. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin + * used as I2S clock source. + */ +#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__)) + +/** @brief Macro to configure the FMPI2C1 clock. + * @param __SOURCE__ specifies the FMPI2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the FMPI2C1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) + +/** @brief Macro to configure the CLK48 clock. + * @param __SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock. + */ +#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CLK48 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock + */ +#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) + +/** @brief Macro to configure the SDIO clock. + * @param __SOURCE__ specifies the SDIO clock source. + * This parameter can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SDIO clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) + +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @brief Macro to configure I2S clock source selection. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. + * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. + */ +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__))) + +/** @brief Macro to Get I2S clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. + * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. + */ +#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) + +/** @brief Macro to configure the FMPI2C1 clock. + * @param __SOURCE__ specifies the FMPI2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the FMPI2C1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) + +/** @brief Macro to configure the LPTIM1 clock. + * @param __SOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the LPTIM1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the Timers clocks prescalers + * @note This feature is only available with STM32F429x/439x Devices. + * @param __PRESC__ specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * division by 4 or more. + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * to division by 8 or more. + */ +#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\ + STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\ + STM32F423xx */ + +/*----------------------------------------------------------------------------*/ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Enable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Disable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) + +/** @brief Clear the PLLSAI RDY interrupt pending bits. + */ +#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) + +/** @brief Check the PLLSAI RDY interrupt has occurred or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Check PLLSAI RDY flag is set or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @brief Macros to enable or disable the RCC MCO1 feature. + */ +#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE) +#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE) + +/** @brief Macros to enable or disable the RCC MCO2 feature. + */ +#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE) +#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE) + +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); + +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +void HAL_RCCEx_SelectLSEMode(uint8_t Mode); +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +#if defined(RCC_PLLI2S_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); +#endif /* RCC_PLLSAI_SUPPORT */ +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ + +/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +/* --- CR Register ---*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* Alias word address of PLLSAION bit */ +#define RCC_PLLSAION_BIT_NUMBER 0x1CU +#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U)) + +#define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Alias word address of PLLI2SON bit */ +#define RCC_PLLI2SON_BIT_NUMBER 0x1AU +#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || + STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/* --- DCKCFGR Register ---*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ + defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Alias word address of TIMPRE bit */ +#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU) +#define RCC_TIMPRE_BIT_NUMBER 0x18U +#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\ + STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/* --- CFGR Register ---*/ +#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) +/* Alias word address of I2SSRC bit */ +#define RCC_I2SSRC_BIT_NUMBER 0x17U +#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U)) + +#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +/* --- PLLI2SCFGR Register ---*/ +#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U) +/* Alias word address of PLLI2SSRC bit */ +#define RCC_PLLI2SSRC_BIT_NUMBER 0x16U +#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE\ + + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U)) + +#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/* Alias word address of MCO1EN bit */ +#define RCC_MCO1EN_BIT_NUMBER 0x8U +#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U)) + +/* Alias word address of MCO2EN bit */ +#define RCC_MCO2EN_BIT_NUMBER 0x9U +#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#define PLL_TIMEOUT_VALUE 2U /* 2 ms */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU)) +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F446xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU)) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU)) +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU)) +#endif /* STM32F413xx || STM32F423xx */ + +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) + +#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ + ((VALUE) == RCC_PLLSAIDIVR_4) ||\ + ((VALUE) == RCC_PLLSAIDIVR_8) ||\ + ((VALUE) == RCC_PLLSAIDIVR_16)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) + +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) +#endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) + +#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) + +#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) + +#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F446xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ + ((VALUE) == RCC_PLLI2SP_DIV4) ||\ + ((VALUE) == RCC_PLLI2SP_DIV6) ||\ + ((VALUE) == RCC_PLLI2SP_DIV8)) + +#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U) + +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) + +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAI1CLKSOURCE_EXT)) + +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) + +#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) + +#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) + +#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) + +#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ + ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) + +#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ + ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) + +#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) + +#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ + ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) + +#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ + ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) + +#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) + +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \ + ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT)) + +#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) + +#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) + +#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) + +#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ + ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ)) + +#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ + ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \ + ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2)) + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \ + ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2)) + +#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) + +#define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\ + ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC)) + +#define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\ + ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC)) + +#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#endif /* STM32F413xx || STM32F423xx */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \ + STM32F412Rx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_RCC_EX_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h new file mode 100644 index 00000000..53c9bf66 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h @@ -0,0 +1,2157 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_TIM_H +#define STM32F4xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__HANDLE__)->Instance->CCR4)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + (__HANDLE__)->ChannelState[3]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__);\ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32f4xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_HAL_TIM_H */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h new file mode 100644 index 00000000..4f1d01b0 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h @@ -0,0 +1,357 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_TIM_EX_H +#define STM32F4xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#if defined (TIM2) +#if defined(TIM8) +#define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */ +#endif /* TIM8 */ +#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */ +#define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */ +#define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */ +#endif /* TIM2 */ + +#define TIM_TIM5_GPIO 0x00000000U /*!< TIM5 TI4 is connected to GPIO */ +#define TIM_TIM5_LSI TIM_OR_TI4_RMP_0 /*!< TIM5 TI4 is connected to LSI */ +#define TIM_TIM5_LSE TIM_OR_TI4_RMP_1 /*!< TIM5 TI4 is connected to LSE */ +#define TIM_TIM5_RTC (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0) /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */ + +#define TIM_TIM11_GPIO 0x00000000U /*!< TIM11 TI1 is connected to GPIO */ +#define TIM_TIM11_HSE TIM_OR_TI1_RMP_1 /*!< TIM11 TI1 is connected to HSE_RTC clock */ +#if defined(SPDIFRX) +#define TIM_TIM11_SPDIFRX TIM_OR_TI1_RMP_0 /*!< TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC */ +#endif /* SPDIFRX*/ + +#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) +#define LPTIM_REMAP_MASK 0x10000000U + +#define TIM_TIM9_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM9 ITR1 is connected to TIM3 TRGO */ +#define TIM_TIM9_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP) /*!< TIM9 ITR1 is connected to LPTIM1 output */ + +#define TIM_TIM5_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM5 ITR1 is connected to TIM3 TRGO */ +#define TIM_TIM5_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP) /*!< TIM5 ITR1 is connected to LPTIM1 output */ + +#define TIM_TIM1_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM1 ITR2 is connected to TIM3 TRGO */ +#define TIM_TIM1_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP) /*!< TIM1 ITR2 is connected to LPTIM1 output */ +#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#if defined(SPDIFRX) +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#elif defined(TIM2) +#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ + ((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE))) || \ + (((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \ + ((TIM_REMAP) == TIM_TIM1_LPTIM))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \ + ((TIM_REMAP) == TIM_TIM5_LPTIM))) || \ + (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \ + ((TIM_REMAP) == TIM_TIM9_LPTIM)))) +#elif defined(TIM8) +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ + ((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#else +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ +#else +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#endif /* SPDIFRX */ + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F4xx_HAL_TIM_EX_H */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h new file mode 100644 index 00000000..e6ce82fc --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h @@ -0,0 +1,909 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_UART_H +#define __STM32F4xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 + Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UART_Word_Length */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). + This parameter can be a value of @ref UART_Over_Sampling */ +} UART_InitTypeDef; + +/** + * @brief HAL UART State structures definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState. + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef enum +{ + HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_UART_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ +} HAL_UART_StateTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * This parameter can be a value of @ref UART_Reception_Type_Values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_Error_Code UART Error Code + * @{ + */ +#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */ +#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */ +#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */ +#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */ +#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Word_Length UART Word Length + * @{ + */ +#define UART_WORDLENGTH_8B 0x00000000U +#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_1 0x00000000U +#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U +#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U +#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) +#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) +#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX ((uint32_t)USART_CR1_RE) +#define UART_MODE_TX ((uint32_t)USART_CR1_TE) +#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE)) +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U +#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U +#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U +#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) +/** + * @} + */ + +/** @defgroup UART_WakeUp_functions UART Wakeup Functions + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U +#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) +/** + * @} + */ + +/** @defgroup UART_Flags UART FLags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the SR register + * @{ + */ +#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) +#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) +#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) +#define UART_FLAG_TC ((uint32_t)USART_SR_TC) +#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) +#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) +#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) +#define UART_FLAG_NE ((uint32_t)USART_SR_NE) +#define UART_FLAG_FE ((uint32_t)USART_SR_FE) +#define UART_FLAG_PE ((uint32_t)USART_SR_PE) +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupt Definitions + * Elements values convention: 0xY000XXXX + * - XXXX : Interrupt mask (16 bits) in the Y register + * - Y : Interrupt source register (2bits) + * - 0001: CR1 register + * - 0010: CR2 register + * - 0011: CR3 register + * @{ + */ + +#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) +#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) +#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) +#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) +#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) + +#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) + +#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) +#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) +/** + * @} + */ + +/** @defgroup UART_Reception_Type_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +/** + * @} + */ + +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle gstate & RxState + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flushes the UART DR register + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + +/** @brief Checks whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg UART_FLAG_LBD: LIN Break detection flag + * @arg UART_FLAG_TXE: Transmit data register empty flag + * @arg UART_FLAG_TC: Transmission Complete flag + * @arg UART_FLAG_RXNE: Receive data register not empty flag + * @arg UART_FLAG_IDLE: Idle Line detection flag + * @arg UART_FLAG_ORE: Overrun Error flag + * @arg UART_FLAG_NE: Noise Error flag + * @arg UART_FLAG_FE: Framing Error flag + * @arg UART_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg UART_FLAG_LBD: LIN Break detection flag. + * @arg UART_FLAG_TC: Transmission Complete flag. + * @arg UART_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register followed by a read + * operation to USART_DR register. + * @note RXNE flag can be also cleared by a read to the USART_DR register. + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register followed by a write operation to USART_DR register. + * @note TXE flag is cleared only by a write to the USART_DR register. + * + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Clears the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ + } while(0U) + +/** @brief Clears the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) + +/** @brief Checks whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __IT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_ERR: Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) + +/** @brief Enable CTS flow control + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control + * This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control + * This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) + +/** @brief Macro to enable the UART's one bit sample method + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Macro to disable the UART's one bit sample method + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) + +/** @brief Enable UART + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); + +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +/** @brief UART interruptions flag mask + * + */ +#define UART_IT_MASK 0x0000FFFFU + +#define UART_CR1_REG_INDEX 1U +#define UART_CR2_REG_INDEX 2U +#define UART_CR3_REG_INDEX 3U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ + ((LENGTH) == UART_WORDLENGTH_9B)) +#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ + ((STOPBITS) == UART_STOPBITS_2)) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ + ((PARITY) == UART_PARITY_EVEN) || \ + ((PARITY) == UART_PARITY_ODD)) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HWCONTROL_NONE) || \ + ((CONTROL) == UART_HWCONTROL_RTS) || \ + ((CONTROL) == UART_HWCONTROL_CTS) || \ + ((CONTROL) == UART_HWCONTROL_RTS_CTS)) +#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U)) +#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ + ((STATE) == UART_STATE_ENABLE)) +#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ + ((SAMPLING) == UART_OVERSAMPLING_8)) +#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) +#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) +#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) +#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U) +#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) + +#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_))))) +#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U)\ + + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ +#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) + +#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_))))) +#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U)\ + + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ +#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ + ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U) + \ + (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_UART_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h new file mode 100644 index 00000000..ce19d4d9 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h @@ -0,0 +1,2105 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_BUS_H +#define __STM32F4xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN +#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN +#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN +#if defined(GPIOD) +#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN +#endif /* GPIOD */ +#if defined(GPIOE) +#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN +#endif /* GPIOE */ +#if defined(GPIOF) +#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN +#endif /* GPIOG */ +#if defined(GPIOH) +#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN +#endif /* GPIOH */ +#if defined(GPIOI) +#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN +#endif /* GPIOI */ +#if defined(GPIOJ) +#define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN +#endif /* GPIOJ */ +#if defined(GPIOK) +#define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN +#endif /* GPIOK */ +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#if defined(RCC_AHB1ENR_BKPSRAMEN) +#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN +#endif /* RCC_AHB1ENR_BKPSRAMEN */ +#if defined(RCC_AHB1ENR_CCMDATARAMEN) +#define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN +#endif /* RCC_AHB1ENR_CCMDATARAMEN */ +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#if defined(RCC_AHB1ENR_RNGEN) +#define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN +#endif /* RCC_AHB1ENR_RNGEN */ +#if defined(DMA2D) +#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN +#endif /* DMA2D */ +#if defined(ETH) +#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN +#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN +#endif /* ETH */ +#if defined(USB_OTG_HS) +#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN +#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN +#endif /* USB_OTG_HS */ +#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN +#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN +#if defined(RCC_AHB1LPENR_SRAM2LPEN) +#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN +#endif /* RCC_AHB1LPENR_SRAM2LPEN */ +#if defined(RCC_AHB1LPENR_SRAM3LPEN) +#define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN +#endif /* RCC_AHB1LPENR_SRAM3LPEN */ +/** + * @} + */ + +#if defined(RCC_AHB2_SUPPORT) +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(DCMI) +#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN +#endif /* DCMI */ +#if defined(CRYP) +#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN +#endif /* CRYP */ +#if defined(AES) +#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN +#endif /* AES */ +#if defined(HASH) +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#endif /* HASH */ +#if defined(RCC_AHB2ENR_RNGEN) +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#endif /* RCC_AHB2ENR_RNGEN */ +#if defined(USB_OTG_FS) +#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN +#endif /* USB_OTG_FS */ +/** + * @} + */ +#endif /* RCC_AHB2_SUPPORT */ + +#if defined(RCC_AHB3_SUPPORT) +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(FSMC_Bank1) +#define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN +#endif /* FSMC_Bank1 */ +#if defined(FMC_Bank1) +#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN +#endif /* FMC_Bank1 */ +#if defined(QUADSPI) +#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN +#endif /* QUADSPI */ +/** + * @} + */ +#endif /* RCC_AHB3_SUPPORT */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(TIM2) +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#endif /* TIM2 */ +#if defined(TIM3) +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#endif /* TIM3 */ +#if defined(TIM4) +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN +#endif /* TIM4 */ +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN +#if defined(TIM6) +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#endif /* TIM6 */ +#if defined(TIM7) +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#endif /* TIM7 */ +#if defined(TIM12) +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN +#endif /* TIM12 */ +#if defined(TIM13) +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN +#endif /* TIM13 */ +#if defined(TIM14) +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN +#endif /* TIM14 */ +#if defined(LPTIM1) +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN +#endif /* LPTIM1 */ +#if defined(RCC_APB1ENR_RTCAPBEN) +#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN +#endif /* RCC_APB1ENR_RTCAPBEN */ +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#endif /* SPI2 */ +#if defined(SPI3) +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN +#endif /* SPI3 */ +#if defined(SPDIFRX) +#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN +#endif /* SPDIFRX */ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#endif /* USART3 */ +#if defined(UART4) +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN +#endif /* UART4 */ +#if defined(UART5) +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN +#endif /* UART5 */ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#if defined(I2C3) +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN +#endif /* I2C3 */ +#if defined(FMPI2C1) +#define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN +#endif /* FMPI2C1 */ +#if defined(CAN1) +#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN +#endif /* CAN1 */ +#if defined(CAN2) +#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN +#endif /* CAN2 */ +#if defined(CAN3) +#define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN +#endif /* CAN3 */ +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN +#endif /* CEC */ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#if defined(DAC1) +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN +#endif /* DAC1 */ +#if defined(UART7) +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN +#endif /* UART7 */ +#if defined(UART8) +#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN +#endif /* UART8 */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#if defined(TIM8) +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#endif /* TIM8 */ +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#if defined(USART6) +#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN +#endif /* USART6 */ +#if defined(UART9) +#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN +#endif /* UART9 */ +#if defined(UART10) +#define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN +#endif /* UART10 */ +#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#if defined(ADC2) +#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN +#endif /* ADC2 */ +#if defined(ADC3) +#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN +#endif /* ADC3 */ +#if defined(SDIO) +#define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN +#endif /* SDIO */ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#if defined(SPI4) +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#endif /* SPI4 */ +#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN +#if defined(RCC_APB2ENR_EXTITEN) +#define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN +#endif /* RCC_APB2ENR_EXTITEN */ +#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN +#if defined(TIM10) +#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN +#endif /* TIM10 */ +#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN +#if defined(SPI5) +#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN +#endif /* SPI5 */ +#if defined(SPI6) +#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN +#endif /* SPI6 */ +#if defined(SAI1) +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#endif /* SAI1 */ +#if defined(SAI2) +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#endif /* SAI2 */ +#if defined(LTDC) +#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN +#endif /* LTDC */ +#if defined(DSI) +#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN +#endif /* DSI */ +#if defined(DFSDM1_Channel0) +#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN +#endif /* DFSDM1_Channel0 */ +#if defined(DFSDM2_Channel0) +#define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN +#endif /* DFSDM2_Channel0 */ +#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripheral clocks in low-power mode + * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripheral clocks in low-power mode + * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +#if defined(RCC_AHB2_SUPPORT) +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripheral clocks in low-power mode + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB2 peripheral clocks in low-power mode + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2LPENR, Periphs); +} + +/** + * @} + */ +#endif /* RCC_AHB2_SUPPORT */ + +#if defined(RCC_AHB3_SUPPORT) +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripheral clocks in low-power mode + * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB3 peripheral clocks in low-power mode + * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3LPENR, Periphs); +} + +/** + * @} + */ +#endif /* RCC_AHB3_SUPPORT */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n + * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n + * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in low-power mode + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripheral clocks in low-power mode + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripheral clocks in low-power mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripheral clocks in low-power mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_BUS_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h new file mode 100644 index 00000000..9a183ea7 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h @@ -0,0 +1,647 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (MPU services provided only on some devices) + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_CORTEX_H +#define __STM32F4xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Clear pending events. + * @retval None + */ +__STATIC_INLINE void LL_LPM_ClearEvent(void) +{ + __SEV(); + __WFE(); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M4 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC24 for Cortex-M4 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_CORTEX_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h new file mode 100644 index 00000000..055ba5f2 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h @@ -0,0 +1,2868 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_DMA_H +#define __STM32F4xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ +static const uint8_t STREAM_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) +}; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Constants DMA Private Constants + * @{ + */ +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Stream + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t Channel; /*!< Specifies the peripheral channel. + This parameter can be a value of @ref DMA_LL_EC_CHANNEL + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_LL_FIFOMODE + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream + + This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_MBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_PBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_STREAM STREAM + * @{ + */ +#define LL_DMA_STREAM_0 0x00000000U +#define LL_DMA_STREAM_1 0x00000001U +#define LL_DMA_STREAM_2 0x00000002U +#define LL_DMA_STREAM_3 0x00000003U +#define LL_DMA_STREAM_4 0x00000004U +#define LL_DMA_STREAM_5 0x00000005U +#define LL_DMA_STREAM_6 0x00000006U +#define LL_DMA_STREAM_7 0x00000007U +#define LL_DMA_STREAM_ALL 0xFFFF0000U +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION DIRECTION + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE MODE + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ +#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE + * @{ + */ +#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ +#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH PERIPH + * @{ + */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY MEMORY + * @{ + */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE + * @{ + */ +#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ +#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY PRIORITY + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */ +#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */ +#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */ +#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */ +#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */ +#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */ +#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */ +#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */ +#if defined (DMA_SxCR_CHSEL_3) +#define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */ +#define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */ +#define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */ +#define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */ +#define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */ +#define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */ +#define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */ +#define LL_DMA_CHANNEL_15 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel15 of DMA Instance */ +#endif /* DMA_SxCR_CHSEL_3 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MBURST MBURST + * @{ + */ +#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ +#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ +#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ +#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PBURST PBURST + * @{ + */ +#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ +#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ +#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ +#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE + * @{ + */ +#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ +#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 + * @{ + */ +#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ +#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ +#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ +#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ +#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ +#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD + * @{ + */ +#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ +#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ +#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM + * @{ + */ +#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ +#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy + * @{ + */ +/** + * @brief Convert DMAx_Streamy into DMAx + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval DMAx + */ +#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) + +/** + * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval LL_DMA_CHANNEL_y + */ +#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ + LL_DMA_STREAM_7) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy + * @param __DMA_INSTANCE__ DMAx + * @param __STREAM__ LL_DMA_STREAM_y + * @retval DMAx_Streamy + */ +#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ + DMA2_Stream7) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA stream. + * @rmtoll CR EN LL_DMA_EnableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); +} + +/** + * @brief Disable DMA stream. + * @rmtoll CR EN LL_DMA_DisableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); +} + +/** + * @brief Check if DMA stream is enabled or disabled. + * @rmtoll CR EN LL_DMA_IsEnabledStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); +} + +/** + * @brief Configure all parameters linked to DMA transfer. + * @rmtoll CR DIR LL_DMA_ConfigTransfer\n + * CR CIRC LL_DMA_ConfigTransfer\n + * CR PINC LL_DMA_ConfigTransfer\n + * CR MINC LL_DMA_ConfigTransfer\n + * CR PSIZE LL_DMA_ConfigTransfer\n + * CR MSIZE LL_DMA_ConfigTransfer\n + * CR PL LL_DMA_ConfigTransfer\n + * CR PFCTRL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + *@retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, + DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR)); +} + +/** + * @brief Set DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_SetMode\n + * CR PFCTRL LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); +} + +/** + * @brief Get DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_GetMode\n + * CR PFCTRL LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size); +} + +/** + * @brief Get Memory size. + * @rmtoll CR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE)); +} + +/** + * @brief Set Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param OffsetSize This parameter can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize); +} + +/** + * @brief Get Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + */ +__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS)); +} + +/** + * @brief Set Stream priority level. + * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority); +} + +/** + * @brief Get Stream priority level. + * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_SetDataLength + * @note This action has no effect if + * stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param NbData Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_GetDataLength + * @note Once the stream is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT)); +} + +/** + * @brief Select Channel number associated to the Stream. + * @rmtoll CR CHSEL LL_DMA_SetChannelSelection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel); +} + +/** + * @brief Get the Channel number associated to the Stream. + * @rmtoll CR CHSEL LL_DMA_GetChannelSelection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL)); +} + +/** + * @brief Set Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mburst This parameter can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst); +} + +/** + * @brief Get Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST)); +} + +/** + * @brief Set Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Pburst This parameter can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst); +} + +/** + * @brief Get Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST)); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_SetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param CurrentMemory This parameter can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory); +} + +/** + * @brief Get Current target (only in double buffer mode). + * @rmtoll CR CT LL_DMA_GetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT)); +} + +/** + * @brief Enable the double buffer mode. + * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Disable the double buffer mode. + * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Get FIFO status. + * @rmtoll FCR FS LL_DMA_GetFIFOStatus + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOSTATUS_0_25 + * @arg @ref LL_DMA_FIFOSTATUS_25_50 + * @arg @ref LL_DMA_FIFOSTATUS_50_75 + * @arg @ref LL_DMA_FIFOSTATUS_75_100 + * @arg @ref LL_DMA_FIFOSTATUS_EMPTY + * @arg @ref LL_DMA_FIFOSTATUS_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); +} + +/** + * @brief Disable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Enable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Select FIFO threshold. + * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold); +} + +/** + * @brief Get FIFO threshold. + * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); +} + +/** + * @brief Configure the FIFO . + * @rmtoll FCR FTH LL_DMA_ConfigFifo\n + * FCR DMDIS LL_DMA_ConfigFifo + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param FifoMode This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOMODE_ENABLE + * @arg @ref LL_DMA_FIFOMODE_DISABLE + * @param FifoThreshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA stream is enabled. + * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n + * PAR PA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DstAddress Between 0 to 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @rmtoll PAR PA LL_DMA_SetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param PeriphAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress); +} + +/** + * @brief Get the Memory address. + * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); +} + +/** + * @brief Get the Peripheral address. + * @rmtoll PAR PA LL_DMA_GetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); + } + +/** + * @brief Get the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) + { + return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); + } + +/** + * @brief Get the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); +} + +/** + * @brief Set Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_SetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Address Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, Address); +} + +/** + * @brief Get Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_GetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Stream 0 half transfer flag. + * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); +} + +/** + * @brief Get Stream 1 half transfer flag. + * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); +} + +/** + * @brief Get Stream 2 half transfer flag. + * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); +} + +/** + * @brief Get Stream 3 half transfer flag. + * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); +} + +/** + * @brief Get Stream 4 half transfer flag. + * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); +} + +/** + * @brief Get Stream 5 half transfer flag. + * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); +} + +/** + * @brief Get Stream 6 half transfer flag. + * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); +} + +/** + * @brief Get Stream 7 half transfer flag. + * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); +} + +/** + * @brief Get Stream 0 transfer complete flag. + * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); +} + +/** + * @brief Get Stream 1 transfer complete flag. + * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); +} + +/** + * @brief Get Stream 2 transfer complete flag. + * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); +} + +/** + * @brief Get Stream 3 transfer complete flag. + * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); +} + +/** + * @brief Get Stream 4 transfer complete flag. + * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); +} + +/** + * @brief Get Stream 5 transfer complete flag. + * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); +} + +/** + * @brief Get Stream 6 transfer complete flag. + * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); +} + +/** + * @brief Get Stream 7 transfer complete flag. + * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); +} + +/** + * @brief Get Stream 0 transfer error flag. + * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); +} + +/** + * @brief Get Stream 1 transfer error flag. + * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); +} + +/** + * @brief Get Stream 2 transfer error flag. + * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); +} + +/** + * @brief Get Stream 3 transfer error flag. + * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); +} + +/** + * @brief Get Stream 4 transfer error flag. + * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); +} + +/** + * @brief Get Stream 5 transfer error flag. + * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); +} + +/** + * @brief Get Stream 6 transfer error flag. + * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); +} + +/** + * @brief Get Stream 7 transfer error flag. + * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); +} + +/** + * @brief Get Stream 0 direct mode error flag. + * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); +} + +/** + * @brief Get Stream 1 direct mode error flag. + * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); +} + +/** + * @brief Get Stream 2 direct mode error flag. + * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); +} + +/** + * @brief Get Stream 3 direct mode error flag. + * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); +} + +/** + * @brief Get Stream 4 direct mode error flag. + * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); +} + +/** + * @brief Get Stream 5 direct mode error flag. + * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); +} + +/** + * @brief Get Stream 6 direct mode error flag. + * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); +} + +/** + * @brief Get Stream 7 direct mode error flag. + * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); +} + +/** + * @brief Get Stream 0 FIFO error flag. + * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); +} + +/** + * @brief Get Stream 1 FIFO error flag. + * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); +} + +/** + * @brief Get Stream 2 FIFO error flag. + * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); +} + +/** + * @brief Get Stream 3 FIFO error flag. + * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); +} + +/** + * @brief Get Stream 4 FIFO error flag. + * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); +} + +/** + * @brief Get Stream 5 FIFO error flag. + * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); +} + +/** + * @brief Get Stream 6 FIFO error flag. + * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); +} + +/** + * @brief Get Stream 7 FIFO error flag. + * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); +} + +/** + * @brief Clear Stream 0 half transfer flag. + * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); +} + +/** + * @brief Clear Stream 1 half transfer flag. + * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); +} + +/** + * @brief Clear Stream 2 half transfer flag. + * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); +} + +/** + * @brief Clear Stream 3 half transfer flag. + * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); +} + +/** + * @brief Clear Stream 4 half transfer flag. + * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); +} + +/** + * @brief Clear Stream 5 half transfer flag. + * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); +} + +/** + * @brief Clear Stream 6 half transfer flag. + * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); +} + +/** + * @brief Clear Stream 7 half transfer flag. + * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); +} + +/** + * @brief Clear Stream 0 transfer complete flag. + * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); +} + +/** + * @brief Clear Stream 1 transfer complete flag. + * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); +} + +/** + * @brief Clear Stream 2 transfer complete flag. + * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); +} + +/** + * @brief Clear Stream 3 transfer complete flag. + * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); +} + +/** + * @brief Clear Stream 4 transfer complete flag. + * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); +} + +/** + * @brief Clear Stream 5 transfer complete flag. + * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); +} + +/** + * @brief Clear Stream 6 transfer complete flag. + * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); +} + +/** + * @brief Clear Stream 7 transfer complete flag. + * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); +} + +/** + * @brief Clear Stream 0 transfer error flag. + * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); +} + +/** + * @brief Clear Stream 1 transfer error flag. + * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); +} + +/** + * @brief Clear Stream 2 transfer error flag. + * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); +} + +/** + * @brief Clear Stream 3 transfer error flag. + * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); +} + +/** + * @brief Clear Stream 4 transfer error flag. + * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); +} + +/** + * @brief Clear Stream 5 transfer error flag. + * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); +} + +/** + * @brief Clear Stream 6 transfer error flag. + * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); +} + +/** + * @brief Clear Stream 7 transfer error flag. + * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); +} + +/** + * @brief Clear Stream 0 direct mode error flag. + * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); +} + +/** + * @brief Clear Stream 1 direct mode error flag. + * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); +} + +/** + * @brief Clear Stream 2 direct mode error flag. + * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); +} + +/** + * @brief Clear Stream 3 direct mode error flag. + * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); +} + +/** + * @brief Clear Stream 4 direct mode error flag. + * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); +} + +/** + * @brief Clear Stream 5 direct mode error flag. + * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); +} + +/** + * @brief Clear Stream 6 direct mode error flag. + * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); +} + +/** + * @brief Clear Stream 7 direct mode error flag. + * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); +} + +/** + * @brief Clear Stream 0 FIFO error flag. + * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); +} + +/** + * @brief Clear Stream 1 FIFO error flag. + * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); +} + +/** + * @brief Clear Stream 2 FIFO error flag. + * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); +} + +/** + * @brief Clear Stream 3 FIFO error flag. + * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); +} + +/** + * @brief Clear Stream 4 FIFO error flag. + * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); +} + +/** + * @brief Clear Stream 5 FIFO error flag. + * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); +} + +/** + * @brief Clear Stream 6 FIFO error flag. + * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); +} + +/** + * @brief Clear Stream 7 FIFO error flag. + * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Enable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_EnableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Enable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_EnableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Disable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_DisableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Disable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_DisableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Check if Half transfer interrupt is enabled. + * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); +} + +/** + * @brief Check if Transfer error nterrup is enabled. + * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE); +} + +/** + * @brief Check if Transfer complete interrupt is enabled. + * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); +} + +/** + * @brief Check if Direct mode error interrupt is enabled. + * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE); +} + +/** + * @brief Check if FIFO error interrupt is enabled. + * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_DMA_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h new file mode 100644 index 00000000..65ab6918 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h @@ -0,0 +1,954 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS.Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_EXTI_H +#define __STM32F4xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#if defined(EXTI_IMR_IM23) +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#endif +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_EXTI_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h new file mode 100644 index 00000000..6bee7fd1 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h @@ -0,0 +1,981 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_GPIO_H +#define __STM32F4xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + GPIO_BSRR_BS_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, + (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), + (Speed << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, + (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, + (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)), + (Alternate << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)), + (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, (PinMask << 16)); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_GPIO_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h new file mode 100644 index 00000000..5a17be59 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h @@ -0,0 +1,1890 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_i2c.h + * @author MCD Application Team + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_I2C_H +#define __STM32F4xx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ + +/* Defines used to perform compute and check in the macros */ +#define LL_I2C_MAX_SPEED_STANDARD 100000U +#define LL_I2C_MAX_SPEED_FAST 400000U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_Private_Macros I2C Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ + + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz (in Hz) + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod() + or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */ + +#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) + uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION + + This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + + uint32_t DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ + +#endif + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE + + This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */ +#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or + Address matched flag (slave mode) */ +#define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */ +#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */ +#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */ +#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */ +#define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */ +#define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */ +#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */ +#define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */ +#define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */ +#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */ +#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */ +#define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */ +#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */ +#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */ +#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */ +#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */ +#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */ +#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */ +/** + * @} + */ + +#if defined(I2C_FLTR_ANOFF) +/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF /*!< Analog filter is disabled.*/ +/** + * @} + */ + +#endif +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle + * @{ + */ +#define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */ +#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode + * @{ + */ +#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */ +#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */ +#define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported Macros Helper + * @{ + */ + +/** + * @brief Convert Peripheral Clock Frequency in Mhz. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @retval Value of peripheral clock (in Mhz) + */ +#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U) + +/** + * @brief Convert Peripheral Clock Frequency in Hz. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz). + * @retval Value of peripheral clock (in Hz) + */ +#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U) + +/** + * @brief Compute I2C Clock rising time. + * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz). + * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). + * @retval Value between Min_Data=0x02 and Max_Data=0x3F + */ +#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) + +/** + * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). + * @param __DUTYCYCLE__ This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + */ +#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \ + (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \ + (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__)))) + +/** + * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz). + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF. + */ +#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) + +/** + * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz). + * @param __DUTYCYCLE__ This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval Value between Min_Data=0x001 and Max_Data=0xFFF + */ +#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \ + (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \ + (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U)))) + +/** + * @brief Get the Least significant bits of a 10-Bits address. + * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) + +/** + * @brief Convert a 10-Bits address to a 10-Bits header with Write direction. + * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. + * @retval Value between Min_Data=0xF0 and Max_Data=0xF6 + */ +#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) + +/** + * @brief Convert a 10-Bits address to a 10-Bits header with Read direction. + * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. + * @retval Value between Min_Data=0xF1 and Max_Data=0xF7 + */ +#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); +} + +#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) +/** + * @brief Configure Noise Filters (Analog and Digital). + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll FLTR ANOFF LL_I2C_ConfigFilters\n + * FLTR DNF LL_I2C_ConfigFilters + * @param I2Cx I2C Instance. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1) + * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter); +} +#endif +#if defined(I2C_FLTR_DNF) + +/** + * @brief Configure Digital Noise Filter. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll FLTR DNF LL_I2C_SetDigitalFilter + * @param I2Cx I2C Instance. + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1) + * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll FLTR DNF LL_I2C_GetDigitalFilter + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF)); +} +#endif +#if defined(I2C_FLTR_ANOFF) + +/** + * @brief Enable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll FLTR ANOFF LL_I2C_EnableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll FLTR ANOFF LL_I2C_DisableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll FLTR ANOFF LL_I2C_IsEnabledAnalogFilter + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF)); +} +#endif + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); +} + +/** + * @brief Get the data register address used for DMA transfer. + * @rmtoll DR DR LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance. + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx) +{ + return (uint32_t) & (I2Cx->DR); +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); +} + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ENGC); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n + * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n + * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n + * OAR1 ADDMODE LL_I2C_SetOwnAddress1 + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2 + * @param I2Cx I2C Instance. + * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2) +{ + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL)); +} + +/** + * @brief Configure the Peripheral clock frequency. + * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock + * @param I2Cx I2C Instance. + * @param PeriphClock Peripheral Clock (in Hz) + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock)); +} + +/** + * @brief Get the Peripheral clock frequency. + * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock + * @param I2Cx I2C Instance. + * @retval Value of Peripheral Clock (in Hz) + */ +__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ))); +} + +/** + * @brief Configure the Duty cycle (Fast mode only). + * @rmtoll CCR DUTY LL_I2C_SetDutyCycle + * @param I2Cx I2C Instance. + * @param DutyCycle This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle); +} + +/** + * @brief Get the Duty cycle (Fast mode only). + * @rmtoll CCR DUTY LL_I2C_GetDutyCycle + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + */ +__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY)); +} + +/** + * @brief Configure the I2C master clock speed mode. + * @rmtoll CCR FS LL_I2C_SetClockSpeedMode + * @param I2Cx I2C Instance. + * @param ClockSpeedMode This parameter can be one of the following values: + * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE + * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode); +} + +/** + * @brief Get the the I2C master speed mode. + * @rmtoll CCR FS LL_I2C_GetClockSpeedMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE + * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS)); +} + +/** + * @brief Configure the SCL, SDA rising time. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TRISE TRISE LL_I2C_SetRiseTime + * @param I2Cx I2C Instance. + * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime) +{ + MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime); +} + +/** + * @brief Get the SCL, SDA rising time. + * @rmtoll TRISE TRISE LL_I2C_GetRiseTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x02 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE)); +} + +/** + * @brief Configure the SCL high and low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CCR CCR LL_I2C_SetClockPeriod + * @param I2Cx I2C Instance. + * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod); +} + +/** + * @brief Get the SCL high and low period. + * @rmtoll CCR CCR LL_I2C_GetClockPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR)); +} + +/** + * @brief Configure the SCL speed. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n + * TRISE TRISE LL_I2C_ConfigSpeed\n + * CCR FS LL_I2C_ConfigSpeed\n + * CCR DUTY LL_I2C_ConfigSpeed\n + * CCR CCR LL_I2C_ConfigSpeed + * @param I2Cx I2C Instance. + * @param PeriphClock Peripheral Clock (in Hz) + * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz). + * @param DutyCycle This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed, + uint32_t DutyCycle) +{ + uint32_t freqrange = 0x0U; + uint32_t clockconfig = 0x0U; + + /* Compute frequency range */ + freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock); + + /* Configure I2Cx: Frequency range register */ + MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange); + + /* Configure I2Cx: Rise Time register */ + MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed)); + + /* Configure Speed mode, Duty Cycle and Clock control register value */ + if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD) + { + /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */ + clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \ + __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \ + DutyCycle; + } + else + { + /* Set Speed mode at standard for Clock Speed request in standard clock range */ + clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \ + __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed); + } + + /* Configure I2Cx: Clock control register */ + MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig); +} + +/** + * @brief Configure peripheral mode. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBUS LL_I2C_SetMode\n + * CR1 SMBTYPE LL_I2C_SetMode\n + * CR1 ENARP LL_I2C_SetMode + * @param I2Cx I2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBUS LL_I2C_GetMode\n + * CR1 SMBTYPE LL_I2C_GetMode\n + * CR1 ENARP LL_I2C_GetMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ALERT); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT)); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC)); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n + * CR2 ITBUFEN LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable TXE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n + * CR2 ITBUFEN LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if the TXE Interrupt is enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n + * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n + * CR2 ITBUFEN LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n + * CR2 ITBUFEN LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n + * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable Events interrupts. + * @note Any of these events will generate interrupt : + * Start Bit (SB) + * Address sent, Address matched (ADDR) + * 10-bit header sent (ADD10) + * Stop detection (STOPF) + * Byte transfer finished (BTF) + * + * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); +} + +/** + * @brief Disable Events interrupts. + * @note Any of these events will generate interrupt : + * Start Bit (SB) + * Address sent, Address matched (ADDR) + * 10-bit header sent (ADD10) + * Stop detection (STOPF) + * Byte transfer finished (BTF) + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); +} + +/** + * @brief Check if Events interrupts are enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN)); +} + +/** + * @brief Enable Buffer interrupts. + * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable Buffer interrupts. + * @note Any of these Buffer events will generate interrupt : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if Buffer interrupts are enabled or disabled. + * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable Error interrupts. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Bus Error detection (BERR) + * Arbitration Loss (ARLO) + * Acknowledge Failure(AF) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (SMBALERT) + * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN); +} + +/** + * @brief Disable Error interrupts. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Bus Error detection (BERR) + * Arbitration Loss (ARLO) + * Acknowledge Failure(AF) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (SMBALERT) + * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN)); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE)); +} + +/** + * @brief Indicate the status of Byte Transfer Finished flag. + * RESET: When Data byte transfer not done. + * SET: When Data byte transfer succeeded. + * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF)); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE)); +} + +/** + * @brief Indicate the status of Start Bit (master mode). + * @note RESET: When No Start condition. + * SET: When Start condition is generated. + * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB)); +} + +/** + * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode). + * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR)); +} + +/** + * @brief Indicate the status of 10-bit header sent (master mode). + * @note RESET: When no ADD10 event occurred. + * SET: When the master has sent the first address byte (header). + * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10)); +} + +/** + * @brief Indicate the status of Acknowledge failure flag. + * @note RESET: No acknowledge failure. + * SET: When an acknowledge failure is received after a byte transmission. + * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF)); +} + +/** + * @brief Indicate the status of Stop detection flag (slave mode). + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF)); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR)); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO)); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag. + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR)); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR)); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT)); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT)); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY)); +} + +/** + * @brief Indicate the status of Dual flag. + * @note RESET: Received address matched with OAR1. + * SET: Received address matched with OAR2. + * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF)); +} + +/** + * @brief Indicate the status of SMBus Host address reception (Slave mode). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: No SMBus Host address + * SET: SMBus Host address received. + * @note This status is cleared by hardware after a STOP condition or repeated START condition. + * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST)); +} + +/** + * @brief Indicate the status of SMBus Device default address reception (Slave mode). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: No SMBus Device default address + * SET: SMBus Device default address received. + * @note This status is cleared by hardware after a STOP condition or repeated START condition. + * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT)); +} + +/** + * @brief Indicate the status of General call address reception (Slave mode). + * @note RESET: No General call address + * SET: General call address received. + * @note This status is cleared by hardware after a STOP condition or repeated START condition. + * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL)); +} + +/** + * @brief Indicate the status of Master/Slave flag. + * @note RESET: Slave Mode. + * SET: Master Mode. + * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL)); +} + +/** + * @brief Clear Address Matched flag. + * @note Clearing this flag is done by a read access to the I2Cx_SR1 + * register followed by a read access to the I2Cx_SR2 register. + * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + __IO uint32_t tmpreg; + tmpreg = I2Cx->SR1; + (void) tmpreg; + tmpreg = I2Cx->SR2; + (void) tmpreg; +} + +/** + * @brief Clear Acknowledge failure flag. + * @rmtoll SR1 AF LL_I2C_ClearFlag_AF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF); +} + +/** + * @brief Clear Stop detection flag. + * @note Clearing this flag is done by a read access to the I2Cx_SR1 + * register followed by a write access to I2Cx_CR1 register. + * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n + * CR1 PE LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + __IO uint32_t tmpreg; + tmpreg = I2Cx->SR1; + (void) tmpreg; + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR); +} + +/** + * @brief Clear SMBus PEC error flag. + * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT); +} + +/** + * @brief Clear SMBus Alert flag. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable Reset of I2C peripheral. + * @rmtoll CR1 SWRST LL_I2C_EnableReset + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SWRST); +} + +/** + * @brief Disable Reset of I2C peripheral. + * @rmtoll CR1 SWRST LL_I2C_DisableReset + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST); +} + +/** + * @brief Check if the I2C peripheral is under reset state or not. + * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST)); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @note Usage in Slave or Master mode. + * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR1 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOP); +} + +/** + * @brief Enable bit POS (master/host mode). + * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC. + * @rmtoll CR1 POS LL_I2C_EnableBitPOS + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_POS); +} + +/** + * @brief Disable bit POS (master/host mode). + * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC. + * @rmtoll CR1 POS LL_I2C_DisableBitPOS + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS); +} + +/** + * @brief Check if bit POS is enabled or disabled. + * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS)); +} + +/** + * @brief Indicate the value of transfer direction. + * @note RESET: Bus is in read transfer (peripheral point of view). + * SET: Bus is in write transfer (peripheral point of view). + * @rmtoll SR2 TRA LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA)); +} + +/** + * @brief Enable DMA last transfer. + * @note This action mean that next DMA EOT is the last transfer. + * @rmtoll CR2 LAST LL_I2C_EnableLastDMA + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_LAST); +} + +/** + * @brief Disable DMA last transfer. + * @note This action mean that next DMA EOT is not the last transfer. + * @rmtoll CR2 LAST LL_I2C_DisableLastDMA + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST); +} + +/** + * @brief Check if DMA last transfer is enabled or disabled. + * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST)); +} + +/** + * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred or compared, + * or by a START or STOP condition, it is also cleared by software. + * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PEC); +} + +/** + * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC); +} + +/** + * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC)); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos); +} + +/** + * @brief Read Receive Data register. + * @rmtoll DR DR LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll DR DR LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); +uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_I2C_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h new file mode 100644 index 00000000..ea23dc52 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h @@ -0,0 +1,985 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_PWR_H +#define __STM32F4xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ +#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ +#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ +#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ +#define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */ +#if defined(PWR_CSR_EWUP) +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */ +#elif defined(PWR_CSR_EWUP1) +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ +#endif /* PWR_CSR_EWUP */ +#if defined(PWR_CSR_EWUP2) +#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ +#endif /* PWR_CSR_EWUP2 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ +#endif /* PWR_CSR_EWUP3 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage + * @{ + */ +#if defined(PWR_CR_VOS_0) +#define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0) +#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */ +#else +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS) +#define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U +#endif /* PWR_CR_VOS_0 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ +#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) +#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */ +#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ +#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) +#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */ +#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ +/** + * @} + */ +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#if defined(PWR_CSR_EWUP) +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */ +#endif /* PWR_CSR_EWUP */ +#if defined(PWR_CSR_EWUP1) +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ +#endif /* PWR_CSR_EWUP1 */ +#if defined(PWR_CSR_EWUP2) +#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */ +#endif /* PWR_CSR_EWUP2 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */ +#endif /* PWR_CSR_EWUP3 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ +#if defined(PWR_CR_FISSR) +/** + * @brief Enable FLASH interface STOP while system Run is ON + * @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP + * @note This mode is enabled only with STOP low power mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void) +{ + SET_BIT(PWR->CR, PWR_CR_FISSR); +} + +/** + * @brief Disable FLASH Interface STOP while system Run is ON + * @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_FISSR); +} + +/** + * @brief Check if FLASH Interface STOP while system Run feature is enabled + * @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR)); +} +#endif /* PWR_CR_FISSR */ + +#if defined(PWR_CR_FMSSR) +/** + * @brief Enable FLASH Memory STOP while system Run is ON + * @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP + * @note This mode is enabled only with STOP low power mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void) +{ + SET_BIT(PWR->CR, PWR_CR_FMSSR); +} + +/** + * @brief Disable FLASH Memory STOP while system Run is ON + * @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); +} + +/** + * @brief Check if FLASH Memory STOP while system Run feature is enabled + * @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR)); +} +#endif /* PWR_CR_FMSSR */ +#if defined(PWR_CR_UDEN) +/** + * @brief Enable Under Drive Mode + * @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main Regulator or the low power Regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage Regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_UDEN); +} + +/** + * @brief Disable Under Drive Mode + * @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_UDEN); +} + +/** + * @brief Check if Under Drive Mode is enabled + * @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN)); +} +#endif /* PWR_CR_UDEN */ + +#if defined(PWR_CR_ODSWEN) +/** + * @brief Enable Over drive switching + * @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void) +{ + SET_BIT(PWR->CR, PWR_CR_ODSWEN); +} + +/** + * @brief Disable Over drive switching + * @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN); +} + +/** + * @brief Check if Over drive switching is enabled + * @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN)); +} +#endif /* PWR_CR_ODSWEN */ +#if defined(PWR_CR_ODEN) +/** + * @brief Enable Over drive Mode + * @rmtoll CR ODEN LL_PWR_EnableOverDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_ODEN); +} + +/** + * @brief Disable Over drive Mode + * @rmtoll CR ODEN LL_PWR_DisableOverDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_ODEN); +} + +/** + * @brief Check if Over drive switching is enabled + * @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN)); +} +#endif /* PWR_CR_ODEN */ +#if defined(PWR_CR_MRUDS) +/** + * @brief Enable Main Regulator in deepsleep under-drive Mode + * @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_MRUDS); +} + +/** + * @brief Disable Main Regulator in deepsleep under-drive Mode + * @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_MRUDS); +} + +/** + * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled + * @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS)); +} +#endif /* PWR_CR_MRUDS */ + +#if defined(PWR_CR_LPUDS) +/** + * @brief Enable Low Power Regulator in deepsleep under-drive Mode + * @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_LPUDS); +} + +/** + * @brief Disable Low Power Regulator in deepsleep under-drive Mode + * @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_LPUDS); +} + +/** + * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled + * @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS)); +} +#endif /* PWR_CR_LPUDS */ + +#if defined(PWR_CR_MRLVDS) +/** + * @brief Enable Main Regulator low voltage Mode + * @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_MRLVDS); +} + +/** + * @brief Disable Main Regulator low voltage Mode + * @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS); +} + +/** + * @brief Check if Main Regulator low voltage Mode is enabled + * @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS)); +} +#endif /* PWR_CR_MRLVDS */ + +#if defined(PWR_CR_LPLVDS) +/** + * @brief Enable Low Power Regulator low voltage Mode + * @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_LPLVDS); +} + +/** + * @brief Disable Low Power Regulator low voltage Mode + * @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS); +} + +/** + * @brief Check if Low Power Regulator low voltage Mode is enabled + * @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS)); +} +#endif /* PWR_CR_LPLVDS */ +/** + * @brief Set the main internal Regulator output voltage + * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*) + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling); +} + +/** + * @brief Get the main internal Regulator output voltage + * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*) + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS)); +} +/** + * @brief Enable the Flash Power Down in Stop Mode + * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) +{ + SET_BIT(PWR->CR, PWR_CR_FPDS); +} + +/** + * @brief Disable the Flash Power Down in Stop Mode + * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_FPDS); +} + +/** + * @brief Check if the Flash Power Down in Stop Mode is enabled + * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); +} +/** + * @brief Enable the backup Regulator + * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator + * @note The BRE bit of the PWR_CSR register is protected against parasitic write access. + * The LL_PWR_EnableBkUpAccess() must be called before using this API. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) +{ + SET_BIT(PWR->CSR, PWR_CSR_BRE); +} + +/** + * @brief Disable the backup Regulator + * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator + * @note The BRE bit of the PWR_CSR register is protected against parasitic write access. + * The LL_PWR_EnableBkUpAccess() must be called before using this API. + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) +{ + CLEAR_BIT(PWR->CSR, PWR_CSR_BRE); +} + +/** + * @brief Check if the backup Regulator is enabled + * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE)); +} + +/** + * @brief Set voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); +} + +/** + * @brief Get voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); +} + +/** + * @brief Set Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_SetPowerMode\n + * @rmtoll CR MRUDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPUDS LL_PWR_SetPowerMode\n + * @rmtoll CR FPDS LL_PWR_SetPowerMode\n + * @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n + * @rmtoll CR FPDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*) + * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*) + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*) + * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*) + * + * (*) not available on all devices + * @arg @ref LL_PWR_MODE_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ +#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode); +#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode); +#else + MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); +#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ +} + +/** + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode\n + * @rmtoll CR MRUDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPUDS LL_PWR_GetPowerMode\n + * @rmtoll CR FPDS LL_PWR_GetPowerMode\n + * @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n + * @rmtoll CR FPDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*) + * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*) + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*) + * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*) + * + * (*) not available on all devices + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ +#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS))); +#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS))); +#else + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); +#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); +} + + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag + * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); +} + +/** + * @brief Get Backup Regulator ready Flag + * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR)); +} +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); +} + +/** + * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level + * @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ + return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS)); +} +#if defined(PWR_CR_ODEN) +/** + * @brief Indicate whether the Over-Drive mode is ready or not + * @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY)); +} +#endif /* PWR_CR_ODEN */ + +#if defined(PWR_CR_ODSWEN) +/** + * @brief Indicate whether the Over-Drive mode switching is ready or not + * @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY)); +} +#endif /* PWR_CR_ODSWEN */ + +#if defined(PWR_CR_UDEN) +/** + * @brief Indicate whether the Under-Drive mode is ready or not + * @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY)); +} +#endif /* PWR_CR_UDEN */ +/** + * @brief Clear Standby Flag + * @rmtoll CR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR, PWR_CR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll CR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + SET_BIT(PWR->CR, PWR_CR_CWUF); +} +#if defined(PWR_CSR_UDRDY) +/** + * @brief Clear Under-Drive ready Flag + * @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_UD(void) +{ + WRITE_REG(PWR->CSR, PWR_CSR_UDRDY); +} +#endif /* PWR_CSR_UDRDY */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_PWR_H */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h new file mode 100644 index 00000000..0a6a5b92 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h @@ -0,0 +1,7101 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_RCC_H +#define __STM32F4xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ + +#if defined(RCC_PLLSAI_SUPPORT) && defined(LTDC) +static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16}; +#endif /* RCC_PLLSAI_SUPPORT && LTDC */ + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#if defined(RCC_PLLI2S_SUPPORT) +#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */ +#endif /* RCC_PLLSAI_SUPPORT */ +#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#if defined(RCC_PLLI2S_SUPPORT) +#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */ +#endif /* RCC_PLLSAI_SUPPORT */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#if defined(RCC_CSR_BORRSTF) +#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ +#endif /* RCC_CSR_BORRSTF */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#if defined(RCC_PLLI2S_SUPPORT) +#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */ +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */ +#endif /* RCC_PLLSAI_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +#if defined(RCC_CFGR_SW_PLLR) +#define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */ +#endif /* RCC_CFGR_SW_PLLR */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +#if defined(RCC_PLLR_SYSCLK_SUPPORT) +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */ +#endif /* RCC_PLLR_SYSCLK_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */ +#if defined(RCC_CFGR_MCO2) +#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */ +#endif /* RCC_CFGR_MCO2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */ +#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */ +#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */ +#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */ +#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */ +#if defined(RCC_CFGR_MCO2PRE) +#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */ +#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */ +#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */ +#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */ +#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */ +#endif /* RCC_CFGR_MCO2PRE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock + * @{ + */ +#define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ +#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ +#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */ +#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ +#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */ +#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */ +#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */ +#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ +#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */ +#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */ +#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */ +#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */ +#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */ +#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */ +#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */ +#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ +#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */ +#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */ +#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */ +#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */ +#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */ +#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */ +#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */ +#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */ +#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */ +#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */ +#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */ +#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */ +#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */ +#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */ +#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +#if defined(FMPI2C1) +/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection + * @{ + */ +#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */ +#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */ +#define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */ +/** + * @} + */ +#endif /* FMPI2C1 */ + +#if defined(LPTIM1) +/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */ +/** + * @} + */ +#endif /* LPTIM1 */ + +#if defined(SAI1) +/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection + * @{ + */ +#if defined(RCC_DCKCFGR_SAI1SRC) +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */ +#endif /* RCC_DCKCFGR_SAI1SRC */ +#if defined(RCC_DCKCFGR_SAI2SRC) +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */ +#endif /* RCC_DCKCFGR_SAI2SRC */ +#if defined(RCC_DCKCFGR_SAI1ASRC) +#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT) +#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */ +#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */ +#define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */ +#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */ +#else +#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */ +#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */ +#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */ +#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */ +#endif /* RCC_DCKCFGR_SAI1ASRC */ +#if defined(RCC_DCKCFGR_SAI1BSRC) +#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT) +#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */ +#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */ +#define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */ +#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */ +#else +#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */ +#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */ +#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */ +#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */ +#endif /* RCC_DCKCFGR_SAI1BSRC */ +/** + * @} + */ +#endif /* SAI1 */ + +#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) +/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection + * @{ + */ +#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */ +#if defined(RCC_DCKCFGR_SDIOSEL) +#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */ +#else +#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */ +#endif /* RCC_DCKCFGR_SDIOSEL */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ +#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */ +#define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */ +/** + * @} + */ +#endif /* CEC */ + +/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#if defined(RCC_CFGR_I2SSRC) +#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */ +#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */ +#endif /* RCC_CFGR_I2SSRC */ +#if defined(RCC_DCKCFGR_I2SSRC) +#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */ +#endif /* RCC_DCKCFGR_I2SSRC */ +#if defined(RCC_DCKCFGR_I2S1SRC) +#define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */ +#endif /* RCC_DCKCFGR_I2S1SRC */ +#if defined(RCC_DCKCFGR_I2S2SRC) +#define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */ +#endif /* RCC_DCKCFGR_I2S2SRC */ +/** + * @} + */ + +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection + * @{ + */ +#if defined(RCC_DCKCFGR_CK48MSEL) +#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ +#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ +#endif /* RCC_DCKCFGR_CK48MSEL */ +#if defined(RCC_DCKCFGR2_CK48MSEL) +#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ +#endif /* RCC_PLLSAI_SUPPORT */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) +#define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */ +#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ +#endif /* RCC_DCKCFGR2_CK48MSEL */ +/** + * @} + */ + +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */ +#endif /* RCC_PLLSAI_SUPPORT */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) +#define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */ +#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ +/** + * @} + */ +#endif /* RNG */ + +#if defined(USB_OTG_FS) || defined(USB_OTG_HS) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */ +#endif /* RCC_PLLSAI_SUPPORT */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) +#define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */ +#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ +/** + * @} + */ +#endif /* USB_OTG_FS || USB_OTG_HS */ + +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ + +#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) +/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */ +#if defined(DFSDM2_Channel0) +#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */ +#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */ +#endif /* DFSDM2_Channel0 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection + * @{ + */ +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */ +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */ +#if defined(DFSDM2_Channel0) +#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */ +#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */ +#endif /* DFSDM2_Channel0 */ +/** + * @} + */ +#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ + +#if defined(FMPI2C1) +/** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source + * @{ + */ +#define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */ +/** + * @} + */ +#endif /* FMPI2C1 */ + +#if defined(SPDIFRX) +/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection + * @{ + */ +#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */ +#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */ +/** + * @} + */ +#endif /* SPDIFRX */ + +#if defined(LPTIM1) +/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */ +/** + * @} + */ +#endif /* LPTIM1 */ + +#if defined(SAI1) +/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source + * @{ + */ +#if defined(RCC_DCKCFGR_SAI1ASRC) +#define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */ +#endif /* RCC_DCKCFGR_SAI1ASRC */ +#if defined(RCC_DCKCFGR_SAI1BSRC) +#define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */ +#endif /* RCC_DCKCFGR_SAI1BSRC */ +#if defined(RCC_DCKCFGR_SAI1SRC) +#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */ +#endif /* RCC_DCKCFGR_SAI1SRC */ +#if defined(RCC_DCKCFGR_SAI2SRC) +#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */ +#endif /* RCC_DCKCFGR_SAI2SRC */ +/** + * @} + */ +#endif /* SAI1 */ + +#if defined(SDIO) +/** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source + * @{ + */ +#if defined(RCC_DCKCFGR_SDIOSEL) +#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */ +#elif defined(RCC_DCKCFGR2_SDIOSEL) +#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */ +#else +#define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */ +#endif /* RCC_DCKCFGR_SDIOSEL */ +/** + * @} + */ +#endif /* SDIO */ + +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source + * @{ + */ +#if defined(RCC_DCKCFGR_CK48MSEL) +#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */ +#endif /* RCC_DCKCFGR_CK48MSEL */ +#if defined(RCC_DCKCFGR2_CK48MSEL) +#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */ +#endif /* RCC_DCKCFGR_CK48MSEL */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ + +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +#define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */ +#else +#define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */ +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ +/** + * @} + */ +#endif /* RNG */ + +#if defined(USB_OTG_FS) || defined(USB_OTG_HS) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +#define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */ +#else +#define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */ +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ +/** + * @} + */ +#endif /* USB_OTG_FS || USB_OTG_HS */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */ +/** + * @} + */ +#endif /* CEC */ + +/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source + * @{ + */ +#if defined(RCC_CFGR_I2SSRC) +#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */ +#endif /* RCC_CFGR_I2SSRC */ +#if defined(RCC_DCKCFGR_I2SSRC) +#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */ +#endif /* RCC_DCKCFGR_I2SSRC */ +#if defined(RCC_DCKCFGR_I2S1SRC) +#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */ +#endif /* RCC_DCKCFGR_I2S1SRC */ +#if defined(RCC_DCKCFGR_I2S2SRC) +#define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */ +#endif /* RCC_DCKCFGR_I2S2SRC */ +/** + * @} + */ + +#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) +/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */ +#if defined(DFSDM2_Channel0) +#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */ +#endif /* DFSDM2_Channel0 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source + * @{ + */ +#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */ +#if defined(DFSDM2_Channel0) +#define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */ +#endif /* DFSDM2_Channel0 */ +/** + * @} + */ +#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ + +#if defined(SPDIFRX) +/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source + * @{ + */ +#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */ +/** + * @} + */ +#endif /* SPDIFRX */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */ +/** + * @} + */ +#endif /* LTDC */ + + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */ +/** + * @} + */ + +#if defined(RCC_DCKCFGR_TIMPRE) +/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + * @{ + */ +#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */ +#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_TIMPRE */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +#if defined(RCC_PLLI2SCFGR_PLLI2SSRC) +#define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */ +#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor + * @{ + */ +#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */ +#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */ +#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */ +#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */ +#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */ +#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */ +#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */ +#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */ +#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */ +#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */ +#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */ +#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */ +#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */ +#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */ +#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */ +#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */ +#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */ +#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */ +#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */ +#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */ +#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */ +#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */ +#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */ +#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */ +#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */ +#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */ +#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */ +#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */ +#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */ +#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */ +#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */ +#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */ +#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */ +#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */ +#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */ +#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */ +#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */ +#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */ +#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */ +#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */ +#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */ +#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */ +#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */ +#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */ +#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */ +#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */ +#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */ +#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */ +#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */ +#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */ +#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */ +#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */ +#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */ +#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */ +#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */ +#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */ +#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */ +#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */ +#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */ +#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */ +#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */ +#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */ +/** + * @} + */ + +#if defined(RCC_PLLCFGR_PLLR) +/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) + * @{ + */ +#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ +#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ +#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ +#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ +#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ +#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ +/** + * @} + */ +#endif /* RCC_PLLCFGR_PLLR */ + +#if defined(RCC_DCKCFGR_PLLDIVR) +/** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR) + * @{ + */ +#define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */ +#define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */ +#define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */ +#define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */ +#define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */ +#define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */ +#define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */ +#define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */ +#define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */ +#define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */ +#define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */ +#define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */ +#define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */ +#define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */ +#define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */ +#define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */ +#define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */ +#define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */ +#define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */ +#define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */ +#define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */ +#define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */ +#define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */ +#define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */ +#define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */ +#define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */ +#define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */ +#define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */ +#define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */ +#define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */ +#define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_PLLDIVR */ + +/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) + * @{ + */ +#define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */ +#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */ +#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) + * @{ + */ +#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */ +#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */ +#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */ +#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */ +#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ +#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */ +#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */ +#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */ +#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */ +#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */ +#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */ +#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */ +#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */ +#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection + * @{ + */ +#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */ +#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */ +/** + * @} + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM) + * @{ + */ +#if defined(RCC_PLLI2SCFGR_PLLI2SM) +#define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */ +#define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */ +#define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */ +#define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */ +#define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */ +#define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */ +#define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */ +#define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */ +#define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */ +#define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */ +#define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */ +#define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */ +#define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */ +#define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */ +#define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */ +#define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */ +#define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */ +#define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */ +#define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */ +#define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */ +#define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */ +#define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */ +#define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */ +#define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */ +#define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */ +#define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */ +#define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */ +#define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */ +#define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */ +#define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */ +#define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */ +#define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */ +#define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */ +#define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */ +#define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */ +#define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */ +#define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */ +#define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */ +#define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */ +#define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */ +#define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */ +#define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */ +#define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */ +#define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */ +#define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */ +#define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */ +#define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */ +#define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */ +#define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */ +#define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */ +#define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */ +#define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */ +#define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */ +#define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */ +#define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */ +#define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */ +#define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */ +#define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */ +#define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */ +#define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */ +#define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */ +#define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */ +#else +#define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */ +#define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */ +#define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */ +#define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */ +#define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */ +#define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */ +#define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */ +#define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */ +#define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */ +#define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */ +#define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */ +#define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */ +#define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */ +#define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */ +#define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */ +#define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */ +#define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */ +#define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */ +#define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */ +#define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */ +#define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */ +#define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */ +#define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */ +#define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */ +#define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */ +#define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */ +#define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */ +#define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */ +#define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */ +#define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */ +#define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */ +#define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */ +#define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */ +#define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */ +#define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */ +#define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */ +#define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */ +#define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */ +#define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */ +#define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */ +#define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */ +#define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */ +#define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */ +#define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */ +#define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */ +#define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */ +#define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */ +#define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */ +#define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */ +#define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */ +#define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */ +#define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */ +#define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */ +#define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */ +#define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */ +#define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */ +#define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */ +#define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */ +#define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */ +#define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */ +#define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */ +#define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */ +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ +/** + * @} + */ + +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) +/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ) + * @{ + */ +#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */ +#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */ +#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */ +#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */ +#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */ +#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */ +#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */ +#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */ +#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */ +#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */ +#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */ +#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */ +#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */ +#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */ +/** + * @} + */ +#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ + +#if defined(RCC_DCKCFGR_PLLI2SDIVQ) +/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ) + * @{ + */ +#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */ +#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */ +#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */ +#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */ +#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */ +#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */ +#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */ +#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */ +#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */ +#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */ +#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */ +#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */ +#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */ +#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */ +#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */ +#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */ +#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */ +#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */ +#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */ +#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */ +#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */ +#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */ +#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */ +#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */ +#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */ +#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */ +#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */ +#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */ +#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */ +#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */ +#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */ +#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ + +#if defined(RCC_DCKCFGR_PLLI2SDIVR) +/** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR) + * @{ + */ +#define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */ +#define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */ +#define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */ +#define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */ +#define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */ +#define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */ +#define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */ +#define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */ +#define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */ +#define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */ +#define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */ +#define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */ +#define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */ +#define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */ +#define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */ +#define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */ +#define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */ +#define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */ +#define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */ +#define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */ +#define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */ +#define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */ +#define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */ +#define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */ +#define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */ +#define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */ +#define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */ +#define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */ +#define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */ +#define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */ +#define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_PLLI2SDIVR */ + +/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) + * @{ + */ +#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */ +#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */ +#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */ +#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */ +#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */ +#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */ +/** + * @} + */ + +#if defined(RCC_PLLI2SCFGR_PLLI2SP) +/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP) + * @{ + */ +#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */ +#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */ +#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */ +#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM) + * @{ + */ +#if defined(RCC_PLLSAICFGR_PLLSAIM) +#define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */ +#define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */ +#define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */ +#define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */ +#define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */ +#define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */ +#define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */ +#define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */ +#define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */ +#define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */ +#define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */ +#define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */ +#define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */ +#define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */ +#define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */ +#define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */ +#define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */ +#define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */ +#define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */ +#define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */ +#define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */ +#define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */ +#define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */ +#define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */ +#define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */ +#define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */ +#define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */ +#define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */ +#define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */ +#define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */ +#define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */ +#define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */ +#define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */ +#define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */ +#define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */ +#define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */ +#define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */ +#define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */ +#define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */ +#define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */ +#define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */ +#define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */ +#define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */ +#define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */ +#define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */ +#define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */ +#define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */ +#define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */ +#define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */ +#define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */ +#define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */ +#define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */ +#define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */ +#define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */ +#define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */ +#define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */ +#define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */ +#define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */ +#define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */ +#define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */ +#define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */ +#define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */ +#else +#define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */ +#define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */ +#define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */ +#define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */ +#define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */ +#define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */ +#define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */ +#define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */ +#define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */ +#define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */ +#define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */ +#define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */ +#define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */ +#define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */ +#define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */ +#define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */ +#define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */ +#define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */ +#define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */ +#define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */ +#define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */ +#define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */ +#define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */ +#define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */ +#define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */ +#define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */ +#define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */ +#define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */ +#define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */ +#define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */ +#define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */ +#define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */ +#define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */ +#define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */ +#define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */ +#define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */ +#define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */ +#define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */ +#define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */ +#define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */ +#define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */ +#define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */ +#define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */ +#define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */ +#define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */ +#define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */ +#define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */ +#define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */ +#define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */ +#define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */ +#define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */ +#define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */ +#define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */ +#define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */ +#define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */ +#define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */ +#define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */ +#define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */ +#define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */ +#define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */ +#define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */ +#define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */ +#endif /* RCC_PLLSAICFGR_PLLSAIM */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ) + * @{ + */ +#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */ +#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */ +#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */ +#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */ +#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */ +#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */ +#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */ +#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */ +#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */ +#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */ +#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */ +#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */ +#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */ +#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */ +/** + * @} + */ + +#if defined(RCC_DCKCFGR_PLLSAIDIVQ) +/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ) + * @{ + */ +#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */ +#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */ +#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */ +#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */ +#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */ +#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */ +#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */ +#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */ +#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */ +#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */ +#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */ +#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */ +#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */ +#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */ +#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */ +#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */ +#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */ +#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */ +#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */ +#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */ +#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */ +#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */ +#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */ +#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */ +#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */ +#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */ +#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */ +#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */ +#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */ +#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */ +#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */ +#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_PLLSAIDIVQ */ + +#if defined(RCC_PLLSAICFGR_PLLSAIR) +/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR) + * @{ + */ +#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */ +#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */ +#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */ +#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */ +#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */ +#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */ +/** + * @} + */ +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + +#if defined(RCC_DCKCFGR_PLLSAIDIVR) +/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR) + * @{ + */ +#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */ +#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */ +#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */ +#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_PLLSAIDIVR */ + +#if defined(RCC_PLLSAICFGR_PLLSAIP) +/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP) + * @{ + */ +#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */ +#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */ +#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */ +#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLSAICFGR_PLLSAIP */ +#endif /* RCC_PLLSAI_SUPPORT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) + +#if defined(RCC_PLLR_SYSCLK_SUPPORT) +/** + * @brief Helper macro to calculate the PLLRCLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) + +#endif /* RCC_PLLR_SYSCLK_SUPPORT */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) + +#if defined(DSI) +/** + * @brief Helper macro to calculate the PLLCLK frequency used on DSI + * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +#endif /* DSI */ + +#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) +/** + * @brief Helper macro to calculate the PLLCLK frequency used on I2S + * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ + +#if defined(SPDIFRX) +/** + * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX + * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +#endif /* SPDIFRX */ + +#if defined(RCC_PLLCFGR_PLLR) +#if defined(SAI1) +/** + * @brief Helper macro to calculate the PLLCLK frequency used on SAI + * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @param __PLLDIVR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) + * + * (*) value not defined in all devices. + * @retval PLL clock frequency (in Hz) + */ +#if defined(RCC_DCKCFGR_PLLDIVR) +#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos )) +#else +#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +#endif /* RCC_DCKCFGR_PLLDIVR */ +#endif /* SAI1 */ +#endif /* RCC_PLLCFGR_PLLR */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param __PLLSAIN__ Between 49/50(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLSAIQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + * @param __PLLSAIDIVQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U))) + +#if defined(RCC_PLLSAICFGR_PLLSAIP) +/** + * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param __PLLSAIN__ Between 50 and 432 + * @param __PLLSAIP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U)) +#endif /* RCC_PLLSAICFGR_PLLSAIP */ + +#if defined(LTDC) +/** + * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param __PLLSAIN__ Between 49/50(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLSAIR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + * @param __PLLSAIDIVR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos]))) +#endif /* LTDC */ +#endif /* RCC_PLLSAI_SUPPORT */ + +#if defined(RCC_PLLI2S_SUPPORT) +#if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR) +/** + * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param __PLLI2SN__ Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLI2SQ_R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) + * + * (*) value not defined in all devices. + * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) + * + * (*) value not defined in all devices. + * @retval PLLI2S clock frequency (in Hz) + */ +#if defined(RCC_DCKCFGR_PLLI2SDIVQ) +#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U))) +#else +#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos))) + +#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ +#endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */ + +#if defined(SPDIFRX) +/** + * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param __PLLI2SN__ Between 50 and 432 + * @param __PLLI2SP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U)) + +#endif /* SPDIFRX */ + +/** + * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param __PLLI2SN__ Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLI2SR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) + +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) +/** + * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param __PLLI2SN__ Between 50 and 432 + * @param __PLLI2SQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos)) + +#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ +#endif /* RCC_PLLI2S_SUPPORT */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) &\ + RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 31 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +} + +#if defined(RCC_BDCR_LSEMOD) +/** + * @brief Enable LSE high drive mode. + * @note LSE high drive mode can be enabled only when the LSE clock is disabled + * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); +} + +/** + * @brief Disable LSE high drive mode. + * @note LSE high drive mode can be disabled only when the LSE clock is disabled + * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); +} +#endif /* RCC_BDCR_LSEMOD */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +#if defined(RCC_CFGR_MCO1EN) +/** + * @brief Enable MCO1 output + * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MCO1_Enable(void) +{ + SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); +} + +/** + * @brief Disable MCO1 output + * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MCO1_Disable(void) +{ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); +} +#endif /* RCC_CFGR_MCO1EN */ + +#if defined(RCC_CFGR_MCO2EN) +/** + * @brief Enable MCO2 output + * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MCO2_Enable(void) +{ + SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); +} + +/** + * @brief Disable MCO2 output + * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MCO2_Disable(void) +{ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); +} +#endif /* RCC_CFGR_MCO2EN */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n + * CFGR MCO1PRE LL_RCC_ConfigMCO\n + * CFGR MCO2 LL_RCC_ConfigMCO\n + * CFGR MCO2PRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_3 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_5 + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_3 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_5 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ +#if defined(FMPI2C1) +/** + * @brief Configure FMPI2C clock source + * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource + * @param FMPI2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource); +} +#endif /* FMPI2C1 */ + +#if defined(LPTIM1) +/** + * @brief Configure LPTIMx clock source + * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); +} +#endif /* LPTIM1 */ + +#if defined(SAI1) +/** + * @brief Configure SAIx clock source + * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n + * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n + * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n + * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) +{ + MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); +} +#endif /* SAI1 */ + +#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) +/** + * @brief Configure SDIO clock source + * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n + * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource + * @param SDIOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK + * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource) +{ +#if defined(RCC_DCKCFGR_SDIOSEL) + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource); +#else + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource); +#endif /* RCC_DCKCFGR_SDIOSEL */ +} +#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ + +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +/** + * @brief Configure 48Mhz domain clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource + * @param CK48MxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource); +#else + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} + +#if defined(RNG) +/** + * @brief Configure RNG clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource); +#else + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} +#endif /* RNG */ + +#if defined(USB_OTG_FS) || defined(USB_OTG_HS) +/** + * @brief Configure USB clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource); +#else + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} +#endif /* USB_OTG_FS || USB_OTG_HS */ +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ + +#if defined(CEC) +/** + * @brief Configure CEC clock source + * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); +} +#endif /* CEC */ + +/** + * @brief Configure I2S clock source + * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n + * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n + * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n + * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) +{ +#if defined(RCC_CFGR_I2SSRC) + MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); +#else + MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U)); +#endif /* RCC_CFGR_I2SSRC */ +} + +#if defined(DSI) +/** + * @brief Configure DSI clock source + * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source); +} +#endif /* DSI */ + +#if defined(DFSDM1_Channel0) +/** + * @brief Configure DFSDM Audio clock source + * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n + * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 + * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) + * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U)); +} + +/** + * @brief Configure DFSDM Kernel clock source + * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source); +} +#endif /* DFSDM1_Channel0 */ + +#if defined(SPDIFRX) +/** + * @brief Configure SPDIFRX clock source + * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource + * @param SPDIFRXxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource); +} +#endif /* SPDIFRX */ + +#if defined(FMPI2C1) +/** + * @brief Get FMPI2C clock source + * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource + * @param FMPI2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx)); +} +#endif /* FMPI2C1 */ + +#if defined(LPTIM1) +/** + * @brief Get LPTIMx clock source + * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); +} +#endif /* LPTIM1 */ + +#if defined(SAI1) +/** + * @brief Get SAIx clock source + * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n + * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n + * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n + * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource + * @param SAIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx); +} +#endif /* SAI1 */ + +#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) +/** + * @brief Get SDIOx clock source + * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n + * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource + * @param SDIOx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDIO_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK + * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx) +{ +#if defined(RCC_DCKCFGR_SDIOSEL) + return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx)); +#else + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx)); +#endif /* RCC_DCKCFGR_SDIOSEL */ +} +#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ + +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +/** + * @brief Get 48Mhz domain clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource + * @param CK48Mx This parameter can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx)); +#else + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} + +#if defined(RNG) +/** + * @brief Get RNGx clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx)); +#else + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} +#endif /* RNG */ + +#if defined(USB_OTG_FS) || defined(USB_OTG_HS) +/** + * @brief Get USBx clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx)); +#else + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} +#endif /* USB_OTG_FS || USB_OTG_HS */ +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ + +#if defined(CEC) +/** + * @brief Get CEC Clock Source + * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource + * @param CECx This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); +} +#endif /* CEC */ + +/** + * @brief Get I2S Clock Source + * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n + * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n + * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n + * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @arg @ref LL_RCC_I2S2_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ +#if defined(RCC_CFGR_I2SSRC) + return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); +#else + return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx); +#endif /* RCC_CFGR_I2SSRC */ +} + +#if defined(DFSDM1_Channel0) +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n + * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE + * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 + * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) + * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx); +} + +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx)); +} +#endif /* DFSDM1_Channel0 */ + +#if defined(SPDIFRX) +/** + * @brief Get SPDIFRX clock source + * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource + * @param SPDIFRXx This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx)); +} +#endif /* SPDIFRX */ + +#if defined(DSI) +/** + * @brief Get DSI Clock Source + * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource + * @param DSIx This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx)); +} +#endif /* DSI */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Set HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); +} + +/** + * @brief Get HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); +} + +/** + * @} + */ + +#if defined(RCC_DCKCFGR_TIMPRE) +/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM + * @{ + */ + +/** + * @brief Set Timers Clock Prescalers + * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler); +} + +/** + * @brief Get Timers Clock Prescalers + * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE)); +} + +/** + * @} + */ +#endif /* RCC_DCKCFGR_TIMPRE */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLP can be written only when PLL is disabled + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLP_R This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLR_DIV_2 (*) + * @arg @ref LL_RCC_PLLR_DIV_3 (*) + * @arg @ref LL_RCC_PLLR_DIV_4 (*) + * @arg @ref LL_RCC_PLLR_DIV_5 (*) + * @arg @ref LL_RCC_PLLR_DIV_6 (*) + * @arg @ref LL_RCC_PLLR_DIV_7 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos); + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R); +#if defined(RCC_PLLR_SYSCLK_SUPPORT) + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R); +#endif /* RCC_PLLR_SYSCLK_SUPPORT */ +} + +/** + * @brief Configure PLL used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note This can be selected for USB, RNG, SDIO + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); +} + +#if defined(DSI) +/** + * @brief Configure PLL used for DSI clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @note This can be selected for DSI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +} +#endif /* DSI */ + +#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) +/** + * @brief Configure PLL used for I2S clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @note This can be selected for I2S + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +} +#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ + +#if defined(SPDIFRX) +/** + * @brief Configure PLL used for SPDIFRX clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @note This can be selected for SPDIFRX + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +} +#endif /* SPDIFRX */ + +#if defined(RCC_PLLCFGR_PLLR) +#if defined(SAI1) +/** + * @brief Configure PLL used for SAI clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @note This can be selected for SAI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n + * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @param PLLDIVR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +#if defined(RCC_DCKCFGR_PLLDIVR) +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, + uint32_t PLLDIVR) +#else +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +#endif /* RCC_DCKCFGR_PLLDIVR */ +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +#if defined(RCC_DCKCFGR_PLLDIVR) + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR); +#endif /* RCC_DCKCFGR_PLLDIVR */ +} +#endif /* SAI1 */ +#endif /* RCC_PLLCFGR_PLLR */ + +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + +/** + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); +} + +/** + * @brief Get Main PLL division factor for PLLP + * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); +} + +/** + * @brief Get Main PLL division factor for PLLQ + * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock) + * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); +} + +#if defined(RCC_PLLCFGR_PLLR) +/** + * @brief Get Main PLL division factor for PLLR + * @note used for PLLCLK (system clock) + * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); +} +#endif /* RCC_PLLCFGR_PLLR */ + +#if defined(RCC_DCKCFGR_PLLDIVR) +/** + * @brief Get Main PLL division factor for PLLDIVR + * @note used for PLLSAICLK (SAI1 and SAI2 clock) + * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLDIVR_DIV_1 + * @arg @ref LL_RCC_PLLDIVR_DIV_2 + * @arg @ref LL_RCC_PLLDIVR_DIV_3 + * @arg @ref LL_RCC_PLLDIVR_DIV_4 + * @arg @ref LL_RCC_PLLDIVR_DIV_5 + * @arg @ref LL_RCC_PLLDIVR_DIV_6 + * @arg @ref LL_RCC_PLLDIVR_DIV_7 + * @arg @ref LL_RCC_PLLDIVR_DIV_8 + * @arg @ref LL_RCC_PLLDIVR_DIV_9 + * @arg @ref LL_RCC_PLLDIVR_DIV_10 + * @arg @ref LL_RCC_PLLDIVR_DIV_11 + * @arg @ref LL_RCC_PLLDIVR_DIV_12 + * @arg @ref LL_RCC_PLLDIVR_DIV_13 + * @arg @ref LL_RCC_PLLDIVR_DIV_14 + * @arg @ref LL_RCC_PLLDIVR_DIV_15 + * @arg @ref LL_RCC_PLLDIVR_DIV_16 + * @arg @ref LL_RCC_PLLDIVR_DIV_17 + * @arg @ref LL_RCC_PLLDIVR_DIV_18 + * @arg @ref LL_RCC_PLLDIVR_DIV_19 + * @arg @ref LL_RCC_PLLDIVR_DIV_20 + * @arg @ref LL_RCC_PLLDIVR_DIV_21 + * @arg @ref LL_RCC_PLLDIVR_DIV_22 + * @arg @ref LL_RCC_PLLDIVR_DIV_23 + * @arg @ref LL_RCC_PLLDIVR_DIV_24 + * @arg @ref LL_RCC_PLLDIVR_DIV_25 + * @arg @ref LL_RCC_PLLDIVR_DIV_26 + * @arg @ref LL_RCC_PLLDIVR_DIV_27 + * @arg @ref LL_RCC_PLLDIVR_DIV_28 + * @arg @ref LL_RCC_PLLDIVR_DIV_29 + * @arg @ref LL_RCC_PLLDIVR_DIV_30 + * @arg @ref LL_RCC_PLLDIVR_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR)); +} +#endif /* RCC_DCKCFGR_PLLDIVR */ + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +} + +/** + * @brief Configure Spread Spectrum used for PLL + * @note These bits must be written before enabling PLL + * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n + * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n + * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum + * @param Mod Between Min_Data=0 and Max_Data=8191 + * @param Inc Between Min_Data=0 and Max_Data=32767 + * @param Sel This parameter can be one of the following values: + * @arg @ref LL_RCC_SPREAD_SELECT_CENTER + * @arg @ref LL_RCC_SPREAD_SELECT_DOWN + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) +{ + MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel); +} + +/** + * @brief Get Spread Spectrum Modulation Period for PLL + * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation + * @retval Between Min_Data=0 and Max_Data=8191 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); +} + +/** + * @brief Get Spread Spectrum Incrementation Step for PLL + * @note Must be written before enabling PLL + * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation + * @retval Between Min_Data=0 and Max_Data=32767 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); +} + +/** + * @brief Get Spread Spectrum Selection for PLL + * @note Must be written before enabling PLL + * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPREAD_SELECT_CENTER + * @arg @ref LL_RCC_SPREAD_SELECT_DOWN + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); +} + +/** + * @brief Enable Spread Spectrum for PLL. + * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) +{ + SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +} + +/** + * @brief Disable Spread Spectrum for PLL. + * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) +{ + CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +} + +/** + * @} + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** @defgroup RCC_LL_EF_PLLI2S PLLI2S + * @{ + */ + +/** + * @brief Enable PLLI2S + * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLI2SON); +} + +/** + * @brief Disable PLLI2S + * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); +} + +/** + * @brief Check if PLLI2S Ready + * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); +} + +#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)) +/** + * @brief Configure PLLI2S used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled + * @note This can be selected for SAI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n + * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n + * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) + * + * (*) value not defined in all devices. + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param PLLN Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLQ_R This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) + * + * (*) value not defined in all devices. + * @param PLLDIVQ_R This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, + uint32_t PLLDIVQ_R) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); + MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos); +#if defined(RCC_DCKCFGR_PLLI2SDIVQ) + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R); + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R); +#else + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R); + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R); +#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ +} +#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */ + +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) +/** + * @brief Configure PLLI2S used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLQ can be written only when PLLI2S is disabled + * @note This can be selected for RNG, USB, SDIO + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n + * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n + * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n + * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) + * + * (*) value not defined in all devices. + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); + MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ); +} +#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ + +#if defined(SPDIFRX) +/** + * @brief Configure PLLI2S used for SPDIFRX domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLP can be written only when PLLI2S is disabled + * @note This can be selected for SPDIFRX + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP); +} +#endif /* SPDIFRX */ + +/** + * @brief Configure PLLI2S used for I2S1 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLR can be written only when PLLI2S is disabled + * @note This can be selected for I2S + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) + * + * (*) value not defined in all devices. + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param PLLN Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); + MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR); +} + +/** + * @brief Get I2SPLL multiplication factor for VCO + * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN + * @retval Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); +} + +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) +/** + * @brief Get I2SPLL division factor for PLLI2SQ + * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ)); +} +#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ + +/** + * @brief Get I2SPLL division factor for PLLI2SR + * @note used for PLLI2SCLK (I2S clock) + * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); +} + +#if defined(RCC_PLLI2SCFGR_PLLI2SP) +/** + * @brief Get I2SPLL division factor for PLLI2SP + * @note used for PLLSPDIFRXCLK (SPDIFRX clock) + * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP)); +} +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ + +#if defined(RCC_DCKCFGR_PLLI2SDIVQ) +/** + * @brief Get I2SPLL division factor for PLLI2SDIVQ + * @note used PLLSAICLK selected (SAI clock) + * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ)); +} +#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ + +#if defined(RCC_DCKCFGR_PLLI2SDIVR) +/** + * @brief Get I2SPLL division factor for PLLI2SDIVR + * @note used PLLSAICLK selected (SAI clock) + * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR)); +} +#endif /* RCC_DCKCFGR_PLLI2SDIVR */ + +/** + * @brief Get division factor for PLLI2S input clock + * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n + * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void) +{ +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM)); +#else + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n + * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void) +{ +#if defined(RCC_PLLI2SCFGR_PLLI2SSRC) + uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC); + uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U; + return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1); +#else + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ +} + +/** + * @} + */ +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** @defgroup RCC_LL_EF_PLLSAI PLLSAI + * @{ + */ + +/** + * @brief Enable PLLSAI + * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLSAION); +} + +/** + * @brief Disable PLLSAI + * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); +} + +/** + * @brief Check if PLLSAI Ready + * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY)); +} + +/** + * @brief Configure PLLSAI used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLQ can be written only when PLLSAI is disabled + * @note This can be selected for SAI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n + * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param PLLN Between 49/50(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + * @param PLLDIVQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, + uint32_t PLLDIVQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); +#if defined(RCC_PLLSAICFGR_PLLSAIM) + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ); + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ); +} + +#if defined(RCC_PLLSAICFGR_PLLSAIP) +/** + * @brief Configure PLLSAI used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLP can be written only when PLLSAI is disabled + * @note This can be selected for USB, RNG, SDIO + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); +#if defined(RCC_PLLSAICFGR_PLLSAIM) + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP); +} +#endif /* RCC_PLLSAICFGR_PLLSAIP */ + +#if defined(LTDC) +/** + * @brief Configure PLLSAI used for LTDC domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLR can be written only when PLLSAI is disabled + * @note This can be selected for LTDC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param PLLN Between 49/50(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + * @param PLLDIVR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, + uint32_t PLLDIVR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR); + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR); +} +#endif /* LTDC */ + +/** + * @brief Get division factor for PLLSAI input clock + * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n + * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void) +{ +#if defined(RCC_PLLSAICFGR_PLLSAIM) + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM)); +#else + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ +} + +/** + * @brief Get SAIPLL multiplication factor for VCO + * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN + * @retval Between 49/50(*) and 432 + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); +} + +/** + * @brief Get SAIPLL division factor for PLLSAIQ + * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ)); +} + +#if defined(RCC_PLLSAICFGR_PLLSAIR) +/** + * @brief Get SAIPLL division factor for PLLSAIR + * @note used for PLLSAICLK (SAI clock) + * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR)); +} +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + +#if defined(RCC_PLLSAICFGR_PLLSAIP) +/** + * @brief Get SAIPLL division factor for PLLSAIP + * @note used for PLL48MCLK (48M domain clock) + * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP)); +} +#endif /* RCC_PLLSAICFGR_PLLSAIP */ + +/** + * @brief Get SAIPLL division factor for PLLSAIDIVQ + * @note used PLLSAICLK selected (SAI clock) + * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ)); +} + +#if defined(RCC_DCKCFGR_PLLSAIDIVR) +/** + * @brief Get SAIPLL division factor for PLLSAIDIVR + * @note used for LTDC domain clock + * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR)); +} +#endif /* RCC_DCKCFGR_PLLSAIDIVR */ + +/** + * @} + */ +#endif /* RCC_PLLSAI_SUPPORT */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Clear PLLI2S ready interrupt flag + * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Clear PLLSAI ready interrupt flag + * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +} + +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_CSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Check if PLLI2S ready interrupt occurred or not + * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF)); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Check if PLLSAI ready interrupt occurred or not + * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF)); +} +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); +} + +#if defined(RCC_CSR_BORRSTF) +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); +} +#endif /* RCC_CSR_BORRSTF */ + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Enable PLLI2S ready interrupt + * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Enable PLLSAI ready interrupt + * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +} +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Disable PLLI2S ready interrupt + * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Disable PLLSAI ready interrupt + * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +} +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE)); +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Checks if PLLSAI ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE)); +} +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +#if defined(FMPI2C1) +uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource); +#endif /* FMPI2C1 */ +#if defined(LPTIM1) +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +#endif /* LPTIM1 */ +#if defined(SAI1) +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +#endif /* SAI1 */ +#if defined(SDIO) +uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource); +#endif /* SDIO */ +#if defined(RNG) +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +#endif /* RNG */ +#if defined(USB_OTG_FS) || defined(USB_OTG_HS) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_OTG_FS || USB_OTG_HS */ +#if defined(DFSDM1_Channel0) +uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); +uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); +#endif /* DFSDM1_Channel0 */ +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +#if defined(CEC) +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +#endif /* CEC */ +#if defined(LTDC) +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +#endif /* LTDC */ +#if defined(SPDIFRX) +uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource); +#endif /* SPDIFRX */ +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_RCC_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h new file mode 100644 index 00000000..84ea5c4d --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h @@ -0,0 +1,1711 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + *Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_SYSTEM_H +#define __STM32F4xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP +* @{ +*/ +#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /*!< Main Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ +#if defined(FSMC_Bank1) +#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ +#endif /* FSMC_Bank1 */ +#if defined(FMC_Bank1) +#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SDRAM SYSCFG_MEMRMP_MEM_MODE_2 /*!< FMC/SDRAM mapped at 0x00000000 */ +#endif /* FMC_Bank1 */ +#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */ + +/** + * @} + */ + +#if defined(SYSCFG_PMC_MII_RMII_SEL) + /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC +* @{ +*/ +#define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /*!< ETH Media MII interface */ +#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */ + +/** + * @} + */ +#endif /* SYSCFG_PMC_MII_RMII_SEL */ + + + +#if defined(SYSCFG_MEMRMP_UFB_MODE) +/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE + * @{ + */ +#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM) + and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/ +#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_UFB_MODE /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM) + and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */ +/** + * @} + */ +#endif /* SYSCFG_MEMRMP_UFB_MODE */ +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#if defined(SYSCFG_CFGR_FMPI2C1_SCL) +#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/ +#endif /* SYSCFG_CFGR_FMPI2C1_SCL */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */ +#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */ +#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */ +#if defined(GPIOF) +#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */ +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */ +#endif /* GPIOG */ +#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /*!< EXTI PORT H */ +#if defined(GPIOI) +#define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /*!< EXTI PORT I */ +#endif /* GPIOI */ +#if defined(GPIOJ) +#define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /*!< EXTI PORT J */ +#endif /* GPIOJ */ +#if defined(GPIOK) +#define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /*!< EXTI PORT k */ +#endif /* GPIOK */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 + with Break Input of TIM1/8 */ +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input + and also the PVDE and PLS bits of the Power Control Interface */ +#endif /* SYSCFG_CFGR2_CLL */ +/** + * @} + */ + +#if defined(SYSCFG_MCHDLYCR_BSCKSEL) +/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL + * @{ + */ +#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000 +#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN + * @{ + */ +#define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN +#define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source SYSCFG MCHDLY DFSDMD0SEL + * @{ + */ +#define LL_SYSCFG_DFSDM1_DataIn0 SYSCFG_MCHDLYCR_DFSDM1D0SEL +#define LL_SYSCFG_DFSDM2_DataIn0 SYSCFG_MCHDLYCR_DFSDM2D0SEL + +#define LL_SYSCFG_DFSDM1_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000) +#define LL_SYSCFG_DFSDM1_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL) +#define LL_SYSCFG_DFSDM2_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000) +#define LL_SYSCFG_DFSDM2_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL) +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL + * @{ + */ +#define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL +#define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL + +#define LL_SYSCFG_DFSDM1_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000) +#define LL_SYSCFG_DFSDM1_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL) +#define LL_SYSCFG_DFSDM2_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000) +#define LL_SYSCFG_DFSDM2_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL) +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL + * @{ + */ +#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL + * @{ + */ +#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG + * @{ + */ +#define LL_SYSCFG_DFSDM1_CKIN_PAD (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL + * @{ + */ +#define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL +/** + * @} + */ + +/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG + * @{ + */ +#define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL +/** + * @} + */ +#endif /* SYSCFG_MCHDLYCR_BSCKSEL */ + +/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */ +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP) +#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP /*!< LPTIM counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT) +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */ +#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT) +#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ +#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ +#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */ +#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ +#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ +#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */ +#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ +#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ +#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ +#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ +#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ +#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ +#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ +#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ +#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ +#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ +/** + * @brief Set memory mapping at address 0x00000000 + * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory + * @param Memory This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @arg @ref LL_SYSCFG_REMAP_FSMC (*) + * @arg @ref LL_SYSCFG_REMAP_FMC (*) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) +{ + MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @arg @ref LL_SYSCFG_REMAP_FSMC (*) + * @arg @ref LL_SYSCFG_REMAP_FMC (*) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); +} + +#if defined(SYSCFG_MEMRMP_SWP_FMC) +/** + * @brief Enables the FMC Memory Mapping Swapping + * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping + * @note SDRAM is accessible at 0x60000000 and NOR/RAM + * is accessible at 0xC0000000 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void) +{ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0); +} + +/** + * @brief Disables the FMC Memory Mapping Swapping + * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping + * @note SDRAM is accessible at 0xC0000000 (default mapping) + * and NOR/RAM is accessible at 0x60000000 (default mapping) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void) +{ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC); +} + +#endif /* SYSCFG_MEMRMP_SWP_FMC */ +/** + * @brief Enables the Compensation cell Power Down + * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) +{ + SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); +} + +/** + * @brief Disables the Compensation cell Power Down + * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); +} + +/** + * @brief Get Compensation Cell ready Flag + * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) +{ + return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY)); +} + +#if defined(SYSCFG_PMC_MII_RMII_SEL) +/** + * @brief Select Ethernet PHY interface + * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface + * @param Interface This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_PMC_ETHMII + * @arg @ref LL_SYSCFG_PMC_ETHRMII + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) +{ + MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface); +} + +/** + * @brief Get Ethernet PHY interface + * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_PMC_ETHMII + * @arg @ref LL_SYSCFG_PMC_ETHRMII + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL)); +} +#endif /* SYSCFG_PMC_MII_RMII_SEL */ + + + +#if defined(SYSCFG_MEMRMP_UFB_MODE) +/** + * @brief Select Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_SetFlashBankMode + * @param Bank This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) +{ + MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank); +} + +/** + * @brief Get Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_GetFlashBankMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE)); +} +#endif /* SYSCFG_MEMRMP_UFB_MODE */ + +#if defined(SYSCFG_CFGR_FMPI2C1_SCL) +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_DisableFastModePlus\n + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus); +} +#endif /* SYSCFG_CFGR_FMPI2C1_SCL */ + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF (*) + * @arg @ref LL_SYSCFG_EXTI_PORTG (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16))); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF (*) + * @arg @ref LL_SYSCFG_EXTI_PORTG (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16)); +} + +#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) +/** + * @brief Set connections to TIM1/8 break inputs + * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n + * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break); +} + +/** + * @brief Get connections to TIM1/8 Break inputs + * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n + * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)); +} +#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ +#if defined(SYSCFG_MCHDLYCR_BSCKSEL) +/** + * @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock. + * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 + * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource); +} +/** + * @brief Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock. + * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 + * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL)); +} +/** + * @brief Enables the DFSDM1 or DFSDM2 Delay clock + * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock + * @param MCHDLY This parameter can be one of the following values + * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN + * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY) +{ + SET_BIT(SYSCFG->MCHDLYCR, MCHDLY); +} + +/** + * @brief Disables the DFSDM1 or the DFSDM2 Delay clock + * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock + * @param MCHDLY This parameter can be one of the following values + * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN + * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY) +{ + CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY); +} + +/** + * @brief Select the source for DFSDM1 or DFSDM2 DatIn0 + * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF)); +} +/** + * @brief Get the source for DFSDM1 or DFSDM2 DatIn0. + * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_GetDataIn0Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn0 + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source)); +} +/** + * @brief Select the source for DFSDM1 or DFSDM2 DatIn2 + * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF)); +} +/** + * @brief Get the source for DFSDM1 or DFSDM2 DatIn2. + * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_GetDataIn2Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn2 + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM4 OC2 + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM4 OC2 + * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM4 OC1 + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM4 OC1 + * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL)); +} + +/** + * @brief Select the DFSDM1 Clock In + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD + * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource); +} +/** + * @brief GET the DFSDM1 Clock In + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_GetClockInSourceSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD + * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG)); +} + +/** + * @brief Select the DFSDM1 Clock Out + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_CKOUT + * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource); +} +/** + * @brief GET the DFSDM1 Clock Out + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_GetClockOutSourceSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_CKOUT + * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL)); +} + +/** + * @brief Enables the DFSDM2 Delay clock + * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_EnableDelayClock + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void) +{ + SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN); +} + +/** + * @brief Disables the DFSDM2 Delay clock + * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_DisableDelayClock + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void) +{ + CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN); +} +/** + * @brief Select the source for DFSDM2 DatIn0 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source); +} +/** + * @brief Get the source for DFSDM2 DatIn0. + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_GetDataIn0Source + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL)); +} + +/** + * @brief Select the source for DFSDM2 DatIn2 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source); +} +/** + * @brief Get the source for DFSDM2 DatIn2. + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_GetDataIn2Source + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL)); +} + +/** + * @brief Select the source for DFSDM2 DatIn4 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source); +} +/** + * @brief Get the source for DFSDM2 DatIn4. + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_GetDataIn4Source + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL)); +} + +/** + * @brief Select the source for DFSDM2 DatIn6 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source); +} +/** + * @brief Get the source for DFSDM2 DatIn6. + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_GetDataIn6Source + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM3 OC4 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM3 OC4 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM3 OC3 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM3 OC4 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM3 OC2 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM3 OC2 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM3 OC1 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM3 OC1 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL)); +} + +/** + * @brief Select the DFSDM2 Clock In + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD + * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource); +} +/** + * @brief GET the DFSDM2 Clock In + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_GetClockInSourceSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD + * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG)); +} + +/** + * @brief Select the DFSDM2 Clock Out + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_CKOUT + * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource); +} +/** + * @brief GET the DFSDM2 Clock Out + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_GetClockOutSourceSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_CKOUT + * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL)); +} + +#endif /* SYSCFG_MCHDLYCR_BSCKSEL */ +/** + * @} + */ + + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413 + * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419 + * @note For STM32F401xx devices, the device ID is 0x423 + * @note For STM32F401xx devices, the device ID is 0x433 + * @note For STM32F411xx devices, the device ID is 0x431 + * @note For STM32F410xx devices, the device ID is 0x458 + * @note For STM32F412xx devices, the device ID is 0x441 + * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463 + * @note For STM32F446xx devices, the device ID is 0x421 + * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices + For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices + For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices + For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices + For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices + For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Set Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + * @param PinAssignment This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); +} + +/** + * @brief Get Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); +} + +/** + * @brief Enable Instruction cache + * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableInstCache(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ICEN); +} + +/** + * @brief Disable Instruction cache + * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableInstCache(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN); +} + +/** + * @brief Enable Data cache + * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableDataCache(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_DCEN); +} + +/** + * @brief Disable Data cache + * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableDataCache(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN); +} + +/** + * @brief Enable Instruction cache reset + * @note bit can be written only when the instruction cache is disabled + * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); +} + +/** + * @brief Disable Instruction cache reset + * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); +} + +/** + * @brief Enable Data cache reset + * @note bit can be written only when the data cache is disabled + * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); +} + +/** + * @brief Disable Data cache reset + * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_SYSTEM_H */ + + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h new file mode 100644 index 00000000..a11f5619 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h @@ -0,0 +1,4096 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_tim.h + * @author MCD Application Team + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_TIM_H +#define __STM32F4xx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U /* 6: TIMx_CH4 */ +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U /* 6: OC4M, OC4FE, OC4PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U /* 6: CC4S, IC4PSC, IC4F */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U /* 6: CC4P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U /* 6: OIS4 */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + + +/* Remap mask definitions */ +#define TIMx_OR_RMP_SHIFT 16U +#define TIMx_OR_RMP_MASK 0x0000FFFFU +#define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) +#define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) +#define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ +#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ +#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ +#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ +#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division + * @{ + */ +#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + * @{ + */ +#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ +#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + * @{ + */ +#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ +#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + * @{ + */ +#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ +#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + * @{ + */ +#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ +#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ +#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ +#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ +#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ +#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ +#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ +#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + * @{ + */ +#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ +#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + * @{ + */ +#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity + * @{ + */ +#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ +#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State + * @{ + */ +#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +{ + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) +{ + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS1N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS1N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * CCER CC4NP LL_TIM_IC_Config + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * CCER CC4NP LL_TIM_IC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * CCER CC4NP LL_TIM_IC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) +{ + __IO uint32_t tmpreg; + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); + /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) +{ + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping + * @{ + */ +/** + * @brief Remap TIM inputs (input channel, internal/external triggers). + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * a some timer inputs can be remapped. + * @rmtoll TIM1_OR ITR2_RMP LL_TIM_SetRemap\n + * TIM2_OR ITR1_RMP LL_TIM_SetRemap\n + * TIM5_OR ITR1_RMP LL_TIM_SetRemap\n + * TIM5_OR TI4_RMP LL_TIM_SetRemap\n + * TIM9_OR ITR1_RMP LL_TIM_SetRemap\n + * TIM11_OR TI1_RMP LL_TIM_SetRemap\n + * LPTIM1_OR OR LL_TIM_SetRemap + * @param TIMx Timer instance + * @param Remap Remap param depends on the TIMx. Description available only + * in CHM version of the User Manual (not in .pdf). + * Otherwise see Reference Manual description of OR registers. + * + * Below description summarizes "Timer Instance" and "Remap" param combinations: + * + * TIM1: one of the following values + * + * ITR2_RMP can be one of the following values + * @arg @ref LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO (*) + * @arg @ref LL_TIM_TIM1_ITR2_RMP_LPTIM (*) + * + * TIM2: one of the following values + * + * ITR1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO + * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF + * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF + * + * TIM5: one of the following values + * + * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO + * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI + * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE + * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC + * @arg @ref LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO (*) + * @arg @ref LL_TIM_TIM5_ITR1_RMP_LPTIM (*) + * + * TIM9: one of the following values + * + * ITR1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO (*) + * @arg @ref LL_TIM_TIM9_ITR1_RMP_LPTIM (*) + * + * TIM11: one of the following values + * + * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 (*) + * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC + * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2 + * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX (*) + * + * (*) Value not defined in all devices. \n + * + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +{ +#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP) + if ((Remap & LL_TIM_LPTIM_REMAP_MASK) == LL_TIM_LPTIM_REMAP_MASK) + { + /* Connect TIMx internal trigger to LPTIM1 output */ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN); + MODIFY_REG(LPTIM1->OR, + (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP), + Remap & ~(LL_TIM_LPTIM_REMAP_MASK)); + } + else + { + MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); + } +#else + MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); +#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */ +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_TIM_H */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h new file mode 100644 index 00000000..ed83b6c6 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h @@ -0,0 +1,2521 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_usart.h + * @author MCD Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_USART_H +#define __STM32F4xx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets*/ +#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_SR_PE USART_SR_PE /*!< Parity error flag */ +#define LL_USART_SR_FE USART_SR_FE /*!< Framing error flag */ +#define LL_USART_SR_NE USART_SR_NE /*!< Noise detected flag */ +#define LL_USART_SR_ORE USART_SR_ORE /*!< Overrun error flag */ +#define LL_USART_SR_IDLE USART_SR_IDLE /*!< Idle line detected flag */ +#define LL_USART_SR_RXNE USART_SR_RXNE /*!< Read data register not empty flag */ +#define LL_USART_SR_TC USART_SR_TC /*!< Transmission complete flag */ +#define LL_USART_SR_TXE USART_SR_TXE /*!< Transmit data register empty flag */ +#define LL_USART_SR_LBD USART_SR_LBD /*!< LIN break detection flag */ +#define LL_USART_SR_CTS USART_SR_CTS /*!< CTS flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported Macros Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(2*((uint64_t)(__BAUDRATE__))))) +#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100) +#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8)\ + + 50) / 100) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ + ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \ + (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(4*((uint64_t)(__BAUDRATE__))))) +#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) +#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16)\ + + 50) / 100) +/* USART BRR = mantissa + overflow + fraction + = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_SR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @rmtoll CR2 ADD LL_USART_SetNodeAddress + * @param USARTx USART Instance + * @param NodeAddress 4 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD)); +} + +/** + * @brief Return 4 bit Address of the USART node as set in ADD field of CR2. + * @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); +} + +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, + uint32_t BaudRate) +{ + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +{ + uint32_t usartdiv = 0x0U; + uint32_t brrresult = 0x0U; + + usartdiv = USARTx->BRR; + + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + if ((usartdiv & 0xFFF7U) != 0U) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + brrresult = (PeriphClk * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = PeriphClk / usartdiv; + } + } + return (brrresult); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); +} + +/** + * @brief Enable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll SR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE)); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll SR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE)); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll SR NF LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE)); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll SR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE)); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE)); +} + +/** + * @brief Check if the USART Read Data Register Not Empty Flag is set or not + * @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE)); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll SR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC)); +} + +/** + * @brief Check if the USART Transmit Data Register Empty Flag is set or not + * @rmtoll SR TXE LL_USART_IsActiveFlag_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE)); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD)); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS)); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK)); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU)); +} + +/** + * @brief Clear Parity Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * NE, FE, ORE, IDLE would also be cleared. + * @rmtoll SR PE LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Framing Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, ORE, IDLE would also be cleared. + * @rmtoll SR FE LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Noise detected Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, FE, ORE, IDLE would also be cleared. + * @rmtoll SR NF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear OverRun Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, FE, IDLE would also be cleared. + * @rmtoll SR ORE LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear IDLE line detected Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, FE, ORE would also be cleared. + * @rmtoll SR IDLE LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll SR TC LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_TC)); +} + +/** + * @brief Clear RX Not Empty Flag + * @rmtoll SR RXNE LL_USART_ClearFlag_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_RXNE)); +} + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll SR LBD LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_LBD)); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll SR CTS LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_CTS)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Enable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Enable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Disable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Disable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); +} + +/** + * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); +} + +/** + * @brief Check if the USART TX Empty Interrupt is enabled or disabled. + * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll DR DR LL_USART_DMA_GetRegAddr + * @note Address of Data Register is valid for both Transmit and Receive transfers. + * @param USARTx USART Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx) +{ + /* return address of DR register */ + return ((uint32_t) &(USARTx->DR)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll DR DR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR)); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll DR DR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll DR DR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->DR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll DR DR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->DR = Value & 0x1FFU; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll CR1 SBK LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_SBK); +} + +/** + * @brief Put USART in Mute mode + * @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RWU); +} + +/** + * @brief Put USART in Active mode + * @rmtoll CR1 RWU LL_USART_RequestExitMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RWU); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_USART_H */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h new file mode 100644 index 00000000..caabcf33 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h @@ -0,0 +1,578 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_usb.h + * @author MCD Application Team + * @brief Header file of USB Low Layer HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_LL_USB_H +#define STM32F4xx_LL_USB_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup USB_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +#ifndef HAL_USB_TIMEOUT +#define HAL_USB_TIMEOUT 0xF000000U +#endif /* define HAL_USB_TIMEOUT */ + +#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS +#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U +#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ + +/** + * @brief USB Mode definition + */ + +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; + +/** + * @brief URB States definition + */ +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_NYET, + URB_ERROR, + URB_STALL +} USB_URBStateTypeDef; + +/** + * @brief Host channel States definition + */ +typedef enum +{ + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_ACK, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR +} USB_HCStateTypeDef; + + +/** + * @brief USB Instance Initialization Structure definition + */ +typedef struct +{ + uint8_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t Host_channels; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t dma_enable; /*!< USB DMA state. + If DMA is not supported this parameter shall be set by default to zero */ + + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + +} USB_CfgTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_LL_EP_Type */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_size; /*!< requested transfer size */ +} USB_EPTypeDef; + +typedef struct +{ + uint8_t dev_addr; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref HCD_Device_Speed: + (HCD_DEVICE_SPEED_xxx) */ + + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ + uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ + uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ + uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ + + uint8_t hub_port_nbr; /*!< USB HUB port number */ + uint8_t hub_addr; /*!< USB HUB address */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_LL_EP_Type */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t XferSize; /*!< OTG Channel transfer size. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + + uint32_t ErrCnt; /*!< Host channel error count. */ + uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ + + USB_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_URBStateTypeDef */ + + USB_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_HCStateTypeDef */ +} USB_HCTypeDef; + +typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; +typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; +typedef USB_EPTypeDef USB_OTG_EPTypeDef; +typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; +typedef USB_HCTypeDef USB_OTG_HCTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +/** + * @} + */ + +/** @defgroup USB_Core_Mode_ USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_FULL 3U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY + * @{ + */ +#define USB_OTG_ULPI_PHY 1U +#define USB_OTG_EMBEDDED_PHY 2U +/** + * @} + */ + +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE +#define USBD_HS_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ + +/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type + * @{ + */ +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_6_MHZ 6000U +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU + +#define HC_MAX_PKT_CNT 256U +#define ISO_SPLT_MPS 188U + +#define HCSPLT_BEGIN 1U +#define HCSPLT_MIDDLE 2U +#define HCSPLT_END 3U +#define HCSPLT_FULL 4U + +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ + + USB_OTG_HOST_CHANNEL_BASE\ + + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + + +#define EP_ADDR_MSK 0xFU +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma); + +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); + +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, + USB_OTG_HCTypeDef *hc, uint8_t dma); + +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32F4xx_LL_USB_H */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h new file mode 100644 index 00000000..accdac7b --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_UTILS_H +#define __STM32F4xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE + and Max_Data = @ref RCC_PLLN_MIN_VALUE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLP; /*!< Division for the main system clock. + This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 0x00000500U /*!< LQFP208 or TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Frequency of Ticks (Hz) + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_UTILS_H */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt new file mode 100644 index 00000000..3edc4d14 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c new file mode 100644 index 00000000..862ec732 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -0,0 +1,616 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup HAL_Private_Constants + * @{ + */ +/** + * @brief STM32F4xx HAL Driver version number V1.8.5 + */ +#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32F4xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK 0x00000FFFU + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) +/* --- MEMRMP Register ---*/ +/* Alias word address of UFB_MODE bit */ +#define MEMRMP_OFFSET SYSCFG_OFFSET +#define UFB_MODE_BIT_NUMBER SYSCFG_MEMRMP_UFB_MODE_Pos +#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) + +/* --- CMPCR Register ---*/ +/* Alias word address of CMP_PD bit */ +#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U) +#define CMP_PD_BIT_NUMBER SYSCFG_CMPCR_CMP_PD_Pos +#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U)) + +/* --- MCHDLYCR Register ---*/ +/* Alias word address of BSCKSEL bit */ +#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U) +#define BSCKSEL_BIT_NUMBER SYSCFG_MCHDLYCR_BSCKSEL_Pos +#define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U)) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Private_Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configure the Flash prefetch, instruction and Data caches. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f4xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch, Instruction cache, Data cache */ +#if (INSTRUCTION_CACHE_ENABLE != 0U) + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (DATA_CACHE_ENABLE != 0U) + __HAL_FLASH_DATA_CACHE_ENABLE(); +#endif /* DATA_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F4xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Enables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_EnableCompensationCell(void) +{ + *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE; +} + +/** + * @brief Power-down the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_DisableCompensationCell(void) +{ + *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Enables the Internal FLASH Bank Swapping. + * + * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. + * + * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) + * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) + * + * @retval None + */ +void HAL_EnableMemorySwappingBank(void) +{ + *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Internal FLASH Bank Swapping. + * + * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. + * + * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) + * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) + * + * @retval None + */ +void HAL_DisableMemorySwappingBank(void) +{ + *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE; +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c new file mode 100644 index 00000000..c3d2ba8e --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c @@ -0,0 +1,538 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M4 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value 0x0F. + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f4xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00U; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0U; +} + +/** + * @brief Enable the MPU. + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Enables the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disables the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Clear pending events. + * @retval None + */ +void HAL_CORTEX_ClearEvent(void) +{ + __SEV(); + __WFE(); +} + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c new file mode 100644 index 00000000..3dbb4776 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c @@ -0,0 +1,1305 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Stream, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Stream Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + + -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros: + __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(). + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred. + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + (+) Use HAL_DMA_Abort() function to abort the current transfer. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + [..] + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort_IT() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + Half-Word data size for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two half words will be packed and written in + a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + and Destination. In this case the Peripheral Data Size will be applied to both Source + and Destination. + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Constants + * @{ + */ + #define HAL_TIMEOUT_DMA_ABORT 5U /* 5 ms */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Stream source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Stream priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + { + assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Get the CR register value */ + tmp = hdma->Instance->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + tmp |= hdma->Init.Channel | hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Write to DMA Stream CR register */ + hdma->Instance->CR = tmp; + + /* Get the FCR register value */ + tmp = hdma->Instance->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + tmp |= hdma->Init.FIFOMode; + + /* The FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + tmp |= hdma->Init.FIFOThreshold; + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 bursts */ + if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + } + + /* Write to DMA Stream FCR */ + hdma->Instance->FCR = tmp; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if(hdma->State == HAL_DMA_STATE_BUSY) + { + /* Return error status */ + return HAL_BUSY; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Streamx control register */ + hdma->Instance->CR = 0U; + + /* Reset DMA Streamx number of data to transfer register */ + hdma->Instance->NDTR = 0U; + + /* Reset DMA Streamx peripheral address register */ + hdma->Instance->PAR = 0U; + + /* Reset DMA Streamx memory 0 address register */ + hdma->Instance->M0AR = 0U; + + /* Reset DMA Streamx memory 1 address register */ + hdma->Instance->M1AR = 0U; + + /* Reset DMA Streamx FIFO control register */ + hdma->Instance->FCR = 0x00000021U; + + /* Get DMA steam Base Address */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + + if(hdma->XferHalfCpltCallback != NULL) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * + * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + * effectively disabled is added. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + uint32_t tickstart = HAL_GetTick(); + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_TIMEOUT; + } + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CompleteLevel Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t mask_cpltlevel; + uint32_t tickstart = HAL_GetTick(); + uint32_t tmpisr; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* No transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode and double buffering mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + } + else + { + /* Half Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + } + + regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + tmpisr = regs->ISR; + + while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) + { + /* Check for the Timeout (Not applicable in circular mode)*/ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_TIMEOUT; + } + } + + /* Get the ISR register value */ + tmpisr = regs->ISR; + + if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + } + } + + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + HAL_DMA_Abort(hdma); + + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + else + { + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; + } + + return status; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t tmpisr; + __IO uint32_t count = 0U; + uint32_t timeout = SystemCoreClock / 9600U; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr = regs->ISR; + + /* Transfer Error Interrupt management ***************************************/ + if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + { + /* Disable the transfer error interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TE); + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + } + } + /* FIFO Error Interrupt management ******************************************/ + if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) + { + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) + { + /* Clear the direct mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + { + /* Clear the half transfer complete flag */ + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + + /* Multi_Buffering mode enabled */ + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the half transfer interrupt */ + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + { + /* Clear the transfer complete flag */ + regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + + if(HAL_DMA_STATE_ABORT == hdma->State) + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the transfer complete interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifier + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear DBM bit */ + hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number]; + + if (stream_number > 3U) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); + } + + return hdma->StreamBaseAddress; +} + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = hdma->Init.FIFOThreshold; + + /* Memory Data size equal to Byte */ + if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + break; + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + return status; +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c new file mode 100644 index 00000000..7167e77e --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c @@ -0,0 +1,313 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function + for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. + + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. + -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default. + -@- In Multi (Double) buffer mode, it is possible to update the base address for + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMAEx_Private_Functions + * @{ + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer with interrupt + (+) Change on the fly the memory0 or memory1 address. + +@endverbatim + * @{ + */ + + +/** + * @brief Starts the multi_buffer DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + } + else + { + /* Process Locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Enable the double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Return error status */ + status = HAL_BUSY; + } + } + return status; +} + +/** + * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Check callback functions */ + if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback)) + { + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Enable the Double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Change the memory0 or memory1 address on the fly. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param Address The new address + * @param memory the memory to be changed, This parameter can be one of + * the following values: + * MEMORY0 / + * MEMORY1 + * @note The MEMORY0 address can be changed only when the current transfer use + * MEMORY1 and the MEMORY1 address can be changed only when the current + * transfer use MEMORY0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) +{ + if(memory == MEMORY0) + { + /* change the memory0 address */ + hdma->Instance->M0AR = Address; + } + else + { + /* change the memory1 address */ + hdma->Instance->M1AR = Address; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c new file mode 100644 index 00000000..3e463122 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c @@ -0,0 +1,553 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + EXTI->RTSR |= maskline; + } + else + { + EXTI->RTSR &= ~maskline; + } + + /* Configure falling trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + EXTI->FTSR |= maskline; + } + else + { + EXTI->FTSR &= ~maskline; + } + + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + EXTI->IMR |= maskline; + } + else + { + EXTI->IMR &= ~maskline; + } + + /* Configure event mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + EXTI->EMR |= maskline; + } + else + { + EXTI->EMR &= ~maskline; + } + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + + /* Check if selected line is enable */ + if ((EXTI->IMR & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + /* Check if selected line is enable */ + if ((EXTI->EMR & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + /* Check if configuration of selected line is enable */ + if ((EXTI->RTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + /* Check if configuration of selected line is enable */ + if ((EXTI->FTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; + } + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + EXTI->IMR = (EXTI->IMR & ~maskline); + + /* 2] Clear event mode */ + EXTI->EMR = (EXTI->EMR & ~maskline); + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + EXTI->RTSR = (EXTI->RTSR & ~maskline); + EXTI->FTSR = (EXTI->FTSR & ~maskline); + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t maskline; + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regval = (EXTI->PR & maskline); + if (regval != 0x00u) + { + /* Clear pending bit */ + EXTI->PR = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Edge); + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* return 1 if bit is set else 0 */ + regval = ((EXTI->PR & maskline) >> linepos); + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t maskline; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Edge); + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Clear Pending bit */ + EXTI->PR = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Generate Software interrupt */ + EXTI->SWIER = maskline; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c new file mode 100644 index 00000000..808949ea --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c @@ -0,0 +1,776 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch and cache lines. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) 64 cache lines of 128 bits on I-Code + (+) 8 cache lines of 128 bits on D-Code + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F4xx devices. + + (#) FLASH Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: byte, half word, word and double word + (++) There Two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Wait for last FLASH operation according to its status + (++) Get error flag status by calling HAL_SetErrorCode() + + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the Instruction cache and the Data cache + (+) Reset the Instruction cache and the Data cache + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variable used for Erase sectors under interruption */ +FLASH_ProcessTypeDef pFlash = {.ProcedureOnGoing = FLASH_PROC_NONE, + .NbSectorsToErase = 0U, + .VoltageForErase= FLASH_VOLTAGE_RANGE_1, + .Sector = 0U, + .Bank = FLASH_BANK_1, + .Address = 0U, + .Lock = HAL_UNLOCKED, + .ErrorCode = HAL_FLASH_ERROR_NONE}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +/* Program operations */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); +static void FLASH_Program_Word(uint32_t Address, uint32_t Data); +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); +static void FLASH_SetErrorCode(void); + +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program byte, halfword, word or double word at a specified address + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (TypeProgram == FLASH_TYPEPROGRAM_BYTE) + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + } + else if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + } + else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + } + else + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + pFlash.Address = Address; + + if (TypeProgram == FLASH_TYPEPROGRAM_BYTE) + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + } + else if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + } + else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + } + else + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + } + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0U; + + /* Check FLASH operation error flags */ +#if defined(FLASH_SR_RDERR) + if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) +#else + if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET) +#endif /* FLASH_SR_RDERR */ + { + if (pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) + { + /*return the faulty sector*/ + addresstmp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /*return the faulty bank*/ + addresstmp = pFlash.Bank; + } + else + { + /*return the faulty address*/ + addresstmp = pFlash.Address; + } + + /*Save the Error code*/ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /*Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + if (pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) + { + /*Nb of sector to erased can be decreased*/ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase*/ + if (pFlash.NbSectorsToErase != 0U) + { + addresstmp = pFlash.Sector; + /*Indicate user which sector has been erased*/ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + pFlash.Sector++; + addresstmp = pFlash.Sector; + FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase); + } + else + { + /*No more sectors to Erase, user callback can be called.*/ + /*Reset Sector and stop Erase sectors procedure*/ + pFlash.Sector = addresstmp = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches(); + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else + { + if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* MassErase ended. Return the selected bank */ + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches(); + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Bank); + } + else + { + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + + if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Operation is completed, disable the PG, SER, SNB and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT)); + + /* Disable End of FLASH Operation interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); + + /* Disable Error source interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector which has been erased + * (if 0xFFFFFFFFU, it means that all the selected sectors have been erased) + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + FLASH->CR |= FLASH_CR_LOCK; + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) + { + /* Authorizes the Option Byte register programming */ + FLASH->OPTKEYR = FLASH_OPT_KEY1; + FLASH->OPTKEYR = FLASH_OPT_KEY2; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OPTSTRT bit in OPTCR register */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; + + /* Wait for last operation to be completed */ + return (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode: The returned value can be a combination of: + * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) + * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag + * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag + * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag + * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag + * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operationtimeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Clear Error Code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) + { + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } +#if defined(FLASH_SR_RDERR) + if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) +#else + if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET) +#endif /* FLASH_SR_RDERR */ + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* If there is no error flag set */ + return HAL_OK; + +} + +/** + * @brief Program a double word (64-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V and Vpp in the range 7V to 9V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; + FLASH->CR |= FLASH_CR_PG; + + /* Program first word */ + *(__IO uint32_t *)Address = (uint32_t)Data; + + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ + *(__IO uint32_t *)(Address + 4) = (uint32_t)(Data >> 32); +} + + +/** + * @brief Program word (32-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Word(uint32_t Address, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint32_t *)Address = Data; +} + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.1V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_HALF_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t *)Address = Data; +} + +/** + * @brief Program byte (8-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 1.8V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_BYTE; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint8_t *)Address = Data; +} + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + + /* Clear FLASH write protection error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR); + } + + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + + /* Clear FLASH Programming alignment error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR); + } + + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; + + /* Clear FLASH Programming parallelism error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR); + } + + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS; + + /* Clear FLASH Programming sequence error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR); + } +#if defined(FLASH_SR_RDERR) + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + + /* Clear FLASH Proprietary readout protection error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR); + } +#endif /* FLASH_SR_RDERR */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; + + /* Clear FLASH Operation error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR); + } +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c new file mode 100644 index 00000000..839c91b1 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c @@ -0,0 +1,1344 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extension peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and + STM32F429xx/439xx devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) PCROP protection for all banks + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx + devices. It includes + (#) FLASH Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Erase sector, erase all sectors + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to : + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Set the BOR level + (++) Program the user Option Bytes + (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to : + (++) Extended space (bank 2) erase function + (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2) + (++) Dual Boot activation + (++) Write protection configuration for bank 2 + (++) PCROP protection configuration and control for both banks + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ +/* Option bytes control */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby); +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); +static uint8_t FLASH_OB_GetUser(void); +static uint16_t FLASH_OB_GetWRP(void); +static uint8_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetBOR(void); + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector); +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector); +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx + STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extension FLASH + programming operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] SectorError pointer to variable that + * contains the configuration information on faulty sector in case of error + * (0xFFFFFFFFU means that all the sectors have been correctly erased) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) +{ + HAL_StatusTypeDef status; + uint32_t index = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /*Initialization of SectorError variable*/ + *SectorError = 0xFFFFFFFFU; + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_MER_BIT); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + /* Erase by sector by sector to be done*/ + for (index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) + { + FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the SER and SNB Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector*/ + *SectorError = index; + break; + } + } + } + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches(); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + pFlash.Bank = pEraseInit->Banks; + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); + } + else + { + /* Erase by sector to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE; + pFlash.NbSectorsToErase = pEraseInit->NbSectors; + pFlash.Sector = pEraseInit->Sector; + pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; + + /*Erase 1st sector and wait for IT*/ + FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange); + } + + return status; +} + +/** + * @brief Program option bytes + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /*Write protection configuration*/ + if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ + status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks); + } + else + { + /*Disable of Write protection on the selected Sector*/ + status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks); + } + } + + /*Read protection configuration*/ + if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + } + + /*USER configuration*/ + if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST); + } + + /*BOR Level configuration*/ + if ((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; + + /*Get WRP*/ + pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser(); + + /*Get BOR Level*/ + pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR(); +} + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Program option bytes + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OBEX(pAdvOBInit->OptionType)); + + /*Program PCROP option byte*/ + if (((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + { + /* Check the parameters */ + assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); + if ((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors); +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + } + else + { + /*Disable of Write protection on the selected Sector*/ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors); +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + } + } + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + /*Program BOOT config option byte*/ + if (((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) + { + status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); + } +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + + return status; +} + +/** + * @brief Get the OBEX byte configuration + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +{ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + /*Get Sector*/ + pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + /*Get Sector for Bank1*/ + pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); + + /*Get Sector for Bank2*/ + pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); + + /*Get Boot config OB*/ + pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS; +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ +} + +/** + * @brief Select the Protection Mode + * + * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted + * Global Read Out Protection modification (from level1 to level0) + * @note Once SPRMOD bit is active unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ + * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) +{ + uint8_t optiontmp; + + /* Mask SPRMOD bit */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + + /* Update Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp); + + return HAL_OK; +} + +/** + * @brief Deselect the Protection Mode + * + * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted + * Global Read Out Protection modification (from level1 to level0) + * @note Once SPRMOD bit is active unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ + * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) +{ + uint8_t optiontmp; + + /* Mask SPRMOD bit */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + + /* Update Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp); + + return HAL_OK; +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\ + STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Returns the FLASH Write Protection Option Bytes value for Bank 2 + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices. + * @retval The FLASH Write Protection Option Bytes value + */ +uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/** + * @} + */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Full erase of FLASH memory sectors + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + assert_param(IS_FLASH_BANK(Banks)); + + /* if the previous operation is completed, proceed to erase all sectors */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + + if (Banks == FLASH_BANK_BOTH) + { + /* bank1 & bank2 will be erased*/ + FLASH->CR |= FLASH_MER_BIT; + } + else if (Banks == FLASH_BANK_1) + { + /*Only bank1 will be erased*/ + FLASH->CR |= FLASH_CR_MER1; + } + else + { + /*Only bank2 will be erased*/ + FLASH->CR |= FLASH_CR_MER2; + } + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0U; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if (VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if (VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if (VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ + if (Sector > FLASH_SECTOR_11) + { + Sector += 4U; + } + /* If the previous operation is completed, proceed to erase the sector */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= tmp_psize; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; +} + +/** + * @brief Enable the write protection of the desired bank1 or bank 2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 + * @arg OB_WRP_SECTOR_All + * @note BANK2 starts from OB_WRP_SECTOR_12 + * + * @param Banks Enable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * @arg FLASH_BANK_2: WRP on all sectors of bank2 + * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 + * + * @retval HAL FLASH State + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || + (WRPSector < OB_WRP_SECTOR_12)) + { + if (WRPSector == OB_WRP_SECTOR_All) + { + /*Write protection on all sector of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~(WRPSector >> 12)); + } + else + { + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector); + } + } + else + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12)); + } + + /*Write protection on all sector of BANK2*/ + if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12)); + } + } + + } + return status; +} + +/** + * @brief Disable the write protection of the desired bank1 or bank 2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 + * @arg OB_WRP_Sector_All + * @note BANK2 starts from OB_WRP_SECTOR_12 + * + * @param Banks Disable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || + (WRPSector < OB_WRP_SECTOR_12)) + { + if (WRPSector == OB_WRP_SECTOR_All) + { + /*Write protection on all sector of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); + } + else + { + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; + } + } + else + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); + } + + /*Write protection on all sector of BANK2*/ + if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); + } + } + + } + + return status; +} + +/** + * @brief Configure the Dual Bank Boot. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param BootConfig specifies the Dual Bank Boot Option byte. + * This parameter can be one of the following values: + * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable + * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled + * @retval None + */ +static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_BOOT(BootConfig)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set Dual Bank Boot */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig; + } + + return status; +} + +/** + * @brief Enable the read/write protection (PCROP) of the desired + * sectors of Bank 1 and/or Bank 2. + * @note This function can be used only for STM32F42xxx/43xxx devices. + * @param SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11 + * @arg OB_PCROP_SECTOR__All + * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23 + * @arg OB_PCROP_SECTOR__All + * @param Banks Enable PCROP protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * @arg FLASH_BANK_2: WRP on all sectors of bank2 + * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) + { + assert_param(IS_OB_PCROP(SectorBank1)); + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1; + } + else + { + assert_param(IS_OB_PCROP(SectorBank2)); + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; + } + + /*Write protection on all sector of BANK2*/ + if (Banks == FLASH_BANK_BOTH) + { + assert_param(IS_OB_PCROP(SectorBank2)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; + } + } + + } + + return status; +} + + +/** + * @brief Disable the read/write protection (PCROP) of the desired + * sectors of Bank 1 and/or Bank 2. + * @note This function can be used only for STM32F42xxx/43xxx devices. + * @param SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11 + * @arg OB_PCROP_SECTOR__All + * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23 + * @arg OB_PCROP_SECTOR__All + * @param Banks Disable PCROP protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * @arg FLASH_BANK_2: WRP on all sectors of bank2 + * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) + { + assert_param(IS_OB_PCROP(SectorBank1)); + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~SectorBank1); + } + else + { + /*Write protection done on sectors of BANK2*/ + assert_param(IS_OB_PCROP(SectorBank2)); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); + } + + /*Write protection on all sector of BANK2*/ + if (Banks == FLASH_BANK_BOTH) + { + assert_param(IS_OB_PCROP(SectorBank2)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); + } + } + + } + + return status; + +} + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +/** + * @brief Mass erase of FLASH memory + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * + * @retval None + */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + assert_param(IS_FLASH_BANK(Banks)); + + /* If the previous operation is completed, proceed to erase all sectors */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0U; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if (VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if (VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if (VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* If the previous operation is completed, proceed to erase the sector */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= tmp_psize; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; +} + +/** + * @brief Enable the write protection of the desired bank 1 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * The value of this parameter depend on device used within the same series + * + * @param Banks Enable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector); + } + + return status; +} + +/** + * @brief Disable the write protection of the desired bank 1 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * The value of this parameter depend on device used within the same series + * + * @param Banks Enable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; + } + + return status; +} +#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx + STM32F413xx || STM32F423xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Enable the read/write protection (PCROP) of the desired sectors. + * @note This function can be used only for STM32F401xx devices. + * @param Sector specifies the sector(s) to be read/write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 + * @arg OB_PCROP_Sector_All + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP(Sector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector; + } + + return status; +} + + +/** + * @brief Disable the read/write protection (PCROP) of the desired sectors. + * @note This function can be used only for STM32F401xx devices. + * @param Sector specifies the sector(s) to be read/write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 + * @arg OB_PCROP_Sector_All + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP(Sector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~Sector); + } + + return status; + +} +#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx + STM32F413xx || STM32F423xx */ + +/** + * @brief Set the read protection level. + * @param Level specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + * + * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(Level)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint8_t *)OPTCR_BYTE1_ADDRESS = Level; + } + + return status; +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Iwdg Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby) +{ + uint8_t optiontmp; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); + + /* Update User Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp))); + } + + return status; +} + +/** + * @brief Set the BOR Level. + * @param Level specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) +{ + /* Check the parameters */ + assert_param(IS_OB_BOR_LEVEL(Level)); + + /* Set the BOR Level */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level; + + return HAL_OK; + +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint8_t)(FLASH->OPTCR & 0xE0)); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint16_t FLASH Write Protection Option Bytes value + */ +static uint16_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH ReadOut Protection Status: + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + */ +static uint8_t FLASH_OB_GetRDP(void) +{ + uint8_t readstatus = OB_RDP_LEVEL_0; + + if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2) + { + readstatus = OB_RDP_LEVEL_2; + } + else if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0) + { + readstatus = OB_RDP_LEVEL_0; + } + else + { + readstatus = OB_RDP_LEVEL_1; + } + + return readstatus; +} + +/** + * @brief Returns the FLASH BOR level. + * @retval uint8_t The FLASH BOR level: + * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V + */ +static uint8_t FLASH_OB_GetBOR(void) +{ + /* Return the FLASH BOR level */ + return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); +} + +/** + * @brief Flush the instruction and data caches + * @retval None + */ +void FLASH_FlushCaches(void) +{ + /* Flush instruction cache */ + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) + { + /* Disable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + /* Reset instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + /* Enable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + } + + /* Flush data cache */ + if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + { + /* Disable data cache */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + /* Reset data cache */ + __HAL_FLASH_DATA_CACHE_RESET(); + /* Enable data cache */ + __HAL_FLASH_DATA_CACHE_ENABLE(); + } +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c new file mode 100644 index 00000000..e6ab3ac8 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c @@ -0,0 +1,172 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ramfunc.c + * @author MCD Application Team + * @brief FLASH RAMFUNC module driver. + * This file provides a FLASH firmware functions which should be + * executed from internal SRAM + * + Stop/Start the flash interface while System Run + * + Enable/Disable the flash sleep while System Run + @verbatim + ============================================================================== + ##### APIs executed from Internal RAM ##### + ============================================================================== + [..] + *** ARM Compiler *** + -------------------- + [..] RAM functions are defined using the toolchain options. + Functions that are be executed in RAM should reside in a separate + source module. Using the 'Options for File' dialog you can simply change + the 'Code / Const' area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the + Options for Target' dialog. + + *** ICCARM Compiler *** + ----------------------- + [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". + + *** GNU Compiler *** + -------------------- + [..] RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC + * @brief FLASH functions executed from RAM + * @{ + */ +#ifdef HAL_FLASH_MODULE_ENABLED +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions + * @{ + */ + +/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM + * @brief Peripheral Extended features functions + * +@verbatim + + =============================================================================== + ##### ramfunc functions ##### + =============================================================================== + [..] + This subsection provides a set of functions that should be executed from RAM + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Stop the flash interface while System Run + * @note This mode is only available for STM32F41xxx/STM32F446xx devices. + * @note This mode couldn't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Stop the flash interface while System Run */ + SET_BIT(PWR->CR, PWR_CR_FISSR); + + return HAL_OK; +} + +/** + * @brief Start the flash interface while System Run + * @note This mode is only available for STM32F411xx/STM32F446xx devices. + * @note This mode couldn't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Start the flash interface while System Run */ + CLEAR_BIT(PWR->CR, PWR_CR_FISSR); + + return HAL_OK; +} + +/** + * @brief Enable the flash sleep while System Run + * @note This mode is only available for STM32F41xxx/STM32F446xx devices. + * @note This mode could n't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Enable the flash sleep while System Run */ + SET_BIT(PWR->CR, PWR_CR_FMSSR); + + return HAL_OK; +} + +/** + * @brief Disable the flash sleep while System Run + * @note This mode is only available for STM32F41xxx/STM32F446xx devices. + * @note This mode couldn't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Disable the flash sleep while System Run */ + CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c new file mode 100644 index 00000000..b3ce9bbc --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c @@ -0,0 +1,533 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) Alternate function mode + (+) External interrupt/event lines + + [..] + During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +#define GPIO_NUMBER 16U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position; + uint32_t ioposition = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t temp = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + for(position = 0U; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = 0x01U << position; + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + + if(iocurrent == ioposition) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ + (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the parameters */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2U]; + temp &= ~(0x0FU << (4U * (position & 0x03U))); + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2U] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->FTSR = temp; + + temp = EXTI->EMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + { + temp |= iocurrent; + } + EXTI->EMR = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & EXTI_IT) != 0x00U) + { + temp |= iocurrent; + } + EXTI->IMR = temp; + } + } + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position; + uint32_t ioposition = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Configure the port pins */ + for(position = 0U; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = 0x01U << position; + /* Get the current IO position */ + iocurrent = (GPIO_Pin) & ioposition; + + if(iocurrent == ioposition) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= (0x0FU << (4U * (position & 0x03U))); + if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + EXTI->EMR &= ~((uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->FTSR &= ~((uint32_t)iocurrent); + EXTI->RTSR &= ~((uint32_t)iocurrent); + + /* Configure the External Interrupt or event for the current IO */ + tmp = 0x0FU << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floating Mode */ + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + } + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; + } +} + +/** + * @brief Toggles the specified GPIO pins. + * @param GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family + * @param GPIO_Pin specifies the port bit to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKR register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* Read again in order to confirm lock is active */ + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c new file mode 100644 index 00000000..9ad44f63 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -0,0 +1,7567 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State, Mode and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx stream + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx stream + + (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XferOptions_definition and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition, an then permit a call the same master sequential interface + several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT() + or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT() + or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT() + or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT() + or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ +#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ +#define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */ +#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macros + * @{ + */ +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +static void I2C_ITError(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); + +/* Private functions for I2C transfer IRQ handler */ +static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); +static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); +static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_Master_SB(I2C_HandleTypeDef *hi2c); +static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); +static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); + +static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags); +static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); +static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c); + +static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); + +/* Private function to flush DR register */ +static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Duty cycle + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + uint32_t freqrange; + uint32_t pclk1; + + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); + assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*Reset I2C*/ + hi2c->Instance->CR1 |= I2C_CR1_SWRST; + hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; + + /* Get PCLK1 frequency */ + pclk1 = HAL_RCC_GetPCLK1Freq(); + + /* Check the minimum allowed PCLK1 frequency */ + if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) + { + return HAL_ERROR; + } + + /* Calculate frequency range */ + freqrange = I2C_FREQRANGE(pclk1); + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Frequency range */ + MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); + + /*---------------------------- I2Cx TRISE Configuration --------------------*/ + /* Configure I2Cx: Rise Time */ + MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); + + /*---------------------------- I2Cx CCR Configuration ----------------------*/ + /* Configure I2Cx: Speed */ + MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and addressing mode */ + MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @brief I2C data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c) +{ + /* Write a dummy data in DR to clear TXE flag */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET) + { + hi2c->Instance->DR = 0x00U; + } +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address */ + if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until BTF flag is set */ + if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address */ + if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + if (hi2c->XferSize <= 3U) + { + /* One byte */ + if (hi2c->XferSize == 1U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if (hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + + if (hi2c->XferSize == 3U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + } + } + + /* Wait until AF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == (uint16_t)0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while (hi2c->XferSize > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until BTF flag is set */ + if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + if (hi2c->XferSize <= 3U) + { + /* One byte */ + if (hi2c->XferSize == 1U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if (hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + if (hi2c->XferSize == 3U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + if (hi2c->XferSize > 0U) + { + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Abort the ongoing DMA */ + dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx); + + /* Prevent unused argument(s) compilation and MISRA warning */ + UNUSED(dmaxferstatus); + + /* Set the unused I2C DMA transfer complete callback to NULL */ + hi2c->hdmatx->XferCpltCallback = NULL; + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferSize = 0U; + hi2c->XferCount = 0U; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Abort the ongoing DMA */ + dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx); + + /* Prevent unused argument(s) compilation and MISRA warning */ + UNUSED(dmaxferstatus); + + /* Set the unused I2C DMA transfer complete callback to NULL */ + hi2c->hdmarx->XferCpltCallback = NULL; + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferSize = 0U; + hi2c->XferCount = 0U; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + return HAL_ERROR; + } + + if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + /* Get tick */ + uint32_t tickstart = HAL_GetTick(); + uint32_t I2C_Trials = 0U; + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + do + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR or AF flag are set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET)) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->State = HAL_I2C_STATE_TIMEOUT; + } + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if the ADDR flag has been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear ADDR Flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Increment Trials */ + I2C_Trials++; + } + while (I2C_Trials < Trials); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ + /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ + if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0U; + uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) + { + if (Prev_State == I2C_STATE_MASTER_BUSY_RX) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */ + enableIT &= ~I2C_IT_BUF; + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable interrupts */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0U; + uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear Last DMA bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if (hi2c->XferSize > 0U) + { + if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) + { + if (Prev_State == I2C_STATE_MASTER_BUSY_RX) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + } + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + if (dmaxferstatus == HAL_OK) + { + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Update interrupt for only EVT and ERR */ + enableIT = (I2C_IT_EVT | I2C_IT_ERR); + } + else + { + /* Update interrupt for only ERR */ + enableIT = I2C_IT_ERR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ + /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ + if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable interrupts */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(DevAddress); + + /* Abort Master transfer during Receive or Transmit process */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && ((CurrentMode == HAL_I2C_MODE_MASTER) || + (CurrentMode == HAL_I2C_MODE_MEM))) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->XferCount = 0U; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + /* Or periphal is not in busy state, mean there is no active sequence to be abort */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t sr1itflags; + uint32_t sr2itflags = 0U; + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + uint32_t CurrentXferOptions = hi2c->XferOptions; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* Master or Memory mode selected */ + if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + sr1itflags = READ_REG(hi2c->Instance->SR1); + + /* Exit IRQ event until Start Bit detected in case of Other frame requested */ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U)) + { + return; + } + + /* SB Set ----------------------------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + I2C_Master_SB(hi2c); + } + /* ADD10 Set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Master_ADD10(hi2c); + } + /* ADDR Set --------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Master_ADDR(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET) + { + /* Do not check buffer and BTF flag if a Xfer DMA is on going */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_MasterTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + if (CurrentState == HAL_I2C_STATE_BUSY_TX) + { + I2C_MasterTransmit_BTF(hi2c); + } + else /* HAL_I2C_MODE_MEM */ + { + if (CurrentMode == HAL_I2C_MODE_MEM) + { + I2C_MemoryTransmit_TXE_BTF(hi2c); + } + } + } + else + { + /* Do nothing */ + } + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* Do not check buffer and BTF flag if a Xfer DMA is on going */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) + { + /* RXNE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_MasterReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_MasterReceive_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + } + } + /* Slave mode selected */ + else + { + /* If an error is detected, read only SR1 register to prevent */ + /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + sr1itflags = READ_REG(hi2c->Instance->SR1); + } + else + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + sr1itflags = READ_REG(hi2c->Instance->SR1); + } + + /* ADDR set --------------------------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + /* Now time to read SR2, this will clear ADDR flag automatically */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + } + I2C_Slave_ADDR(hi2c, sr2itflags); + } + /* STOPF set --------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Slave_STOPF(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_SlaveTransmit_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset ----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_SlaveReceive_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + HAL_I2C_ModeTypeDef tmp1; + uint32_t tmp2; + HAL_I2C_StateTypeDef tmp3; + uint32_t tmp4; + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + uint32_t error = HAL_I2C_ERROR_NONE; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + + /* I2C Bus error interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Arbitration Lost error interrupt occurred ---------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* I2C Acknowledge failure error interrupt occurred ------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + tmp1 = CurrentMode; + tmp2 = hi2c->XferCount; + tmp3 = hi2c->State; + tmp4 = hi2c->PreviousState; + if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ + ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ + ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) + { + I2C_Slave_AF(hi2c); + } + else + { + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + error |= HAL_I2C_ERROR_AF; + + /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ + if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + } + + /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_OVR; + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* Call the Error Callback in case of Error detected -----------------------*/ + if (error != HAL_I2C_ERROR_NONE) + { + hi2c->ErrorCode |= error; + I2C_ITError(hi2c); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Handle TXE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ + ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) + { + if (hi2c->XferCount == 0U) + { + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + else + { + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + I2C_MemoryTransmit_TXE_BTF(hi2c); + } + else + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief Handle BTF flag for Master transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief Handle TXE and BTF flag for Memory transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if (hi2c->EventCount == 0U) + { + /* If Memory address size is 8Bit */ + if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount += 2U; + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + } + else if (hi2c->EventCount == 1U) + { + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + else if (hi2c->EventCount == 2U) + { + if (CurrentState == HAL_I2C_STATE_BUSY_RX) + { + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + hi2c->EventCount++; + } + else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Generate Stop condition then Call TxCpltCallback() */ + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Do nothing */ + } + } + else + { + /* Clear TXE and BTF flags */ + I2C_Flush_DR(hi2c); + } +} + +/** + * @brief Handle RXNE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + uint32_t tmp; + uint32_t CurrentXferOptions; + + CurrentXferOptions = hi2c->XferOptions; + tmp = hi2c->XferCount; + if (tmp > 3U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if (hi2c->XferCount == (uint16_t)3) + { + /* Disable BUF interrupt, this help to treat correctly the last 4 bytes + on BTF subroutine */ + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + } + else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U))) + { + if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call user error callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + } +} + +/** + * @brief Handle BTF flag for Master receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (hi2c->XferCount == 4U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else if (hi2c->XferCount == 3U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else if (hi2c->XferCount == 2U) + { + /* Prepare next transfer or stop current transfer */ + if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME)) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + hi2c->State = HAL_I2C_STATE_READY; + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle SB flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_SB(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + if (hi2c->EventCount == 0U) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + } + else + { + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave 7 Bits address */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + + if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) + || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + } + else + { + if (hi2c->EventCount == 0U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); + } + else if (hi2c->EventCount == 1U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); + } + else + { + /* Do nothing */ + } + } + } +} + +/** + * @brief Handle ADD10 flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) +{ + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); + + if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) + || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } +} + +/** + * @brief Handle ADDR flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + uint32_t Prev_State = hi2c->PreviousState; + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + hi2c->EventCount++; + } + else + { + if (hi2c->XferCount == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferCount == 1U) + { + if (CurrentXferOptions == I2C_NO_OPTION_FRAME) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + /* Prepare next transfer or stop current transfer */ + else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ + && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME))) + { + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + else if (hi2c->XferCount == 2U) + { + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + /* Reset Event counter */ + hi2c->EventCount = 0U; + } + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } +} + +/** + * @brief Handle TXE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Handle BTF flag for Slave transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle RXNE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if (hi2c->XferCount != 0U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Handle BTF flag for Slave receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->XferCount != 0U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle ADD flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param IT2Flags Interrupt2 flags to handle. + * @retval None + */ +static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) +{ + uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; + uint16_t SlaveAddrCode; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */ + __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF)); + + /* Transfer Direction requested by Master */ + if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET) + { + TransferDirection = I2C_DIRECTION_TRANSMIT; + } + + if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET) + { + SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1; + } + else + { + SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode); +#else + HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief Handle STOPF flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear STOPF flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If a DMA is ongoing, Update handle size context */ + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx)); + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Disable, stop the current DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else + { + hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx)); + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Disable, stop the current DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + } + else + { + if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ + (CurrentState == HAL_I2C_STATE_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else if (CurrentState == HAL_I2C_STATE_BUSY_TX) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear TXE flag */ + I2C_Flush_DR(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Clear AF flag only */ + /* State Listen, but XferOptions == FIRST or NEXT */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } +} + +/** + * @brief I2C interrupts error process + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentError; + + if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + } + + if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT)) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + hi2c->PreviousState = I2C_STATE_NONE; + } + + /* Abort DMA transfer */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + if (hi2c->hdmatx->State != HAL_DMA_STATE_READY) + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Call user error callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */ + CurrentError = hi2c->ErrorCode; + + if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \ + ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \ + ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \ + ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR)) + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + /* So may inform upper layer that listen phase is stopped */ + /* during NACK error treatment */ + CurrentState = hi2c->State; + if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Generate Start condition if first transfer */ + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else + { + /* Do nothing */ + } + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start condition if first transfer */ + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else + { + /* Do nothing */ + } + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief DMA I2C process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Clear Complete callback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } + + if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) + { + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0U; + + if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Do nothing */ + } + + /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + } + /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */ + else if (hi2c->Mode != HAL_I2C_MODE_NONE) + { + if (hi2c->XferCount == (uint16_t)1) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Prepare next transfer or stop current transfer */ + if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + + /* Disable Last DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0U; + + /* Check if Errors has been detected during transfer */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Clear Complete callback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } + + /* Ignore DMA FIFO error */ + if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->XferCount = 0U; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + __IO uint32_t count = 0U; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* During abort treatment, check that there is no pending STOP request */ + /* Wait until STOP flag is reset */ + count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + if (count == 0U) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + break; + } + count--; + } + while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); + + /* Clear Complete callback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferCount = 0U; + + /* Reset XferAbortCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Check if come from abort from user */ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Renable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until flag is set */ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for Master addressing phase. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c) +{ + __IO uint32_t count = 0U; + + /* Wait until STOP flag is reset */ + count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); + + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) +{ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c new file mode 100644 index 00000000..351f4fda --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c @@ -0,0 +1,182 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extension HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C extension peripheral: + * + Extension features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### I2C peripheral extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ + 429xx/439xx devices contains the following additional features : + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter + (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config() + (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Functions I2C Exported Functions + * @{ + */ + + +/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions + * @brief Extension features functions + * +@verbatim + =============================================================================== + ##### Extension features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures I2C Analog noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter new state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); + + /* Disable the analog filter */ + hi2c->Instance->FLTR |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures I2C Digital noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->FLTR; + + /* Reset I2Cx DNF bit [3:0] */ + tmpreg &= ~(I2C_FLTR_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter; + + /* Store the new register value */ + hi2c->Instance->FLTR = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ +#endif + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c new file mode 100644 index 00000000..dacbfeb4 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c @@ -0,0 +1,2394 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pcd.c + * @author MCD Application Team + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PCD HAL driver can be used as follows: + + (#) Declare a PCD_HandleTypeDef handle structure, for example: + PCD_HandleTypeDef hpcd; + + (#) Fill parameters of Init structure in HCD handle + + (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) + + (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + + (##) Initialize the related GPIO clocks + (##) Configure PCD pin-out + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB device stack to the HAL PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable PCD transmission and reception: + (##) HAL_PCD_Start(); + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup PCD PCD + * @brief PCD HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ +#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup PCD_Private_Functions PCD Private Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and initialize the associated handle. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ + uint8_t i; + + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + +#if defined (USB_OTG_FS) + USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + + if (hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback = HAL_PCD_SOFCallback; + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + hpcd->ResetCallback = HAL_PCD_ResetCallback; + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; + hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; + + if (hpcd->MspInitCallback == NULL) + { + hpcd->MspInitCallback = HAL_PCD_MspInit; + } + + /* Init the low level hardware */ + hpcd->MspInitCallback(hpcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); +#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ + } + + hpcd->State = HAL_PCD_STATE_BUSY; + +#if defined (USB_OTG_FS) + /* Disable DMA mode for FS instance */ + if (USBx == USB_OTG_FS) + { + hpcd->Init.dma_enable = 0U; + } +#endif /* defined (USB_OTG_FS) */ + + /* Disable the Interrupts */ + __HAL_PCD_DISABLE(hpcd); + + /*Init the Core (common init.) */ + if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Force Device Mode */ + if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Init endpoints structures */ + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } + + /* Init Device */ + if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + hpcd->USB_Address = 0U; + hpcd->State = HAL_PCD_STATE_READY; +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) + /* Activate LPM */ + if (hpcd->Init.lpm_enable == 1U) + { + (void)HAL_PCDEx_ActivateLPM(hpcd); + } +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ + (void)USB_DevDisconnect(hpcd->Instance); + + return HAL_OK; +} + +/** + * @brief DeInitializes the PCD peripheral. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) +{ + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Stop Device */ + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + return HAL_ERROR; + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + if (hpcd->MspDeInitCallback == NULL) + { + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hpcd->MspDeInitCallback(hpcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_PCD_MspDeInit(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + hpcd->State = HAL_PCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB PCD Callback + * To be used instead of the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = pCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = pCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = pCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = pCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = pCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = pCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = pCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Unregister an USB PCD Callback + * USB PCD callback is redirected to the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + /* Setup Legacy weak Callbacks */ + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = HAL_PCD_SOFCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = HAL_PCD_ResetCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Register USB PCD Data OUT Stage Callback + * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data OUT Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Data OUT Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Data IN Stage Callback + * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data IN Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Data IN Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso OUT incomplete Callback + * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Iso OUT incomplete Callback + * USB PCD Iso OUT incomplete Callback is redirected + * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso IN incomplete Callback + * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Iso IN incomplete Callback + * USB PCD Iso IN incomplete Callback is redirected + * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD BCD Callback + * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD BCD Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->BCDCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD BCD Callback + * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD LPM Callback + * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD LPM Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD LPM Callback + * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + + __HAL_PCD_ENABLE(hpcd); + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Stop the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + __HAL_PCD_DISABLE(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); + + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t i; + uint32_t ep_intr; + uint32_t epint; + uint32_t epnum; + uint32_t fifoemptymsk; + uint32_t RegVal; + + /* ensure that we are in device mode */ + if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) + { + /* avoid spurious interrupt */ + if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) + { + return; + } + + /* store current frame number */ + hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) + { + /* incorrect mode, acknowledge the interrupt */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle RxQLevel Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + { + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + RegVal = USBx->GRXSTSP; + + ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; + + if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(USBx, ep->xfer_buff, + (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + { + epnum = 0U; + + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) + { + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); + (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); + /* Class B setup phase done for previous decoded setup */ + (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); + } + + /* Clear OUT Endpoint disable interrupt */ + if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) + { + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + } + + ep = &hpcd->OUT_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); + } + + /* Clear Status Phase Received interrupt */ + if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + + /* Clear OUT NAK interrupt */ + if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) + { + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); + + epnum = 0U; + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) /* In ITR */ + { + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); + + if (hpcd->Init.dma_enable == 1U) + { + hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; + + /* this is ZLP, so prepare EP0 for next setup */ + if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) + { + /* prepare to rx more setup packets */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); + } + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); + } + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); + } + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + { + (void)USB_FlushTxFifo(USBx, epnum); + + ep = &hpcd->IN_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); + } + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + { + (void)PCD_WriteEmptyTxFifo(hpcd, epnum); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + /* Handle Resume Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + { + /* Clear the Remote Wake-up Signaling */ + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + + if (hpcd->LPM_State == LPM_L1) + { + hpcd->LPM_State = LPM_L0; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); + } + + /* Handle Suspend Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + { + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); + } +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) + /* Handle LPM Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); + + if (hpcd->LPM_State == LPM_L0) + { + hpcd->LPM_State = LPM_L1; + hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ + /* Handle Reset Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + { + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + } + USBx_DEVICE->DAINTMSK |= 0x10001U; + + if (hpcd->Init.use_dedicated_ep1 != 0U) + { + USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM; + + USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + else + { + USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM | + USB_OTG_DOEPMSK_OTEPSPRM | + USB_OTG_DOEPMSK_NAKM; + + USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + + /* Set Default Address to 0 */ + USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; + + /* setup EP0 to receive SETUP packets */ + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, + (uint8_t *)hpcd->Setup); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); + } + + /* Handle Enumeration done Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + { + (void)USB_ActivateSetup(hpcd->Instance); + hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); + + /* Set USB Turnaround time */ + (void)USB_SetTurnaroundTime(hpcd->Instance, + HAL_RCC_GetHCLKFreq(), + (uint8_t)hpcd->Init.speed); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); + } + + /* Handle SOF Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else + HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Global OUT NAK effective Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) + { + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) + { + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + } + } + } + + /* Handle Incomplete ISO IN Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_INEP(epnum)->DIEPCTL; + + if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) + { + hpcd->IN_ep[epnum].is_iso_incomplete = 1U; + + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); + } + + /* Handle Incomplete ISO OUT Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_OUTEP(epnum)->DOEPCTL; + + if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && + (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) + { + hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; + + USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + break; + } + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + /* Handle Connection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ConnectCallback(hpcd); +#else + HAL_PCD_ConnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); + } + + /* Handle Disconnection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) + { + RegVal = hpcd->Instance->GOTGINT; + + if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DisconnectCallback(hpcd); +#else + HAL_PCD_DisconnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + hpcd->Instance->GOTGINT |= RegVal; + } + } +} + + +/** + * @brief Handles PCD Wakeup interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd) +{ +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx; + USBx = hpcd->Instance; + + if (USBx == USB_OTG_FS) + { + /* Clear EXTI pending Bit */ + __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG(); + } + else +#endif /* defined (USB_OTG_FS) */ + { + /* Clear EXTI pending Bit */ + __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG(); + } +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @brief Data OUT stage callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callback + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implemented in the user file + */ +} + +/** + * @brief Suspend event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Connect the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Disconnect the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Set the USB Device address. + * @param hpcd PCD handle + * @param address new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + __HAL_LOCK(hpcd); + hpcd->USB_Address = address; + (void)USB_SetDevAddress(hpcd->Instance, address); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} +/** + * @brief Open and configure an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) +{ + HAL_StatusTypeDef ret = HAL_OK; + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->num = ep_addr & EP_ADDR_MSK; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; + ep->type = ep_type; + + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) + { + ep->data_pid_start = 0U; + } + + __HAL_LOCK(hpcd); + (void)USB_ActivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return ret; +} + +/** + * @brief Deactivate an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + + +/** + * @brief Receive an amount of data. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + + return HAL_OK; +} + +/** + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + + return HAL_OK; +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; + } + + ep->is_stall = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + + (void)USB_EPSetStall(hpcd->Instance, ep); + + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->is_stall = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_EPClearStall(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Abort an USB EP transaction. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + HAL_StatusTypeDef ret; + PCD_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + } + + /* Stop Xfer */ + ret = USB_EPStopXfer(hpcd->Instance, ep); + + return ret; +} + +/** + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FlushRxFifo(hpcd->Instance); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Activate remote wakeup signalling + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_ActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @brief De-activate remote wakeup signalling. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_DeActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD handle state. + * @param hpcd PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) +{ + return hpcd->State; +} + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set the USB Device high speed test mode. + * @param hpcd PCD handle + * @param testmode USB Device high speed test mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + + switch (testmode) + { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + case TEST_FORCE_EN: + USBx_DEVICE->DCTL &= ~(0x7U << 4); + USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; + break; + + default: + break; + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup PCD_Private_Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Check FIFO for the next packet to be loaded. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; + + ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return HAL_ERROR; + } + + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32b = (len + 3U) / 4U; + + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32b = (len + 3U) / 4U; + + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, + (uint8_t)hpcd->Init.dma_enable); + + ep->xfer_buff += len; + ep->xfer_count += len; + } + + if (ep->xfer_len <= ep->xfer_count) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_EPTypeDef *ep; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if (hpcd->Init.dma_enable == 1U) + { + if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + } + else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + ep = &hpcd->OUT_ep[epnum]; + + /* out data packet received over EP */ + ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + + if (epnum == 0U) + { + if (ep->xfer_len == 0U) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + else + { + ep->xfer_buff += ep->xfer_count; + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + /* ... */ + } + } + else + { + if (gSNPSiD == USB_OTG_CORE_ID_310A) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT setup packet received interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + + /* Inform the upper layer that a setup packet is available */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) + { + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* HAL_PCD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c new file mode 100644 index 00000000..b66be6ac --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c @@ -0,0 +1,347 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pcd_ex.c + * @author MCD Application Team + * @brief PCD Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup PCDEx PCDEx + * @brief PCD Extended HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ + +/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @brief PCDEx control functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Update FIFO configuration + +@endverbatim + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set Tx FIFO + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t Tx_Offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = hpcd->Instance->GRXFSIZ; + + if (fifo == 0U) + { + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; + } + else + { + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0U; i < (fifo - 1U); i++) + { + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; + } + + return HAL_OK; +} + +/** + * @brief Set Rx FIFO + * @param hpcd PCD handle + * @param size Size of Rx fifo + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) +{ + hpcd->Instance->GRXFSIZ = size; + + return HAL_OK; +} +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) +/** + * @brief Activate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 1U; + hpcd->LPM_State = LPM_L0; + USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + +/** + * @brief Deactivate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; + USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \ + || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Handle BatteryCharging Process. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t tickstart = HAL_GetTick(); + + /* Enable DCD : Data Contact Detect */ + USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; + + /* Wait for Min DCD Timeout */ + HAL_Delay(300U); + + /* Check Detect flag */ + if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + /* Primary detection: checks if connected to Standard Downstream Port + (without charging capability) */ + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN; + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + HAL_Delay(50U); + + if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U) + { + /* Case of Standard Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* start secondary detection to check connection to Charging Downstream + Port or Dedicated Charging Port */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + HAL_Delay(50U); + + if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET) + { + /* case Dedicated Charging Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* case Charging Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Battery Charging capability discovery finished */ + (void)HAL_PCDEx_DeActivateBCD(hpcd); + + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Activate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + + /* Power Down USB transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Enable Battery charging */ + USBx->GCCFG |= USB_OTG_GCCFG_BCDEN; + + hpcd->battery_charging_active = 1U; + + return HAL_OK; +} + +/** + * @brief Deactivate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + + /* Disable Battery charging */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + + hpcd->battery_charging_active = 0U; + + return HAL_OK; +} +#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @brief Send LPM message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_LPM_Callback could be implemented in the user file + */ +} + +/** + * @brief Send BatteryCharging message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_BCD_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* HAL_PCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c new file mode 100644 index 00000000..5ccde648 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c @@ -0,0 +1,598 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWR_Private_Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT 0x00010000U +#define PVD_MODE_EVT 0x00020000U +#define PVD_RISING_EDGE 0x00000001U +#define PVD_FALLING_EDGE 0x00000002U +/** + * @} + */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @note The following sequence is required to bypass the delay between + * DBP bit programming and the effective enabling of the backup domain. + * Please check the Errata Sheet for more details under "Possible delay + * in backup domain protection disabling/enabling after programming the + * DBP bit" section. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + __IO uint32_t dummyread; + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; + dummyread = PWR->CR; + UNUSED(dummyread); +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @note The following sequence is required to bypass the delay between + * DBP bit programming and the effective disabling of the backup domain. + * Please check the Errata Sheet for more details under "Possible delay + * in backup domain protection disabling/enabling after programming the + * DBP bit" section. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + __IO uint32_t dummyread; + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; + dummyread = PWR->CR; + UNUSED(dummyread); +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** Wake-up pin configuration *** + ================================ + [..] + (+) Wake-up pin is used to wake up the system from Standby mode. This pin is + forced in input pull-down configuration and is active on rising edges. + (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. + (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 + (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off. + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and + no clear of pending event before. + + -@@- The Regulator parameter is not used for the STM32F4 family + and is kept as parameter just to maintain compatibility with the + lower power families (STM32L). + (+) Exit: + Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption In Stop mode, FLASH can be powered off before + entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the Stop mode using + the HAL_PWREx_DisableFlashPowerDown() function. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry) + function with: + (++) Regulator: + (+++) Main regulator ON. + (+++) Low Power regulator ON. + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + clear of pending events before. + (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + no clear of pending event before. + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** Standby mode *** + ==================== + [..] + (+) + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. + The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby + circuitry. + + The voltage regulator is OFF. + + (++) Entry: + (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (++) Exit: + (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wake-up (AWU) from low-power mode *** + ============================================= + [..] + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wake-up event, a tamper event or a time-stamp event, without depending on + an external interrupt (Auto-wake-up mode). + + (+) RTC auto-wake-up (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to + configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables the Wake-up PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + /* Enable the wake up pin */ + SET_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Disables the Wake-up PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + /* Disable the wake up pin */ + CLEAR_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Enters Sleep mode. + * + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * + * @note In Sleep mode, the systick is stopped to avoid exit from this mode with + * systick interrupt when used as time base for Timeout + * + * @param Regulator Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + * @note This parameter is not used for the STM32F4 family and is kept as parameter + * just to maintain compatibility with the lower power families. + * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and + * no clear of pending event before. + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + if(SLEEPEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + + /* Request Wait For Event */ + __WFE(); + } +} + +/** + * @brief Enters Stop mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wake-up event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE : Enter Stop mode with WFE instruction and + * clear of pending events before. + * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + * no clear of pending event before. + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + if(STOPEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enters Standby mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. + * - WKUP pin 1 (PA0) if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + SET_BIT(PWR->CR, PWR_CR_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR Exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enables CORTEX M4 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Disables CORTEX M4 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c new file mode 100644 index 00000000..77f9c35b --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c @@ -0,0 +1,600 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of PWR extension peripheral: + * + Peripheral Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Constants + * @{ + */ +#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U +#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U +#define PWR_BKPREG_TIMEOUT_VALUE 1000U +#define PWR_VOSRDY_TIMEOUT_VALUE 1000U +/** + * @} + */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions + * @brief Peripheral Extended features functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended features functions ##### + =============================================================================== + + *** Main and Backup Regulators configuration *** + ================================================ + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from + the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is + retained even in Standby or VBAT mode when the low power backup regulator + is enabled. It can be considered as an internal EEPROM when VBAT is + always present. You can use the HAL_PWREx_EnableBkUpReg() function to + enable the low power backup regulator. + + (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to + save battery life. + + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash + programming manual. + + (+) The main internal regulator can be configured to have a tradeoff between + performance and power consumption when the device does not operate at + the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() + macro which configure VOS bit in PWR_CR register + + Refer to the product datasheets for more details. + + *** FLASH Power Down configuration **** + ======================================= + [..] + (+) By setting the FPDS bit in the PWR_CR register by using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power + down mode when the device enters Stop mode. When the Flash memory + is in power down mode, an additional startup delay is incurred when + waking up from Stop mode. + + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL + is OFF and the HSI or HSE clock source is selected as system clock. + The new value programmed is active only when the PLL is ON. + When the PLL is OFF, the voltage scale 3 is automatically selected. + Refer to the datasheets for more details. + + *** Over-Drive and Under-Drive configuration **** + ================================================= + [..] + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has + 2 operating modes available: + (++) Normal mode: The CPU and core logic operate at maximum frequency at a given + voltage scaling (scale 1, scale 2 or scale 3) + (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a + higher frequency than the normal mode for a given voltage scaling (scale 1, + scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and + disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow + the sequence described in Reference manual. + + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator + supplies a low power voltage to the 1.2V domain, thus preserving the content of registers + and internal SRAM. 2 operating modes are available: + (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only + available when the main regulator or the low power regulator is used in Scale 3 or + low voltage mode. + (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only + available when the main regulator or the low power regulator is in low voltage mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) +{ + uint32_t tickstart = 0U; + + *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Disables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) +{ + uint32_t tickstart = 0U; + + *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Enables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_EnableFlashPowerDown(void) +{ + *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_DisableFlashPowerDown(void) +{ + *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE; +} + +/** + * @brief Return Voltage Scaling Range. + * @retval The configured scale for the regulator voltage(VOS bit field). + * The returned value can be one of the following: + * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->CR & PWR_CR_VOS); +} + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +/** + * @brief Configures the main internal regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, + * the maximum value of fHCLK = 168 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, + * the maximum value of fHCLK = 144 MHz. + * @note When moving from Range 1 to Range 2, the system frequency must be decreased to + * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API. + * When moving from Range 2 to Range 1, the system frequency can be increased to + * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart = 0U; + + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Enable PWR RCC Clock Peripheral */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Set Range */ + __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) + { + if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Configures the main internal regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, + * the maximum value of fHCLK is 168 MHz. It can be extended to + * 180 MHz by activating the over-drive mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, + * the maximum value of fHCLK is 144 MHz. It can be extended to, + * 168 MHz by activating the over-drive mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode, + * the maximum value of fHCLK is 120 MHz. + * @note To update the system clock frequency(SYSCLK): + * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). + * - Call the HAL_RCC_OscConfig() to configure the PLL. + * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. + * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). + * @note The scale can be modified only when the HSI or HSE clock source is selected + * as system clock source, otherwise the API returns HAL_ERROR. + * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits + * value in the PWR_CR1 register are not taken in account. + * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. + * @note The new voltage scale is active only when the PLL is ON. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart = 0U; + + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Enable PWR RCC Clock Peripheral */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + /* Disable the main PLL */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set Range */ + __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); + + /* Enable the main PLL */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) + { + if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Enables Main Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xx devices. + * @retval None + */ +void HAL_PWREx_EnableMainRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables Main Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xxdevices. + * @retval None + */ +void HAL_PWREx_DisableMainRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables Low Power Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xx devices. + * @retval None + */ +void HAL_PWREx_EnableLowRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables Low Power Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xx devices. + * @retval None + */ +void HAL_PWREx_DisableLowRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; +} + +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Activates the Over-Drive mode. + * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. + * This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) +{ + uint32_t tickstart = 0U; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ + __HAL_PWR_OVERDRIVE_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Enable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Deactivates the Over-Drive mode. + * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. + * This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) +{ + uint32_t tickstart = 0U; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Disable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Over-drive */ + __HAL_PWR_OVERDRIVE_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Enters in Under-Drive STOP mode. + * + * @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. + * + * @note This mode can be selected only when the Under-Drive is already active + * + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode + * + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * + * @note When exiting Stop mode by issuing an interrupt or a wake-up event, + * the HSI RC oscillator is selected as system clock. + * + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param Regulator specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction + * @retval None + */ +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Enable the Under-drive Mode ---------------------------------------------*/ + /* Clear Under-drive flag */ + __HAL_PWR_CLEAR_ODRUDR_FLAG(); + + /* Enable the Under-drive */ + __HAL_PWR_UNDERDRIVE_ENABLE(); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg1 = PWR->CR; + /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ + tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS); + + /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ + tmpreg1 |= Regulator; + + /* Store the new value */ + PWR->CR = tmpreg1; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + return HAL_OK; +} + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c new file mode 100644 index 00000000..c18fa09b --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c @@ -0,0 +1,1124 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Implemented Workaround: + (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/* Private macro -------------------------------------------------------------*/ +#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOC +#define MCO2_PIN GPIO_PIN_9 +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + (++) The first output is used to generate the high speed system clock (up to 168 MHz) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clocks automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M4 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + + [..] System, AHB and APB busses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum + frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + + (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices, + the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + + (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz, + PCLK2 84 MHz and PCLK1 42 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + + (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz, + PCLK2 100 MHz and PCLK1 50 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this API. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this API. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t pll_config; + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ + RCC_OscInitStruct->PLL.PLLM | \ + (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ + (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ + (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; +#if defined (RCC_PLLCFGR_PLLR) + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) +#else + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) +#endif /* RCC_PLLCFGR_PLLR */ + { + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings */ + HAL_InitTick(uwTickPrio); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PA8/PC9 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). + * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param RCC_MCODiv specifies the MCOx prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have + * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5). + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + /* RCC_MCO1 */ + if (RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO1 Clock Enable */ + __MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + + /* This RCC MCO1 enable feature is available only on STM32F410xx devices */ +#if defined(RCC_CFGR_MCO1EN) + __HAL_RCC_MCO1_ENABLE(); +#endif /* RCC_CFGR_MCO1EN */ + } +#if defined(RCC_CFGR_MCO2) + else + { + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + + /* MCO2 Clock Enable */ + __MCO2_CLK_ENABLE(); + + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U))); + + /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */ +#if defined(RCC_CFGR_MCO2EN) + __HAL_RCC_MCO2_ENABLE(); +#endif /* RCC_CFGR_MCO2EN */ + } +#endif /* RCC_CFGR_MCO2 */ +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +__weak uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllm = 0U; + uint32_t pllvco = 0U; + uint32_t pllp = 0U; + uint32_t sysclockfreq = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + break; + } + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); + + sysclockfreq = pllvco / pllp; + break; + } + default: + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); +} + +/** + * @brief Configures the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval None + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c new file mode 100644 index 00000000..04317181 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c @@ -0,0 +1,3833 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extension RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCCEx HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ + +#if defined(STM32F446xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + uint32_t plli2sp = 0U; + uint32_t plli2sq = 0U; + uint32_t plli2sr = 0U; + uint32_t pllsaip = 0U; + uint32_t pllsaiq = 0U; + uint32_t plli2sused = 0U; + uint32_t pllsaiused = 0U; + + /* Check the peripheral clock selection parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------ I2S APB1 configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- I2S APB2 configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*--------------------------- SAI1 configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + { + pllsaiused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*-------------------------- SAI2 configuration ----------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + { + pllsaiused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- RTC configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- FMPI2C1 Configuration -----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); + + /* Configure the FMPI2C1 clock source */ + __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------ CEC Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- CLK48 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 clock source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLSAI when it's used as clock source for CLK48 */ + if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) + { + pllsaiused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- SDIO Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------ SPDIFRX Configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + /* Check the parameters */ + assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); + + /* Configure the SPDIFRX clock source */ + __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); + /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ + if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- PLLI2S Configuration ------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, + I2S on APB2 or SPDIFRX */ + if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ + if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) + && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq, + PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ + if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, + PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, + plli2sq, plli2sr); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, + PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- PLLSAI Configuration -----------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ + if (pllsaiused == 1U) + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is disabled */ + while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ + if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + { + /* check for PLLSAIQ Parameter */ + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, + PeriphClkInit->PLLSAI.PLLSAIQ, 0U); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ + /* In Case of PLLI2S is selected as source clock for CLK48 */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, + pllsaiq, 0U); + } + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is ready */ + while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 | \ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO | \ + RCC_PERIPHCLK_SPDIFRX; + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Get the PLLSAI Clock configuration --------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos); + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); + + /* Get the SAI1 clock configuration ----------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + + /* Get the SAI2 clock configuration ----------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + + /* Get the I2S APB1 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); + + /* Get the I2S APB2 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); + + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the CEC clock configuration -----------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + + /* Get the FMPI2C1 clock configuration -------------------------------------*/ + PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); + + /* Get the CLK48 clock configuration ----------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDIO clock configuration ----------------------------------------*/ + PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); + + /* Get the SPDIFRX clock configuration -------------------------------------*/ + PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); + + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock + * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock + * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t tmpreg1 = 0U; + /* This variable used to store the SAI clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + /* This variable used to store the SAI clock source */ + uint32_t saiclocksource = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_SAI1: + case RCC_PERIPHCLK_SAI2: + { + saiclocksource = RCC->DCKCFGR; + saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC); + switch (saiclocksource) + { + case 0U: /* PLLSAI is the clock source for SAI*/ + { + /* Configure the PLLSAI division factor */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM))); + } + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U; + frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U)) / (tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U); + frequency = frequency / (tmpreg1); + break; + } + case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/ + case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/ + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM))); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U; + frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U); + frequency = frequency / (tmpreg1); + break; + } + case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/ + case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/ + { + /* Configure the PLLI2S division factor */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + /* SAI_CLK_x = PLL_VCO Output/PLLR */ + tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U; + frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U)) / (tmpreg1); + break; + } + case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/ + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + frequency = (uint32_t)(HSI_VALUE); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + frequency = (uint32_t)(HSE_VALUE); + } + break; + } + default : + { + break; + } + } + break; + } + case RCC_PERIPHCLK_I2S_APB1: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB1CLKSOURCE_PLLSRC: + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + case RCC_PERIPHCLK_I2S_APB2: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB2CLKSOURCE_PLLSRC: + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC, RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + uint32_t pllsaip = 0U; + uint32_t pllsaiq = 0U; + uint32_t pllsair = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*--------------------------- CLK48 Configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 clock source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------ SDIO Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ + /*------------------- Common configuration SAI/I2S -------------------------*/ + /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division + factor is common parameters for both peripherals */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------- I2S configuration -------------------------------*/ + /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added + only for I2S configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must + be added only for SAI configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) + { + /* Check the PLLI2S division factors */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Configure the PLLI2S multiplication and division factors */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, + PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ + /*----------------------- Common configuration SAI/LTDC --------------------*/ + /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division + factor is common parameters for these peripherals */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && + (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))) + { + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is disabled */ + while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must + be added only for SAI configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) + { + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair); + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*---------------------------- LTDC configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR); + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + } + + /*---------------------------- CLK48 configuration ------------------------*/ + /* Configure the PLLSAI when it is used as clock source for CLK48 */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) && + (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) + { + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + + /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair); + } + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is ready */ + while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*--------------------------------------------------------------------------*/ + + /*---------------------------- RTC configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + return HAL_OK; +} + +/** + * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | \ + RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO; + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Get the PLLSAI Clock configuration --------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); + PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the CLK48 clock configuration -------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDIO clock configuration ----------------------------------------*/ + PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); + + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SCLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, LTDC RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; +#if defined(STM32F413xx) || defined(STM32F423xx) + uint32_t plli2sq = 0U; +#endif /* STM32F413xx || STM32F423xx */ + uint32_t plli2sused = 0U; + + /* Check the peripheral clock selection parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S APB1 configuration ---------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------------- I2S APB2 configuration ---------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + +#if defined(STM32F413xx) || defined(STM32F423xx) + /*----------------------- SAI1 Block A configuration -----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR) + { + /* Check for PLL/DIVR parameters */ + assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ + __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------- SAI1 Block B configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR) + { + /* Check for PLL/DIVR parameters */ + assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ + __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); + } + } + /*--------------------------------------------------------------------------*/ +#endif /* STM32F413xx || STM32F423xx */ + + /*------------------------------------ RTC configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------ TIM configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------- FMPI2C1 Configuration --------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); + + /* Configure the FMPI2C1 clock source */ + __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------- CLK48 Configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for CLK48 */ + if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------- SDIO Configuration -----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*-------------------------------------- PLLI2S Configuration --------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or + I2S on APB2*/ + if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection)); + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + /*-------------------- Set the PLL I2S clock -----------------------------*/ + __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection); + + /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/ + if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) + && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, + PeriphClkInit->PLLI2S.PLLI2SR); + } + +#if defined(STM32F413xx) || defined(STM32F423xx) + /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ + if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) + && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + /* Check for PLLI2S/DIVR parameters */ + assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR)); + + /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, + PeriphClkInit->PLLI2S.PLLI2SR); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR); + } +#endif /* STM32F413xx || STM32F423xx */ + + /*----------------- In Case of PLLI2S is just selected ------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, + PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*-------------------- DFSDM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*-------------------- DFSDM1 Audio clock source configuration -------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM1 Audio interface clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + } + /*--------------------------------------------------------------------------*/ + +#if defined(STM32F413xx) || defined(STM32F423xx) + /*-------------------- DFSDM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*-------------------- DFSDM2 Audio clock source configuration -------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection)); + + /* Configure the DFSDM1 Audio interface clock source */ + __HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- LPTIM1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LPTIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + /*--------------------------------------------------------------------------*/ +#endif /* STM32F413xx || STM32F423xx */ + + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 | \ + RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 | \ + RCC_PERIPHCLK_DFSDM1_AUDIO | RCC_PERIPHCLK_DFSDM2 | \ + RCC_PERIPHCLK_DFSDM2_AUDIO | RCC_PERIPHCLK_LPTIM1 | \ + RCC_PERIPHCLK_SAIA | RCC_PERIPHCLK_SAIB; +#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 | \ + RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 | \ + RCC_PERIPHCLK_DFSDM1_AUDIO; +#endif /* STM32F413xx || STM32F423xx */ + + + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); +#if defined(STM32F413xx) || defined(STM32F423xx) + /* Get the PLL/PLLI2S division factors -------------------------------------*/ + PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos); + PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos); +#endif /* STM32F413xx || STM32F423xx */ + + /* Get the I2S APB1 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); + + /* Get the I2S APB2 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); + + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the FMPI2C1 clock configuration -------------------------------------*/ + PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); + + /* Get the CLK48 clock configuration ---------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDIO clock configuration ----------------------------------------*/ + PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); + + /* Get the DFSDM1 clock configuration --------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); + + /* Get the DFSDM1 Audio clock configuration --------------------------------*/ + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); + +#if defined(STM32F413xx) || defined(STM32F423xx) + /* Get the DFSDM2 clock configuration --------------------------------------*/ + PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); + + /* Get the DFSDM2 Audio clock configuration --------------------------------*/ + PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE(); + + /* Get the LPTIM1 clock configuration --------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the SAI1 Block Aclock configuration ---------------------------------*/ + PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE(); + + /* Get the SAI1 Block B clock configuration --------------------------------*/ + PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE(); +#endif /* STM32F413xx || STM32F423xx */ + + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(I2S..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock + * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S_APB1: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLI2S: + { + if ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + } + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB1CLKSOURCE_PLLSRC: + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + case RCC_PERIPHCLK_I2S_APB2: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLI2S: + { + if ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + } + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB2CLKSOURCE_PLLSRC: + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). + * + * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case + * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup + * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- FMPI2C1 Configuration -----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); + + /* Configure the FMPI2C1 clock source */ + __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- LPTIM1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LPTIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*---------------------------- I2S Configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection)); + + /* Configure the I2S clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection); + } + + return HAL_OK; +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; + + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } + /* Get the FMPI2C1 clock configuration -------------------------------------*/ + PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); + + /* Get the I2S clock configuration -----------------------------------------*/ + PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE(); + + +} +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPBCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPBCLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPBCLKSOURCE_PLLSRC: + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ + /*----------------------- Common configuration SAI/I2S ---------------------*/ + /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division + factor is common parameters for both peripherals */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------------- I2S configuration -------------------------*/ + /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added + only for I2S configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must + be added only for SAI configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) + { + /* Check the PLLI2S division factors */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Configure the PLLI2S multiplication and division factors */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, + PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ + /*----------------------- Common configuration SAI/LTDC --------------------*/ + /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division + factor is common parameters for both peripherals */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) + { + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is disabled */ + while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must + be added only for SAI configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) + { + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*---------------------------- LTDC configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR); + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + } + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is ready */ + while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- RTC configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + return HAL_OK; +} + +/** + * @brief Configures the PeriphClkInit according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; + + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); + PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); + /* Get the RTC Clock configuration -----------------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SCLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). + * + * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case + * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup + * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- I2S configuration ---------------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); +#if defined(STM32F411xE) + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); +#endif /* STM32F411xE */ + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + +#if defined(STM32F411xE) + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, + PeriphClkInit->PLLI2S.PLLI2SR); +#else + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); +#endif /* STM32F411xE */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*---------------------------- RTC configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + /*---------------------------- TIM configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + return HAL_OK; +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC; + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); +#if defined(STM32F411xE) + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM); +#endif /* STM32F411xE */ + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SCLKSOURCE_PLLI2S: + { +#if defined(STM32F411xE) + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } +#else + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } +#endif /* STM32F411xE */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Select LSE mode + * + * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. + * + * @param Mode specifies the LSE mode. + * This parameter can be one of the following values: + * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection + * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection + * @retval None + */ +void HAL_RCCEx_SelectLSEMode(uint8_t Mode) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE_MODE(Mode)); + if (Mode == RCC_LSE_HIGHDRIVE_MODE) + { + SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } + else + { + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } +} + +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of PLLI2S, PLLSAI. +@endverbatim + * @{ + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Enable PLLI2S. + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM)); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ +#if defined(RCC_PLLI2SCFGR_PLLI2SP) + assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); +#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLI2S division factors */ +#if defined(STM32F446xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F411xE) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#else + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#endif /* STM32F446xx */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Wait till PLLI2S is ready */ + tickstart = HAL_GetTick(); + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart; + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Enable PLLSAI. + * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that + * contains the configuration information for the PLLSAI + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); +#if defined(RCC_PLLSAICFGR_PLLSAIM) + assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM)); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ +#if defined(RCC_PLLSAICFGR_PLLSAIP) + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); +#endif /* RCC_PLLSAICFGR_PLLSAIP */ +#if defined(RCC_PLLSAICFGR_PLLSAIR) + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLSAI division factors */ +#if defined(STM32F446xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \ + PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U); +#elif defined(STM32F469xx) || defined(STM32F479xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ + PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#else + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#endif /* STM32F446xx */ + + /* Enable the PLLSAI */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Wait till PLLSAI is ready */ + tickstart = HAL_GetTick(); + while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLSAI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) +{ + uint32_t tickstart; + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @} + */ + +#if defined(STM32F446xx) +/** + * @brief Returns the SYSCLK frequency + * + * @note This function implementation is valid only for STM32F446xx devices. + * @note This function add the PLL/PLLR System clock source + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllm = 0U; + uint32_t pllvco = 0U; + uint32_t pllp = 0U; + uint32_t pllr = 0U; + uint32_t sysclockfreq = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + break; + } + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); + + sysclockfreq = pllvco / pllp; + break; + } + case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); + + sysclockfreq = pllvco / pllr; + break; + } + default: + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} +#endif /* STM32F446xx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL, PLLI2S and PLLSAI OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[4:0] bits to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear HSEON, HSEBYP and CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + +#if defined(RCC_PLLI2S_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLI2SON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); + + /* Wait till PLLI2S is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLSAI bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); + + /* Wait till PLLSAI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLSAI_SUPPORT */ + + /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ +#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1; +#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) + RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3; +#else + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2; +#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */ + + /* Reset PLLI2SCFGR register to default value */ +#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; +#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; +#elif defined(STM32F411xE) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; +#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */ + + /* Reset PLLSAICFGR register */ +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1; +#elif defined(STM32F446xx) + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2; +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */ + + /* Disable all interrupts */ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE); + +#if defined(RCC_CIR_PLLI2SRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +#endif /* RCC_CIR_PLLI2SRDYIE */ + +#if defined(RCC_CIR_PLLSAIRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +#endif /* RCC_CIR_PLLSAIRDYIE */ + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | + RCC_CIR_CSSC); + +#if defined(RCC_CIR_PLLI2SRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +#endif /* RCC_CIR_PLLI2SRDYC */ + +#if defined(RCC_CIR_PLLSAIRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +#endif /* RCC_CIR_PLLSAIRDYC */ + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this API. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this API. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note This function add the PLL/PLLR factor management during PLL configuration this feature + * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t pll_config; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ +#if defined(STM32F446xx) + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) + || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) +#else + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) + || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) +#endif /* STM32F446xx */ + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ +#if defined(STM32F446xx) + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) + || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) +#else + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) + || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) +#endif /* STM32F446xx */ + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ + RCC_OscInitStruct->PLL.PLLM | \ + (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ + (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ + (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ + (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; +#if defined (RCC_PLLCFGR_PLLR) + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) +#else + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) +#endif /* RCC_PLLCFGR_PLLR */ + { + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured. + * + * @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. + * @note This function add the PLL/PLLR factor management + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); +} +#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c new file mode 100644 index 00000000..f056ebf2 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c @@ -0,0 +1,7629 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + default: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) + { + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_4) + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + else + { + status = HAL_ERROR; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + HAL_StatusTypeDef status = HAL_OK; + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances + * supporting a break input. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + default: + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + status = HAL_ERROR; + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c new file mode 100644 index 00000000..889f8fb9 --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c @@ -0,0 +1,2410 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM1, the parameter can have the following values: (**) + * @arg TIM_TIM1_TIM3_TRGO: TIM1 ITR2 is connected to TIM3 TRGO + * @arg TIM_TIM1_LPTIM: TIM1 ITR2 is connected to LPTIM1 output + * + * For TIM2, the parameter can have the following values: (**) + * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 is connected to TIM8 TRGO (*) + * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 is connected to PTP trigger output (*) + * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 is connected to OTG FS SOF + * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 is connected to OTG FS SOF + * + * For TIM5, the parameter can have the following values: + * @arg TIM_TIM5_GPIO: TIM5 TI4 is connected to GPIO + * @arg TIM_TIM5_LSI: TIM5 TI4 is connected to LSI + * @arg TIM_TIM5_LSE: TIM5 TI4 is connected to LSE + * @arg TIM_TIM5_RTC: TIM5 TI4 is connected to the RTC wakeup interrupt + * @arg TIM_TIM5_TIM3_TRGO: TIM5 ITR1 is connected to TIM3 TRGO (*) + * @arg TIM_TIM5_LPTIM: TIM5 ITR1 is connected to LPTIM1 output (*) + * + * For TIM9, the parameter can have the following values: (**) + * @arg TIM_TIM9_TIM3_TRGO: TIM9 ITR1 is connected to TIM3 TRGO + * @arg TIM_TIM9_LPTIM: TIM9 ITR1 is connected to LPTIM1 output + * + * For TIM11, the parameter can have the following values: + * @arg TIM_TIM11_GPIO: TIM11 TI1 is connected to GPIO + * @arg TIM_TIM11_HSE: TIM11 TI1 is connected to HSE_RTC clock + * @arg TIM_TIM11_SPDIFRX: TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC (*) + * + * (*) Value not defined in all devices. \n + * (**) Register not available in all devices. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Check parameters */ + assert_param(IS_TIM_REMAP(htim->Instance, Remap)); + + __HAL_LOCK(htim); + +#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP) + if ((Remap & LPTIM_REMAP_MASK) == LPTIM_REMAP_MASK) + { + /* Connect TIMx internal trigger to LPTIM1 output */ + __HAL_RCC_LPTIM1_CLK_ENABLE(); + MODIFY_REG(LPTIM1->OR, + (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP), + Remap & ~(LPTIM_REMAP_MASK)); + } + else + { + /* Set the Timer remapping configuration */ + WRITE_REG(htim->Instance->OR, Remap); + } +#else + /* Set the Timer remapping configuration */ + WRITE_REG(htim->Instance->OR, Remap); +#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */ + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Commutation callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Commutation half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c new file mode 100644 index 00000000..cf6d201b --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c @@ -0,0 +1,3807 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (##) Enable the USARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure the UART TX/RX pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx stream. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required + Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx stream. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx stream. + (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle + (used for last byte sending completion detection in DMA non circular mode) + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the huart Init structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. + + (#) For the Multi-Processor mode, initialize the UART registers by calling + the HAL_MultiProcessor_Init() API. + + [..] + (@) The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit + and receive process. + + [..] + (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the + low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized + HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_UART_Transmit() + (+) Receive an amount of data in blocking mode using HAL_UART_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() + (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() + (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + (+) Pause the DMA Transfer using HAL_UART_DMAPause() + (+) Resume the DMA Transfer using HAL_UART_DMAResume() + (+) Stop the DMA Transfer using HAL_UART_DMAStop() + + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (+) Detection of inactivity period (RX line has not been active for a given period). + (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + + (#) There are two mode of transfer: + (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (+) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (+) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (+) HAL_UARTEx_ReceiveToIdle_DMA() + + + *** UART HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in UART HAL driver. + + (+) __HAL_UART_ENABLE: Enable the UART peripheral + (+) __HAL_UART_DISABLE: Disable the UART peripheral + (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not + (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag + (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt + (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt + (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not + + [..] + (@) You can refer to the UART HAL driver header file for more useful macros + + @endverbatim + [..] + (@) Additional remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible UART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | UART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup UART_Private_Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +static void UART_SetConfig(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + please refer to Reference manual for possible UART frame formats. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs + follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration + procedures (details for the procedures are available in reference manual + (RM0430 for STM32F4X3xx MCUs and RM0402 for STM32F412xx MCUs + RM0383 for STM32F411xC/E MCUs and RM0401 for STM32F410xx MCUs + RM0090 for STM32F4X5xx/STM32F4X7xx/STM32F429xx/STM32F439xx MCUs + RM0390 for STM32F446xx MCUs and RM0386 for STM32F469xx/STM32F479xx MCUs)). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the UART mode according to the specified parameters in + * the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* The hardware flow control is available only for USART1, USART2, USART3 and USART6. + Except for STM32F446xx devices, that is available for USART1, USART2, USART3, USART6, UART4 and UART5. + */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + } + else + { + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief Initializes the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief Initializes the LIN mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection + * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In LIN mode, the following bits must be kept cleared: + - CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL); + SET_BIT(huart->Instance->CR2, BreakDetectLength); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief Initializes the Multi-Processor mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Address USART address + * @param WakeUpMethod specifies the USART wake-up method. + * This parameter can be one of the following values: + * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection + * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Check the Address & wake up method parameters */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + assert_param(IS_UART_ADDRESS(Address)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In Multi-Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Set the USART address node */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD); + SET_BIT(huart->Instance->CR2, Address); + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE); + SET_BIT(huart->Instance->CR1, WakeUpMethod); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief DeInitializes the UART peripheral. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Process Unlock */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief UART MSP Init. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspInit could be implemented in the user file + */ +} + +/** + * @brief UART MSP DeInit. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used instead of the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), + * HAL_MultiProcessor_Init() to register callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() to un-register callbacks for HAL_UART_MSPINIT_CB_ID + * and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + return status; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts + or DMA, these API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected. + + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (+) HAL_UART_Abort() + (+) HAL_UART_AbortTransmit() + (+) HAL_UART_AbortReceive() + (+) HAL_UART_Abort_IT() + (+) HAL_UART_AbortTransmit_IT() + (+) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (+) HAL_UART_AbortCpltCallback() + (+) HAL_UART_AbortTransmitCpltCallback() + (+) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: + (+) HAL_UARTEx_RxEventCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart = 0U; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart = 0U; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Check the remain data to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF); + pdata16bits++; + } + else + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Enable the UART Transmit data register empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return (UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + const uint32_t *tmp; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA stream */ + tmp = (const uint32_t *)&pData; + if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return (UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pauses the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + uint32_t dmarequest = 0x00U; + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + /* Disable the UART DMA Tx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_UART_CLEAR_OREFLAG(huart); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + uint32_t dmarequest = 0x00U; + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() + */ + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream */ + if (huart->hdmatx != NULL) + { + HAL_DMA_Abort(huart->hdmatx); + } + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream */ + if (huart->hdmarx != NULL) + { + HAL_DMA_Abort(huart->hdmarx); + } + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_IDLEFLAG(huart); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + pdata16bits++; + } + else + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_IT(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_IDLEFLAG(huart); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_IDLEFLAG(huart); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (returned value will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return(huart->RxEventType); +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream: use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream: use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->RxState and huart->gState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t AbortCplt = 0x01U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + AbortCplt = 0x01U; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (AbortCplt == 0x01U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief This function handles UART interrupt request. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->SR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + uint32_t errorflags = 0x00U; + uint32_t dmarequest = 0x00U; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); + if (errorflags == RESET) + { + /* UART in mode Receiver -------------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + return; + } + } + + /* If some errors occur */ + if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + { + /* UART parity error interrupt occurred ----------------------------------*/ + if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART noise error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART frame error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART Over-Run interrupt occurred --------------------------------------*/ + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) + || ((cr3its & USART_CR3_EIE) != RESET))) + { + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver -----------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_SR_IDLE) != 0U) + && ((cr1its & USART_CR1_IDLEIE) != 0U)) + { + __HAL_UART_CLEAR_IDLEFLAG(huart); + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } + return; + } + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + return; + } + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) + { + UART_Transmit_IT(huart); + return; + } + + /* UART in mode Transmitter end --------------------------------------------*/ + if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + { + UART_EndTransmit_IT(huart); + return; + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief UART error callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART: + (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character. + (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. + (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software. + (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode + (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode + +@endverbatim + * @{ + */ + +/** + * @brief Transmits break characters. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_SBK); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enters the UART in mute mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RWU); + + huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Exits the UART mute mode: wake up software. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); + + huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART transmitter and disables the UART receiver. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_TE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART receiver and disables the UART transmitter. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_RE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief UART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + UART communication process, return Peripheral Errors occurred during communication + process + (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral. + (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the UART state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +{ + uint32_t temp1 = 0x00U, temp2 = 0x00U; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART error code + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief DMA UART transmit process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* DMA Normal mode*/ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) + { + huart->TxXferCount = 0x00U; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* DMA Normal mode*/ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) + { + huart->RxXferCount = 0U; + + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize / 2U); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + uint32_t dmarequest = 0x00U; + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + huart->TxXferCount = 0x00U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + huart->RxXferCount = 0x00U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Flag specifies the UART flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + + return HAL_TIMEOUT; + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_OREFLAG(huart); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->Init.Parity != UART_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + + /* Enable the UART Data Register not empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); + + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + tmp = (uint32_t *)&pData; + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ + __HAL_UART_CLEAR_OREFLAG(huart); + + if (huart->Init.Parity != UART_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + huart->RxXferCount = 0x00U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); + huart->pTxBuffPtr += 2U; + } + else + { + huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); + } + + if (--huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + return HAL_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +{ + uint8_t *pdata8bits = NULL; + uint16_t *pdata16bits = NULL; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + /* Unused pdata8bits */ + UNUSED(pdata8bits); + pdata16bits = (uint16_t *) huart->pRxBuffPtr; + *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + huart->pRxBuffPtr += 2U; + } + else + { + pdata8bits = (uint8_t *) huart->pRxBuffPtr; + /* Unused pdata16bits */ + UNUSED(pdata16bits); + + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + huart->pRxBuffPtr += 1U; + } + + if (--huart->RxXferCount == 0U) + { + /* Disable the UART Data Register not empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_IDLEFLAG(huart); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures the UART peripheral. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits + according to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the UART Word Length, Parity and mode: + Set the M bits according to huart->Init.WordLength value + Set PCE and PS bits according to huart->Init.Parity value + Set TE and RE bits according to huart->Init.Mode value + Set OVER8 bit according to huart->Init.OverSampling value */ + + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; + MODIFY_REG(huart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ + MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); + + +#if defined(USART6) && defined(UART9) && defined(UART10) + if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) + { + pclk = HAL_RCC_GetPCLK2Freq(); + } +#elif defined(USART6) + if ((huart->Instance == USART1) || (huart->Instance == USART6)) + { + pclk = HAL_RCC_GetPCLK2Freq(); + } +#else + if (huart->Instance == USART1) + { + pclk = HAL_RCC_GetPCLK2Freq(); + } +#endif /* USART6 */ + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + } + /*-------------------------- USART BRR Configuration ---------------------*/ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } + else + { + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c new file mode 100644 index 00000000..7d98361b --- /dev/null +++ b/firmware/numpad/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -0,0 +1,2323 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_usb.c + * @author MCD Application Team + * @brief USB Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Fill parameters of Init structure in USB_CfgTypeDef structure. + + (#) Call USB_CoreInit() API to initialize the USB Core peripheral. + + (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + + @endverbatim + + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_LL_USB_DRIVER + * @{ + */ + +#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ + +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the USB Core + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Init The ULPI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + if (cfg.use_external_vbus == 1U) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + } + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + } + else /* FS interface (embedded Phy) */ + { + /* Select FS Embedded PHY */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + if (cfg.battery_charging_enable == 0U) + { + /* Activate the USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + else + { + /* Deactivate the USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + } + + if (cfg.dma_enable == 1U) + { + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + } + + return ret; +} + + +/** + * @brief Set the USB turnaround time + * @param USBx USB Instance + * @param hclk: AHB clock frequency + * @retval USB turnaround time In PHY Clocks number + */ +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, + uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USBD_FS_SPEED) + { + if ((hclk >= 14200000U) && (hclk < 15000000U)) + { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } + else if ((hclk >= 15000000U) && (hclk < 16000000U)) + { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } + else if ((hclk >= 16000000U) && (hclk < 17200000U)) + { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } + else if ((hclk >= 17200000U) && (hclk < 18500000U)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } + else if ((hclk >= 18500000U) && (hclk < 20000000U)) + { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } + else if ((hclk >= 20000000U) && (hclk < 21800000U)) + { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } + else if ((hclk >= 21800000U) && (hclk < 24000000U)) + { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } + else if ((hclk >= 24000000U) && (hclk < 27700000U)) + { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } + else if ((hclk >= 27700000U) && (hclk < 32000000U)) + { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } + else if (speed == USBD_HS_SPEED) + { + UsbTrd = USBD_HS_TRDT_VALUE; + } + else + { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + + return HAL_OK; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode + * This parameter can be one of these values: + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) +{ + uint32_t ms = 0U; + + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + + do + { + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); + } + else if (mode == USB_DEVICE_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + + do + { + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); + } + else + { + return HAL_ERROR; + } + + if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_DevInit Initializes the USB_OTG controller registers + * for device mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } + +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) + /* VBUS Sensing setup */ + if (cfg.vbus_sensing_enable == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + /* Deactivate VBUS Sensing B */ + USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + /* B-peripheral session valid override enable */ + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + } + else + { + /* Enable HW VBUS sensing */ + USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + } +#else + /* VBUS Sensing setup */ + if (cfg.vbus_sensing_enable == 0U) + { + /* + * Disable HW VBUS sensing. VBUS is internally considered to be always + * at VBUS-Valid level (5V). + */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + } + else + { + /* Enable HW VBUS sensing */ + USBx->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; + USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + } +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + if (cfg.speed == USBD_HS_SPEED) + { + /* Set Core speed to High speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); + } + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); + } + + /* Flush the FIFOs */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending Device Interrupts */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } + } + else + { + USBx_INEP(i)->DIEPCTL = 0U; + } + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + } + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } + } + else + { + USBx_OUTEP(i)->DOEPCTL = 0U; + } + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xBFFFFFFFU; + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; + + if (cfg.Sof_enable != 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; + } + + if (cfg.vbus_sensing_enable == 1U) + { + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + } + + return ret; +} + +/** + * @brief USB_FlushTxFifo Flush a Tx FIFO + * @param USBx Selected device + * @param num FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush TX Fifo */ + count = 0U; + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo Flush Rx FIFO + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush RX Fifo */ + count = 0U; + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register + * depending the PHY type and the enumeration speed of the device. + * @param USBx Selected device + * @param speed device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG |= speed; + return HAL_OK; +} + +/** + * @brief USB_GetDevSpeed Return the Dev Speed + * @param USBx Selected device + * @retval speed device speed + * This parameter can be one of these values: + * @arg USBD_HS_SPEED: High speed mode + * @arg USBD_FS_SPEED: Full speed mode + */ +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + { + speed = USBD_HS_SPEED; + } + else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + { + speed = USBD_FS_SPEED; + } + else + { + speed = 0xFU; + } + + return speed; +} + +/** + * @brief Activate and configure an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + } + else + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } + } + return HAL_OK; +} + +/** + * @brief Activate and configure a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + } + + return HAL_OK; +} + +/** + * @brief USB_EPStartXfer : setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); + } + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + } + + if (dma == 1U) + { + if ((uint32_t)ep->dma_addr != 0U) + { + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + } + else + { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + else + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + } + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; + + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + } + } + + if (dma == 1U) + { + if ((uint32_t)ep->xfer_buff != 0U) + { + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + } + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } + else + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } + } + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* EP enable, IN data in FIFO */ + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } + } + else /* OUT endpoint */ + { + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } + } + + return ret; +} + + +/** + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * with the EP/channel + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pSrc = src; + uint32_t count32b; + uint32_t i; + + if (dma == 0U) + { + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) + { + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + pSrc++; + pSrc++; + pSrc++; + } + } + + return HAL_OK; +} + +/** + * @brief USB_ReadPacket : read a packet from the RX FIFO + * @param USBx Selected device + * @param dest source pointer + * @param len Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pDest = dest; + uint32_t pData; + uint32_t i; + uint32_t count32b = (uint32_t)len >> 2U; + uint16_t remaining_bytes = len % 4U; + + for (i = 0U; i < count32b; i++) + { + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + pDest++; + pDest++; + pDest++; + pDest++; + } + + /* When Number of data is not word aligned, read the remaining byte */ + if (remaining_bytes != 0U) + { + i = 0U; + __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); + + do + { + *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); + i++; + pDest++; + remaining_bytes--; + } while (remaining_bytes != 0U); + } + + return ((void *)pDest); +} + +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} + +/** + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Clear Pending interrupt */ + for (i = 0U; i < 15U; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + /* Flush the FIFO */ + ret = USB_FlushRxFifo(USBx); + if (ret != HAL_OK) + { + return ret; + } + + ret = USB_FlushTxFifo(USBx, 0x10U); + if (ret != HAL_OK) + { + return ret; + } + + return ret; +} + +/** + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + + return HAL_OK; +} + +/** + * @brief USB_DevConnect : Connect the USB device by enabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx Selected device + * @retval USB Global Interrupt status + */ +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->GINTSTS; + tmpreg &= USBx->GINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadChInterrupts: return USB channel interrupt status + * @param USBx Selected device + * @param chnum Channel number + * @retval USB Channel Interrupt status + */ +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_HC(chnum)->HCINT; + tmpreg &= USBx_HC(chnum)->HCINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USBx Selected device + * @retval USB Device OUT EP interrupt status + */ +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status + * @param USBx Selected device + * @retval USB Device IN EP interrupt status + */ +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USBx_DEVICE->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + uint32_t msk; + uint32_t emp; + + msk = USBx_DEVICE->DIEPMSK; + emp = USBx_DEVICE->DIEPEMPMSK; + msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; +} + +/** + * @brief USB_ClearInterrupts: clear a USB interrupt + * @param USBx Selected device + * @param interrupt flag + * @retval None + */ +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +{ + USBx->GINTSTS &= interrupt; +} + +/** + * @brief Returns USB core mode + * @param USBx Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 1 : Host + * 0 : Device + */ +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) +{ + return ((USBx->GINTSTS) & 0x1U); +} + +/** + * @brief Activate EP0 for Setup transactions + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* Set the MPS of the IN EP0 to 64 bytes */ + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; + + return HAL_OK; +} + +/** + * @brief Prepare the EP0 to start the first control setup + * @param USBx Selected device + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + + if (gSNPSiD > USB_OTG_CORE_ID_300A) + { + if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + return HAL_OK; + } + } + + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + + if (dma == 1U) + { + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + /* EP enable */ + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + } + + return HAL_OK; +} + +/** + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + count = 10U; + + /* few cycles before setting core reset */ + while (count > 0U) + { + count--; + } + + /* Core Soft Reset */ + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + + return HAL_OK; +} + +/** + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ + || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ + || defined(STM32F423xx) + /* Disable HW VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); +#else + /* + * Disable HW VBUS sensing. VBUS is internally considered to be always + * at VBUS-Valid level (5V). + */ + USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || + defined(STM32F423xx) */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) \ + || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); +#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + if (cfg.speed == USBH_FSLS_SPEED) + { + /* Force Device Enumeration to FS/LS mode only */ + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + + /* Make sure the FIFOs are flushed. */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + { + USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; + USBx_HC(i)->HCINTMSK = 0U; + } + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x200U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + } + else +#endif /* defined (USB_OTG_HS) */ + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + } + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + return ret; +} + +/** + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * HCFG register on the PHY type and set the right frame interval + * @param USBx Selected device + * @param freq clock frequency + * This parameter can be one of these values: + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval HAL status + */ +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = HFIR_48_MHZ; + } + else if (freq == HCFG_6_MHZ) + { + USBx_HOST->HFIR = HFIR_6_MHZ; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_OTG_ResetPort : Reset Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + HAL_Delay(100U); /* See Note #1 */ + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay(10U); + + return HAL_OK; +} + +/** + * @brief USB_DriveVbus : activate or de-activate vbus + * @param state VBUS state + * This parameter can be one of these values: + * 0 : Deactivate VBUS + * 1 : Activate VBUS + * @retval HAL status + */ +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) + { + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) + { + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + } + return HAL_OK; +} + +/** + * @brief Return Host Port speed + * @param USBx Selected device + * @retval speed : Host port device speed + * This parameter can be one of these values: + * @arg HCD_DEVICE_SPEED_HIGH: High speed mode + * @arg HCD_DEVICE_SPEED_FULL: Full speed mode + * @arg HCD_DEVICE_SPEED_LOW: Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); +} + +/** + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); +} + +/** + * @brief Initialize a host channel + * @param USBx Selected device + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @arg USB_OTG_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochronous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to 32K + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir; + uint32_t HCcharLowSpeed; + uint32_t HostCoreSpeed; + + /* Clear old interrupt conditions for this host channel. */ + USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; + + /* Enable channel interrupts required for this transfer. */ + switch (ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + else + { +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM; + } +#endif /* defined (USB_OTG_HS) */ + } + break; + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + + /* Enable host channel Halt interrupt */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; + + /* Enable the top level host channel interrupt. */ + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + /* Make sure host channel interrupts are enabled. */ + USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + HostCoreSpeed = USB_GetHostSpeed(USBx); + + /* LS device plugged to HUB */ + if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | + USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; + + if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) + { + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + } + + return ret; +} + +/** + * @brief Start a transfer over a host channel + * @param USBx Selected device + * @param hc pointer to host channel structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + __IO uint32_t tmpreg; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; + +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ + if (dma == 1U) + { + if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) + { + + USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NAKM); + } + } + else + { + if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U)) + { + (void)USB_DoPing(USBx, hc->ch_num); + return HAL_OK; + } + } + } +#endif /* defined (USB_OTG_HS) */ + + if (hc->do_ssplit == 1U) + { + /* Set number of packet to 1 for Split transaction */ + num_packets = 1U; + + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + if (hc->ep_type == EP_TYPE_ISOC) + { + if (hc->xfer_len > ISO_SPLT_MPS) + { + /* Isochrone Max Packet Size for Split mode */ + hc->XferSize = hc->max_packet; + hc->xfer_len = hc->XferSize; + + if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_MIDDLE; + } + else + { + hc->iso_splt_xactPos = HCSPLT_BEGIN; + } + } + else + { + hc->XferSize = hc->xfer_len; + + if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_FULL; + } + else + { + hc->iso_splt_xactPos = HCSPLT_END; + } + } + } + else + { + if ((dma == 1U) && (hc->xfer_len > hc->max_packet)) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + } + } + else + { + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + + /* Initialize the HCTSIZn register */ + USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + + if (dma != 0U) + { + /* xfer_buff MUST be 32-bits aligned */ + USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + } + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + if (hc->do_ssplit == 1U) + { + /* Set Hub start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) | + (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN; + + /* unmask ack & nyet for IN/OUT transactions */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NYET); + + if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + } + + if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) && + (hc->do_csplit == 1U) && (hc->ep_is_in == 1U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + } + + /* Position management for iso out transaction on split mode */ + if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U)) + { + /* Set data payload position */ + switch (hc->iso_splt_xactPos) + { + case HCSPLT_BEGIN: + /* First data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1; + break; + + case HCSPLT_MIDDLE: + /* Middle data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos; + break; + + case HCSPLT_END: + /* End data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0; + break; + + case HCSPLT_FULL: + /* Entire data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS; + break; + + default: + break; + } + } + } + else + { + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + } + + /* Set host channel enable */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + + if (dma != 0U) /* dma mode */ + { + return HAL_OK; + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U)) + { + switch (hc->ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + } + + return HAL_OK; +} + +/** + * @brief Read all host channel interrupts status + * @param USBx Selected device + * @retval HAL state + */ +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); +} + +/** + * @brief Halt a host channel + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + __IO uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; + + /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. + At the end of the next uframe/frame (in the worst case), the core generates a channel halted + and disables the channel automatically. */ + + if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && + ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) + { + return HAL_OK; + } + + /* Check for space in the request queue to issue the halt. */ + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) + { + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + + return HAL_OK; +} + +/** + * @brief Initiate Do Ping protocol + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; + + /* Set host channel enable */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + + return HAL_OK; +} + +/** + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t count = 0U; + uint32_t value; + uint32_t i; + + (void)USB_DisableGlobalInt(USBx); + + /* Flush USB FIFO */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Flush out any leftover queued requests. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + } + + /* Halt all channels to put them into a known state. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value |= USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; + + (void)USB_EnableGlobalInt(USBx); + + return ret; +} + +/** + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + } + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ + +/** + * @} + */ diff --git a/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h new file mode 100644 index 00000000..b6e8d43e --- /dev/null +++ b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h @@ -0,0 +1,190 @@ +/** + ****************************************************************************** + * @file usbd_hid.h + * @author MCD Application Team + * @brief Header file for the usbd_hid_core.c file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_HID_H +#define __USB_HID_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_HID + * @brief This file is the Header file for usbd_hid.c + * @{ + */ + + +///** @defgroup USBD_HID_Exported_Defines +// * @{ +// */ +//#ifndef HID_EPIN_ADDR +//#define HID_EPIN_ADDR 0x81U +//#endif /* HID_EPIN_ADDR */ +//#define HID_EPIN_SIZE 0x04U +// +//#define USB_HID_CONFIG_DESC_SIZ 34U +//#define USB_HID_DESC_SIZ 9U +//#define HID_MOUSE_REPORT_DESC_SIZE 63U +// +//#define HID_DESCRIPTOR_TYPE 0x21U +//#define HID_REPORT_DESC 0x22U +// +//#ifndef HID_HS_BINTERVAL +//#define HID_HS_BINTERVAL 0x07U +//#endif /* HID_HS_BINTERVAL */ +// +//#ifndef HID_FS_BINTERVAL +//#define HID_FS_BINTERVAL 0x0AU +//#endif /* HID_FS_BINTERVAL */ +// +//#define USBD_HID_REQ_SET_PROTOCOL 0x0BU +//#define USBD_HID_REQ_GET_PROTOCOL 0x03U +// +//#define USBD_HID_REQ_SET_IDLE 0x0AU +//#define USBD_HID_REQ_GET_IDLE 0x02U +// +//#define USBD_HID_REQ_SET_REPORT 0x09U +//#define USBD_HID_REQ_GET_REPORT 0x01U +///** +// * @} +// */ + +/** @defgroup USBD_HID_Exported_Defines + * @{ + */ +#ifndef HID_EPIN_ADDR +#define HID_EPIN_ADDR 0x81U +#endif /* HID_EPIN_ADDR */ +#define HID_EPIN_SIZE 0x0EU + +#define USB_HID_CONFIG_DESC_SIZ 34U +#define USB_HID_DESC_SIZ 9U +#define HID_MOUSE_REPORT_DESC_SIZE 0x2DU + +#define HID_DESCRIPTOR_TYPE 0x21U +#define HID_REPORT_DESC 0x22U + +#ifndef HID_HS_BINTERVAL +#define HID_HS_BINTERVAL 0x07U +#endif /* HID_HS_BINTERVAL */ + +#ifndef HID_FS_BINTERVAL +#define HID_FS_BINTERVAL 0x0AU +#endif /* HID_FS_BINTERVAL */ + +#define USBD_HID_REQ_SET_PROTOCOL 0x0BU +#define USBD_HID_REQ_GET_PROTOCOL 0x03U + +#define USBD_HID_REQ_SET_IDLE 0x0AU +#define USBD_HID_REQ_GET_IDLE 0x02U + +#define USBD_HID_REQ_SET_REPORT 0x09U +#define USBD_HID_REQ_GET_REPORT 0x01U +/** + * @} + */ + +typedef enum +{ + USBD_HID_IDLE = 0, + USBD_HID_BUSY, +} USBD_HID_StateTypeDef; + + +typedef struct +{ + uint32_t Protocol; + uint32_t IdleState; + uint32_t AltSetting; + USBD_HID_StateTypeDef state; +} USBD_HID_HandleTypeDef; + +/* + * HID Class specification version 1.1 + * 6.2.1 HID Descriptor + */ + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bHIDDescriptorType; + uint16_t wItemLength; +} __PACKED USBD_HIDDescTypeDef; + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_ClassTypeDef USBD_HID; +#define USBD_HID_CLASS &USBD_HID +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +#ifdef USE_USBD_COMPOSITE +uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId); +#else +uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len); +#endif /* USE_USBD_COMPOSITE */ +uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HID_H */ +/** + * @} + */ + +/** + * @} + */ diff --git a/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c new file mode 100644 index 00000000..1040f939 --- /dev/null +++ b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c @@ -0,0 +1,674 @@ +/** + ****************************************************************************** + * @file usbd_hid.c + * @author MCD Application Team + * @brief This file provides the HID core functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * @verbatim + * + * =================================================================== + * HID Class Description + * =================================================================== + * This module manages the HID class V1.11 following the "Device Class Definition + * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001". + * This driver implements the following aspects of the specification: + * - The Boot Interface Subclass + * - The Mouse protocol + * - Usage Page : Generic Desktop + * - Usage : Joystick + * - Collection : Application + * + * @note In HS mode and when the DMA is used, all variables and data structures + * dealing with the DMA during the transaction process should be 32-bit aligned. + * + * + * @endverbatim + * + ****************************************************************************** + */ + +/* BSPDependencies +- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c" +- "stm32xxxxx_{eval}{discovery}_io.c" +EndBSPDependencies */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_hid.h" +#include "usbd_ctlreq.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_HID + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_HID_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_HID_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_HID_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_HID_Private_FunctionPrototypes + * @{ + */ + +static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); +#ifndef USE_USBD_COMPOSITE +static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length); +static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length); +static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length); +static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length); +#endif /* USE_USBD_COMPOSITE */ +/** + * @} + */ + +/** @defgroup USBD_HID_Private_Variables + * @{ + */ + +USBD_ClassTypeDef USBD_HID = +{ + USBD_HID_Init, + USBD_HID_DeInit, + USBD_HID_Setup, + NULL, /* EP0_TxSent */ + NULL, /* EP0_RxReady */ + USBD_HID_DataIn, /* DataIn */ + NULL, /* DataOut */ + NULL, /* SOF */ + NULL, + NULL, +#ifdef USE_USBD_COMPOSITE + NULL, + NULL, + NULL, + NULL, +#else + USBD_HID_GetHSCfgDesc, + USBD_HID_GetFSCfgDesc, + USBD_HID_GetOtherSpeedCfgDesc, + USBD_HID_GetDeviceQualifierDesc, +#endif /* USE_USBD_COMPOSITE */ +}; + +#ifndef USE_USBD_COMPOSITE +/* USB HID device FS Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_HID_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor + describing the configuration */ +#if (USBD_SELF_POWERED == 1U) + 0xE0, /* bmAttributes: Bus Powered according to user configuration */ +#else + 0xA0, /* bmAttributes: Bus Powered according to user configuration */ +#endif /* USBD_SELF_POWERED */ + USBD_MAX_POWER, /* MaxPower (mA) */ + + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x00, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x0, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/ + + HID_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_EPIN_SIZE, /* wMaxPacketSize: 4 Bytes max */ + 0x00, + HID_FS_BINTERVAL, /* bInterval: Polling Interval */ + /* 34 */ +}; +#endif /* USE_USBD_COMPOSITE */ + +/* USB HID device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_DESC_SIZ] __ALIGN_END = +{ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, +}; + +#ifndef USE_USBD_COMPOSITE +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +{ + USB_LEN_DEV_QUALIFIER_DESC, + USB_DESC_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +}; +#endif /* USE_USBD_COMPOSITE */ + +__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END = +{ +// 0x05, 0x01, // USAGE_PAGE (Generic Desktop) +// 0x09, 0x06, // USAGE (Keyboard) +// 0xa1, 0x01, // COLLECTION (Application) +// 0x05, 0x07, // USAGE_PAGE (Keyboard) +// 0x19, 0xe0, // USAGE_MINIMUM (Keyboard LeftControl) +// 0x29, 0xe7, // USAGE_MAXIMUM (Keyboard Right GUI) +// 0x15, 0x00, // LOGICAL_MINIMUM (0) +// 0x25, 0x01, // LOGICAL_MAXIMUM (1) +// 0x75, 0x01, // REPORT_SIZE (1) +// 0x95, 0x08, // REPORT_COUNT (8) +// 0x81, 0x02, // INPUT (Data,Var,Abs) +// 0x95, 0x01, // REPORT_COUNT (1) +// 0x75, 0x08, // REPORT_SIZE (8) +// 0x81, 0x03, // INPUT (Cnst,Var,Abs) +// 0x95, 0x05, // REPORT_COUNT (5) +// 0x75, 0x01, // REPORT_SIZE (1) +// 0x05, 0x08, // USAGE_PAGE (LEDs) +// 0x19, 0x01, // USAGE_MINIMUM (Num Lock) +// 0x29, 0x05, // USAGE_MAXIMUM (Kana) +// 0x91, 0x02, // OUTPUT (Data,Var,Abs) +// 0x95, 0x01, // REPORT_COUNT (1) +// 0x75, 0x03, // REPORT_SIZE (3) +// 0x91, 0x03, // OUTPUT (Cnst,Var,Abs) +// 0x95, 0x06, // REPORT_COUNT (6) +// 0x75, 0x08, // REPORT_SIZE (8) +// 0x15, 0x00, // LOGICAL_MINIMUM (0) +// 0x25, 0x65, // LOGICAL_MAXIMUM (101) +// 0x05, 0x07, // USAGE_PAGE (Keyboard) +// 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated)) +// 0x29, 0x65, // USAGE_MAXIMUM (Keyboard Application) +// 0x81, 0x00, // INPUT (Data,Ary,Abs) +// 0xc0 // END_COLLECTION + // 0xC0 /* End Collection */ + 0x05, 0x01, // Usage Page (Generic Desktop) + 0x09, 0x06, // Usage (Keyboard) + 0xA1, 0x01, // Collection (Application) + + // Modifiers (8 bits) + 0x05, 0x07, // Usage Page (Keyboard/Keypad) + 0x19, 0xE0, // Usage Minimum (224) - Left Control + 0x29, 0xE7, // Usage Maximum (231) - Right GUI + 0x15, 0x00, // Logical Minimum (0) + 0x25, 0x01, // Logical Maximum (1) + 0x75, 0x01, // Report Size (1 bit) + 0x95, 0x08, // Report Count (8 bits) + 0x81, 0x02, // Input (Data, Variable, Absolute) + + // Reserved byte (8 bits) + 0x75, 0x08, // Report Size (8 bits) + 0x95, 0x01, // Report Count (1) + 0x81, 0x01, // Input (Constant) + + // Key bitfield (96 bits = 12 bytes) + 0x05, 0x07, // Usage Page (Keyboard/Keypad) + 0x19, 0x04, // Usage Minimum (4) — 'A' key + 0x29, 0x63, // Usage Maximum (99) — 96 keys total (4 to 99) + 0x15, 0x00, // Logical Minimum (0) + 0x25, 0x01, // Logical Maximum (1) + 0x75, 0x01, // Report Size (1 bit) + 0x95, 0x60, // Report Count (96 bits) + 0x81, 0x02, // Input (Data, Variable, Absolute) + + 0xC0 // End Collection +}; + +static uint8_t HIDInEpAdd = HID_EPIN_ADDR; + +/** + * @} + */ + +/** @defgroup USBD_HID_Private_Functions + * @{ + */ + +/** + * @brief USBD_HID_Init + * Initialize the HID interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + UNUSED(cfgidx); + + USBD_HID_HandleTypeDef *hhid; + + hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); + + if (hhid == NULL) + { + pdev->pClassDataCmsit[pdev->classId] = NULL; + return (uint8_t)USBD_EMEM; + } + + pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; + pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; + +#ifdef USE_USBD_COMPOSITE + /* Get the Endpoints addresses allocated for this class instance */ + HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); +#endif /* USE_USBD_COMPOSITE */ + + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; + } + else /* LOW and FULL-speed endpoints */ + { + pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; + } + + /* Open EP IN */ + (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); + pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; + + hhid->state = USBD_HID_IDLE; + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_HID_DeInit + * DeInitialize the HID layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + UNUSED(cfgidx); + +#ifdef USE_USBD_COMPOSITE + /* Get the Endpoints addresses allocated for this class instance */ + HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); +#endif /* USE_USBD_COMPOSITE */ + + /* Close HID EPs */ + (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); + pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; + pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; + + /* Free allocated memory */ + if (pdev->pClassDataCmsit[pdev->classId] != NULL) + { + (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); + pdev->pClassDataCmsit[pdev->classId] = NULL; + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_HID_Setup + * Handle the HID specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + USBD_StatusTypeDef ret = USBD_OK; + uint16_t len; + uint8_t *pbuf; + uint16_t status_info = 0U; + + if (hhid == NULL) + { + return (uint8_t)USBD_FAIL; + } + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case USBD_HID_REQ_SET_PROTOCOL: + hhid->Protocol = (uint8_t)(req->wValue); + break; + + case USBD_HID_REQ_GET_PROTOCOL: + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); + break; + + case USBD_HID_REQ_SET_IDLE: + hhid->IdleState = (uint8_t)(req->wValue >> 8); + break; + + case USBD_HID_REQ_GET_IDLE: + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8) == HID_REPORT_DESC) + { + len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); + pbuf = HID_MOUSE_ReportDesc; + } + else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) + { + pbuf = USBD_HID_Desc; + len = MIN(USB_HID_DESC_SIZ, req->wLength); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + (void)USBD_CtlSendData(pdev, pbuf, len); + break; + + case USB_REQ_GET_INTERFACE : + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_SET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + hhid->AltSetting = (uint8_t)(req->wValue); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_CLEAR_FEATURE: + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + + return (uint8_t)ret; +} + + +/** + * @brief USBD_HID_SendReport + * Send HID Report + * @param pdev: device instance + * @param buff: pointer to report + * @param ClassId: The Class ID + * @retval status + */ +#ifdef USE_USBD_COMPOSITE +uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId) +{ + USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; +#else +uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) +{ + USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; +#endif /* USE_USBD_COMPOSITE */ + + if (hhid == NULL) + { + return (uint8_t)USBD_FAIL; + } + +#ifdef USE_USBD_COMPOSITE + /* Get the Endpoints addresses allocated for this class instance */ + HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId); +#endif /* USE_USBD_COMPOSITE */ + + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + if (hhid->state == USBD_HID_IDLE) + { + hhid->state = USBD_HID_BUSY; + (void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len); + } + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_HID_GetPollingInterval + * return polling interval from endpoint descriptor + * @param pdev: device instance + * @retval polling interval + */ +uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev) +{ + uint32_t polling_interval; + + /* HIGH-speed endpoints */ + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + /* Sets the data transfer polling interval for high speed transfers. + Values between 1..16 are allowed. Values correspond to interval + of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */ + polling_interval = (((1U << (HID_HS_BINTERVAL - 1U))) / 8U); + } + else /* LOW and FULL-speed endpoints */ + { + /* Sets the data transfer polling interval for low and full + speed transfers */ + polling_interval = HID_FS_BINTERVAL; + } + + return ((uint32_t)(polling_interval)); +} + +#ifndef USE_USBD_COMPOSITE +/** + * @brief USBD_HID_GetCfgFSDesc + * return FS configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) +{ + USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); + + if (pEpDesc != NULL) + { + pEpDesc->bInterval = HID_FS_BINTERVAL; + } + + *length = (uint16_t)sizeof(USBD_HID_CfgDesc); + return USBD_HID_CfgDesc; +} + +/** + * @brief USBD_HID_GetCfgHSDesc + * return HS configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) +{ + USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); + + if (pEpDesc != NULL) + { + pEpDesc->bInterval = HID_HS_BINTERVAL; + } + + *length = (uint16_t)sizeof(USBD_HID_CfgDesc); + return USBD_HID_CfgDesc; +} + +/** + * @brief USBD_HID_GetOtherSpeedCfgDesc + * return other speed configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) +{ + USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); + + if (pEpDesc != NULL) + { + pEpDesc->bInterval = HID_FS_BINTERVAL; + } + + *length = (uint16_t)sizeof(USBD_HID_CfgDesc); + return USBD_HID_CfgDesc; +} +#endif /* USE_USBD_COMPOSITE */ + +/** + * @brief USBD_HID_DataIn + * handle data IN Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ +static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + UNUSED(epnum); + /* Ensure that the FIFO is empty before a new transfer, this condition could + be caused by a new transfer before the end of the previous transfer */ + ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; + + return (uint8_t)USBD_OK; +} + +#ifndef USE_USBD_COMPOSITE +/** + * @brief DeviceQualifierDescriptor + * return Device Qualifier descriptor + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); + + return USBD_HID_DeviceQualifierDesc; +} +#endif /* USE_USBD_COMPOSITE */ +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ diff --git a/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h new file mode 100644 index 00000000..4672921b --- /dev/null +++ b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file usbd_core.h + * @author MCD Application Team + * @brief Header file for usbd_core.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" +#include "usbd_def.h" +#include "usbd_ioreq.h" +#include "usbd_ctlreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_CORE + * @brief This file is the Header file for usbd_core.c file + * @{ + */ + + +/** @defgroup USBD_CORE_Exported_Defines + * @{ + */ +#ifndef USBD_DEBUG_LEVEL +#define USBD_DEBUG_LEVEL 0U +#endif /* USBD_DEBUG_LEVEL */ +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ +#define USBD_SOF USBD_LL_SOF +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_FunctionsPrototype + * @{ + */ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id); +USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass); +#if (USBD_USER_REGISTER_CALLBACK == 1U) +USBD_StatusTypeDef USBD_RegisterDevStateCallback(USBD_HandleTypeDef *pdev, USBD_DevStateCallbackTypeDef pUserCallback); +#endif /* USBD_USER_REGISTER_CALLBACK */ + +#ifdef USE_USBD_COMPOSITE +USBD_StatusTypeDef USBD_RegisterClassComposite(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass, + USBD_CompositeClassTypeDef classtype, uint8_t *EpAddr); + +USBD_StatusTypeDef USBD_UnRegisterClassComposite(USBD_HandleTypeDef *pdev); +uint8_t USBD_CoreGetEPAdd(USBD_HandleTypeDef *pdev, uint8_t ep_dir, uint8_t ep_type, uint8_t ClassId); +#endif /* USE_USBD_COMPOSITE */ + +uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index); +uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index); + +USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); + +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup); +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata); +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata); + +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); + +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); + +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); + +/* USBD Low Level Driver */ +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev); + +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, + uint8_t ep_type, uint16_t ep_mps); + +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr); + +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, + uint8_t *pbuf, uint32_t size); + +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, + uint8_t *pbuf, uint32_t size); + +#ifdef USBD_HS_TESTMODE_ENABLE +USBD_StatusTypeDef USBD_LL_SetTestMode(USBD_HandleTypeDef *pdev, uint8_t testmode); +#endif /* USBD_HS_TESTMODE_ENABLE */ + +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr); + +void USBD_LL_Delay(uint32_t Delay); + +void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr); +USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CORE_H */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h new file mode 100644 index 00000000..6c45d6ce --- /dev/null +++ b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h @@ -0,0 +1,101 @@ +/** + ****************************************************************************** + * @file usbd_req.h + * @author MCD Application Team + * @brief Header file for the usbd_req.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_REQUEST_H +#define __USB_REQUEST_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_REQ + * @brief header file for the usbd_req.c file + * @{ + */ + +/** @defgroup USBD_REQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Exported_Types + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_REQ_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + +void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata); +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_REQUEST_H */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h new file mode 100644 index 00000000..5b2394e7 --- /dev/null +++ b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h @@ -0,0 +1,524 @@ +/** + ****************************************************************************** + * @file usbd_def.h + * @author MCD Application Team + * @brief General defines for the usb device library + ****************************************************************************** + * @attention + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_DEF_H +#define __USBD_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" + +/** @addtogroup STM32_USBD_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_DEF + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_DEF_Exported_Defines + * @{ + */ + +#ifndef NULL +#define NULL 0U +#endif /* NULL */ + +#ifndef USBD_MAX_NUM_INTERFACES +#define USBD_MAX_NUM_INTERFACES 1U +#endif /* USBD_MAX_NUM_CONFIGURATION */ + +#ifndef USBD_MAX_NUM_CONFIGURATION +#define USBD_MAX_NUM_CONFIGURATION 1U +#endif /* USBD_MAX_NUM_CONFIGURATION */ + +#ifdef USE_USBD_COMPOSITE +#ifndef USBD_MAX_SUPPORTED_CLASS +#define USBD_MAX_SUPPORTED_CLASS 4U +#endif /* USBD_MAX_SUPPORTED_CLASS */ +#else +#ifndef USBD_MAX_SUPPORTED_CLASS +#define USBD_MAX_SUPPORTED_CLASS 1U +#endif /* USBD_MAX_SUPPORTED_CLASS */ +#endif /* USE_USBD_COMPOSITE */ + +#ifndef USBD_MAX_CLASS_ENDPOINTS +#define USBD_MAX_CLASS_ENDPOINTS 5U +#endif /* USBD_MAX_CLASS_ENDPOINTS */ + +#ifndef USBD_MAX_CLASS_INTERFACES +#define USBD_MAX_CLASS_INTERFACES 5U +#endif /* USBD_MAX_CLASS_INTERFACES */ + +#ifndef USBD_LPM_ENABLED +#define USBD_LPM_ENABLED 0U +#endif /* USBD_LPM_ENABLED */ + +#ifndef USBD_SELF_POWERED +#define USBD_SELF_POWERED 1U +#endif /*USBD_SELF_POWERED */ + +#ifndef USBD_MAX_POWER +#define USBD_MAX_POWER 0x32U /* 100 mA */ +#endif /* USBD_MAX_POWER */ + +#ifndef USBD_SUPPORT_USER_STRING_DESC +#define USBD_SUPPORT_USER_STRING_DESC 0U +#endif /* USBD_SUPPORT_USER_STRING_DESC */ + +#ifndef USBD_CLASS_USER_STRING_DESC +#define USBD_CLASS_USER_STRING_DESC 0U +#endif /* USBD_CLASS_USER_STRING_DESC */ + +#define USB_LEN_DEV_QUALIFIER_DESC 0x0AU +#define USB_LEN_DEV_DESC 0x12U +#define USB_LEN_CFG_DESC 0x09U +#define USB_LEN_IF_DESC 0x09U +#define USB_LEN_EP_DESC 0x07U +#define USB_LEN_OTG_DESC 0x03U +#define USB_LEN_LANGID_STR_DESC 0x04U +#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09U + +#define USBD_IDX_LANGID_STR 0x00U +#define USBD_IDX_MFC_STR 0x01U +#define USBD_IDX_PRODUCT_STR 0x02U +#define USBD_IDX_SERIAL_STR 0x03U +#define USBD_IDX_CONFIG_STR 0x04U +#define USBD_IDX_INTERFACE_STR 0x05U + +#define USB_REQ_TYPE_STANDARD 0x00U +#define USB_REQ_TYPE_CLASS 0x20U +#define USB_REQ_TYPE_VENDOR 0x40U +#define USB_REQ_TYPE_MASK 0x60U + +#define USB_REQ_RECIPIENT_DEVICE 0x00U +#define USB_REQ_RECIPIENT_INTERFACE 0x01U +#define USB_REQ_RECIPIENT_ENDPOINT 0x02U +#define USB_REQ_RECIPIENT_MASK 0x03U + +#define USB_REQ_GET_STATUS 0x00U +#define USB_REQ_CLEAR_FEATURE 0x01U +#define USB_REQ_SET_FEATURE 0x03U +#define USB_REQ_SET_ADDRESS 0x05U +#define USB_REQ_GET_DESCRIPTOR 0x06U +#define USB_REQ_SET_DESCRIPTOR 0x07U +#define USB_REQ_GET_CONFIGURATION 0x08U +#define USB_REQ_SET_CONFIGURATION 0x09U +#define USB_REQ_GET_INTERFACE 0x0AU +#define USB_REQ_SET_INTERFACE 0x0BU +#define USB_REQ_SYNCH_FRAME 0x0CU + +#define USB_DESC_TYPE_DEVICE 0x01U +#define USB_DESC_TYPE_CONFIGURATION 0x02U +#define USB_DESC_TYPE_STRING 0x03U +#define USB_DESC_TYPE_INTERFACE 0x04U +#define USB_DESC_TYPE_ENDPOINT 0x05U +#define USB_DESC_TYPE_DEVICE_QUALIFIER 0x06U +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 0x07U +#define USB_DESC_TYPE_IAD 0x0BU +#define USB_DESC_TYPE_BOS 0x0FU + +#define USB_CONFIG_REMOTE_WAKEUP 0x02U +#define USB_CONFIG_SELF_POWERED 0x01U + +#define USB_FEATURE_EP_HALT 0x00U +#define USB_FEATURE_REMOTE_WAKEUP 0x01U +#define USB_FEATURE_TEST_MODE 0x02U + +#define USB_DEVICE_CAPABITY_TYPE 0x10U + +#define USB_CONF_DESC_SIZE 0x09U +#define USB_IF_DESC_SIZE 0x09U +#define USB_EP_DESC_SIZE 0x07U +#define USB_IAD_DESC_SIZE 0x08U + +#define USB_HS_MAX_PACKET_SIZE 512U +#define USB_FS_MAX_PACKET_SIZE 64U +#define USB_MAX_EP0_SIZE 64U + +/* Device Status */ +#define USBD_STATE_DEFAULT 0x01U +#define USBD_STATE_ADDRESSED 0x02U +#define USBD_STATE_CONFIGURED 0x03U +#define USBD_STATE_SUSPENDED 0x04U + + +/* EP0 State */ +#define USBD_EP0_IDLE 0x00U +#define USBD_EP0_SETUP 0x01U +#define USBD_EP0_DATA_IN 0x02U +#define USBD_EP0_DATA_OUT 0x03U +#define USBD_EP0_STATUS_IN 0x04U +#define USBD_EP0_STATUS_OUT 0x05U +#define USBD_EP0_STALL 0x06U + +#define USBD_EP_TYPE_CTRL 0x00U +#define USBD_EP_TYPE_ISOC 0x01U +#define USBD_EP_TYPE_BULK 0x02U +#define USBD_EP_TYPE_INTR 0x03U + +#ifdef USE_USBD_COMPOSITE +#define USBD_EP_IN 0x80U +#define USBD_EP_OUT 0x00U +#define USBD_FUNC_DESCRIPTOR_TYPE 0x24U +#define USBD_DESC_SUBTYPE_ACM 0x0FU +#define USBD_DESC_ECM_BCD_LOW 0x00U +#define USBD_DESC_ECM_BCD_HIGH 0x10U +#endif /* USE_USBD_COMPOSITE */ +/** + * @} + */ + + +/** @defgroup USBD_DEF_Exported_TypesDefinitions + * @{ + */ + +typedef struct usb_setup_req +{ + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USBD_SetupReqTypedef; + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} __PACKED USBD_ConfigDescTypeDef; + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumDeviceCaps; +} USBD_BosDescTypeDef; + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; +} __PACKED USBD_EpDescTypeDef; + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; +} USBD_DescHeaderTypeDef; + +struct _USBD_HandleTypeDef; + +typedef struct _Device_cb +{ + uint8_t (*Init)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx); + uint8_t (*DeInit)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx); + /* Control Endpoints*/ + uint8_t (*Setup)(struct _USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + uint8_t (*EP0_TxSent)(struct _USBD_HandleTypeDef *pdev); + uint8_t (*EP0_RxReady)(struct _USBD_HandleTypeDef *pdev); + /* Class Specific Endpoints*/ + uint8_t (*DataIn)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + uint8_t (*DataOut)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + uint8_t (*SOF)(struct _USBD_HandleTypeDef *pdev); + uint8_t (*IsoINIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + uint8_t (*IsoOUTIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + + uint8_t *(*GetHSConfigDescriptor)(uint16_t *length); + uint8_t *(*GetFSConfigDescriptor)(uint16_t *length); + uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length); + uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length); +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) + uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length); +#endif /* USBD_SUPPORT_USER_STRING_DESC */ + +} USBD_ClassTypeDef; + +/* Following USB Device Speed */ +typedef enum +{ + USBD_SPEED_HIGH = 0U, + USBD_SPEED_FULL = 1U, + USBD_SPEED_LOW = 2U, +} USBD_SpeedTypeDef; + +/* Following USB Device status */ +typedef enum +{ + USBD_OK = 0U, + USBD_BUSY, + USBD_EMEM, + USBD_FAIL, +} USBD_StatusTypeDef; + +/* USB Device descriptors structure */ +typedef struct +{ + uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); +#if (USBD_CLASS_USER_STRING_DESC == 1) + uint8_t *(*GetUserStrDescriptor)(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); +#endif /* USBD_CLASS_USER_STRING_DESC */ +#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1)) + uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); +#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1) */ +} USBD_DescriptorsTypeDef; + +/* USB Device handle structure */ +typedef struct +{ + uint32_t total_length; + uint32_t rem_length; + uint32_t bInterval; + uint16_t maxpacket; + uint8_t status; + uint8_t is_used; + uint8_t *pbuffer; +} USBD_EndpointTypeDef; + +#ifdef USE_USBD_COMPOSITE +typedef enum +{ + CLASS_TYPE_NONE = 0, + CLASS_TYPE_HID = 1, + CLASS_TYPE_CDC = 2, + CLASS_TYPE_MSC = 3, + CLASS_TYPE_DFU = 4, + CLASS_TYPE_CHID = 5, + CLASS_TYPE_AUDIO = 6, + CLASS_TYPE_ECM = 7, + CLASS_TYPE_RNDIS = 8, + CLASS_TYPE_MTP = 9, + CLASS_TYPE_VIDEO = 10, + CLASS_TYPE_PRINTER = 11, + CLASS_TYPE_CCID = 12, +} USBD_CompositeClassTypeDef; + + +/* USB Device handle structure */ +typedef struct +{ + uint8_t add; + uint8_t type; + uint8_t size; + uint8_t is_used; +} USBD_EPTypeDef; + +/* USB Device handle structure */ +typedef struct +{ + USBD_CompositeClassTypeDef ClassType; + uint32_t ClassId; + uint32_t Active; + uint32_t NumEps; + USBD_EPTypeDef Eps[USBD_MAX_CLASS_ENDPOINTS]; + uint8_t *EpAdd; + uint32_t NumIf; + uint8_t Ifs[USBD_MAX_CLASS_INTERFACES]; + uint32_t CurrPcktSze; +} USBD_CompositeElementTypeDef; +#endif /* USE_USBD_COMPOSITE */ + +/* USB Device handle structure */ +typedef struct _USBD_HandleTypeDef +{ + uint8_t id; + uint32_t dev_config; + uint32_t dev_default_config; + uint32_t dev_config_status; + USBD_SpeedTypeDef dev_speed; + USBD_EndpointTypeDef ep_in[16]; + USBD_EndpointTypeDef ep_out[16]; + __IO uint32_t ep0_state; + uint32_t ep0_data_len; + __IO uint8_t dev_state; + __IO uint8_t dev_old_state; + uint8_t dev_address; + uint8_t dev_connection_status; + uint8_t dev_test_mode; + uint32_t dev_remote_wakeup; + uint8_t ConfIdx; + + USBD_SetupReqTypedef request; + USBD_DescriptorsTypeDef *pDesc; + USBD_ClassTypeDef *pClass[USBD_MAX_SUPPORTED_CLASS]; + void *pClassData; + void *pClassDataCmsit[USBD_MAX_SUPPORTED_CLASS]; + void *pUserData[USBD_MAX_SUPPORTED_CLASS]; + void *pData; + void *pBosDesc; + void *pConfDesc; + uint32_t classId; + uint32_t NumClasses; +#ifdef USE_USBD_COMPOSITE + USBD_CompositeElementTypeDef tclasslist[USBD_MAX_SUPPORTED_CLASS]; +#endif /* USE_USBD_COMPOSITE */ +#if (USBD_USER_REGISTER_CALLBACK == 1U) + void (* DevStateCallback)(uint8_t dev_state, uint8_t cfgidx); /*!< User Notification callback */ +#endif /* USBD_USER_REGISTER_CALLBACK */ +} USBD_HandleTypeDef; + +#if (USBD_USER_REGISTER_CALLBACK == 1U) +typedef void (*USBD_DevStateCallbackTypeDef)(uint8_t dev_state, uint8_t cfgidx); /*!< pointer to User callback function */ +#endif /* USBD_USER_REGISTER_CALLBACK */ + +/* USB Device endpoint direction */ +typedef enum +{ + OUT = 0x00, + IN = 0x80, +} USBD_EPDirectionTypeDef; + +typedef enum +{ + NETWORK_CONNECTION = 0x00, + RESPONSE_AVAILABLE = 0x01, + CONNECTION_SPEED_CHANGE = 0x2A +} USBD_CDC_NotifCodeTypeDef; +/** + * @} + */ + + + +/** @defgroup USBD_DEF_Exported_Macros + * @{ + */ +__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) +{ + uint16_t _SwapVal; + uint16_t _Byte1; + uint16_t _Byte2; + uint8_t *_pbuff = addr; + + _Byte1 = *(uint8_t *)_pbuff; + _pbuff++; + _Byte2 = *(uint8_t *)_pbuff; + + _SwapVal = (_Byte2 << 8) | _Byte1; + + return _SwapVal; +} + +#ifndef LOBYTE +#define LOBYTE(x) ((uint8_t)((x) & 0x00FFU)) +#endif /* LOBYTE */ + +#ifndef HIBYTE +#define HIBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) +#endif /* HIBYTE */ + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif /* MIN */ + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif /* MAX */ + +#if defined ( __GNUC__ ) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + + +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4U))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#if defined (__CC_ARM) /* ARM Compiler */ +#define __ALIGN_BEGIN __align(4U) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_DEF_H */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h new file mode 100644 index 00000000..15197b92 --- /dev/null +++ b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h @@ -0,0 +1,113 @@ +/** + ****************************************************************************** + * @file usbd_ioreq.h + * @author MCD Application Team + * @brief Header file for the usbd_ioreq.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_IOREQ_H +#define __USBD_IOREQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" +#include "usbd_core.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_IOREQ + * @brief header file for the usbd_ioreq.c file + * @{ + */ + +/** @defgroup USBD_IOREQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Exported_Types + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_IOREQ_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); + +USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); + +USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); + +USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); + +USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev); + +uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_IOREQ_H */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c new file mode 100644 index 00000000..bcf571e5 --- /dev/null +++ b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c @@ -0,0 +1,1221 @@ +/** + ****************************************************************************** + * @file usbd_core.c + * @author MCD Application Team + * @brief This file provides all the USBD core functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" + +#ifdef USE_USBD_COMPOSITE +#include "usbd_composite_builder.h" +#endif /* USE_USBD_COMPOSITE */ + +/** @addtogroup STM32_USBD_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_CORE + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_CORE_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Private_Functions + * @{ + */ + +/** + * @brief USBD_Init + * Initialize the device stack and load the class driver + * @param pdev: device instance + * @param pdesc: Descriptor structure address + * @param id: Low level core index + * @retval status: USBD Status + */ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, + USBD_DescriptorsTypeDef *pdesc, uint8_t id) +{ + USBD_StatusTypeDef ret; + + /* Check whether the USB Host handle is valid */ + if (pdev == NULL) + { +#if (USBD_DEBUG_LEVEL > 1U) + USBD_ErrLog("Invalid Device handle"); +#endif /* (USBD_DEBUG_LEVEL > 1U) */ + return USBD_FAIL; + } + +#ifdef USE_USBD_COMPOSITE + /* Parse the table of classes in use */ + for (uint32_t i = 0; i < USBD_MAX_SUPPORTED_CLASS; i++) + { + /* Unlink previous class*/ + pdev->pClass[i] = NULL; + pdev->pUserData[i] = NULL; + + /* Set class as inactive */ + pdev->tclasslist[i].Active = 0; + pdev->NumClasses = 0; + pdev->classId = 0; + } +#else + /* Unlink previous class*/ + pdev->pClass[0] = NULL; + pdev->pUserData[0] = NULL; +#endif /* USE_USBD_COMPOSITE */ + + pdev->pConfDesc = NULL; + + /* Assign USBD Descriptors */ + if (pdesc != NULL) + { + pdev->pDesc = pdesc; + } + + /* Set Device initial State */ + pdev->dev_state = USBD_STATE_DEFAULT; + pdev->id = id; + + /* Initialize low level driver */ + ret = USBD_LL_Init(pdev); + + return ret; +} + +/** + * @brief USBD_DeInit + * De-Initialize the device library + * @param pdev: device instance + * @retval status: USBD Status + */ +USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) +{ + USBD_StatusTypeDef ret; + + /* Disconnect the USB Device */ + (void)USBD_LL_Stop(pdev); + + /* Set Default State */ + pdev->dev_state = USBD_STATE_DEFAULT; + +#ifdef USE_USBD_COMPOSITE + /* Parse the table of classes in use */ + for (uint32_t i = 0; i < USBD_MAX_SUPPORTED_CLASS; i++) + { + /* Check if current class is in use */ + if ((pdev->tclasslist[i].Active) == 1U) + { + if (pdev->pClass[i] != NULL) + { + pdev->classId = i; + /* Free Class Resources */ + pdev->pClass[i]->DeInit(pdev, (uint8_t)pdev->dev_config); + } + } + } +#else + /* Free Class Resources */ + if (pdev->pClass[0] != NULL) + { + pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config); + } + + pdev->pUserData[0] = NULL; + +#endif /* USE_USBD_COMPOSITE */ + + /* Free Device descriptors resources */ + pdev->pDesc = NULL; + pdev->pConfDesc = NULL; + + /* DeInitialize low level driver */ + ret = USBD_LL_DeInit(pdev); + + return ret; +} + +/** + * @brief USBD_RegisterClass + * Link class driver to Device Core. + * @param pdev: Device Handle + * @param pclass: Class handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) +{ + uint16_t len = 0U; + + if (pclass == NULL) + { +#if (USBD_DEBUG_LEVEL > 1U) + USBD_ErrLog("Invalid Class handle"); +#endif /* (USBD_DEBUG_LEVEL > 1U) */ + return USBD_FAIL; + } + + /* link the class to the USB Device handle */ + pdev->pClass[0] = pclass; + + /* Get Device Configuration Descriptor */ +#ifdef USE_USB_HS + if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) + { + pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); + } +#else /* Default USE_USB_FS */ + if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) + { + pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); + } +#endif /* USE_USB_FS */ + + /* Increment the NumClasses */ + pdev->NumClasses++; + + return USBD_OK; +} + +#ifdef USE_USBD_COMPOSITE +/** + * @brief USBD_RegisterClassComposite + * Link class driver to Device Core. + * @param pdev : Device Handle + * @param pclass: Class handle + * @param classtype: Class type + * @param EpAddr: Endpoint Address handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_RegisterClassComposite(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass, + USBD_CompositeClassTypeDef classtype, uint8_t *EpAddr) +{ + USBD_StatusTypeDef ret = USBD_OK; + uint16_t len = 0U; + + if ((pdev->classId < USBD_MAX_SUPPORTED_CLASS) && (pdev->NumClasses < USBD_MAX_SUPPORTED_CLASS)) + { + if ((uint32_t)pclass != 0U) + { + /* Link the class to the USB Device handle */ + pdev->pClass[pdev->classId] = pclass; + ret = USBD_OK; + + pdev->tclasslist[pdev->classId].EpAdd = EpAddr; + + /* Call the composite class builder */ + (void)USBD_CMPSIT_AddClass(pdev, pclass, classtype, 0); + + /* Increment the ClassId for the next occurrence */ + pdev->classId ++; + pdev->NumClasses ++; + } + else + { +#if (USBD_DEBUG_LEVEL > 1U) + USBD_ErrLog("Invalid Class handle"); +#endif /* (USBD_DEBUG_LEVEL > 1U) */ + ret = USBD_FAIL; + } + } + + if (ret == USBD_OK) + { + /* Get Device Configuration Descriptor */ +#ifdef USE_USB_HS + pdev->pConfDesc = USBD_CMPSIT.GetHSConfigDescriptor(&len); +#else /* Default USE_USB_FS */ + pdev->pConfDesc = USBD_CMPSIT.GetFSConfigDescriptor(&len); +#endif /* USE_USB_FS */ + } + + return ret; +} + +/** + * @brief USBD_UnRegisterClassComposite + * UnLink all composite class drivers from Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_UnRegisterClassComposite(USBD_HandleTypeDef *pdev) +{ + USBD_StatusTypeDef ret = USBD_OK; + uint8_t idx1; + uint8_t idx2; + + /* Unroll all activated classes */ + for (idx1 = 0; idx1 < pdev->NumClasses; idx1++) + { + /* Check if the class correspond to the requested type and if it is active */ + if (pdev->tclasslist[idx1].Active == 1U) + { + /* Set the new class ID */ + pdev->classId = idx1; + + /* Free resources used by the selected class */ + if (pdev->pClass[pdev->classId] != NULL) + { + /* Free Class Resources */ + if (pdev->pClass[pdev->classId]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) + { +#if (USBD_DEBUG_LEVEL > 1U) + USBD_ErrLog("Class DeInit didn't succeed!, can't unregister selected class"); +#endif /* (USBD_DEBUG_LEVEL > 1U) */ + + ret = USBD_FAIL; + } + } + + /* Free the class pointer */ + pdev->pClass[pdev->classId] = NULL; + + /* Free the class location in classes table and reset its parameters to zero */ + pdev->tclasslist[pdev->classId].ClassType = CLASS_TYPE_NONE; + pdev->tclasslist[pdev->classId].ClassId = 0U; + pdev->tclasslist[pdev->classId].Active = 0U; + pdev->tclasslist[pdev->classId].NumEps = 0U; + pdev->tclasslist[pdev->classId].NumIf = 0U; + pdev->tclasslist[pdev->classId].CurrPcktSze = 0U; + + for (idx2 = 0U; idx2 < USBD_MAX_CLASS_ENDPOINTS; idx2++) + { + pdev->tclasslist[pdev->classId].Eps[idx2].add = 0U; + pdev->tclasslist[pdev->classId].Eps[idx2].type = 0U; + pdev->tclasslist[pdev->classId].Eps[idx2].size = 0U; + pdev->tclasslist[pdev->classId].Eps[idx2].is_used = 0U; + } + + for (idx2 = 0U; idx2 < USBD_MAX_CLASS_INTERFACES; idx2++) + { + pdev->tclasslist[pdev->classId].Ifs[idx2] = 0U; + } + } + } + + /* Reset the configuration descriptor */ + (void)USBD_CMPST_ClearConfDesc(pdev); + + /* Reset the class ID and number of classes */ + pdev->classId = 0U; + pdev->NumClasses = 0U; + + return ret; +} +#endif /* USE_USBD_COMPOSITE */ + +#if (USBD_USER_REGISTER_CALLBACK == 1U) +/** + * @brief USBD_RegisterDevStateCallback + * @param pdev : Device Handle + * @param pUserCallback: User Callback + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_RegisterDevStateCallback(USBD_HandleTypeDef *pdev, USBD_DevStateCallbackTypeDef pUserCallback) +{ + pdev->DevStateCallback = pUserCallback; + + return USBD_OK; +} +#endif /* USBD_USER_REGISTER_CALLBACK */ + +/** + * @brief USBD_Start + * Start the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) +{ +#ifdef USE_USBD_COMPOSITE + pdev->classId = 0U; +#endif /* USE_USBD_COMPOSITE */ + + /* Start the low level driver */ + return USBD_LL_Start(pdev); +} + +/** + * @brief USBD_Stop + * Stop the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev) +{ + /* Disconnect USB Device */ + (void)USBD_LL_Stop(pdev); + + /* Free Class Resources */ +#ifdef USE_USBD_COMPOSITE + /* Parse the table of classes in use */ + for (uint32_t i = 0U; i < USBD_MAX_SUPPORTED_CLASS; i++) + { + /* Check if current class is in use */ + if ((pdev->tclasslist[i].Active) == 1U) + { + if (pdev->pClass[i] != NULL) + { + pdev->classId = i; + /* Free Class Resources */ + (void)pdev->pClass[i]->DeInit(pdev, (uint8_t)pdev->dev_config); + } + } + } + + /* Reset the class ID */ + pdev->classId = 0U; +#else + if (pdev->pClass[0] != NULL) + { + (void)pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config); + } +#endif /* USE_USBD_COMPOSITE */ + + return USBD_OK; +} + +/** + * @brief USBD_RunTestMode + * Launch test mode process + * @param pdev: device instance + * @retval status + */ +USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) +{ +#ifdef USBD_HS_TESTMODE_ENABLE + USBD_StatusTypeDef ret; + + /* Run USB HS test mode */ + ret = USBD_LL_SetTestMode(pdev, pdev->dev_test_mode); + + return ret; +#else + /* Prevent unused argument compilation warning */ + UNUSED(pdev); + + return USBD_OK; +#endif /* USBD_HS_TESTMODE_ENABLE */ +} + +/** + * @brief USBD_SetClassConfig + * Configure device and start the interface + * @param pdev: device instance + * @param cfgidx: configuration index + * @retval status + */ + +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + USBD_StatusTypeDef ret = USBD_OK; + +#ifdef USE_USBD_COMPOSITE + /* Parse the table of classes in use */ + for (uint32_t i = 0U; i < USBD_MAX_SUPPORTED_CLASS; i++) + { + /* Check if current class is in use */ + if ((pdev->tclasslist[i].Active) == 1U) + { + if (pdev->pClass[i] != NULL) + { + pdev->classId = i; + /* Set configuration and Start the Class*/ + if (pdev->pClass[i]->Init(pdev, cfgidx) != 0U) + { + ret = USBD_FAIL; + } + } + } + } +#else + if (pdev->pClass[0] != NULL) + { + /* Set configuration and Start the Class */ + ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); + } +#endif /* USE_USBD_COMPOSITE */ + + return ret; +} + +/** + * @brief USBD_ClrClassConfig + * Clear current configuration + * @param pdev: device instance + * @param cfgidx: configuration index + * @retval status + */ +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + USBD_StatusTypeDef ret = USBD_OK; + +#ifdef USE_USBD_COMPOSITE + /* Parse the table of classes in use */ + for (uint32_t i = 0U; i < USBD_MAX_SUPPORTED_CLASS; i++) + { + /* Check if current class is in use */ + if ((pdev->tclasslist[i].Active) == 1U) + { + if (pdev->pClass[i] != NULL) + { + pdev->classId = i; + /* Clear configuration and De-initialize the Class process */ + if (pdev->pClass[i]->DeInit(pdev, cfgidx) != 0U) + { + ret = USBD_FAIL; + } + } + } + } +#else + /* Clear configuration and De-initialize the Class process */ + if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) + { + ret = USBD_FAIL; + } +#endif /* USE_USBD_COMPOSITE */ + + return ret; +} + + +/** + * @brief USBD_LL_SetupStage + * Handle the setup stage + * @param pdev: device instance + * @param psetup: setup packet buffer pointer + * @retval status + */ +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) +{ + USBD_StatusTypeDef ret; + + USBD_ParseSetupRequest(&pdev->request, psetup); + + pdev->ep0_state = USBD_EP0_SETUP; + + pdev->ep0_data_len = pdev->request.wLength; + + switch (pdev->request.bmRequest & 0x1FU) + { + case USB_REQ_RECIPIENT_DEVICE: + ret = USBD_StdDevReq(pdev, &pdev->request); + break; + + case USB_REQ_RECIPIENT_INTERFACE: + ret = USBD_StdItfReq(pdev, &pdev->request); + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + ret = USBD_StdEPReq(pdev, &pdev->request); + break; + + default: + ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); + break; + } + + return ret; +} + +/** + * @brief USBD_LL_DataOutStage + * Handle data OUT stage + * @param pdev: device instance + * @param epnum: endpoint index + * @param pdata: data pointer + * @retval status + */ +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, + uint8_t epnum, uint8_t *pdata) +{ + USBD_EndpointTypeDef *pep; + USBD_StatusTypeDef ret = USBD_OK; + uint8_t idx; + + UNUSED(pdata); + + if (epnum == 0U) + { + pep = &pdev->ep_out[0]; + + if (pdev->ep0_state == USBD_EP0_DATA_OUT) + { + if (pep->rem_length > pep->maxpacket) + { + pep->rem_length -= pep->maxpacket; + pep->pbuffer += pep->maxpacket; + + (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); + } + else + { + /* Find the class ID relative to the current request */ + switch (pdev->request.bmRequest & 0x1FU) + { + case USB_REQ_RECIPIENT_DEVICE: + /* Device requests must be managed by the first instantiated class + (or duplicated by all classes for simplicity) */ + idx = 0U; + break; + + case USB_REQ_RECIPIENT_INTERFACE: + idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); + break; + + default: + /* Back to the first class in case of doubt */ + idx = 0U; + break; + } + + if (idx < USBD_MAX_SUPPORTED_CLASS) + { + /* Setup the class ID and route the request to the relative class function */ + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + if (pdev->pClass[idx]->EP0_RxReady != NULL) + { + pdev->classId = idx; + pdev->pClass[idx]->EP0_RxReady(pdev); + } + } + } + + (void)USBD_CtlSendStatus(pdev); + } + } + } + else + { + /* Get the class index relative to this interface */ + idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); + + if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) + { + /* Call the class data out function to manage the request */ + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + if (pdev->pClass[idx]->DataOut != NULL) + { + pdev->classId = idx; + ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); + } + } + if (ret != USBD_OK) + { + return ret; + } + } + } + + return USBD_OK; +} + +/** + * @brief USBD_LL_DataInStage + * Handle data in stage + * @param pdev: device instance + * @param epnum: endpoint index + * @param pdata: data pointer + * @retval status + */ +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, + uint8_t epnum, uint8_t *pdata) +{ + USBD_EndpointTypeDef *pep; + USBD_StatusTypeDef ret; + uint8_t idx; + + UNUSED(pdata); + + if (epnum == 0U) + { + pep = &pdev->ep_in[0]; + + if (pdev->ep0_state == USBD_EP0_DATA_IN) + { + if (pep->rem_length > pep->maxpacket) + { + pep->rem_length -= pep->maxpacket; + pep->pbuffer += pep->maxpacket; + + (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); + + /* Prepare endpoint for premature end of transfer */ + (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + } + else + { + /* last packet is MPS multiple, so send ZLP packet */ + if ((pep->maxpacket == pep->rem_length) && + (pep->total_length >= pep->maxpacket) && + (pep->total_length < pdev->ep0_data_len)) + { + (void)USBD_CtlContinueSendData(pdev, NULL, 0U); + pdev->ep0_data_len = 0U; + + /* Prepare endpoint for premature end of transfer */ + (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + } + else + { + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + if (pdev->pClass[0]->EP0_TxSent != NULL) + { + pdev->classId = 0U; + pdev->pClass[0]->EP0_TxSent(pdev); + } + } + (void)USBD_LL_StallEP(pdev, 0x80U); + (void)USBD_CtlReceiveStatus(pdev); + } + } + } + + if (pdev->dev_test_mode != 0U) + { + (void)USBD_RunTestMode(pdev); + pdev->dev_test_mode = 0U; + } + } + else + { + /* Get the class index relative to this interface */ + idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); + + if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) + { + /* Call the class data out function to manage the request */ + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + if (pdev->pClass[idx]->DataIn != NULL) + { + pdev->classId = idx; + ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); + + if (ret != USBD_OK) + { + return ret; + } + } + } + } + } + + return USBD_OK; +} + +/** + * @brief USBD_LL_Reset + * Handle Reset event + * @param pdev: device instance + * @retval status + */ +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) +{ + USBD_StatusTypeDef ret = USBD_OK; + + /* Upon Reset call user call back */ + pdev->dev_state = USBD_STATE_DEFAULT; + pdev->ep0_state = USBD_EP0_IDLE; + pdev->dev_config = 0U; + pdev->dev_remote_wakeup = 0U; + pdev->dev_test_mode = 0U; + +#ifdef USE_USBD_COMPOSITE + /* Parse the table of classes in use */ + for (uint32_t i = 0U; i < USBD_MAX_SUPPORTED_CLASS; i++) + { + /* Check if current class is in use */ + if ((pdev->tclasslist[i].Active) == 1U) + { + if (pdev->pClass[i] != NULL) + { + pdev->classId = i; + /* Clear configuration and De-initialize the Class process*/ + + if (pdev->pClass[i]->DeInit != NULL) + { + if (pdev->pClass[i]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) + { + ret = USBD_FAIL; + } + } + } + } + } +#else + + if (pdev->pClass[0] != NULL) + { + if (pdev->pClass[0]->DeInit != NULL) + { + if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) + { + ret = USBD_FAIL; + } + } + } +#endif /* USE_USBD_COMPOSITE */ + + /* Open EP0 OUT */ + (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + pdev->ep_out[0x00U & 0xFU].is_used = 1U; + + pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; + + /* Open EP0 IN */ + (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + pdev->ep_in[0x80U & 0xFU].is_used = 1U; + + pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; + + return ret; +} + +/** + * @brief USBD_LL_SetSpeed + * Handle Reset event + * @param pdev: device instance + * @retval status + */ +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, + USBD_SpeedTypeDef speed) +{ + pdev->dev_speed = speed; + + return USBD_OK; +} + +/** + * @brief USBD_LL_Suspend + * Handle Suspend event + * @param pdev: device instance + * @retval status + */ +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) +{ + if (pdev->dev_state != USBD_STATE_SUSPENDED) + { + pdev->dev_old_state = pdev->dev_state; + } + + pdev->dev_state = USBD_STATE_SUSPENDED; + + return USBD_OK; +} + +/** + * @brief USBD_LL_Resume + * Handle Resume event + * @param pdev: device instance + * @retval status + */ +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) +{ + if (pdev->dev_state == USBD_STATE_SUSPENDED) + { + pdev->dev_state = pdev->dev_old_state; + } + + return USBD_OK; +} + +/** + * @brief USBD_LL_SOF + * Handle SOF event + * @param pdev: device instance + * @retval status + */ +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) +{ + /* The SOF event can be distributed for all classes that support it */ + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { +#ifdef USE_USBD_COMPOSITE + /* Parse the table of classes in use */ + for (uint32_t i = 0; i < USBD_MAX_SUPPORTED_CLASS; i++) + { + /* Check if current class is in use */ + if ((pdev->tclasslist[i].Active) == 1U) + { + if (pdev->pClass[i] != NULL) + { + if (pdev->pClass[i]->SOF != NULL) + { + pdev->classId = i; + (void)pdev->pClass[i]->SOF(pdev); + } + } + } + } +#else + if (pdev->pClass[0] != NULL) + { + if (pdev->pClass[0]->SOF != NULL) + { + (void)pdev->pClass[0]->SOF(pdev); + } + } +#endif /* USE_USBD_COMPOSITE */ + } + + return USBD_OK; +} + +/** + * @brief USBD_LL_IsoINIncomplete + * Handle iso in incomplete event + * @param pdev: device instance + * @param epnum: Endpoint number + * @retval status + */ +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, + uint8_t epnum) +{ + if (pdev->pClass[pdev->classId] == NULL) + { + return USBD_FAIL; + } + + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL) + { + (void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum); + } + } + + return USBD_OK; +} + +/** + * @brief USBD_LL_IsoOUTIncomplete + * Handle iso out incomplete event + * @param pdev: device instance + * @param epnum: Endpoint number + * @retval status + */ +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, + uint8_t epnum) +{ + if (pdev->pClass[pdev->classId] == NULL) + { + return USBD_FAIL; + } + + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL) + { + (void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum); + } + } + + return USBD_OK; +} + +/** + * @brief USBD_LL_DevConnected + * Handle device connection event + * @param pdev: device instance + * @retval status + */ +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) +{ + /* Prevent unused argument compilation warning */ + UNUSED(pdev); + + return USBD_OK; +} + +/** + * @brief USBD_LL_DevDisconnected + * Handle device disconnection event + * @param pdev: device instance + * @retval status + */ +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) +{ + USBD_StatusTypeDef ret = USBD_OK; + + /* Free Class Resources */ + pdev->dev_state = USBD_STATE_DEFAULT; + +#ifdef USE_USBD_COMPOSITE + /* Parse the table of classes in use */ + for (uint32_t i = 0; i < USBD_MAX_SUPPORTED_CLASS; i++) + { + /* Check if current class is in use */ + if ((pdev->tclasslist[i].Active) == 1U) + { + if (pdev->pClass[i] != NULL) + { + pdev->classId = i; + /* Clear configuration and De-initialize the Class process*/ + if (pdev->pClass[i]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) + { + ret = USBD_FAIL; + } + } + } + } +#else + if (pdev->pClass[0] != NULL) + { + if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) + { + ret = USBD_FAIL; + } + } +#endif /* USE_USBD_COMPOSITE */ + + return ret; +} + +/** + * @brief USBD_CoreFindIF + * return the class index relative to the selected interface + * @param pdev: device instance + * @param index : selected interface number + * @retval index of the class using the selected interface number. OxFF if no class found. + */ +uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) +{ +#ifdef USE_USBD_COMPOSITE + /* Parse the table of classes in use */ + for (uint32_t i = 0U; i < USBD_MAX_SUPPORTED_CLASS; i++) + { + /* Check if current class is in use */ + if ((pdev->tclasslist[i].Active) == 1U) + { + /* Parse all interfaces listed in the current class */ + for (uint32_t j = 0U; j < pdev->tclasslist[i].NumIf; j++) + { + /* Check if requested Interface matches the current class interface */ + if (pdev->tclasslist[i].Ifs[j] == index) + { + if (pdev->pClass[i]->Setup != NULL) + { + return (uint8_t)i; + } + } + } + } + } + + return 0xFFU; +#else + UNUSED(pdev); + UNUSED(index); + + return 0x00U; +#endif /* USE_USBD_COMPOSITE */ +} + +/** + * @brief USBD_CoreFindEP + * return the class index relative to the selected endpoint + * @param pdev: device instance + * @param index : selected endpoint number + * @retval index of the class using the selected endpoint number. 0xFF if no class found. + */ +uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) +{ +#ifdef USE_USBD_COMPOSITE + /* Parse the table of classes in use */ + for (uint32_t i = 0U; i < USBD_MAX_SUPPORTED_CLASS; i++) + { + /* Check if current class is in use */ + if ((pdev->tclasslist[i].Active) == 1U) + { + /* Parse all endpoints listed in the current class */ + for (uint32_t j = 0U; j < pdev->tclasslist[i].NumEps; j++) + { + /* Check if requested endpoint matches the current class endpoint */ + if (pdev->tclasslist[i].Eps[j].add == index) + { + if (pdev->pClass[i]->Setup != NULL) + { + return (uint8_t)i; + } + } + } + } + } + + return 0xFFU; +#else + UNUSED(pdev); + UNUSED(index); + + return 0x00U; +#endif /* USE_USBD_COMPOSITE */ +} + +#ifdef USE_USBD_COMPOSITE +/** + * @brief USBD_CoreGetEPAdd + * Get the endpoint address relative to a selected class + * @param pdev: device instance + * @param ep_dir: USBD_EP_IN or USBD_EP_OUT + * @param ep_type: USBD_EP_TYPE_CTRL, USBD_EP_TYPE_ISOC, USBD_EP_TYPE_BULK or USBD_EP_TYPE_INTR + * @param ClassId: The Class ID + * @retval Address of the selected endpoint or 0xFFU if no endpoint found. + */ +uint8_t USBD_CoreGetEPAdd(USBD_HandleTypeDef *pdev, uint8_t ep_dir, uint8_t ep_type, uint8_t ClassId) +{ + uint8_t idx; + + /* Find the EP address in the selected class table */ + for (idx = 0; idx < pdev->tclasslist[ClassId].NumEps; idx++) + { + if (((pdev->tclasslist[ClassId].Eps[idx].add & USBD_EP_IN) == ep_dir) && \ + (pdev->tclasslist[ClassId].Eps[idx].type == ep_type) && \ + (pdev->tclasslist[ClassId].Eps[idx].is_used != 0U)) + { + return (pdev->tclasslist[ClassId].Eps[idx].add); + } + } + + /* If reaching this point, then no endpoint was found */ + return 0xFFU; +} +#endif /* USE_USBD_COMPOSITE */ + +/** + * @brief USBD_GetEpDesc + * This function return the Endpoint descriptor + * @param pdev: device instance + * @param pConfDesc: pointer to Bos descriptor + * @param EpAddr: endpoint address + * @retval pointer to video endpoint descriptor + */ +void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) +{ + USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; + USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; + USBD_EpDescTypeDef *pEpDesc = NULL; + uint16_t ptr; + + if (desc->wTotalLength > desc->bLength) + { + ptr = desc->bLength; + + while (ptr < desc->wTotalLength) + { + pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); + + if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) + { + pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; + + if (pEpDesc->bEndpointAddress == EpAddr) + { + break; + } + else + { + pEpDesc = NULL; + } + } + } + } + + return (void *)pEpDesc; +} + +/** + * @brief USBD_GetNextDesc + * This function return the next descriptor header + * @param buf: Buffer where the descriptor is available + * @param ptr: data pointer inside the descriptor + * @retval next header + */ +USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) +{ + USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; + + *ptr += pnext->bLength; + pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); + + return (pnext); +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + diff --git a/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c new file mode 100644 index 00000000..814b810c --- /dev/null +++ b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c @@ -0,0 +1,1058 @@ +/** + ****************************************************************************** + * @file usbd_req.c + * @author MCD Application Team + * @brief This file provides the standard USB requests following chapter 9. + ****************************************************************************** + * @attention + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ctlreq.h" +#include "usbd_ioreq.h" + +#ifdef USE_USBD_COMPOSITE +#include "usbd_composite_builder.h" +#endif /* USE_USBD_COMPOSITE */ + +/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_REQ + * @brief USB standard requests module + * @{ + */ + +/** @defgroup USBD_REQ_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Defines + * @{ + */ +#ifndef USBD_MAX_STR_DESC_SIZ +#define USBD_MAX_STR_DESC_SIZ 64U +#endif /* USBD_MAX_STR_DESC_SIZ */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_FunctionPrototypes + * @{ + */ +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_GetLen(uint8_t *buf); + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Functions + * @{ + */ + + +/** + * @brief USBD_StdDevReq + * Handle standard usb device requests + * @param pdev: device instance + * @param req: usb request + * @retval status + */ +USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_StatusTypeDef ret = USBD_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + USBD_GetDescriptor(pdev, req); + break; + + case USB_REQ_SET_ADDRESS: + USBD_SetAddress(pdev, req); + break; + + case USB_REQ_SET_CONFIGURATION: + ret = USBD_SetConfig(pdev, req); + break; + + case USB_REQ_GET_CONFIGURATION: + USBD_GetConfig(pdev, req); + break; + + case USB_REQ_GET_STATUS: + USBD_GetStatus(pdev, req); + break; + + case USB_REQ_SET_FEATURE: + USBD_SetFeature(pdev, req); + break; + + case USB_REQ_CLEAR_FEATURE: + USBD_ClrFeature(pdev, req); + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + + return ret; +} + +/** + * @brief USBD_StdItfReq + * Handle standard usb interface requests + * @param pdev: device instance + * @param req: usb request + * @retval status + */ +USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_StatusTypeDef ret = USBD_OK; + uint8_t idx; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + case USB_REQ_TYPE_STANDARD: + switch (pdev->dev_state) + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + + if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) + { + /* Get the class index relative to this interface */ + idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); + if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) + { + /* Call the class data out function to manage the request */ + if (pdev->pClass[idx]->Setup != NULL) + { + pdev->classId = idx; + ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); + } + else + { + /* should never reach this condition */ + ret = USBD_FAIL; + } + } + else + { + /* No relative interface found */ + ret = USBD_FAIL; + } + + if ((req->wLength == 0U) && (ret == USBD_OK)) + { + (void)USBD_CtlSendStatus(pdev); + } + } + else + { + USBD_CtlError(pdev, req); + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + + return ret; +} + +/** + * @brief USBD_StdEPReq + * Handle standard usb endpoint requests + * @param pdev: device instance + * @param req: usb request + * @retval status + */ +USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_EndpointTypeDef *pep; + uint8_t ep_addr; + uint8_t idx; + USBD_StatusTypeDef ret = USBD_OK; + + ep_addr = LOBYTE(req->wIndex); + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + /* Get the class index relative to this endpoint */ + idx = USBD_CoreFindEP(pdev, ep_addr); + if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) + { + pdev->classId = idx; + /* Call the class data out function to manage the request */ + if (pdev->pClass[idx]->Setup != NULL) + { + ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); + } + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_SET_FEATURE: + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { + (void)USBD_LL_StallEP(pdev, ep_addr); + (void)USBD_LL_StallEP(pdev, 0x80U); + } + else + { + USBD_CtlError(pdev, req); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) + { + (void)USBD_LL_StallEP(pdev, ep_addr); + } + } + (void)USBD_CtlSendStatus(pdev); + + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + case USB_REQ_CLEAR_FEATURE: + + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { + (void)USBD_LL_StallEP(pdev, ep_addr); + (void)USBD_LL_StallEP(pdev, 0x80U); + } + else + { + USBD_CtlError(pdev, req); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr & 0x7FU) != 0x00U) + { + (void)USBD_LL_ClearStallEP(pdev, ep_addr); + } + (void)USBD_CtlSendStatus(pdev); + + /* Get the class index relative to this interface */ + idx = USBD_CoreFindEP(pdev, ep_addr); + if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) + { + pdev->classId = idx; + /* Call the class data out function to manage the request */ + if (pdev->pClass[idx]->Setup != NULL) + { + ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); + } + } + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + case USB_REQ_GET_STATUS: + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { + USBD_CtlError(pdev, req); + break; + } + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + &pdev->ep_out[ep_addr & 0x7FU]; + + pep->status = 0x0000U; + + (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); + break; + + case USBD_STATE_CONFIGURED: + if ((ep_addr & 0x80U) == 0x80U) + { + if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) + { + USBD_CtlError(pdev, req); + break; + } + } + else + { + if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) + { + USBD_CtlError(pdev, req); + break; + } + } + + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + &pdev->ep_out[ep_addr & 0x7FU]; + + if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) + { + pep->status = 0x0000U; + } + else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) + { + pep->status = 0x0001U; + } + else + { + pep->status = 0x0000U; + } + + (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + + return ret; +} + + +/** + * @brief USBD_GetDescriptor + * Handle Get Descriptor requests + * @param pdev: device instance + * @param req: usb request + * @retval None + */ +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + uint16_t len = 0U; + uint8_t *pbuf = NULL; + uint8_t err = 0U; + + switch (req->wValue >> 8) + { +#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) + case USB_DESC_TYPE_BOS: + if (pdev->pDesc->GetBOSDescriptor != NULL) + { + pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; +#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); + break; + + case USB_DESC_TYPE_CONFIGURATION: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { +#ifdef USE_USBD_COMPOSITE + if ((uint8_t)(pdev->NumClasses) > 0U) + { + pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); + } + else +#endif /* USE_USBD_COMPOSITE */ + { + pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); + } + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + else + { +#ifdef USE_USBD_COMPOSITE + if ((uint8_t)(pdev->NumClasses) > 0U) + { + pbuf = (uint8_t *)USBD_CMPSIT.GetFSConfigDescriptor(&len); + } + else +#endif /* USE_USBD_COMPOSITE */ + { + pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); + } + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + break; + + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) + { + case USBD_IDX_LANGID_STR: + if (pdev->pDesc->GetLangIDStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_MFC_STR: + if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_PRODUCT_STR: + if (pdev->pDesc->GetProductStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_SERIAL_STR: + if (pdev->pDesc->GetSerialStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_CONFIG_STR: + if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_INTERFACE_STR: + if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + default: +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) + pbuf = NULL; + + for (uint32_t idx = 0U; (idx < pdev->NumClasses); idx++) + { + if (pdev->pClass[idx]->GetUsrStrDescriptor != NULL) + { + pdev->classId = idx; + pbuf = pdev->pClass[idx]->GetUsrStrDescriptor(pdev, LOBYTE(req->wValue), &len); + + if (pbuf == NULL) /* This means that no class recognized the string index */ + { + continue; + } + else + { + break; + } + } + } +#endif /* USBD_SUPPORT_USER_STRING_DESC */ + +#if (USBD_CLASS_USER_STRING_DESC == 1U) + if (pdev->pDesc->GetUserStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetUserStrDescriptor(pdev->dev_speed, LOBYTE(req->wValue), &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } +#endif /* USBD_SUPPORT_USER_STRING_DESC */ + +#if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) + USBD_CtlError(pdev, req); + err++; +#endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ + break; + } + break; + + case USB_DESC_TYPE_DEVICE_QUALIFIER: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { +#ifdef USE_USBD_COMPOSITE + if ((uint8_t)(pdev->NumClasses) > 0U) + { + pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); + } + else +#endif /* USE_USBD_COMPOSITE */ + { + pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); + } + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { +#ifdef USE_USBD_COMPOSITE + if ((uint8_t)(pdev->NumClasses) > 0U) + { + pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); + } + else +#endif /* USE_USBD_COMPOSITE */ + { + pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); + } + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + default: + USBD_CtlError(pdev, req); + err++; + break; + } + + if (err != 0U) + { + return; + } + + if (req->wLength != 0U) + { + if (len != 0U) + { + len = MIN(len, req->wLength); + (void)USBD_CtlSendData(pdev, pbuf, len); + } + else + { + USBD_CtlError(pdev, req); + } + } + else + { + (void)USBD_CtlSendStatus(pdev); + } +} + + +/** + * @brief USBD_SetAddress + * Set device address + * @param pdev: device instance + * @param req: usb request + * @retval None + */ +static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + uint8_t dev_addr; + + if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) + { + dev_addr = (uint8_t)(req->wValue) & 0x7FU; + + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + USBD_CtlError(pdev, req); + } + else + { + pdev->dev_address = dev_addr; + (void)USBD_LL_SetUSBAddress(pdev, dev_addr); + (void)USBD_CtlSendStatus(pdev); + + if (dev_addr != 0U) + { + pdev->dev_state = USBD_STATE_ADDRESSED; + } + else + { + pdev->dev_state = USBD_STATE_DEFAULT; + } + } + } + else + { + USBD_CtlError(pdev, req); + } +} + +/** + * @brief USBD_SetConfig + * Handle Set device configuration request + * @param pdev: device instance + * @param req: usb request + * @retval status + */ +static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_StatusTypeDef ret = USBD_OK; + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + + if (cfgidx > USBD_MAX_NUM_CONFIGURATION) + { + USBD_CtlError(pdev, req); + return USBD_FAIL; + } + + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if (cfgidx != 0U) + { + pdev->dev_config = cfgidx; + + ret = USBD_SetClassConfig(pdev, cfgidx); + + if (ret != USBD_OK) + { + USBD_CtlError(pdev, req); + pdev->dev_state = USBD_STATE_ADDRESSED; + } + else + { + (void)USBD_CtlSendStatus(pdev); + pdev->dev_state = USBD_STATE_CONFIGURED; + +#if (USBD_USER_REGISTER_CALLBACK == 1U) + if (pdev->DevStateCallback != NULL) + { + pdev->DevStateCallback(USBD_STATE_CONFIGURED, cfgidx); + } +#endif /* USBD_USER_REGISTER_CALLBACK */ + } + } + else + { + (void)USBD_CtlSendStatus(pdev); + } + break; + + case USBD_STATE_CONFIGURED: + if (cfgidx == 0U) + { + pdev->dev_state = USBD_STATE_ADDRESSED; + pdev->dev_config = cfgidx; + (void)USBD_ClrClassConfig(pdev, cfgidx); + (void)USBD_CtlSendStatus(pdev); + } + else if (cfgidx != pdev->dev_config) + { + /* Clear old configuration */ + (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + + /* set new configuration */ + pdev->dev_config = cfgidx; + + ret = USBD_SetClassConfig(pdev, cfgidx); + + if (ret != USBD_OK) + { + USBD_CtlError(pdev, req); + (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + pdev->dev_state = USBD_STATE_ADDRESSED; + } + else + { + (void)USBD_CtlSendStatus(pdev); + } + } + else + { + (void)USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev, req); + (void)USBD_ClrClassConfig(pdev, cfgidx); + ret = USBD_FAIL; + break; + } + + return ret; +} + +/** + * @brief USBD_GetConfig + * Handle Get device configuration request + * @param pdev: device instance + * @param req: usb request + * @retval None + */ +static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + if (req->wLength != 1U) + { + USBD_CtlError(pdev, req); + } + else + { + switch (pdev->dev_state) + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + pdev->dev_default_config = 0U; + (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); + break; + + case USBD_STATE_CONFIGURED: + (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); + break; + + default: + USBD_CtlError(pdev, req); + break; + } + } +} + +/** + * @brief USBD_GetStatus + * Handle Get Status request + * @param pdev: device instance + * @param req: usb request + * @retval None + */ +static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + switch (pdev->dev_state) + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + if (req->wLength != 0x2U) + { + USBD_CtlError(pdev, req); + break; + } + +#if (USBD_SELF_POWERED == 1U) + pdev->dev_config_status = USB_CONFIG_SELF_POWERED; +#else + pdev->dev_config_status = 0U; +#endif /* USBD_SELF_POWERED */ + + if (pdev->dev_remote_wakeup != 0U) + { + pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; + } + + (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); + break; + + default: + USBD_CtlError(pdev, req); + break; + } +} + + +/** + * @brief USBD_SetFeature + * Handle Set device feature request + * @param pdev: device instance + * @param req: usb request + * @retval None + */ +static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + pdev->dev_remote_wakeup = 1U; + (void)USBD_CtlSendStatus(pdev); + } + else if (req->wValue == USB_FEATURE_TEST_MODE) + { + pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); + (void)USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlError(pdev, req); + } +} + + +/** + * @brief USBD_ClrFeature + * Handle clear device feature request + * @param pdev: device instance + * @param req: usb request + * @retval None + */ +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + switch (pdev->dev_state) + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + pdev->dev_remote_wakeup = 0U; + (void)USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } +} + + +/** + * @brief USBD_ParseSetupRequest + * Copy buffer into setup structure + * @param req: usb request + * @param pdata: setup data pointer + * @retval None + */ +void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) +{ + uint8_t *pbuff = pdata; + + req->bmRequest = *(uint8_t *)(pbuff); + + pbuff++; + req->bRequest = *(uint8_t *)(pbuff); + + pbuff++; + req->wValue = SWAPBYTE(pbuff); + + pbuff++; + pbuff++; + req->wIndex = SWAPBYTE(pbuff); + + pbuff++; + pbuff++; + req->wLength = SWAPBYTE(pbuff); +} + + +/** + * @brief USBD_CtlError + * Handle USB low level Error + * @param pdev: device instance + * @param req: usb request + * @retval None + */ +void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + UNUSED(req); + + (void)USBD_LL_StallEP(pdev, 0x80U); + (void)USBD_LL_StallEP(pdev, 0U); +} + + +/** + * @brief USBD_GetString + * Convert Ascii string into unicode one + * @param desc : descriptor buffer + * @param unicode : Formatted string buffer (unicode) + * @param len : descriptor length + * @retval None + */ +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) +{ + uint8_t idx = 0U; + uint8_t *pdesc; + + if (desc == NULL) + { + return; + } + + pdesc = desc; + *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); + + unicode[idx] = *(uint8_t *)len; + idx++; + unicode[idx] = USB_DESC_TYPE_STRING; + idx++; + + while (*pdesc != (uint8_t)'\0') + { + unicode[idx] = *pdesc; + pdesc++; + idx++; + + unicode[idx] = 0U; + idx++; + } +} + + +/** + * @brief USBD_GetLen + * return the string length + * @param buf : pointer to the ascii string buffer + * @retval string length + */ +static uint8_t USBD_GetLen(uint8_t *buf) +{ + uint8_t len = 0U; + uint8_t *pbuff = buf; + + while (*pbuff != (uint8_t)'\0') + { + len++; + pbuff++; + } + + return len; +} +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + diff --git a/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c new file mode 100644 index 00000000..2171398b --- /dev/null +++ b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file usbd_ioreq.c + * @author MCD Application Team + * @brief This file provides the IO requests APIs for control endpoints. + ****************************************************************************** + * @attention + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_IOREQ + * @brief control I/O requests module + * @{ + */ + +/** @defgroup USBD_IOREQ_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Functions + * @{ + */ + +/** + * @brief USBD_CtlSendData + * send data on the ctl pipe + * @param pdev: device instance + * @param buff: pointer to data buffer + * @param len: length of data to be sent + * @retval status + */ +USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_IN; + pdev->ep_in[0].total_length = len; + pdev->ep_in[0].pbuffer = pbuf; + +#ifdef USBD_AVOID_PACKET_SPLIT_MPS + pdev->ep_in[0].rem_length = 0U; +#else + pdev->ep_in[0].rem_length = len; +#endif /* USBD_AVOID_PACKET_SPLIT_MPS */ + + /* Start the transfer */ + (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + + return USBD_OK; +} + +/** + * @brief USBD_CtlContinueSendData + * continue sending data on the ctl pipe + * @param pdev: device instance + * @param buff: pointer to data buffer + * @param len: length of data to be sent + * @retval status + */ +USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len) +{ + /* Start the next transfer */ + (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + + return USBD_OK; +} + +/** + * @brief USBD_CtlPrepareRx + * receive data on the ctl pipe + * @param pdev: device instance + * @param buff: pointer to data buffer + * @param len: length of data to be received + * @retval status + */ +USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_OUT; + pdev->ep_out[0].total_length = len; + pdev->ep_out[0].pbuffer = pbuf; + +#ifdef USBD_AVOID_PACKET_SPLIT_MPS + pdev->ep_out[0].rem_length = 0U; +#else + pdev->ep_out[0].rem_length = len; +#endif /* USBD_AVOID_PACKET_SPLIT_MPS */ + + /* Start the transfer */ + (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + + return USBD_OK; +} + +/** + * @brief USBD_CtlContinueRx + * continue receive data on the ctl pipe + * @param pdev: device instance + * @param buff: pointer to data buffer + * @param len: length of data to be received + * @retval status + */ +USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len) +{ + (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + + return USBD_OK; +} + +/** + * @brief USBD_CtlSendStatus + * send zero lzngth packet on the ctl pipe + * @param pdev: device instance + * @retval status + */ +USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_IN; + + /* Start the transfer */ + (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); + + return USBD_OK; +} + +/** + * @brief USBD_CtlReceiveStatus + * receive zero lzngth packet on the ctl pipe + * @param pdev: device instance + * @retval status + */ +USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_OUT; + + /* Start the transfer */ + (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + + return USBD_OK; +} + +/** + * @brief USBD_GetRxCount + * returns the received data length + * @param pdev: device instance + * @param ep_addr: endpoint address + * @retval Rx Data blength + */ +uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return USBD_LL_GetRxDataSize(pdev, ep_addr); +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + diff --git a/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/LICENSE.txt b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/LICENSE.txt new file mode 100644 index 00000000..e66295c5 --- /dev/null +++ b/firmware/numpad/Middlewares/ST/STM32_USB_Device_Library/LICENSE.txt @@ -0,0 +1,86 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the SLA0044 license shall apply and are fully reproduced below: + +SLA0044 Rev5/February 2018 + +Software license agreement + +ULTIMATE LIBERTY SOFTWARE LICENSE AGREEMENT + +BY INSTALLING, COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE +OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS +INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES +(STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON +BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES +TO BE BOUND BY THIS SOFTWARE LICENSE AGREEMENT. + +Under STMicroelectronics’ intellectual property rights, the redistribution, +reproduction and use in source and binary forms of the software or any part +thereof, with or without modification, are permitted provided that the following +conditions are met: + +1. Redistribution of source code (modified or not) must retain any copyright +notice, this list of conditions and the disclaimer set forth below as items 10 +and 11. + +2. Redistributions in binary form, except as embedded into microcontroller or +microprocessor device manufactured by or for STMicroelectronics or a software +update for such device, must reproduce any copyright notice provided with the +binary code, this list of conditions, and the disclaimer set forth below as +items 10 and 11, in documentation and/or other materials provided with the +distribution. + +3. Neither the name of STMicroelectronics nor the names of other contributors to +this software may be used to endorse or promote products derived from this +software or part thereof without specific written permission. + +4. This software or any part thereof, including modifications and/or derivative +works of this software, must be used and execute solely and exclusively on or in +combination with a microcontroller or microprocessor device manufactured by or +for STMicroelectronics. + +5. No use, reproduction or redistribution of this software partially or totally +may be done in any manner that would subject this software to any Open Source +Terms. “Open Source Terms” shall mean any open source license which requires as +part of distribution of software that the source code of such software is +distributed therewith or otherwise made available, or open source license that +substantially complies with the Open Source definition specified at +www.opensource.org and any other comparable open source license such as for +example GNU General Public License (GPL), Eclipse Public License (EPL), Apache +Software License, BSD license or MIT license. + +6. STMicroelectronics has no obligation to provide any maintenance, support or +updates for the software. + +7. The software is and will remain the exclusive property of STMicroelectronics +and its licensors. The recipient will not take any action that jeopardizes +STMicroelectronics and its licensors' proprietary rights or acquire any rights +in the software, except the limited rights specified hereunder. + +8. The recipient shall comply with all applicable laws and regulations affecting +the use of the software or any part thereof including any applicable export +control law or regulation. + +9. Redistribution and use of this software or any part thereof other than as +permitted under this license is void and will automatically terminate your +rights under this license. + +10. THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS, WHICH ARE +DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL +STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +11. EXCEPT AS EXPRESSLY PERMITTED HEREUNDER, NO LICENSE OR OTHER RIGHTS, WHETHER +EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY +RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY. + diff --git a/firmware/numpad/Release/Core/Src/main.cyclo b/firmware/numpad/Release/Core/Src/main.cyclo new file mode 100644 index 00000000..ec333fe5 --- /dev/null +++ b/firmware/numpad/Release/Core/Src/main.cyclo @@ -0,0 +1,3 @@ +../Core/Src/main.c:152:6:SystemClock_Config 3 +../Core/Src/main.c:94:5:main 1 +../Core/Src/main.c:556:6:Error_Handler 1 diff --git a/firmware/numpad/Release/Core/Src/main.d b/firmware/numpad/Release/Core/Src/main.d new file mode 100644 index 00000000..efa445e4 --- /dev/null +++ b/firmware/numpad/Release/Core/Src/main.d @@ -0,0 +1,86 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../USB_DEVICE/App/usb_device.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../USB_DEVICE/App/usb_device.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/firmware/numpad/Release/Core/Src/main.o b/firmware/numpad/Release/Core/Src/main.o new file mode 100644 index 00000000..b0b06b52 Binary files /dev/null and b/firmware/numpad/Release/Core/Src/main.o differ diff --git a/firmware/numpad/Release/Core/Src/main.su b/firmware/numpad/Release/Core/Src/main.su new file mode 100644 index 00000000..57c69fef --- /dev/null +++ b/firmware/numpad/Release/Core/Src/main.su @@ -0,0 +1,3 @@ +../Core/Src/main.c:152:6:SystemClock_Config 88 static,ignoring_inline_asm +../Core/Src/main.c:94:5:main 48 static +../Core/Src/main.c:556:6:Error_Handler 0 static,ignoring_inline_asm diff --git a/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.cyclo b/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.cyclo new file mode 100644 index 00000000..f8c22f1d --- /dev/null +++ b/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.cyclo @@ -0,0 +1,10 @@ +../Core/Src/stm32f4xx_hal_msp.c:65:6:HAL_MspInit 1 +../Core/Src/stm32f4xx_hal_msp.c:88:6:HAL_I2C_MspInit 2 +../Core/Src/stm32f4xx_hal_msp.c:125:6:HAL_I2C_MspDeInit 2 +../Core/Src/stm32f4xx_hal_msp.c:156:6:HAL_TIM_OC_MspInit 2 +../Core/Src/stm32f4xx_hal_msp.c:179:6:HAL_TIM_Encoder_MspInit 2 +../Core/Src/stm32f4xx_hal_msp.c:210:6:HAL_TIM_MspPostInit 2 +../Core/Src/stm32f4xx_hal_msp.c:242:6:HAL_TIM_OC_MspDeInit 2 +../Core/Src/stm32f4xx_hal_msp.c:264:6:HAL_TIM_Encoder_MspDeInit 2 +../Core/Src/stm32f4xx_hal_msp.c:293:6:HAL_UART_MspInit 6 +../Core/Src/stm32f4xx_hal_msp.c:433:6:HAL_UART_MspDeInit 6 diff --git a/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.d b/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.d new file mode 100644 index 00000000..4b18fd24 --- /dev/null +++ b/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.d @@ -0,0 +1,68 @@ +Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.o b/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.o new file mode 100644 index 00000000..f42ce8a9 Binary files /dev/null and b/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.o differ diff --git a/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.su b/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.su new file mode 100644 index 00000000..56e830cc --- /dev/null +++ b/firmware/numpad/Release/Core/Src/stm32f4xx_hal_msp.su @@ -0,0 +1,10 @@ +../Core/Src/stm32f4xx_hal_msp.c:65:6:HAL_MspInit 8 static +../Core/Src/stm32f4xx_hal_msp.c:88:6:HAL_I2C_MspInit 48 static +../Core/Src/stm32f4xx_hal_msp.c:125:6:HAL_I2C_MspDeInit 8 static +../Core/Src/stm32f4xx_hal_msp.c:156:6:HAL_TIM_OC_MspInit 8 static +../Core/Src/stm32f4xx_hal_msp.c:179:6:HAL_TIM_Encoder_MspInit 40 static +../Core/Src/stm32f4xx_hal_msp.c:210:6:HAL_TIM_MspPostInit 32 static +../Core/Src/stm32f4xx_hal_msp.c:242:6:HAL_TIM_OC_MspDeInit 0 static +../Core/Src/stm32f4xx_hal_msp.c:264:6:HAL_TIM_Encoder_MspDeInit 0 static +../Core/Src/stm32f4xx_hal_msp.c:293:6:HAL_UART_MspInit 88 static +../Core/Src/stm32f4xx_hal_msp.c:433:6:HAL_UART_MspDeInit 8 static diff --git a/firmware/numpad/Release/Core/Src/stm32f4xx_it.cyclo b/firmware/numpad/Release/Core/Src/stm32f4xx_it.cyclo new file mode 100644 index 00000000..104167e1 --- /dev/null +++ b/firmware/numpad/Release/Core/Src/stm32f4xx_it.cyclo @@ -0,0 +1,10 @@ +../Core/Src/stm32f4xx_it.c:69:6:NMI_Handler 1 +../Core/Src/stm32f4xx_it.c:84:6:HardFault_Handler 1 +../Core/Src/stm32f4xx_it.c:99:6:MemManage_Handler 1 +../Core/Src/stm32f4xx_it.c:114:6:BusFault_Handler 1 +../Core/Src/stm32f4xx_it.c:129:6:UsageFault_Handler 1 +../Core/Src/stm32f4xx_it.c:144:6:SVC_Handler 1 +../Core/Src/stm32f4xx_it.c:157:6:DebugMon_Handler 1 +../Core/Src/stm32f4xx_it.c:170:6:PendSV_Handler 1 +../Core/Src/stm32f4xx_it.c:183:6:SysTick_Handler 1 +../Core/Src/stm32f4xx_it.c:204:6:OTG_FS_IRQHandler 1 diff --git a/firmware/numpad/Release/Core/Src/stm32f4xx_it.d b/firmware/numpad/Release/Core/Src/stm32f4xx_it.d new file mode 100644 index 00000000..37eb467d --- /dev/null +++ b/firmware/numpad/Release/Core/Src/stm32f4xx_it.d @@ -0,0 +1,70 @@ +Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Core/Inc/stm32f4xx_it.h +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Core/Inc/stm32f4xx_it.h: diff --git a/firmware/numpad/Release/Core/Src/stm32f4xx_it.o b/firmware/numpad/Release/Core/Src/stm32f4xx_it.o new file mode 100644 index 00000000..1ae4528b Binary files /dev/null and b/firmware/numpad/Release/Core/Src/stm32f4xx_it.o differ diff --git a/firmware/numpad/Release/Core/Src/stm32f4xx_it.su b/firmware/numpad/Release/Core/Src/stm32f4xx_it.su new file mode 100644 index 00000000..cbe9e53e --- /dev/null +++ b/firmware/numpad/Release/Core/Src/stm32f4xx_it.su @@ -0,0 +1,10 @@ +../Core/Src/stm32f4xx_it.c:69:6:NMI_Handler 0 static +../Core/Src/stm32f4xx_it.c:84:6:HardFault_Handler 0 static +../Core/Src/stm32f4xx_it.c:99:6:MemManage_Handler 0 static +../Core/Src/stm32f4xx_it.c:114:6:BusFault_Handler 0 static +../Core/Src/stm32f4xx_it.c:129:6:UsageFault_Handler 0 static +../Core/Src/stm32f4xx_it.c:144:6:SVC_Handler 0 static +../Core/Src/stm32f4xx_it.c:157:6:DebugMon_Handler 0 static +../Core/Src/stm32f4xx_it.c:170:6:PendSV_Handler 0 static +../Core/Src/stm32f4xx_it.c:183:6:SysTick_Handler 0 static +../Core/Src/stm32f4xx_it.c:204:6:OTG_FS_IRQHandler 0 static diff --git a/firmware/numpad/Release/Core/Src/subdir.mk b/firmware/numpad/Release/Core/Src/subdir.mk new file mode 100644 index 00000000..7ceeab9e --- /dev/null +++ b/firmware/numpad/Release/Core/Src/subdir.mk @@ -0,0 +1,42 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/main.c \ +../Core/Src/stm32f4xx_hal_msp.c \ +../Core/Src/stm32f4xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f4xx.c + +OBJS += \ +./Core/Src/main.o \ +./Core/Src/stm32f4xx_hal_msp.o \ +./Core/Src/stm32f4xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f4xx.o + +C_DEPS += \ +./Core/Src/main.d \ +./Core/Src/stm32f4xx_hal_msp.d \ +./Core/Src/stm32f4xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f4xx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Core-2f-Src + +clean-Core-2f-Src: + -$(RM) ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32f4xx_hal_msp.cyclo ./Core/Src/stm32f4xx_hal_msp.d ./Core/Src/stm32f4xx_hal_msp.o ./Core/Src/stm32f4xx_hal_msp.su ./Core/Src/stm32f4xx_it.cyclo ./Core/Src/stm32f4xx_it.d ./Core/Src/stm32f4xx_it.o ./Core/Src/stm32f4xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f4xx.cyclo ./Core/Src/system_stm32f4xx.d ./Core/Src/system_stm32f4xx.o ./Core/Src/system_stm32f4xx.su + +.PHONY: clean-Core-2f-Src + diff --git a/firmware/numpad/Release/Core/Src/syscalls.cyclo b/firmware/numpad/Release/Core/Src/syscalls.cyclo new file mode 100644 index 00000000..6cbfdd05 --- /dev/null +++ b/firmware/numpad/Release/Core/Src/syscalls.cyclo @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1 +../Core/Src/syscalls.c:48:5:_getpid 1 +../Core/Src/syscalls.c:53:5:_kill 1 +../Core/Src/syscalls.c:61:6:_exit 1 +../Core/Src/syscalls.c:67:27:_read 2 +../Core/Src/syscalls.c:80:27:_write 2 +../Core/Src/syscalls.c:92:5:_close 1 +../Core/Src/syscalls.c:99:5:_fstat 1 +../Core/Src/syscalls.c:106:5:_isatty 1 +../Core/Src/syscalls.c:112:5:_lseek 1 +../Core/Src/syscalls.c:120:5:_open 1 +../Core/Src/syscalls.c:128:5:_wait 1 +../Core/Src/syscalls.c:135:5:_unlink 1 +../Core/Src/syscalls.c:142:5:_times 1 +../Core/Src/syscalls.c:148:5:_stat 1 +../Core/Src/syscalls.c:155:5:_link 1 +../Core/Src/syscalls.c:163:5:_fork 1 +../Core/Src/syscalls.c:169:5:_execve 1 diff --git a/firmware/numpad/Release/Core/Src/syscalls.d b/firmware/numpad/Release/Core/Src/syscalls.d new file mode 100644 index 00000000..8667c708 --- /dev/null +++ b/firmware/numpad/Release/Core/Src/syscalls.d @@ -0,0 +1 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c diff --git a/firmware/numpad/Release/Core/Src/syscalls.o b/firmware/numpad/Release/Core/Src/syscalls.o new file mode 100644 index 00000000..eaf673c8 Binary files /dev/null and b/firmware/numpad/Release/Core/Src/syscalls.o differ diff --git a/firmware/numpad/Release/Core/Src/syscalls.su b/firmware/numpad/Release/Core/Src/syscalls.su new file mode 100644 index 00000000..268646b2 --- /dev/null +++ b/firmware/numpad/Release/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 0 static +../Core/Src/syscalls.c:48:5:_getpid 0 static +../Core/Src/syscalls.c:53:5:_kill 8 static +../Core/Src/syscalls.c:61:6:_exit 8 static +../Core/Src/syscalls.c:67:27:_read 16 static +../Core/Src/syscalls.c:80:27:_write 16 static +../Core/Src/syscalls.c:92:5:_close 0 static +../Core/Src/syscalls.c:99:5:_fstat 0 static +../Core/Src/syscalls.c:106:5:_isatty 0 static +../Core/Src/syscalls.c:112:5:_lseek 0 static +../Core/Src/syscalls.c:120:5:_open 0 static +../Core/Src/syscalls.c:128:5:_wait 8 static +../Core/Src/syscalls.c:135:5:_unlink 8 static +../Core/Src/syscalls.c:142:5:_times 0 static +../Core/Src/syscalls.c:148:5:_stat 0 static +../Core/Src/syscalls.c:155:5:_link 8 static +../Core/Src/syscalls.c:163:5:_fork 8 static +../Core/Src/syscalls.c:169:5:_execve 8 static diff --git a/firmware/numpad/Release/Core/Src/sysmem.cyclo b/firmware/numpad/Release/Core/Src/sysmem.cyclo new file mode 100644 index 00000000..0090c10f --- /dev/null +++ b/firmware/numpad/Release/Core/Src/sysmem.cyclo @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 3 diff --git a/firmware/numpad/Release/Core/Src/sysmem.d b/firmware/numpad/Release/Core/Src/sysmem.d new file mode 100644 index 00000000..74fecf9b --- /dev/null +++ b/firmware/numpad/Release/Core/Src/sysmem.d @@ -0,0 +1 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c diff --git a/firmware/numpad/Release/Core/Src/sysmem.o b/firmware/numpad/Release/Core/Src/sysmem.o new file mode 100644 index 00000000..a0542ca4 Binary files /dev/null and b/firmware/numpad/Release/Core/Src/sysmem.o differ diff --git a/firmware/numpad/Release/Core/Src/sysmem.su b/firmware/numpad/Release/Core/Src/sysmem.su new file mode 100644 index 00000000..43d062a7 --- /dev/null +++ b/firmware/numpad/Release/Core/Src/sysmem.su @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 8 static diff --git a/firmware/numpad/Release/Core/Src/system_stm32f4xx.cyclo b/firmware/numpad/Release/Core/Src/system_stm32f4xx.cyclo new file mode 100644 index 00000000..8e385a80 --- /dev/null +++ b/firmware/numpad/Release/Core/Src/system_stm32f4xx.cyclo @@ -0,0 +1,2 @@ +../Core/Src/system_stm32f4xx.c:167:6:SystemInit 1 +../Core/Src/system_stm32f4xx.c:220:6:SystemCoreClockUpdate 4 diff --git a/firmware/numpad/Release/Core/Src/system_stm32f4xx.d b/firmware/numpad/Release/Core/Src/system_stm32f4xx.d new file mode 100644 index 00000000..8e525e44 --- /dev/null +++ b/firmware/numpad/Release/Core/Src/system_stm32f4xx.d @@ -0,0 +1,67 @@ +Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Core/Src/system_stm32f4xx.o b/firmware/numpad/Release/Core/Src/system_stm32f4xx.o new file mode 100644 index 00000000..efcec98f Binary files /dev/null and b/firmware/numpad/Release/Core/Src/system_stm32f4xx.o differ diff --git a/firmware/numpad/Release/Core/Src/system_stm32f4xx.su b/firmware/numpad/Release/Core/Src/system_stm32f4xx.su new file mode 100644 index 00000000..f786683e --- /dev/null +++ b/firmware/numpad/Release/Core/Src/system_stm32f4xx.su @@ -0,0 +1,2 @@ +../Core/Src/system_stm32f4xx.c:167:6:SystemInit 0 static +../Core/Src/system_stm32f4xx.c:220:6:SystemCoreClockUpdate 0 static diff --git a/firmware/numpad/Release/Core/Startup/startup_stm32f446retx.d b/firmware/numpad/Release/Core/Startup/startup_stm32f446retx.d new file mode 100644 index 00000000..168e9e87 --- /dev/null +++ b/firmware/numpad/Release/Core/Startup/startup_stm32f446retx.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32f446retx.o: \ + ../Core/Startup/startup_stm32f446retx.s diff --git a/firmware/numpad/Release/Core/Startup/startup_stm32f446retx.o b/firmware/numpad/Release/Core/Startup/startup_stm32f446retx.o new file mode 100644 index 00000000..9b847dcb Binary files /dev/null and b/firmware/numpad/Release/Core/Startup/startup_stm32f446retx.o differ diff --git a/firmware/numpad/Release/Core/Startup/subdir.mk b/firmware/numpad/Release/Core/Startup/subdir.mk new file mode 100644 index 00000000..e5fe2425 --- /dev/null +++ b/firmware/numpad/Release/Core/Startup/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f446retx.s + +OBJS += \ +./Core/Startup/startup_stm32f446retx.o + +S_DEPS += \ +./Core/Startup/startup_stm32f446retx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" + +clean: clean-Core-2f-Startup + +clean-Core-2f-Startup: + -$(RM) ./Core/Startup/startup_stm32f446retx.d ./Core/Startup/startup_stm32f446retx.o + +.PHONY: clean-Core-2f-Startup + diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo new file mode 100644 index 00000000..97c4624f --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo @@ -0,0 +1,27 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:219:13:HAL_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:230:13:HAL_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:190:19:HAL_DeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:253:26:HAL_InitTick 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:157:19:HAL_Init 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:312:13:HAL_IncTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323:17:HAL_GetTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:332:10:HAL_GetTickPrio 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:341:19:HAL_SetTickFreq 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:374:21:HAL_GetTickFreq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:390:13:HAL_Delay 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:416:13:HAL_SuspendTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:432:13:HAL_ResumeTick 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:442:10:HAL_GetHalVersion 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:451:10:HAL_GetREVID 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:460:10:HAL_GetDEVID 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:469:6:HAL_DBGMCU_EnableDBGSleepMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:478:6:HAL_DBGMCU_DisableDBGSleepMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:487:6:HAL_DBGMCU_EnableDBGStopMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:496:6:HAL_DBGMCU_DisableDBGStopMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:505:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:514:6:HAL_DBGMCU_DisableDBGStandbyMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:525:6:HAL_EnableCompensationCell 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:536:6:HAL_DisableCompensationCell 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:545:10:HAL_GetUIDw0 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:554:10:HAL_GetUIDw1 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:563:10:HAL_GetUIDw2 1 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d new file mode 100644 index 00000000..4c8c5b86 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o new file mode 100644 index 00000000..cc542f8c Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su new file mode 100644 index 00000000..c420924a --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su @@ -0,0 +1,27 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:219:13:HAL_MspInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:230:13:HAL_MspDeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:190:19:HAL_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:253:26:HAL_InitTick 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:157:19:HAL_Init 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:312:13:HAL_IncTick 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323:17:HAL_GetTick 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:332:10:HAL_GetTickPrio 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:341:19:HAL_SetTickFreq 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:374:21:HAL_GetTickFreq 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:390:13:HAL_Delay 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:416:13:HAL_SuspendTick 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:432:13:HAL_ResumeTick 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:442:10:HAL_GetHalVersion 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:451:10:HAL_GetREVID 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:460:10:HAL_GetDEVID 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:469:6:HAL_DBGMCU_EnableDBGSleepMode 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:478:6:HAL_DBGMCU_DisableDBGSleepMode 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:487:6:HAL_DBGMCU_EnableDBGStopMode 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:496:6:HAL_DBGMCU_DisableDBGStopMode 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:505:6:HAL_DBGMCU_EnableDBGStandbyMode 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:514:6:HAL_DBGMCU_DisableDBGStandbyMode 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:525:6:HAL_EnableCompensationCell 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:536:6:HAL_DisableCompensationCell 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:545:10:HAL_GetUIDw0 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:554:10:HAL_GetUIDw1 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:563:10:HAL_GetUIDw2 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo new file mode 100644 index 00000000..2a621aa4 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo @@ -0,0 +1,21 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:141:6:HAL_NVIC_SetPriorityGrouping 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:163:6:HAL_NVIC_SetPriority 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:185:6:HAL_NVIC_EnableIRQ 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:201:6:HAL_NVIC_DisableIRQ 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:214:6:HAL_NVIC_SystemReset 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:227:10:HAL_SYSTICK_Config 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:256:6:HAL_MPU_Disable 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:279:6:HAL_MPU_Enable 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:296:6:HAL_MPU_EnableRegion 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:312:6:HAL_MPU_DisableRegion 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:330:6:HAL_MPU_ConfigRegion 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:368:6:HAL_CORTEX_ClearEvent 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:378:10:HAL_NVIC_GetPriorityGrouping 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:405:6:HAL_NVIC_GetPriority 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:420:6:HAL_NVIC_SetPendingIRQ 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:438:10:HAL_NVIC_GetPendingIRQ 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:454:6:HAL_NVIC_ClearPendingIRQ 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:471:10:HAL_NVIC_GetActive 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:488:6:HAL_SYSTICK_CLKSourceConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:515:13:HAL_SYSTICK_Callback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:506:6:HAL_SYSTICK_IRQHandler 1 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d new file mode 100644 index 00000000..93b84ece --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o new file mode 100644 index 00000000..df5fb8cd Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su new file mode 100644 index 00000000..fd031510 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su @@ -0,0 +1,21 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:141:6:HAL_NVIC_SetPriorityGrouping 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:163:6:HAL_NVIC_SetPriority 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:185:6:HAL_NVIC_EnableIRQ 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:201:6:HAL_NVIC_DisableIRQ 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:214:6:HAL_NVIC_SystemReset 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:227:10:HAL_SYSTICK_Config 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:256:6:HAL_MPU_Disable 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:279:6:HAL_MPU_Enable 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:296:6:HAL_MPU_EnableRegion 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:312:6:HAL_MPU_DisableRegion 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:330:6:HAL_MPU_ConfigRegion 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:368:6:HAL_CORTEX_ClearEvent 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:378:10:HAL_NVIC_GetPriorityGrouping 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:405:6:HAL_NVIC_GetPriority 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:420:6:HAL_NVIC_SetPendingIRQ 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:438:10:HAL_NVIC_GetPendingIRQ 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:454:6:HAL_NVIC_ClearPendingIRQ 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:471:10:HAL_NVIC_GetActive 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:488:6:HAL_SYSTICK_CLKSourceConfig 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:515:13:HAL_SYSTICK_Callback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:506:6:HAL_SYSTICK_IRQHandler 8 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo new file mode 100644 index 00000000..1f6a706b --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo @@ -0,0 +1,13 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1185:17:DMA_CalcBaseAndBitshift 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:170:19:HAL_DMA_Init 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:309:19:HAL_DMA_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:407:19:HAL_DMA_Start 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:451:19:HAL_DMA_Start_IT 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:513:19:HAL_DMA_Abort 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:580:19:HAL_DMA_Abort_IT 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:610:19:HAL_DMA_PollForTransfer 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:746:6:HAL_DMA_IRQHandler 32 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:967:19:HAL_DMA_RegisterCallback 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1029:19:HAL_DMA_UnRegisterCallback 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1114:22:HAL_DMA_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1125:10:HAL_DMA_GetError 1 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d new file mode 100644 index 00000000..44fd2965 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o new file mode 100644 index 00000000..a89935c9 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su new file mode 100644 index 00000000..05740a8b --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su @@ -0,0 +1,13 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1185:17:DMA_CalcBaseAndBitshift 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:170:19:HAL_DMA_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:309:19:HAL_DMA_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:407:19:HAL_DMA_Start 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:451:19:HAL_DMA_Start_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:513:19:HAL_DMA_Abort 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:580:19:HAL_DMA_Abort_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:610:19:HAL_DMA_PollForTransfer 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:746:6:HAL_DMA_IRQHandler 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:967:19:HAL_DMA_RegisterCallback 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1029:19:HAL_DMA_UnRegisterCallback 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1114:22:HAL_DMA_GetState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1125:10:HAL_DMA_GetError 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo new file mode 100644 index 00000000..937046c8 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo @@ -0,0 +1,3 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:100:19:HAL_DMAEx_MultiBufferStart 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:154:19:HAL_DMAEx_MultiBufferStart_IT 25 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:239:19:HAL_DMAEx_ChangeMemory 2 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d new file mode 100644 index 00000000..a5b9ab6f --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o new file mode 100644 index 00000000..7024be02 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su new file mode 100644 index 00000000..d872f0ff --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su @@ -0,0 +1,3 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:100:19:HAL_DMAEx_MultiBufferStart 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:154:19:HAL_DMAEx_MultiBufferStart_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:239:19:HAL_DMAEx_ChangeMemory 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo new file mode 100644 index 00000000..a472e146 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:466:10:HAL_EXTI_GetPending 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:498:6:HAL_EXTI_ClearPending 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:522:6:HAL_EXTI_GenerateSWI 1 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d new file mode 100644 index 00000000..387a44c6 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o new file mode 100644 index 00000000..80d456c8 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su new file mode 100644 index 00000000..fb571f7d --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su @@ -0,0 +1,9 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:466:10:HAL_EXTI_GetPending 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:498:6:HAL_EXTI_ClearPending 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:522:6:HAL_EXTI_GenerateSWI 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo new file mode 100644 index 00000000..5b3d56cf --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo @@ -0,0 +1,16 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:611:13:FLASH_Program_DoubleWord 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:645:13:FLASH_Program_Word 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:670:13:FLASH_Program_HalfWord 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:712:13:FLASH_SetErrorCode 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:219:19:HAL_FLASH_Program_IT 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:383:13:HAL_FLASH_EndOfOperationCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:400:13:HAL_FLASH_OperationErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:263:6:HAL_FLASH_IRQHandler 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:432:19:HAL_FLASH_Unlock 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:456:19:HAL_FLASH_Lock 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:468:19:HAL_FLASH_OB_Unlock 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:488:19:HAL_FLASH_OB_Lock 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:537:10:HAL_FLASH_GetError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:551:19:FLASH_WaitForLastOperation 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:161:19:HAL_FLASH_Program 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:500:19:HAL_FLASH_OB_Launch 1 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d new file mode 100644 index 00000000..bc34265a --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o new file mode 100644 index 00000000..cbe96ac4 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su new file mode 100644 index 00000000..1234c815 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su @@ -0,0 +1,16 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:611:13:FLASH_Program_DoubleWord 8 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:645:13:FLASH_Program_Word 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:670:13:FLASH_Program_HalfWord 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:712:13:FLASH_SetErrorCode 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:219:19:HAL_FLASH_Program_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:383:13:HAL_FLASH_EndOfOperationCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:400:13:HAL_FLASH_OperationErrorCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:263:6:HAL_FLASH_IRQHandler 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:432:19:HAL_FLASH_Unlock 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:456:19:HAL_FLASH_Lock 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:468:19:HAL_FLASH_OB_Unlock 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:488:19:HAL_FLASH_OB_Lock 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:537:10:HAL_FLASH_GetError 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:551:19:FLASH_WaitForLastOperation 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:161:19:HAL_FLASH_Program 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:500:19:HAL_FLASH_OB_Launch 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo new file mode 100644 index 00000000..8d4a9cfb --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo @@ -0,0 +1,11 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:948:13:FLASH_MassErase.isra 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:281:19:HAL_FLASHEx_OBProgram 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:340:6:HAL_FLASHEx_OBGetConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:369:19:HAL_FLASHEx_AdvOBProgram 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:425:6:HAL_FLASHEx_AdvOBGetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:457:19:HAL_FLASHEx_OB_SelectPCROP 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:482:19:HAL_FLASHEx_OB_DeSelectPCROP 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:977:6:FLASH_Erase_Sector 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:231:19:HAL_FLASHEx_Erase_IT 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1306:6:FLASH_FlushCaches 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:160:19:HAL_FLASHEx_Erase 6 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d new file mode 100644 index 00000000..db1c6529 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o new file mode 100644 index 00000000..5fd97714 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su new file mode 100644 index 00000000..f63139ee --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su @@ -0,0 +1,11 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:948:13:FLASH_MassErase.isra 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:281:19:HAL_FLASHEx_OBProgram 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:340:6:HAL_FLASHEx_OBGetConfig 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:369:19:HAL_FLASHEx_AdvOBProgram 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:425:6:HAL_FLASHEx_AdvOBGetConfig 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:457:19:HAL_FLASHEx_OB_SelectPCROP 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:482:19:HAL_FLASHEx_OB_DeSelectPCROP 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:977:6:FLASH_Erase_Sector 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:231:19:HAL_FLASHEx_Erase_IT 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1306:6:FLASH_FlushCaches 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:160:19:HAL_FLASHEx_Erase 32 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo new file mode 100644 index 00000000..bd716274 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo @@ -0,0 +1,4 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:94:30:HAL_FLASHEx_StopFlashInterfaceClk 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:111:30:HAL_FLASHEx_StartFlashInterfaceClk 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:128:30:HAL_FLASHEx_EnableFlashSleepMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:145:30:HAL_FLASHEx_DisableFlashSleepMode 1 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d new file mode 100644 index 00000000..141bd7f2 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o new file mode 100644 index 00000000..dafaad06 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su new file mode 100644 index 00000000..ab196ef4 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su @@ -0,0 +1,4 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:94:30:HAL_FLASHEx_StopFlashInterfaceClk 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:111:30:HAL_FLASHEx_StartFlashInterfaceClk 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:128:30:HAL_FLASHEx_EnableFlashSleepMode 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:145:30:HAL_FLASHEx_DisableFlashSleepMode 8 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo new file mode 100644 index 00000000..fc62138b --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo @@ -0,0 +1,8 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:164:6:HAL_GPIO_Init 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:294:6:HAL_GPIO_DeInit 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:375:15:HAL_GPIO_ReadPin 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:410:6:HAL_GPIO_WritePin 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:433:6:HAL_GPIO_TogglePin 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:458:19:HAL_GPIO_LockPin 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:507:13:HAL_GPIO_EXTI_Callback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:492:6:HAL_GPIO_EXTI_IRQHandler 2 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d new file mode 100644 index 00000000..12e17379 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o new file mode 100644 index 00000000..6fc0d58e Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su new file mode 100644 index 00000000..0cfe1359 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su @@ -0,0 +1,8 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:164:6:HAL_GPIO_Init 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:294:6:HAL_GPIO_DeInit 36 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:375:15:HAL_GPIO_ReadPin 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:410:6:HAL_GPIO_WritePin 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:433:6:HAL_GPIO_TogglePin 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:458:19:HAL_GPIO_LockPin 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:507:13:HAL_GPIO_EXTI_Callback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:492:6:HAL_GPIO_EXTI_IRQHandler 8 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo new file mode 100644 index 00000000..a89752cc --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo @@ -0,0 +1,62 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7507:26:I2C_IsAcknowledgeFailed 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7221:26:I2C_WaitOnFlagUntilTimeout 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7258:26:I2C_WaitOnMasterAddressFlagUntilTimeout 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7312:26:I2C_WaitOnTXEFlagUntilTimeout 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6743:26:I2C_RequestMemoryWrite 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6823:26:I2C_RequestMemoryRead 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7353:26:I2C_WaitOnBTFFlagUntilTimeout 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7459:26:I2C_WaitOnRXNEFlagUntilTimeout 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:606:13:HAL_I2C_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:445:19:HAL_I2C_Init 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:622:13:HAL_I2C_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:560:19:HAL_I2C_DeInit 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1056:19:HAL_I2C_Master_Transmit 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1177:19:HAL_I2C_Master_Receive 31 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1428:19:HAL_I2C_Slave_Transmit 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1558:19:HAL_I2C_Slave_Receive 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1679:19:HAL_I2C_Master_Transmit_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1756:19:HAL_I2C_Master_Receive_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1836:19:HAL_I2C_Slave_Transmit_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1898:19:HAL_I2C_Slave_Receive_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1962:19:HAL_I2C_Master_Transmit_DMA 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2117:19:HAL_I2C_Master_Receive_DMA 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2270:19:HAL_I2C_Slave_Transmit_DMA 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2384:19:HAL_I2C_Slave_Receive_DMA 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2503:19:HAL_I2C_Mem_Write 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2626:19:HAL_I2C_Mem_Read 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2878:19:HAL_I2C_Mem_Write_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2963:19:HAL_I2C_Mem_Read_IT 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3054:19:HAL_I2C_Mem_Write_DMA 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3236:19:HAL_I2C_Mem_Read_DMA 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3432:19:HAL_I2C_IsDeviceReady 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3568:19:HAL_I2C_Master_Seq_Transmit_IT 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3663:19:HAL_I2C_Master_Seq_Transmit_DMA 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3843:19:HAL_I2C_Master_Seq_Receive_IT 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3964:19:HAL_I2C_Master_Seq_Receive_DMA 27 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4179:19:HAL_I2C_Slave_Seq_Transmit_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4245:19:HAL_I2C_Slave_Seq_Transmit_DMA 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4419:19:HAL_I2C_Slave_Seq_Receive_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4485:19:HAL_I2C_Slave_Seq_Receive_DMA 16 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4655:19:HAL_I2C_EnableListen_IT 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4688:19:HAL_I2C_DisableListen_IT 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5032:13:HAL_I2C_MasterTxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5048:13:HAL_I2C_MasterRxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5063:13:HAL_I2C_SlaveTxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5079:13:HAL_I2C_SlaveRxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5097:13:HAL_I2C_AddrCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5115:13:HAL_I2C_ListenCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5131:13:HAL_I2C_MemTxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5433:13:I2C_MemoryTransmit_TXE_BTF 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5147:13:HAL_I2C_MemRxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5163:13:HAL_I2C_ErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7077:13:I2C_DMAError 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6932:13:I2C_DMAXferCplt 18 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5179:13:HAL_I2C_AbortCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7118:13:I2C_DMAAbort 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6407:13:I2C_ITError 18 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4723:19:HAL_I2C_Master_Abort_IT 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4783:6:HAL_I2C_EV_IRQHandler 156 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4952:6:HAL_I2C_ER_IRQHandler 22 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5214:22:HAL_I2C_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5226:21:HAL_I2C_GetMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5237:10:HAL_I2C_GetError 1 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d new file mode 100644 index 00000000..cfb11d36 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o new file mode 100644 index 00000000..c125883e Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su new file mode 100644 index 00000000..c9dce67d --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su @@ -0,0 +1,62 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7507:26:I2C_IsAcknowledgeFailed 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7221:26:I2C_WaitOnFlagUntilTimeout 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7258:26:I2C_WaitOnMasterAddressFlagUntilTimeout 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7312:26:I2C_WaitOnTXEFlagUntilTimeout 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6743:26:I2C_RequestMemoryWrite 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6823:26:I2C_RequestMemoryRead 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7353:26:I2C_WaitOnBTFFlagUntilTimeout 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7459:26:I2C_WaitOnRXNEFlagUntilTimeout 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:606:13:HAL_I2C_MspInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:445:19:HAL_I2C_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:622:13:HAL_I2C_MspDeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:560:19:HAL_I2C_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1056:19:HAL_I2C_Master_Transmit 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1177:19:HAL_I2C_Master_Receive 64 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1428:19:HAL_I2C_Slave_Transmit 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1558:19:HAL_I2C_Slave_Receive 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1679:19:HAL_I2C_Master_Transmit_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1756:19:HAL_I2C_Master_Receive_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1836:19:HAL_I2C_Slave_Transmit_IT 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1898:19:HAL_I2C_Slave_Receive_IT 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:1962:19:HAL_I2C_Master_Transmit_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2117:19:HAL_I2C_Master_Receive_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2270:19:HAL_I2C_Slave_Transmit_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2384:19:HAL_I2C_Slave_Receive_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2503:19:HAL_I2C_Mem_Write 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2626:19:HAL_I2C_Mem_Read 56 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2878:19:HAL_I2C_Mem_Write_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:2963:19:HAL_I2C_Mem_Read_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3054:19:HAL_I2C_Mem_Write_DMA 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3236:19:HAL_I2C_Mem_Read_DMA 56 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3432:19:HAL_I2C_IsDeviceReady 56 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3568:19:HAL_I2C_Master_Seq_Transmit_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3663:19:HAL_I2C_Master_Seq_Transmit_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3843:19:HAL_I2C_Master_Seq_Receive_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:3964:19:HAL_I2C_Master_Seq_Receive_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4179:19:HAL_I2C_Slave_Seq_Transmit_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4245:19:HAL_I2C_Slave_Seq_Transmit_DMA 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4419:19:HAL_I2C_Slave_Seq_Receive_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4485:19:HAL_I2C_Slave_Seq_Receive_DMA 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4655:19:HAL_I2C_EnableListen_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4688:19:HAL_I2C_DisableListen_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5032:13:HAL_I2C_MasterTxCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5048:13:HAL_I2C_MasterRxCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5063:13:HAL_I2C_SlaveTxCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5079:13:HAL_I2C_SlaveRxCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5097:13:HAL_I2C_AddrCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5115:13:HAL_I2C_ListenCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5131:13:HAL_I2C_MemTxCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5433:13:I2C_MemoryTransmit_TXE_BTF 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5147:13:HAL_I2C_MemRxCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5163:13:HAL_I2C_ErrorCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7077:13:I2C_DMAError 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6932:13:I2C_DMAXferCplt 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5179:13:HAL_I2C_AbortCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:7118:13:I2C_DMAAbort 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:6407:13:I2C_ITError 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4723:19:HAL_I2C_Master_Abort_IT 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4783:6:HAL_I2C_EV_IRQHandler 80 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:4952:6:HAL_I2C_ER_IRQHandler 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5214:22:HAL_I2C_GetState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5226:21:HAL_I2C_GetMode 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c:5237:10:HAL_I2C_GetError 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo new file mode 100644 index 00000000..84b11ba7 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo @@ -0,0 +1,2 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c:88:19:HAL_I2CEx_ConfigAnalogFilter 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c:126:19:HAL_I2CEx_ConfigDigitalFilter 2 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d new file mode 100644 index 00000000..2cffc3d7 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o new file mode 100644 index 00000000..7b9fb538 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su new file mode 100644 index 00000000..b443fe65 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su @@ -0,0 +1,2 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c:88:19:HAL_I2CEx_ConfigAnalogFilter 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c:126:19:HAL_I2CEx_ConfigDigitalFilter 12 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo new file mode 100644 index 00000000..3f8dd06a --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo @@ -0,0 +1,35 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:297:13:HAL_PCD_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:123:19:HAL_PCD_Init 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:312:13:HAL_PCD_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:258:19:HAL_PCD_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1015:19:HAL_PCD_Start 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1040:19:HAL_PCD_Stop 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1532:6:HAL_PCD_WKUP_IRQHandler 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1559:13:HAL_PCD_DataOutStageCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1576:13:HAL_PCD_DataInStageCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1591:13:HAL_PCD_SetupStageCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1606:13:HAL_PCD_SOFCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1621:13:HAL_PCD_ResetCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1636:13:HAL_PCD_SuspendCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1651:13:HAL_PCD_ResumeCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1667:13:HAL_PCD_ISOOUTIncompleteCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1684:13:HAL_PCD_ISOINIncompleteCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1700:13:HAL_PCD_ConnectCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1715:13:HAL_PCD_DisconnectCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1749:19:HAL_PCD_DevConnect 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1772:19:HAL_PCD_DevDisconnect 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1797:19:HAL_PCD_SetAddress 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1814:19:HAL_PCD_EP_Open 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1860:19:HAL_PCD_EP_Close 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1891:19:HAL_PCD_EP_Receive 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1920:10:HAL_PCD_EP_GetRxCount 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1932:19:HAL_PCD_EP_Transmit 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1961:19:HAL_PCD_EP_SetStall 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2004:19:HAL_PCD_EP_ClrStall 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2040:19:HAL_PCD_EP_Abort 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1068:6:HAL_PCD_IRQHandler 81 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2066:19:HAL_PCD_EP_Flush 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2089:19:HAL_PCD_ActivateRemoteWakeup 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2099:19:HAL_PCD_DeActivateRemoteWakeup 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2128:18:HAL_PCD_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2140:19:HAL_PCD_SetTestMode 2 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d new file mode 100644 index 00000000..8ed93470 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o new file mode 100644 index 00000000..bacab9b1 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su new file mode 100644 index 00000000..96a9c3c0 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su @@ -0,0 +1,35 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:297:13:HAL_PCD_MspInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:123:19:HAL_PCD_Init 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:312:13:HAL_PCD_MspDeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:258:19:HAL_PCD_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1015:19:HAL_PCD_Start 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1040:19:HAL_PCD_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1532:6:HAL_PCD_WKUP_IRQHandler 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1559:13:HAL_PCD_DataOutStageCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1576:13:HAL_PCD_DataInStageCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1591:13:HAL_PCD_SetupStageCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1606:13:HAL_PCD_SOFCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1621:13:HAL_PCD_ResetCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1636:13:HAL_PCD_SuspendCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1651:13:HAL_PCD_ResumeCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1667:13:HAL_PCD_ISOOUTIncompleteCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1684:13:HAL_PCD_ISOINIncompleteCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1700:13:HAL_PCD_ConnectCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1715:13:HAL_PCD_DisconnectCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1749:19:HAL_PCD_DevConnect 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1772:19:HAL_PCD_DevDisconnect 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1797:19:HAL_PCD_SetAddress 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1814:19:HAL_PCD_EP_Open 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1860:19:HAL_PCD_EP_Close 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1891:19:HAL_PCD_EP_Receive 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1920:10:HAL_PCD_EP_GetRxCount 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1932:19:HAL_PCD_EP_Transmit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1961:19:HAL_PCD_EP_SetStall 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2004:19:HAL_PCD_EP_ClrStall 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2040:19:HAL_PCD_EP_Abort 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:1068:6:HAL_PCD_IRQHandler 72 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2066:19:HAL_PCD_EP_Flush 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2089:19:HAL_PCD_ActivateRemoteWakeup 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2099:19:HAL_PCD_DeActivateRemoteWakeup 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2128:18:HAL_PCD_GetState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c:2140:19:HAL_PCD_SetTestMode 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo new file mode 100644 index 00000000..f616ddf9 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo @@ -0,0 +1,6 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:70:19:HAL_PCDEx_SetTxFiFo 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:112:19:HAL_PCDEx_SetRxFiFo 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:126:19:HAL_PCDEx_ActivateLPM 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:143:19:HAL_PCDEx_DeActivateLPM 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:303:13:HAL_PCDEx_LPM_Callback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:320:13:HAL_PCDEx_BCD_Callback 1 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d new file mode 100644 index 00000000..a330b78f --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o new file mode 100644 index 00000000..822a92af Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su new file mode 100644 index 00000000..864fbfa3 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su @@ -0,0 +1,6 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:70:19:HAL_PCDEx_SetTxFiFo 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:112:19:HAL_PCDEx_SetRxFiFo 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:126:19:HAL_PCDEx_ActivateLPM 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:143:19:HAL_PCDEx_DeActivateLPM 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:303:13:HAL_PCDEx_LPM_Callback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c:320:13:HAL_PCDEx_BCD_Callback 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo new file mode 100644 index 00000000..37de02b1 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo @@ -0,0 +1,17 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:90:6:HAL_PWR_DeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:108:6:HAL_PWR_EnableBkUpAccess 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:128:6:HAL_PWR_DisableBkUpAccess 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:275:6:HAL_PWR_ConfigPVD 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:318:6:HAL_PWR_EnablePVD 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:327:6:HAL_PWR_DisablePVD 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:341:6:HAL_PWR_EnableWakeUpPin 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:359:6:HAL_PWR_DisableWakeUpPin 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:391:6:HAL_PWR_EnterSLEEPMode 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:445:6:HAL_PWR_EnterSTOPMode 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:488:6:HAL_PWR_EnterSTANDBYMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:526:13:HAL_PWR_PVDCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:509:6:HAL_PWR_PVD_IRQHandler 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:541:6:HAL_PWR_EnableSleepOnExit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:553:6:HAL_PWR_DisableSleepOnExit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:565:6:HAL_PWR_EnableSEVOnPend 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:577:6:HAL_PWR_DisableSEVOnPend 1 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d new file mode 100644 index 00000000..75b77829 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o new file mode 100644 index 00000000..2073e4f8 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su new file mode 100644 index 00000000..9f0e3275 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su @@ -0,0 +1,17 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:90:6:HAL_PWR_DeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:108:6:HAL_PWR_EnableBkUpAccess 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:128:6:HAL_PWR_DisableBkUpAccess 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:275:6:HAL_PWR_ConfigPVD 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:318:6:HAL_PWR_EnablePVD 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:327:6:HAL_PWR_DisablePVD 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:341:6:HAL_PWR_EnableWakeUpPin 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:359:6:HAL_PWR_DisableWakeUpPin 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:391:6:HAL_PWR_EnterSLEEPMode 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:445:6:HAL_PWR_EnterSTOPMode 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:488:6:HAL_PWR_EnterSTANDBYMode 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:526:13:HAL_PWR_PVDCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:509:6:HAL_PWR_PVD_IRQHandler 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:541:6:HAL_PWR_EnableSleepOnExit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:553:6:HAL_PWR_DisableSleepOnExit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:565:6:HAL_PWR_EnableSEVOnPend 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:577:6:HAL_PWR_DisableSEVOnPend 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo new file mode 100644 index 00000000..970ac44e --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:141:19:HAL_PWREx_EnableBkUpReg 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:165:19:HAL_PWREx_DisableBkUpReg 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:189:6:HAL_PWREx_EnableFlashPowerDown 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:198:6:HAL_PWREx_DisableFlashPowerDown 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:211:10:HAL_PWREx_GetVoltageRange 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:288:19:HAL_PWREx_ControlVoltageScaling 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:413:19:HAL_PWREx_EnableOverDrive 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:460:19:HAL_PWREx_DisableOverDrive 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:536:19:HAL_PWREx_EnterUnderDriveSTOPMode 2 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d new file mode 100644 index 00000000..220344d7 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o new file mode 100644 index 00000000..86717c0b Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su new file mode 100644 index 00000000..df62720b --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su @@ -0,0 +1,9 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:141:19:HAL_PWREx_EnableBkUpReg 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:165:19:HAL_PWREx_DisableBkUpReg 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:189:6:HAL_PWREx_EnableFlashPowerDown 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:198:6:HAL_PWREx_DisableFlashPowerDown 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:211:10:HAL_PWREx_GetVoltageRange 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:288:19:HAL_PWREx_ControlVoltageScaling 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:413:19:HAL_PWREx_EnableOverDrive 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:460:19:HAL_PWREx_DisableOverDrive 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:536:19:HAL_PWREx_EnterUnderDriveSTOPMode 8 static,ignoring_inline_asm diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo new file mode 100644 index 00000000..445a5337 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:200:26:HAL_RCC_DeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:219:26:HAL_RCC_OscConfig 60 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:775:6:HAL_RCC_MCOConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:841:6:HAL_RCC_EnableCSS 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:850:6:HAL_RCC_DisableCSS 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:885:17:HAL_RCC_GetSysClockFreq 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:591:19:HAL_RCC_ClockConfig 19 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:943:10:HAL_RCC_GetHCLKFreq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:954:10:HAL_RCC_GetPCLK1Freq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:966:10:HAL_RCC_GetPCLK2Freq 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:979:13:HAL_RCC_GetOscConfig 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1058:6:HAL_RCC_GetClockConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1101:13:HAL_RCC_CSSCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1084:6:HAL_RCC_NMI_IRQHandler 2 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d new file mode 100644 index 00000000..ed14ce03 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o new file mode 100644 index 00000000..3955c412 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su new file mode 100644 index 00000000..bd421422 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su @@ -0,0 +1,14 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:200:26:HAL_RCC_DeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:219:26:HAL_RCC_OscConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:775:6:HAL_RCC_MCOConfig 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:841:6:HAL_RCC_EnableCSS 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:850:6:HAL_RCC_DisableCSS 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:885:17:HAL_RCC_GetSysClockFreq 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:591:19:HAL_RCC_ClockConfig 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:943:10:HAL_RCC_GetHCLKFreq 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:954:10:HAL_RCC_GetPCLK1Freq 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:966:10:HAL_RCC_GetPCLK2Freq 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:979:13:HAL_RCC_GetOscConfig 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1058:6:HAL_RCC_GetClockConfig 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1101:13:HAL_RCC_CSSCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1084:6:HAL_RCC_NMI_IRQHandler 8 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo new file mode 100644 index 00000000..4f039ca9 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo @@ -0,0 +1,12 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:87:19:HAL_RCCEx_PeriphCLKConfig 51 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:500:6:HAL_RCCEx_GetPeriphCLKConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:580:10:HAL_RCCEx_GetPeriphCLKFreq 27 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2809:6:HAL_RCCEx_SelectLSEMode 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2846:19:HAL_RCCEx_EnablePLLI2S 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2929:19:HAL_RCCEx_DisablePLLI2S 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2959:19:HAL_RCCEx_EnablePLLSAI 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3033:19:HAL_RCCEx_DisablePLLSAI 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3094:10:HAL_RCC_GetSysClockFreq 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3186:19:HAL_RCC_DeInit 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3377:19:HAL_RCC_OscConfig 64 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3752:6:HAL_RCC_GetOscConfig 3 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d new file mode 100644 index 00000000..efb9c676 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o new file mode 100644 index 00000000..decd53a0 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su new file mode 100644 index 00000000..b22b21bc --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su @@ -0,0 +1,12 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:87:19:HAL_RCCEx_PeriphCLKConfig 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:500:6:HAL_RCCEx_GetPeriphCLKConfig 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:580:10:HAL_RCCEx_GetPeriphCLKFreq 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2809:6:HAL_RCCEx_SelectLSEMode 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2846:19:HAL_RCCEx_EnablePLLI2S 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2929:19:HAL_RCCEx_DisablePLLI2S 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2959:19:HAL_RCCEx_EnablePLLSAI 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3033:19:HAL_RCCEx_DisablePLLSAI 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3094:10:HAL_RCC_GetSysClockFreq 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3186:19:HAL_RCC_DeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3377:19:HAL_RCC_OscConfig 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3752:6:HAL_RCC_GetOscConfig 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo new file mode 100644 index 00000000..861c0142 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo @@ -0,0 +1,113 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6829:13:TIM_OC1_SetConfig 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6981:13:TIM_OC3_SetConfig 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7056:13:TIM_OC4_SetConfig 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:369:13:HAL_TIM_Base_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:384:13:HAL_TIM_Base_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:326:19:HAL_TIM_Base_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:400:19:HAL_TIM_Base_Start 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:439:19:HAL_TIM_Base_Stop 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:459:19:HAL_TIM_Base_Start_IT 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:501:19:HAL_TIM_Base_Stop_IT 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:526:19:HAL_TIM_Base_Start_DMA 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:595:19:HAL_TIM_Base_Stop_DMA 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:753:13:HAL_TIM_OC_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:768:13:HAL_TIM_OC_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:710:19:HAL_TIM_OC_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1418:13:HAL_TIM_PWM_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1375:19:HAL_TIM_PWM_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2082:13:HAL_TIM_IC_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2097:13:HAL_TIM_IC_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2039:19:HAL_TIM_IC_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2742:13:HAL_TIM_OnePulse_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2757:13:HAL_TIM_OnePulse_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2697:19:HAL_TIM_OnePulse_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2777:19:HAL_TIM_OnePulse_Start 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2834:19:HAL_TIM_OnePulse_Stop 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2877:19:HAL_TIM_OnePulse_Start_IT 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2940:19:HAL_TIM_OnePulse_Stop_IT 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3179:13:HAL_TIM_Encoder_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3194:13:HAL_TIM_Encoder_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3134:19:HAL_TIM_Encoder_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3214:19:HAL_TIM_Encoder_Start 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3308:19:HAL_TIM_Encoder_Stop 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3368:19:HAL_TIM_Encoder_Start_IT 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3468:19:HAL_TIM_Encoder_Stop_IT 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3533:19:HAL_TIM_Encoder_Start_DMA 30 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3746:19:HAL_TIM_Encoder_Stop_DMA 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4534:19:HAL_TIM_DMABurst_MultiWriteStart 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4481:19:HAL_TIM_DMABurst_WriteStart 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4718:19:HAL_TIM_DMABurst_WriteStop 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4870:19:HAL_TIM_DMABurst_MultiReadStart 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4819:19:HAL_TIM_DMABurst_ReadStart 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5054:19:HAL_TIM_DMABurst_ReadStop 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5137:19:HAL_TIM_GenerateEvent 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5458:19:HAL_TIM_ConfigTI1Input 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5573:10:HAL_TIM_ReadCapturedValue 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5657:13:HAL_TIM_PeriodElapsedCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6702:13:TIM_DMAPeriodElapsedCplt 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5672:13:HAL_TIM_PeriodElapsedHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6723:13:TIM_DMAPeriodElapsedHalfCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5687:13:HAL_TIM_OC_DelayElapsedCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5702:13:HAL_TIM_IC_CaptureCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6600:6:TIM_DMACaptureCplt 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5717:13:HAL_TIM_IC_CaptureHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6663:6:TIM_DMACaptureHalfCplt 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5732:13:HAL_TIM_PWM_PulseFinishedCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6502:13:TIM_DMADelayPulseCplt 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5747:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6561:6:TIM_DMADelayPulseHalfCplt 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5762:13:HAL_TIM_TriggerCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3823:6:HAL_TIM_IRQHandler 21 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6739:13:TIM_DMATriggerCplt 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5777:13:HAL_TIM_TriggerHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6760:13:TIM_DMATriggerHalfCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5792:13:HAL_TIM_ErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6459:6:TIM_DMAError 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6339:22:HAL_TIM_Base_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6349:22:HAL_TIM_OC_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6359:22:HAL_TIM_PWM_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6369:22:HAL_TIM_IC_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6379:22:HAL_TIM_OnePulse_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6389:22:HAL_TIM_Encoder_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6399:23:HAL_TIM_GetActiveChannel 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6417:29:HAL_TIM_GetChannelState 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6434:30:HAL_TIM_DMABurstState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6777:6:TIM_Base_SetConfig 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:266:19:HAL_TIM_Base_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:650:19:HAL_TIM_OC_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1315:19:HAL_TIM_PWM_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1979:19:HAL_TIM_IC_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2628:19:HAL_TIM_OnePulse_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3019:19:HAL_TIM_Encoder_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6905:6:TIM_OC2_SetConfig 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4041:19:HAL_TIM_OC_ConfigChannel 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4219:19:HAL_TIM_PWM_ConfigChannel 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7251:6:TIM_TI1_SetConfig 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4120:19:HAL_TIM_IC_ConfigChannel 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4333:19:HAL_TIM_OnePulse_ConfigChannel 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7545:6:TIM_ETR_SetConfig 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5174:19:HAL_TIM_ConfigOCrefClear 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5304:19:HAL_TIM_ConfigClockSource 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7117:26:TIM_SlaveTimer_SetConfig.constprop 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5530:19:HAL_TIM_SlaveConfigSynchro_IT 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5490:19:HAL_TIM_SlaveConfigSynchro 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7575:6:TIM_CCxChannelCmd 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:789:19:HAL_TIM_OC_Start 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1454:19:HAL_TIM_PWM_Start 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:843:19:HAL_TIM_OC_Stop 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1508:19:HAL_TIM_PWM_Stop 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:878:19:HAL_TIM_OC_Start_IT 18 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1543:19:HAL_TIM_PWM_Start_IT 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:971:19:HAL_TIM_OC_Stop_IT 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1636:19:HAL_TIM_PWM_Stop_IT 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1048:19:HAL_TIM_OC_Start_DMA 28 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1713:19:HAL_TIM_PWM_Start_DMA 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1212:19:HAL_TIM_OC_Stop_DMA 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1876:19:HAL_TIM_PWM_Stop_DMA 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2118:19:HAL_TIM_IC_Start 18 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2170:19:HAL_TIM_IC_Stop 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2200:19:HAL_TIM_IC_Start_IT 19 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2292:19:HAL_TIM_IC_Stop_IT 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2364:19:HAL_TIM_IC_Start_DMA 31 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2523:19:HAL_TIM_IC_Stop_DMA 11 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d new file mode 100644 index 00000000..74d1f732 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o new file mode 100644 index 00000000..845bc90c Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su new file mode 100644 index 00000000..b9cc97e0 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su @@ -0,0 +1,113 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6829:13:TIM_OC1_SetConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6981:13:TIM_OC3_SetConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7056:13:TIM_OC4_SetConfig 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:369:13:HAL_TIM_Base_MspInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:384:13:HAL_TIM_Base_MspDeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:326:19:HAL_TIM_Base_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:400:19:HAL_TIM_Base_Start 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:439:19:HAL_TIM_Base_Stop 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:459:19:HAL_TIM_Base_Start_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:501:19:HAL_TIM_Base_Stop_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:526:19:HAL_TIM_Base_Start_DMA 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:595:19:HAL_TIM_Base_Stop_DMA 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:753:13:HAL_TIM_OC_MspInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:768:13:HAL_TIM_OC_MspDeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:710:19:HAL_TIM_OC_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1418:13:HAL_TIM_PWM_MspInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspDeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1375:19:HAL_TIM_PWM_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2082:13:HAL_TIM_IC_MspInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2097:13:HAL_TIM_IC_MspDeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2039:19:HAL_TIM_IC_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2742:13:HAL_TIM_OnePulse_MspInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2757:13:HAL_TIM_OnePulse_MspDeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2697:19:HAL_TIM_OnePulse_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2777:19:HAL_TIM_OnePulse_Start 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2834:19:HAL_TIM_OnePulse_Stop 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2877:19:HAL_TIM_OnePulse_Start_IT 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2940:19:HAL_TIM_OnePulse_Stop_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3179:13:HAL_TIM_Encoder_MspInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3194:13:HAL_TIM_Encoder_MspDeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3134:19:HAL_TIM_Encoder_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3214:19:HAL_TIM_Encoder_Start 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3308:19:HAL_TIM_Encoder_Stop 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3368:19:HAL_TIM_Encoder_Start_IT 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3468:19:HAL_TIM_Encoder_Stop_IT 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3533:19:HAL_TIM_Encoder_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3746:19:HAL_TIM_Encoder_Stop_DMA 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4534:19:HAL_TIM_DMABurst_MultiWriteStart 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4481:19:HAL_TIM_DMABurst_WriteStart 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4718:19:HAL_TIM_DMABurst_WriteStop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4870:19:HAL_TIM_DMABurst_MultiReadStart 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4819:19:HAL_TIM_DMABurst_ReadStart 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5054:19:HAL_TIM_DMABurst_ReadStop 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5137:19:HAL_TIM_GenerateEvent 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5458:19:HAL_TIM_ConfigTI1Input 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5573:10:HAL_TIM_ReadCapturedValue 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5657:13:HAL_TIM_PeriodElapsedCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6702:13:TIM_DMAPeriodElapsedCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5672:13:HAL_TIM_PeriodElapsedHalfCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6723:13:TIM_DMAPeriodElapsedHalfCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5687:13:HAL_TIM_OC_DelayElapsedCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5702:13:HAL_TIM_IC_CaptureCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6600:6:TIM_DMACaptureCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5717:13:HAL_TIM_IC_CaptureHalfCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6663:6:TIM_DMACaptureHalfCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5732:13:HAL_TIM_PWM_PulseFinishedCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6502:13:TIM_DMADelayPulseCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5747:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6561:6:TIM_DMADelayPulseHalfCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5762:13:HAL_TIM_TriggerCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3823:6:HAL_TIM_IRQHandler 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6739:13:TIM_DMATriggerCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5777:13:HAL_TIM_TriggerHalfCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6760:13:TIM_DMATriggerHalfCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5792:13:HAL_TIM_ErrorCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6459:6:TIM_DMAError 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6339:22:HAL_TIM_Base_GetState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6349:22:HAL_TIM_OC_GetState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6359:22:HAL_TIM_PWM_GetState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6369:22:HAL_TIM_IC_GetState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6379:22:HAL_TIM_OnePulse_GetState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6389:22:HAL_TIM_Encoder_GetState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6399:23:HAL_TIM_GetActiveChannel 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6417:29:HAL_TIM_GetChannelState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6434:30:HAL_TIM_DMABurstState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6777:6:TIM_Base_SetConfig 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:266:19:HAL_TIM_Base_Init 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:650:19:HAL_TIM_OC_Init 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1315:19:HAL_TIM_PWM_Init 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1979:19:HAL_TIM_IC_Init 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2628:19:HAL_TIM_OnePulse_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:3019:19:HAL_TIM_Encoder_Init 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:6905:6:TIM_OC2_SetConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4041:19:HAL_TIM_OC_ConfigChannel 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4219:19:HAL_TIM_PWM_ConfigChannel 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7251:6:TIM_TI1_SetConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4120:19:HAL_TIM_IC_ConfigChannel 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:4333:19:HAL_TIM_OnePulse_ConfigChannel 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7545:6:TIM_ETR_SetConfig 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5174:19:HAL_TIM_ConfigOCrefClear 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5304:19:HAL_TIM_ConfigClockSource 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7117:26:TIM_SlaveTimer_SetConfig.constprop 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5530:19:HAL_TIM_SlaveConfigSynchro_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:5490:19:HAL_TIM_SlaveConfigSynchro 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:7575:6:TIM_CCxChannelCmd 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:789:19:HAL_TIM_OC_Start 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1454:19:HAL_TIM_PWM_Start 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:843:19:HAL_TIM_OC_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1508:19:HAL_TIM_PWM_Stop 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:878:19:HAL_TIM_OC_Start_IT 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1543:19:HAL_TIM_PWM_Start_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:971:19:HAL_TIM_OC_Stop_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1636:19:HAL_TIM_PWM_Stop_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1048:19:HAL_TIM_OC_Start_DMA 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1713:19:HAL_TIM_PWM_Start_DMA 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1212:19:HAL_TIM_OC_Stop_DMA 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:1876:19:HAL_TIM_PWM_Stop_DMA 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2118:19:HAL_TIM_IC_Start 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2170:19:HAL_TIM_IC_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2200:19:HAL_TIM_IC_Start_IT 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2292:19:HAL_TIM_IC_Stop_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2364:19:HAL_TIM_IC_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c:2523:19:HAL_TIM_IC_Stop_DMA 16 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo new file mode 100644 index 00000000..75307948 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo @@ -0,0 +1,42 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2387:13:TIM_CCxNChannelCmd 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2342:13:TIM_DMAErrorCCxN 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2292:13:TIM_DMADelayPulseNCplt 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:285:13:HAL_TIMEx_HallSensor_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:138:19:HAL_TIMEx_HallSensor_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:300:13:HAL_TIMEx_HallSensor_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:240:19:HAL_TIMEx_HallSensor_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:315:19:HAL_TIMEx_HallSensor_Start 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:369:19:HAL_TIMEx_HallSensor_Stop 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:397:19:HAL_TIMEx_HallSensor_Start_IT 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:454:19:HAL_TIMEx_HallSensor_Stop_IT 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:487:19:HAL_TIMEx_HallSensor_Start_DMA 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:563:19:HAL_TIMEx_HallSensor_Stop_DMA 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:625:19:HAL_TIMEx_OCN_Start 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:676:19:HAL_TIMEx_OCN_Stop 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:708:19:HAL_TIMEx_OCN_Start_IT 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:795:19:HAL_TIMEx_OCN_Stop_IT 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:870:19:HAL_TIMEx_OCN_Start_DMA 26 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1008:19:HAL_TIMEx_OCN_Stop_DMA 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1098:19:HAL_TIMEx_PWMN_Start 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1148:19:HAL_TIMEx_PWMN_Stop 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1180:19:HAL_TIMEx_PWMN_Start_IT 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1266:19:HAL_TIMEx_PWMN_Stop_IT 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1341:19:HAL_TIMEx_PWMN_Start_DMA 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1479:19:HAL_TIMEx_PWMN_Stop_DMA 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1570:19:HAL_TIMEx_OnePulseN_Start 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1619:19:HAL_TIMEx_OnePulseN_Stop 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1658:19:HAL_TIMEx_OnePulseN_Start_IT 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1713:19:HAL_TIMEx_OnePulseN_Stop_IT 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1792:19:HAL_TIMEx_ConfigCommutEvent 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1848:19:HAL_TIMEx_ConfigCommutEvent_IT 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1905:19:HAL_TIMEx_ConfigCommutEvent_DMA 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1954:19:HAL_TIMEx_MasterConfigSynchronization 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2015:19:HAL_TIMEx_ConfigBreakDeadTime 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2091:19:HAL_TIMEx_RemapConfig 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2147:13:HAL_TIMEx_CommutCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2253:6:TIMEx_DMACommutationCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2161:13:HAL_TIMEx_CommutHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2272:6:TIMEx_DMACommutationHalfCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2176:13:HAL_TIMEx_BreakCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2209:22:HAL_TIMEx_HallSensor_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2224:29:HAL_TIMEx_GetChannelNState 4 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d new file mode 100644 index 00000000..cf3ba16a --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o new file mode 100644 index 00000000..5c30cdf6 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su new file mode 100644 index 00000000..2b61829c --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su @@ -0,0 +1,42 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2387:13:TIM_CCxNChannelCmd 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2342:13:TIM_DMAErrorCCxN 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2292:13:TIM_DMADelayPulseNCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:285:13:HAL_TIMEx_HallSensor_MspInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:138:19:HAL_TIMEx_HallSensor_Init 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:300:13:HAL_TIMEx_HallSensor_MspDeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:240:19:HAL_TIMEx_HallSensor_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:315:19:HAL_TIMEx_HallSensor_Start 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:369:19:HAL_TIMEx_HallSensor_Stop 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:397:19:HAL_TIMEx_HallSensor_Start_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:454:19:HAL_TIMEx_HallSensor_Stop_IT 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:487:19:HAL_TIMEx_HallSensor_Start_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:563:19:HAL_TIMEx_HallSensor_Stop_DMA 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:625:19:HAL_TIMEx_OCN_Start 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:676:19:HAL_TIMEx_OCN_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:708:19:HAL_TIMEx_OCN_Start_IT 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:795:19:HAL_TIMEx_OCN_Stop_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:870:19:HAL_TIMEx_OCN_Start_DMA 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1008:19:HAL_TIMEx_OCN_Stop_DMA 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1098:19:HAL_TIMEx_PWMN_Start 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1148:19:HAL_TIMEx_PWMN_Stop 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1180:19:HAL_TIMEx_PWMN_Start_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1266:19:HAL_TIMEx_PWMN_Stop_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1341:19:HAL_TIMEx_PWMN_Start_DMA 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1479:19:HAL_TIMEx_PWMN_Stop_DMA 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1570:19:HAL_TIMEx_OnePulseN_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1619:19:HAL_TIMEx_OnePulseN_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1658:19:HAL_TIMEx_OnePulseN_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1713:19:HAL_TIMEx_OnePulseN_Stop_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1792:19:HAL_TIMEx_ConfigCommutEvent 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1848:19:HAL_TIMEx_ConfigCommutEvent_IT 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1905:19:HAL_TIMEx_ConfigCommutEvent_DMA 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:1954:19:HAL_TIMEx_MasterConfigSynchronization 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2015:19:HAL_TIMEx_ConfigBreakDeadTime 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2091:19:HAL_TIMEx_RemapConfig 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2147:13:HAL_TIMEx_CommutCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2253:6:TIMEx_DMACommutationCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2161:13:HAL_TIMEx_CommutHalfCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2272:6:TIMEx_DMACommutationHalfCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2176:13:HAL_TIMEx_BreakCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2209:22:HAL_TIMEx_HallSensor_GetState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c:2224:29:HAL_TIMEx_GetChannelNState 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo new file mode 100644 index 00000000..3b78358e --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo @@ -0,0 +1,59 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3370:13:UART_EndRxTransfer 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3731:13:UART_SetConfig 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3212:26:UART_WaitOnFlagUntilTimeout.constprop 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:715:13:HAL_UART_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:357:19:HAL_UART_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:435:19:HAL_HalfDuplex_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:509:19:HAL_LIN_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:591:19:HAL_MultiProcessor_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:730:13:HAL_UART_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:669:19:HAL_UART_DeInit 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1135:19:HAL_UART_Transmit 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1221:19:HAL_UART_Receive 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1308:19:HAL_UART_Transmit_IT 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1379:19:HAL_UART_Transmit_DMA 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1476:19:HAL_UART_DMAPause 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1507:19:HAL_UART_DMAResume 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1541:19:HAL_UART_DMAStop 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1596:19:HAL_UARTEx_ReceiveToIdle 17 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1846:29:HAL_UARTEx_GetRxEventType 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1864:19:HAL_UART_Abort 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1953:19:HAL_UART_AbortTransmit 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2004:19:HAL_UART_AbortReceive 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2619:13:HAL_UART_TxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3015:13:UART_DMATransmitCplt 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2634:13:HAL_UART_TxHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3050:13:UART_DMATxHalfCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2649:13:HAL_UART_RxCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2664:13:HAL_UART_RxHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2679:13:HAL_UART_ErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3170:13:UART_DMAError 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3394:13:UART_DMAAbortOnError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2693:13:HAL_UART_AbortCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2065:19:HAL_UART_Abort_IT 18 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3463:13:UART_DMARxAbortCallback 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3417:13:UART_DMATxAbortCallback 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2708:13:HAL_UART_AbortTransmitCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2200:19:HAL_UART_AbortTransmit_IT 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3509:13:UART_DMATxOnlyAbortCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2723:13:HAL_UART_AbortReceiveCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2277:19:HAL_UART_AbortReceive_IT 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3537:13:UART_DMARxOnlyAbortCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2740:13:HAL_UARTEx_RxEventCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3131:13:UART_DMARxHalfCplt 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3069:13:UART_DMAReceiveCplt 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3628:26:UART_Receive_IT.isra 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2355:6:HAL_UART_IRQHandler 47 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2780:19:HAL_LIN_SendBreak 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2807:19:HAL_MultiProcessor_EnterMuteMode 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2835:19:HAL_MultiProcessor_ExitMuteMode 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2863:19:HAL_HalfDuplex_EnableTransmitter 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2898:19:HAL_HalfDuplex_EnableReceiver 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2955:23:HAL_UART_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2970:10:HAL_UART_GetError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3263:19:UART_Start_Receive_IT 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1347:19:HAL_UART_Receive_IT 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1721:19:HAL_UARTEx_ReceiveToIdle_IT 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3298:19:UART_Start_Receive_DMA 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1449:19:HAL_UART_Receive_DMA 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1781:19:HAL_UARTEx_ReceiveToIdle_DMA 6 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d new file mode 100644 index 00000000..180b2c9f --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o new file mode 100644 index 00000000..55064944 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su new file mode 100644 index 00000000..94e96e37 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su @@ -0,0 +1,59 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3370:13:UART_EndRxTransfer 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3731:13:UART_SetConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3212:26:UART_WaitOnFlagUntilTimeout.constprop 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:715:13:HAL_UART_MspInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:357:19:HAL_UART_Init 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:435:19:HAL_HalfDuplex_Init 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:509:19:HAL_LIN_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:591:19:HAL_MultiProcessor_Init 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:730:13:HAL_UART_MspDeInit 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:669:19:HAL_UART_DeInit 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1135:19:HAL_UART_Transmit 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1221:19:HAL_UART_Receive 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1308:19:HAL_UART_Transmit_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1379:19:HAL_UART_Transmit_DMA 16 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1476:19:HAL_UART_DMAPause 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1507:19:HAL_UART_DMAResume 8 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1541:19:HAL_UART_DMAStop 8 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1596:19:HAL_UARTEx_ReceiveToIdle 40 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1846:29:HAL_UARTEx_GetRxEventType 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1864:19:HAL_UART_Abort 8 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1953:19:HAL_UART_AbortTransmit 8 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2004:19:HAL_UART_AbortReceive 8 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2619:13:HAL_UART_TxCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3015:13:UART_DMATransmitCplt 8 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2634:13:HAL_UART_TxHalfCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3050:13:UART_DMATxHalfCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2649:13:HAL_UART_RxCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2664:13:HAL_UART_RxHalfCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2679:13:HAL_UART_ErrorCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3170:13:UART_DMAError 8 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3394:13:UART_DMAAbortOnError 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2693:13:HAL_UART_AbortCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2065:19:HAL_UART_Abort_IT 16 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3463:13:UART_DMARxAbortCallback 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3417:13:UART_DMATxAbortCallback 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2708:13:HAL_UART_AbortTransmitCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2200:19:HAL_UART_AbortTransmit_IT 8 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3509:13:UART_DMATxOnlyAbortCallback 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2723:13:HAL_UART_AbortReceiveCpltCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2277:19:HAL_UART_AbortReceive_IT 8 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3537:13:UART_DMARxOnlyAbortCallback 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2740:13:HAL_UARTEx_RxEventCallback 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3131:13:UART_DMARxHalfCplt 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3069:13:UART_DMAReceiveCplt 8 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3628:26:UART_Receive_IT.isra 16 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2355:6:HAL_UART_IRQHandler 24 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2780:19:HAL_LIN_SendBreak 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2807:19:HAL_MultiProcessor_EnterMuteMode 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2835:19:HAL_MultiProcessor_ExitMuteMode 0 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2863:19:HAL_HalfDuplex_EnableTransmitter 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2898:19:HAL_HalfDuplex_EnableReceiver 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2955:23:HAL_UART_GetState 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2970:10:HAL_UART_GetError 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3263:19:UART_Start_Receive_IT 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1347:19:HAL_UART_Receive_IT 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1721:19:HAL_UARTEx_ReceiveToIdle_IT 24 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3298:19:UART_Start_Receive_DMA 24 static,ignoring_inline_asm +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1449:19:HAL_UART_Receive_DMA 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1781:19:HAL_UARTEx_ReceiveToIdle_DMA 24 static,ignoring_inline_asm diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo new file mode 100644 index 00000000..b38b4ae6 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo @@ -0,0 +1,49 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1406:26:USB_CoreReset 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:83:19:USB_CoreInit 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:139:19:USB_SetTurnaroundTime 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:222:19:USB_EnableGlobalInt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:234:19:USB_DisableGlobalInt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:249:19:USB_SetCurrentMode 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:473:19:USB_FlushTxFifo 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:510:19:USB_FlushRxFifo 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:553:19:USB_SetDevSpeed 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:296:19:USB_DevInit 14 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:569:9:USB_GetDevSpeed 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:598:19:USB_ActivateEndpoint 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:636:19:USB_ActivateDedicatedEndpoint 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:675:19:USB_DeactivateEndpoint 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:722:19:USB_DeactivateDedicatedEndpoint 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:936:19:USB_EPStopXfer 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1000:19:USB_WritePacket 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:764:19:USB_EPStartXfer 20 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1031:7:USB_ReadPacket 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1073:19:USB_EPSetStall 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1104:19:USB_EPClearStall 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1133:19:USB_StopDevice 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1174:19:USB_SetDevAddress 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1189:19:USB_DevConnect 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1206:19:USB_DevDisconnect 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1223:10:USB_ReadInterrupts 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1239:10:USB_ReadChInterrupts 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1255:10:USB_ReadDevAllOutEpInterrupt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1271:10:USB_ReadDevAllInEpInterrupt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1289:10:USB_ReadDevOutEPInterrupt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1307:10:USB_ReadDevInEPInterrupt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1328:7:USB_ClearInterrupts 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1341:10:USB_GetMode 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1351:19:USB_ActivateSetup 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1373:19:USB_EP0_OutStart 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1453:19:USB_HostInit 6 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1568:19:USB_InitFSLSPClkSel 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1598:19:USB_ResetPort 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1625:19:USB_DriveVbus 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1655:10:USB_GetHostSpeed 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1669:10:USB_GetCurrentFrame 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1700:19:USB_HC_Init 10 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2095:10:USB_HC_ReadInterrupt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2109:19:USB_HC_Halt 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2193:19:USB_DoPing 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1832:19:USB_HC_StartXfer 39 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2217:19:USB_StopHost 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2282:19:USB_ActivateRemoteWakeup 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2300:19:USB_DeActivateRemoteWakeup 1 diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d new file mode 100644 index 00000000..1ed2e89c --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d @@ -0,0 +1,68 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o new file mode 100644 index 00000000..fe95fcb2 Binary files /dev/null and b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o differ diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su new file mode 100644 index 00000000..ae55907f --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su @@ -0,0 +1,49 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1406:26:USB_CoreReset 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:83:19:USB_CoreInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:139:19:USB_SetTurnaroundTime 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:222:19:USB_EnableGlobalInt 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:234:19:USB_DisableGlobalInt 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:249:19:USB_SetCurrentMode 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:473:19:USB_FlushTxFifo 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:510:19:USB_FlushRxFifo 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:553:19:USB_SetDevSpeed 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:296:19:USB_DevInit 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:569:9:USB_GetDevSpeed 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:598:19:USB_ActivateEndpoint 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:636:19:USB_ActivateDedicatedEndpoint 20 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:675:19:USB_DeactivateEndpoint 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:722:19:USB_DeactivateDedicatedEndpoint 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:936:19:USB_EPStopXfer 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1000:19:USB_WritePacket 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:764:19:USB_EPStartXfer 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1031:7:USB_ReadPacket 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1073:19:USB_EPSetStall 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1104:19:USB_EPClearStall 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1133:19:USB_StopDevice 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1174:19:USB_SetDevAddress 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1189:19:USB_DevConnect 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1206:19:USB_DevDisconnect 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1223:10:USB_ReadInterrupts 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1239:10:USB_ReadChInterrupts 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1255:10:USB_ReadDevAllOutEpInterrupt 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1271:10:USB_ReadDevAllInEpInterrupt 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1289:10:USB_ReadDevOutEPInterrupt 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1307:10:USB_ReadDevInEPInterrupt 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1328:7:USB_ClearInterrupts 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1341:10:USB_GetMode 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1351:19:USB_ActivateSetup 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1373:19:USB_EP0_OutStart 12 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1453:19:USB_HostInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1568:19:USB_InitFSLSPClkSel 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1598:19:USB_ResetPort 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1625:19:USB_DriveVbus 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1655:10:USB_GetHostSpeed 8 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1669:10:USB_GetCurrentFrame 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1700:19:USB_HC_Init 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2095:10:USB_HC_ReadInterrupt 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2109:19:USB_HC_Halt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2193:19:USB_DoPing 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:1832:19:USB_HC_StartXfer 48 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2217:19:USB_StopHost 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2282:19:USB_ActivateRemoteWakeup 0 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c:2300:19:USB_DeActivateRemoteWakeup 0 static diff --git a/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 00000000..6a692c63 --- /dev/null +++ b/firmware/numpad/Release/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,87 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c + +OBJS += \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + +C_DEPS += \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F4xx_HAL_Driver/Src/%.o Drivers/STM32F4xx_HAL_Driver/Src/%.su Drivers/STM32F4xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32F4xx_HAL_Driver/Src/%.c Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src + +clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src: + -$(RM) ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.su + +.PHONY: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src + diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk new file mode 100644 index 00000000..d50975d6 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c + +OBJS += \ +./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + +C_DEPS += \ +./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.o Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.su Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.cyclo: ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.c Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Class-2f-HID-2f-Src + +clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Class-2f-HID-2f-Src: + -$(RM) ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su + +.PHONY: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Class-2f-HID-2f-Src + diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo new file mode 100644 index 00000000..c8d80008 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo @@ -0,0 +1,10 @@ +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:607:16:USBD_HID_DataIn 1 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:624:17:USBD_HID_GetDeviceQualifierDesc 1 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:546:17:USBD_HID_GetFSCfgDesc 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:586:17:USBD_HID_GetOtherSpeedCfgDesc 1 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:566:17:USBD_HID_GetHSCfgDesc 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:351:16:USBD_HID_Setup 18 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:320:16:USBD_HID_DeInit 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:273:16:USBD_HID_Init 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:483:9:USBD_HID_SendReport 4 +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:516:10:USBD_HID_GetPollingInterval 1 diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d new file mode 100644 index 00000000..dbb7e592 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d @@ -0,0 +1,85 @@ +Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o: \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o new file mode 100644 index 00000000..c4ad5d42 Binary files /dev/null and b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o differ diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su new file mode 100644 index 00000000..20eda204 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su @@ -0,0 +1,10 @@ +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:607:16:USBD_HID_DataIn 0 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:624:17:USBD_HID_GetDeviceQualifierDesc 0 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:546:17:USBD_HID_GetFSCfgDesc 8 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:586:17:USBD_HID_GetOtherSpeedCfgDesc 0 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:566:17:USBD_HID_GetHSCfgDesc 8 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:351:16:USBD_HID_Setup 16 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:320:16:USBD_HID_DeInit 16 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:273:16:USBD_HID_Init 16 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:483:9:USBD_HID_SendReport 8 static +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:516:10:USBD_HID_GetPollingInterval 0 static diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk new file mode 100644 index 00000000..1bb63c34 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c + +OBJS += \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + +C_DEPS += \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.o Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.su Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.cyclo: ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.c Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Core-2f-Src + +clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Core-2f-Src: + -$(RM) ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su + +.PHONY: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Core-2f-Src + diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo new file mode 100644 index 00000000..b915e796 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.cyclo @@ -0,0 +1,24 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:92:20:USBD_Init 3 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:149:20:USBD_DeInit 2 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:202:20:USBD_RegisterClass 3 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:384:20:USBD_Start 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:400:20:USBD_Stop 2 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:440:20:USBD_RunTestMode 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:465:20:USBD_SetClassConfig 2 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:505:20:USBD_ClrClassConfig 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:546:20:USBD_LL_SetupStage 4 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:586:20:USBD_LL_DataOutStage 8 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:684:20:USBD_LL_DataInStage 12 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:777:20:USBD_LL_Reset 4 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:845:20:USBD_LL_SetSpeed 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:859:20:USBD_LL_Suspend 2 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:877:20:USBD_LL_Resume 2 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:893:20:USBD_LL_SOF 4 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:936:20:USBD_LL_IsoINIncomplete 4 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:962:20:USBD_LL_IsoOUTIncomplete 4 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:987:20:USBD_LL_DevConnected 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1001:20:USBD_LL_DevDisconnected 3 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1046:9:USBD_CoreFindIF 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1086:9:USBD_CoreFindEP 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1157:7:USBD_GetEpDesc 5 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1198:25:USBD_GetNextDesc 1 diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d new file mode 100644 index 00000000..f6fb1ae9 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d @@ -0,0 +1,81 @@ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o: \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o new file mode 100644 index 00000000..4ea1a5fa Binary files /dev/null and b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o differ diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su new file mode 100644 index 00000000..d4285285 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.su @@ -0,0 +1,24 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:92:20:USBD_Init 0 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:149:20:USBD_DeInit 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:202:20:USBD_RegisterClass 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:384:20:USBD_Start 0 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:400:20:USBD_Stop 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:440:20:USBD_RunTestMode 0 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:465:20:USBD_SetClassConfig 0 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:505:20:USBD_ClrClassConfig 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:546:20:USBD_LL_SetupStage 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:586:20:USBD_LL_DataOutStage 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:684:20:USBD_LL_DataInStage 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:777:20:USBD_LL_Reset 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:845:20:USBD_LL_SetSpeed 0 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:859:20:USBD_LL_Suspend 0 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:877:20:USBD_LL_Resume 0 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:893:20:USBD_LL_SOF 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:936:20:USBD_LL_IsoINIncomplete 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:962:20:USBD_LL_IsoOUTIncomplete 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:987:20:USBD_LL_DevConnected 0 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1001:20:USBD_LL_DevDisconnected 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1046:9:USBD_CoreFindIF 0 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1086:9:USBD_CoreFindEP 0 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1157:7:USBD_GetEpDesc 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c:1198:25:USBD_GetNextDesc 0 static diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo new file mode 100644 index 00000000..f2280d9e --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.cyclo @@ -0,0 +1,7 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:979:6:USBD_CtlError.constprop 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:104:20:USBD_StdDevReq 58 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:167:20:USBD_StdItfReq 9 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:239:20:USBD_StdEPReq 32 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:950:6:USBD_ParseSetupRequest 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:979:6:USBD_CtlError 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:996:6:USBD_GetString 3 diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d new file mode 100644 index 00000000..692469a4 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d @@ -0,0 +1,83 @@ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o: \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o new file mode 100644 index 00000000..4949400e Binary files /dev/null and b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o differ diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su new file mode 100644 index 00000000..7cf92096 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.su @@ -0,0 +1,7 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:979:6:USBD_CtlError.constprop 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:104:20:USBD_StdDevReq 24 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:167:20:USBD_StdItfReq 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:239:20:USBD_StdEPReq 16 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:950:6:USBD_ParseSetupRequest 0 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:979:6:USBD_CtlError 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c:996:6:USBD_GetString 16 static diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo new file mode 100644 index 00000000..b8d45878 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.cyclo @@ -0,0 +1,7 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:86:20:USBD_CtlSendData 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:114:20:USBD_CtlContinueSendData 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:131:20:USBD_CtlPrepareRx 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:159:20:USBD_CtlContinueRx 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:173:20:USBD_CtlSendStatus 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:190:20:USBD_CtlReceiveStatus 1 +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:208:10:USBD_GetRxCount 1 diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d new file mode 100644 index 00000000..68758366 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d @@ -0,0 +1,81 @@ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o: \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o new file mode 100644 index 00000000..678e42d4 Binary files /dev/null and b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o differ diff --git a/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su new file mode 100644 index 00000000..c358e6f8 --- /dev/null +++ b/firmware/numpad/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.su @@ -0,0 +1,7 @@ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:86:20:USBD_CtlSendData 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:114:20:USBD_CtlContinueSendData 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:131:20:USBD_CtlPrepareRx 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:159:20:USBD_CtlContinueRx 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:173:20:USBD_CtlSendStatus 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:190:20:USBD_CtlReceiveStatus 8 static +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c:208:10:USBD_GetRxCount 0 static diff --git a/firmware/numpad/Release/USB_DEVICE/App/subdir.mk b/firmware/numpad/Release/USB_DEVICE/App/subdir.mk new file mode 100644 index 00000000..358c99d6 --- /dev/null +++ b/firmware/numpad/Release/USB_DEVICE/App/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../USB_DEVICE/App/usb_device.c \ +../USB_DEVICE/App/usbd_desc.c + +OBJS += \ +./USB_DEVICE/App/usb_device.o \ +./USB_DEVICE/App/usbd_desc.o + +C_DEPS += \ +./USB_DEVICE/App/usb_device.d \ +./USB_DEVICE/App/usbd_desc.d + + +# Each subdirectory must supply rules for building sources it contributes +USB_DEVICE/App/%.o USB_DEVICE/App/%.su USB_DEVICE/App/%.cyclo: ../USB_DEVICE/App/%.c USB_DEVICE/App/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-USB_DEVICE-2f-App + +clean-USB_DEVICE-2f-App: + -$(RM) ./USB_DEVICE/App/usb_device.cyclo ./USB_DEVICE/App/usb_device.d ./USB_DEVICE/App/usb_device.o ./USB_DEVICE/App/usb_device.su ./USB_DEVICE/App/usbd_desc.cyclo ./USB_DEVICE/App/usbd_desc.d ./USB_DEVICE/App/usbd_desc.o ./USB_DEVICE/App/usbd_desc.su + +.PHONY: clean-USB_DEVICE-2f-App + diff --git a/firmware/numpad/Release/USB_DEVICE/App/usb_device.cyclo b/firmware/numpad/Release/USB_DEVICE/App/usb_device.cyclo new file mode 100644 index 00000000..ff36f216 --- /dev/null +++ b/firmware/numpad/Release/USB_DEVICE/App/usb_device.cyclo @@ -0,0 +1 @@ +../USB_DEVICE/App/usb_device.c:63:6:MX_USB_DEVICE_Init 4 diff --git a/firmware/numpad/Release/USB_DEVICE/App/usb_device.d b/firmware/numpad/Release/USB_DEVICE/App/usb_device.d new file mode 100644 index 00000000..f8cd5595 --- /dev/null +++ b/firmware/numpad/Release/USB_DEVICE/App/usb_device.d @@ -0,0 +1,90 @@ +USB_DEVICE/App/usb_device.o: ../USB_DEVICE/App/usb_device.c \ + ../USB_DEVICE/App/usb_device.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + ../USB_DEVICE/App/usbd_desc.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h +../USB_DEVICE/App/usb_device.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +../USB_DEVICE/App/usbd_desc.h: +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: diff --git a/firmware/numpad/Release/USB_DEVICE/App/usb_device.o b/firmware/numpad/Release/USB_DEVICE/App/usb_device.o new file mode 100644 index 00000000..2dd43363 Binary files /dev/null and b/firmware/numpad/Release/USB_DEVICE/App/usb_device.o differ diff --git a/firmware/numpad/Release/USB_DEVICE/App/usb_device.su b/firmware/numpad/Release/USB_DEVICE/App/usb_device.su new file mode 100644 index 00000000..e29c600d --- /dev/null +++ b/firmware/numpad/Release/USB_DEVICE/App/usb_device.su @@ -0,0 +1 @@ +../USB_DEVICE/App/usb_device.c:63:6:MX_USB_DEVICE_Init 8 static diff --git a/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.cyclo b/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.cyclo new file mode 100644 index 00000000..09c8122a --- /dev/null +++ b/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.cyclo @@ -0,0 +1,9 @@ +../USB_DEVICE/App/usbd_desc.c:258:11:USBD_FS_DeviceDescriptor 1 +../USB_DEVICE/App/usbd_desc.c:271:11:USBD_FS_LangIDStrDescriptor 1 +../USB_DEVICE/App/usbd_desc.c:375:11:USBD_FS_USR_BOSDescriptor 1 +../USB_DEVICE/App/usbd_desc.c:414:13:IntToUnicode 3 +../USB_DEVICE/App/usbd_desc.c:316:11:USBD_FS_SerialStrDescriptor 2 +../USB_DEVICE/App/usbd_desc.c:303:11:USBD_FS_ManufacturerStrDescriptor 1 +../USB_DEVICE/App/usbd_desc.c:284:11:USBD_FS_ProductStrDescriptor 1 +../USB_DEVICE/App/usbd_desc.c:336:11:USBD_FS_ConfigStrDescriptor 1 +../USB_DEVICE/App/usbd_desc.c:355:11:USBD_FS_InterfaceStrDescriptor 1 diff --git a/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.d b/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.d new file mode 100644 index 00000000..e610db0b --- /dev/null +++ b/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.d @@ -0,0 +1,84 @@ +USB_DEVICE/App/usbd_desc.o: ../USB_DEVICE/App/usbd_desc.c \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + ../USB_DEVICE/App/usbd_desc.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +../USB_DEVICE/App/usbd_desc.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: diff --git a/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.o b/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.o new file mode 100644 index 00000000..2d879c9c Binary files /dev/null and b/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.o differ diff --git a/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.su b/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.su new file mode 100644 index 00000000..3e298ea6 --- /dev/null +++ b/firmware/numpad/Release/USB_DEVICE/App/usbd_desc.su @@ -0,0 +1,9 @@ +../USB_DEVICE/App/usbd_desc.c:258:11:USBD_FS_DeviceDescriptor 0 static +../USB_DEVICE/App/usbd_desc.c:271:11:USBD_FS_LangIDStrDescriptor 0 static +../USB_DEVICE/App/usbd_desc.c:375:11:USBD_FS_USR_BOSDescriptor 0 static +../USB_DEVICE/App/usbd_desc.c:414:13:IntToUnicode 16 static +../USB_DEVICE/App/usbd_desc.c:316:11:USBD_FS_SerialStrDescriptor 8 static +../USB_DEVICE/App/usbd_desc.c:303:11:USBD_FS_ManufacturerStrDescriptor 8 static +../USB_DEVICE/App/usbd_desc.c:284:11:USBD_FS_ProductStrDescriptor 8 static +../USB_DEVICE/App/usbd_desc.c:336:11:USBD_FS_ConfigStrDescriptor 8 static +../USB_DEVICE/App/usbd_desc.c:355:11:USBD_FS_InterfaceStrDescriptor 8 static diff --git a/firmware/numpad/Release/USB_DEVICE/Target/subdir.mk b/firmware/numpad/Release/USB_DEVICE/Target/subdir.mk new file mode 100644 index 00000000..9f55130b --- /dev/null +++ b/firmware/numpad/Release/USB_DEVICE/Target/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../USB_DEVICE/Target/usbd_conf.c + +OBJS += \ +./USB_DEVICE/Target/usbd_conf.o + +C_DEPS += \ +./USB_DEVICE/Target/usbd_conf.d + + +# Each subdirectory must supply rules for building sources it contributes +USB_DEVICE/Target/%.o USB_DEVICE/Target/%.su USB_DEVICE/Target/%.cyclo: ../USB_DEVICE/Target/%.c USB_DEVICE/Target/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-USB_DEVICE-2f-Target + +clean-USB_DEVICE-2f-Target: + -$(RM) ./USB_DEVICE/Target/usbd_conf.cyclo ./USB_DEVICE/Target/usbd_conf.d ./USB_DEVICE/Target/usbd_conf.o ./USB_DEVICE/Target/usbd_conf.su + +.PHONY: clean-USB_DEVICE-2f-Target + diff --git a/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.cyclo b/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.cyclo new file mode 100644 index 00000000..01f51e43 --- /dev/null +++ b/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.cyclo @@ -0,0 +1,32 @@ +../USB_DEVICE/Target/usbd_conf.c:69:6:HAL_PCD_MspInit 3 +../USB_DEVICE/Target/usbd_conf.c:112:6:HAL_PCD_MspDeInit 2 +../USB_DEVICE/Target/usbd_conf.c:145:6:HAL_PCD_SetupStageCallback 1 +../USB_DEVICE/Target/usbd_conf.c:160:6:HAL_PCD_DataOutStageCallback 1 +../USB_DEVICE/Target/usbd_conf.c:175:6:HAL_PCD_DataInStageCallback 1 +../USB_DEVICE/Target/usbd_conf.c:189:6:HAL_PCD_SOFCallback 1 +../USB_DEVICE/Target/usbd_conf.c:203:6:HAL_PCD_ResetCallback 3 +../USB_DEVICE/Target/usbd_conf.c:236:6:HAL_PCD_SuspendCallback 2 +../USB_DEVICE/Target/usbd_conf.c:261:6:HAL_PCD_ResumeCallback 1 +../USB_DEVICE/Target/usbd_conf.c:279:6:HAL_PCD_ISOOUTIncompleteCallback 1 +../USB_DEVICE/Target/usbd_conf.c:294:6:HAL_PCD_ISOINIncompleteCallback 1 +../USB_DEVICE/Target/usbd_conf.c:308:6:HAL_PCD_ConnectCallback 1 +../USB_DEVICE/Target/usbd_conf.c:322:6:HAL_PCD_DisconnectCallback 1 +../USB_DEVICE/Target/usbd_conf.c:337:20:USBD_LL_Init 3 +../USB_DEVICE/Target/usbd_conf.c:531:9:USBD_LL_IsStallEP 2 +../USB_DEVICE/Target/usbd_conf.c:609:10:USBD_LL_GetRxDataSize 1 +../USB_DEVICE/Target/usbd_conf.c:620:6:HAL_PCDEx_LPM_Callback 5 +../USB_DEVICE/Target/usbd_conf.c:671:7:USBD_static_malloc 1 +../USB_DEVICE/Target/usbd_conf.c:682:6:USBD_static_free 1 +../USB_DEVICE/Target/usbd_conf.c:692:6:USBD_LL_Delay 1 +../USB_DEVICE/Target/usbd_conf.c:702:20:USBD_Get_USB_Status 2 +../USB_DEVICE/Target/usbd_conf.c:387:20:USBD_LL_DeInit 1 +../USB_DEVICE/Target/usbd_conf.c:404:20:USBD_LL_Start 1 +../USB_DEVICE/Target/usbd_conf.c:421:20:USBD_LL_Stop 1 +../USB_DEVICE/Target/usbd_conf.c:441:20:USBD_LL_OpenEP 1 +../USB_DEVICE/Target/usbd_conf.c:459:20:USBD_LL_CloseEP 1 +../USB_DEVICE/Target/usbd_conf.c:477:20:USBD_LL_FlushEP 1 +../USB_DEVICE/Target/usbd_conf.c:495:20:USBD_LL_StallEP 1 +../USB_DEVICE/Target/usbd_conf.c:513:20:USBD_LL_ClearStallEP 1 +../USB_DEVICE/Target/usbd_conf.c:551:20:USBD_LL_SetUSBAddress 1 +../USB_DEVICE/Target/usbd_conf.c:571:20:USBD_LL_Transmit 1 +../USB_DEVICE/Target/usbd_conf.c:591:20:USBD_LL_PrepareReceive 1 diff --git a/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.d b/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.d new file mode 100644 index 00000000..5fb644c5 --- /dev/null +++ b/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.d @@ -0,0 +1,86 @@ +USB_DEVICE/Target/usbd_conf.o: ../USB_DEVICE/Target/usbd_conf.c \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: diff --git a/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.o b/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.o new file mode 100644 index 00000000..ef263190 Binary files /dev/null and b/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.o differ diff --git a/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.su b/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.su new file mode 100644 index 00000000..00773c1e --- /dev/null +++ b/firmware/numpad/Release/USB_DEVICE/Target/usbd_conf.su @@ -0,0 +1,32 @@ +../USB_DEVICE/Target/usbd_conf.c:69:6:HAL_PCD_MspInit 136 static +../USB_DEVICE/Target/usbd_conf.c:112:6:HAL_PCD_MspDeInit 8 static +../USB_DEVICE/Target/usbd_conf.c:145:6:HAL_PCD_SetupStageCallback 0 static +../USB_DEVICE/Target/usbd_conf.c:160:6:HAL_PCD_DataOutStageCallback 0 static +../USB_DEVICE/Target/usbd_conf.c:175:6:HAL_PCD_DataInStageCallback 0 static +../USB_DEVICE/Target/usbd_conf.c:189:6:HAL_PCD_SOFCallback 0 static +../USB_DEVICE/Target/usbd_conf.c:203:6:HAL_PCD_ResetCallback 8 static +../USB_DEVICE/Target/usbd_conf.c:236:6:HAL_PCD_SuspendCallback 8 static +../USB_DEVICE/Target/usbd_conf.c:261:6:HAL_PCD_ResumeCallback 0 static +../USB_DEVICE/Target/usbd_conf.c:279:6:HAL_PCD_ISOOUTIncompleteCallback 0 static +../USB_DEVICE/Target/usbd_conf.c:294:6:HAL_PCD_ISOINIncompleteCallback 0 static +../USB_DEVICE/Target/usbd_conf.c:308:6:HAL_PCD_ConnectCallback 0 static +../USB_DEVICE/Target/usbd_conf.c:322:6:HAL_PCD_DisconnectCallback 0 static +../USB_DEVICE/Target/usbd_conf.c:337:20:USBD_LL_Init 8 static +../USB_DEVICE/Target/usbd_conf.c:531:9:USBD_LL_IsStallEP 0 static +../USB_DEVICE/Target/usbd_conf.c:609:10:USBD_LL_GetRxDataSize 0 static +../USB_DEVICE/Target/usbd_conf.c:620:6:HAL_PCDEx_LPM_Callback 8 static +../USB_DEVICE/Target/usbd_conf.c:671:7:USBD_static_malloc 0 static +../USB_DEVICE/Target/usbd_conf.c:682:6:USBD_static_free 0 static +../USB_DEVICE/Target/usbd_conf.c:692:6:USBD_LL_Delay 0 static +../USB_DEVICE/Target/usbd_conf.c:702:20:USBD_Get_USB_Status 0 static +../USB_DEVICE/Target/usbd_conf.c:387:20:USBD_LL_DeInit 8 static +../USB_DEVICE/Target/usbd_conf.c:404:20:USBD_LL_Start 8 static +../USB_DEVICE/Target/usbd_conf.c:421:20:USBD_LL_Stop 8 static +../USB_DEVICE/Target/usbd_conf.c:441:20:USBD_LL_OpenEP 8 static +../USB_DEVICE/Target/usbd_conf.c:459:20:USBD_LL_CloseEP 8 static +../USB_DEVICE/Target/usbd_conf.c:477:20:USBD_LL_FlushEP 8 static +../USB_DEVICE/Target/usbd_conf.c:495:20:USBD_LL_StallEP 8 static +../USB_DEVICE/Target/usbd_conf.c:513:20:USBD_LL_ClearStallEP 8 static +../USB_DEVICE/Target/usbd_conf.c:551:20:USBD_LL_SetUSBAddress 8 static +../USB_DEVICE/Target/usbd_conf.c:571:20:USBD_LL_Transmit 8 static +../USB_DEVICE/Target/usbd_conf.c:591:20:USBD_LL_PrepareReceive 8 static diff --git a/firmware/numpad/Release/makefile b/firmware/numpad/Release/makefile new file mode 100644 index 00000000..d7889bf9 --- /dev/null +++ b/firmware/numpad/Release/makefile @@ -0,0 +1,98 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include USB_DEVICE/Target/subdir.mk +-include USB_DEVICE/App/subdir.mk +-include Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk +-include Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk +-include Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := modularkbd +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +modularkbd.elf \ + +MAP_FILES += \ +modularkbd.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +modularkbd.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: modularkbd.elf secondary-outputs + +# Tool invocations +modularkbd.elf modularkbd.map: $(OBJS) $(USER_OBJS) /home/ukim/Projects/modular-kbd/firmware/stm32cubeide_workspace/modularkbd/STM32F446RETX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "modularkbd.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"/home/ukim/Projects/modular-kbd/firmware/stm32cubeide_workspace/modularkbd/STM32F446RETX_FLASH.ld" --specs=nosys.specs -Wl,-Map="modularkbd.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +modularkbd.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "modularkbd.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) default.size.stdout modularkbd.elf modularkbd.list modularkbd.map + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/firmware/numpad/Release/modularkbd.elf b/firmware/numpad/Release/modularkbd.elf new file mode 100755 index 00000000..32e106d1 Binary files /dev/null and b/firmware/numpad/Release/modularkbd.elf differ diff --git a/firmware/numpad/Release/modularkbd.list b/firmware/numpad/Release/modularkbd.list new file mode 100644 index 00000000..baee7d80 --- /dev/null +++ b/firmware/numpad/Release/modularkbd.list @@ -0,0 +1,5636 @@ + +modularkbd.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000001c4 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00003718 080001c4 080001c4 000011c4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000044 080038dc 080038dc 000048dc 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08003920 08003920 00005120 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 08003920 08003920 00004920 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08003928 08003928 00005120 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08003928 08003928 00004928 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 0800392c 0800392c 0000492c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 00000120 20000000 08003930 00005000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000a00 20000120 08003a50 00005120 2**2 + ALLOC + 10 ._user_heap_stack 00000600 20000b20 08003a50 00005b20 2**0 + ALLOC + 11 .ARM.attributes 00000030 00000000 00000000 00005120 2**0 + CONTENTS, READONLY + 12 .comment 00000043 00000000 00000000 00005150 2**0 + CONTENTS, READONLY + 13 .debug_frame 000000ac 00000000 00000000 00005194 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080001c4 <__do_global_dtors_aux>: + 80001c4: b510 push {r4, lr} + 80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>) + 80001c8: 7823 ldrb r3, [r4, #0] + 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> + 80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>) + 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> + 80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>) + 80001d2: f3af 8000 nop.w + 80001d6: 2301 movs r3, #1 + 80001d8: 7023 strb r3, [r4, #0] + 80001da: bd10 pop {r4, pc} + 80001dc: 20000120 .word 0x20000120 + 80001e0: 00000000 .word 0x00000000 + 80001e4: 080038c4 .word 0x080038c4 + +080001e8 : + 80001e8: b508 push {r3, lr} + 80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 ) + 80001ec: b11b cbz r3, 80001f6 + 80001ee: 4903 ldr r1, [pc, #12] @ (80001fc ) + 80001f0: 4803 ldr r0, [pc, #12] @ (8000200 ) + 80001f2: f3af 8000 nop.w + 80001f6: bd08 pop {r3, pc} + 80001f8: 00000000 .word 0x00000000 + 80001fc: 20000124 .word 0x20000124 + 8000200: 080038c4 .word 0x080038c4 + +08000204 : + 8000204: 4603 mov r3, r0 + 8000206: f813 2b01 ldrb.w r2, [r3], #1 + 800020a: 2a00 cmp r2, #0 + 800020c: d1fb bne.n 8000206 + 800020e: 1a18 subs r0, r3, r0 + 8000210: 3801 subs r0, #1 + 8000212: 4770 bx lr + +08000214 <__aeabi_uldivmod>: + 8000214: b953 cbnz r3, 800022c <__aeabi_uldivmod+0x18> + 8000216: b94a cbnz r2, 800022c <__aeabi_uldivmod+0x18> + 8000218: 2900 cmp r1, #0 + 800021a: bf08 it eq + 800021c: 2800 cmpeq r0, #0 + 800021e: bf1c itt ne + 8000220: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 8000224: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8000228: f000 b988 b.w 800053c <__aeabi_idiv0> + 800022c: f1ad 0c08 sub.w ip, sp, #8 + 8000230: e96d ce04 strd ip, lr, [sp, #-16]! + 8000234: f000 f806 bl 8000244 <__udivmoddi4> + 8000238: f8dd e004 ldr.w lr, [sp, #4] + 800023c: e9dd 2302 ldrd r2, r3, [sp, #8] + 8000240: b004 add sp, #16 + 8000242: 4770 bx lr + +08000244 <__udivmoddi4>: + 8000244: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8000248: 9d08 ldr r5, [sp, #32] + 800024a: 468e mov lr, r1 + 800024c: 4604 mov r4, r0 + 800024e: 4688 mov r8, r1 + 8000250: 2b00 cmp r3, #0 + 8000252: d14a bne.n 80002ea <__udivmoddi4+0xa6> + 8000254: 428a cmp r2, r1 + 8000256: 4617 mov r7, r2 + 8000258: d962 bls.n 8000320 <__udivmoddi4+0xdc> + 800025a: fab2 f682 clz r6, r2 + 800025e: b14e cbz r6, 8000274 <__udivmoddi4+0x30> + 8000260: f1c6 0320 rsb r3, r6, #32 + 8000264: fa01 f806 lsl.w r8, r1, r6 + 8000268: fa20 f303 lsr.w r3, r0, r3 + 800026c: 40b7 lsls r7, r6 + 800026e: ea43 0808 orr.w r8, r3, r8 + 8000272: 40b4 lsls r4, r6 + 8000274: ea4f 4e17 mov.w lr, r7, lsr #16 + 8000278: fa1f fc87 uxth.w ip, r7 + 800027c: fbb8 f1fe udiv r1, r8, lr + 8000280: 0c23 lsrs r3, r4, #16 + 8000282: fb0e 8811 mls r8, lr, r1, r8 + 8000286: ea43 4308 orr.w r3, r3, r8, lsl #16 + 800028a: fb01 f20c mul.w r2, r1, ip + 800028e: 429a cmp r2, r3 + 8000290: d909 bls.n 80002a6 <__udivmoddi4+0x62> + 8000292: 18fb adds r3, r7, r3 + 8000294: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8000298: f080 80ea bcs.w 8000470 <__udivmoddi4+0x22c> + 800029c: 429a cmp r2, r3 + 800029e: f240 80e7 bls.w 8000470 <__udivmoddi4+0x22c> + 80002a2: 3902 subs r1, #2 + 80002a4: 443b add r3, r7 + 80002a6: 1a9a subs r2, r3, r2 + 80002a8: b2a3 uxth r3, r4 + 80002aa: fbb2 f0fe udiv r0, r2, lr + 80002ae: fb0e 2210 mls r2, lr, r0, r2 + 80002b2: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002b6: fb00 fc0c mul.w ip, r0, ip + 80002ba: 459c cmp ip, r3 + 80002bc: d909 bls.n 80002d2 <__udivmoddi4+0x8e> + 80002be: 18fb adds r3, r7, r3 + 80002c0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 80002c4: f080 80d6 bcs.w 8000474 <__udivmoddi4+0x230> + 80002c8: 459c cmp ip, r3 + 80002ca: f240 80d3 bls.w 8000474 <__udivmoddi4+0x230> + 80002ce: 443b add r3, r7 + 80002d0: 3802 subs r0, #2 + 80002d2: ea40 4001 orr.w r0, r0, r1, lsl #16 + 80002d6: eba3 030c sub.w r3, r3, ip + 80002da: 2100 movs r1, #0 + 80002dc: b11d cbz r5, 80002e6 <__udivmoddi4+0xa2> + 80002de: 40f3 lsrs r3, r6 + 80002e0: 2200 movs r2, #0 + 80002e2: e9c5 3200 strd r3, r2, [r5] + 80002e6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 80002ea: 428b cmp r3, r1 + 80002ec: d905 bls.n 80002fa <__udivmoddi4+0xb6> + 80002ee: b10d cbz r5, 80002f4 <__udivmoddi4+0xb0> + 80002f0: e9c5 0100 strd r0, r1, [r5] + 80002f4: 2100 movs r1, #0 + 80002f6: 4608 mov r0, r1 + 80002f8: e7f5 b.n 80002e6 <__udivmoddi4+0xa2> + 80002fa: fab3 f183 clz r1, r3 + 80002fe: 2900 cmp r1, #0 + 8000300: d146 bne.n 8000390 <__udivmoddi4+0x14c> + 8000302: 4573 cmp r3, lr + 8000304: d302 bcc.n 800030c <__udivmoddi4+0xc8> + 8000306: 4282 cmp r2, r0 + 8000308: f200 8105 bhi.w 8000516 <__udivmoddi4+0x2d2> + 800030c: 1a84 subs r4, r0, r2 + 800030e: eb6e 0203 sbc.w r2, lr, r3 + 8000312: 2001 movs r0, #1 + 8000314: 4690 mov r8, r2 + 8000316: 2d00 cmp r5, #0 + 8000318: d0e5 beq.n 80002e6 <__udivmoddi4+0xa2> + 800031a: e9c5 4800 strd r4, r8, [r5] + 800031e: e7e2 b.n 80002e6 <__udivmoddi4+0xa2> + 8000320: 2a00 cmp r2, #0 + 8000322: f000 8090 beq.w 8000446 <__udivmoddi4+0x202> + 8000326: fab2 f682 clz r6, r2 + 800032a: 2e00 cmp r6, #0 + 800032c: f040 80a4 bne.w 8000478 <__udivmoddi4+0x234> + 8000330: 1a8a subs r2, r1, r2 + 8000332: 0c03 lsrs r3, r0, #16 + 8000334: ea4f 4e17 mov.w lr, r7, lsr #16 + 8000338: b280 uxth r0, r0 + 800033a: b2bc uxth r4, r7 + 800033c: 2101 movs r1, #1 + 800033e: fbb2 fcfe udiv ip, r2, lr + 8000342: fb0e 221c mls r2, lr, ip, r2 + 8000346: ea43 4302 orr.w r3, r3, r2, lsl #16 + 800034a: fb04 f20c mul.w r2, r4, ip + 800034e: 429a cmp r2, r3 + 8000350: d907 bls.n 8000362 <__udivmoddi4+0x11e> + 8000352: 18fb adds r3, r7, r3 + 8000354: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 8000358: d202 bcs.n 8000360 <__udivmoddi4+0x11c> + 800035a: 429a cmp r2, r3 + 800035c: f200 80e0 bhi.w 8000520 <__udivmoddi4+0x2dc> + 8000360: 46c4 mov ip, r8 + 8000362: 1a9b subs r3, r3, r2 + 8000364: fbb3 f2fe udiv r2, r3, lr + 8000368: fb0e 3312 mls r3, lr, r2, r3 + 800036c: ea40 4303 orr.w r3, r0, r3, lsl #16 + 8000370: fb02 f404 mul.w r4, r2, r4 + 8000374: 429c cmp r4, r3 + 8000376: d907 bls.n 8000388 <__udivmoddi4+0x144> + 8000378: 18fb adds r3, r7, r3 + 800037a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 800037e: d202 bcs.n 8000386 <__udivmoddi4+0x142> + 8000380: 429c cmp r4, r3 + 8000382: f200 80ca bhi.w 800051a <__udivmoddi4+0x2d6> + 8000386: 4602 mov r2, r0 + 8000388: 1b1b subs r3, r3, r4 + 800038a: ea42 400c orr.w r0, r2, ip, lsl #16 + 800038e: e7a5 b.n 80002dc <__udivmoddi4+0x98> + 8000390: f1c1 0620 rsb r6, r1, #32 + 8000394: 408b lsls r3, r1 + 8000396: fa22 f706 lsr.w r7, r2, r6 + 800039a: 431f orrs r7, r3 + 800039c: fa0e f401 lsl.w r4, lr, r1 + 80003a0: fa20 f306 lsr.w r3, r0, r6 + 80003a4: fa2e fe06 lsr.w lr, lr, r6 + 80003a8: ea4f 4917 mov.w r9, r7, lsr #16 + 80003ac: 4323 orrs r3, r4 + 80003ae: fa00 f801 lsl.w r8, r0, r1 + 80003b2: fa1f fc87 uxth.w ip, r7 + 80003b6: fbbe f0f9 udiv r0, lr, r9 + 80003ba: 0c1c lsrs r4, r3, #16 + 80003bc: fb09 ee10 mls lr, r9, r0, lr + 80003c0: ea44 440e orr.w r4, r4, lr, lsl #16 + 80003c4: fb00 fe0c mul.w lr, r0, ip + 80003c8: 45a6 cmp lr, r4 + 80003ca: fa02 f201 lsl.w r2, r2, r1 + 80003ce: d909 bls.n 80003e4 <__udivmoddi4+0x1a0> + 80003d0: 193c adds r4, r7, r4 + 80003d2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff + 80003d6: f080 809c bcs.w 8000512 <__udivmoddi4+0x2ce> + 80003da: 45a6 cmp lr, r4 + 80003dc: f240 8099 bls.w 8000512 <__udivmoddi4+0x2ce> + 80003e0: 3802 subs r0, #2 + 80003e2: 443c add r4, r7 + 80003e4: eba4 040e sub.w r4, r4, lr + 80003e8: fa1f fe83 uxth.w lr, r3 + 80003ec: fbb4 f3f9 udiv r3, r4, r9 + 80003f0: fb09 4413 mls r4, r9, r3, r4 + 80003f4: ea4e 4404 orr.w r4, lr, r4, lsl #16 + 80003f8: fb03 fc0c mul.w ip, r3, ip + 80003fc: 45a4 cmp ip, r4 + 80003fe: d908 bls.n 8000412 <__udivmoddi4+0x1ce> + 8000400: 193c adds r4, r7, r4 + 8000402: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff + 8000406: f080 8082 bcs.w 800050e <__udivmoddi4+0x2ca> + 800040a: 45a4 cmp ip, r4 + 800040c: d97f bls.n 800050e <__udivmoddi4+0x2ca> + 800040e: 3b02 subs r3, #2 + 8000410: 443c add r4, r7 + 8000412: ea43 4000 orr.w r0, r3, r0, lsl #16 + 8000416: eba4 040c sub.w r4, r4, ip + 800041a: fba0 ec02 umull lr, ip, r0, r2 + 800041e: 4564 cmp r4, ip + 8000420: 4673 mov r3, lr + 8000422: 46e1 mov r9, ip + 8000424: d362 bcc.n 80004ec <__udivmoddi4+0x2a8> + 8000426: d05f beq.n 80004e8 <__udivmoddi4+0x2a4> + 8000428: b15d cbz r5, 8000442 <__udivmoddi4+0x1fe> + 800042a: ebb8 0203 subs.w r2, r8, r3 + 800042e: eb64 0409 sbc.w r4, r4, r9 + 8000432: fa04 f606 lsl.w r6, r4, r6 + 8000436: fa22 f301 lsr.w r3, r2, r1 + 800043a: 431e orrs r6, r3 + 800043c: 40cc lsrs r4, r1 + 800043e: e9c5 6400 strd r6, r4, [r5] + 8000442: 2100 movs r1, #0 + 8000444: e74f b.n 80002e6 <__udivmoddi4+0xa2> + 8000446: fbb1 fcf2 udiv ip, r1, r2 + 800044a: 0c01 lsrs r1, r0, #16 + 800044c: ea41 410e orr.w r1, r1, lr, lsl #16 + 8000450: b280 uxth r0, r0 + 8000452: ea40 4201 orr.w r2, r0, r1, lsl #16 + 8000456: 463b mov r3, r7 + 8000458: 4638 mov r0, r7 + 800045a: 463c mov r4, r7 + 800045c: 46b8 mov r8, r7 + 800045e: 46be mov lr, r7 + 8000460: 2620 movs r6, #32 + 8000462: fbb1 f1f7 udiv r1, r1, r7 + 8000466: eba2 0208 sub.w r2, r2, r8 + 800046a: ea41 410c orr.w r1, r1, ip, lsl #16 + 800046e: e766 b.n 800033e <__udivmoddi4+0xfa> + 8000470: 4601 mov r1, r0 + 8000472: e718 b.n 80002a6 <__udivmoddi4+0x62> + 8000474: 4610 mov r0, r2 + 8000476: e72c b.n 80002d2 <__udivmoddi4+0x8e> + 8000478: f1c6 0220 rsb r2, r6, #32 + 800047c: fa2e f302 lsr.w r3, lr, r2 + 8000480: 40b7 lsls r7, r6 + 8000482: 40b1 lsls r1, r6 + 8000484: fa20 f202 lsr.w r2, r0, r2 + 8000488: ea4f 4e17 mov.w lr, r7, lsr #16 + 800048c: 430a orrs r2, r1 + 800048e: fbb3 f8fe udiv r8, r3, lr + 8000492: b2bc uxth r4, r7 + 8000494: fb0e 3318 mls r3, lr, r8, r3 + 8000498: 0c11 lsrs r1, r2, #16 + 800049a: ea41 4103 orr.w r1, r1, r3, lsl #16 + 800049e: fb08 f904 mul.w r9, r8, r4 + 80004a2: 40b0 lsls r0, r6 + 80004a4: 4589 cmp r9, r1 + 80004a6: ea4f 4310 mov.w r3, r0, lsr #16 + 80004aa: b280 uxth r0, r0 + 80004ac: d93e bls.n 800052c <__udivmoddi4+0x2e8> + 80004ae: 1879 adds r1, r7, r1 + 80004b0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 80004b4: d201 bcs.n 80004ba <__udivmoddi4+0x276> + 80004b6: 4589 cmp r9, r1 + 80004b8: d81f bhi.n 80004fa <__udivmoddi4+0x2b6> + 80004ba: eba1 0109 sub.w r1, r1, r9 + 80004be: fbb1 f9fe udiv r9, r1, lr + 80004c2: fb09 f804 mul.w r8, r9, r4 + 80004c6: fb0e 1119 mls r1, lr, r9, r1 + 80004ca: b292 uxth r2, r2 + 80004cc: ea42 4201 orr.w r2, r2, r1, lsl #16 + 80004d0: 4542 cmp r2, r8 + 80004d2: d229 bcs.n 8000528 <__udivmoddi4+0x2e4> + 80004d4: 18ba adds r2, r7, r2 + 80004d6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 80004da: d2c4 bcs.n 8000466 <__udivmoddi4+0x222> + 80004dc: 4542 cmp r2, r8 + 80004de: d2c2 bcs.n 8000466 <__udivmoddi4+0x222> + 80004e0: f1a9 0102 sub.w r1, r9, #2 + 80004e4: 443a add r2, r7 + 80004e6: e7be b.n 8000466 <__udivmoddi4+0x222> + 80004e8: 45f0 cmp r8, lr + 80004ea: d29d bcs.n 8000428 <__udivmoddi4+0x1e4> + 80004ec: ebbe 0302 subs.w r3, lr, r2 + 80004f0: eb6c 0c07 sbc.w ip, ip, r7 + 80004f4: 3801 subs r0, #1 + 80004f6: 46e1 mov r9, ip + 80004f8: e796 b.n 8000428 <__udivmoddi4+0x1e4> + 80004fa: eba7 0909 sub.w r9, r7, r9 + 80004fe: 4449 add r1, r9 + 8000500: f1a8 0c02 sub.w ip, r8, #2 + 8000504: fbb1 f9fe udiv r9, r1, lr + 8000508: fb09 f804 mul.w r8, r9, r4 + 800050c: e7db b.n 80004c6 <__udivmoddi4+0x282> + 800050e: 4673 mov r3, lr + 8000510: e77f b.n 8000412 <__udivmoddi4+0x1ce> + 8000512: 4650 mov r0, sl + 8000514: e766 b.n 80003e4 <__udivmoddi4+0x1a0> + 8000516: 4608 mov r0, r1 + 8000518: e6fd b.n 8000316 <__udivmoddi4+0xd2> + 800051a: 443b add r3, r7 + 800051c: 3a02 subs r2, #2 + 800051e: e733 b.n 8000388 <__udivmoddi4+0x144> + 8000520: f1ac 0c02 sub.w ip, ip, #2 + 8000524: 443b add r3, r7 + 8000526: e71c b.n 8000362 <__udivmoddi4+0x11e> + 8000528: 4649 mov r1, r9 + 800052a: e79c b.n 8000466 <__udivmoddi4+0x222> + 800052c: eba1 0109 sub.w r1, r1, r9 + 8000530: 46c4 mov ip, r8 + 8000532: fbb1 f9fe udiv r9, r1, lr + 8000536: fb09 f804 mul.w r8, r9, r4 + 800053a: e7c4 b.n 80004c6 <__udivmoddi4+0x282> + +0800053c <__aeabi_idiv0>: + 800053c: 4770 bx lr + 800053e: bf00 nop + +08000540 : + 8000540: b500 push {lr} + 8000542: b095 sub sp, #84 @ 0x54 + 8000544: 2214 movs r2, #20 + 8000546: 2100 movs r1, #0 + 8000548: a808 add r0, sp, #32 + 800054a: f003 f98f bl 800386c + 800054e: 2214 movs r2, #20 + 8000550: 2100 movs r1, #0 + 8000552: a802 add r0, sp, #8 + 8000554: f003 f98a bl 800386c + 8000558: 4b20 ldr r3, [pc, #128] @ (80005dc ) + 800055a: 2100 movs r1, #0 + 800055c: 9100 str r1, [sp, #0] + 800055e: 6c1a ldr r2, [r3, #64] @ 0x40 + 8000560: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 + 8000564: 641a str r2, [r3, #64] @ 0x40 + 8000566: 6c1b ldr r3, [r3, #64] @ 0x40 + 8000568: 4a1d ldr r2, [pc, #116] @ (80005e0 ) + 800056a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800056e: 9300 str r3, [sp, #0] + 8000570: 9b00 ldr r3, [sp, #0] + 8000572: 9101 str r1, [sp, #4] + 8000574: 6813 ldr r3, [r2, #0] + 8000576: f423 4340 bic.w r3, r3, #49152 @ 0xc000 + 800057a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 800057e: 6013 str r3, [r2, #0] + 8000580: 6813 ldr r3, [r2, #0] + 8000582: 2101 movs r1, #1 + 8000584: f403 4340 and.w r3, r3, #49152 @ 0xc000 + 8000588: 2210 movs r2, #16 + 800058a: e9cd 120a strd r1, r2, [sp, #40] @ 0x28 + 800058e: 9301 str r3, [sp, #4] + 8000590: f44f 0080 mov.w r0, #4194304 @ 0x400000 + 8000594: 2204 movs r2, #4 + 8000596: e9cd 020e strd r0, r2, [sp, #56] @ 0x38 + 800059a: 9b01 ldr r3, [sp, #4] + 800059c: 2248 movs r2, #72 @ 0x48 + 800059e: 2302 movs r3, #2 + 80005a0: e9cd 2310 strd r2, r3, [sp, #64] @ 0x40 + 80005a4: a807 add r0, sp, #28 + 80005a6: 2203 movs r2, #3 + 80005a8: e9cd 2312 strd r2, r3, [sp, #72] @ 0x48 + 80005ac: 9307 str r3, [sp, #28] + 80005ae: 930d str r3, [sp, #52] @ 0x34 + 80005b0: f001 fb02 bl 8001bb8 + 80005b4: 4601 mov r1, r0 + 80005b6: b108 cbz r0, 80005bc + 80005b8: b672 cpsid i + 80005ba: e7fe b.n 80005ba + 80005bc: 230f movs r3, #15 + 80005be: e9cd 3002 strd r3, r0, [sp, #8] + 80005c2: e9cd 0004 strd r0, r0, [sp, #16] + 80005c6: 9006 str r0, [sp, #24] + 80005c8: a802 add r0, sp, #8 + 80005ca: f001 f803 bl 80015d4 + 80005ce: b108 cbz r0, 80005d4 + 80005d0: b672 cpsid i + 80005d2: e7fe b.n 80005d2 + 80005d4: b015 add sp, #84 @ 0x54 + 80005d6: f85d fb04 ldr.w pc, [sp], #4 + 80005da: bf00 nop + 80005dc: 40023800 .word 0x40023800 + 80005e0: 40007000 .word 0x40007000 + +080005e4
: + 80005e4: b500 push {lr} + 80005e6: b08b sub sp, #44 @ 0x2c + 80005e8: f000 f918 bl 800081c + 80005ec: f7ff ffa8 bl 8000540 + 80005f0: 2032 movs r0, #50 @ 0x32 + 80005f2: f000 f93f bl 8000874 + 80005f6: 2214 movs r2, #20 + 80005f8: 2100 movs r1, #0 + 80005fa: eb0d 0002 add.w r0, sp, r2 + 80005fe: f003 f935 bl 800386c + 8000602: 2400 movs r4, #0 + 8000604: 4b3c ldr r3, [pc, #240] @ (80006f8 ) + 8000606: 9400 str r4, [sp, #0] + 8000608: 6b1a ldr r2, [r3, #48] @ 0x30 + 800060a: 483c ldr r0, [pc, #240] @ (80006fc ) + 800060c: f042 0280 orr.w r2, r2, #128 @ 0x80 + 8000610: 631a str r2, [r3, #48] @ 0x30 + 8000612: 6b1a ldr r2, [r3, #48] @ 0x30 + 8000614: f002 0280 and.w r2, r2, #128 @ 0x80 + 8000618: 9200 str r2, [sp, #0] + 800061a: 9a00 ldr r2, [sp, #0] + 800061c: 9401 str r4, [sp, #4] + 800061e: 6b1a ldr r2, [r3, #48] @ 0x30 + 8000620: f042 0201 orr.w r2, r2, #1 + 8000624: 631a str r2, [r3, #48] @ 0x30 + 8000626: 6b1a ldr r2, [r3, #48] @ 0x30 + 8000628: f002 0201 and.w r2, r2, #1 + 800062c: 9201 str r2, [sp, #4] + 800062e: 9a01 ldr r2, [sp, #4] + 8000630: 9402 str r4, [sp, #8] + 8000632: 6b1a ldr r2, [r3, #48] @ 0x30 + 8000634: f042 0204 orr.w r2, r2, #4 + 8000638: 631a str r2, [r3, #48] @ 0x30 + 800063a: 6b1a ldr r2, [r3, #48] @ 0x30 + 800063c: f002 0204 and.w r2, r2, #4 + 8000640: 9202 str r2, [sp, #8] + 8000642: 9a02 ldr r2, [sp, #8] + 8000644: 9403 str r4, [sp, #12] + 8000646: 6b1a ldr r2, [r3, #48] @ 0x30 + 8000648: f042 0202 orr.w r2, r2, #2 + 800064c: 631a str r2, [r3, #48] @ 0x30 + 800064e: 6b1a ldr r2, [r3, #48] @ 0x30 + 8000650: f002 0202 and.w r2, r2, #2 + 8000654: 9203 str r2, [sp, #12] + 8000656: 9a03 ldr r2, [sp, #12] + 8000658: 9404 str r4, [sp, #16] + 800065a: 6b1a ldr r2, [r3, #48] @ 0x30 + 800065c: f042 0208 orr.w r2, r2, #8 + 8000660: 631a str r2, [r3, #48] @ 0x30 + 8000662: 6b1b ldr r3, [r3, #48] @ 0x30 + 8000664: f003 0308 and.w r3, r3, #8 + 8000668: 4622 mov r2, r4 + 800066a: 9304 str r3, [sp, #16] + 800066c: f44f 7170 mov.w r1, #960 @ 0x3c0 + 8000670: 9b04 ldr r3, [sp, #16] + 8000672: f000 fa4b bl 8000b0c + 8000676: 4622 mov r2, r4 + 8000678: 4821 ldr r0, [pc, #132] @ (8000700 ) + 800067a: f44f 7180 mov.w r1, #256 @ 0x100 + 800067e: f000 fa45 bl 8000b0c + 8000682: 2330 movs r3, #48 @ 0x30 + 8000684: 481d ldr r0, [pc, #116] @ (80006fc ) + 8000686: 9407 str r4, [sp, #28] + 8000688: a905 add r1, sp, #20 + 800068a: e9cd 3405 strd r3, r4, [sp, #20] + 800068e: f000 f96b bl 8000968 + 8000692: f240 4307 movw r3, #1031 @ 0x407 + 8000696: 481b ldr r0, [pc, #108] @ (8000704 ) + 8000698: 9407 str r4, [sp, #28] + 800069a: a905 add r1, sp, #20 + 800069c: e9cd 3405 strd r3, r4, [sp, #20] + 80006a0: 2501 movs r5, #1 + 80006a2: f000 f961 bl 8000968 + 80006a6: f44f 7370 mov.w r3, #960 @ 0x3c0 + 80006aa: 4814 ldr r0, [pc, #80] @ (80006fc ) + 80006ac: a905 add r1, sp, #20 + 80006ae: e9cd 3505 strd r3, r5, [sp, #20] + 80006b2: e9cd 4407 strd r4, r4, [sp, #28] + 80006b6: f000 f957 bl 8000968 + 80006ba: f44f 7380 mov.w r3, #256 @ 0x100 + 80006be: 4810 ldr r0, [pc, #64] @ (8000700 ) + 80006c0: a905 add r1, sp, #20 + 80006c2: e9cd 3505 strd r3, r5, [sp, #20] + 80006c6: e9cd 4407 strd r4, r4, [sp, #28] + 80006ca: f000 f94d bl 8000968 + 80006ce: f002 febd bl 800344c + 80006d2: 2032 movs r0, #50 @ 0x32 + 80006d4: f000 f8ce bl 8000874 + 80006d8: 4c0b ldr r4, [pc, #44] @ (8000708 ) + 80006da: 4d0c ldr r5, [pc, #48] @ (800070c ) + 80006dc: f04f 0602 mov.w r6, #2 + 80006e0: 2304 movs r3, #4 + 80006e2: 4909 ldr r1, [pc, #36] @ (8000708 ) + 80006e4: 7026 strb r6, [r4, #0] + 80006e6: 2208 movs r2, #8 + 80006e8: 4628 mov r0, r5 + 80006ea: 70a3 strb r3, [r4, #2] + 80006ec: f002 fa34 bl 8002b58 + 80006f0: 2064 movs r0, #100 @ 0x64 + 80006f2: f000 f8bf bl 8000874 + 80006f6: e7f3 b.n 80006e0 + 80006f8: 40023800 .word 0x40023800 + 80006fc: 40020800 .word 0x40020800 + 8000700: 40020000 .word 0x40020000 + 8000704: 40020400 .word 0x40020400 + 8000708: 2000013c .word 0x2000013c + 800070c: 2000014c .word 0x2000014c + +08000710 : + 8000710: b672 cpsid i + 8000712: e7fe b.n 8000712 + +08000714 : + 8000714: b082 sub sp, #8 + 8000716: 4b0c ldr r3, [pc, #48] @ (8000748 ) + 8000718: 2100 movs r1, #0 + 800071a: 9100 str r1, [sp, #0] + 800071c: 6c5a ldr r2, [r3, #68] @ 0x44 + 800071e: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8000722: 645a str r2, [r3, #68] @ 0x44 + 8000724: 6c5a ldr r2, [r3, #68] @ 0x44 + 8000726: f402 4280 and.w r2, r2, #16384 @ 0x4000 + 800072a: 9200 str r2, [sp, #0] + 800072c: 9a00 ldr r2, [sp, #0] + 800072e: 9101 str r1, [sp, #4] + 8000730: 6c1a ldr r2, [r3, #64] @ 0x40 + 8000732: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 + 8000736: 641a str r2, [r3, #64] @ 0x40 + 8000738: 6c1b ldr r3, [r3, #64] @ 0x40 + 800073a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800073e: 9301 str r3, [sp, #4] + 8000740: 9b01 ldr r3, [sp, #4] + 8000742: b002 add sp, #8 + 8000744: 4770 bx lr + 8000746: bf00 nop + 8000748: 40023800 .word 0x40023800 + +0800074c : + 800074c: e7fe b.n 800074c + +0800074e : + 800074e: e7fe b.n 800074e + +08000750 : + 8000750: e7fe b.n 8000750 + +08000752 : + 8000752: e7fe b.n 8000752 + +08000754 : + 8000754: e7fe b.n 8000754 + +08000756 : + 8000756: 4770 bx lr + +08000758 : + 8000758: 4770 bx lr + +0800075a : + 800075a: 4770 bx lr + +0800075c : + 800075c: f000 b878 b.w 8000850 + +08000760 : + 8000760: 4801 ldr r0, [pc, #4] @ (8000768 ) + 8000762: f000 bb9b b.w 8000e9c + 8000766: bf00 nop + 8000768: 2000063c .word 0x2000063c + +0800076c : + 800076c: 4a03 ldr r2, [pc, #12] @ (800077c ) + 800076e: f8d2 3088 ldr.w r3, [r2, #136] @ 0x88 + 8000772: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 + 8000776: f8c2 3088 str.w r3, [r2, #136] @ 0x88 + 800077a: 4770 bx lr + 800077c: e000ed00 .word 0xe000ed00 + +08000780 : + 8000780: f8df d034 ldr.w sp, [pc, #52] @ 80007b8 + 8000784: f7ff fff2 bl 800076c + 8000788: 480c ldr r0, [pc, #48] @ (80007bc ) + 800078a: 490d ldr r1, [pc, #52] @ (80007c0 ) + 800078c: 4a0d ldr r2, [pc, #52] @ (80007c4 ) + 800078e: 2300 movs r3, #0 + 8000790: e002 b.n 8000798 + +08000792 : + 8000792: 58d4 ldr r4, [r2, r3] + 8000794: 50c4 str r4, [r0, r3] + 8000796: 3304 adds r3, #4 + +08000798 : + 8000798: 18c4 adds r4, r0, r3 + 800079a: 428c cmp r4, r1 + 800079c: d3f9 bcc.n 8000792 + 800079e: 4a0a ldr r2, [pc, #40] @ (80007c8 ) + 80007a0: 4c0a ldr r4, [pc, #40] @ (80007cc ) + 80007a2: 2300 movs r3, #0 + 80007a4: e001 b.n 80007aa + +080007a6 : + 80007a6: 6013 str r3, [r2, #0] + 80007a8: 3204 adds r2, #4 + +080007aa : + 80007aa: 42a2 cmp r2, r4 + 80007ac: d3fb bcc.n 80007a6 + 80007ae: f003 f865 bl 800387c <__libc_init_array> + 80007b2: f7ff ff17 bl 80005e4
+ 80007b6: 4770 bx lr + 80007b8: 20020000 .word 0x20020000 + 80007bc: 20000000 .word 0x20000000 + 80007c0: 20000120 .word 0x20000120 + 80007c4: 08003930 .word 0x08003930 + 80007c8: 20000120 .word 0x20000120 + 80007cc: 20000b20 .word 0x20000b20 + +080007d0 : + 80007d0: e7fe b.n 80007d0 + ... + +080007d4 : + 80007d4: b538 push {r3, r4, r5, lr} + 80007d6: 4b0e ldr r3, [pc, #56] @ (8000810 ) + 80007d8: 781a ldrb r2, [r3, #0] + 80007da: f44f 737a mov.w r3, #1000 @ 0x3e8 + 80007de: fbb3 f3f2 udiv r3, r3, r2 + 80007e2: 4a0c ldr r2, [pc, #48] @ (8000814 ) + 80007e4: 4605 mov r5, r0 + 80007e6: 6810 ldr r0, [r2, #0] + 80007e8: fbb0 f0f3 udiv r0, r0, r3 + 80007ec: f000 f8a8 bl 8000940 + 80007f0: 4604 mov r4, r0 + 80007f2: b958 cbnz r0, 800080c + 80007f4: 2d0f cmp r5, #15 + 80007f6: d809 bhi.n 800080c + 80007f8: 4602 mov r2, r0 + 80007fa: 4629 mov r1, r5 + 80007fc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000800: f000 f85e bl 80008c0 + 8000804: 4b04 ldr r3, [pc, #16] @ (8000818 ) + 8000806: 4620 mov r0, r4 + 8000808: 601d str r5, [r3, #0] + 800080a: bd38 pop {r3, r4, r5, pc} + 800080c: 2001 movs r0, #1 + 800080e: e7fc b.n 800080a + 8000810: 20000004 .word 0x20000004 + 8000814: 20000000 .word 0x20000000 + 8000818: 20000008 .word 0x20000008 + +0800081c : + 800081c: b508 push {r3, lr} + 800081e: 4b0b ldr r3, [pc, #44] @ (800084c ) + 8000820: 681a ldr r2, [r3, #0] + 8000822: f442 7200 orr.w r2, r2, #512 @ 0x200 + 8000826: 601a str r2, [r3, #0] + 8000828: 681a ldr r2, [r3, #0] + 800082a: f442 6280 orr.w r2, r2, #1024 @ 0x400 + 800082e: 601a str r2, [r3, #0] + 8000830: 681a ldr r2, [r3, #0] + 8000832: f442 7280 orr.w r2, r2, #256 @ 0x100 + 8000836: 601a str r2, [r3, #0] + 8000838: 2003 movs r0, #3 + 800083a: f000 f82f bl 800089c + 800083e: 200f movs r0, #15 + 8000840: f7ff ffc8 bl 80007d4 + 8000844: f7ff ff66 bl 8000714 + 8000848: 2000 movs r0, #0 + 800084a: bd08 pop {r3, pc} + 800084c: 40023c00 .word 0x40023c00 + +08000850 : + 8000850: 4a03 ldr r2, [pc, #12] @ (8000860 ) + 8000852: 4b04 ldr r3, [pc, #16] @ (8000864 ) + 8000854: 6811 ldr r1, [r2, #0] + 8000856: 781b ldrb r3, [r3, #0] + 8000858: 440b add r3, r1 + 800085a: 6013 str r3, [r2, #0] + 800085c: 4770 bx lr + 800085e: bf00 nop + 8000860: 20000144 .word 0x20000144 + 8000864: 20000004 .word 0x20000004 + +08000868 : + 8000868: 4b01 ldr r3, [pc, #4] @ (8000870 ) + 800086a: 6818 ldr r0, [r3, #0] + 800086c: 4770 bx lr + 800086e: bf00 nop + 8000870: 20000144 .word 0x20000144 + +08000874 : + 8000874: b538 push {r3, r4, r5, lr} + 8000876: 4604 mov r4, r0 + 8000878: f7ff fff6 bl 8000868 + 800087c: 1c63 adds r3, r4, #1 + 800087e: bf1c itt ne + 8000880: 4b05 ldrne r3, [pc, #20] @ (8000898 ) + 8000882: 781b ldrbne r3, [r3, #0] + 8000884: 4605 mov r5, r0 + 8000886: bf18 it ne + 8000888: 18e4 addne r4, r4, r3 + 800088a: f7ff ffed bl 8000868 + 800088e: 1b43 subs r3, r0, r5 + 8000890: 42a3 cmp r3, r4 + 8000892: d3fa bcc.n 800088a + 8000894: bd38 pop {r3, r4, r5, pc} + 8000896: bf00 nop + 8000898: 20000004 .word 0x20000004 + +0800089c : + 800089c: 4907 ldr r1, [pc, #28] @ (80008bc ) + 800089e: 68ca ldr r2, [r1, #12] + 80008a0: f422 62e0 bic.w r2, r2, #1792 @ 0x700 + 80008a4: 0203 lsls r3, r0, #8 + 80008a6: 0412 lsls r2, r2, #16 + 80008a8: f403 63e0 and.w r3, r3, #1792 @ 0x700 + 80008ac: 0c12 lsrs r2, r2, #16 + 80008ae: 4313 orrs r3, r2 + 80008b0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 80008b4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 80008b8: 60cb str r3, [r1, #12] + 80008ba: 4770 bx lr + 80008bc: e000ed00 .word 0xe000ed00 + +080008c0 : + 80008c0: 4b16 ldr r3, [pc, #88] @ (800091c ) + 80008c2: b530 push {r4, r5, lr} + 80008c4: 68dc ldr r4, [r3, #12] + 80008c6: f3c4 2402 ubfx r4, r4, #8, #3 + 80008ca: f1c4 0307 rsb r3, r4, #7 + 80008ce: 1d25 adds r5, r4, #4 + 80008d0: 2b04 cmp r3, #4 + 80008d2: bf28 it cs + 80008d4: 2304 movcs r3, #4 + 80008d6: 2d06 cmp r5, #6 + 80008d8: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff + 80008dc: bf8c ite hi + 80008de: 3c03 subhi r4, #3 + 80008e0: 2400 movls r4, #0 + 80008e2: fa05 f303 lsl.w r3, r5, r3 + 80008e6: ea21 0303 bic.w r3, r1, r3 + 80008ea: 40a5 lsls r5, r4 + 80008ec: ea22 0205 bic.w r2, r2, r5 + 80008f0: 40a3 lsls r3, r4 + 80008f2: 2800 cmp r0, #0 + 80008f4: ea43 0302 orr.w r3, r3, r2 + 80008f8: bfac ite ge + 80008fa: f100 4060 addge.w r0, r0, #3758096384 @ 0xe0000000 + 80008fe: 4a08 ldrlt r2, [pc, #32] @ (8000920 ) + 8000900: ea4f 1303 mov.w r3, r3, lsl #4 + 8000904: bfb8 it lt + 8000906: f000 000f andlt.w r0, r0, #15 + 800090a: b2db uxtb r3, r3 + 800090c: bfaa itet ge + 800090e: f500 4061 addge.w r0, r0, #57600 @ 0xe100 + 8000912: 5413 strblt r3, [r2, r0] + 8000914: f880 3300 strbge.w r3, [r0, #768] @ 0x300 + 8000918: bd30 pop {r4, r5, pc} + 800091a: bf00 nop + 800091c: e000ed00 .word 0xe000ed00 + 8000920: e000ed14 .word 0xe000ed14 + +08000924 : + 8000924: 2800 cmp r0, #0 + 8000926: db07 blt.n 8000938 + 8000928: 4a04 ldr r2, [pc, #16] @ (800093c ) + 800092a: 0941 lsrs r1, r0, #5 + 800092c: 2301 movs r3, #1 + 800092e: f000 001f and.w r0, r0, #31 + 8000932: 4083 lsls r3, r0 + 8000934: f842 3021 str.w r3, [r2, r1, lsl #2] + 8000938: 4770 bx lr + 800093a: bf00 nop + 800093c: e000e100 .word 0xe000e100 + +08000940 : + 8000940: 3801 subs r0, #1 + 8000942: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 + 8000946: d20b bcs.n 8000960 + 8000948: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 + 800094c: 4a05 ldr r2, [pc, #20] @ (8000964 ) + 800094e: 6158 str r0, [r3, #20] + 8000950: 21f0 movs r1, #240 @ 0xf0 + 8000952: f882 1023 strb.w r1, [r2, #35] @ 0x23 + 8000956: 2000 movs r0, #0 + 8000958: 2207 movs r2, #7 + 800095a: 6198 str r0, [r3, #24] + 800095c: 611a str r2, [r3, #16] + 800095e: 4770 bx lr + 8000960: 2001 movs r0, #1 + 8000962: 4770 bx lr + 8000964: e000ed00 .word 0xe000ed00 + +08000968 : + 8000968: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800096c: f8df 9198 ldr.w r9, [pc, #408] @ 8000b08 + 8000970: 4a63 ldr r2, [pc, #396] @ (8000b00 ) + 8000972: 2300 movs r3, #0 + 8000974: 680d ldr r5, [r1, #0] + 8000976: 2401 movs r4, #1 + 8000978: 409c lsls r4, r3 + 800097a: ea04 0605 and.w r6, r4, r5 + 800097e: 43ac bics r4, r5 + 8000980: f040 80ab bne.w 8000ada + 8000984: 684d ldr r5, [r1, #4] + 8000986: 2703 movs r7, #3 + 8000988: f005 0403 and.w r4, r5, #3 + 800098c: ea4f 0843 mov.w r8, r3, lsl #1 + 8000990: fa07 fc08 lsl.w ip, r7, r8 + 8000994: 1e67 subs r7, r4, #1 + 8000996: 2f01 cmp r7, #1 + 8000998: ea6f 0c0c mvn.w ip, ip + 800099c: d834 bhi.n 8000a08 + 800099e: 6887 ldr r7, [r0, #8] + 80009a0: ea07 0e0c and.w lr, r7, ip + 80009a4: 68cf ldr r7, [r1, #12] + 80009a6: fa07 f708 lsl.w r7, r7, r8 + 80009aa: ea47 070e orr.w r7, r7, lr + 80009ae: 6087 str r7, [r0, #8] + 80009b0: 6847 ldr r7, [r0, #4] + 80009b2: ea27 0e06 bic.w lr, r7, r6 + 80009b6: f3c5 1700 ubfx r7, r5, #4, #1 + 80009ba: 409f lsls r7, r3 + 80009bc: ea47 070e orr.w r7, r7, lr + 80009c0: 6047 str r7, [r0, #4] + 80009c2: 68c7 ldr r7, [r0, #12] + 80009c4: ea07 0e0c and.w lr, r7, ip + 80009c8: 688f ldr r7, [r1, #8] + 80009ca: fa07 f708 lsl.w r7, r7, r8 + 80009ce: ea47 070e orr.w r7, r7, lr + 80009d2: 2c02 cmp r4, #2 + 80009d4: 60c7 str r7, [r0, #12] + 80009d6: d119 bne.n 8000a0c + 80009d8: ea4f 0ad3 mov.w sl, r3, lsr #3 + 80009dc: eb00 0a8a add.w sl, r0, sl, lsl #2 + 80009e0: f003 0b07 and.w fp, r3, #7 + 80009e4: f8da 7020 ldr.w r7, [sl, #32] + 80009e8: ea4f 0b8b mov.w fp, fp, lsl #2 + 80009ec: f04f 0e0f mov.w lr, #15 + 80009f0: fa0e fe0b lsl.w lr, lr, fp + 80009f4: ea27 0e0e bic.w lr, r7, lr + 80009f8: 690f ldr r7, [r1, #16] + 80009fa: fa07 f70b lsl.w r7, r7, fp + 80009fe: ea47 070e orr.w r7, r7, lr + 8000a02: f8ca 7020 str.w r7, [sl, #32] + 8000a06: e001 b.n 8000a0c + 8000a08: 2c03 cmp r4, #3 + 8000a0a: d1da bne.n 80009c2 + 8000a0c: 6807 ldr r7, [r0, #0] + 8000a0e: fa04 f408 lsl.w r4, r4, r8 + 8000a12: ea07 070c and.w r7, r7, ip + 8000a16: 433c orrs r4, r7 + 8000a18: f415 3f40 tst.w r5, #196608 @ 0x30000 + 8000a1c: 6004 str r4, [r0, #0] + 8000a1e: d05c beq.n 8000ada + 8000a20: 2400 movs r4, #0 + 8000a22: 9401 str r4, [sp, #4] + 8000a24: f8d9 4044 ldr.w r4, [r9, #68] @ 0x44 + 8000a28: f444 4480 orr.w r4, r4, #16384 @ 0x4000 + 8000a2c: f8c9 4044 str.w r4, [r9, #68] @ 0x44 + 8000a30: f8d9 4044 ldr.w r4, [r9, #68] @ 0x44 + 8000a34: f023 0703 bic.w r7, r3, #3 + 8000a38: f107 4780 add.w r7, r7, #1073741824 @ 0x40000000 + 8000a3c: f404 4480 and.w r4, r4, #16384 @ 0x4000 + 8000a40: f507 379c add.w r7, r7, #79872 @ 0x13800 + 8000a44: 9401 str r4, [sp, #4] + 8000a46: f003 0c03 and.w ip, r3, #3 + 8000a4a: 9c01 ldr r4, [sp, #4] + 8000a4c: f8d7 e008 ldr.w lr, [r7, #8] + 8000a50: ea4f 0c8c mov.w ip, ip, lsl #2 + 8000a54: 240f movs r4, #15 + 8000a56: fa04 f40c lsl.w r4, r4, ip + 8000a5a: ea2e 0e04 bic.w lr, lr, r4 + 8000a5e: 4c29 ldr r4, [pc, #164] @ (8000b04 ) + 8000a60: 42a0 cmp r0, r4 + 8000a62: d041 beq.n 8000ae8 + 8000a64: f504 6480 add.w r4, r4, #1024 @ 0x400 + 8000a68: 42a0 cmp r0, r4 + 8000a6a: d03f beq.n 8000aec + 8000a6c: f504 6480 add.w r4, r4, #1024 @ 0x400 + 8000a70: 42a0 cmp r0, r4 + 8000a72: d03d beq.n 8000af0 + 8000a74: f504 6480 add.w r4, r4, #1024 @ 0x400 + 8000a78: 42a0 cmp r0, r4 + 8000a7a: d03b beq.n 8000af4 + 8000a7c: f504 6480 add.w r4, r4, #1024 @ 0x400 + 8000a80: 42a0 cmp r0, r4 + 8000a82: d039 beq.n 8000af8 + 8000a84: f504 6480 add.w r4, r4, #1024 @ 0x400 + 8000a88: 42a0 cmp r0, r4 + 8000a8a: d037 beq.n 8000afc + 8000a8c: f504 6480 add.w r4, r4, #1024 @ 0x400 + 8000a90: 42a0 cmp r0, r4 + 8000a92: bf14 ite ne + 8000a94: 2407 movne r4, #7 + 8000a96: 2406 moveq r4, #6 + 8000a98: fa04 f40c lsl.w r4, r4, ip + 8000a9c: ea44 040e orr.w r4, r4, lr + 8000aa0: 60bc str r4, [r7, #8] + 8000aa2: 6894 ldr r4, [r2, #8] + 8000aa4: 43f7 mvns r7, r6 + 8000aa6: f415 1f80 tst.w r5, #1048576 @ 0x100000 + 8000aaa: bf0c ite eq + 8000aac: 403c andeq r4, r7 + 8000aae: 4334 orrne r4, r6 + 8000ab0: 6094 str r4, [r2, #8] + 8000ab2: 68d4 ldr r4, [r2, #12] + 8000ab4: f415 1f00 tst.w r5, #2097152 @ 0x200000 + 8000ab8: bf0c ite eq + 8000aba: 403c andeq r4, r7 + 8000abc: 4334 orrne r4, r6 + 8000abe: 60d4 str r4, [r2, #12] + 8000ac0: 6854 ldr r4, [r2, #4] + 8000ac2: f415 3f00 tst.w r5, #131072 @ 0x20000 + 8000ac6: bf0c ite eq + 8000ac8: 403c andeq r4, r7 + 8000aca: 4334 orrne r4, r6 + 8000acc: 6054 str r4, [r2, #4] + 8000ace: 6814 ldr r4, [r2, #0] + 8000ad0: 03ed lsls r5, r5, #15 + 8000ad2: bf54 ite pl + 8000ad4: 403c andpl r4, r7 + 8000ad6: 4334 orrmi r4, r6 + 8000ad8: 6014 str r4, [r2, #0] + 8000ada: 3301 adds r3, #1 + 8000adc: 2b10 cmp r3, #16 + 8000ade: f47f af49 bne.w 8000974 + 8000ae2: b003 add sp, #12 + 8000ae4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8000ae8: 2400 movs r4, #0 + 8000aea: e7d5 b.n 8000a98 + 8000aec: 2401 movs r4, #1 + 8000aee: e7d3 b.n 8000a98 + 8000af0: 2402 movs r4, #2 + 8000af2: e7d1 b.n 8000a98 + 8000af4: 2403 movs r4, #3 + 8000af6: e7cf b.n 8000a98 + 8000af8: 2404 movs r4, #4 + 8000afa: e7cd b.n 8000a98 + 8000afc: 2405 movs r4, #5 + 8000afe: e7cb b.n 8000a98 + 8000b00: 40013c00 .word 0x40013c00 + 8000b04: 40020000 .word 0x40020000 + 8000b08: 40023800 .word 0x40023800 + +08000b0c : + 8000b0c: b10a cbz r2, 8000b12 + 8000b0e: 6181 str r1, [r0, #24] + 8000b10: 4770 bx lr + 8000b12: 0409 lsls r1, r1, #16 + 8000b14: e7fb b.n 8000b0e + +08000b16 : + 8000b16: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 8000b18: 4604 mov r4, r0 + 8000b1a: b310 cbz r0, 8000b62 + 8000b1c: f890 3495 ldrb.w r3, [r0, #1173] @ 0x495 + 8000b20: 6805 ldr r5, [r0, #0] + 8000b22: f003 02ff and.w r2, r3, #255 @ 0xff + 8000b26: b91b cbnz r3, 8000b30 + 8000b28: f880 2494 strb.w r2, [r0, #1172] @ 0x494 + 8000b2c: f002 fd2c bl 8003588 + 8000b30: 2303 movs r3, #3 + 8000b32: f1b5 4fa0 cmp.w r5, #1342177280 @ 0x50000000 + 8000b36: f884 3495 strb.w r3, [r4, #1173] @ 0x495 + 8000b3a: bf04 itt eq + 8000b3c: 2300 moveq r3, #0 + 8000b3e: 71a3 strbeq r3, [r4, #6] + 8000b40: 6820 ldr r0, [r4, #0] + 8000b42: f001 fae9 bl 8002118 + 8000b46: 7c23 ldrb r3, [r4, #16] + 8000b48: f88d 3000 strb.w r3, [sp] + 8000b4c: 1d25 adds r5, r4, #4 + 8000b4e: e895 000e ldmia.w r5, {r1, r2, r3} + 8000b52: 6820 ldr r0, [r4, #0] + 8000b54: f001 fa26 bl 8001fa4 + 8000b58: 4601 mov r1, r0 + 8000b5a: b130 cbz r0, 8000b6a + 8000b5c: 2302 movs r3, #2 + 8000b5e: f884 3495 strb.w r3, [r4, #1173] @ 0x495 + 8000b62: 2501 movs r5, #1 + 8000b64: 4628 mov r0, r5 + 8000b66: b003 add sp, #12 + 8000b68: bdf0 pop {r4, r5, r6, r7, pc} + 8000b6a: 6820 ldr r0, [r4, #0] + 8000b6c: f001 fada bl 8002124 + 8000b70: 2800 cmp r0, #0 + 8000b72: d1f3 bne.n 8000b5c + 8000b74: 7926 ldrb r6, [r4, #4] + 8000b76: f104 0314 add.w r3, r4, #20 + 8000b7a: 2701 movs r7, #1 + 8000b7c: 4602 mov r2, r0 + 8000b7e: b2c1 uxtb r1, r0 + 8000b80: 428e cmp r6, r1 + 8000b82: f103 0324 add.w r3, r3, #36 @ 0x24 + 8000b86: d821 bhi.n 8000bcc + 8000b88: 2100 movs r1, #0 + 8000b8a: f504 7315 add.w r3, r4, #596 @ 0x254 + 8000b8e: 460a mov r2, r1 + 8000b90: b2c8 uxtb r0, r1 + 8000b92: 4286 cmp r6, r0 + 8000b94: f103 0324 add.w r3, r3, #36 @ 0x24 + 8000b98: d826 bhi.n 8000be8 + 8000b9a: 7c23 ldrb r3, [r4, #16] + 8000b9c: f88d 3000 strb.w r3, [sp] + 8000ba0: e895 000e ldmia.w r5, {r1, r2, r3} + 8000ba4: 6820 ldr r0, [r4, #0] + 8000ba6: f001 fb39 bl 800221c + 8000baa: 4605 mov r5, r0 + 8000bac: 2800 cmp r0, #0 + 8000bae: d1d5 bne.n 8000b5c + 8000bb0: 2301 movs r3, #1 + 8000bb2: 7460 strb r0, [r4, #17] + 8000bb4: f884 3495 strb.w r3, [r4, #1173] @ 0x495 + 8000bb8: 7b23 ldrb r3, [r4, #12] + 8000bba: 2b01 cmp r3, #1 + 8000bbc: d102 bne.n 8000bc4 + 8000bbe: 4620 mov r0, r4 + 8000bc0: f000 fcf5 bl 80015ae + 8000bc4: 6820 ldr r0, [r4, #0] + 8000bc6: f001 fe6b bl 80028a0 + 8000bca: e7cb b.n 8000b64 + 8000bcc: f823 0c0a strh.w r0, [r3, #-10] + 8000bd0: e943 2207 strd r2, r2, [r3, #-28] + 8000bd4: f803 7c23 strb.w r7, [r3, #-35] + 8000bd8: f803 1c24 strb.w r1, [r3, #-36] + 8000bdc: f803 2c20 strb.w r2, [r3, #-32] + 8000be0: f843 2c14 str.w r2, [r3, #-20] + 8000be4: 3001 adds r0, #1 + 8000be6: e7ca b.n 8000b7e + 8000be8: e943 2207 strd r2, r2, [r3, #-28] + 8000bec: f803 2c23 strb.w r2, [r3, #-35] + 8000bf0: f803 0c24 strb.w r0, [r3, #-36] + 8000bf4: f803 2c20 strb.w r2, [r3, #-32] + 8000bf8: f843 2c14 str.w r2, [r3, #-20] + 8000bfc: 3101 adds r1, #1 + 8000bfe: e7c7 b.n 8000b90 + +08000c00 : + 8000c00: b510 push {r4, lr} + 8000c02: 4604 mov r4, r0 + 8000c04: 6800 ldr r0, [r0, #0] + 8000c06: f894 3494 ldrb.w r3, [r4, #1172] @ 0x494 + 8000c0a: 2b01 cmp r3, #1 + 8000c0c: d015 beq.n 8000c3a + 8000c0e: 2301 movs r3, #1 + 8000c10: f884 3494 strb.w r3, [r4, #1172] @ 0x494 + 8000c14: 68c3 ldr r3, [r0, #12] + 8000c16: 065b lsls r3, r3, #25 + 8000c18: d506 bpl.n 8000c28 + 8000c1a: 7b63 ldrb r3, [r4, #13] + 8000c1c: 2b01 cmp r3, #1 + 8000c1e: bf02 ittt eq + 8000c20: 6b83 ldreq r3, [r0, #56] @ 0x38 + 8000c22: f443 3380 orreq.w r3, r3, #65536 @ 0x10000 + 8000c26: 6383 streq r3, [r0, #56] @ 0x38 + 8000c28: f001 fa70 bl 800210c + 8000c2c: 6820 ldr r0, [r4, #0] + 8000c2e: f001 fe29 bl 8002884 + 8000c32: 2000 movs r0, #0 + 8000c34: f884 0494 strb.w r0, [r4, #1172] @ 0x494 + 8000c38: bd10 pop {r4, pc} + 8000c3a: 2002 movs r0, #2 + 8000c3c: e7fc b.n 8000c38 + +08000c3e : + 8000c3e: b510 push {r4, lr} + 8000c40: f890 2494 ldrb.w r2, [r0, #1172] @ 0x494 + 8000c44: 2a01 cmp r2, #1 + 8000c46: 4604 mov r4, r0 + 8000c48: d00a beq.n 8000c60 + 8000c4a: 2201 movs r2, #1 + 8000c4c: f880 2494 strb.w r2, [r0, #1172] @ 0x494 + 8000c50: 7441 strb r1, [r0, #17] + 8000c52: 6800 ldr r0, [r0, #0] + 8000c54: f001 fe06 bl 8002864 + 8000c58: 2000 movs r0, #0 + 8000c5a: f884 0494 strb.w r0, [r4, #1172] @ 0x494 + 8000c5e: bd10 pop {r4, pc} + 8000c60: 2002 movs r0, #2 + 8000c62: e7fc b.n 8000c5e + +08000c64 : + 8000c64: b570 push {r4, r5, r6, lr} + 8000c66: f001 060f and.w r6, r1, #15 + 8000c6a: eb06 04c6 add.w r4, r6, r6, lsl #3 + 8000c6e: f011 0f80 tst.w r1, #128 @ 0x80 + 8000c72: 4605 mov r5, r0 + 8000c74: ea4f 0484 mov.w r4, r4, lsl #2 + 8000c78: f04f 0024 mov.w r0, #36 @ 0x24 + 8000c7c: d020 beq.n 8000cc0 + 8000c7e: fb00 5006 mla r0, r0, r6, r5 + 8000c82: f104 0114 add.w r1, r4, #20 + 8000c86: 2401 movs r4, #1 + 8000c88: 4429 add r1, r5 + 8000c8a: 7544 strb r4, [r0, #21] + 8000c8c: f3c2 020a ubfx r2, r2, #0, #11 + 8000c90: 608a str r2, [r1, #8] + 8000c92: 784a ldrb r2, [r1, #1] + 8000c94: 700e strb r6, [r1, #0] + 8000c96: 710b strb r3, [r1, #4] + 8000c98: b102 cbz r2, 8000c9c + 8000c9a: 834e strh r6, [r1, #26] + 8000c9c: 2b02 cmp r3, #2 + 8000c9e: bf04 itt eq + 8000ca0: 2300 moveq r3, #0 + 8000ca2: 714b strbeq r3, [r1, #5] + 8000ca4: f895 3494 ldrb.w r3, [r5, #1172] @ 0x494 + 8000ca8: 2b01 cmp r3, #1 + 8000caa: d012 beq.n 8000cd2 + 8000cac: 2301 movs r3, #1 + 8000cae: 6828 ldr r0, [r5, #0] + 8000cb0: f885 3494 strb.w r3, [r5, #1172] @ 0x494 + 8000cb4: f001 fb75 bl 80023a2 + 8000cb8: 2000 movs r0, #0 + 8000cba: f885 0494 strb.w r0, [r5, #1172] @ 0x494 + 8000cbe: bd70 pop {r4, r5, r6, pc} + 8000cc0: fb00 5006 mla r0, r0, r6, r5 + 8000cc4: f504 7115 add.w r1, r4, #596 @ 0x254 + 8000cc8: 2400 movs r4, #0 + 8000cca: 4429 add r1, r5 + 8000ccc: f880 4255 strb.w r4, [r0, #597] @ 0x255 + 8000cd0: e7dc b.n 8000c8c + 8000cd2: 2002 movs r0, #2 + 8000cd4: e7f3 b.n 8000cbe + +08000cd6 : + 8000cd6: b510 push {r4, lr} + 8000cd8: 4604 mov r4, r0 + 8000cda: f001 000f and.w r0, r1, #15 + 8000cde: eb00 03c0 add.w r3, r0, r0, lsl #3 + 8000ce2: f011 0f80 tst.w r1, #128 @ 0x80 + 8000ce6: ea4f 0383 mov.w r3, r3, lsl #2 + 8000cea: f04f 0224 mov.w r2, #36 @ 0x24 + 8000cee: d015 beq.n 8000d1c + 8000cf0: fb02 4200 mla r2, r2, r0, r4 + 8000cf4: f103 0114 add.w r1, r3, #20 + 8000cf8: 2301 movs r3, #1 + 8000cfa: 4421 add r1, r4 + 8000cfc: 7553 strb r3, [r2, #21] + 8000cfe: 7008 strb r0, [r1, #0] + 8000d00: f894 3494 ldrb.w r3, [r4, #1172] @ 0x494 + 8000d04: 2b01 cmp r3, #1 + 8000d06: d012 beq.n 8000d2e + 8000d08: 2301 movs r3, #1 + 8000d0a: 6820 ldr r0, [r4, #0] + 8000d0c: f884 3494 strb.w r3, [r4, #1172] @ 0x494 + 8000d10: f001 fb86 bl 8002420 + 8000d14: 2000 movs r0, #0 + 8000d16: f884 0494 strb.w r0, [r4, #1172] @ 0x494 + 8000d1a: bd10 pop {r4, pc} + 8000d1c: fb02 4200 mla r2, r2, r0, r4 + 8000d20: f503 7115 add.w r1, r3, #596 @ 0x254 + 8000d24: 2300 movs r3, #0 + 8000d26: 4421 add r1, r4 + 8000d28: f882 3255 strb.w r3, [r2, #597] @ 0x255 + 8000d2c: e7e7 b.n 8000cfe + 8000d2e: 2002 movs r0, #2 + 8000d30: e7f3 b.n 8000d1a + +08000d32 : + 8000d32: b570 push {r4, r5, r6, lr} + 8000d34: f001 050f and.w r5, r1, #15 + 8000d38: 2424 movs r4, #36 @ 0x24 + 8000d3a: fb04 0105 mla r1, r4, r5, r0 + 8000d3e: fb04 0405 mla r4, r4, r5, r0 + 8000d42: e9c4 2398 strd r2, r3, [r4, #608] @ 0x260 + 8000d46: 2300 movs r3, #0 + 8000d48: f8c4 3268 str.w r3, [r4, #616] @ 0x268 + 8000d4c: f884 3255 strb.w r3, [r4, #597] @ 0x255 + 8000d50: f884 5254 strb.w r5, [r4, #596] @ 0x254 + 8000d54: 4616 mov r6, r2 + 8000d56: 7982 ldrb r2, [r0, #6] + 8000d58: 6800 ldr r0, [r0, #0] + 8000d5a: 2a01 cmp r2, #1 + 8000d5c: f501 7115 add.w r1, r1, #596 @ 0x254 + 8000d60: bf08 it eq + 8000d62: f8c4 6270 streq.w r6, [r4, #624] @ 0x270 + 8000d66: f001 fc07 bl 8002578 + 8000d6a: 2000 movs r0, #0 + 8000d6c: bd70 pop {r4, r5, r6, pc} + +08000d6e : + 8000d6e: b570 push {r4, r5, r6, lr} + 8000d70: f001 050f and.w r5, r1, #15 + 8000d74: 2424 movs r4, #36 @ 0x24 + 8000d76: fb04 0105 mla r1, r4, r5, r0 + 8000d7a: fb04 0405 mla r4, r4, r5, r0 + 8000d7e: e9c4 2308 strd r2, r3, [r4, #32] + 8000d82: 2300 movs r3, #0 + 8000d84: 62a3 str r3, [r4, #40] @ 0x28 + 8000d86: 2301 movs r3, #1 + 8000d88: 7563 strb r3, [r4, #21] + 8000d8a: 7525 strb r5, [r4, #20] + 8000d8c: 4616 mov r6, r2 + 8000d8e: 7982 ldrb r2, [r0, #6] + 8000d90: 6800 ldr r0, [r0, #0] + 8000d92: 429a cmp r2, r3 + 8000d94: f101 0114 add.w r1, r1, #20 + 8000d98: bf08 it eq + 8000d9a: 6326 streq r6, [r4, #48] @ 0x30 + 8000d9c: f001 fbec bl 8002578 + 8000da0: 2000 movs r0, #0 + 8000da2: bd70 pop {r4, r5, r6, pc} + +08000da4 : + 8000da4: b538 push {r3, r4, r5, lr} + 8000da6: 7903 ldrb r3, [r0, #4] + 8000da8: f001 050f and.w r5, r1, #15 + 8000dac: 42ab cmp r3, r5 + 8000dae: 4604 mov r4, r0 + 8000db0: d32b bcc.n 8000e0a + 8000db2: f011 0f80 tst.w r1, #128 @ 0x80 + 8000db6: f04f 0024 mov.w r0, #36 @ 0x24 + 8000dba: d01d beq.n 8000df8 + 8000dbc: fb00 4105 mla r1, r0, r5, r4 + 8000dc0: fb00 4005 mla r0, r0, r5, r4 + 8000dc4: 2301 movs r3, #1 + 8000dc6: 3114 adds r1, #20 + 8000dc8: 7543 strb r3, [r0, #21] + 8000dca: 2301 movs r3, #1 + 8000dcc: 708b strb r3, [r1, #2] + 8000dce: 700d strb r5, [r1, #0] + 8000dd0: f894 2494 ldrb.w r2, [r4, #1172] @ 0x494 + 8000dd4: 429a cmp r2, r3 + 8000dd6: d01a beq.n 8000e0e + 8000dd8: 6820 ldr r0, [r4, #0] + 8000dda: f884 3494 strb.w r3, [r4, #1172] @ 0x494 + 8000dde: f001 fced bl 80027bc + 8000de2: b92d cbnz r5, 8000df0 + 8000de4: 79a1 ldrb r1, [r4, #6] + 8000de6: 6820 ldr r0, [r4, #0] + 8000de8: f204 429c addw r2, r4, #1180 @ 0x49c + 8000dec: f001 fda6 bl 800293c + 8000df0: 2000 movs r0, #0 + 8000df2: f884 0494 strb.w r0, [r4, #1172] @ 0x494 + 8000df6: bd38 pop {r3, r4, r5, pc} + 8000df8: fb00 4301 mla r3, r0, r1, r4 + 8000dfc: 461a mov r2, r3 + 8000dfe: f503 7115 add.w r1, r3, #596 @ 0x254 + 8000e02: 2300 movs r3, #0 + 8000e04: f882 3255 strb.w r3, [r2, #597] @ 0x255 + 8000e08: e7df b.n 8000dca + 8000e0a: 2001 movs r0, #1 + 8000e0c: e7f3 b.n 8000df6 + 8000e0e: 2002 movs r0, #2 + 8000e10: e7f1 b.n 8000df6 + +08000e12 : + 8000e12: b538 push {r3, r4, r5, lr} + 8000e14: 7903 ldrb r3, [r0, #4] + 8000e16: f001 020f and.w r2, r1, #15 + 8000e1a: 4293 cmp r3, r2 + 8000e1c: 4604 mov r4, r0 + 8000e1e: d329 bcc.n 8000e74 + 8000e20: eb02 03c2 add.w r3, r2, r2, lsl #3 + 8000e24: f011 0f80 tst.w r1, #128 @ 0x80 + 8000e28: ea4f 0383 mov.w r3, r3, lsl #2 + 8000e2c: f04f 0024 mov.w r0, #36 @ 0x24 + 8000e30: d017 beq.n 8000e62 + 8000e32: fb00 4002 mla r0, r0, r2, r4 + 8000e36: f103 0114 add.w r1, r3, #20 + 8000e3a: 2301 movs r3, #1 + 8000e3c: 4421 add r1, r4 + 8000e3e: 7543 strb r3, [r0, #21] + 8000e40: 2500 movs r5, #0 + 8000e42: 708d strb r5, [r1, #2] + 8000e44: 700a strb r2, [r1, #0] + 8000e46: f894 3494 ldrb.w r3, [r4, #1172] @ 0x494 + 8000e4a: 2b01 cmp r3, #1 + 8000e4c: d014 beq.n 8000e78 + 8000e4e: 2301 movs r3, #1 + 8000e50: 6820 ldr r0, [r4, #0] + 8000e52: f884 3494 strb.w r3, [r4, #1172] @ 0x494 + 8000e56: f001 fcdc bl 8002812 + 8000e5a: f884 5494 strb.w r5, [r4, #1172] @ 0x494 + 8000e5e: 4628 mov r0, r5 + 8000e60: bd38 pop {r3, r4, r5, pc} + 8000e62: fb00 4002 mla r0, r0, r2, r4 + 8000e66: f503 7115 add.w r1, r3, #596 @ 0x254 + 8000e6a: 2300 movs r3, #0 + 8000e6c: 4421 add r1, r4 + 8000e6e: f880 3255 strb.w r3, [r0, #597] @ 0x255 + 8000e72: e7e5 b.n 8000e40 + 8000e74: 2001 movs r0, #1 + 8000e76: e7f3 b.n 8000e60 + 8000e78: 2002 movs r0, #2 + 8000e7a: e7f1 b.n 8000e60 + +08000e7c : + 8000e7c: f001 030f and.w r3, r1, #15 + 8000e80: eb03 03c3 add.w r3, r3, r3, lsl #3 + 8000e84: 060a lsls r2, r1, #24 + 8000e86: ea4f 0383 mov.w r3, r3, lsl #2 + 8000e8a: bf4c ite mi + 8000e8c: f103 0114 addmi.w r1, r3, #20 + 8000e90: f503 7115 addpl.w r1, r3, #596 @ 0x254 + 8000e94: 4401 add r1, r0 + 8000e96: 6800 ldr r0, [r0, #0] + 8000e98: f001 bb18 b.w 80024cc + +08000e9c : + 8000e9c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8000ea0: 6806 ldr r6, [r0, #0] + 8000ea2: b089 sub sp, #36 @ 0x24 + 8000ea4: 4604 mov r4, r0 + 8000ea6: 4630 mov r0, r6 + 8000ea8: f001 fd36 bl 8002918 + 8000eac: 9003 str r0, [sp, #12] + 8000eae: 2800 cmp r0, #0 + 8000eb0: f040 8170 bne.w 8001194 + 8000eb4: 6820 ldr r0, [r4, #0] + 8000eb6: f001 fd01 bl 80028bc + 8000eba: 2800 cmp r0, #0 + 8000ebc: f000 816a beq.w 8001194 + 8000ec0: f8d6 3808 ldr.w r3, [r6, #2056] @ 0x808 + 8000ec4: 6820 ldr r0, [r4, #0] + 8000ec6: f3c3 230d ubfx r3, r3, #8, #14 + 8000eca: f8c4 34d4 str.w r3, [r4, #1236] @ 0x4d4 + 8000ece: f001 fcf5 bl 80028bc + 8000ed2: 0787 lsls r7, r0, #30 + 8000ed4: bf48 it mi + 8000ed6: 6822 ldrmi r2, [r4, #0] + 8000ed8: 6820 ldr r0, [r4, #0] + 8000eda: bf42 ittt mi + 8000edc: 6953 ldrmi r3, [r2, #20] + 8000ede: f003 0302 andmi.w r3, r3, #2 + 8000ee2: 6153 strmi r3, [r2, #20] + 8000ee4: f001 fcea bl 80028bc + 8000ee8: 06c0 lsls r0, r0, #27 + 8000eea: f506 6500 add.w r5, r6, #2048 @ 0x800 + 8000eee: d52d bpl.n 8000f4c + 8000ef0: 6822 ldr r2, [r4, #0] + 8000ef2: 6993 ldr r3, [r2, #24] + 8000ef4: f023 0310 bic.w r3, r3, #16 + 8000ef8: 6193 str r3, [r2, #24] + 8000efa: f8d6 8020 ldr.w r8, [r6, #32] + 8000efe: f408 13f0 and.w r3, r8, #1966080 @ 0x1e0000 + 8000f02: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 + 8000f06: f008 070f and.w r7, r8, #15 + 8000f0a: f040 8146 bne.w 800119a + 8000f0e: f647 73f0 movw r3, #32752 @ 0x7ff0 + 8000f12: ea18 0f03 tst.w r8, r3 + 8000f16: d014 beq.n 8000f42 + 8000f18: 2324 movs r3, #36 @ 0x24 + 8000f1a: fb03 4707 mla r7, r3, r7, r4 + 8000f1e: f3c8 190a ubfx r9, r8, #4, #11 + 8000f22: f8d7 1260 ldr.w r1, [r7, #608] @ 0x260 + 8000f26: 464a mov r2, r9 + 8000f28: 4630 mov r0, r6 + 8000f2a: f001 fc27 bl 800277c + 8000f2e: f8d7 3260 ldr.w r3, [r7, #608] @ 0x260 + 8000f32: 444b add r3, r9 + 8000f34: f8c7 3260 str.w r3, [r7, #608] @ 0x260 + 8000f38: f8d7 3268 ldr.w r3, [r7, #616] @ 0x268 + 8000f3c: 444b add r3, r9 + 8000f3e: f8c7 3268 str.w r3, [r7, #616] @ 0x268 + 8000f42: 6822 ldr r2, [r4, #0] + 8000f44: 6993 ldr r3, [r2, #24] + 8000f46: f043 0310 orr.w r3, r3, #16 + 8000f4a: 6193 str r3, [r2, #24] + 8000f4c: 6820 ldr r0, [r4, #0] + 8000f4e: f001 fcb5 bl 80028bc + 8000f52: 0301 lsls r1, r0, #12 + 8000f54: f100 8134 bmi.w 80011c0 + 8000f58: 6820 ldr r0, [r4, #0] + 8000f5a: f001 fcaf bl 80028bc + 8000f5e: 0342 lsls r2, r0, #13 + 8000f60: d50d bpl.n 8000f7e + 8000f62: 6820 ldr r0, [r4, #0] + 8000f64: f001 fcb6 bl 80028d4 + 8000f68: 4627 mov r7, r4 + 8000f6a: 9004 str r0, [sp, #16] + 8000f6c: f506 6b10 add.w fp, r6, #2304 @ 0x900 + 8000f70: f04f 0a00 mov.w sl, #0 + 8000f74: 9b04 ldr r3, [sp, #16] + 8000f76: 6820 ldr r0, [r4, #0] + 8000f78: 2b00 cmp r3, #0 + 8000f7a: f040 81eb bne.w 8001354 + 8000f7e: 6820 ldr r0, [r4, #0] + 8000f80: f001 fc9c bl 80028bc + 8000f84: 2800 cmp r0, #0 + 8000f86: da13 bge.n 8000fb0 + 8000f88: 686b ldr r3, [r5, #4] + 8000f8a: f023 0301 bic.w r3, r3, #1 + 8000f8e: 606b str r3, [r5, #4] + 8000f90: f894 34cc ldrb.w r3, [r4, #1228] @ 0x4cc + 8000f94: 2b01 cmp r3, #1 + 8000f96: f040 8283 bne.w 80014a0 + 8000f9a: 2100 movs r1, #0 + 8000f9c: f884 14cc strb.w r1, [r4, #1228] @ 0x4cc + 8000fa0: 4620 mov r0, r4 + 8000fa2: f002 fbdb bl 800375c + 8000fa6: 6822 ldr r2, [r4, #0] + 8000fa8: 6953 ldr r3, [r2, #20] + 8000faa: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 8000fae: 6153 str r3, [r2, #20] + 8000fb0: 6820 ldr r0, [r4, #0] + 8000fb2: f001 fc83 bl 80028bc + 8000fb6: 0503 lsls r3, r0, #20 + 8000fb8: d50a bpl.n 8000fd0 + 8000fba: 68ab ldr r3, [r5, #8] + 8000fbc: 07df lsls r7, r3, #31 + 8000fbe: d502 bpl.n 8000fc6 + 8000fc0: 4620 mov r0, r4 + 8000fc2: f002 fb5f bl 8003684 + 8000fc6: 6822 ldr r2, [r4, #0] + 8000fc8: 6953 ldr r3, [r2, #20] + 8000fca: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8000fce: 6153 str r3, [r2, #20] + 8000fd0: 6820 ldr r0, [r4, #0] + 8000fd2: f001 fc73 bl 80028bc + 8000fd6: 0100 lsls r0, r0, #4 + 8000fd8: d514 bpl.n 8001004 + 8000fda: 6823 ldr r3, [r4, #0] + 8000fdc: 695a ldr r2, [r3, #20] + 8000fde: f002 6200 and.w r2, r2, #134217728 @ 0x8000000 + 8000fe2: 615a str r2, [r3, #20] + 8000fe4: f894 24cc ldrb.w r2, [r4, #1228] @ 0x4cc + 8000fe8: 2a00 cmp r2, #0 + 8000fea: f040 825d bne.w 80014a8 + 8000fee: 2101 movs r1, #1 + 8000ff0: f884 14cc strb.w r1, [r4, #1228] @ 0x4cc + 8000ff4: 6d5b ldr r3, [r3, #84] @ 0x54 + 8000ff6: f3c3 0383 ubfx r3, r3, #2, #4 + 8000ffa: f8c4 34d0 str.w r3, [r4, #1232] @ 0x4d0 + 8000ffe: 4620 mov r0, r4 + 8001000: f002 fbac bl 800375c + 8001004: 6820 ldr r0, [r4, #0] + 8001006: f001 fc59 bl 80028bc + 800100a: 04c1 lsls r1, r0, #19 + 800100c: d533 bpl.n 8001076 + 800100e: 686b ldr r3, [r5, #4] + 8001010: 6820 ldr r0, [r4, #0] + 8001012: f023 0301 bic.w r3, r3, #1 + 8001016: 606b str r3, [r5, #4] + 8001018: 2110 movs r1, #16 + 800101a: f001 f8b3 bl 8002184 + 800101e: 7920 ldrb r0, [r4, #4] + 8001020: f506 6310 add.w r3, r6, #2304 @ 0x900 + 8001024: f64f 317f movw r1, #64383 @ 0xfb7f + 8001028: 9a03 ldr r2, [sp, #12] + 800102a: 4290 cmp r0, r2 + 800102c: f200 8240 bhi.w 80014b0 + 8001030: 69eb ldr r3, [r5, #28] + 8001032: f043 1301 orr.w r3, r3, #65537 @ 0x10001 + 8001036: 61eb str r3, [r5, #28] + 8001038: 7be3 ldrb r3, [r4, #15] + 800103a: 2b00 cmp r3, #0 + 800103c: f000 8254 beq.w 80014e8 + 8001040: f8d5 3084 ldr.w r3, [r5, #132] @ 0x84 + 8001044: f043 030b orr.w r3, r3, #11 + 8001048: f8c5 3084 str.w r3, [r5, #132] @ 0x84 + 800104c: 6c6b ldr r3, [r5, #68] @ 0x44 + 800104e: f043 030b orr.w r3, r3, #11 + 8001052: 646b str r3, [r5, #68] @ 0x44 + 8001054: f8d6 3800 ldr.w r3, [r6, #2048] @ 0x800 + 8001058: 6820 ldr r0, [r4, #0] + 800105a: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 + 800105e: f8c6 3800 str.w r3, [r6, #2048] @ 0x800 + 8001062: f204 429c addw r2, r4, #1180 @ 0x49c + 8001066: 79a1 ldrb r1, [r4, #6] + 8001068: f001 fc68 bl 800293c + 800106c: 6822 ldr r2, [r4, #0] + 800106e: 6953 ldr r3, [r2, #20] + 8001070: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 8001074: 6153 str r3, [r2, #20] + 8001076: 6820 ldr r0, [r4, #0] + 8001078: f001 fc20 bl 80028bc + 800107c: 0482 lsls r2, r0, #18 + 800107e: d516 bpl.n 80010ae + 8001080: 6820 ldr r0, [r4, #0] + 8001082: f001 fc4d bl 8002920 + 8001086: 6820 ldr r0, [r4, #0] + 8001088: f001 f980 bl 800238c + 800108c: 71e0 strb r0, [r4, #7] + 800108e: 6827 ldr r7, [r4, #0] + 8001090: f000 fb3a bl 8001708 + 8001094: 79e2 ldrb r2, [r4, #7] + 8001096: 4601 mov r1, r0 + 8001098: 4638 mov r0, r7 + 800109a: f000 ffc7 bl 800202c + 800109e: 4620 mov r0, r4 + 80010a0: f002 fadd bl 800365e + 80010a4: 6822 ldr r2, [r4, #0] + 80010a6: 6953 ldr r3, [r2, #20] + 80010a8: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 80010ac: 6153 str r3, [r2, #20] + 80010ae: 6820 ldr r0, [r4, #0] + 80010b0: f001 fc04 bl 80028bc + 80010b4: 0703 lsls r3, r0, #28 + 80010b6: d507 bpl.n 80010c8 + 80010b8: 4620 mov r0, r4 + 80010ba: f002 facc bl 8003656 + 80010be: 6822 ldr r2, [r4, #0] + 80010c0: 6953 ldr r3, [r2, #20] + 80010c2: f003 0308 and.w r3, r3, #8 + 80010c6: 6153 str r3, [r2, #20] + 80010c8: 6820 ldr r0, [r4, #0] + 80010ca: f001 fbf7 bl 80028bc + 80010ce: 0607 lsls r7, r0, #24 + 80010d0: f100 8215 bmi.w 80014fe + 80010d4: 6820 ldr r0, [r4, #0] + 80010d6: f001 fbf1 bl 80028bc + 80010da: 02c0 lsls r0, r0, #11 + 80010dc: d50c bpl.n 80010f8 + 80010de: 46a0 mov r8, r4 + 80010e0: f506 6912 add.w r9, r6, #2336 @ 0x920 + 80010e4: 2701 movs r7, #1 + 80010e6: 7923 ldrb r3, [r4, #4] + 80010e8: 42bb cmp r3, r7 + 80010ea: f200 8221 bhi.w 8001530 + 80010ee: 6822 ldr r2, [r4, #0] + 80010f0: 6953 ldr r3, [r2, #20] + 80010f2: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 80010f6: 6153 str r3, [r2, #20] + 80010f8: 6820 ldr r0, [r4, #0] + 80010fa: f001 fbdf bl 80028bc + 80010fe: 0281 lsls r1, r0, #10 + 8001100: d52b bpl.n 800115a + 8001102: f894 e004 ldrb.w lr, [r4, #4] + 8001106: 4623 mov r3, r4 + 8001108: f506 6132 add.w r1, r6, #2848 @ 0xb20 + 800110c: f04f 0c01 mov.w ip, #1 + 8001110: 45e6 cmp lr, ip + 8001112: d91d bls.n 8001150 + 8001114: f893 727c ldrb.w r7, [r3, #636] @ 0x27c + 8001118: 6808 ldr r0, [r1, #0] + 800111a: 2f01 cmp r7, #1 + 800111c: f040 821e bne.w 800155c + 8001120: 2800 cmp r0, #0 + 8001122: f280 821b bge.w 800155c + 8001126: f8d4 24d4 ldr.w r2, [r4, #1236] @ 0x4d4 + 800112a: ea82 4010 eor.w r0, r2, r0, lsr #16 + 800112e: 07c2 lsls r2, r0, #31 + 8001130: f100 8214 bmi.w 800155c + 8001134: f883 727b strb.w r7, [r3, #635] @ 0x27b + 8001138: 69b0 ldr r0, [r6, #24] + 800113a: f040 0080 orr.w r0, r0, #128 @ 0x80 + 800113e: 61b0 str r0, [r6, #24] + 8001140: 6970 ldr r0, [r6, #20] + 8001142: 0600 lsls r0, r0, #24 + 8001144: f100 820a bmi.w 800155c + 8001148: 686b ldr r3, [r5, #4] + 800114a: f443 7300 orr.w r3, r3, #512 @ 0x200 + 800114e: 606b str r3, [r5, #4] + 8001150: 6822 ldr r2, [r4, #0] + 8001152: 6953 ldr r3, [r2, #20] + 8001154: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8001158: 6153 str r3, [r2, #20] + 800115a: 6820 ldr r0, [r4, #0] + 800115c: f001 fbae bl 80028bc + 8001160: 0041 lsls r1, r0, #1 + 8001162: d507 bpl.n 8001174 + 8001164: 4620 mov r0, r4 + 8001166: f002 fab1 bl 80036cc + 800116a: 6822 ldr r2, [r4, #0] + 800116c: 6953 ldr r3, [r2, #20] + 800116e: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 + 8001172: 6153 str r3, [r2, #20] + 8001174: 6820 ldr r0, [r4, #0] + 8001176: f001 fba1 bl 80028bc + 800117a: 0742 lsls r2, r0, #29 + 800117c: d50a bpl.n 8001194 + 800117e: 6823 ldr r3, [r4, #0] + 8001180: 685d ldr r5, [r3, #4] + 8001182: 076b lsls r3, r5, #29 + 8001184: d502 bpl.n 800118c + 8001186: 4620 mov r0, r4 + 8001188: f002 faa4 bl 80036d4 + 800118c: 6822 ldr r2, [r4, #0] + 800118e: 6853 ldr r3, [r2, #4] + 8001190: 432b orrs r3, r5 + 8001192: 6053 str r3, [r2, #4] + 8001194: b009 add sp, #36 @ 0x24 + 8001196: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800119a: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 + 800119e: f47f aed0 bne.w 8000f42 + 80011a2: 2208 movs r2, #8 + 80011a4: f204 419c addw r1, r4, #1180 @ 0x49c + 80011a8: 4630 mov r0, r6 + 80011aa: f001 fae7 bl 800277c + 80011ae: 2324 movs r3, #36 @ 0x24 + 80011b0: fb03 4707 mla r7, r3, r7, r4 + 80011b4: f3c8 180a ubfx r8, r8, #4, #11 + 80011b8: f8d7 3268 ldr.w r3, [r7, #616] @ 0x268 + 80011bc: 4443 add r3, r8 + 80011be: e6be b.n 8000f3e + 80011c0: 6820 ldr r0, [r4, #0] + 80011c2: f001 fb7f bl 80028c4 + 80011c6: f506 6830 add.w r8, r6, #2816 @ 0xb00 + 80011ca: 9004 str r0, [sp, #16] + 80011cc: 46a2 mov sl, r4 + 80011ce: 2700 movs r7, #0 + 80011d0: 9b04 ldr r3, [sp, #16] + 80011d2: 6820 ldr r0, [r4, #0] + 80011d4: 2b00 cmp r3, #0 + 80011d6: f43f aebf beq.w 8000f58 + 80011da: 9b04 ldr r3, [sp, #16] + 80011dc: 07db lsls r3, r3, #31 + 80011de: d578 bpl.n 80012d2 + 80011e0: fa5f fb87 uxtb.w fp, r7 + 80011e4: 4659 mov r1, fp + 80011e6: f001 fb7d bl 80028e4 + 80011ea: f010 0f01 tst.w r0, #1 + 80011ee: 4681 mov r9, r0 + 80011f0: d01f beq.n 8001232 + 80011f2: 6820 ldr r0, [r4, #0] + 80011f4: 2301 movs r3, #1 + 80011f6: f8c8 3008 str.w r3, [r8, #8] + 80011fa: f894 c006 ldrb.w ip, [r4, #6] + 80011fe: 6c01 ldr r1, [r0, #64] @ 0x40 + 8001200: f500 6330 add.w r3, r0, #2816 @ 0xb00 + 8001204: eb03 1347 add.w r3, r3, r7, lsl #5 + 8001208: f1bc 0f01 cmp.w ip, #1 + 800120c: 689a ldr r2, [r3, #8] + 800120e: f040 808b bne.w 8001328 + 8001212: f012 0f08 tst.w r2, #8 + 8001216: d007 beq.n 8001228 + 8001218: 48b1 ldr r0, [pc, #708] @ (80014e0 ) + 800121a: 4281 cmp r1, r0 + 800121c: d909 bls.n 8001232 + 800121e: 0412 lsls r2, r2, #16 + 8001220: d507 bpl.n 8001232 + 8001222: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001226: e003 b.n 8001230 + 8001228: f012 0f20 tst.w r2, #32 + 800122c: d05a beq.n 80012e4 + 800122e: 2220 movs r2, #32 + 8001230: 609a str r2, [r3, #8] + 8001232: f019 0f08 tst.w r9, #8 + 8001236: d021 beq.n 800127c + 8001238: 2308 movs r3, #8 + 800123a: f8c8 3008 str.w r3, [r8, #8] + 800123e: 6823 ldr r3, [r4, #0] + 8001240: 49a7 ldr r1, [pc, #668] @ (80014e0 ) + 8001242: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001244: f503 6330 add.w r3, r3, #2816 @ 0xb00 + 8001248: eb03 1347 add.w r3, r3, r7, lsl #5 + 800124c: 428a cmp r2, r1 + 800124e: 6898 ldr r0, [r3, #8] + 8001250: d904 bls.n 800125c + 8001252: 0400 lsls r0, r0, #16 + 8001254: bf44 itt mi + 8001256: f44f 4000 movmi.w r0, #32768 @ 0x8000 + 800125a: 6098 strmi r0, [r3, #8] + 800125c: 4620 mov r0, r4 + 800125e: 9205 str r2, [sp, #20] + 8001260: f002 f9e2 bl 8003628 + 8001264: 9a05 ldr r2, [sp, #20] + 8001266: 499e ldr r1, [pc, #632] @ (80014e0 ) + 8001268: 428a cmp r2, r1 + 800126a: d907 bls.n 800127c + 800126c: 79a1 ldrb r1, [r4, #6] + 800126e: 2901 cmp r1, #1 + 8001270: d104 bne.n 800127c + 8001272: 6820 ldr r0, [r4, #0] + 8001274: f204 429c addw r2, r4, #1180 @ 0x49c + 8001278: f001 fb60 bl 800293c + 800127c: f019 0f10 tst.w r9, #16 + 8001280: bf1c itt ne + 8001282: 2310 movne r3, #16 + 8001284: f8c8 3008 strne.w r3, [r8, #8] + 8001288: f019 0f02 tst.w r9, #2 + 800128c: d014 beq.n 80012b8 + 800128e: 6973 ldr r3, [r6, #20] + 8001290: 0619 lsls r1, r3, #24 + 8001292: bf42 ittt mi + 8001294: 686b ldrmi r3, [r5, #4] + 8001296: f443 6380 orrmi.w r3, r3, #1024 @ 0x400 + 800129a: 606b strmi r3, [r5, #4] + 800129c: f89a 3257 ldrb.w r3, [sl, #599] @ 0x257 + 80012a0: 2b01 cmp r3, #1 + 80012a2: d106 bne.n 80012b2 + 80012a4: 2300 movs r3, #0 + 80012a6: f88a 3257 strb.w r3, [sl, #599] @ 0x257 + 80012aa: 4659 mov r1, fp + 80012ac: 4620 mov r0, r4 + 80012ae: f002 fa05 bl 80036bc + 80012b2: 2302 movs r3, #2 + 80012b4: f8c8 3008 str.w r3, [r8, #8] + 80012b8: f019 0f20 tst.w r9, #32 + 80012bc: bf1c itt ne + 80012be: 2320 movne r3, #32 + 80012c0: f8c8 3008 strne.w r3, [r8, #8] + 80012c4: f419 5f00 tst.w r9, #8192 @ 0x2000 + 80012c8: bf1c itt ne + 80012ca: f44f 5300 movne.w r3, #8192 @ 0x2000 + 80012ce: f8c8 3008 strne.w r3, [r8, #8] + 80012d2: 9b04 ldr r3, [sp, #16] + 80012d4: 085b lsrs r3, r3, #1 + 80012d6: 3701 adds r7, #1 + 80012d8: 9304 str r3, [sp, #16] + 80012da: f108 0820 add.w r8, r8, #32 + 80012de: f10a 0a24 add.w sl, sl, #36 @ 0x24 + 80012e2: e775 b.n 80011d0 + 80012e4: f8df c1f8 ldr.w ip, [pc, #504] @ 80014e0 + 80012e8: 4561 cmp r1, ip + 80012ea: d901 bls.n 80012f0 + 80012ec: 0412 lsls r2, r2, #16 + 80012ee: d498 bmi.n 8001222 + 80012f0: 691a ldr r2, [r3, #16] + 80012f2: f8da 3274 ldr.w r3, [sl, #628] @ 0x274 + 80012f6: f3c2 0212 ubfx r2, r2, #0, #19 + 80012fa: 1a9b subs r3, r3, r2 + 80012fc: f8ca 3268 str.w r3, [sl, #616] @ 0x268 + 8001300: b96f cbnz r7, 800131e + 8001302: f8d4 2264 ldr.w r2, [r4, #612] @ 0x264 + 8001306: b92a cbnz r2, 8001314 + 8001308: f204 429c addw r2, r4, #1180 @ 0x49c + 800130c: 2101 movs r1, #1 + 800130e: f001 fb15 bl 800293c + 8001312: e004 b.n 800131e + 8001314: f8d4 2260 ldr.w r2, [r4, #608] @ 0x260 + 8001318: 441a add r2, r3 + 800131a: f8c4 2260 str.w r2, [r4, #608] @ 0x260 + 800131e: 4659 mov r1, fp + 8001320: 4620 mov r0, r4 + 8001322: f002 f987 bl 8003634 + 8001326: e784 b.n 8001232 + 8001328: f8df c1b8 ldr.w ip, [pc, #440] @ 80014e4 + 800132c: 4561 cmp r1, ip + 800132e: d107 bne.n 8001340 + 8001330: 0411 lsls r1, r2, #16 + 8001332: f53f af76 bmi.w 8001222 + 8001336: 0692 lsls r2, r2, #26 + 8001338: d5f1 bpl.n 800131e + 800133a: 2220 movs r2, #32 + 800133c: 609a str r2, [r3, #8] + 800133e: e7ee b.n 800131e + 8001340: 2f00 cmp r7, #0 + 8001342: d1ec bne.n 800131e + 8001344: f8d4 3264 ldr.w r3, [r4, #612] @ 0x264 + 8001348: 2b00 cmp r3, #0 + 800134a: d1e8 bne.n 800131e + 800134c: f204 429c addw r2, r4, #1180 @ 0x49c + 8001350: 4639 mov r1, r7 + 8001352: e7dc b.n 800130e + 8001354: 9b04 ldr r3, [sp, #16] + 8001356: 07da lsls r2, r3, #31 + 8001358: f140 8099 bpl.w 800148e + 800135c: fa5f f38a uxtb.w r3, sl + 8001360: 4619 mov r1, r3 + 8001362: 9305 str r3, [sp, #20] + 8001364: f001 fac7 bl 80028f6 + 8001368: f010 0f01 tst.w r0, #1 + 800136c: 4680 mov r8, r0 + 800136e: d01f beq.n 80013b0 + 8001370: 6b6b ldr r3, [r5, #52] @ 0x34 + 8001372: 2101 movs r1, #1 + 8001374: f00a 020f and.w r2, sl, #15 + 8001378: fa01 f202 lsl.w r2, r1, r2 + 800137c: ea23 0302 bic.w r3, r3, r2 + 8001380: 636b str r3, [r5, #52] @ 0x34 + 8001382: f8cb 1008 str.w r1, [fp, #8] + 8001386: 79a1 ldrb r1, [r4, #6] + 8001388: 2901 cmp r1, #1 + 800138a: d10d bne.n 80013a8 + 800138c: e9d7 2307 ldrd r2, r3, [r7, #28] + 8001390: 4413 add r3, r2 + 8001392: 623b str r3, [r7, #32] + 8001394: f1ba 0f00 cmp.w sl, #0 + 8001398: d106 bne.n 80013a8 + 800139a: 6a63 ldr r3, [r4, #36] @ 0x24 + 800139c: b923 cbnz r3, 80013a8 + 800139e: 6820 ldr r0, [r4, #0] + 80013a0: f204 429c addw r2, r4, #1180 @ 0x49c + 80013a4: f001 faca bl 800293c + 80013a8: 9905 ldr r1, [sp, #20] + 80013aa: 4620 mov r0, r4 + 80013ac: f002 f94b bl 8003646 + 80013b0: f018 0f08 tst.w r8, #8 + 80013b4: bf1c itt ne + 80013b6: 2308 movne r3, #8 + 80013b8: f8cb 3008 strne.w r3, [fp, #8] + 80013bc: f018 0f10 tst.w r8, #16 + 80013c0: bf1c itt ne + 80013c2: 2310 movne r3, #16 + 80013c4: f8cb 3008 strne.w r3, [fp, #8] + 80013c8: f018 0f40 tst.w r8, #64 @ 0x40 + 80013cc: bf1c itt ne + 80013ce: 2340 movne r3, #64 @ 0x40 + 80013d0: f8cb 3008 strne.w r3, [fp, #8] + 80013d4: f018 0f02 tst.w r8, #2 + 80013d8: d00f beq.n 80013fa + 80013da: 4651 mov r1, sl + 80013dc: 4630 mov r0, r6 + 80013de: f000 fed1 bl 8002184 + 80013e2: 7dfb ldrb r3, [r7, #23] + 80013e4: 2b01 cmp r3, #1 + 80013e6: d105 bne.n 80013f4 + 80013e8: 2300 movs r3, #0 + 80013ea: 9905 ldr r1, [sp, #20] + 80013ec: 75fb strb r3, [r7, #23] + 80013ee: 4620 mov r0, r4 + 80013f0: f002 f968 bl 80036c4 + 80013f4: 2302 movs r3, #2 + 80013f6: f8cb 3008 str.w r3, [fp, #8] + 80013fa: 6823 ldr r3, [r4, #0] + 80013fc: 9306 str r3, [sp, #24] + 80013fe: f018 0f80 tst.w r8, #128 @ 0x80 + 8001402: d044 beq.n 800148e + 8001404: e9d7 3209 ldrd r3, r2, [r7, #36] @ 0x24 + 8001408: 429a cmp r2, r3 + 800140a: d840 bhi.n 800148e + 800140c: eba3 0802 sub.w r8, r3, r2 + 8001410: 69fb ldr r3, [r7, #28] + 8001412: 4598 cmp r8, r3 + 8001414: bf28 it cs + 8001416: 4698 movcs r8, r3 + 8001418: 9b06 ldr r3, [sp, #24] + 800141a: f503 6310 add.w r3, r3, #2304 @ 0x900 + 800141e: f108 0803 add.w r8, r8, #3 + 8001422: eb03 134a add.w r3, r3, sl, lsl #5 + 8001426: ea4f 0898 mov.w r8, r8, lsr #2 + 800142a: 9307 str r3, [sp, #28] + 800142c: 9b07 ldr r3, [sp, #28] + 800142e: 6999 ldr r1, [r3, #24] + 8001430: b289 uxth r1, r1 + 8001432: 4541 cmp r1, r8 + 8001434: e9d7 3209 ldrd r3, r2, [r7, #36] @ 0x24 + 8001438: d327 bcc.n 800148a + 800143a: 4293 cmp r3, r2 + 800143c: d80b bhi.n 8001456 + 800143e: 9b06 ldr r3, [sp, #24] + 8001440: f00a 000f and.w r0, sl, #15 + 8001444: f8d3 2834 ldr.w r2, [r3, #2100] @ 0x834 + 8001448: 2101 movs r1, #1 + 800144a: 4081 lsls r1, r0 + 800144c: ea22 0201 bic.w r2, r2, r1 + 8001450: f8c3 2834 str.w r2, [r3, #2100] @ 0x834 + 8001454: e01b b.n 800148e + 8001456: eba3 0902 sub.w r9, r3, r2 + 800145a: 69fb ldr r3, [r7, #28] + 800145c: 9a05 ldr r2, [sp, #20] + 800145e: 9806 ldr r0, [sp, #24] + 8001460: 4599 cmp r9, r3 + 8001462: bf28 it cs + 8001464: 4699 movcs r9, r3 + 8001466: 79a3 ldrb r3, [r4, #6] + 8001468: 9300 str r3, [sp, #0] + 800146a: 6a39 ldr r1, [r7, #32] + 800146c: fa1f f389 uxth.w r3, r9 + 8001470: f001 f86e bl 8002550 + 8001474: 6a3b ldr r3, [r7, #32] + 8001476: 444b add r3, r9 + 8001478: 623b str r3, [r7, #32] + 800147a: 6abb ldr r3, [r7, #40] @ 0x28 + 800147c: f109 0803 add.w r8, r9, #3 + 8001480: 444b add r3, r9 + 8001482: ea4f 0898 mov.w r8, r8, lsr #2 + 8001486: 62bb str r3, [r7, #40] @ 0x28 + 8001488: e7d0 b.n 800142c + 800148a: 4293 cmp r3, r2 + 800148c: d9d7 bls.n 800143e + 800148e: 9b04 ldr r3, [sp, #16] + 8001490: 085b lsrs r3, r3, #1 + 8001492: f10a 0a01 add.w sl, sl, #1 + 8001496: 9304 str r3, [sp, #16] + 8001498: 3724 adds r7, #36 @ 0x24 + 800149a: f10b 0b20 add.w fp, fp, #32 + 800149e: e569 b.n 8000f74 + 80014a0: 4620 mov r0, r4 + 80014a2: f002 f907 bl 80036b4 + 80014a6: e57e b.n 8000fa6 + 80014a8: 4620 mov r0, r4 + 80014aa: f002 f8eb bl 8003684 + 80014ae: e5a9 b.n 8001004 + 80014b0: 6099 str r1, [r3, #8] + 80014b2: 681a ldr r2, [r3, #0] + 80014b4: f422 1200 bic.w r2, r2, #2097152 @ 0x200000 + 80014b8: 601a str r2, [r3, #0] + 80014ba: f8c3 1208 str.w r1, [r3, #520] @ 0x208 + 80014be: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 + 80014c2: f422 1200 bic.w r2, r2, #2097152 @ 0x200000 + 80014c6: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + 80014ca: f8d3 2200 ldr.w r2, [r3, #512] @ 0x200 + 80014ce: f042 6200 orr.w r2, r2, #134217728 @ 0x8000000 + 80014d2: f8c3 2200 str.w r2, [r3, #512] @ 0x200 + 80014d6: 9a03 ldr r2, [sp, #12] + 80014d8: 3201 adds r2, #1 + 80014da: 9203 str r2, [sp, #12] + 80014dc: 3320 adds r3, #32 + 80014de: e5a3 b.n 8001028 + 80014e0: 4f54300a .word 0x4f54300a + 80014e4: 4f54310a .word 0x4f54310a + 80014e8: 696b ldr r3, [r5, #20] + 80014ea: f443 5300 orr.w r3, r3, #8192 @ 0x2000 + 80014ee: f043 032b orr.w r3, r3, #43 @ 0x2b + 80014f2: 616b str r3, [r5, #20] + 80014f4: 692b ldr r3, [r5, #16] + 80014f6: f043 030b orr.w r3, r3, #11 + 80014fa: 612b str r3, [r5, #16] + 80014fc: e5aa b.n 8001054 + 80014fe: 69b3 ldr r3, [r6, #24] + 8001500: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8001504: 61b3 str r3, [r6, #24] + 8001506: 2701 movs r7, #1 + 8001508: f204 2857 addw r8, r4, #599 @ 0x257 + 800150c: f04f 0924 mov.w r9, #36 @ 0x24 + 8001510: 7923 ldrb r3, [r4, #4] + 8001512: 42bb cmp r3, r7 + 8001514: f67f adde bls.w 80010d4 + 8001518: fb09 f307 mul.w r3, r9, r7 + 800151c: f818 3003 ldrb.w r3, [r8, r3] + 8001520: 2b01 cmp r3, #1 + 8001522: d103 bne.n 800152c + 8001524: b2f9 uxtb r1, r7 + 8001526: 4620 mov r0, r4 + 8001528: f7ff fca8 bl 8000e7c + 800152c: 3701 adds r7, #1 + 800152e: e7ef b.n 8001510 + 8001530: f898 303c ldrb.w r3, [r8, #60] @ 0x3c + 8001534: f8d9 2000 ldr.w r2, [r9] + 8001538: 2b01 cmp r3, #1 + 800153a: d109 bne.n 8001550 + 800153c: 2a00 cmp r2, #0 + 800153e: da07 bge.n 8001550 + 8001540: f067 017f orn r1, r7, #127 @ 0x7f + 8001544: f888 303b strb.w r3, [r8, #59] @ 0x3b + 8001548: b2c9 uxtb r1, r1 + 800154a: 4620 mov r0, r4 + 800154c: f7ff fc96 bl 8000e7c + 8001550: 3701 adds r7, #1 + 8001552: f108 0824 add.w r8, r8, #36 @ 0x24 + 8001556: f109 0920 add.w r9, r9, #32 + 800155a: e5c4 b.n 80010e6 + 800155c: f10c 0c01 add.w ip, ip, #1 + 8001560: 3324 adds r3, #36 @ 0x24 + 8001562: 3120 adds r1, #32 + 8001564: e5d4 b.n 8001110 + 8001566: bf00 nop + +08001568 : + 8001568: 6800 ldr r0, [r0, #0] + 800156a: b570 push {r4, r5, r6, lr} + 800156c: 6a43 ldr r3, [r0, #36] @ 0x24 + 800156e: 0412 lsls r2, r2, #16 + 8001570: b919 cbnz r1, 800157a + 8001572: 4313 orrs r3, r2 + 8001574: 6283 str r3, [r0, #40] @ 0x28 + 8001576: 2000 movs r0, #0 + 8001578: bd70 pop {r4, r5, r6, pc} + 800157a: 6a84 ldr r4, [r0, #40] @ 0x28 + 800157c: 1e4e subs r6, r1, #1 + 800157e: eb03 4314 add.w r3, r3, r4, lsr #16 + 8001582: 2400 movs r4, #0 + 8001584: 42b4 cmp r4, r6 + 8001586: d305 bcc.n 8001594 + 8001588: 313f adds r1, #63 @ 0x3f + 800158a: eb00 0081 add.w r0, r0, r1, lsl #2 + 800158e: 4313 orrs r3, r2 + 8001590: 6043 str r3, [r0, #4] + 8001592: e7f0 b.n 8001576 + 8001594: f104 0540 add.w r5, r4, #64 @ 0x40 + 8001598: eb00 0585 add.w r5, r0, r5, lsl #2 + 800159c: 3401 adds r4, #1 + 800159e: 686d ldr r5, [r5, #4] + 80015a0: eb03 4315 add.w r3, r3, r5, lsr #16 + 80015a4: e7ee b.n 8001584 + +080015a6 : + 80015a6: 6803 ldr r3, [r0, #0] + 80015a8: 2000 movs r0, #0 + 80015aa: 6259 str r1, [r3, #36] @ 0x24 + 80015ac: 4770 bx lr + +080015ae : + 80015ae: 4603 mov r3, r0 + 80015b0: 2101 movs r1, #1 + 80015b2: 6802 ldr r2, [r0, #0] + 80015b4: f8c0 14d8 str.w r1, [r0, #1240] @ 0x4d8 + 80015b8: 2000 movs r0, #0 + 80015ba: f883 04cc strb.w r0, [r3, #1228] @ 0x4cc + 80015be: 6993 ldr r3, [r2, #24] + 80015c0: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 + 80015c4: 6193 str r3, [r2, #24] + 80015c6: 6d53 ldr r3, [r2, #84] @ 0x54 + 80015c8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 80015cc: f043 0303 orr.w r3, r3, #3 + 80015d0: 6553 str r3, [r2, #84] @ 0x54 + 80015d2: 4770 bx lr + +080015d4 : + 80015d4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 80015d8: 460d mov r5, r1 + 80015da: 4604 mov r4, r0 + 80015dc: b910 cbnz r0, 80015e4 + 80015de: 2001 movs r0, #1 + 80015e0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80015e4: 4b43 ldr r3, [pc, #268] @ (80016f4 ) + 80015e6: 681a ldr r2, [r3, #0] + 80015e8: f002 020f and.w r2, r2, #15 + 80015ec: 428a cmp r2, r1 + 80015ee: d328 bcc.n 8001642 + 80015f0: 6821 ldr r1, [r4, #0] + 80015f2: 078f lsls r7, r1, #30 + 80015f4: d42d bmi.n 8001652 + 80015f6: 07c8 lsls r0, r1, #31 + 80015f8: d440 bmi.n 800167c + 80015fa: 4b3e ldr r3, [pc, #248] @ (80016f4 ) + 80015fc: 681a ldr r2, [r3, #0] + 80015fe: f002 020f and.w r2, r2, #15 + 8001602: 42aa cmp r2, r5 + 8001604: d865 bhi.n 80016d2 + 8001606: 6822 ldr r2, [r4, #0] + 8001608: 0751 lsls r1, r2, #29 + 800160a: d46b bmi.n 80016e4 + 800160c: 0713 lsls r3, r2, #28 + 800160e: d507 bpl.n 8001620 + 8001610: 4a39 ldr r2, [pc, #228] @ (80016f8 ) + 8001612: 6921 ldr r1, [r4, #16] + 8001614: 6893 ldr r3, [r2, #8] + 8001616: f423 4360 bic.w r3, r3, #57344 @ 0xe000 + 800161a: ea43 03c1 orr.w r3, r3, r1, lsl #3 + 800161e: 6093 str r3, [r2, #8] + 8001620: f000 fa82 bl 8001b28 + 8001624: 4b34 ldr r3, [pc, #208] @ (80016f8 ) + 8001626: 4a35 ldr r2, [pc, #212] @ (80016fc ) + 8001628: 689b ldr r3, [r3, #8] + 800162a: f3c3 1303 ubfx r3, r3, #4, #4 + 800162e: 5cd3 ldrb r3, [r2, r3] + 8001630: 40d8 lsrs r0, r3 + 8001632: 4b33 ldr r3, [pc, #204] @ (8001700 ) + 8001634: 6018 str r0, [r3, #0] + 8001636: 4b33 ldr r3, [pc, #204] @ (8001704 ) + 8001638: 6818 ldr r0, [r3, #0] + 800163a: f7ff f8cb bl 80007d4 + 800163e: 2000 movs r0, #0 + 8001640: e7ce b.n 80015e0 + 8001642: b2ca uxtb r2, r1 + 8001644: 701a strb r2, [r3, #0] + 8001646: 681b ldr r3, [r3, #0] + 8001648: f003 030f and.w r3, r3, #15 + 800164c: 428b cmp r3, r1 + 800164e: d1c6 bne.n 80015de + 8001650: e7ce b.n 80015f0 + 8001652: 4b29 ldr r3, [pc, #164] @ (80016f8 ) + 8001654: f011 0f04 tst.w r1, #4 + 8001658: bf1e ittt ne + 800165a: 689a ldrne r2, [r3, #8] + 800165c: f442 52e0 orrne.w r2, r2, #7168 @ 0x1c00 + 8001660: 609a strne r2, [r3, #8] + 8001662: 070e lsls r6, r1, #28 + 8001664: bf42 ittt mi + 8001666: 689a ldrmi r2, [r3, #8] + 8001668: f442 4260 orrmi.w r2, r2, #57344 @ 0xe000 + 800166c: 609a strmi r2, [r3, #8] + 800166e: 689a ldr r2, [r3, #8] + 8001670: 68a0 ldr r0, [r4, #8] + 8001672: f022 02f0 bic.w r2, r2, #240 @ 0xf0 + 8001676: 4302 orrs r2, r0 + 8001678: 609a str r2, [r3, #8] + 800167a: e7bc b.n 80015f6 + 800167c: 6862 ldr r2, [r4, #4] + 800167e: 4b1e ldr r3, [pc, #120] @ (80016f8 ) + 8001680: 2a01 cmp r2, #1 + 8001682: d11c bne.n 80016be + 8001684: 681b ldr r3, [r3, #0] + 8001686: f413 3f00 tst.w r3, #131072 @ 0x20000 + 800168a: d0a8 beq.n 80015de + 800168c: 4e1a ldr r6, [pc, #104] @ (80016f8 ) + 800168e: 68b3 ldr r3, [r6, #8] + 8001690: f023 0303 bic.w r3, r3, #3 + 8001694: 4313 orrs r3, r2 + 8001696: 60b3 str r3, [r6, #8] + 8001698: f7ff f8e6 bl 8000868 + 800169c: f241 3888 movw r8, #5000 @ 0x1388 + 80016a0: 4607 mov r7, r0 + 80016a2: 68b3 ldr r3, [r6, #8] + 80016a4: 6862 ldr r2, [r4, #4] + 80016a6: f003 030c and.w r3, r3, #12 + 80016aa: ebb3 0f82 cmp.w r3, r2, lsl #2 + 80016ae: d0a4 beq.n 80015fa + 80016b0: f7ff f8da bl 8000868 + 80016b4: 1bc0 subs r0, r0, r7 + 80016b6: 4540 cmp r0, r8 + 80016b8: d9f3 bls.n 80016a2 + 80016ba: 2003 movs r0, #3 + 80016bc: e790 b.n 80015e0 + 80016be: 1e91 subs r1, r2, #2 + 80016c0: 2901 cmp r1, #1 + 80016c2: 681b ldr r3, [r3, #0] + 80016c4: d802 bhi.n 80016cc + 80016c6: f013 7f00 tst.w r3, #33554432 @ 0x2000000 + 80016ca: e7de b.n 800168a + 80016cc: f013 0f02 tst.w r3, #2 + 80016d0: e7db b.n 800168a + 80016d2: b2ea uxtb r2, r5 + 80016d4: 701a strb r2, [r3, #0] + 80016d6: 681b ldr r3, [r3, #0] + 80016d8: f003 030f and.w r3, r3, #15 + 80016dc: 42ab cmp r3, r5 + 80016de: f47f af7e bne.w 80015de + 80016e2: e790 b.n 8001606 + 80016e4: 4904 ldr r1, [pc, #16] @ (80016f8 ) + 80016e6: 68e0 ldr r0, [r4, #12] + 80016e8: 688b ldr r3, [r1, #8] + 80016ea: f423 53e0 bic.w r3, r3, #7168 @ 0x1c00 + 80016ee: 4303 orrs r3, r0 + 80016f0: 608b str r3, [r1, #8] + 80016f2: e78b b.n 800160c + 80016f4: 40023c00 .word 0x40023c00 + 80016f8: 40023800 .word 0x40023800 + 80016fc: 080038dc .word 0x080038dc + 8001700: 20000000 .word 0x20000000 + 8001704: 20000008 .word 0x20000008 + +08001708 : + 8001708: 4b01 ldr r3, [pc, #4] @ (8001710 ) + 800170a: 6818 ldr r0, [r3, #0] + 800170c: 4770 bx lr + 800170e: bf00 nop + 8001710: 20000000 .word 0x20000000 + +08001714 : + 8001714: 6803 ldr r3, [r0, #0] + 8001716: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + 800171a: f013 0601 ands.w r6, r3, #1 + 800171e: 4604 mov r4, r0 + 8001720: d00b beq.n 800173a + 8001722: 49ac ldr r1, [pc, #688] @ (80019d4 ) + 8001724: 6b86 ldr r6, [r0, #56] @ 0x38 + 8001726: f8d1 208c ldr.w r2, [r1, #140] @ 0x8c + 800172a: f022 62c0 bic.w r2, r2, #100663296 @ 0x6000000 + 800172e: 4332 orrs r2, r6 + 8001730: fab6 f686 clz r6, r6 + 8001734: f8c1 208c str.w r2, [r1, #140] @ 0x8c + 8001738: 0976 lsrs r6, r6, #5 + 800173a: 079a lsls r2, r3, #30 + 800173c: d50b bpl.n 8001756 + 800173e: 48a5 ldr r0, [pc, #660] @ (80019d4 ) + 8001740: 6be1 ldr r1, [r4, #60] @ 0x3c + 8001742: f8d0 208c ldr.w r2, [r0, #140] @ 0x8c + 8001746: f022 52c0 bic.w r2, r2, #402653184 @ 0x18000000 + 800174a: 430a orrs r2, r1 + 800174c: 2900 cmp r1, #0 + 800174e: f8c0 208c str.w r2, [r0, #140] @ 0x8c + 8001752: bf08 it eq + 8001754: 2601 moveq r6, #1 + 8001756: f013 0504 ands.w r5, r3, #4 + 800175a: d012 beq.n 8001782 + 800175c: 499d ldr r1, [pc, #628] @ (80019d4 ) + 800175e: 6b25 ldr r5, [r4, #48] @ 0x30 + 8001760: f8d1 208c ldr.w r2, [r1, #140] @ 0x8c + 8001764: f5b5 1f80 cmp.w r5, #1048576 @ 0x100000 + 8001768: f422 1240 bic.w r2, r2, #3145728 @ 0x300000 + 800176c: ea42 0205 orr.w r2, r2, r5 + 8001770: bf18 it ne + 8001772: fab5 f585 clzne r5, r5 + 8001776: f8c1 208c str.w r2, [r1, #140] @ 0x8c + 800177a: bf12 itee ne + 800177c: 096d lsrne r5, r5, #5 + 800177e: 2500 moveq r5, #0 + 8001780: 2601 moveq r6, #1 + 8001782: 071f lsls r7, r3, #28 + 8001784: d50f bpl.n 80017a6 + 8001786: 4893 ldr r0, [pc, #588] @ (80019d4 ) + 8001788: 6b61 ldr r1, [r4, #52] @ 0x34 + 800178a: f8d0 208c ldr.w r2, [r0, #140] @ 0x8c + 800178e: f422 0240 bic.w r2, r2, #12582912 @ 0xc00000 + 8001792: 430a orrs r2, r1 + 8001794: f5b1 0f80 cmp.w r1, #4194304 @ 0x400000 + 8001798: f8c0 208c str.w r2, [r0, #140] @ 0x8c + 800179c: f000 810c beq.w 80019b8 + 80017a0: 2900 cmp r1, #0 + 80017a2: bf08 it eq + 80017a4: 2501 moveq r5, #1 + 80017a6: 0698 lsls r0, r3, #26 + 80017a8: d534 bpl.n 8001814 + 80017aa: 2300 movs r3, #0 + 80017ac: 9301 str r3, [sp, #4] + 80017ae: 4b89 ldr r3, [pc, #548] @ (80019d4 ) + 80017b0: 4f89 ldr r7, [pc, #548] @ (80019d8 ) + 80017b2: 6c1a ldr r2, [r3, #64] @ 0x40 + 80017b4: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 + 80017b8: 641a str r2, [r3, #64] @ 0x40 + 80017ba: 6c1b ldr r3, [r3, #64] @ 0x40 + 80017bc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80017c0: 9301 str r3, [sp, #4] + 80017c2: 9b01 ldr r3, [sp, #4] + 80017c4: 683b ldr r3, [r7, #0] + 80017c6: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80017ca: 603b str r3, [r7, #0] + 80017cc: f7ff f84c bl 8000868 + 80017d0: 4680 mov r8, r0 + 80017d2: 683b ldr r3, [r7, #0] + 80017d4: 05d9 lsls r1, r3, #23 + 80017d6: f140 80f1 bpl.w 80019bc + 80017da: 4f7e ldr r7, [pc, #504] @ (80019d4 ) + 80017dc: 6c22 ldr r2, [r4, #64] @ 0x40 + 80017de: 6f3b ldr r3, [r7, #112] @ 0x70 + 80017e0: f413 7340 ands.w r3, r3, #768 @ 0x300 + 80017e4: f040 80fe bne.w 80019e4 + 80017e8: 6c23 ldr r3, [r4, #64] @ 0x40 + 80017ea: f403 7240 and.w r2, r3, #768 @ 0x300 + 80017ee: f5b2 7f40 cmp.w r2, #768 @ 0x300 + 80017f2: 4a78 ldr r2, [pc, #480] @ (80019d4 ) + 80017f4: f040 811a bne.w 8001a2c + 80017f8: 6891 ldr r1, [r2, #8] + 80017fa: f023 4070 bic.w r0, r3, #4026531840 @ 0xf0000000 + 80017fe: f421 11f8 bic.w r1, r1, #2031616 @ 0x1f0000 + 8001802: f420 7040 bic.w r0, r0, #768 @ 0x300 + 8001806: 4301 orrs r1, r0 + 8001808: 6091 str r1, [r2, #8] + 800180a: 6f11 ldr r1, [r2, #112] @ 0x70 + 800180c: f3c3 030b ubfx r3, r3, #0, #12 + 8001810: 430b orrs r3, r1 + 8001812: 6713 str r3, [r2, #112] @ 0x70 + 8001814: 6823 ldr r3, [r4, #0] + 8001816: 06d8 lsls r0, r3, #27 + 8001818: bf42 ittt mi + 800181a: 4b70 ldrmi r3, [pc, #448] @ (80019dc ) + 800181c: f894 2058 ldrbmi.w r2, [r4, #88] @ 0x58 + 8001820: f8c3 21e0 strmi.w r2, [r3, #480] @ 0x1e0 + 8001824: 6823 ldr r3, [r4, #0] + 8001826: 0619 lsls r1, r3, #24 + 8001828: d508 bpl.n 800183c + 800182a: 496a ldr r1, [pc, #424] @ (80019d4 ) + 800182c: 6ce0 ldr r0, [r4, #76] @ 0x4c + 800182e: f8d1 2094 ldr.w r2, [r1, #148] @ 0x94 + 8001832: f422 0240 bic.w r2, r2, #12582912 @ 0xc00000 + 8001836: 4302 orrs r2, r0 + 8001838: f8c1 2094 str.w r2, [r1, #148] @ 0x94 + 800183c: 065a lsls r2, r3, #25 + 800183e: d508 bpl.n 8001852 + 8001840: 4964 ldr r1, [pc, #400] @ (80019d4 ) + 8001842: 6ca0 ldr r0, [r4, #72] @ 0x48 + 8001844: f8d1 2094 ldr.w r2, [r1, #148] @ 0x94 + 8001848: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000 + 800184c: 4302 orrs r2, r0 + 800184e: f8c1 2094 str.w r2, [r1, #148] @ 0x94 + 8001852: 05df lsls r7, r3, #23 + 8001854: d50c bpl.n 8001870 + 8001856: 485f ldr r0, [pc, #380] @ (80019d4 ) + 8001858: 6d61 ldr r1, [r4, #84] @ 0x54 + 800185a: f8d0 2094 ldr.w r2, [r0, #148] @ 0x94 + 800185e: f022 6200 bic.w r2, r2, #134217728 @ 0x8000000 + 8001862: 430a orrs r2, r1 + 8001864: f1b1 6f00 cmp.w r1, #134217728 @ 0x8000000 + 8001868: f8c0 2094 str.w r2, [r0, #148] @ 0x94 + 800186c: bf08 it eq + 800186e: 2501 moveq r5, #1 + 8001870: 0598 lsls r0, r3, #22 + 8001872: d508 bpl.n 8001886 + 8001874: 4957 ldr r1, [pc, #348] @ (80019d4 ) + 8001876: 6c60 ldr r0, [r4, #68] @ 0x44 + 8001878: f8d1 2094 ldr.w r2, [r1, #148] @ 0x94 + 800187c: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 + 8001880: 4302 orrs r2, r0 + 8001882: f8c1 2094 str.w r2, [r1, #148] @ 0x94 + 8001886: 0559 lsls r1, r3, #21 + 8001888: f100 80d4 bmi.w 8001a34 + 800188c: 2e01 cmp r6, #1 + 800188e: f040 80df bne.w 8001a50 + 8001892: 4b53 ldr r3, [pc, #332] @ (80019e0 ) + 8001894: 4f4f ldr r7, [pc, #316] @ (80019d4 ) + 8001896: 2200 movs r2, #0 + 8001898: 669a str r2, [r3, #104] @ 0x68 + 800189a: f7fe ffe5 bl 8000868 + 800189e: 4606 mov r6, r0 + 80018a0: 683b ldr r3, [r7, #0] + 80018a2: 011a lsls r2, r3, #4 + 80018a4: f100 8129 bmi.w 8001afa + 80018a8: 6822 ldr r2, [r4, #0] + 80018aa: 07d3 lsls r3, r2, #31 + 80018ac: d501 bpl.n 80018b2 + 80018ae: 6ba3 ldr r3, [r4, #56] @ 0x38 + 80018b0: b11b cbz r3, 80018ba + 80018b2: 0797 lsls r7, r2, #30 + 80018b4: d515 bpl.n 80018e2 + 80018b6: 6be3 ldr r3, [r4, #60] @ 0x3c + 80018b8: b99b cbnz r3, 80018e2 + 80018ba: 4946 ldr r1, [pc, #280] @ (80019d4 ) + 80018bc: f8d1 3084 ldr.w r3, [r1, #132] @ 0x84 + 80018c0: f8d1 0084 ldr.w r0, [r1, #132] @ 0x84 + 80018c4: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 80018c8: f000 6070 and.w r0, r0, #251658240 @ 0xf000000 + 80018cc: 4303 orrs r3, r0 + 80018ce: 6860 ldr r0, [r4, #4] + 80018d0: 4303 orrs r3, r0 + 80018d2: 68a0 ldr r0, [r4, #8] + 80018d4: ea43 1380 orr.w r3, r3, r0, lsl #6 + 80018d8: 6960 ldr r0, [r4, #20] + 80018da: ea43 7300 orr.w r3, r3, r0, lsl #28 + 80018de: f8c1 3084 str.w r3, [r1, #132] @ 0x84 + 80018e2: 0756 lsls r6, r2, #29 + 80018e4: d503 bpl.n 80018ee + 80018e6: 6b23 ldr r3, [r4, #48] @ 0x30 + 80018e8: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 80018ec: d005 beq.n 80018fa + 80018ee: 0710 lsls r0, r2, #28 + 80018f0: d520 bpl.n 8001934 + 80018f2: 6b63 ldr r3, [r4, #52] @ 0x34 + 80018f4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 80018f8: d11c bne.n 8001934 + 80018fa: 4936 ldr r1, [pc, #216] @ (80019d4 ) + 80018fc: f8d1 3084 ldr.w r3, [r1, #132] @ 0x84 + 8001900: f8d1 0084 ldr.w r0, [r1, #132] @ 0x84 + 8001904: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8001908: f000 40e0 and.w r0, r0, #1879048192 @ 0x70000000 + 800190c: 4303 orrs r3, r0 + 800190e: 6860 ldr r0, [r4, #4] + 8001910: 4303 orrs r3, r0 + 8001912: 68a0 ldr r0, [r4, #8] + 8001914: ea43 1380 orr.w r3, r3, r0, lsl #6 + 8001918: 6920 ldr r0, [r4, #16] + 800191a: ea43 6300 orr.w r3, r3, r0, lsl #24 + 800191e: f8c1 3084 str.w r3, [r1, #132] @ 0x84 + 8001922: f8d1 008c ldr.w r0, [r1, #140] @ 0x8c + 8001926: 6aa3 ldr r3, [r4, #40] @ 0x28 + 8001928: f020 001f bic.w r0, r0, #31 + 800192c: 3b01 subs r3, #1 + 800192e: 4303 orrs r3, r0 + 8001930: f8c1 308c str.w r3, [r1, #140] @ 0x8c + 8001934: 0551 lsls r1, r2, #21 + 8001936: d51b bpl.n 8001970 + 8001938: 6d23 ldr r3, [r4, #80] @ 0x50 + 800193a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 800193e: d117 bne.n 8001970 + 8001940: 4824 ldr r0, [pc, #144] @ (80019d4 ) + 8001942: 6866 ldr r6, [r4, #4] + 8001944: f8d0 1084 ldr.w r1, [r0, #132] @ 0x84 + 8001948: f8d0 3084 ldr.w r3, [r0, #132] @ 0x84 + 800194c: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 + 8001950: 4333 orrs r3, r6 + 8001952: 68a6 ldr r6, [r4, #8] + 8001954: f3c1 4101 ubfx r1, r1, #16, #2 + 8001958: 3101 adds r1, #1 + 800195a: ea43 1386 orr.w r3, r3, r6, lsl #6 + 800195e: ea43 6341 orr.w r3, r3, r1, lsl #25 + 8001962: 68e1 ldr r1, [r4, #12] + 8001964: 0849 lsrs r1, r1, #1 + 8001966: 3901 subs r1, #1 + 8001968: ea43 4301 orr.w r3, r3, r1, lsl #16 + 800196c: f8c0 3084 str.w r3, [r0, #132] @ 0x84 + 8001970: 0512 lsls r2, r2, #20 + 8001972: d511 bpl.n 8001998 + 8001974: 6923 ldr r3, [r4, #16] + 8001976: 68a2 ldr r2, [r4, #8] + 8001978: 061b lsls r3, r3, #24 + 800197a: ea43 1382 orr.w r3, r3, r2, lsl #6 + 800197e: 6862 ldr r2, [r4, #4] + 8001980: 4313 orrs r3, r2 + 8001982: 6962 ldr r2, [r4, #20] + 8001984: ea43 7302 orr.w r3, r3, r2, lsl #28 + 8001988: 68e2 ldr r2, [r4, #12] + 800198a: 0852 lsrs r2, r2, #1 + 800198c: 3a01 subs r2, #1 + 800198e: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8001992: 4a10 ldr r2, [pc, #64] @ (80019d4 ) + 8001994: f8c2 3084 str.w r3, [r2, #132] @ 0x84 + 8001998: 4b11 ldr r3, [pc, #68] @ (80019e0 ) + 800199a: 4f0e ldr r7, [pc, #56] @ (80019d4 ) + 800199c: 2201 movs r2, #1 + 800199e: 669a str r2, [r3, #104] @ 0x68 + 80019a0: f7fe ff62 bl 8000868 + 80019a4: 4606 mov r6, r0 + 80019a6: 683b ldr r3, [r7, #0] + 80019a8: 011b lsls r3, r3, #4 + 80019aa: d455 bmi.n 8001a58 + 80019ac: f7fe ff5c bl 8000868 + 80019b0: 1b80 subs r0, r0, r6 + 80019b2: 2802 cmp r0, #2 + 80019b4: d9f7 bls.n 80019a6 + 80019b6: e008 b.n 80019ca + 80019b8: 2601 movs r6, #1 + 80019ba: e6f4 b.n 80017a6 + 80019bc: f7fe ff54 bl 8000868 + 80019c0: eba0 0008 sub.w r0, r0, r8 + 80019c4: 2802 cmp r0, #2 + 80019c6: f67f af04 bls.w 80017d2 + 80019ca: 2003 movs r0, #3 + 80019cc: b003 add sp, #12 + 80019ce: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 80019d2: bf00 nop + 80019d4: 40023800 .word 0x40023800 + 80019d8: 40007000 .word 0x40007000 + 80019dc: 42471000 .word 0x42471000 + 80019e0: 42470000 .word 0x42470000 + 80019e4: f402 7240 and.w r2, r2, #768 @ 0x300 + 80019e8: 4293 cmp r3, r2 + 80019ea: f43f aefd beq.w 80017e8 + 80019ee: 6f3b ldr r3, [r7, #112] @ 0x70 + 80019f0: 4a4b ldr r2, [pc, #300] @ (8001b20 ) + 80019f2: 2101 movs r1, #1 + 80019f4: f8c2 1e40 str.w r1, [r2, #3648] @ 0xe40 + 80019f8: f423 7340 bic.w r3, r3, #768 @ 0x300 + 80019fc: 2100 movs r1, #0 + 80019fe: f8c2 1e40 str.w r1, [r2, #3648] @ 0xe40 + 8001a02: 673b str r3, [r7, #112] @ 0x70 + 8001a04: 6f3b ldr r3, [r7, #112] @ 0x70 + 8001a06: 07da lsls r2, r3, #31 + 8001a08: f57f aeee bpl.w 80017e8 + 8001a0c: f7fe ff2c bl 8000868 + 8001a10: f241 3988 movw r9, #5000 @ 0x1388 + 8001a14: 4680 mov r8, r0 + 8001a16: 6f3b ldr r3, [r7, #112] @ 0x70 + 8001a18: 079b lsls r3, r3, #30 + 8001a1a: f53f aee5 bmi.w 80017e8 + 8001a1e: f7fe ff23 bl 8000868 + 8001a22: eba0 0008 sub.w r0, r0, r8 + 8001a26: 4548 cmp r0, r9 + 8001a28: d9f5 bls.n 8001a16 + 8001a2a: e7ce b.n 80019ca + 8001a2c: 6891 ldr r1, [r2, #8] + 8001a2e: f421 11f8 bic.w r1, r1, #2031616 @ 0x1f0000 + 8001a32: e6e9 b.n 8001808 + 8001a34: 483b ldr r0, [pc, #236] @ (8001b24 ) + 8001a36: 6d21 ldr r1, [r4, #80] @ 0x50 + 8001a38: f8d0 2094 ldr.w r2, [r0, #148] @ 0x94 + 8001a3c: f022 5200 bic.w r2, r2, #536870912 @ 0x20000000 + 8001a40: 430a orrs r2, r1 + 8001a42: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000 + 8001a46: f8c0 2094 str.w r2, [r0, #148] @ 0x94 + 8001a4a: f47f af1f bne.w 800188c + 8001a4e: e720 b.n 8001892 + 8001a50: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8001a54: f43f af1d beq.w 8001892 + 8001a58: 2d01 cmp r5, #1 + 8001a5a: d14c bne.n 8001af6 + 8001a5c: 4b30 ldr r3, [pc, #192] @ (8001b20 ) + 8001a5e: 4e31 ldr r6, [pc, #196] @ (8001b24 ) + 8001a60: 2200 movs r2, #0 + 8001a62: 671a str r2, [r3, #112] @ 0x70 + 8001a64: f7fe ff00 bl 8000868 + 8001a68: 4605 mov r5, r0 + 8001a6a: 6833 ldr r3, [r6, #0] + 8001a6c: 009f lsls r7, r3, #2 + 8001a6e: d44b bmi.n 8001b08 + 8001a70: 6821 ldr r1, [r4, #0] + 8001a72: 074d lsls r5, r1, #29 + 8001a74: d501 bpl.n 8001a7a + 8001a76: 6b23 ldr r3, [r4, #48] @ 0x30 + 8001a78: b11b cbz r3, 8001a82 + 8001a7a: 0708 lsls r0, r1, #28 + 8001a7c: d51a bpl.n 8001ab4 + 8001a7e: 6b63 ldr r3, [r4, #52] @ 0x34 + 8001a80: b9c3 cbnz r3, 8001ab4 + 8001a82: 4a28 ldr r2, [pc, #160] @ (8001b24 ) + 8001a84: 69a0 ldr r0, [r4, #24] + 8001a86: f8d2 3088 ldr.w r3, [r2, #136] @ 0x88 + 8001a8a: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8001a8e: 4303 orrs r3, r0 + 8001a90: 69e0 ldr r0, [r4, #28] + 8001a92: ea43 1380 orr.w r3, r3, r0, lsl #6 + 8001a96: 6a60 ldr r0, [r4, #36] @ 0x24 + 8001a98: ea43 6300 orr.w r3, r3, r0, lsl #24 + 8001a9c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 + 8001aa0: f8d2 308c ldr.w r3, [r2, #140] @ 0x8c + 8001aa4: 6ae0 ldr r0, [r4, #44] @ 0x2c + 8001aa6: f423 53f8 bic.w r3, r3, #7936 @ 0x1f00 + 8001aaa: 3801 subs r0, #1 + 8001aac: ea43 2300 orr.w r3, r3, r0, lsl #8 + 8001ab0: f8c2 308c str.w r3, [r2, #140] @ 0x8c + 8001ab4: 05ca lsls r2, r1, #23 + 8001ab6: d514 bpl.n 8001ae2 + 8001ab8: 6d63 ldr r3, [r4, #84] @ 0x54 + 8001aba: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 + 8001abe: d110 bne.n 8001ae2 + 8001ac0: 4918 ldr r1, [pc, #96] @ (8001b24 ) + 8001ac2: 69a2 ldr r2, [r4, #24] + 8001ac4: f8d1 3088 ldr.w r3, [r1, #136] @ 0x88 + 8001ac8: f003 6370 and.w r3, r3, #251658240 @ 0xf000000 + 8001acc: 4313 orrs r3, r2 + 8001ace: 69e2 ldr r2, [r4, #28] + 8001ad0: ea43 1382 orr.w r3, r3, r2, lsl #6 + 8001ad4: 6a22 ldr r2, [r4, #32] + 8001ad6: 0852 lsrs r2, r2, #1 + 8001ad8: 3a01 subs r2, #1 + 8001ada: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8001ade: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8001ae2: 4b0f ldr r3, [pc, #60] @ (8001b20 ) + 8001ae4: 4d0f ldr r5, [pc, #60] @ (8001b24 ) + 8001ae6: 2201 movs r2, #1 + 8001ae8: 671a str r2, [r3, #112] @ 0x70 + 8001aea: f7fe febd bl 8000868 + 8001aee: 4604 mov r4, r0 + 8001af0: 682b ldr r3, [r5, #0] + 8001af2: 009b lsls r3, r3, #2 + 8001af4: d50e bpl.n 8001b14 + 8001af6: 2000 movs r0, #0 + 8001af8: e768 b.n 80019cc + 8001afa: f7fe feb5 bl 8000868 + 8001afe: 1b80 subs r0, r0, r6 + 8001b00: 2802 cmp r0, #2 + 8001b02: f67f aecd bls.w 80018a0 + 8001b06: e760 b.n 80019ca + 8001b08: f7fe feae bl 8000868 + 8001b0c: 1b40 subs r0, r0, r5 + 8001b0e: 2802 cmp r0, #2 + 8001b10: d9ab bls.n 8001a6a + 8001b12: e75a b.n 80019ca + 8001b14: f7fe fea8 bl 8000868 + 8001b18: 1b00 subs r0, r0, r4 + 8001b1a: 2802 cmp r0, #2 + 8001b1c: d9e8 bls.n 8001af0 + 8001b1e: e754 b.n 80019ca + 8001b20: 42470000 .word 0x42470000 + 8001b24: 40023800 .word 0x40023800 + +08001b28 : + 8001b28: 4920 ldr r1, [pc, #128] @ (8001bac ) + 8001b2a: b508 push {r3, lr} + 8001b2c: 688b ldr r3, [r1, #8] + 8001b2e: f003 030c and.w r3, r3, #12 + 8001b32: 2b08 cmp r3, #8 + 8001b34: d007 beq.n 8001b46 + 8001b36: 2b0c cmp r3, #12 + 8001b38: d020 beq.n 8001b7c + 8001b3a: 481d ldr r0, [pc, #116] @ (8001bb0 ) + 8001b3c: 4a1d ldr r2, [pc, #116] @ (8001bb4 ) + 8001b3e: 2b04 cmp r3, #4 + 8001b40: bf18 it ne + 8001b42: 4610 movne r0, r2 + 8001b44: bd08 pop {r3, pc} + 8001b46: 684a ldr r2, [r1, #4] + 8001b48: 684b ldr r3, [r1, #4] + 8001b4a: 6849 ldr r1, [r1, #4] + 8001b4c: f413 0380 ands.w r3, r3, #4194304 @ 0x400000 + 8001b50: bf14 ite ne + 8001b52: 4817 ldrne r0, [pc, #92] @ (8001bb0 ) + 8001b54: 4817 ldreq r0, [pc, #92] @ (8001bb4 ) + 8001b56: f3c1 1188 ubfx r1, r1, #6, #9 + 8001b5a: bf18 it ne + 8001b5c: 2300 movne r3, #0 + 8001b5e: f002 023f and.w r2, r2, #63 @ 0x3f + 8001b62: fba1 0100 umull r0, r1, r1, r0 + 8001b66: f7fe fb55 bl 8000214 <__aeabi_uldivmod> + 8001b6a: 4b10 ldr r3, [pc, #64] @ (8001bac ) + 8001b6c: 685b ldr r3, [r3, #4] + 8001b6e: f3c3 4301 ubfx r3, r3, #16, #2 + 8001b72: 3301 adds r3, #1 + 8001b74: 005b lsls r3, r3, #1 + 8001b76: fbb0 f0f3 udiv r0, r0, r3 + 8001b7a: e7e3 b.n 8001b44 + 8001b7c: 684a ldr r2, [r1, #4] + 8001b7e: 684b ldr r3, [r1, #4] + 8001b80: 6849 ldr r1, [r1, #4] + 8001b82: f413 0380 ands.w r3, r3, #4194304 @ 0x400000 + 8001b86: bf14 ite ne + 8001b88: 4809 ldrne r0, [pc, #36] @ (8001bb0 ) + 8001b8a: 480a ldreq r0, [pc, #40] @ (8001bb4 ) + 8001b8c: f3c1 1188 ubfx r1, r1, #6, #9 + 8001b90: bf18 it ne + 8001b92: 2300 movne r3, #0 + 8001b94: f002 023f and.w r2, r2, #63 @ 0x3f + 8001b98: fba1 0100 umull r0, r1, r1, r0 + 8001b9c: f7fe fb3a bl 8000214 <__aeabi_uldivmod> + 8001ba0: 4b02 ldr r3, [pc, #8] @ (8001bac ) + 8001ba2: 685b ldr r3, [r3, #4] + 8001ba4: f3c3 7302 ubfx r3, r3, #28, #3 + 8001ba8: e7e5 b.n 8001b76 + 8001baa: bf00 nop + 8001bac: 40023800 .word 0x40023800 + 8001bb0: 007a1200 .word 0x007a1200 + 8001bb4: 00f42400 .word 0x00f42400 + +08001bb8 : + 8001bb8: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + 8001bbc: 4604 mov r4, r0 + 8001bbe: 2800 cmp r0, #0 + 8001bc0: d031 beq.n 8001c26 + 8001bc2: 6803 ldr r3, [r0, #0] + 8001bc4: 07df lsls r7, r3, #31 + 8001bc6: d410 bmi.n 8001bea + 8001bc8: 6823 ldr r3, [r4, #0] + 8001bca: 079e lsls r6, r3, #30 + 8001bcc: d467 bmi.n 8001c9e + 8001bce: 6823 ldr r3, [r4, #0] + 8001bd0: 0719 lsls r1, r3, #28 + 8001bd2: f100 80b2 bmi.w 8001d3a + 8001bd6: 6823 ldr r3, [r4, #0] + 8001bd8: 075a lsls r2, r3, #29 + 8001bda: f100 80d2 bmi.w 8001d82 + 8001bde: 69a3 ldr r3, [r4, #24] + 8001be0: 2b00 cmp r3, #0 + 8001be2: f040 8139 bne.w 8001e58 + 8001be6: 2000 movs r0, #0 + 8001be8: e034 b.n 8001c54 + 8001bea: 4b98 ldr r3, [pc, #608] @ (8001e4c ) + 8001bec: 689a ldr r2, [r3, #8] + 8001bee: f002 020c and.w r2, r2, #12 + 8001bf2: 2a04 cmp r2, #4 + 8001bf4: d010 beq.n 8001c18 + 8001bf6: 689a ldr r2, [r3, #8] + 8001bf8: f002 020c and.w r2, r2, #12 + 8001bfc: 2a08 cmp r2, #8 + 8001bfe: d102 bne.n 8001c06 + 8001c00: 685b ldr r3, [r3, #4] + 8001c02: 025d lsls r5, r3, #9 + 8001c04: d408 bmi.n 8001c18 + 8001c06: 4b91 ldr r3, [pc, #580] @ (8001e4c ) + 8001c08: 689a ldr r2, [r3, #8] + 8001c0a: f002 020c and.w r2, r2, #12 + 8001c0e: 2a0c cmp r2, #12 + 8001c10: d10b bne.n 8001c2a + 8001c12: 685a ldr r2, [r3, #4] + 8001c14: 0251 lsls r1, r2, #9 + 8001c16: d508 bpl.n 8001c2a + 8001c18: 4b8c ldr r3, [pc, #560] @ (8001e4c ) + 8001c1a: 681b ldr r3, [r3, #0] + 8001c1c: 039a lsls r2, r3, #14 + 8001c1e: d5d3 bpl.n 8001bc8 + 8001c20: 6863 ldr r3, [r4, #4] + 8001c22: 2b00 cmp r3, #0 + 8001c24: d1d0 bne.n 8001bc8 + 8001c26: 2001 movs r0, #1 + 8001c28: e014 b.n 8001c54 + 8001c2a: 6862 ldr r2, [r4, #4] + 8001c2c: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 + 8001c30: d113 bne.n 8001c5a + 8001c32: 681a ldr r2, [r3, #0] + 8001c34: f442 3280 orr.w r2, r2, #65536 @ 0x10000 + 8001c38: 601a str r2, [r3, #0] + 8001c3a: f7fe fe15 bl 8000868 + 8001c3e: 4e83 ldr r6, [pc, #524] @ (8001e4c ) + 8001c40: 4605 mov r5, r0 + 8001c42: 6833 ldr r3, [r6, #0] + 8001c44: 039b lsls r3, r3, #14 + 8001c46: d4bf bmi.n 8001bc8 + 8001c48: f7fe fe0e bl 8000868 + 8001c4c: 1b40 subs r0, r0, r5 + 8001c4e: 2864 cmp r0, #100 @ 0x64 + 8001c50: d9f7 bls.n 8001c42 + 8001c52: 2003 movs r0, #3 + 8001c54: b002 add sp, #8 + 8001c56: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8001c5a: 4d7c ldr r5, [pc, #496] @ (8001e4c ) + 8001c5c: f5b2 2fa0 cmp.w r2, #327680 @ 0x50000 + 8001c60: 682b ldr r3, [r5, #0] + 8001c62: d107 bne.n 8001c74 + 8001c64: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8001c68: 602b str r3, [r5, #0] + 8001c6a: 682b ldr r3, [r5, #0] + 8001c6c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001c70: 602b str r3, [r5, #0] + 8001c72: e7e2 b.n 8001c3a + 8001c74: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001c78: 602b str r3, [r5, #0] + 8001c7a: 682b ldr r3, [r5, #0] + 8001c7c: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001c80: 602b str r3, [r5, #0] + 8001c82: 2a00 cmp r2, #0 + 8001c84: d1d9 bne.n 8001c3a + 8001c86: f7fe fdef bl 8000868 + 8001c8a: 4606 mov r6, r0 + 8001c8c: 682b ldr r3, [r5, #0] + 8001c8e: 039f lsls r7, r3, #14 + 8001c90: d59a bpl.n 8001bc8 + 8001c92: f7fe fde9 bl 8000868 + 8001c96: 1b80 subs r0, r0, r6 + 8001c98: 2864 cmp r0, #100 @ 0x64 + 8001c9a: d9f7 bls.n 8001c8c + 8001c9c: e7d9 b.n 8001c52 + 8001c9e: 4b6b ldr r3, [pc, #428] @ (8001e4c ) + 8001ca0: 689a ldr r2, [r3, #8] + 8001ca2: f012 0f0c tst.w r2, #12 + 8001ca6: d010 beq.n 8001cca + 8001ca8: 689a ldr r2, [r3, #8] + 8001caa: f002 020c and.w r2, r2, #12 + 8001cae: 2a08 cmp r2, #8 + 8001cb0: d102 bne.n 8001cb8 + 8001cb2: 685b ldr r3, [r3, #4] + 8001cb4: 025e lsls r6, r3, #9 + 8001cb6: d508 bpl.n 8001cca + 8001cb8: 4a64 ldr r2, [pc, #400] @ (8001e4c ) + 8001cba: 6893 ldr r3, [r2, #8] + 8001cbc: f003 030c and.w r3, r3, #12 + 8001cc0: 2b0c cmp r3, #12 + 8001cc2: d111 bne.n 8001ce8 + 8001cc4: 6853 ldr r3, [r2, #4] + 8001cc6: 025d lsls r5, r3, #9 + 8001cc8: d40e bmi.n 8001ce8 + 8001cca: 4a60 ldr r2, [pc, #384] @ (8001e4c ) + 8001ccc: 6813 ldr r3, [r2, #0] + 8001cce: 0799 lsls r1, r3, #30 + 8001cd0: d502 bpl.n 8001cd8 + 8001cd2: 68e3 ldr r3, [r4, #12] + 8001cd4: 2b01 cmp r3, #1 + 8001cd6: d1a6 bne.n 8001c26 + 8001cd8: 6813 ldr r3, [r2, #0] + 8001cda: 6921 ldr r1, [r4, #16] + 8001cdc: f023 03f8 bic.w r3, r3, #248 @ 0xf8 + 8001ce0: ea43 03c1 orr.w r3, r3, r1, lsl #3 + 8001ce4: 6013 str r3, [r2, #0] + 8001ce6: e772 b.n 8001bce + 8001ce8: 68e2 ldr r2, [r4, #12] + 8001cea: 4b59 ldr r3, [pc, #356] @ (8001e50 ) + 8001cec: b1b2 cbz r2, 8001d1c + 8001cee: 2201 movs r2, #1 + 8001cf0: 601a str r2, [r3, #0] + 8001cf2: f7fe fdb9 bl 8000868 + 8001cf6: 4d55 ldr r5, [pc, #340] @ (8001e4c ) + 8001cf8: 4606 mov r6, r0 + 8001cfa: 682b ldr r3, [r5, #0] + 8001cfc: 079b lsls r3, r3, #30 + 8001cfe: d507 bpl.n 8001d10 + 8001d00: 682b ldr r3, [r5, #0] + 8001d02: 6922 ldr r2, [r4, #16] + 8001d04: f023 03f8 bic.w r3, r3, #248 @ 0xf8 + 8001d08: ea43 03c2 orr.w r3, r3, r2, lsl #3 + 8001d0c: 602b str r3, [r5, #0] + 8001d0e: e75e b.n 8001bce + 8001d10: f7fe fdaa bl 8000868 + 8001d14: 1b80 subs r0, r0, r6 + 8001d16: 2802 cmp r0, #2 + 8001d18: d9ef bls.n 8001cfa + 8001d1a: e79a b.n 8001c52 + 8001d1c: 601a str r2, [r3, #0] + 8001d1e: f7fe fda3 bl 8000868 + 8001d22: 4e4a ldr r6, [pc, #296] @ (8001e4c ) + 8001d24: 4605 mov r5, r0 + 8001d26: 6833 ldr r3, [r6, #0] + 8001d28: 079f lsls r7, r3, #30 + 8001d2a: f57f af50 bpl.w 8001bce + 8001d2e: f7fe fd9b bl 8000868 + 8001d32: 1b40 subs r0, r0, r5 + 8001d34: 2802 cmp r0, #2 + 8001d36: d9f6 bls.n 8001d26 + 8001d38: e78b b.n 8001c52 + 8001d3a: 6962 ldr r2, [r4, #20] + 8001d3c: 4b44 ldr r3, [pc, #272] @ (8001e50 ) + 8001d3e: b182 cbz r2, 8001d62 + 8001d40: 2201 movs r2, #1 + 8001d42: f8c3 2e80 str.w r2, [r3, #3712] @ 0xe80 + 8001d46: f7fe fd8f bl 8000868 + 8001d4a: 4e40 ldr r6, [pc, #256] @ (8001e4c ) + 8001d4c: 4605 mov r5, r0 + 8001d4e: 6f73 ldr r3, [r6, #116] @ 0x74 + 8001d50: 079b lsls r3, r3, #30 + 8001d52: f53f af40 bmi.w 8001bd6 + 8001d56: f7fe fd87 bl 8000868 + 8001d5a: 1b40 subs r0, r0, r5 + 8001d5c: 2802 cmp r0, #2 + 8001d5e: d9f6 bls.n 8001d4e + 8001d60: e777 b.n 8001c52 + 8001d62: f8c3 2e80 str.w r2, [r3, #3712] @ 0xe80 + 8001d66: f7fe fd7f bl 8000868 + 8001d6a: 4e38 ldr r6, [pc, #224] @ (8001e4c ) + 8001d6c: 4605 mov r5, r0 + 8001d6e: 6f73 ldr r3, [r6, #116] @ 0x74 + 8001d70: 079f lsls r7, r3, #30 + 8001d72: f57f af30 bpl.w 8001bd6 + 8001d76: f7fe fd77 bl 8000868 + 8001d7a: 1b40 subs r0, r0, r5 + 8001d7c: 2802 cmp r0, #2 + 8001d7e: d9f6 bls.n 8001d6e + 8001d80: e767 b.n 8001c52 + 8001d82: 4b32 ldr r3, [pc, #200] @ (8001e4c ) + 8001d84: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001d86: f012 5280 ands.w r2, r2, #268435456 @ 0x10000000 + 8001d8a: d128 bne.n 8001dde + 8001d8c: 9201 str r2, [sp, #4] + 8001d8e: 6c1a ldr r2, [r3, #64] @ 0x40 + 8001d90: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 + 8001d94: 641a str r2, [r3, #64] @ 0x40 + 8001d96: 6c1b ldr r3, [r3, #64] @ 0x40 + 8001d98: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001d9c: 9301 str r3, [sp, #4] + 8001d9e: 9b01 ldr r3, [sp, #4] + 8001da0: 2701 movs r7, #1 + 8001da2: 4d2c ldr r5, [pc, #176] @ (8001e54 ) + 8001da4: 682b ldr r3, [r5, #0] + 8001da6: 05d8 lsls r0, r3, #23 + 8001da8: d51b bpl.n 8001de2 + 8001daa: 68a3 ldr r3, [r4, #8] + 8001dac: 4d27 ldr r5, [pc, #156] @ (8001e4c ) + 8001dae: 2b01 cmp r3, #1 + 8001db0: d127 bne.n 8001e02 + 8001db2: 6f2b ldr r3, [r5, #112] @ 0x70 + 8001db4: f043 0301 orr.w r3, r3, #1 + 8001db8: 672b str r3, [r5, #112] @ 0x70 + 8001dba: f7fe fd55 bl 8000868 + 8001dbe: 4e23 ldr r6, [pc, #140] @ (8001e4c ) + 8001dc0: 4605 mov r5, r0 + 8001dc2: f241 3888 movw r8, #5000 @ 0x1388 + 8001dc6: 6f33 ldr r3, [r6, #112] @ 0x70 + 8001dc8: 079a lsls r2, r3, #30 + 8001dca: d539 bpl.n 8001e40 + 8001dcc: 2f00 cmp r7, #0 + 8001dce: f43f af06 beq.w 8001bde + 8001dd2: 4a1e ldr r2, [pc, #120] @ (8001e4c ) + 8001dd4: 6c13 ldr r3, [r2, #64] @ 0x40 + 8001dd6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001dda: 6413 str r3, [r2, #64] @ 0x40 + 8001ddc: e6ff b.n 8001bde + 8001dde: 2700 movs r7, #0 + 8001de0: e7df b.n 8001da2 + 8001de2: 682b ldr r3, [r5, #0] + 8001de4: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001de8: 602b str r3, [r5, #0] + 8001dea: f7fe fd3d bl 8000868 + 8001dee: 4606 mov r6, r0 + 8001df0: 682b ldr r3, [r5, #0] + 8001df2: 05d9 lsls r1, r3, #23 + 8001df4: d4d9 bmi.n 8001daa + 8001df6: f7fe fd37 bl 8000868 + 8001dfa: 1b80 subs r0, r0, r6 + 8001dfc: 2802 cmp r0, #2 + 8001dfe: d9f7 bls.n 8001df0 + 8001e00: e727 b.n 8001c52 + 8001e02: 2b05 cmp r3, #5 + 8001e04: d104 bne.n 8001e10 + 8001e06: 6f2b ldr r3, [r5, #112] @ 0x70 + 8001e08: f043 0304 orr.w r3, r3, #4 + 8001e0c: 672b str r3, [r5, #112] @ 0x70 + 8001e0e: e7d0 b.n 8001db2 + 8001e10: 6f2a ldr r2, [r5, #112] @ 0x70 + 8001e12: f022 0201 bic.w r2, r2, #1 + 8001e16: 672a str r2, [r5, #112] @ 0x70 + 8001e18: 6f2a ldr r2, [r5, #112] @ 0x70 + 8001e1a: f022 0204 bic.w r2, r2, #4 + 8001e1e: 672a str r2, [r5, #112] @ 0x70 + 8001e20: 2b00 cmp r3, #0 + 8001e22: d1ca bne.n 8001dba + 8001e24: f7fe fd20 bl 8000868 + 8001e28: f241 3888 movw r8, #5000 @ 0x1388 + 8001e2c: 4606 mov r6, r0 + 8001e2e: 6f2b ldr r3, [r5, #112] @ 0x70 + 8001e30: 079b lsls r3, r3, #30 + 8001e32: d5cb bpl.n 8001dcc + 8001e34: f7fe fd18 bl 8000868 + 8001e38: 1b80 subs r0, r0, r6 + 8001e3a: 4540 cmp r0, r8 + 8001e3c: d9f7 bls.n 8001e2e + 8001e3e: e708 b.n 8001c52 + 8001e40: f7fe fd12 bl 8000868 + 8001e44: 1b40 subs r0, r0, r5 + 8001e46: 4540 cmp r0, r8 + 8001e48: d9bd bls.n 8001dc6 + 8001e4a: e702 b.n 8001c52 + 8001e4c: 40023800 .word 0x40023800 + 8001e50: 42470000 .word 0x42470000 + 8001e54: 40007000 .word 0x40007000 + 8001e58: 4d3c ldr r5, [pc, #240] @ (8001f4c ) + 8001e5a: 68aa ldr r2, [r5, #8] + 8001e5c: f002 020c and.w r2, r2, #12 + 8001e60: 2a08 cmp r2, #8 + 8001e62: d041 beq.n 8001ee8 + 8001e64: 2b02 cmp r3, #2 + 8001e66: 4b3a ldr r3, [pc, #232] @ (8001f50 ) + 8001e68: f04f 0200 mov.w r2, #0 + 8001e6c: 661a str r2, [r3, #96] @ 0x60 + 8001e6e: d12e bne.n 8001ece + 8001e70: f7fe fcfa bl 8000868 + 8001e74: 4606 mov r6, r0 + 8001e76: 682b ldr r3, [r5, #0] + 8001e78: 0199 lsls r1, r3, #6 + 8001e7a: d422 bmi.n 8001ec2 + 8001e7c: e9d4 3207 ldrd r3, r2, [r4, #28] + 8001e80: 4313 orrs r3, r2 + 8001e82: 6a62 ldr r2, [r4, #36] @ 0x24 + 8001e84: ea43 1382 orr.w r3, r3, r2, lsl #6 + 8001e88: 6ae2 ldr r2, [r4, #44] @ 0x2c + 8001e8a: ea43 6302 orr.w r3, r3, r2, lsl #24 + 8001e8e: 6b22 ldr r2, [r4, #48] @ 0x30 + 8001e90: ea43 7302 orr.w r3, r3, r2, lsl #28 + 8001e94: 6aa2 ldr r2, [r4, #40] @ 0x28 + 8001e96: 0852 lsrs r2, r2, #1 + 8001e98: 3a01 subs r2, #1 + 8001e9a: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8001e9e: 606b str r3, [r5, #4] + 8001ea0: 4b2b ldr r3, [pc, #172] @ (8001f50 ) + 8001ea2: 4d2a ldr r5, [pc, #168] @ (8001f4c ) + 8001ea4: 2201 movs r2, #1 + 8001ea6: 661a str r2, [r3, #96] @ 0x60 + 8001ea8: f7fe fcde bl 8000868 + 8001eac: 4604 mov r4, r0 + 8001eae: 682b ldr r3, [r5, #0] + 8001eb0: 019a lsls r2, r3, #6 + 8001eb2: f53f ae98 bmi.w 8001be6 + 8001eb6: f7fe fcd7 bl 8000868 + 8001eba: 1b00 subs r0, r0, r4 + 8001ebc: 2802 cmp r0, #2 + 8001ebe: d9f6 bls.n 8001eae + 8001ec0: e6c7 b.n 8001c52 + 8001ec2: f7fe fcd1 bl 8000868 + 8001ec6: 1b80 subs r0, r0, r6 + 8001ec8: 2802 cmp r0, #2 + 8001eca: d9d4 bls.n 8001e76 + 8001ecc: e6c1 b.n 8001c52 + 8001ece: f7fe fccb bl 8000868 + 8001ed2: 4604 mov r4, r0 + 8001ed4: 682b ldr r3, [r5, #0] + 8001ed6: 019b lsls r3, r3, #6 + 8001ed8: f57f ae85 bpl.w 8001be6 + 8001edc: f7fe fcc4 bl 8000868 + 8001ee0: 1b00 subs r0, r0, r4 + 8001ee2: 2802 cmp r0, #2 + 8001ee4: d9f6 bls.n 8001ed4 + 8001ee6: e6b4 b.n 8001c52 + 8001ee8: 2b01 cmp r3, #1 + 8001eea: f43f ae9c beq.w 8001c26 + 8001eee: 686b ldr r3, [r5, #4] + 8001ef0: 69e2 ldr r2, [r4, #28] + 8001ef2: f403 0180 and.w r1, r3, #4194304 @ 0x400000 + 8001ef6: 4291 cmp r1, r2 + 8001ef8: f47f ae95 bne.w 8001c26 + 8001efc: 6a21 ldr r1, [r4, #32] + 8001efe: f003 023f and.w r2, r3, #63 @ 0x3f + 8001f02: 428a cmp r2, r1 + 8001f04: f47f ae8f bne.w 8001c26 + 8001f08: 6a61 ldr r1, [r4, #36] @ 0x24 + 8001f0a: f647 72c0 movw r2, #32704 @ 0x7fc0 + 8001f0e: 401a ands r2, r3 + 8001f10: ebb2 1f81 cmp.w r2, r1, lsl #6 + 8001f14: f47f ae87 bne.w 8001c26 + 8001f18: 6aa2 ldr r2, [r4, #40] @ 0x28 + 8001f1a: 0852 lsrs r2, r2, #1 + 8001f1c: f403 3140 and.w r1, r3, #196608 @ 0x30000 + 8001f20: 3a01 subs r2, #1 + 8001f22: ebb1 4f02 cmp.w r1, r2, lsl #16 + 8001f26: f47f ae7e bne.w 8001c26 + 8001f2a: 6ae1 ldr r1, [r4, #44] @ 0x2c + 8001f2c: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 + 8001f30: ebb2 6f01 cmp.w r2, r1, lsl #24 + 8001f34: f47f ae77 bne.w 8001c26 + 8001f38: 6b22 ldr r2, [r4, #48] @ 0x30 + 8001f3a: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 + 8001f3e: ebb3 7f02 cmp.w r3, r2, lsl #28 + 8001f42: bf14 ite ne + 8001f44: 2001 movne r0, #1 + 8001f46: 2000 moveq r0, #0 + 8001f48: e684 b.n 8001c54 + 8001f4a: bf00 nop + 8001f4c: 40023800 .word 0x40023800 + 8001f50: 42470000 .word 0x42470000 + +08001f54 : + 8001f54: b082 sub sp, #8 + 8001f56: 2300 movs r3, #0 + 8001f58: 4602 mov r2, r0 + 8001f5a: 9301 str r3, [sp, #4] + 8001f5c: 9b01 ldr r3, [sp, #4] + 8001f5e: 3301 adds r3, #1 + 8001f60: 9301 str r3, [sp, #4] + 8001f62: 9b01 ldr r3, [sp, #4] + 8001f64: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 8001f68: d81a bhi.n 8001fa0 + 8001f6a: 6913 ldr r3, [r2, #16] + 8001f6c: 2b00 cmp r3, #0 + 8001f6e: daf5 bge.n 8001f5c + 8001f70: 230a movs r3, #10 + 8001f72: 9301 str r3, [sp, #4] + 8001f74: 9b01 ldr r3, [sp, #4] + 8001f76: b983 cbnz r3, 8001f9a + 8001f78: 6913 ldr r3, [r2, #16] + 8001f7a: f043 0301 orr.w r3, r3, #1 + 8001f7e: 6113 str r3, [r2, #16] + 8001f80: 9b01 ldr r3, [sp, #4] + 8001f82: 3301 adds r3, #1 + 8001f84: 9301 str r3, [sp, #4] + 8001f86: 9b01 ldr r3, [sp, #4] + 8001f88: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 8001f8c: d808 bhi.n 8001fa0 + 8001f8e: 6910 ldr r0, [r2, #16] + 8001f90: f010 0001 ands.w r0, r0, #1 + 8001f94: d1f4 bne.n 8001f80 + 8001f96: b002 add sp, #8 + 8001f98: 4770 bx lr + 8001f9a: 9b01 ldr r3, [sp, #4] + 8001f9c: 3b01 subs r3, #1 + 8001f9e: e7e8 b.n 8001f72 + 8001fa0: 2003 movs r0, #3 + 8001fa2: e7f8 b.n 8001f96 + +08001fa4 : + 8001fa4: b084 sub sp, #16 + 8001fa6: b538 push {r3, r4, r5, lr} + 8001fa8: ad05 add r5, sp, #20 + 8001faa: e885 000e stmia.w r5, {r1, r2, r3} + 8001fae: f89d 3019 ldrb.w r3, [sp, #25] + 8001fb2: 2b01 cmp r3, #1 + 8001fb4: 4604 mov r4, r0 + 8001fb6: d127 bne.n 8002008 + 8001fb8: 6b83 ldr r3, [r0, #56] @ 0x38 + 8001fba: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001fbe: 6383 str r3, [r0, #56] @ 0x38 + 8001fc0: 68c3 ldr r3, [r0, #12] + 8001fc2: f423 0384 bic.w r3, r3, #4325376 @ 0x420000 + 8001fc6: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8001fca: 60c3 str r3, [r0, #12] + 8001fcc: 68c3 ldr r3, [r0, #12] + 8001fce: f423 1340 bic.w r3, r3, #3145728 @ 0x300000 + 8001fd2: 60c3 str r3, [r0, #12] + 8001fd4: f89d 3020 ldrb.w r3, [sp, #32] + 8001fd8: 2b01 cmp r3, #1 + 8001fda: bf02 ittt eq + 8001fdc: 68c3 ldreq r3, [r0, #12] + 8001fde: f443 1380 orreq.w r3, r3, #1048576 @ 0x100000 + 8001fe2: 60c3 streq r3, [r0, #12] + 8001fe4: f7ff ffb6 bl 8001f54 + 8001fe8: f89d 3016 ldrb.w r3, [sp, #22] + 8001fec: 2b01 cmp r3, #1 + 8001fee: d107 bne.n 8002000 + 8001ff0: 68a3 ldr r3, [r4, #8] + 8001ff2: f043 0306 orr.w r3, r3, #6 + 8001ff6: 60a3 str r3, [r4, #8] + 8001ff8: 68a3 ldr r3, [r4, #8] + 8001ffa: f043 0320 orr.w r3, r3, #32 + 8001ffe: 60a3 str r3, [r4, #8] + 8002000: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8002004: b004 add sp, #16 + 8002006: 4770 bx lr + 8002008: 68c3 ldr r3, [r0, #12] + 800200a: f043 0340 orr.w r3, r3, #64 @ 0x40 + 800200e: 60c3 str r3, [r0, #12] + 8002010: f7ff ffa0 bl 8001f54 + 8002014: f89d 301d ldrb.w r3, [sp, #29] + 8002018: b923 cbnz r3, 8002024 + 800201a: 6ba3 ldr r3, [r4, #56] @ 0x38 + 800201c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8002020: 63a3 str r3, [r4, #56] @ 0x38 + 8002022: e7e1 b.n 8001fe8 + 8002024: 6ba3 ldr r3, [r4, #56] @ 0x38 + 8002026: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 800202a: e7f9 b.n 8002020 + +0800202c : + 800202c: 2a02 cmp r2, #2 + 800202e: d14a bne.n 80020c6 + 8002030: 4b27 ldr r3, [pc, #156] @ (80020d0 ) + 8002032: 4a28 ldr r2, [pc, #160] @ (80020d4 ) + 8002034: 440b add r3, r1 + 8002036: 4293 cmp r3, r2 + 8002038: d939 bls.n 80020ae + 800203a: 4b27 ldr r3, [pc, #156] @ (80020d8 ) + 800203c: 4a27 ldr r2, [pc, #156] @ (80020dc ) + 800203e: 440b add r3, r1 + 8002040: 4293 cmp r3, r2 + 8002042: d936 bls.n 80020b2 + 8002044: 4a26 ldr r2, [pc, #152] @ (80020e0 ) + 8002046: f5a1 0374 sub.w r3, r1, #15990784 @ 0xf40000 + 800204a: f5a3 5310 sub.w r3, r3, #9216 @ 0x2400 + 800204e: 4293 cmp r3, r2 + 8002050: d931 bls.n 80020b6 + 8002052: 4a24 ldr r2, [pc, #144] @ (80020e4 ) + 8002054: f1a1 7383 sub.w r3, r1, #17170432 @ 0x1060000 + 8002058: f5a3 43e7 sub.w r3, r3, #29568 @ 0x7380 + 800205c: 4293 cmp r3, r2 + 800205e: d32c bcc.n 80020ba + 8002060: 4b21 ldr r3, [pc, #132] @ (80020e8 ) + 8002062: 4a22 ldr r2, [pc, #136] @ (80020ec ) + 8002064: 440b add r3, r1 + 8002066: 4293 cmp r3, r2 + 8002068: d929 bls.n 80020be + 800206a: 4b21 ldr r3, [pc, #132] @ (80020f0 ) + 800206c: 4a21 ldr r2, [pc, #132] @ (80020f4 ) + 800206e: 440b add r3, r1 + 8002070: 4293 cmp r3, r2 + 8002072: d326 bcc.n 80020c2 + 8002074: 4b20 ldr r3, [pc, #128] @ (80020f8 ) + 8002076: 4a21 ldr r2, [pc, #132] @ (80020fc ) + 8002078: 440b add r3, r1 + 800207a: 4293 cmp r3, r2 + 800207c: d323 bcc.n 80020c6 + 800207e: 4a20 ldr r2, [pc, #128] @ (8002100 ) + 8002080: f1a1 73b7 sub.w r3, r1, #23986176 @ 0x16e0000 + 8002084: f5a3 5358 sub.w r3, r3, #13824 @ 0x3600 + 8002088: 4293 cmp r3, r2 + 800208a: d31e bcc.n 80020ca + 800208c: 4b1d ldr r3, [pc, #116] @ (8002104 ) + 800208e: 4a1e ldr r2, [pc, #120] @ (8002108 ) + 8002090: 440b add r3, r1 + 8002092: 4293 cmp r3, r2 + 8002094: bf2c ite cs + 8002096: 2306 movcs r3, #6 + 8002098: 2307 movcc r3, #7 + 800209a: 68c2 ldr r2, [r0, #12] + 800209c: f422 5270 bic.w r2, r2, #15360 @ 0x3c00 + 80020a0: 60c2 str r2, [r0, #12] + 80020a2: 68c2 ldr r2, [r0, #12] + 80020a4: ea42 2383 orr.w r3, r2, r3, lsl #10 + 80020a8: 60c3 str r3, [r0, #12] + 80020aa: 2000 movs r0, #0 + 80020ac: 4770 bx lr + 80020ae: 230f movs r3, #15 + 80020b0: e7f3 b.n 800209a + 80020b2: 230e movs r3, #14 + 80020b4: e7f1 b.n 800209a + 80020b6: 230d movs r3, #13 + 80020b8: e7ef b.n 800209a + 80020ba: 230c movs r3, #12 + 80020bc: e7ed b.n 800209a + 80020be: 230b movs r3, #11 + 80020c0: e7eb b.n 800209a + 80020c2: 230a movs r3, #10 + 80020c4: e7e9 b.n 800209a + 80020c6: 2309 movs r3, #9 + 80020c8: e7e7 b.n 800209a + 80020ca: 2308 movs r3, #8 + 80020cc: e7e5 b.n 800209a + 80020ce: bf00 nop + 80020d0: ff275340 .word 0xff275340 + 80020d4: 000c34ff .word 0x000c34ff + 80020d8: ff1b1e40 .word 0xff1b1e40 + 80020dc: 000f423f .word 0x000f423f + 80020e0: 00124f7f .word 0x00124f7f + 80020e4: 0013d620 .word 0x0013d620 + 80020e8: fee5b660 .word 0xfee5b660 + 80020ec: 0016e35f .word 0x0016e35f + 80020f0: feced300 .word 0xfeced300 + 80020f4: 001b7740 .word 0x001b7740 + 80020f8: feb35bc0 .word 0xfeb35bc0 + 80020fc: 002191c0 .word 0x002191c0 + 8002100: 00387520 .word 0x00387520 + 8002104: fe5954e0 .word 0xfe5954e0 + 8002108: 00419ce0 .word 0x00419ce0 + +0800210c : + 800210c: 6883 ldr r3, [r0, #8] + 800210e: f043 0301 orr.w r3, r3, #1 + 8002112: 6083 str r3, [r0, #8] + 8002114: 2000 movs r0, #0 + 8002116: 4770 bx lr + +08002118 : + 8002118: 6883 ldr r3, [r0, #8] + 800211a: f023 0301 bic.w r3, r3, #1 + 800211e: 6083 str r3, [r0, #8] + 8002120: 2000 movs r0, #0 + 8002122: 4770 bx lr + +08002124 : + 8002124: b538 push {r3, r4, r5, lr} + 8002126: 68c3 ldr r3, [r0, #12] + 8002128: 2901 cmp r1, #1 + 800212a: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 + 800212e: 4605 mov r5, r0 + 8002130: 460c mov r4, r1 + 8002132: 60c3 str r3, [r0, #12] + 8002134: d114 bne.n 8002160 + 8002136: 68c3 ldr r3, [r0, #12] + 8002138: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 + 800213c: 60c3 str r3, [r0, #12] + 800213e: 2400 movs r4, #0 + 8002140: 200a movs r0, #10 + 8002142: f7fe fb97 bl 8000874 + 8002146: 696b ldr r3, [r5, #20] + 8002148: 07d9 lsls r1, r3, #31 + 800214a: f104 040a add.w r4, r4, #10 + 800214e: d402 bmi.n 8002156 + 8002150: 2cc8 cmp r4, #200 @ 0xc8 + 8002152: d1f5 bne.n 8002140 + 8002154: 24c8 movs r4, #200 @ 0xc8 + 8002156: f1a4 03c8 sub.w r3, r4, #200 @ 0xc8 + 800215a: 4258 negs r0, r3 + 800215c: 4158 adcs r0, r3 + 800215e: bd38 pop {r3, r4, r5, pc} + 8002160: b971 cbnz r1, 8002180 + 8002162: 68c3 ldr r3, [r0, #12] + 8002164: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 + 8002168: 60c3 str r3, [r0, #12] + 800216a: 200a movs r0, #10 + 800216c: f7fe fb82 bl 8000874 + 8002170: 696b ldr r3, [r5, #20] + 8002172: 07da lsls r2, r3, #31 + 8002174: f104 040a add.w r4, r4, #10 + 8002178: d5ed bpl.n 8002156 + 800217a: 2cc8 cmp r4, #200 @ 0xc8 + 800217c: d1f5 bne.n 800216a + 800217e: e7e9 b.n 8002154 + 8002180: 2001 movs r0, #1 + 8002182: e7ec b.n 800215e + +08002184 : + 8002184: b082 sub sp, #8 + 8002186: 2300 movs r3, #0 + 8002188: 4602 mov r2, r0 + 800218a: 9301 str r3, [sp, #4] + 800218c: 9b01 ldr r3, [sp, #4] + 800218e: 3301 adds r3, #1 + 8002190: 9301 str r3, [sp, #4] + 8002192: 9b01 ldr r3, [sp, #4] + 8002194: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 8002198: d815 bhi.n 80021c6 + 800219a: 6913 ldr r3, [r2, #16] + 800219c: 2b00 cmp r3, #0 + 800219e: daf5 bge.n 800218c + 80021a0: 0189 lsls r1, r1, #6 + 80021a2: 2300 movs r3, #0 + 80021a4: f041 0120 orr.w r1, r1, #32 + 80021a8: 9301 str r3, [sp, #4] + 80021aa: 6111 str r1, [r2, #16] + 80021ac: 9b01 ldr r3, [sp, #4] + 80021ae: 3301 adds r3, #1 + 80021b0: 9301 str r3, [sp, #4] + 80021b2: 9b01 ldr r3, [sp, #4] + 80021b4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 80021b8: d805 bhi.n 80021c6 + 80021ba: 6910 ldr r0, [r2, #16] + 80021bc: f010 0020 ands.w r0, r0, #32 + 80021c0: d1f4 bne.n 80021ac + 80021c2: b002 add sp, #8 + 80021c4: 4770 bx lr + 80021c6: 2003 movs r0, #3 + 80021c8: e7fb b.n 80021c2 + +080021ca : + 80021ca: b082 sub sp, #8 + 80021cc: 2300 movs r3, #0 + 80021ce: 4602 mov r2, r0 + 80021d0: 9301 str r3, [sp, #4] + 80021d2: 9b01 ldr r3, [sp, #4] + 80021d4: 3301 adds r3, #1 + 80021d6: 9301 str r3, [sp, #4] + 80021d8: 9b01 ldr r3, [sp, #4] + 80021da: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 80021de: d813 bhi.n 8002208 + 80021e0: 6913 ldr r3, [r2, #16] + 80021e2: 2b00 cmp r3, #0 + 80021e4: daf5 bge.n 80021d2 + 80021e6: 2300 movs r3, #0 + 80021e8: 9301 str r3, [sp, #4] + 80021ea: 2310 movs r3, #16 + 80021ec: 6113 str r3, [r2, #16] + 80021ee: 9b01 ldr r3, [sp, #4] + 80021f0: 3301 adds r3, #1 + 80021f2: 9301 str r3, [sp, #4] + 80021f4: 9b01 ldr r3, [sp, #4] + 80021f6: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 + 80021fa: d805 bhi.n 8002208 + 80021fc: 6910 ldr r0, [r2, #16] + 80021fe: f010 0010 ands.w r0, r0, #16 + 8002202: d1f4 bne.n 80021ee + 8002204: b002 add sp, #8 + 8002206: 4770 bx lr + 8002208: 2003 movs r0, #3 + 800220a: e7fb b.n 8002204 + +0800220c : + 800220c: f8d0 3800 ldr.w r3, [r0, #2048] @ 0x800 + 8002210: 4319 orrs r1, r3 + 8002212: f8c0 1800 str.w r1, [r0, #2048] @ 0x800 + 8002216: 2000 movs r0, #0 + 8002218: 4770 bx lr + ... + +0800221c : + 800221c: b084 sub sp, #16 + 800221e: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8002222: 4604 mov r4, r0 + 8002224: a809 add r0, sp, #36 @ 0x24 + 8002226: e880 000e stmia.w r0, {r1, r2, r3} + 800222a: 2300 movs r3, #0 + 800222c: f89d 6024 ldrb.w r6, [sp, #36] @ 0x24 + 8002230: f89d 502e ldrb.w r5, [sp, #46] @ 0x2e + 8002234: 4619 mov r1, r3 + 8002236: f103 0240 add.w r2, r3, #64 @ 0x40 + 800223a: eb04 0282 add.w r2, r4, r2, lsl #2 + 800223e: 3301 adds r3, #1 + 8002240: 2b0f cmp r3, #15 + 8002242: 6051 str r1, [r2, #4] + 8002244: d1f7 bne.n 8002236 + 8002246: f504 6700 add.w r7, r4, #2048 @ 0x800 + 800224a: 2d00 cmp r5, #0 + 800224c: d16c bne.n 8002328 + 800224e: 687b ldr r3, [r7, #4] + 8002250: f043 0302 orr.w r3, r3, #2 + 8002254: 607b str r3, [r7, #4] + 8002256: 6ba3 ldr r3, [r4, #56] @ 0x38 + 8002258: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 + 800225c: 63a3 str r3, [r4, #56] @ 0x38 + 800225e: 6823 ldr r3, [r4, #0] + 8002260: f043 0340 orr.w r3, r3, #64 @ 0x40 + 8002264: 6023 str r3, [r4, #0] + 8002266: 6823 ldr r3, [r4, #0] + 8002268: f043 0380 orr.w r3, r3, #128 @ 0x80 + 800226c: 6023 str r3, [r4, #0] + 800226e: 2300 movs r3, #0 + 8002270: f8c4 3e00 str.w r3, [r4, #3584] @ 0xe00 + 8002274: f89d 3029 ldrb.w r3, [sp, #41] @ 0x29 + 8002278: 2b01 cmp r3, #1 + 800227a: d15c bne.n 8002336 + 800227c: f89d 1027 ldrb.w r1, [sp, #39] @ 0x27 + 8002280: 2900 cmp r1, #0 + 8002282: d156 bne.n 8002332 + 8002284: 4620 mov r0, r4 + 8002286: f7ff ffc1 bl 800220c + 800228a: 2110 movs r1, #16 + 800228c: 4620 mov r0, r4 + 800228e: f7ff ff79 bl 8002184 + 8002292: 4601 mov r1, r0 + 8002294: 4620 mov r0, r4 + 8002296: f7ff ff98 bl 80021ca + 800229a: 4308 orrs r0, r1 + 800229c: b2c0 uxtb r0, r0 + 800229e: 2300 movs r3, #0 + 80022a0: 3800 subs r0, #0 + 80022a2: 613b str r3, [r7, #16] + 80022a4: bf18 it ne + 80022a6: 2001 movne r0, #1 + 80022a8: 617b str r3, [r7, #20] + 80022aa: f504 6210 add.w r2, r4, #2304 @ 0x900 + 80022ae: 61fb str r3, [r7, #28] + 80022b0: 4619 mov r1, r3 + 80022b2: f04f 4c90 mov.w ip, #1207959552 @ 0x48000000 + 80022b6: f04f 6e00 mov.w lr, #134217728 @ 0x8000000 + 80022ba: f64f 387f movw r8, #64383 @ 0xfb7f + 80022be: 429e cmp r6, r3 + 80022c0: d83b bhi.n 800233a + 80022c2: 2200 movs r2, #0 + 80022c4: f504 6330 add.w r3, r4, #2816 @ 0xb00 + 80022c8: 4611 mov r1, r2 + 80022ca: f04f 4c90 mov.w ip, #1207959552 @ 0x48000000 + 80022ce: f04f 6e00 mov.w lr, #134217728 @ 0x8000000 + 80022d2: f64f 387f movw r8, #64383 @ 0xfb7f + 80022d6: 4296 cmp r6, r2 + 80022d8: d842 bhi.n 8002360 + 80022da: 693b ldr r3, [r7, #16] + 80022dc: f423 7380 bic.w r3, r3, #256 @ 0x100 + 80022e0: 613b str r3, [r7, #16] + 80022e2: 2300 movs r3, #0 + 80022e4: 61a3 str r3, [r4, #24] + 80022e6: f06f 4380 mvn.w r3, #1073741824 @ 0x40000000 + 80022ea: 6163 str r3, [r4, #20] + 80022ec: f89d 3026 ldrb.w r3, [sp, #38] @ 0x26 + 80022f0: b91b cbnz r3, 80022fa + 80022f2: 69a3 ldr r3, [r4, #24] + 80022f4: f043 0310 orr.w r3, r3, #16 + 80022f8: 61a3 str r3, [r4, #24] + 80022fa: 69a2 ldr r2, [r4, #24] + 80022fc: 4b22 ldr r3, [pc, #136] @ (8002388 ) + 80022fe: 4313 orrs r3, r2 + 8002300: 61a3 str r3, [r4, #24] + 8002302: f89d 302a ldrb.w r3, [sp, #42] @ 0x2a + 8002306: b11b cbz r3, 8002310 + 8002308: 69a3 ldr r3, [r4, #24] + 800230a: f043 0308 orr.w r3, r3, #8 + 800230e: 61a3 str r3, [r4, #24] + 8002310: 2d01 cmp r5, #1 + 8002312: bf01 itttt eq + 8002314: 69a3 ldreq r3, [r4, #24] + 8002316: f043 4380 orreq.w r3, r3, #1073741824 @ 0x40000000 + 800231a: f043 0304 orreq.w r3, r3, #4 + 800231e: 61a3 streq r3, [r4, #24] + 8002320: e8bd 43f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8002324: b004 add sp, #16 + 8002326: 4770 bx lr + 8002328: 6ba3 ldr r3, [r4, #56] @ 0x38 + 800232a: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 + 800232e: 63a3 str r3, [r4, #56] @ 0x38 + 8002330: e79d b.n 800226e + 8002332: 4619 mov r1, r3 + 8002334: e7a6 b.n 8002284 + 8002336: 2103 movs r1, #3 + 8002338: e7a4 b.n 8002284 + 800233a: f8d2 9000 ldr.w r9, [r2] + 800233e: f1b9 0f00 cmp.w r9, #0 + 8002342: da0b bge.n 800235c + 8002344: b93b cbnz r3, 8002356 + 8002346: f8c2 e000 str.w lr, [r2] + 800234a: 6111 str r1, [r2, #16] + 800234c: 3301 adds r3, #1 + 800234e: f8c2 8008 str.w r8, [r2, #8] + 8002352: 3220 adds r2, #32 + 8002354: e7b3 b.n 80022be + 8002356: f8c2 c000 str.w ip, [r2] + 800235a: e7f6 b.n 800234a + 800235c: 6011 str r1, [r2, #0] + 800235e: e7f4 b.n 800234a + 8002360: f8d3 9000 ldr.w r9, [r3] + 8002364: f1b9 0f00 cmp.w r9, #0 + 8002368: da0b bge.n 8002382 + 800236a: b93a cbnz r2, 800237c + 800236c: f8c3 e000 str.w lr, [r3] + 8002370: 6119 str r1, [r3, #16] + 8002372: 3201 adds r2, #1 + 8002374: f8c3 8008 str.w r8, [r3, #8] + 8002378: 3320 adds r3, #32 + 800237a: e7ac b.n 80022d6 + 800237c: f8c3 c000 str.w ip, [r3] + 8002380: e7f6 b.n 8002370 + 8002382: 6019 str r1, [r3, #0] + 8002384: e7f4 b.n 8002370 + 8002386: bf00 nop + 8002388: 803c3800 .word 0x803c3800 + +0800238c : + 800238c: f8d0 3808 ldr.w r3, [r0, #2056] @ 0x808 + 8002390: f013 0006 ands.w r0, r3, #6 + 8002394: d004 beq.n 80023a0 + 8002396: f013 0f02 tst.w r3, #2 + 800239a: bf14 ite ne + 800239c: 2002 movne r0, #2 + 800239e: 200f moveq r0, #15 + 80023a0: 4770 bx lr + +080023a2 : + 80023a2: b530 push {r4, r5, lr} + 80023a4: 780c ldrb r4, [r1, #0] + 80023a6: 2201 movs r2, #1 + 80023a8: f004 050f and.w r5, r4, #15 + 80023ac: 40aa lsls r2, r5 + 80023ae: 784d ldrb r5, [r1, #1] + 80023b0: 2d01 cmp r5, #1 + 80023b2: f500 6300 add.w r3, r0, #2048 @ 0x800 + 80023b6: eb00 1044 add.w r0, r0, r4, lsl #5 + 80023ba: d119 bne.n 80023f0 + 80023bc: 69dd ldr r5, [r3, #28] + 80023be: 432a orrs r2, r5 + 80023c0: 61da str r2, [r3, #28] + 80023c2: f8d0 3900 ldr.w r3, [r0, #2304] @ 0x900 + 80023c6: 041a lsls r2, r3, #16 + 80023c8: d410 bmi.n 80023ec + 80023ca: 688a ldr r2, [r1, #8] + 80023cc: f8d0 5900 ldr.w r5, [r0, #2304] @ 0x900 + 80023d0: f3c2 030a ubfx r3, r2, #0, #11 + 80023d4: 790a ldrb r2, [r1, #4] + 80023d6: 432b orrs r3, r5 + 80023d8: ea43 4382 orr.w r3, r3, r2, lsl #18 + 80023dc: ea43 5384 orr.w r3, r3, r4, lsl #22 + 80023e0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 80023e4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 80023e8: f8c0 3900 str.w r3, [r0, #2304] @ 0x900 + 80023ec: 2000 movs r0, #0 + 80023ee: bd30 pop {r4, r5, pc} + 80023f0: 69dc ldr r4, [r3, #28] + 80023f2: ea44 4202 orr.w r2, r4, r2, lsl #16 + 80023f6: 61da str r2, [r3, #28] + 80023f8: f8d0 3b00 ldr.w r3, [r0, #2816] @ 0xb00 + 80023fc: 041b lsls r3, r3, #16 + 80023fe: d4f5 bmi.n 80023ec + 8002400: 688b ldr r3, [r1, #8] + 8002402: f8d0 2b00 ldr.w r2, [r0, #2816] @ 0xb00 + 8002406: f3c3 030a ubfx r3, r3, #0, #11 + 800240a: 4313 orrs r3, r2 + 800240c: 790a ldrb r2, [r1, #4] + 800240e: ea43 4382 orr.w r3, r3, r2, lsl #18 + 8002412: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8002416: f443 4300 orr.w r3, r3, #32768 @ 0x8000 + 800241a: f8c0 3b00 str.w r3, [r0, #2816] @ 0xb00 + 800241e: e7e5 b.n 80023ec + +08002420 : + 8002420: b510 push {r4, lr} + 8002422: 780a ldrb r2, [r1, #0] + 8002424: 7849 ldrb r1, [r1, #1] + 8002426: 2901 cmp r1, #1 + 8002428: eb00 1342 add.w r3, r0, r2, lsl #5 + 800242c: f500 6000 add.w r0, r0, #2048 @ 0x800 + 8002430: f002 020f and.w r2, r2, #15 + 8002434: d122 bne.n 800247c + 8002436: f8d3 1900 ldr.w r1, [r3, #2304] @ 0x900 + 800243a: 2900 cmp r1, #0 + 800243c: da0b bge.n 8002456 + 800243e: f8d3 1900 ldr.w r1, [r3, #2304] @ 0x900 + 8002442: f041 6100 orr.w r1, r1, #134217728 @ 0x8000000 + 8002446: f8c3 1900 str.w r1, [r3, #2304] @ 0x900 + 800244a: f8d3 1900 ldr.w r1, [r3, #2304] @ 0x900 + 800244e: f041 4180 orr.w r1, r1, #1073741824 @ 0x40000000 + 8002452: f8c3 1900 str.w r1, [r3, #2304] @ 0x900 + 8002456: 6bc4 ldr r4, [r0, #60] @ 0x3c + 8002458: 2101 movs r1, #1 + 800245a: fa01 f202 lsl.w r2, r1, r2 + 800245e: ea24 0402 bic.w r4, r4, r2 + 8002462: 63c4 str r4, [r0, #60] @ 0x3c + 8002464: 69c1 ldr r1, [r0, #28] + 8002466: ea21 0202 bic.w r2, r1, r2 + 800246a: 61c2 str r2, [r0, #28] + 800246c: f8d3 1900 ldr.w r1, [r3, #2304] @ 0x900 + 8002470: 4a14 ldr r2, [pc, #80] @ (80024c4 ) + 8002472: 400a ands r2, r1 + 8002474: f8c3 2900 str.w r2, [r3, #2304] @ 0x900 + 8002478: 2000 movs r0, #0 + 800247a: bd10 pop {r4, pc} + 800247c: f8d3 1b00 ldr.w r1, [r3, #2816] @ 0xb00 + 8002480: 2900 cmp r1, #0 + 8002482: da0b bge.n 800249c + 8002484: f8d3 1b00 ldr.w r1, [r3, #2816] @ 0xb00 + 8002488: f041 6100 orr.w r1, r1, #134217728 @ 0x8000000 + 800248c: f8c3 1b00 str.w r1, [r3, #2816] @ 0xb00 + 8002490: f8d3 1b00 ldr.w r1, [r3, #2816] @ 0xb00 + 8002494: f041 4180 orr.w r1, r1, #1073741824 @ 0x40000000 + 8002498: f8c3 1b00 str.w r1, [r3, #2816] @ 0xb00 + 800249c: 6bc4 ldr r4, [r0, #60] @ 0x3c + 800249e: f44f 3180 mov.w r1, #65536 @ 0x10000 + 80024a2: fa01 f202 lsl.w r2, r1, r2 + 80024a6: ea24 0402 bic.w r4, r4, r2 + 80024aa: 63c4 str r4, [r0, #60] @ 0x3c + 80024ac: 69c1 ldr r1, [r0, #28] + 80024ae: ea21 0202 bic.w r2, r1, r2 + 80024b2: 61c2 str r2, [r0, #28] + 80024b4: f8d3 1b00 ldr.w r1, [r3, #2816] @ 0xb00 + 80024b8: 4a03 ldr r2, [pc, #12] @ (80024c8 ) + 80024ba: 400a ands r2, r1 + 80024bc: f8c3 2b00 str.w r2, [r3, #2816] @ 0xb00 + 80024c0: e7da b.n 8002478 + 80024c2: bf00 nop + 80024c4: ec337800 .word 0xec337800 + 80024c8: eff37800 .word 0xeff37800 + +080024cc : + 80024cc: b082 sub sp, #8 + 80024ce: 2300 movs r3, #0 + 80024d0: 784a ldrb r2, [r1, #1] + 80024d2: 9301 str r3, [sp, #4] + 80024d4: 780b ldrb r3, [r1, #0] + 80024d6: 2a01 cmp r2, #1 + 80024d8: ea4f 1343 mov.w r3, r3, lsl #5 + 80024dc: d11e bne.n 800251c + 80024de: f500 6010 add.w r0, r0, #2304 @ 0x900 + 80024e2: 18c1 adds r1, r0, r3 + 80024e4: 58c2 ldr r2, [r0, r3] + 80024e6: 2a00 cmp r2, #0 + 80024e8: db02 blt.n 80024f0 + 80024ea: 2000 movs r0, #0 + 80024ec: b002 add sp, #8 + 80024ee: 4770 bx lr + 80024f0: 58c2 ldr r2, [r0, r3] + 80024f2: f042 6200 orr.w r2, r2, #134217728 @ 0x8000000 + 80024f6: 50c2 str r2, [r0, r3] + 80024f8: 58c2 ldr r2, [r0, r3] + 80024fa: f042 4280 orr.w r2, r2, #1073741824 @ 0x40000000 + 80024fe: 50c2 str r2, [r0, r3] + 8002500: f242 7210 movw r2, #10000 @ 0x2710 + 8002504: 9b01 ldr r3, [sp, #4] + 8002506: 3301 adds r3, #1 + 8002508: 9301 str r3, [sp, #4] + 800250a: 9b01 ldr r3, [sp, #4] + 800250c: 4293 cmp r3, r2 + 800250e: d901 bls.n 8002514 + 8002510: 2001 movs r0, #1 + 8002512: e7eb b.n 80024ec + 8002514: 680b ldr r3, [r1, #0] + 8002516: 2b00 cmp r3, #0 + 8002518: dbf4 blt.n 8002504 + 800251a: e7e6 b.n 80024ea + 800251c: f500 6030 add.w r0, r0, #2816 @ 0xb00 + 8002520: 18c1 adds r1, r0, r3 + 8002522: 58c2 ldr r2, [r0, r3] + 8002524: 2a00 cmp r2, #0 + 8002526: dae0 bge.n 80024ea + 8002528: 58c2 ldr r2, [r0, r3] + 800252a: f042 6200 orr.w r2, r2, #134217728 @ 0x8000000 + 800252e: 50c2 str r2, [r0, r3] + 8002530: 58c2 ldr r2, [r0, r3] + 8002532: f042 4280 orr.w r2, r2, #1073741824 @ 0x40000000 + 8002536: 50c2 str r2, [r0, r3] + 8002538: f242 7210 movw r2, #10000 @ 0x2710 + 800253c: 9b01 ldr r3, [sp, #4] + 800253e: 3301 adds r3, #1 + 8002540: 9301 str r3, [sp, #4] + 8002542: 9b01 ldr r3, [sp, #4] + 8002544: 4293 cmp r3, r2 + 8002546: d8e3 bhi.n 8002510 + 8002548: 680b ldr r3, [r1, #0] + 800254a: 2b00 cmp r3, #0 + 800254c: dbf6 blt.n 800253c + 800254e: e7cc b.n 80024ea + +08002550 : + 8002550: b510 push {r4, lr} + 8002552: f89d 4008 ldrb.w r4, [sp, #8] + 8002556: b944 cbnz r4, 800256a + 8002558: 3303 adds r3, #3 + 800255a: 3201 adds r2, #1 + 800255c: 089b lsrs r3, r3, #2 + 800255e: eb00 3002 add.w r0, r0, r2, lsl #12 + 8002562: eb01 0383 add.w r3, r1, r3, lsl #2 + 8002566: 4299 cmp r1, r3 + 8002568: d101 bne.n 800256e + 800256a: 2000 movs r0, #0 + 800256c: bd10 pop {r4, pc} + 800256e: f851 2b04 ldr.w r2, [r1], #4 + 8002572: 6002 str r2, [r0, #0] + 8002574: e7f7 b.n 8002566 + ... + +08002578 : + 8002578: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + 800257c: 784b ldrb r3, [r1, #1] + 800257e: 690c ldr r4, [r1, #16] + 8002580: 790f ldrb r7, [r1, #4] + 8002582: f8df e1f0 ldr.w lr, [pc, #496] @ 8002774 + 8002586: f8df 81f0 ldr.w r8, [pc, #496] @ 8002778 + 800258a: 4616 mov r6, r2 + 800258c: 780a ldrb r2, [r1, #0] + 800258e: 2b01 cmp r3, #1 + 8002590: eb00 1542 add.w r5, r0, r2, lsl #5 + 8002594: f040 8097 bne.w 80026c6 + 8002598: f505 6c10 add.w ip, r5, #2304 @ 0x900 + 800259c: f8dc 3010 ldr.w r3, [ip, #16] + 80025a0: bb74 cbnz r4, 8002600 + 80025a2: ea03 030e and.w r3, r3, lr + 80025a6: f8cc 3010 str.w r3, [ip, #16] + 80025aa: f8dc 3010 ldr.w r3, [ip, #16] + 80025ae: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 80025b2: f8cc 3010 str.w r3, [ip, #16] + 80025b6: f8dc 3010 ldr.w r3, [ip, #16] + 80025ba: ea03 0308 and.w r3, r3, r8 + 80025be: 2e01 cmp r6, #1 + 80025c0: f8cc 3010 str.w r3, [ip, #16] + 80025c4: d157 bne.n 8002676 + 80025c6: 69cb ldr r3, [r1, #28] + 80025c8: b10b cbz r3, 80025ce + 80025ca: f8cc 3014 str.w r3, [ip, #20] + 80025ce: 2f01 cmp r7, #1 + 80025d0: d10c bne.n 80025ec + 80025d2: f8d0 3808 ldr.w r3, [r0, #2056] @ 0x808 + 80025d6: f413 7f80 tst.w r3, #256 @ 0x100 + 80025da: f8d5 3900 ldr.w r3, [r5, #2304] @ 0x900 + 80025de: bf0c ite eq + 80025e0: f043 5300 orreq.w r3, r3, #536870912 @ 0x20000000 + 80025e4: f043 5380 orrne.w r3, r3, #268435456 @ 0x10000000 + 80025e8: f8c5 3900 str.w r3, [r5, #2304] @ 0x900 + 80025ec: f8d5 3900 ldr.w r3, [r5, #2304] @ 0x900 + 80025f0: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 + 80025f4: f8c5 3900 str.w r3, [r5, #2304] @ 0x900 + 80025f8: 2000 movs r0, #0 + 80025fa: b002 add sp, #8 + 80025fc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8002600: ea03 0308 and.w r3, r3, r8 + 8002604: f8cc 3010 str.w r3, [ip, #16] + 8002608: f8dc 3010 ldr.w r3, [ip, #16] + 800260c: ea03 030e and.w r3, r3, lr + 8002610: f8cc 3010 str.w r3, [ip, #16] + 8002614: 688b ldr r3, [r1, #8] + 8002616: b97a cbnz r2, 8002638 + 8002618: 42a3 cmp r3, r4 + 800261a: bf38 it cc + 800261c: 610b strcc r3, [r1, #16] + 800261e: f8dc 3010 ldr.w r3, [ip, #16] + 8002622: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8002626: f8cc 3010 str.w r3, [ip, #16] + 800262a: 690b ldr r3, [r1, #16] + 800262c: f8dc 4010 ldr.w r4, [ip, #16] + 8002630: f3c3 0312 ubfx r3, r3, #0, #19 + 8002634: 4323 orrs r3, r4 + 8002636: e7c2 b.n 80025be + 8002638: 441c add r4, r3 + 800263a: 3c01 subs r4, #1 + 800263c: fbb4 f4f3 udiv r4, r4, r3 + 8002640: 4b4b ldr r3, [pc, #300] @ (8002770 ) + 8002642: f8dc e010 ldr.w lr, [ip, #16] + 8002646: fa1f f884 uxth.w r8, r4 + 800264a: ea03 44c4 and.w r4, r3, r4, lsl #19 + 800264e: ea44 040e orr.w r4, r4, lr + 8002652: 2f01 cmp r7, #1 + 8002654: f8cc 4010 str.w r4, [ip, #16] + 8002658: d1e7 bne.n 800262a + 800265a: f8dc 3010 ldr.w r3, [ip, #16] + 800265e: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 + 8002662: f8cc 3010 str.w r3, [ip, #16] + 8002666: f8dc 4010 ldr.w r4, [ip, #16] + 800266a: ea4f 7348 mov.w r3, r8, lsl #29 + 800266e: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000 + 8002672: 4323 orrs r3, r4 + 8002674: e7d7 b.n 8002626 + 8002676: f8d5 3900 ldr.w r3, [r5, #2304] @ 0x900 + 800267a: 2f01 cmp r7, #1 + 800267c: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 + 8002680: f8c5 3900 str.w r3, [r5, #2304] @ 0x900 + 8002684: 690b ldr r3, [r1, #16] + 8002686: d00b beq.n 80026a0 + 8002688: 2b00 cmp r3, #0 + 800268a: d0b5 beq.n 80025f8 + 800268c: f8d0 1834 ldr.w r1, [r0, #2100] @ 0x834 + 8002690: f002 020f and.w r2, r2, #15 + 8002694: 2301 movs r3, #1 + 8002696: 4093 lsls r3, r2 + 8002698: 430b orrs r3, r1 + 800269a: f8c0 3834 str.w r3, [r0, #2100] @ 0x834 + 800269e: e7ab b.n 80025f8 + 80026a0: f8d0 4808 ldr.w r4, [r0, #2056] @ 0x808 + 80026a4: f414 7f80 tst.w r4, #256 @ 0x100 + 80026a8: f8d5 4900 ldr.w r4, [r5, #2304] @ 0x900 + 80026ac: bf0c ite eq + 80026ae: f044 5400 orreq.w r4, r4, #536870912 @ 0x20000000 + 80026b2: f044 5480 orrne.w r4, r4, #268435456 @ 0x10000000 + 80026b6: f8c5 4900 str.w r4, [r5, #2304] @ 0x900 + 80026ba: 9600 str r6, [sp, #0] + 80026bc: 68c9 ldr r1, [r1, #12] + 80026be: b29b uxth r3, r3 + 80026c0: f7ff ff46 bl 8002550 + 80026c4: e798 b.n 80025f8 + 80026c6: f8d5 3b10 ldr.w r3, [r5, #2832] @ 0xb10 + 80026ca: ea03 0308 and.w r3, r3, r8 + 80026ce: f8c5 3b10 str.w r3, [r5, #2832] @ 0xb10 + 80026d2: f8d5 3b10 ldr.w r3, [r5, #2832] @ 0xb10 + 80026d6: ea03 030e and.w r3, r3, lr + 80026da: f505 6c30 add.w ip, r5, #2816 @ 0xb00 + 80026de: f8cc 3010 str.w r3, [ip, #16] + 80026e2: 688b ldr r3, [r1, #8] + 80026e4: bb5a cbnz r2, 800273e + 80026e6: b104 cbz r4, 80026ea + 80026e8: 610b str r3, [r1, #16] + 80026ea: 620b str r3, [r1, #32] + 80026ec: f8dc 2010 ldr.w r2, [ip, #16] + 80026f0: f3c3 0312 ubfx r3, r3, #0, #19 + 80026f4: 4313 orrs r3, r2 + 80026f6: f8cc 3010 str.w r3, [ip, #16] + 80026fa: f8dc 3010 ldr.w r3, [ip, #16] + 80026fe: f443 2300 orr.w r3, r3, #524288 @ 0x80000 + 8002702: 2e01 cmp r6, #1 + 8002704: f8cc 3010 str.w r3, [ip, #16] + 8002708: d103 bne.n 8002712 + 800270a: 68cb ldr r3, [r1, #12] + 800270c: b10b cbz r3, 8002712 + 800270e: f8cc 3014 str.w r3, [ip, #20] + 8002712: 2f01 cmp r7, #1 + 8002714: d10c bne.n 8002730 + 8002716: f8d0 3808 ldr.w r3, [r0, #2056] @ 0x808 + 800271a: f413 7f80 tst.w r3, #256 @ 0x100 + 800271e: f8d5 3b00 ldr.w r3, [r5, #2816] @ 0xb00 + 8002722: bf0c ite eq + 8002724: f043 5300 orreq.w r3, r3, #536870912 @ 0x20000000 + 8002728: f043 5380 orrne.w r3, r3, #268435456 @ 0x10000000 + 800272c: f8c5 3b00 str.w r3, [r5, #2816] @ 0xb00 + 8002730: f8d5 3b00 ldr.w r3, [r5, #2816] @ 0xb00 + 8002734: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 + 8002738: f8c5 3b00 str.w r3, [r5, #2816] @ 0xb00 + 800273c: e75c b.n 80025f8 + 800273e: 2c00 cmp r4, #0 + 8002740: d0d4 beq.n 80026ec + 8002742: 441c add r4, r3 + 8002744: 4a0a ldr r2, [pc, #40] @ (8002770 ) + 8002746: f8dc e010 ldr.w lr, [ip, #16] + 800274a: 3c01 subs r4, #1 + 800274c: fbb4 f4f3 udiv r4, r4, r3 + 8002750: b2a4 uxth r4, r4 + 8002752: ea02 42c4 and.w r2, r2, r4, lsl #19 + 8002756: 4363 muls r3, r4 + 8002758: ea42 020e orr.w r2, r2, lr + 800275c: 620b str r3, [r1, #32] + 800275e: f8cc 2010 str.w r2, [ip, #16] + 8002762: f8dc 2010 ldr.w r2, [ip, #16] + 8002766: f3c3 0312 ubfx r3, r3, #0, #19 + 800276a: 4313 orrs r3, r2 + 800276c: e7c9 b.n 8002702 + 800276e: bf00 nop + 8002770: 1ff80000 .word 0x1ff80000 + 8002774: e007ffff .word 0xe007ffff + 8002778: fff80000 .word 0xfff80000 + +0800277c : + 800277c: 4603 mov r3, r0 + 800277e: b570 push {r4, r5, r6, lr} + 8002780: 2000 movs r0, #0 + 8002782: 0894 lsrs r4, r2, #2 + 8002784: f503 5580 add.w r5, r3, #4096 @ 0x1000 + 8002788: f002 0203 and.w r2, r2, #3 + 800278c: 42a0 cmp r0, r4 + 800278e: d310 bcc.n 80027b2 + 8002790: eb01 0084 add.w r0, r1, r4, lsl #2 + 8002794: b162 cbz r2, 80027b0 + 8002796: f503 5380 add.w r3, r3, #4096 @ 0x1000 + 800279a: 681c ldr r4, [r3, #0] + 800279c: 2300 movs r3, #0 + 800279e: 00d9 lsls r1, r3, #3 + 80027a0: fa24 f101 lsr.w r1, r4, r1 + 80027a4: 54c1 strb r1, [r0, r3] + 80027a6: 3301 adds r3, #1 + 80027a8: b299 uxth r1, r3 + 80027aa: 428a cmp r2, r1 + 80027ac: d1f7 bne.n 800279e + 80027ae: 4410 add r0, r2 + 80027b0: bd70 pop {r4, r5, r6, pc} + 80027b2: 682e ldr r6, [r5, #0] + 80027b4: f841 6020 str.w r6, [r1, r0, lsl #2] + 80027b8: 3001 adds r0, #1 + 80027ba: e7e7 b.n 800278c + +080027bc : + 80027bc: 784a ldrb r2, [r1, #1] + 80027be: 780b ldrb r3, [r1, #0] + 80027c0: 2a01 cmp r2, #1 + 80027c2: eb00 1043 add.w r0, r0, r3, lsl #5 + 80027c6: d112 bne.n 80027ee + 80027c8: f8d0 2900 ldr.w r2, [r0, #2304] @ 0x900 + 80027cc: 2a00 cmp r2, #0 + 80027ce: db06 blt.n 80027de + 80027d0: b12b cbz r3, 80027de + 80027d2: f8d0 3900 ldr.w r3, [r0, #2304] @ 0x900 + 80027d6: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 + 80027da: f8c0 3900 str.w r3, [r0, #2304] @ 0x900 + 80027de: f8d0 3900 ldr.w r3, [r0, #2304] @ 0x900 + 80027e2: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 + 80027e6: f8c0 3900 str.w r3, [r0, #2304] @ 0x900 + 80027ea: 2000 movs r0, #0 + 80027ec: 4770 bx lr + 80027ee: f8d0 2b00 ldr.w r2, [r0, #2816] @ 0xb00 + 80027f2: 2a00 cmp r2, #0 + 80027f4: db06 blt.n 8002804 + 80027f6: b12b cbz r3, 8002804 + 80027f8: f8d0 3b00 ldr.w r3, [r0, #2816] @ 0xb00 + 80027fc: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 + 8002800: f8c0 3b00 str.w r3, [r0, #2816] @ 0xb00 + 8002804: f8d0 3b00 ldr.w r3, [r0, #2816] @ 0xb00 + 8002808: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 + 800280c: f8c0 3b00 str.w r3, [r0, #2816] @ 0xb00 + 8002810: e7eb b.n 80027ea + +08002812 : + 8002812: 780b ldrb r3, [r1, #0] + 8002814: 784a ldrb r2, [r1, #1] + 8002816: eb00 1043 add.w r0, r0, r3, lsl #5 + 800281a: 790b ldrb r3, [r1, #4] + 800281c: 2a01 cmp r2, #1 + 800281e: f1a3 0302 sub.w r3, r3, #2 + 8002822: b2db uxtb r3, r3 + 8002824: d10f bne.n 8002846 + 8002826: f8d0 2900 ldr.w r2, [r0, #2304] @ 0x900 + 800282a: 2b01 cmp r3, #1 + 800282c: f422 1200 bic.w r2, r2, #2097152 @ 0x200000 + 8002830: f8c0 2900 str.w r2, [r0, #2304] @ 0x900 + 8002834: d805 bhi.n 8002842 + 8002836: f8d0 3900 ldr.w r3, [r0, #2304] @ 0x900 + 800283a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800283e: f8c0 3900 str.w r3, [r0, #2304] @ 0x900 + 8002842: 2000 movs r0, #0 + 8002844: 4770 bx lr + 8002846: f8d0 2b00 ldr.w r2, [r0, #2816] @ 0xb00 + 800284a: f422 1200 bic.w r2, r2, #2097152 @ 0x200000 + 800284e: 2b01 cmp r3, #1 + 8002850: f8c0 2b00 str.w r2, [r0, #2816] @ 0xb00 + 8002854: bf9e ittt ls + 8002856: f8d0 3b00 ldrls.w r3, [r0, #2816] @ 0xb00 + 800285a: f043 5380 orrls.w r3, r3, #268435456 @ 0x10000000 + 800285e: f8c0 3b00 strls.w r3, [r0, #2816] @ 0xb00 + 8002862: e7ee b.n 8002842 + +08002864 : + 8002864: f8d0 3800 ldr.w r3, [r0, #2048] @ 0x800 + 8002868: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 + 800286c: f8c0 3800 str.w r3, [r0, #2048] @ 0x800 + 8002870: f8d0 3800 ldr.w r3, [r0, #2048] @ 0x800 + 8002874: 0109 lsls r1, r1, #4 + 8002876: f401 61fe and.w r1, r1, #2032 @ 0x7f0 + 800287a: 4319 orrs r1, r3 + 800287c: f8c0 1800 str.w r1, [r0, #2048] @ 0x800 + 8002880: 2000 movs r0, #0 + 8002882: 4770 bx lr + +08002884 : + 8002884: f8d0 3e00 ldr.w r3, [r0, #3584] @ 0xe00 + 8002888: f023 0303 bic.w r3, r3, #3 + 800288c: f8c0 3e00 str.w r3, [r0, #3584] @ 0xe00 + 8002890: f8d0 3804 ldr.w r3, [r0, #2052] @ 0x804 + 8002894: f023 0302 bic.w r3, r3, #2 + 8002898: f8c0 3804 str.w r3, [r0, #2052] @ 0x804 + 800289c: 2000 movs r0, #0 + 800289e: 4770 bx lr + +080028a0 : + 80028a0: f8d0 3e00 ldr.w r3, [r0, #3584] @ 0xe00 + 80028a4: f023 0303 bic.w r3, r3, #3 + 80028a8: f8c0 3e00 str.w r3, [r0, #3584] @ 0xe00 + 80028ac: f8d0 3804 ldr.w r3, [r0, #2052] @ 0x804 + 80028b0: f043 0302 orr.w r3, r3, #2 + 80028b4: f8c0 3804 str.w r3, [r0, #2052] @ 0x804 + 80028b8: 2000 movs r0, #0 + 80028ba: 4770 bx lr + +080028bc : + 80028bc: 6942 ldr r2, [r0, #20] + 80028be: 6980 ldr r0, [r0, #24] + 80028c0: 4010 ands r0, r2 + 80028c2: 4770 bx lr + +080028c4 : + 80028c4: f8d0 3818 ldr.w r3, [r0, #2072] @ 0x818 + 80028c8: f500 6000 add.w r0, r0, #2048 @ 0x800 + 80028cc: 69c0 ldr r0, [r0, #28] + 80028ce: 4018 ands r0, r3 + 80028d0: 0c00 lsrs r0, r0, #16 + 80028d2: 4770 bx lr + +080028d4 : + 80028d4: f8d0 3818 ldr.w r3, [r0, #2072] @ 0x818 + 80028d8: f500 6000 add.w r0, r0, #2048 @ 0x800 + 80028dc: 69c0 ldr r0, [r0, #28] + 80028de: 4018 ands r0, r3 + 80028e0: b280 uxth r0, r0 + 80028e2: 4770 bx lr + +080028e4 : + 80028e4: eb00 1141 add.w r1, r0, r1, lsl #5 + 80028e8: f500 6000 add.w r0, r0, #2048 @ 0x800 + 80028ec: f8d1 2b08 ldr.w r2, [r1, #2824] @ 0xb08 + 80028f0: 6940 ldr r0, [r0, #20] + 80028f2: 4010 ands r0, r2 + 80028f4: 4770 bx lr + +080028f6 : + 80028f6: f8d0 2810 ldr.w r2, [r0, #2064] @ 0x810 + 80028fa: f8d0 3834 ldr.w r3, [r0, #2100] @ 0x834 + 80028fe: eb00 1041 add.w r0, r0, r1, lsl #5 + 8002902: f001 010f and.w r1, r1, #15 + 8002906: 40cb lsrs r3, r1 + 8002908: f500 6010 add.w r0, r0, #2304 @ 0x900 + 800290c: 01db lsls r3, r3, #7 + 800290e: 6880 ldr r0, [r0, #8] + 8002910: b2db uxtb r3, r3 + 8002912: 4313 orrs r3, r2 + 8002914: 4018 ands r0, r3 + 8002916: 4770 bx lr + +08002918 : + 8002918: 6940 ldr r0, [r0, #20] + 800291a: f000 0001 and.w r0, r0, #1 + 800291e: 4770 bx lr + +08002920 : + 8002920: f8d0 3900 ldr.w r3, [r0, #2304] @ 0x900 + 8002924: f36f 030a bfc r3, #0, #11 + 8002928: f8c0 3900 str.w r3, [r0, #2304] @ 0x900 + 800292c: f8d0 3804 ldr.w r3, [r0, #2052] @ 0x804 + 8002930: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8002934: f8c0 3804 str.w r3, [r0, #2052] @ 0x804 + 8002938: 2000 movs r0, #0 + 800293a: 4770 bx lr + +0800293c : + 800293c: b530 push {r4, r5, lr} + 800293e: 6c05 ldr r5, [r0, #64] @ 0x40 + 8002940: 4c10 ldr r4, [pc, #64] @ (8002984 ) + 8002942: 42a5 cmp r5, r4 + 8002944: f500 6330 add.w r3, r0, #2816 @ 0xb00 + 8002948: d903 bls.n 8002952 + 800294a: f8d0 4b00 ldr.w r4, [r0, #2816] @ 0xb00 + 800294e: 2c00 cmp r4, #0 + 8002950: db16 blt.n 8002980 + 8002952: 2400 movs r4, #0 + 8002954: 611c str r4, [r3, #16] + 8002956: 691c ldr r4, [r3, #16] + 8002958: f444 2400 orr.w r4, r4, #524288 @ 0x80000 + 800295c: 611c str r4, [r3, #16] + 800295e: 691c ldr r4, [r3, #16] + 8002960: f044 0418 orr.w r4, r4, #24 + 8002964: 611c str r4, [r3, #16] + 8002966: 691c ldr r4, [r3, #16] + 8002968: 2901 cmp r1, #1 + 800296a: f044 44c0 orr.w r4, r4, #1610612736 @ 0x60000000 + 800296e: 611c str r4, [r3, #16] + 8002970: bf01 itttt eq + 8002972: 615a streq r2, [r3, #20] + 8002974: f8d0 3b00 ldreq.w r3, [r0, #2816] @ 0xb00 + 8002978: f043 2380 orreq.w r3, r3, #2147516416 @ 0x80008000 + 800297c: f8c0 3b00 streq.w r3, [r0, #2816] @ 0xb00 + 8002980: 2000 movs r0, #0 + 8002982: bd30 pop {r4, r5, pc} + 8002984: 4f54300a .word 0x4f54300a + +08002988 : + 8002988: f8d0 32d4 ldr.w r3, [r0, #724] @ 0x2d4 + 800298c: 33b0 adds r3, #176 @ 0xb0 + 800298e: f850 3023 ldr.w r3, [r0, r3, lsl #2] + 8002992: 2000 movs r0, #0 + 8002994: 7318 strb r0, [r3, #12] + 8002996: 4770 bx lr + +08002998 : + 8002998: 230a movs r3, #10 + 800299a: 8003 strh r3, [r0, #0] + 800299c: 4800 ldr r0, [pc, #0] @ (80029a0 ) + 800299e: 4770 bx lr + 80029a0: 2000004c .word 0x2000004c + +080029a4 : + 80029a4: b510 push {r4, lr} + 80029a6: 2181 movs r1, #129 @ 0x81 + 80029a8: 4604 mov r4, r0 + 80029aa: 4805 ldr r0, [pc, #20] @ (80029c0 ) + 80029ac: f000 fa7e bl 8002eac + 80029b0: b108 cbz r0, 80029b6 + 80029b2: 230a movs r3, #10 + 80029b4: 7183 strb r3, [r0, #6] + 80029b6: 2322 movs r3, #34 @ 0x22 + 80029b8: 4801 ldr r0, [pc, #4] @ (80029c0 ) + 80029ba: 8023 strh r3, [r4, #0] + 80029bc: bd10 pop {r4, pc} + 80029be: bf00 nop + 80029c0: 20000064 .word 0x20000064 + +080029c4 : + 80029c4: f7ff bfee b.w 80029a4 + +080029c8 : + 80029c8: b510 push {r4, lr} + 80029ca: 2181 movs r1, #129 @ 0x81 + 80029cc: 4604 mov r4, r0 + 80029ce: 4805 ldr r0, [pc, #20] @ (80029e4 ) + 80029d0: f000 fa6c bl 8002eac + 80029d4: b108 cbz r0, 80029da + 80029d6: 2307 movs r3, #7 + 80029d8: 7183 strb r3, [r0, #6] + 80029da: 2322 movs r3, #34 @ 0x22 + 80029dc: 4801 ldr r0, [pc, #4] @ (80029e4 ) + 80029de: 8023 strh r3, [r4, #0] + 80029e0: bd10 pop {r4, pc} + 80029e2: bf00 nop + 80029e4: 20000064 .word 0x20000064 + +080029e8 : + 80029e8: f8d0 32d4 ldr.w r3, [r0, #724] @ 0x2d4 + 80029ec: b513 push {r0, r1, r4, lr} + 80029ee: 33b0 adds r3, #176 @ 0xb0 + 80029f0: 2200 movs r2, #0 + 80029f2: f850 3023 ldr.w r3, [r0, r3, lsl #2] + 80029f6: f8ad 2006 strh.w r2, [sp, #6] + 80029fa: 2b00 cmp r3, #0 + 80029fc: d04a beq.n 8002a94 + 80029fe: 780a ldrb r2, [r1, #0] + 8002a00: f012 0260 ands.w r2, r2, #96 @ 0x60 + 8002a04: d01d beq.n 8002a42 + 8002a06: 2a20 cmp r2, #32 + 8002a08: d142 bne.n 8002a90 + 8002a0a: 784a ldrb r2, [r1, #1] + 8002a0c: 3a02 subs r2, #2 + 8002a0e: 2a09 cmp r2, #9 + 8002a10: d83e bhi.n 8002a90 + 8002a12: e8df f002 tbb [pc, r2] + 8002a16: 0a13 .short 0x0a13 + 8002a18: 3d3d3d3d .word 0x3d3d3d3d + 8002a1c: 050f3d3d .word 0x050f3d3d + 8002a20: 788a ldrb r2, [r1, #2] + 8002a22: 601a str r2, [r3, #0] + 8002a24: 2000 movs r0, #0 + 8002a26: b002 add sp, #8 + 8002a28: bd10 pop {r4, pc} + 8002a2a: 2201 movs r2, #1 + 8002a2c: 4619 mov r1, r3 + 8002a2e: f000 fcd8 bl 80033e2 + 8002a32: e7f7 b.n 8002a24 + 8002a34: 884a ldrh r2, [r1, #2] + 8002a36: 0a12 lsrs r2, r2, #8 + 8002a38: 605a str r2, [r3, #4] + 8002a3a: e7f3 b.n 8002a24 + 8002a3c: 2201 movs r2, #1 + 8002a3e: 1d19 adds r1, r3, #4 + 8002a40: e7f5 b.n 8002a2e + 8002a42: 784a ldrb r2, [r1, #1] + 8002a44: 2a0b cmp r2, #11 + 8002a46: d823 bhi.n 8002a90 + 8002a48: a401 add r4, pc, #4 @ (adr r4, 8002a50 ) + 8002a4a: f854 f022 ldr.w pc, [r4, r2, lsl #2] + 8002a4e: bf00 nop + 8002a50: 08002a81 .word 0x08002a81 + 8002a54: 08002a25 .word 0x08002a25 + 8002a58: 08002a91 .word 0x08002a91 + 8002a5c: 08002a91 .word 0x08002a91 + 8002a60: 08002a91 .word 0x08002a91 + 8002a64: 08002a91 .word 0x08002a91 + 8002a68: 08002a99 .word 0x08002a99 + 8002a6c: 08002a91 .word 0x08002a91 + 8002a70: 08002a91 .word 0x08002a91 + 8002a74: 08002a91 .word 0x08002a91 + 8002a78: 08002abd .word 0x08002abd + 8002a7c: 08002acd .word 0x08002acd + 8002a80: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 8002a84: 2b03 cmp r3, #3 + 8002a86: d103 bne.n 8002a90 + 8002a88: 2202 movs r2, #2 + 8002a8a: f10d 0106 add.w r1, sp, #6 + 8002a8e: e7ce b.n 8002a2e + 8002a90: f000 fc80 bl 8003394 + 8002a94: 2003 movs r0, #3 + 8002a96: e7c6 b.n 8002a26 + 8002a98: 884b ldrh r3, [r1, #2] + 8002a9a: 0a1b lsrs r3, r3, #8 + 8002a9c: 2b22 cmp r3, #34 @ 0x22 + 8002a9e: d105 bne.n 8002aac + 8002aa0: 88ca ldrh r2, [r1, #6] + 8002aa2: 490e ldr r1, [pc, #56] @ (8002adc ) + 8002aa4: 2a3f cmp r2, #63 @ 0x3f + 8002aa6: bf28 it cs + 8002aa8: 223f movcs r2, #63 @ 0x3f + 8002aaa: e7c0 b.n 8002a2e + 8002aac: 2b21 cmp r3, #33 @ 0x21 + 8002aae: d1ef bne.n 8002a90 + 8002ab0: 88ca ldrh r2, [r1, #6] + 8002ab2: 490b ldr r1, [pc, #44] @ (8002ae0 ) + 8002ab4: 2a09 cmp r2, #9 + 8002ab6: bf28 it cs + 8002ab8: 2209 movcs r2, #9 + 8002aba: e7b8 b.n 8002a2e + 8002abc: f890 229c ldrb.w r2, [r0, #668] @ 0x29c + 8002ac0: 2a03 cmp r2, #3 + 8002ac2: d1e5 bne.n 8002a90 + 8002ac4: 2201 movs r2, #1 + 8002ac6: f103 0108 add.w r1, r3, #8 + 8002aca: e7b0 b.n 8002a2e + 8002acc: f890 229c ldrb.w r2, [r0, #668] @ 0x29c + 8002ad0: 2a03 cmp r2, #3 + 8002ad2: d1dd bne.n 8002a90 + 8002ad4: 788a ldrb r2, [r1, #2] + 8002ad6: 609a str r2, [r3, #8] + 8002ad8: e7a4 b.n 8002a24 + 8002ada: bf00 nop + 8002adc: 2000000c .word 0x2000000c + 8002ae0: 20000058 .word 0x20000058 + +08002ae4 : + 8002ae4: b538 push {r3, r4, r5, lr} + 8002ae6: 4604 mov r4, r0 + 8002ae8: 2181 movs r1, #129 @ 0x81 + 8002aea: f000 fe89 bl 8003800 + 8002aee: f8d4 32d4 ldr.w r3, [r4, #724] @ 0x2d4 + 8002af2: 2500 movs r5, #0 + 8002af4: 33b0 adds r3, #176 @ 0xb0 + 8002af6: f884 5037 strb.w r5, [r4, #55] @ 0x37 + 8002afa: f854 0023 ldr.w r0, [r4, r3, lsl #2] + 8002afe: 6325 str r5, [r4, #48] @ 0x30 + 8002b00: b130 cbz r0, 8002b10 + 8002b02: f000 fe61 bl 80037c8 + 8002b06: f8d4 32d4 ldr.w r3, [r4, #724] @ 0x2d4 + 8002b0a: 33b0 adds r3, #176 @ 0xb0 + 8002b0c: f844 5023 str.w r5, [r4, r3, lsl #2] + 8002b10: 2000 movs r0, #0 + 8002b12: bd38 pop {r3, r4, r5, pc} + +08002b14 : + 8002b14: b538 push {r3, r4, r5, lr} + 8002b16: 4604 mov r4, r0 + 8002b18: 2010 movs r0, #16 + 8002b1a: f000 fe51 bl 80037c0 + 8002b1e: f8d4 32d4 ldr.w r3, [r4, #724] @ 0x2d4 + 8002b22: 33b0 adds r3, #176 @ 0xb0 + 8002b24: 4605 mov r5, r0 + 8002b26: f844 0023 str.w r0, [r4, r3, lsl #2] + 8002b2a: b908 cbnz r0, 8002b30 + 8002b2c: 2002 movs r0, #2 + 8002b2e: bd38 pop {r3, r4, r5, pc} + 8002b30: 7c23 ldrb r3, [r4, #16] + 8002b32: f8c4 02bc str.w r0, [r4, #700] @ 0x2bc + 8002b36: 2b00 cmp r3, #0 + 8002b38: bf14 ite ne + 8002b3a: 230a movne r3, #10 + 8002b3c: 2307 moveq r3, #7 + 8002b3e: 6323 str r3, [r4, #48] @ 0x30 + 8002b40: 2203 movs r2, #3 + 8002b42: 2304 movs r3, #4 + 8002b44: 2181 movs r1, #129 @ 0x81 + 8002b46: 4620 mov r0, r4 + 8002b48: f000 fe4e bl 80037e8 + 8002b4c: 2301 movs r3, #1 + 8002b4e: 2000 movs r0, #0 + 8002b50: f884 3037 strb.w r3, [r4, #55] @ 0x37 + 8002b54: 7328 strb r0, [r5, #12] + 8002b56: e7ea b.n 8002b2e + +08002b58 : + 8002b58: 4613 mov r3, r2 + 8002b5a: f8d0 22d4 ldr.w r2, [r0, #724] @ 0x2d4 + 8002b5e: 32b0 adds r2, #176 @ 0xb0 + 8002b60: b510 push {r4, lr} + 8002b62: f850 2022 ldr.w r2, [r0, r2, lsl #2] + 8002b66: b172 cbz r2, 8002b86 + 8002b68: f890 429c ldrb.w r4, [r0, #668] @ 0x29c + 8002b6c: 2c03 cmp r4, #3 + 8002b6e: d101 bne.n 8002b74 + 8002b70: 7b14 ldrb r4, [r2, #12] + 8002b72: b10c cbz r4, 8002b78 + 8002b74: 2000 movs r0, #0 + 8002b76: bd10 pop {r4, pc} + 8002b78: 2401 movs r4, #1 + 8002b7a: 7314 strb r4, [r2, #12] + 8002b7c: 460a mov r2, r1 + 8002b7e: 2181 movs r1, #129 @ 0x81 + 8002b80: f000 fe62 bl 8003848 + 8002b84: e7f6 b.n 8002b74 + 8002b86: 2003 movs r0, #3 + 8002b88: e7f5 b.n 8002b76 + +08002b8a : + 8002b8a: b178 cbz r0, 8002bac + 8002b8c: 2300 movs r3, #0 + 8002b8e: f8c0 32b8 str.w r3, [r0, #696] @ 0x2b8 + 8002b92: f8c0 32c4 str.w r3, [r0, #708] @ 0x2c4 + 8002b96: f8c0 32d0 str.w r3, [r0, #720] @ 0x2d0 + 8002b9a: b109 cbz r1, 8002ba0 + 8002b9c: f8c0 12b4 str.w r1, [r0, #692] @ 0x2b4 + 8002ba0: 2301 movs r3, #1 + 8002ba2: f880 329c strb.w r3, [r0, #668] @ 0x29c + 8002ba6: 7002 strb r2, [r0, #0] + 8002ba8: f000 bd98 b.w 80036dc + 8002bac: 2003 movs r0, #3 + 8002bae: 4770 bx lr + +08002bb0 : + 8002bb0: b513 push {r0, r1, r4, lr} + 8002bb2: 2300 movs r3, #0 + 8002bb4: 4604 mov r4, r0 + 8002bb6: f8ad 3006 strh.w r3, [sp, #6] + 8002bba: b181 cbz r1, 8002bde + 8002bbc: 6acb ldr r3, [r1, #44] @ 0x2c + 8002bbe: f8c0 12b8 str.w r1, [r0, #696] @ 0x2b8 + 8002bc2: b123 cbz r3, 8002bce + 8002bc4: f10d 0006 add.w r0, sp, #6 + 8002bc8: 4798 blx r3 + 8002bca: f8c4 02d0 str.w r0, [r4, #720] @ 0x2d0 + 8002bce: f8d4 32d8 ldr.w r3, [r4, #728] @ 0x2d8 + 8002bd2: 3301 adds r3, #1 + 8002bd4: f8c4 32d8 str.w r3, [r4, #728] @ 0x2d8 + 8002bd8: 2000 movs r0, #0 + 8002bda: b002 add sp, #8 + 8002bdc: bd10 pop {r4, pc} + 8002bde: 2003 movs r0, #3 + 8002be0: e7fb b.n 8002bda + +08002be2 : + 8002be2: f000 bdf8 b.w 80037d6 + +08002be6 : + 8002be6: f8d0 32b8 ldr.w r3, [r0, #696] @ 0x2b8 + 8002bea: b10b cbz r3, 8002bf0 + 8002bec: 681b ldr r3, [r3, #0] + 8002bee: 4718 bx r3 + 8002bf0: 4618 mov r0, r3 + 8002bf2: 4770 bx lr + +08002bf4 : + 8002bf4: b508 push {r3, lr} + 8002bf6: f8d0 32b8 ldr.w r3, [r0, #696] @ 0x2b8 + 8002bfa: 685b ldr r3, [r3, #4] + 8002bfc: 4798 blx r3 + 8002bfe: 2800 cmp r0, #0 + 8002c00: bf18 it ne + 8002c02: 2003 movne r0, #3 + 8002c04: bd08 pop {r3, pc} + +08002c06 : + 8002c06: b538 push {r3, r4, r5, lr} + 8002c08: 4604 mov r4, r0 + 8002c0a: f200 25aa addw r5, r0, #682 @ 0x2aa + 8002c0e: 4628 mov r0, r5 + 8002c10: f000 fbb5 bl 800337e + 8002c14: 2301 movs r3, #1 + 8002c16: f894 12aa ldrb.w r1, [r4, #682] @ 0x2aa + 8002c1a: f8c4 3294 str.w r3, [r4, #660] @ 0x294 + 8002c1e: f8b4 32b0 ldrh.w r3, [r4, #688] @ 0x2b0 + 8002c22: f8c4 3298 str.w r3, [r4, #664] @ 0x298 + 8002c26: f001 031f and.w r3, r1, #31 + 8002c2a: 2b01 cmp r3, #1 + 8002c2c: d008 beq.n 8002c40 + 8002c2e: 2b02 cmp r3, #2 + 8002c30: d00c beq.n 8002c4c + 8002c32: b98b cbnz r3, 8002c58 + 8002c34: 4629 mov r1, r5 + 8002c36: 4620 mov r0, r4 + 8002c38: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8002c3c: f000 b954 b.w 8002ee8 + 8002c40: 4629 mov r1, r5 + 8002c42: 4620 mov r0, r4 + 8002c44: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8002c48: f000 bac6 b.w 80031d8 + 8002c4c: 4629 mov r1, r5 + 8002c4e: 4620 mov r0, r4 + 8002c50: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8002c54: f000 baef b.w 8003236 + 8002c58: 4620 mov r0, r4 + 8002c5a: f001 0180 and.w r1, r1, #128 @ 0x80 + 8002c5e: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8002c62: f000 bdd6 b.w 8003812 + +08002c66 : + 8002c66: b570 push {r4, r5, r6, lr} + 8002c68: 4604 mov r4, r0 + 8002c6a: bb39 cbnz r1, 8002cbc + 8002c6c: f8d0 3294 ldr.w r3, [r0, #660] @ 0x294 + 8002c70: 2b03 cmp r3, #3 + 8002c72: d112 bne.n 8002c9a + 8002c74: f8d0 3158 ldr.w r3, [r0, #344] @ 0x158 + 8002c78: f8b0 2160 ldrh.w r2, [r0, #352] @ 0x160 + 8002c7c: 4293 cmp r3, r2 + 8002c7e: d90e bls.n 8002c9e + 8002c80: f8d0 1164 ldr.w r1, [r0, #356] @ 0x164 + 8002c84: 1a9b subs r3, r3, r2 + 8002c86: 4411 add r1, r2 + 8002c88: 429a cmp r2, r3 + 8002c8a: f8c0 3158 str.w r3, [r0, #344] @ 0x158 + 8002c8e: f8c0 1164 str.w r1, [r0, #356] @ 0x164 + 8002c92: bf38 it cc + 8002c94: 461a movcc r2, r3 + 8002c96: f000 fbba bl 800340e + 8002c9a: 2000 movs r0, #0 + 8002c9c: bd70 pop {r4, r5, r6, pc} + 8002c9e: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 8002ca2: 2b03 cmp r3, #3 + 8002ca4: d106 bne.n 8002cb4 + 8002ca6: f8d0 32b8 ldr.w r3, [r0, #696] @ 0x2b8 + 8002caa: 691b ldr r3, [r3, #16] + 8002cac: b113 cbz r3, 8002cb4 + 8002cae: f8c0 12d4 str.w r1, [r0, #724] @ 0x2d4 + 8002cb2: 4798 blx r3 + 8002cb4: 4620 mov r0, r4 + 8002cb6: f000 fbb2 bl 800341e + 8002cba: e7ee b.n 8002c9a + 8002cbc: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 8002cc0: 2b03 cmp r3, #3 + 8002cc2: d1ea bne.n 8002c9a + 8002cc4: f8d0 32b8 ldr.w r3, [r0, #696] @ 0x2b8 + 8002cc8: 699b ldr r3, [r3, #24] + 8002cca: 2b00 cmp r3, #0 + 8002ccc: d0e5 beq.n 8002c9a + 8002cce: 2200 movs r2, #0 + 8002cd0: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + 8002cd4: f8c0 22d4 str.w r2, [r0, #724] @ 0x2d4 + 8002cd8: 4718 bx r3 + +08002cda : + 8002cda: b570 push {r4, r5, r6, lr} + 8002cdc: 4604 mov r4, r0 + 8002cde: 460d mov r5, r1 + 8002ce0: 2900 cmp r1, #0 + 8002ce2: d13f bne.n 8002d64 + 8002ce4: f8d0 3294 ldr.w r3, [r0, #660] @ 0x294 + 8002ce8: 2b02 cmp r3, #2 + 8002cea: d110 bne.n 8002d0e + 8002cec: 6982 ldr r2, [r0, #24] + 8002cee: 8c03 ldrh r3, [r0, #32] + 8002cf0: 429a cmp r2, r3 + 8002cf2: d914 bls.n 8002d1e + 8002cf4: 6a41 ldr r1, [r0, #36] @ 0x24 + 8002cf6: 1ad2 subs r2, r2, r3 + 8002cf8: 4419 add r1, r3 + 8002cfa: 6182 str r2, [r0, #24] + 8002cfc: 6241 str r1, [r0, #36] @ 0x24 + 8002cfe: f000 fb7e bl 80033fe + 8002d02: 462b mov r3, r5 + 8002d04: 462a mov r2, r5 + 8002d06: 4629 mov r1, r5 + 8002d08: 4620 mov r0, r4 + 8002d0a: f000 fda6 bl 800385a + 8002d0e: f894 32a0 ldrb.w r3, [r4, #672] @ 0x2a0 + 8002d12: b113 cbz r3, 8002d1a + 8002d14: 2300 movs r3, #0 + 8002d16: f884 32a0 strb.w r3, [r4, #672] @ 0x2a0 + 8002d1a: 2000 movs r0, #0 + 8002d1c: bd70 pop {r4, r5, r6, pc} + 8002d1e: d10c bne.n 8002d3a + 8002d20: 6943 ldr r3, [r0, #20] + 8002d22: 429a cmp r2, r3 + 8002d24: d809 bhi.n 8002d3a + 8002d26: f8d0 2298 ldr.w r2, [r0, #664] @ 0x298 + 8002d2a: 4293 cmp r3, r2 + 8002d2c: d205 bcs.n 8002d3a + 8002d2e: 460a mov r2, r1 + 8002d30: f000 fb65 bl 80033fe + 8002d34: f8c4 5298 str.w r5, [r4, #664] @ 0x298 + 8002d38: e7e3 b.n 8002d02 + 8002d3a: f894 329c ldrb.w r3, [r4, #668] @ 0x29c + 8002d3e: 2b03 cmp r3, #3 + 8002d40: d108 bne.n 8002d54 + 8002d42: f8d4 32b8 ldr.w r3, [r4, #696] @ 0x2b8 + 8002d46: 68db ldr r3, [r3, #12] + 8002d48: b123 cbz r3, 8002d54 + 8002d4a: 2200 movs r2, #0 + 8002d4c: f8c4 22d4 str.w r2, [r4, #724] @ 0x2d4 + 8002d50: 4620 mov r0, r4 + 8002d52: 4798 blx r3 + 8002d54: 2180 movs r1, #128 @ 0x80 + 8002d56: 4620 mov r0, r4 + 8002d58: f000 fd5b bl 8003812 + 8002d5c: 4620 mov r0, r4 + 8002d5e: f000 fb69 bl 8003434 + 8002d62: e7d4 b.n 8002d0e + 8002d64: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 8002d68: 2b03 cmp r3, #3 + 8002d6a: d1d6 bne.n 8002d1a + 8002d6c: f8d0 32b8 ldr.w r3, [r0, #696] @ 0x2b8 + 8002d70: 695b ldr r3, [r3, #20] + 8002d72: 2b00 cmp r3, #0 + 8002d74: d0d1 beq.n 8002d1a + 8002d76: 2200 movs r2, #0 + 8002d78: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + 8002d7c: f8c0 22d4 str.w r2, [r0, #724] @ 0x2d4 + 8002d80: 4718 bx r3 + +08002d82 : + 8002d82: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002d84: 2301 movs r3, #1 + 8002d86: f880 329c strb.w r3, [r0, #668] @ 0x29c + 8002d8a: f8d0 32b8 ldr.w r3, [r0, #696] @ 0x2b8 + 8002d8e: 2100 movs r1, #0 + 8002d90: 4604 mov r4, r0 + 8002d92: f8c0 1294 str.w r1, [r0, #660] @ 0x294 + 8002d96: 6041 str r1, [r0, #4] + 8002d98: f8c0 12a4 str.w r1, [r0, #676] @ 0x2a4 + 8002d9c: f880 12a0 strb.w r1, [r0, #672] @ 0x2a0 + 8002da0: b9bb cbnz r3, 8002dd2 + 8002da2: 2600 movs r6, #0 + 8002da4: 2200 movs r2, #0 + 8002da6: 2540 movs r5, #64 @ 0x40 + 8002da8: 4611 mov r1, r2 + 8002daa: 2701 movs r7, #1 + 8002dac: 2340 movs r3, #64 @ 0x40 + 8002dae: 4620 mov r0, r4 + 8002db0: f000 fd1a bl 80037e8 + 8002db4: f884 7163 strb.w r7, [r4, #355] @ 0x163 + 8002db8: f8a4 5160 strh.w r5, [r4, #352] @ 0x160 + 8002dbc: 462b mov r3, r5 + 8002dbe: 2200 movs r2, #0 + 8002dc0: 2180 movs r1, #128 @ 0x80 + 8002dc2: 4620 mov r0, r4 + 8002dc4: f000 fd10 bl 80037e8 + 8002dc8: f884 7023 strb.w r7, [r4, #35] @ 0x23 + 8002dcc: 8425 strh r5, [r4, #32] + 8002dce: 4630 mov r0, r6 + 8002dd0: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8002dd2: 685b ldr r3, [r3, #4] + 8002dd4: 2b00 cmp r3, #0 + 8002dd6: d0e4 beq.n 8002da2 + 8002dd8: 4798 blx r3 + 8002dda: 2800 cmp r0, #0 + 8002ddc: d0e1 beq.n 8002da2 + 8002dde: 2603 movs r6, #3 + 8002de0: e7e0 b.n 8002da4 + +08002de2 : + 8002de2: 7401 strb r1, [r0, #16] + 8002de4: 2000 movs r0, #0 + 8002de6: 4770 bx lr + +08002de8 : + 8002de8: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 8002dec: 2b04 cmp r3, #4 + 8002dee: bf1e ittt ne + 8002df0: f890 329c ldrbne.w r3, [r0, #668] @ 0x29c + 8002df4: b2db uxtbne r3, r3 + 8002df6: f880 329d strbne.w r3, [r0, #669] @ 0x29d + 8002dfa: 2304 movs r3, #4 + 8002dfc: f880 329c strb.w r3, [r0, #668] @ 0x29c + 8002e00: 2000 movs r0, #0 + 8002e02: 4770 bx lr + +08002e04 : + 8002e04: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 8002e08: 2b04 cmp r3, #4 + 8002e0a: bf02 ittt eq + 8002e0c: f890 329d ldrbeq.w r3, [r0, #669] @ 0x29d + 8002e10: b2db uxtbeq r3, r3 + 8002e12: f880 329c strbeq.w r3, [r0, #668] @ 0x29c + 8002e16: 2000 movs r0, #0 + 8002e18: 4770 bx lr + +08002e1a : + 8002e1a: b508 push {r3, lr} + 8002e1c: f890 229c ldrb.w r2, [r0, #668] @ 0x29c + 8002e20: 2a03 cmp r2, #3 + 8002e22: d105 bne.n 8002e30 + 8002e24: f8d0 32b8 ldr.w r3, [r0, #696] @ 0x2b8 + 8002e28: b113 cbz r3, 8002e30 + 8002e2a: 69db ldr r3, [r3, #28] + 8002e2c: b103 cbz r3, 8002e30 + 8002e2e: 4798 blx r3 + 8002e30: 2000 movs r0, #0 + 8002e32: bd08 pop {r3, pc} + +08002e34 : + 8002e34: f8d0 22d4 ldr.w r2, [r0, #724] @ 0x2d4 + 8002e38: 32ae adds r2, #174 @ 0xae + 8002e3a: b508 push {r3, lr} + 8002e3c: f850 2022 ldr.w r2, [r0, r2, lsl #2] + 8002e40: b14a cbz r2, 8002e56 + 8002e42: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 8002e46: 2b03 cmp r3, #3 + 8002e48: d101 bne.n 8002e4e + 8002e4a: 6a13 ldr r3, [r2, #32] + 8002e4c: b90b cbnz r3, 8002e52 + 8002e4e: 2000 movs r0, #0 + 8002e50: bd08 pop {r3, pc} + 8002e52: 4798 blx r3 + 8002e54: e7fb b.n 8002e4e + 8002e56: 2003 movs r0, #3 + 8002e58: e7fa b.n 8002e50 + +08002e5a : + 8002e5a: f8d0 22d4 ldr.w r2, [r0, #724] @ 0x2d4 + 8002e5e: 32ae adds r2, #174 @ 0xae + 8002e60: b508 push {r3, lr} + 8002e62: f850 2022 ldr.w r2, [r0, r2, lsl #2] + 8002e66: b14a cbz r2, 8002e7c + 8002e68: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 8002e6c: 2b03 cmp r3, #3 + 8002e6e: d101 bne.n 8002e74 + 8002e70: 6a53 ldr r3, [r2, #36] @ 0x24 + 8002e72: b90b cbnz r3, 8002e78 + 8002e74: 2000 movs r0, #0 + 8002e76: bd08 pop {r3, pc} + 8002e78: 4798 blx r3 + 8002e7a: e7fb b.n 8002e74 + 8002e7c: 2003 movs r0, #3 + 8002e7e: e7fa b.n 8002e76 + +08002e80 : + 8002e80: 2000 movs r0, #0 + 8002e82: 4770 bx lr + +08002e84 : + 8002e84: 2201 movs r2, #1 + 8002e86: b508 push {r3, lr} + 8002e88: f880 229c strb.w r2, [r0, #668] @ 0x29c + 8002e8c: f8d0 22b8 ldr.w r2, [r0, #696] @ 0x2b8 + 8002e90: b90a cbnz r2, 8002e96 + 8002e92: 2000 movs r0, #0 + 8002e94: bd08 pop {r3, pc} + 8002e96: 6852 ldr r2, [r2, #4] + 8002e98: 7901 ldrb r1, [r0, #4] + 8002e9a: 4790 blx r2 + 8002e9c: 2800 cmp r0, #0 + 8002e9e: d0f8 beq.n 8002e92 + 8002ea0: 2003 movs r0, #3 + 8002ea2: e7f7 b.n 8002e94 + +08002ea4 : + 8002ea4: 2000 movs r0, #0 + 8002ea6: 4770 bx lr + +08002ea8 : + 8002ea8: 2000 movs r0, #0 + 8002eaa: 4770 bx lr + +08002eac : + 8002eac: b510 push {r4, lr} + 8002eae: 8842 ldrh r2, [r0, #2] + 8002eb0: 7803 ldrb r3, [r0, #0] + 8002eb2: 429a cmp r2, r3 + 8002eb4: d801 bhi.n 8002eba + 8002eb6: 2000 movs r0, #0 + 8002eb8: bd10 pop {r4, pc} + 8002eba: 7804 ldrb r4, [r0, #0] + 8002ebc: 4420 add r0, r4 + 8002ebe: 4423 add r3, r4 + 8002ec0: 7844 ldrb r4, [r0, #1] + 8002ec2: 2c05 cmp r4, #5 + 8002ec4: b29b uxth r3, r3 + 8002ec6: d1f4 bne.n 8002eb2 + 8002ec8: 7884 ldrb r4, [r0, #2] + 8002eca: 428c cmp r4, r1 + 8002ecc: d1f1 bne.n 8002eb2 + 8002ece: e7f3 b.n 8002eb8 + +08002ed0 : + 8002ed0: b510 push {r4, lr} + 8002ed2: 2180 movs r1, #128 @ 0x80 + 8002ed4: 4604 mov r4, r0 + 8002ed6: f000 fc9c bl 8003812 + 8002eda: 4620 mov r0, r4 + 8002edc: 2100 movs r1, #0 + 8002ede: e8bd 4010 ldmia.w sp!, {r4, lr} + 8002ee2: f000 bc96 b.w 8003812 + ... + +08002ee8 : + 8002ee8: b573 push {r0, r1, r4, r5, r6, lr} + 8002eea: 780b ldrb r3, [r1, #0] + 8002eec: f003 0360 and.w r3, r3, #96 @ 0x60 + 8002ef0: 2b20 cmp r3, #32 + 8002ef2: 4604 mov r4, r0 + 8002ef4: 460d mov r5, r1 + 8002ef6: d009 beq.n 8002f0c + 8002ef8: 2b40 cmp r3, #64 @ 0x40 + 8002efa: d007 beq.n 8002f0c + 8002efc: b193 cbz r3, 8002f24 + 8002efe: 4620 mov r0, r4 + 8002f00: f7ff ffe6 bl 8002ed0 + 8002f04: 2500 movs r5, #0 + 8002f06: 4628 mov r0, r5 + 8002f08: b002 add sp, #8 + 8002f0a: bd70 pop {r4, r5, r6, pc} + 8002f0c: f8d4 32d4 ldr.w r3, [r4, #724] @ 0x2d4 + 8002f10: 33ae adds r3, #174 @ 0xae + 8002f12: 4629 mov r1, r5 + 8002f14: f854 3023 ldr.w r3, [r4, r3, lsl #2] + 8002f18: 689b ldr r3, [r3, #8] + 8002f1a: 4620 mov r0, r4 + 8002f1c: b002 add sp, #8 + 8002f1e: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + 8002f22: 4718 bx r3 + 8002f24: 784b ldrb r3, [r1, #1] + 8002f26: 2b09 cmp r3, #9 + 8002f28: d8e9 bhi.n 8002efe + 8002f2a: a201 add r2, pc, #4 @ (adr r2, 8002f30 ) + 8002f2c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002f30: 08003179 .word 0x08003179 + 8002f34: 080031bd .word 0x080031bd + 8002f38: 08002eff .word 0x08002eff + 8002f3c: 080031a1 .word 0x080031a1 + 8002f40: 08002eff .word 0x08002eff + 8002f44: 08003073 .word 0x08003073 + 8002f48: 08002f59 .word 0x08002f59 + 8002f4c: 08002eff .word 0x08002eff + 8002f50: 0800314d .word 0x0800314d + 8002f54: 080030b5 .word 0x080030b5 + 8002f58: 2300 movs r3, #0 + 8002f5a: f8ad 3006 strh.w r3, [sp, #6] + 8002f5e: 884b ldrh r3, [r1, #2] + 8002f60: 0a1a lsrs r2, r3, #8 + 8002f62: 3a01 subs r2, #1 + 8002f64: 2a0e cmp r2, #14 + 8002f66: d8ca bhi.n 8002efe + 8002f68: a101 add r1, pc, #4 @ (adr r1, 8002f70 ) + 8002f6a: f851 f022 ldr.w pc, [r1, r2, lsl #2] + 8002f6e: bf00 nop + 8002f70: 08002fb7 .word 0x08002fb7 + 8002f74: 08002fe9 .word 0x08002fe9 + 8002f78: 08003003 .word 0x08003003 + 8002f7c: 08002eff .word 0x08002eff + 8002f80: 08002eff .word 0x08002eff + 8002f84: 08003045 .word 0x08003045 + 8002f88: 0800305b .word 0x0800305b + 8002f8c: 08002eff .word 0x08002eff + 8002f90: 08002eff .word 0x08002eff + 8002f94: 08002eff .word 0x08002eff + 8002f98: 08002eff .word 0x08002eff + 8002f9c: 08002eff .word 0x08002eff + 8002fa0: 08002eff .word 0x08002eff + 8002fa4: 08002eff .word 0x08002eff + 8002fa8: 08002fad .word 0x08002fad + 8002fac: f8d0 32b4 ldr.w r3, [r0, #692] @ 0x2b4 + 8002fb0: 69db ldr r3, [r3, #28] + 8002fb2: b91b cbnz r3, 8002fbc + 8002fb4: e7a3 b.n 8002efe + 8002fb6: f8d0 32b4 ldr.w r3, [r0, #692] @ 0x2b4 + 8002fba: 681b ldr r3, [r3, #0] + 8002fbc: 7c20 ldrb r0, [r4, #16] + 8002fbe: f10d 0106 add.w r1, sp, #6 + 8002fc2: 4798 blx r3 + 8002fc4: 88ea ldrh r2, [r5, #6] + 8002fc6: 2a00 cmp r2, #0 + 8002fc8: f000 80a3 beq.w 8003112 + 8002fcc: f8bd 3006 ldrh.w r3, [sp, #6] + 8002fd0: 2b00 cmp r3, #0 + 8002fd2: d094 beq.n 8002efe + 8002fd4: 429a cmp r2, r3 + 8002fd6: bf28 it cs + 8002fd8: 461a movcs r2, r3 + 8002fda: f8ad 2006 strh.w r2, [sp, #6] + 8002fde: 4601 mov r1, r0 + 8002fe0: 4620 mov r0, r4 + 8002fe2: f000 f9fe bl 80033e2 + 8002fe6: e78d b.n 8002f04 + 8002fe8: 7c02 ldrb r2, [r0, #16] + 8002fea: f8d0 32b8 ldr.w r3, [r0, #696] @ 0x2b8 + 8002fee: b932 cbnz r2, 8002ffe + 8002ff0: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002ff2: f10d 0006 add.w r0, sp, #6 + 8002ff6: 4798 blx r3 + 8002ff8: 2302 movs r3, #2 + 8002ffa: 7043 strb r3, [r0, #1] + 8002ffc: e7e2 b.n 8002fc4 + 8002ffe: 6adb ldr r3, [r3, #44] @ 0x2c + 8003000: e7f7 b.n 8002ff2 + 8003002: b2db uxtb r3, r3 + 8003004: 2b05 cmp r3, #5 + 8003006: f63f af7a bhi.w 8002efe + 800300a: e8df f003 tbb [pc, r3] + 800300e: 0703 .short 0x0703 + 8003010: 17130f0b .word 0x17130f0b + 8003014: f8d0 32b4 ldr.w r3, [r0, #692] @ 0x2b4 + 8003018: 685b ldr r3, [r3, #4] + 800301a: e7ca b.n 8002fb2 + 800301c: f8d0 32b4 ldr.w r3, [r0, #692] @ 0x2b4 + 8003020: 689b ldr r3, [r3, #8] + 8003022: e7c6 b.n 8002fb2 + 8003024: f8d0 32b4 ldr.w r3, [r0, #692] @ 0x2b4 + 8003028: 68db ldr r3, [r3, #12] + 800302a: e7c2 b.n 8002fb2 + 800302c: f8d0 32b4 ldr.w r3, [r0, #692] @ 0x2b4 + 8003030: 691b ldr r3, [r3, #16] + 8003032: e7be b.n 8002fb2 + 8003034: f8d0 32b4 ldr.w r3, [r0, #692] @ 0x2b4 + 8003038: 695b ldr r3, [r3, #20] + 800303a: e7ba b.n 8002fb2 + 800303c: f8d0 32b4 ldr.w r3, [r0, #692] @ 0x2b4 + 8003040: 699b ldr r3, [r3, #24] + 8003042: e7b6 b.n 8002fb2 + 8003044: 7c03 ldrb r3, [r0, #16] + 8003046: 2b00 cmp r3, #0 + 8003048: f47f af59 bne.w 8002efe + 800304c: f8d0 32b8 ldr.w r3, [r0, #696] @ 0x2b8 + 8003050: f10d 0006 add.w r0, sp, #6 + 8003054: 6b5b ldr r3, [r3, #52] @ 0x34 + 8003056: 4798 blx r3 + 8003058: e7b4 b.n 8002fc4 + 800305a: 7c03 ldrb r3, [r0, #16] + 800305c: 2b00 cmp r3, #0 + 800305e: f47f af4e bne.w 8002efe + 8003062: f8d0 32b8 ldr.w r3, [r0, #696] @ 0x2b8 + 8003066: f10d 0006 add.w r0, sp, #6 + 800306a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800306c: 4798 blx r3 + 800306e: 2307 movs r3, #7 + 8003070: e7c3 b.n 8002ffa + 8003072: 888b ldrh r3, [r1, #4] + 8003074: 2b00 cmp r3, #0 + 8003076: f47f af42 bne.w 8002efe + 800307a: 88cb ldrh r3, [r1, #6] + 800307c: 2b00 cmp r3, #0 + 800307e: f47f af3e bne.w 8002efe + 8003082: 884d ldrh r5, [r1, #2] + 8003084: 2d7f cmp r5, #127 @ 0x7f + 8003086: f63f af3a bhi.w 8002efe + 800308a: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 800308e: 2b03 cmp r3, #3 + 8003090: f43f af35 beq.w 8002efe + 8003094: b2ed uxtb r5, r5 + 8003096: f880 529e strb.w r5, [r0, #670] @ 0x29e + 800309a: 4629 mov r1, r5 + 800309c: f000 fbcb bl 8003836 + 80030a0: 4620 mov r0, r4 + 80030a2: f000 f9bc bl 800341e + 80030a6: b11d cbz r5, 80030b0 + 80030a8: 2302 movs r3, #2 + 80030aa: f884 329c strb.w r3, [r4, #668] @ 0x29c + 80030ae: e729 b.n 8002f04 + 80030b0: 2301 movs r3, #1 + 80030b2: e7fa b.n 80030aa + 80030b4: 7889 ldrb r1, [r1, #2] + 80030b6: 4d47 ldr r5, [pc, #284] @ (80031d4 ) + 80030b8: 2901 cmp r1, #1 + 80030ba: 7029 strb r1, [r5, #0] + 80030bc: d903 bls.n 80030c6 + 80030be: f7ff ff07 bl 8002ed0 + 80030c2: 2503 movs r5, #3 + 80030c4: e71f b.n 8002f06 + 80030c6: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 80030ca: 2b02 cmp r3, #2 + 80030cc: b2de uxtb r6, r3 + 80030ce: d008 beq.n 80030e2 + 80030d0: 2e03 cmp r6, #3 + 80030d2: d017 beq.n 8003104 + 80030d4: f7ff fefc bl 8002ed0 + 80030d8: 7829 ldrb r1, [r5, #0] + 80030da: 4620 mov r0, r4 + 80030dc: f7ff fd8a bl 8002bf4 + 80030e0: e7ef b.n 80030c2 + 80030e2: b1b1 cbz r1, 8003112 + 80030e4: 2101 movs r1, #1 + 80030e6: 6041 str r1, [r0, #4] + 80030e8: f7ff fd7d bl 8002be6 + 80030ec: 4605 mov r5, r0 + 80030ee: 4620 mov r0, r4 + 80030f0: b125 cbz r5, 80030fc + 80030f2: f7ff feed bl 8002ed0 + 80030f6: f884 629c strb.w r6, [r4, #668] @ 0x29c + 80030fa: e704 b.n 8002f06 + 80030fc: f000 f98f bl 800341e + 8003100: 2303 movs r3, #3 + 8003102: e7d2 b.n 80030aa + 8003104: b949 cbnz r1, 800311a + 8003106: 2302 movs r3, #2 + 8003108: f880 329c strb.w r3, [r0, #668] @ 0x29c + 800310c: 6041 str r1, [r0, #4] + 800310e: f7ff fd71 bl 8002bf4 + 8003112: 4620 mov r0, r4 + 8003114: f000 f983 bl 800341e + 8003118: e6f4 b.n 8002f04 + 800311a: 6841 ldr r1, [r0, #4] + 800311c: 2901 cmp r1, #1 + 800311e: d0f8 beq.n 8003112 + 8003120: b2c9 uxtb r1, r1 + 8003122: f7ff fd67 bl 8002bf4 + 8003126: 7829 ldrb r1, [r5, #0] + 8003128: 6061 str r1, [r4, #4] + 800312a: 4620 mov r0, r4 + 800312c: f7ff fd5b bl 8002be6 + 8003130: 4605 mov r5, r0 + 8003132: 2800 cmp r0, #0 + 8003134: d0ed beq.n 8003112 + 8003136: 4620 mov r0, r4 + 8003138: f7ff feca bl 8002ed0 + 800313c: 7921 ldrb r1, [r4, #4] + 800313e: 4620 mov r0, r4 + 8003140: f7ff fd58 bl 8002bf4 + 8003144: 2302 movs r3, #2 + 8003146: f884 329c strb.w r3, [r4, #668] @ 0x29c + 800314a: e6dc b.n 8002f06 + 800314c: 88ca ldrh r2, [r1, #6] + 800314e: 2a01 cmp r2, #1 + 8003150: f47f aed5 bne.w 8002efe + 8003154: f890 129c ldrb.w r1, [r0, #668] @ 0x29c + 8003158: 2902 cmp r1, #2 + 800315a: b2cb uxtb r3, r1 + 800315c: d807 bhi.n 800316e + 800315e: 2b00 cmp r3, #0 + 8003160: f43f aecd beq.w 8002efe + 8003164: 4601 mov r1, r0 + 8003166: 2300 movs r3, #0 + 8003168: f841 3f08 str.w r3, [r1, #8]! + 800316c: e738 b.n 8002fe0 + 800316e: 2b03 cmp r3, #3 + 8003170: f47f aec5 bne.w 8002efe + 8003174: 1d01 adds r1, r0, #4 + 8003176: e733 b.n 8002fe0 + 8003178: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 800317c: 3b01 subs r3, #1 + 800317e: 2b02 cmp r3, #2 + 8003180: f63f aebd bhi.w 8002efe + 8003184: 88ca ldrh r2, [r1, #6] + 8003186: 2a02 cmp r2, #2 + 8003188: f47f aeb9 bne.w 8002efe + 800318c: f8d0 32a4 ldr.w r3, [r0, #676] @ 0x2a4 + 8003190: 4601 mov r1, r0 + 8003192: 2b00 cmp r3, #0 + 8003194: bf0c ite eq + 8003196: 2301 moveq r3, #1 + 8003198: 2303 movne r3, #3 + 800319a: f841 3f0c str.w r3, [r1, #12]! + 800319e: e71f b.n 8002fe0 + 80031a0: 884b ldrh r3, [r1, #2] + 80031a2: 2b01 cmp r3, #1 + 80031a4: d102 bne.n 80031ac + 80031a6: f8c4 32a4 str.w r3, [r4, #676] @ 0x2a4 + 80031aa: e7b2 b.n 8003112 + 80031ac: 2b02 cmp r3, #2 + 80031ae: f47f aea6 bne.w 8002efe + 80031b2: 888b ldrh r3, [r1, #4] + 80031b4: 0a1b lsrs r3, r3, #8 + 80031b6: f880 32a0 strb.w r3, [r0, #672] @ 0x2a0 + 80031ba: e7aa b.n 8003112 + 80031bc: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 80031c0: 3b01 subs r3, #1 + 80031c2: 2b02 cmp r3, #2 + 80031c4: f63f ae9b bhi.w 8002efe + 80031c8: 884b ldrh r3, [r1, #2] + 80031ca: 2b01 cmp r3, #1 + 80031cc: f47f ae9a bne.w 8002f04 + 80031d0: 2300 movs r3, #0 + 80031d2: e7e8 b.n 80031a6 + 80031d4: 20000148 .word 0x20000148 + +080031d8 : + 80031d8: b570 push {r4, r5, r6, lr} + 80031da: 780b ldrb r3, [r1, #0] + 80031dc: f003 0260 and.w r2, r3, #96 @ 0x60 + 80031e0: 065b lsls r3, r3, #25 + 80031e2: 4604 mov r4, r0 + 80031e4: 460e mov r6, r1 + 80031e6: d501 bpl.n 80031ec + 80031e8: 2a40 cmp r2, #64 @ 0x40 + 80031ea: d11f bne.n 800322c + 80031ec: f894 329c ldrb.w r3, [r4, #668] @ 0x29c + 80031f0: 3b01 subs r3, #1 + 80031f2: 2b02 cmp r3, #2 + 80031f4: d81a bhi.n 800322c + 80031f6: 7931 ldrb r1, [r6, #4] + 80031f8: 2901 cmp r1, #1 + 80031fa: 4620 mov r0, r4 + 80031fc: d817 bhi.n 800322e + 80031fe: f7ff fe51 bl 8002ea4 + 8003202: b988 cbnz r0, 8003228 + 8003204: f8d4 32b8 ldr.w r3, [r4, #696] @ 0x2b8 + 8003208: 689b ldr r3, [r3, #8] + 800320a: b16b cbz r3, 8003228 + 800320c: f8c4 02d4 str.w r0, [r4, #724] @ 0x2d4 + 8003210: 4631 mov r1, r6 + 8003212: 4620 mov r0, r4 + 8003214: 4798 blx r3 + 8003216: 4605 mov r5, r0 + 8003218: 88f3 ldrh r3, [r6, #6] + 800321a: b91b cbnz r3, 8003224 + 800321c: b915 cbnz r5, 8003224 + 800321e: 4620 mov r0, r4 + 8003220: f000 f8fd bl 800341e + 8003224: 4628 mov r0, r5 + 8003226: bd70 pop {r4, r5, r6, pc} + 8003228: 2503 movs r5, #3 + 800322a: e7f5 b.n 8003218 + 800322c: 4620 mov r0, r4 + 800322e: f7ff fe4f bl 8002ed0 + 8003232: 2500 movs r5, #0 + 8003234: e7f6 b.n 8003224 + +08003236 : + 8003236: b570 push {r4, r5, r6, lr} + 8003238: 780b ldrb r3, [r1, #0] + 800323a: 888a ldrh r2, [r1, #4] + 800323c: 790d ldrb r5, [r1, #4] + 800323e: f003 0360 and.w r3, r3, #96 @ 0x60 + 8003242: 2b20 cmp r3, #32 + 8003244: 4604 mov r4, r0 + 8003246: 460e mov r6, r1 + 8003248: d059 beq.n 80032fe + 800324a: 2b40 cmp r3, #64 @ 0x40 + 800324c: d057 beq.n 80032fe + 800324e: b11b cbz r3, 8003258 + 8003250: 4620 mov r0, r4 + 8003252: f7ff fe3d bl 8002ed0 + 8003256: e03e b.n 80032d6 + 8003258: 784b ldrb r3, [r1, #1] + 800325a: 2b01 cmp r3, #1 + 800325c: d03d beq.n 80032da + 800325e: 2b03 cmp r3, #3 + 8003260: d026 beq.n 80032b0 + 8003262: 2b00 cmp r3, #0 + 8003264: d1f4 bne.n 8003250 + 8003266: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 800326a: 2b02 cmp r3, #2 + 800326c: b2d9 uxtb r1, r3 + 800326e: d062 beq.n 8003336 + 8003270: 2903 cmp r1, #3 + 8003272: d1ed bne.n 8003250 + 8003274: f005 030f and.w r3, r5, #15 + 8003278: f012 0f80 tst.w r2, #128 @ 0x80 + 800327c: f04f 0214 mov.w r2, #20 + 8003280: fb02 0303 mla r3, r2, r3, r0 + 8003284: d067 beq.n 8003356 + 8003286: f893 3023 ldrb.w r3, [r3, #35] @ 0x23 + 800328a: 2b00 cmp r3, #0 + 800328c: d0e0 beq.n 8003250 + 800328e: f005 067f and.w r6, r5, #127 @ 0x7f + 8003292: 3601 adds r6, #1 + 8003294: eb06 0686 add.w r6, r6, r6, lsl #2 + 8003298: 2d80 cmp r5, #128 @ 0x80 + 800329a: eb00 0686 add.w r6, r0, r6, lsl #2 + 800329e: d066 beq.n 800336e + 80032a0: 4629 mov r1, r5 + 80032a2: 4620 mov r0, r4 + 80032a4: f000 fa48 bl 8003738 + 80032a8: 2800 cmp r0, #0 + 80032aa: d066 beq.n 800337a + 80032ac: 2301 movs r3, #1 + 80032ae: e05f b.n 8003370 + 80032b0: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 80032b4: 2b02 cmp r3, #2 + 80032b6: b2da uxtb r2, r3 + 80032b8: d033 beq.n 8003322 + 80032ba: 2a03 cmp r2, #3 + 80032bc: d1c8 bne.n 8003250 + 80032be: 884b ldrh r3, [r1, #2] + 80032c0: b933 cbnz r3, 80032d0 + 80032c2: 0669 lsls r1, r5, #25 + 80032c4: d004 beq.n 80032d0 + 80032c6: 88f3 ldrh r3, [r6, #6] + 80032c8: b913 cbnz r3, 80032d0 + 80032ca: 4629 mov r1, r5 + 80032cc: f000 faa1 bl 8003812 + 80032d0: 4620 mov r0, r4 + 80032d2: f000 f8a4 bl 800341e + 80032d6: 2000 movs r0, #0 + 80032d8: bd70 pop {r4, r5, r6, pc} + 80032da: f890 329c ldrb.w r3, [r0, #668] @ 0x29c + 80032de: 2b02 cmp r3, #2 + 80032e0: b2da uxtb r2, r3 + 80032e2: d01e beq.n 8003322 + 80032e4: 2a03 cmp r2, #3 + 80032e6: d1b3 bne.n 8003250 + 80032e8: 884b ldrh r3, [r1, #2] + 80032ea: 2b00 cmp r3, #0 + 80032ec: d1f3 bne.n 80032d6 + 80032ee: 066b lsls r3, r5, #25 + 80032f0: d002 beq.n 80032f8 + 80032f2: 4629 mov r1, r5 + 80032f4: f000 fa96 bl 8003824 + 80032f8: 4620 mov r0, r4 + 80032fa: f000 f890 bl 800341e + 80032fe: 4629 mov r1, r5 + 8003300: 4620 mov r0, r4 + 8003302: f7ff fdd1 bl 8002ea8 + 8003306: 2800 cmp r0, #0 + 8003308: d1e5 bne.n 80032d6 + 800330a: f8d4 32b8 ldr.w r3, [r4, #696] @ 0x2b8 + 800330e: f8c4 02d4 str.w r0, [r4, #724] @ 0x2d4 + 8003312: 689b ldr r3, [r3, #8] + 8003314: 2b00 cmp r3, #0 + 8003316: d0de beq.n 80032d6 + 8003318: 4631 mov r1, r6 + 800331a: 4620 mov r0, r4 + 800331c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + 8003320: 4718 bx r3 + 8003322: 066a lsls r2, r5, #25 + 8003324: d094 beq.n 8003250 + 8003326: 4629 mov r1, r5 + 8003328: f000 fa73 bl 8003812 + 800332c: 2180 movs r1, #128 @ 0x80 + 800332e: 4620 mov r0, r4 + 8003330: f000 fa6f bl 8003812 + 8003334: e7cf b.n 80032d6 + 8003336: 0669 lsls r1, r5, #25 + 8003338: d18a bne.n 8003250 + 800333a: 0613 lsls r3, r2, #24 + 800333c: bf4c ite mi + 800333e: f100 0114 addmi.w r1, r0, #20 + 8003342: f500 71aa addpl.w r1, r0, #340 @ 0x154 + 8003346: 2300 movs r3, #0 + 8003348: f801 3f0e strb.w r3, [r1, #14]! + 800334c: 2202 movs r2, #2 + 800334e: 4620 mov r0, r4 + 8003350: f000 f847 bl 80033e2 + 8003354: e7bf b.n 80032d6 + 8003356: f893 3163 ldrb.w r3, [r3, #355] @ 0x163 + 800335a: 2b00 cmp r3, #0 + 800335c: f43f af78 beq.w 8003250 + 8003360: 2614 movs r6, #20 + 8003362: fb06 0605 mla r6, r6, r5, r0 + 8003366: f506 76aa add.w r6, r6, #340 @ 0x154 + 800336a: 2d00 cmp r5, #0 + 800336c: d198 bne.n 80032a0 + 800336e: 2300 movs r3, #0 + 8003370: 73b3 strb r3, [r6, #14] + 8003372: 2202 movs r2, #2 + 8003374: f106 010e add.w r1, r6, #14 + 8003378: e7e9 b.n 800334e + 800337a: 73b0 strb r0, [r6, #14] + 800337c: e7f9 b.n 8003372 + +0800337e : + 800337e: 780b ldrb r3, [r1, #0] + 8003380: 7003 strb r3, [r0, #0] + 8003382: 784b ldrb r3, [r1, #1] + 8003384: 7043 strb r3, [r0, #1] + 8003386: 884b ldrh r3, [r1, #2] + 8003388: 8043 strh r3, [r0, #2] + 800338a: 888b ldrh r3, [r1, #4] + 800338c: 8083 strh r3, [r0, #4] + 800338e: 88cb ldrh r3, [r1, #6] + 8003390: 80c3 strh r3, [r0, #6] + 8003392: 4770 bx lr + +08003394 : + 8003394: b510 push {r4, lr} + 8003396: 2180 movs r1, #128 @ 0x80 + 8003398: 4604 mov r4, r0 + 800339a: f000 fa3a bl 8003812 + 800339e: 4620 mov r0, r4 + 80033a0: 2100 movs r1, #0 + 80033a2: e8bd 4010 ldmia.w sp!, {r4, lr} + 80033a6: f000 ba34 b.w 8003812 + +080033aa : + 80033aa: b570 push {r4, r5, r6, lr} + 80033ac: 460d mov r5, r1 + 80033ae: 4616 mov r6, r2 + 80033b0: 4604 mov r4, r0 + 80033b2: b170 cbz r0, 80033d2 + 80033b4: f7fc ff26 bl 8000204 + 80033b8: b2c3 uxtb r3, r0 + 80033ba: 3301 adds r3, #1 + 80033bc: 005b lsls r3, r3, #1 + 80033be: 8033 strh r3, [r6, #0] + 80033c0: 702b strb r3, [r5, #0] + 80033c2: 2303 movs r3, #3 + 80033c4: 706b strb r3, [r5, #1] + 80033c6: 3c01 subs r4, #1 + 80033c8: 2302 movs r3, #2 + 80033ca: 2100 movs r1, #0 + 80033cc: f814 2f01 ldrb.w r2, [r4, #1]! + 80033d0: b902 cbnz r2, 80033d4 + 80033d2: bd70 pop {r4, r5, r6, pc} + 80033d4: 54ea strb r2, [r5, r3] + 80033d6: 1c5a adds r2, r3, #1 + 80033d8: b2d2 uxtb r2, r2 + 80033da: 3302 adds r3, #2 + 80033dc: 54a9 strb r1, [r5, r2] + 80033de: b2db uxtb r3, r3 + 80033e0: e7f4 b.n 80033cc + +080033e2 : + 80033e2: b510 push {r4, lr} + 80033e4: 4613 mov r3, r2 + 80033e6: 2202 movs r2, #2 + 80033e8: f8c0 2294 str.w r2, [r0, #660] @ 0x294 + 80033ec: 6143 str r3, [r0, #20] + 80033ee: 460a mov r2, r1 + 80033f0: 6241 str r1, [r0, #36] @ 0x24 + 80033f2: 6183 str r3, [r0, #24] + 80033f4: 2100 movs r1, #0 + 80033f6: f000 fa27 bl 8003848 + 80033fa: 2000 movs r0, #0 + 80033fc: bd10 pop {r4, pc} + +080033fe : + 80033fe: b508 push {r3, lr} + 8003400: 4613 mov r3, r2 + 8003402: 460a mov r2, r1 + 8003404: 2100 movs r1, #0 + 8003406: f000 fa1f bl 8003848 + 800340a: 2000 movs r0, #0 + 800340c: bd08 pop {r3, pc} + +0800340e : + 800340e: b508 push {r3, lr} + 8003410: 4613 mov r3, r2 + 8003412: 460a mov r2, r1 + 8003414: 2100 movs r1, #0 + 8003416: f000 fa20 bl 800385a + 800341a: 2000 movs r0, #0 + 800341c: bd08 pop {r3, pc} + +0800341e : + 800341e: b508 push {r3, lr} + 8003420: 2204 movs r2, #4 + 8003422: 2300 movs r3, #0 + 8003424: f8c0 2294 str.w r2, [r0, #660] @ 0x294 + 8003428: 4619 mov r1, r3 + 800342a: 461a mov r2, r3 + 800342c: f000 fa0c bl 8003848 + 8003430: 2000 movs r0, #0 + 8003432: bd08 pop {r3, pc} + +08003434 : + 8003434: b508 push {r3, lr} + 8003436: 2205 movs r2, #5 + 8003438: 2300 movs r3, #0 + 800343a: f8c0 2294 str.w r2, [r0, #660] @ 0x294 + 800343e: 4619 mov r1, r3 + 8003440: 461a mov r2, r3 + 8003442: f000 fa0a bl 800385a + 8003446: 2000 movs r0, #0 + 8003448: bd08 pop {r3, pc} + ... + +0800344c : + 800344c: b508 push {r3, lr} + 800344e: 490c ldr r1, [pc, #48] @ (8003480 ) + 8003450: 480c ldr r0, [pc, #48] @ (8003484 ) + 8003452: 2200 movs r2, #0 + 8003454: f7ff fb99 bl 8002b8a + 8003458: b108 cbz r0, 800345e + 800345a: f7fd f959 bl 8000710 + 800345e: 490a ldr r1, [pc, #40] @ (8003488 ) + 8003460: 4808 ldr r0, [pc, #32] @ (8003484 ) + 8003462: f7ff fba5 bl 8002bb0 + 8003466: b108 cbz r0, 800346c + 8003468: f7fd f952 bl 8000710 + 800346c: 4805 ldr r0, [pc, #20] @ (8003484 ) + 800346e: f7ff fbb8 bl 8002be2 + 8003472: b118 cbz r0, 800347c + 8003474: e8bd 4008 ldmia.w sp!, {r3, lr} + 8003478: f7fd b94a b.w 8000710 + 800347c: bd08 pop {r3, pc} + 800347e: bf00 nop + 8003480: 20000100 .word 0x20000100 + 8003484: 2000014c .word 0x2000014c + 8003488: 20000088 .word 0x20000088 + +0800348c : + 800348c: 2312 movs r3, #18 + 800348e: 4801 ldr r0, [pc, #4] @ (8003494 ) + 8003490: 800b strh r3, [r1, #0] + 8003492: 4770 bx lr + 8003494: 200000ec .word 0x200000ec + +08003498 : + 8003498: 2304 movs r3, #4 + 800349a: 4801 ldr r0, [pc, #4] @ (80034a0 ) + 800349c: 800b strh r3, [r1, #0] + 800349e: 4770 bx lr + 80034a0: 200000dc .word 0x200000dc + +080034a4 : + 80034a4: 230c movs r3, #12 + 80034a6: 4801 ldr r0, [pc, #4] @ (80034ac ) + 80034a8: 800b strh r3, [r1, #0] + 80034aa: 4770 bx lr + 80034ac: 200000e0 .word 0x200000e0 + +080034b0 : + 80034b0: 2300 movs r3, #0 + 80034b2: b570 push {r4, r5, r6, lr} + 80034b4: 1c4d adds r5, r1, #1 + 80034b6: 461e mov r6, r3 + 80034b8: 0f04 lsrs r4, r0, #28 + 80034ba: f1b0 4f20 cmp.w r0, #2684354560 @ 0xa0000000 + 80034be: bf34 ite cc + 80034c0: 3430 addcc r4, #48 @ 0x30 + 80034c2: 3437 addcs r4, #55 @ 0x37 + 80034c4: f801 4013 strb.w r4, [r1, r3, lsl #1] + 80034c8: f805 6013 strb.w r6, [r5, r3, lsl #1] + 80034cc: 3301 adds r3, #1 + 80034ce: b2dc uxtb r4, r3 + 80034d0: 42a2 cmp r2, r4 + 80034d2: ea4f 1000 mov.w r0, r0, lsl #4 + 80034d6: d8ef bhi.n 80034b8 + 80034d8: bd70 pop {r4, r5, r6, pc} + ... + +080034dc : + 80034dc: 231a movs r3, #26 + 80034de: b510 push {r4, lr} + 80034e0: 800b strh r3, [r1, #0] + 80034e2: 4b0a ldr r3, [pc, #40] @ (800350c ) + 80034e4: f8d3 0a10 ldr.w r0, [r3, #2576] @ 0xa10 + 80034e8: f8d3 2a18 ldr.w r2, [r3, #2584] @ 0xa18 + 80034ec: 1880 adds r0, r0, r2 + 80034ee: d00a beq.n 8003506 + 80034f0: f8d3 4a14 ldr.w r4, [r3, #2580] @ 0xa14 + 80034f4: 4906 ldr r1, [pc, #24] @ (8003510 ) + 80034f6: 2208 movs r2, #8 + 80034f8: f7ff ffda bl 80034b0 + 80034fc: 2204 movs r2, #4 + 80034fe: 3110 adds r1, #16 + 8003500: 4620 mov r0, r4 + 8003502: f7ff ffd5 bl 80034b0 + 8003506: 4803 ldr r0, [pc, #12] @ (8003514 ) + 8003508: bd10 pop {r4, pc} + 800350a: bf00 nop + 800350c: 1fff7000 .word 0x1fff7000 + 8003510: 200000c2 .word 0x200000c2 + 8003514: 200000c0 .word 0x200000c0 + +08003518 : + 8003518: b510 push {r4, lr} + 800351a: 4c04 ldr r4, [pc, #16] @ (800352c ) + 800351c: 4804 ldr r0, [pc, #16] @ (8003530 ) + 800351e: 460a mov r2, r1 + 8003520: 4621 mov r1, r4 + 8003522: f7ff ff42 bl 80033aa + 8003526: 4620 mov r0, r4 + 8003528: bd10 pop {r4, pc} + 800352a: bf00 nop + 800352c: 20000428 .word 0x20000428 + 8003530: 080038ec .word 0x080038ec + +08003534 : + 8003534: b510 push {r4, lr} + 8003536: 4c04 ldr r4, [pc, #16] @ (8003548 ) + 8003538: 4804 ldr r0, [pc, #16] @ (800354c ) + 800353a: 460a mov r2, r1 + 800353c: 4621 mov r1, r4 + 800353e: f7ff ff34 bl 80033aa + 8003542: 4620 mov r0, r4 + 8003544: bd10 pop {r4, pc} + 8003546: bf00 nop + 8003548: 20000428 .word 0x20000428 + 800354c: 080038f6 .word 0x080038f6 + +08003550 : + 8003550: b510 push {r4, lr} + 8003552: 4c04 ldr r4, [pc, #16] @ (8003564 ) + 8003554: 4804 ldr r0, [pc, #16] @ (8003568 ) + 8003556: 460a mov r2, r1 + 8003558: 4621 mov r1, r4 + 800355a: f7ff ff26 bl 80033aa + 800355e: 4620 mov r0, r4 + 8003560: bd10 pop {r4, pc} + 8003562: bf00 nop + 8003564: 20000428 .word 0x20000428 + 8003568: 08003907 .word 0x08003907 + +0800356c : + 800356c: b510 push {r4, lr} + 800356e: 4c04 ldr r4, [pc, #16] @ (8003580 ) + 8003570: 4804 ldr r0, [pc, #16] @ (8003584 ) + 8003572: 460a mov r2, r1 + 8003574: 4621 mov r1, r4 + 8003576: f7ff ff18 bl 80033aa + 800357a: 4620 mov r0, r4 + 800357c: bd10 pop {r4, pc} + 800357e: bf00 nop + 8003580: 20000428 .word 0x20000428 + 8003584: 08003912 .word 0x08003912 + +08003588 : + 8003588: b530 push {r4, r5, lr} + 800358a: b09f sub sp, #124 @ 0x7c + 800358c: 4604 mov r4, r0 + 800358e: 2214 movs r2, #20 + 8003590: 2100 movs r1, #0 + 8003592: a802 add r0, sp, #8 + 8003594: f000 f96a bl 800386c + 8003598: 225c movs r2, #92 @ 0x5c + 800359a: 2100 movs r1, #0 + 800359c: a807 add r0, sp, #28 + 800359e: f000 f965 bl 800386c + 80035a2: 6823 ldr r3, [r4, #0] + 80035a4: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 80035a8: d138 bne.n 800361c + 80035aa: f44f 7380 mov.w r3, #256 @ 0x100 + 80035ae: a807 add r0, sp, #28 + 80035b0: 9307 str r3, [sp, #28] + 80035b2: f7fe f8af bl 8001714 + 80035b6: b108 cbz r0, 80035bc + 80035b8: f7fd f8aa bl 8000710 + 80035bc: 4c18 ldr r4, [pc, #96] @ (8003620 ) + 80035be: 4819 ldr r0, [pc, #100] @ (8003624 ) + 80035c0: 2500 movs r5, #0 + 80035c2: 9500 str r5, [sp, #0] + 80035c4: 6b23 ldr r3, [r4, #48] @ 0x30 + 80035c6: f043 0301 orr.w r3, r3, #1 + 80035ca: 6323 str r3, [r4, #48] @ 0x30 + 80035cc: 6b23 ldr r3, [r4, #48] @ 0x30 + 80035ce: 9504 str r5, [sp, #16] + 80035d0: f003 0301 and.w r3, r3, #1 + 80035d4: 9300 str r3, [sp, #0] + 80035d6: f44f 52c0 mov.w r2, #6144 @ 0x1800 + 80035da: 9b00 ldr r3, [sp, #0] + 80035dc: 2302 movs r3, #2 + 80035de: e9cd 2302 strd r2, r3, [sp, #8] + 80035e2: 2103 movs r1, #3 + 80035e4: 230a movs r3, #10 + 80035e6: e9cd 1305 strd r1, r3, [sp, #20] + 80035ea: a902 add r1, sp, #8 + 80035ec: f7fd f9bc bl 8000968 + 80035f0: 6b63 ldr r3, [r4, #52] @ 0x34 + 80035f2: f043 0380 orr.w r3, r3, #128 @ 0x80 + 80035f6: 6363 str r3, [r4, #52] @ 0x34 + 80035f8: 9501 str r5, [sp, #4] + 80035fa: 6c63 ldr r3, [r4, #68] @ 0x44 + 80035fc: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 8003600: 6463 str r3, [r4, #68] @ 0x44 + 8003602: 6c63 ldr r3, [r4, #68] @ 0x44 + 8003604: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8003608: 9301 str r3, [sp, #4] + 800360a: 2043 movs r0, #67 @ 0x43 + 800360c: 462a mov r2, r5 + 800360e: 4629 mov r1, r5 + 8003610: 9b01 ldr r3, [sp, #4] + 8003612: f7fd f955 bl 80008c0 + 8003616: 2043 movs r0, #67 @ 0x43 + 8003618: f7fd f984 bl 8000924 + 800361c: b01f add sp, #124 @ 0x7c + 800361e: bd30 pop {r4, r5, pc} + 8003620: 40023800 .word 0x40023800 + 8003624: 40020000 .word 0x40020000 + +08003628 : + 8003628: f200 419c addw r1, r0, #1180 @ 0x49c + 800362c: f8d0 04e0 ldr.w r0, [r0, #1248] @ 0x4e0 + 8003630: f7ff bae9 b.w 8002c06 + +08003634 : + 8003634: 2324 movs r3, #36 @ 0x24 + 8003636: fb03 0301 mla r3, r3, r1, r0 + 800363a: f8d0 04e0 ldr.w r0, [r0, #1248] @ 0x4e0 + 800363e: f8d3 2260 ldr.w r2, [r3, #608] @ 0x260 + 8003642: f7ff bb10 b.w 8002c66 + +08003646 : + 8003646: 2324 movs r3, #36 @ 0x24 + 8003648: fb03 0301 mla r3, r3, r1, r0 + 800364c: f8d0 04e0 ldr.w r0, [r0, #1248] @ 0x4e0 + 8003650: 6a1a ldr r2, [r3, #32] + 8003652: f7ff bb42 b.w 8002cda + +08003656 : + 8003656: f8d0 04e0 ldr.w r0, [r0, #1248] @ 0x4e0 + 800365a: f7ff bbde b.w 8002e1a + +0800365e : + 800365e: b510 push {r4, lr} + 8003660: 79c1 ldrb r1, [r0, #7] + 8003662: 4604 mov r4, r0 + 8003664: b121 cbz r1, 8003670 + 8003666: 2902 cmp r1, #2 + 8003668: d001 beq.n 800366e + 800366a: f7fd f851 bl 8000710 + 800366e: 2101 movs r1, #1 + 8003670: f8d4 04e0 ldr.w r0, [r4, #1248] @ 0x4e0 + 8003674: f7ff fbb5 bl 8002de2 + 8003678: f8d4 04e0 ldr.w r0, [r4, #1248] @ 0x4e0 + 800367c: e8bd 4010 ldmia.w sp!, {r4, lr} + 8003680: f7ff bb7f b.w 8002d82 + +08003684 : + 8003684: b510 push {r4, lr} + 8003686: 4604 mov r4, r0 + 8003688: f8d0 04e0 ldr.w r0, [r0, #1248] @ 0x4e0 + 800368c: f7ff fbac bl 8002de8 + 8003690: 6822 ldr r2, [r4, #0] + 8003692: f8d2 3e00 ldr.w r3, [r2, #3584] @ 0xe00 + 8003696: f043 0301 orr.w r3, r3, #1 + 800369a: f8c2 3e00 str.w r3, [r2, #3584] @ 0xe00 + 800369e: 7ae3 ldrb r3, [r4, #11] + 80036a0: b123 cbz r3, 80036ac + 80036a2: 4a03 ldr r2, [pc, #12] @ (80036b0 ) + 80036a4: 6913 ldr r3, [r2, #16] + 80036a6: f043 0306 orr.w r3, r3, #6 + 80036aa: 6113 str r3, [r2, #16] + 80036ac: bd10 pop {r4, pc} + 80036ae: bf00 nop + 80036b0: e000ed00 .word 0xe000ed00 + +080036b4 : + 80036b4: f8d0 04e0 ldr.w r0, [r0, #1248] @ 0x4e0 + 80036b8: f7ff bba4 b.w 8002e04 + +080036bc : + 80036bc: f8d0 04e0 ldr.w r0, [r0, #1248] @ 0x4e0 + 80036c0: f7ff bbcb b.w 8002e5a + +080036c4 : + 80036c4: f8d0 04e0 ldr.w r0, [r0, #1248] @ 0x4e0 + 80036c8: f7ff bbb4 b.w 8002e34 + +080036cc : + 80036cc: f8d0 04e0 ldr.w r0, [r0, #1248] @ 0x4e0 + 80036d0: f7ff bbd6 b.w 8002e80 + +080036d4 : + 80036d4: f8d0 04e0 ldr.w r0, [r0, #1248] @ 0x4e0 + 80036d8: f7ff bbd4 b.w 8002e84 + +080036dc : + 80036dc: b508 push {r3, lr} + 80036de: 7802 ldrb r2, [r0, #0] + 80036e0: 4603 mov r3, r0 + 80036e2: bb22 cbnz r2, 800372e + 80036e4: 4813 ldr r0, [pc, #76] @ (8003734 ) + 80036e6: f8c0 34e0 str.w r3, [r0, #1248] @ 0x4e0 + 80036ea: f8c3 02c8 str.w r0, [r3, #712] @ 0x2c8 + 80036ee: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 80036f2: 6003 str r3, [r0, #0] + 80036f4: 2306 movs r3, #6 + 80036f6: 7103 strb r3, [r0, #4] + 80036f8: f44f 7300 mov.w r3, #512 @ 0x200 + 80036fc: 80c3 strh r3, [r0, #6] + 80036fe: 2302 movs r3, #2 + 8003700: 7243 strb r3, [r0, #9] + 8003702: 8142 strh r2, [r0, #10] + 8003704: 7302 strb r2, [r0, #12] + 8003706: 81c2 strh r2, [r0, #14] + 8003708: f7fd fa05 bl 8000b16 + 800370c: b108 cbz r0, 8003712 + 800370e: f7fc ffff bl 8000710 + 8003712: 2180 movs r1, #128 @ 0x80 + 8003714: 4807 ldr r0, [pc, #28] @ (8003734 ) + 8003716: f7fd ff46 bl 80015a6 + 800371a: 2240 movs r2, #64 @ 0x40 + 800371c: 2100 movs r1, #0 + 800371e: 4805 ldr r0, [pc, #20] @ (8003734 ) + 8003720: f7fd ff22 bl 8001568 + 8003724: 4803 ldr r0, [pc, #12] @ (8003734 ) + 8003726: 2280 movs r2, #128 @ 0x80 + 8003728: 2101 movs r1, #1 + 800372a: f7fd ff1d bl 8001568 + 800372e: 2000 movs r0, #0 + 8003730: bd08 pop {r3, pc} + 8003732: bf00 nop + 8003734: 2000063c .word 0x2000063c + +08003738 : + 8003738: f011 0f80 tst.w r1, #128 @ 0x80 + 800373c: f8d0 32c8 ldr.w r3, [r0, #712] @ 0x2c8 + 8003740: f04f 0224 mov.w r2, #36 @ 0x24 + 8003744: bf1b ittet ne + 8003746: f001 017f andne.w r1, r1, #127 @ 0x7f + 800374a: fb02 3301 mlane r3, r2, r1, r3 + 800374e: fb02 3301 mlaeq r3, r2, r1, r3 + 8003752: 7d98 ldrbne r0, [r3, #22] + 8003754: bf08 it eq + 8003756: f893 0256 ldrbeq.w r0, [r3, #598] @ 0x256 + 800375a: 4770 bx lr + +0800375c : + 800375c: b510 push {r4, lr} + 800375e: 4604 mov r4, r0 + 8003760: b111 cbz r1, 8003768 + 8003762: 2901 cmp r1, #1 + 8003764: d016 beq.n 8003794 + 8003766: bd10 pop {r4, pc} + 8003768: 7ac3 ldrb r3, [r0, #11] + 800376a: b133 cbz r3, 800377a + 800376c: f7fc fee8 bl 8000540 + 8003770: 4a12 ldr r2, [pc, #72] @ (80037bc ) + 8003772: 6913 ldr r3, [r2, #16] + 8003774: f023 0306 bic.w r3, r3, #6 + 8003778: 6113 str r3, [r2, #16] + 800377a: 6822 ldr r2, [r4, #0] + 800377c: f8d4 04e0 ldr.w r0, [r4, #1248] @ 0x4e0 + 8003780: f8d2 3e00 ldr.w r3, [r2, #3584] @ 0xe00 + 8003784: f023 0301 bic.w r3, r3, #1 + 8003788: e8bd 4010 ldmia.w sp!, {r4, lr} + 800378c: f8c2 3e00 str.w r3, [r2, #3584] @ 0xe00 + 8003790: f7ff bb38 b.w 8002e04 + 8003794: 6802 ldr r2, [r0, #0] + 8003796: f8d0 04e0 ldr.w r0, [r0, #1248] @ 0x4e0 + 800379a: f8d2 3e00 ldr.w r3, [r2, #3584] @ 0xe00 + 800379e: f043 0301 orr.w r3, r3, #1 + 80037a2: f8c2 3e00 str.w r3, [r2, #3584] @ 0xe00 + 80037a6: f7ff fb1f bl 8002de8 + 80037aa: 7ae3 ldrb r3, [r4, #11] + 80037ac: 2b00 cmp r3, #0 + 80037ae: d0da beq.n 8003766 + 80037b0: 4a02 ldr r2, [pc, #8] @ (80037bc ) + 80037b2: 6913 ldr r3, [r2, #16] + 80037b4: f043 0306 orr.w r3, r3, #6 + 80037b8: 6113 str r3, [r2, #16] + 80037ba: e7d4 b.n 8003766 + 80037bc: e000ed00 .word 0xe000ed00 + +080037c0 : + 80037c0: 4800 ldr r0, [pc, #0] @ (80037c4 ) + 80037c2: 4770 bx lr + 80037c4: 20000628 .word 0x20000628 + +080037c8 : + 80037c8: 4770 bx lr + +080037ca : + 80037ca: b118 cbz r0, 80037d4 + 80037cc: 2802 cmp r0, #2 + 80037ce: bf0c ite eq + 80037d0: 2001 moveq r0, #1 + 80037d2: 2003 movne r0, #3 + 80037d4: 4770 bx lr + +080037d6 : + 80037d6: b508 push {r3, lr} + 80037d8: f8d0 02c8 ldr.w r0, [r0, #712] @ 0x2c8 + 80037dc: f7fd fa10 bl 8000c00 + 80037e0: e8bd 4008 ldmia.w sp!, {r3, lr} + 80037e4: f7ff bff1 b.w 80037ca + +080037e8 : + 80037e8: b510 push {r4, lr} + 80037ea: 4614 mov r4, r2 + 80037ec: f8d0 02c8 ldr.w r0, [r0, #712] @ 0x2c8 + 80037f0: 461a mov r2, r3 + 80037f2: 4623 mov r3, r4 + 80037f4: f7fd fa36 bl 8000c64 + 80037f8: e8bd 4010 ldmia.w sp!, {r4, lr} + 80037fc: f7ff bfe5 b.w 80037ca + +08003800 : + 8003800: b508 push {r3, lr} + 8003802: f8d0 02c8 ldr.w r0, [r0, #712] @ 0x2c8 + 8003806: f7fd fa66 bl 8000cd6 + 800380a: e8bd 4008 ldmia.w sp!, {r3, lr} + 800380e: f7ff bfdc b.w 80037ca + +08003812 : + 8003812: b508 push {r3, lr} + 8003814: f8d0 02c8 ldr.w r0, [r0, #712] @ 0x2c8 + 8003818: f7fd fac4 bl 8000da4 + 800381c: e8bd 4008 ldmia.w sp!, {r3, lr} + 8003820: f7ff bfd3 b.w 80037ca + +08003824 : + 8003824: b508 push {r3, lr} + 8003826: f8d0 02c8 ldr.w r0, [r0, #712] @ 0x2c8 + 800382a: f7fd faf2 bl 8000e12 + 800382e: e8bd 4008 ldmia.w sp!, {r3, lr} + 8003832: f7ff bfca b.w 80037ca + +08003836 : + 8003836: b508 push {r3, lr} + 8003838: f8d0 02c8 ldr.w r0, [r0, #712] @ 0x2c8 + 800383c: f7fd f9ff bl 8000c3e + 8003840: e8bd 4008 ldmia.w sp!, {r3, lr} + 8003844: f7ff bfc1 b.w 80037ca + +08003848 : + 8003848: b508 push {r3, lr} + 800384a: f8d0 02c8 ldr.w r0, [r0, #712] @ 0x2c8 + 800384e: f7fd fa8e bl 8000d6e + 8003852: e8bd 4008 ldmia.w sp!, {r3, lr} + 8003856: f7ff bfb8 b.w 80037ca + +0800385a : + 800385a: b508 push {r3, lr} + 800385c: f8d0 02c8 ldr.w r0, [r0, #712] @ 0x2c8 + 8003860: f7fd fa67 bl 8000d32 + 8003864: e8bd 4008 ldmia.w sp!, {r3, lr} + 8003868: f7ff bfaf b.w 80037ca + +0800386c : + 800386c: 4402 add r2, r0 + 800386e: 4603 mov r3, r0 + 8003870: 4293 cmp r3, r2 + 8003872: d100 bne.n 8003876 + 8003874: 4770 bx lr + 8003876: f803 1b01 strb.w r1, [r3], #1 + 800387a: e7f9 b.n 8003870 + +0800387c <__libc_init_array>: + 800387c: b570 push {r4, r5, r6, lr} + 800387e: 4d0d ldr r5, [pc, #52] @ (80038b4 <__libc_init_array+0x38>) + 8003880: 4c0d ldr r4, [pc, #52] @ (80038b8 <__libc_init_array+0x3c>) + 8003882: 1b64 subs r4, r4, r5 + 8003884: 10a4 asrs r4, r4, #2 + 8003886: 2600 movs r6, #0 + 8003888: 42a6 cmp r6, r4 + 800388a: d109 bne.n 80038a0 <__libc_init_array+0x24> + 800388c: 4d0b ldr r5, [pc, #44] @ (80038bc <__libc_init_array+0x40>) + 800388e: 4c0c ldr r4, [pc, #48] @ (80038c0 <__libc_init_array+0x44>) + 8003890: f000 f818 bl 80038c4 <_init> + 8003894: 1b64 subs r4, r4, r5 + 8003896: 10a4 asrs r4, r4, #2 + 8003898: 2600 movs r6, #0 + 800389a: 42a6 cmp r6, r4 + 800389c: d105 bne.n 80038aa <__libc_init_array+0x2e> + 800389e: bd70 pop {r4, r5, r6, pc} + 80038a0: f855 3b04 ldr.w r3, [r5], #4 + 80038a4: 4798 blx r3 + 80038a6: 3601 adds r6, #1 + 80038a8: e7ee b.n 8003888 <__libc_init_array+0xc> + 80038aa: f855 3b04 ldr.w r3, [r5], #4 + 80038ae: 4798 blx r3 + 80038b0: 3601 adds r6, #1 + 80038b2: e7f2 b.n 800389a <__libc_init_array+0x1e> + 80038b4: 08003928 .word 0x08003928 + 80038b8: 08003928 .word 0x08003928 + 80038bc: 08003928 .word 0x08003928 + 80038c0: 0800392c .word 0x0800392c + +080038c4 <_init>: + 80038c4: b5f8 push {r3, r4, r5, r6, r7, lr} + 80038c6: bf00 nop + 80038c8: bcf8 pop {r3, r4, r5, r6, r7} + 80038ca: bc08 pop {r3} + 80038cc: 469e mov lr, r3 + 80038ce: 4770 bx lr + +080038d0 <_fini>: + 80038d0: b5f8 push {r3, r4, r5, r6, r7, lr} + 80038d2: bf00 nop + 80038d4: bcf8 pop {r3, r4, r5, r6, r7} + 80038d6: bc08 pop {r3} + 80038d8: 469e mov lr, r3 + 80038da: 4770 bx lr diff --git a/firmware/numpad/Release/modularkbd.map b/firmware/numpad/Release/modularkbd.map new file mode 100644 index 00000000..584e68ce --- /dev/null +++ b/firmware/numpad/Release/modularkbd.map @@ -0,0 +1,2396 @@ +Archive member included to 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.ARM.extab 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + .data 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o) + .bss 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o) + .text 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .data 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .bss 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .rodata 0x00000000 0x24 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .eh_frame 0x00000000 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .ARM.attributes + 0x00000000 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o + .text 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + .data 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + .bss 0x00000000 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x20000000 0x00020000 xrw +FLASH 0x08000000 0x00080000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crti.o +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +LOAD ./Core/Src/main.o +LOAD ./Core/Src/stm32f4xx_hal_msp.o +LOAD ./Core/Src/stm32f4xx_it.o +LOAD ./Core/Src/syscalls.o +LOAD ./Core/Src/sysmem.o +LOAD ./Core/Src/system_stm32f4xx.o +LOAD ./Core/Startup/startup_stm32f446retx.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o +LOAD ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o +LOAD ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o +LOAD ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o +LOAD ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o +LOAD ./USB_DEVICE/App/usb_device.o +LOAD ./USB_DEVICE/App/usbd_desc.o +LOAD ./USB_DEVICE/Target/usbd_conf.o +START GROUP +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a +END GROUP +START GROUP +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +END GROUP +START GROUP +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a +END GROUP +START GROUP +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a +END GROUP +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtend.o +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + 0x20020000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x08000000 0x1c4 + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0x1c4 ./Core/Startup/startup_stm32f446retx.o + 0x08000000 g_pfnVectors + 0x080001c4 . = ALIGN (0x4) + +.text 0x080001c4 0x3718 + 0x080001c4 . = ALIGN (0x4) + *(.text) + .text 0x080001c4 0x40 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .text 0x08000204 0x10 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-strlen.o) + 0x08000204 strlen + .text 0x08000214 0x30 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) + 0x08000214 __aeabi_uldivmod + .text 0x08000244 0x2f8 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + 0x08000244 __udivmoddi4 + .text 0x0800053c 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o) + 0x0800053c __aeabi_ldiv0 + 0x0800053c __aeabi_idiv0 + *(.text*) + .text.SystemClock_Config + 0x08000540 0xa4 ./Core/Src/main.o + 0x08000540 SystemClock_Config + .text.startup.main + 0x080005e4 0x12c ./Core/Src/main.o + 0x080005e4 main + .text.Error_Handler + 0x08000710 0x4 ./Core/Src/main.o + 0x08000710 Error_Handler + .text.HAL_MspInit + 0x08000714 0x38 ./Core/Src/stm32f4xx_hal_msp.o + 0x08000714 HAL_MspInit + .text.NMI_Handler + 0x0800074c 0x2 ./Core/Src/stm32f4xx_it.o + 0x0800074c NMI_Handler + .text.HardFault_Handler + 0x0800074e 0x2 ./Core/Src/stm32f4xx_it.o + 0x0800074e HardFault_Handler + .text.MemManage_Handler + 0x08000750 0x2 ./Core/Src/stm32f4xx_it.o + 0x08000750 MemManage_Handler + .text.BusFault_Handler + 0x08000752 0x2 ./Core/Src/stm32f4xx_it.o + 0x08000752 BusFault_Handler + .text.UsageFault_Handler + 0x08000754 0x2 ./Core/Src/stm32f4xx_it.o + 0x08000754 UsageFault_Handler + .text.SVC_Handler + 0x08000756 0x2 ./Core/Src/stm32f4xx_it.o + 0x08000756 SVC_Handler + .text.DebugMon_Handler + 0x08000758 0x2 ./Core/Src/stm32f4xx_it.o + 0x08000758 DebugMon_Handler + .text.PendSV_Handler + 0x0800075a 0x2 ./Core/Src/stm32f4xx_it.o + 0x0800075a PendSV_Handler + .text.SysTick_Handler + 0x0800075c 0x4 ./Core/Src/stm32f4xx_it.o + 0x0800075c SysTick_Handler + .text.OTG_FS_IRQHandler + 0x08000760 0xc ./Core/Src/stm32f4xx_it.o + 0x08000760 OTG_FS_IRQHandler + .text.SystemInit + 0x0800076c 0x14 ./Core/Src/system_stm32f4xx.o + 0x0800076c SystemInit + .text.Reset_Handler + 0x08000780 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./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x08002578 USB_EPStartXfer + .text.USB_ReadPacket + 0x0800277c 0x40 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x0800277c USB_ReadPacket + .text.USB_EPSetStall + 0x080027bc 0x56 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x080027bc USB_EPSetStall + .text.USB_EPClearStall + 0x08002812 0x52 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x08002812 USB_EPClearStall + .text.USB_SetDevAddress + 0x08002864 0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x08002864 USB_SetDevAddress + .text.USB_DevConnect + 0x08002884 0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x08002884 USB_DevConnect + .text.USB_DevDisconnect + 0x080028a0 0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x080028a0 USB_DevDisconnect + .text.USB_ReadInterrupts + 0x080028bc 0x8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x080028bc USB_ReadInterrupts + .text.USB_ReadDevAllOutEpInterrupt + 0x080028c4 0x10 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x080028c4 USB_ReadDevAllOutEpInterrupt + .text.USB_ReadDevAllInEpInterrupt + 0x080028d4 0x10 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x080028d4 USB_ReadDevAllInEpInterrupt + .text.USB_ReadDevOutEPInterrupt + 0x080028e4 0x12 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x080028e4 USB_ReadDevOutEPInterrupt + .text.USB_ReadDevInEPInterrupt + 0x080028f6 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x080028f6 USB_ReadDevInEPInterrupt + .text.USB_GetMode + 0x08002918 0x8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x08002918 USB_GetMode + .text.USB_ActivateSetup + 0x08002920 0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x08002920 USB_ActivateSetup + .text.USB_EP0_OutStart + 0x0800293c 0x4c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + 0x0800293c USB_EP0_OutStart + .text.USBD_HID_DataIn + 0x08002988 0x10 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./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x08002e5a USBD_LL_IsoOUTIncomplete + .text.USBD_LL_DevConnected + 0x08002e80 0x4 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x08002e80 USBD_LL_DevConnected + .text.USBD_LL_DevDisconnected + 0x08002e84 0x20 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x08002e84 USBD_LL_DevDisconnected + .text.USBD_CoreFindIF + 0x08002ea4 0x4 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x08002ea4 USBD_CoreFindIF + .text.USBD_CoreFindEP + 0x08002ea8 0x4 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x08002ea8 USBD_CoreFindEP + .text.USBD_GetEpDesc + 0x08002eac 0x24 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x08002eac USBD_GetEpDesc + .text.USBD_CtlError.constprop.0 + 0x08002ed0 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + *fill* 0x08002ee6 0x2 + .text.USBD_StdDevReq + 0x08002ee8 0x2f0 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x08002ee8 USBD_StdDevReq + .text.USBD_StdItfReq + 0x080031d8 0x5e ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x080031d8 USBD_StdItfReq + .text.USBD_StdEPReq + 0x08003236 0x148 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x08003236 USBD_StdEPReq + .text.USBD_ParseSetupRequest + 0x0800337e 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x0800337e USBD_ParseSetupRequest + .text.USBD_CtlError + 0x08003394 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x08003394 USBD_CtlError + .text.USBD_GetString + 0x080033aa 0x38 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x080033aa USBD_GetString + .text.USBD_CtlSendData + 0x080033e2 0x1c ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x080033e2 USBD_CtlSendData + .text.USBD_CtlContinueSendData + 0x080033fe 0x10 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x080033fe USBD_CtlContinueSendData + .text.USBD_CtlContinueRx + 0x0800340e 0x10 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0800340e USBD_CtlContinueRx + .text.USBD_CtlSendStatus + 0x0800341e 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x0800341e USBD_CtlSendStatus + .text.USBD_CtlReceiveStatus + 0x08003434 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x08003434 USBD_CtlReceiveStatus + *fill* 0x0800344a 0x2 + .text.MX_USB_DEVICE_Init + 0x0800344c 0x40 ./USB_DEVICE/App/usb_device.o + 0x0800344c MX_USB_DEVICE_Init + .text.USBD_FS_DeviceDescriptor + 0x0800348c 0xc ./USB_DEVICE/App/usbd_desc.o + 0x0800348c USBD_FS_DeviceDescriptor + .text.USBD_FS_LangIDStrDescriptor + 0x08003498 0xc ./USB_DEVICE/App/usbd_desc.o + 0x08003498 USBD_FS_LangIDStrDescriptor + .text.USBD_FS_USR_BOSDescriptor + 0x080034a4 0xc ./USB_DEVICE/App/usbd_desc.o + 0x080034a4 USBD_FS_USR_BOSDescriptor + .text.IntToUnicode + 0x080034b0 0x2a ./USB_DEVICE/App/usbd_desc.o + *fill* 0x080034da 0x2 + .text.USBD_FS_SerialStrDescriptor + 0x080034dc 0x3c ./USB_DEVICE/App/usbd_desc.o + 0x080034dc USBD_FS_SerialStrDescriptor + .text.USBD_FS_ManufacturerStrDescriptor + 0x08003518 0x1c ./USB_DEVICE/App/usbd_desc.o + 0x08003518 USBD_FS_ManufacturerStrDescriptor + .text.USBD_FS_ProductStrDescriptor + 0x08003534 0x1c ./USB_DEVICE/App/usbd_desc.o + 0x08003534 USBD_FS_ProductStrDescriptor + .text.USBD_FS_ConfigStrDescriptor + 0x08003550 0x1c ./USB_DEVICE/App/usbd_desc.o + 0x08003550 USBD_FS_ConfigStrDescriptor + .text.USBD_FS_InterfaceStrDescriptor + 0x0800356c 0x1c ./USB_DEVICE/App/usbd_desc.o + 0x0800356c USBD_FS_InterfaceStrDescriptor + .text.HAL_PCD_MspInit + 0x08003588 0xa0 ./USB_DEVICE/Target/usbd_conf.o + 0x08003588 HAL_PCD_MspInit + .text.HAL_PCD_SetupStageCallback + 0x08003628 0xc ./USB_DEVICE/Target/usbd_conf.o + 0x08003628 HAL_PCD_SetupStageCallback + .text.HAL_PCD_DataOutStageCallback + 0x08003634 0x12 ./USB_DEVICE/Target/usbd_conf.o + 0x08003634 HAL_PCD_DataOutStageCallback + .text.HAL_PCD_DataInStageCallback + 0x08003646 0x10 ./USB_DEVICE/Target/usbd_conf.o + 0x08003646 HAL_PCD_DataInStageCallback + .text.HAL_PCD_SOFCallback + 0x08003656 0x8 ./USB_DEVICE/Target/usbd_conf.o + 0x08003656 HAL_PCD_SOFCallback + .text.HAL_PCD_ResetCallback + 0x0800365e 0x26 ./USB_DEVICE/Target/usbd_conf.o + 0x0800365e HAL_PCD_ResetCallback + .text.HAL_PCD_SuspendCallback + 0x08003684 0x30 ./USB_DEVICE/Target/usbd_conf.o + 0x08003684 HAL_PCD_SuspendCallback + .text.HAL_PCD_ResumeCallback + 0x080036b4 0x8 ./USB_DEVICE/Target/usbd_conf.o + 0x080036b4 HAL_PCD_ResumeCallback + .text.HAL_PCD_ISOOUTIncompleteCallback + 0x080036bc 0x8 ./USB_DEVICE/Target/usbd_conf.o + 0x080036bc HAL_PCD_ISOOUTIncompleteCallback + .text.HAL_PCD_ISOINIncompleteCallback + 0x080036c4 0x8 ./USB_DEVICE/Target/usbd_conf.o + 0x080036c4 HAL_PCD_ISOINIncompleteCallback + .text.HAL_PCD_ConnectCallback + 0x080036cc 0x8 ./USB_DEVICE/Target/usbd_conf.o + 0x080036cc HAL_PCD_ConnectCallback + .text.HAL_PCD_DisconnectCallback + 0x080036d4 0x8 ./USB_DEVICE/Target/usbd_conf.o + 0x080036d4 HAL_PCD_DisconnectCallback + .text.USBD_LL_Init + 0x080036dc 0x5c ./USB_DEVICE/Target/usbd_conf.o + 0x080036dc USBD_LL_Init + .text.USBD_LL_IsStallEP + 0x08003738 0x24 ./USB_DEVICE/Target/usbd_conf.o + 0x08003738 USBD_LL_IsStallEP + .text.HAL_PCDEx_LPM_Callback + 0x0800375c 0x64 ./USB_DEVICE/Target/usbd_conf.o + 0x0800375c HAL_PCDEx_LPM_Callback + .text.USBD_static_malloc + 0x080037c0 0x8 ./USB_DEVICE/Target/usbd_conf.o + 0x080037c0 USBD_static_malloc + .text.USBD_static_free + 0x080037c8 0x2 ./USB_DEVICE/Target/usbd_conf.o + 0x080037c8 USBD_static_free + .text.USBD_Get_USB_Status + 0x080037ca 0xc ./USB_DEVICE/Target/usbd_conf.o + 0x080037ca USBD_Get_USB_Status + .text.USBD_LL_Start + 0x080037d6 0x12 ./USB_DEVICE/Target/usbd_conf.o + 0x080037d6 USBD_LL_Start + .text.USBD_LL_OpenEP + 0x080037e8 0x18 ./USB_DEVICE/Target/usbd_conf.o + 0x080037e8 USBD_LL_OpenEP + .text.USBD_LL_CloseEP + 0x08003800 0x12 ./USB_DEVICE/Target/usbd_conf.o + 0x08003800 USBD_LL_CloseEP + .text.USBD_LL_StallEP + 0x08003812 0x12 ./USB_DEVICE/Target/usbd_conf.o + 0x08003812 USBD_LL_StallEP + .text.USBD_LL_ClearStallEP + 0x08003824 0x12 ./USB_DEVICE/Target/usbd_conf.o + 0x08003824 USBD_LL_ClearStallEP + .text.USBD_LL_SetUSBAddress + 0x08003836 0x12 ./USB_DEVICE/Target/usbd_conf.o + 0x08003836 USBD_LL_SetUSBAddress + .text.USBD_LL_Transmit + 0x08003848 0x12 ./USB_DEVICE/Target/usbd_conf.o + 0x08003848 USBD_LL_Transmit + .text.USBD_LL_PrepareReceive + 0x0800385a 0x12 ./USB_DEVICE/Target/usbd_conf.o + 0x0800385a USBD_LL_PrepareReceive + .text.memset 0x0800386c 0x10 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memset.o) + 0x0800386c memset + .text.__libc_init_array + 0x0800387c 0x48 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-init.o) + 0x0800387c __libc_init_array + *(.glue_7) + .glue_7 0x080038c4 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x080038c4 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x080038c4 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + *(.init) + .init 0x080038c4 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crti.o + 0x080038c4 _init + .init 0x080038c8 0x8 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + *(.fini) + .fini 0x080038d0 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crti.o + 0x080038d0 _fini + .fini 0x080038d4 0x8 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + 0x080038dc . = ALIGN (0x4) + 0x080038dc _etext = . + +.vfp11_veneer 0x080038dc 0x0 + .vfp11_veneer 0x080038dc 0x0 linker stubs + +.v4_bx 0x080038dc 0x0 + .v4_bx 0x080038dc 0x0 linker stubs + +.iplt 0x080038dc 0x0 + .iplt 0x080038dc 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + +.rodata 0x080038dc 0x44 + 0x080038dc . = ALIGN (0x4) + *(.rodata) + *(.rodata*) + .rodata.AHBPrescTable + 0x080038dc 0x10 ./Core/Src/system_stm32f4xx.o + 0x080038dc AHBPrescTable + .rodata.USBD_FS_ManufacturerStrDescriptor.str1.1 + 0x080038ec 0x34 ./USB_DEVICE/App/usbd_desc.o + 0xa (size before relaxing) + .rodata.USBD_FS_ProductStrDescriptor.str1.1 + 0x08003920 0x11 ./USB_DEVICE/App/usbd_desc.o + .rodata.USBD_FS_ConfigStrDescriptor.str1.1 + 0x08003920 0xb ./USB_DEVICE/App/usbd_desc.o + .rodata.USBD_FS_InterfaceStrDescriptor.str1.1 + 0x08003920 0xe ./USB_DEVICE/App/usbd_desc.o + 0x08003934 . = ALIGN (0x4) + +.ARM.extab 0x08003920 0x0 + 0x08003920 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x08003920 . = ALIGN (0x4) + +.ARM 0x08003920 0x8 + 0x08003920 . = ALIGN (0x4) + 0x08003920 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x08003920 0x8 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-strlen.o) + .ARM.exidx 0x08003928 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + 0x8 (size before relaxing) + 0x08003928 __exidx_end = . + 0x08003928 . = ALIGN (0x4) + +.preinit_array 0x08003928 0x0 + 0x08003928 . = ALIGN (0x4) + 0x08003928 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x08003928 PROVIDE (__preinit_array_end = .) + 0x08003928 . = ALIGN (0x4) + +.init_array 0x08003928 0x4 + 0x08003928 . = ALIGN (0x4) + 0x08003928 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x08003928 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x0800392c PROVIDE (__init_array_end = .) + 0x0800392c . = ALIGN (0x4) + +.fini_array 0x0800392c 0x4 + 0x0800392c . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x0800392c 0x4 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x08003930 . = ALIGN (0x4) + 0x08003930 _sidata = LOADADDR (.data) + +.rel.dyn 0x08003930 0x0 + .rel.iplt 0x08003930 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + +.data 0x20000000 0x120 load address 0x08003930 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.SystemCoreClock + 0x20000000 0x4 ./Core/Src/system_stm32f4xx.o + 0x20000000 SystemCoreClock + .data.uwTickFreq + 0x20000004 0x1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x20000004 uwTickFreq + *fill* 0x20000005 0x3 + .data.uwTickPrio + 0x20000008 0x4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x20000008 uwTickPrio + .data.HID_MOUSE_ReportDesc + 0x2000000c 0x3f ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + *fill* 0x2000004b 0x1 + .data.USBD_HID_DeviceQualifierDesc + 0x2000004c 0xa ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + *fill* 0x20000056 0x2 + .data.USBD_HID_Desc + 0x20000058 0x9 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + *fill* 0x20000061 0x3 + .data.USBD_HID_CfgDesc + 0x20000064 0x22 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + *fill* 0x20000086 0x2 + .data.USBD_HID + 0x20000088 0x38 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + 0x20000088 USBD_HID + .data.USBD_StringSerial + 0x200000c0 0x1a ./USB_DEVICE/App/usbd_desc.o + 0x200000c0 USBD_StringSerial + *fill* 0x200000da 0x2 + .data.USBD_LangIDDesc + 0x200000dc 0x4 ./USB_DEVICE/App/usbd_desc.o + 0x200000dc USBD_LangIDDesc + .data.USBD_FS_BOSDesc + 0x200000e0 0xc ./USB_DEVICE/App/usbd_desc.o + 0x200000e0 USBD_FS_BOSDesc + .data.USBD_FS_DeviceDesc + 0x200000ec 0x12 ./USB_DEVICE/App/usbd_desc.o + 0x200000ec USBD_FS_DeviceDesc + *fill* 0x200000fe 0x2 + .data.FS_Desc 0x20000100 0x20 ./USB_DEVICE/App/usbd_desc.o + 0x20000100 FS_Desc + *(.RamFunc) + *(.RamFunc*) + 0x20000120 . = ALIGN (0x4) + 0x20000120 _edata = . + +.igot.plt 0x20000120 0x0 load address 0x08003a50 + .igot.plt 0x20000120 0x0 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x20000120 . = ALIGN (0x4) + +.bss 0x20000120 0xa00 load address 0x08003a50 + 0x20000120 _sbss = . + 0x20000120 __bss_start__ = _sbss + *(.bss) + .bss 0x20000120 0x1c /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + *(.bss*) + .bss.USBREPORT + 0x2000013c 0x8 ./Core/Src/main.o + 0x2000013c USBREPORT + .bss.uwTick 0x20000144 0x4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x20000144 uwTick + .bss.cfgidx.0 0x20000148 0x1 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + *fill* 0x20000149 0x3 + .bss.hUsbDeviceFS + 0x2000014c 0x2dc ./USB_DEVICE/App/usb_device.o + 0x2000014c hUsbDeviceFS + .bss.USBD_StrDesc + 0x20000428 0x200 ./USB_DEVICE/App/usbd_desc.o + 0x20000428 USBD_StrDesc + .bss.mem.0 0x20000628 0x14 ./USB_DEVICE/Target/usbd_conf.o + .bss.hpcd_USB_OTG_FS + 0x2000063c 0x4e4 ./USB_DEVICE/Target/usbd_conf.o + 0x2000063c hpcd_USB_OTG_FS + *(COMMON) + 0x20000b20 . = ALIGN (0x4) + 0x20000b20 _ebss = . + 0x20000b20 __bss_end__ = _ebss + +._user_heap_stack + 0x20000b20 0x600 load address 0x08003a50 + 0x20000b20 . = ALIGN (0x8) + [!provide] PROVIDE (end = .) + 0x20000b20 PROVIDE (_end = .) + 0x20000d20 . = (. + _Min_Heap_Size) + *fill* 0x20000b20 0x200 + 0x20001120 . = (. + _Min_Stack_Size) + *fill* 0x20000d20 0x400 + 0x20001120 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x00000000 0x30 + *(.ARM.attributes) + .ARM.attributes + 0x00000000 0x22 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crti.o + .ARM.attributes + 0x00000022 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .ARM.attributes + 0x00000056 0x34 ./Core/Src/main.o + .ARM.attributes + 0x0000008a 0x34 ./Core/Src/stm32f4xx_hal_msp.o + .ARM.attributes + 0x000000be 0x34 ./Core/Src/stm32f4xx_it.o + .ARM.attributes + 0x000000f2 0x34 ./Core/Src/system_stm32f4xx.o + .ARM.attributes + 0x00000126 0x21 ./Core/Startup/startup_stm32f446retx.o + .ARM.attributes + 0x00000147 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .ARM.attributes + 0x0000017b 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .ARM.attributes + 0x000001af 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .ARM.attributes + 0x000001e3 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o + .ARM.attributes + 0x00000217 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o + .ARM.attributes + 0x0000024b 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .ARM.attributes + 0x0000027f 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .ARM.attributes + 0x000002b3 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + .ARM.attributes + 0x000002e7 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .ARM.attributes + 0x0000031b 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .ARM.attributes + 0x0000034f 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .ARM.attributes + 0x00000383 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .ARM.attributes + 0x000003b7 0x34 ./USB_DEVICE/App/usb_device.o + .ARM.attributes + 0x000003eb 0x34 ./USB_DEVICE/App/usbd_desc.o + .ARM.attributes + 0x0000041f 0x34 ./USB_DEVICE/Target/usbd_conf.o + .ARM.attributes + 0x00000453 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memset.o) + .ARM.attributes + 0x00000487 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-init.o) + .ARM.attributes + 0x000004bb 0x17 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-strlen.o) + .ARM.attributes + 0x000004d2 0x22 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x000004f4 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x00000528 0x22 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x0000054a 0x22 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o +OUTPUT(modularkbd.elf elf32-littlearm) +LOAD linker stubs +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a +LOAD /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a + +.comment 0x00000000 0x43 + .comment 0x00000000 0x43 ./Core/Src/main.o + 0x44 (size before relaxing) + .comment 0x00000043 0x44 ./Core/Src/stm32f4xx_hal_msp.o + .comment 0x00000043 0x44 ./Core/Src/stm32f4xx_it.o + .comment 0x00000043 0x44 ./Core/Src/system_stm32f4xx.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o + .comment 0x00000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .comment 0x00000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .comment 0x00000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .comment 0x00000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .comment 0x00000043 0x44 ./USB_DEVICE/App/usb_device.o + .comment 0x00000043 0x44 ./USB_DEVICE/App/usbd_desc.o + .comment 0x00000043 0x44 ./USB_DEVICE/Target/usbd_conf.o + +.debug_frame 0x00000000 0xac + .debug_frame 0x00000000 0x20 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memset.o) + .debug_frame 0x00000020 0x2c /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-init.o) + .debug_frame 0x0000004c 0x2c /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00000078 0x34 /home/ukim/st/stm32cubeide_1.19.0/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.linux64_1.0.0.202410170706/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/libgcc.a(_udivmoddi4.o) diff --git a/firmware/numpad/Release/objects.list b/firmware/numpad/Release/objects.list new file mode 100644 index 00000000..00e4a516 --- /dev/null +++ b/firmware/numpad/Release/objects.list @@ -0,0 +1,35 @@ +"./Core/Src/main.o" +"./Core/Src/stm32f4xx_hal_msp.o" +"./Core/Src/stm32f4xx_it.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32f4xx.o" +"./Core/Startup/startup_stm32f446retx.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.o" +"./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o" +"./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o" +"./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o" +"./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o" +"./USB_DEVICE/App/usb_device.o" +"./USB_DEVICE/App/usbd_desc.o" +"./USB_DEVICE/Target/usbd_conf.o" diff --git a/firmware/numpad/Release/objects.mk b/firmware/numpad/Release/objects.mk new file mode 100644 index 00000000..b471e98e --- /dev/null +++ b/firmware/numpad/Release/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/firmware/numpad/Release/sources.mk b/firmware/numpad/Release/sources.mk new file mode 100644 index 00000000..083ab34c --- /dev/null +++ b/firmware/numpad/Release/sources.mk @@ -0,0 +1,32 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +CYCLO_FILES := +SIZE_OUTPUT := +OBJDUMP_LIST := +SU_FILES := +EXECUTABLES := +OBJS := +MAP_FILES := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/STM32F4xx_HAL_Driver/Src \ +Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src \ +Middlewares/ST/STM32_USB_Device_Library/Core/Src \ +USB_DEVICE/App \ +USB_DEVICE/Target \ + diff --git a/firmware/numpad/STM32F446RETX_FLASH.ld b/firmware/numpad/STM32F446RETX_FLASH.ld new file mode 100644 index 00000000..09d5db96 --- /dev/null +++ b/firmware/numpad/STM32F446RETX_FLASH.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32F446RETx Device from STM32F4 series +** 512KBytes FLASH +** 128KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/firmware/numpad/STM32F446RETX_RAM.ld b/firmware/numpad/STM32F446RETX_RAM.ld new file mode 100644 index 00000000..b458d6fb --- /dev/null +++ b/firmware/numpad/STM32F446RETX_RAM.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld (debug in RAM dedicated) +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32F446RETx Device from STM32F4 series +** 512KBytes FLASH +** 128KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >RAM + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >RAM + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >RAM + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >RAM + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/firmware/numpad/USB_DEVICE/App/usb_device.c b/firmware/numpad/USB_DEVICE/App/usb_device.c new file mode 100644 index 00000000..3d3e900d --- /dev/null +++ b/firmware/numpad/USB_DEVICE/App/usb_device.c @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usb_device.c + * @version : v1.0_Cube + * @brief : This file implements the USB Device + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ + +#include "usb_device.h" +#include "usbd_core.h" +#include "usbd_desc.h" +#include "usbd_hid.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ + +/* USER CODE END PFP */ + +/* USB Device Core handle declaration. */ +USBD_HandleTypeDef hUsbDeviceFS; + +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* + * -- Insert your external function declaration here -- + */ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Init USB device Library, add supported class and start the library + * @retval None + */ +void MX_USB_DEVICE_Init(void) +{ + /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ + + /* USER CODE END USB_DEVICE_Init_PreTreatment */ + + /* Init Device Library, add supported class and start the library. */ + if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) + { + Error_Handler(); + } + if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) + { + Error_Handler(); + } + if (USBD_Start(&hUsbDeviceFS) != USBD_OK) + { + Error_Handler(); + } + + /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ + + /* USER CODE END USB_DEVICE_Init_PostTreatment */ +} + +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/USB_DEVICE/App/usb_device.h b/firmware/numpad/USB_DEVICE/App/usb_device.h new file mode 100644 index 00000000..5d3020f4 --- /dev/null +++ b/firmware/numpad/USB_DEVICE/App/usb_device.h @@ -0,0 +1,102 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usb_device.h + * @version : v1.0_Cube + * @brief : Header for usb_device.c file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_DEVICE__H__ +#define __USB_DEVICE__H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" +#include "stm32f4xx_hal.h" +#include "usbd_def.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup USBD_OTG_DRIVER + * @{ + */ + +/** @defgroup USBD_DEVICE USBD_DEVICE + * @brief Device file for Usb otg low level driver. + * @{ + */ + +/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables + * @brief Public variables. + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN VARIABLES */ + +/* USER CODE END VARIABLES */ +/** + * @} + */ + +/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb device. + * @{ + */ + +/** USB Device initialization function. */ +void MX_USB_DEVICE_Init(void); + +/* + * -- Insert functions declaration here -- + */ +/* USER CODE BEGIN FD */ + +/* USER CODE END FD */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEVICE__H__ */ diff --git a/firmware/numpad/USB_DEVICE/App/usbd_desc.c b/firmware/numpad/USB_DEVICE/App/usbd_desc.c new file mode 100644 index 00000000..332d755b --- /dev/null +++ b/firmware/numpad/USB_DEVICE/App/usbd_desc.c @@ -0,0 +1,445 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : App/usbd_desc.c + * @version : v1.0_Cube + * @brief : This file implements the USB device descriptors. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" +#include "usbd_desc.h" +#include "usbd_conf.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @addtogroup USBD_DESC + * @{ + */ + +/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions + * @brief Private types. + * @{ + */ + +/* USER CODE BEGIN PRIVATE_TYPES */ + +/* USER CODE END PRIVATE_TYPES */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines + * @brief Private defines. + * @{ + */ + +#define USBD_VID 1155 +#define USBD_LANGID_STRING 1033 +#define USBD_MANUFACTURER_STRING "Team SKBD" +#define USBD_PID_FS 22315 +#define USBD_PRODUCT_STRING_FS "Modular Keyboard" +#define USBD_CONFIGURATION_STRING_FS "HID Config" +#define USBD_INTERFACE_STRING_FS "HID Interface" + +#define USB_SIZ_BOS_DESC 0x0C + +/* USER CODE BEGIN PRIVATE_DEFINES */ + +/* USER CODE END PRIVATE_DEFINES */ + +/** + * @} + */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros + * @brief Private macros. + * @{ + */ + +/* USER CODE BEGIN PRIVATE_MACRO */ + +/* USER CODE END PRIVATE_MACRO */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes + * @brief Private functions declaration. + * @{ + */ + +static void Get_SerialNum(void); +static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len); + +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes + * @brief Private functions declaration for FS. + * @{ + */ + +uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +#if (USBD_LPM_ENABLED == 1) +uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +#endif /* (USBD_LPM_ENABLED == 1) */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables + * @brief Private variables. + * @{ + */ + +USBD_DescriptorsTypeDef FS_Desc = +{ + USBD_FS_DeviceDescriptor +, USBD_FS_LangIDStrDescriptor +, USBD_FS_ManufacturerStrDescriptor +, USBD_FS_ProductStrDescriptor +, USBD_FS_SerialStrDescriptor +, USBD_FS_ConfigStrDescriptor +, USBD_FS_InterfaceStrDescriptor +#if (USBD_LPM_ENABLED == 1) +, USBD_FS_USR_BOSDescriptor +#endif /* (USBD_LPM_ENABLED == 1) */ +}; + +#if defined ( __ICCARM__ ) /* IAR Compiler */ + #pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +/** USB standard device descriptor. */ +__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = +{ + 0x12, /*bLength */ + USB_DESC_TYPE_DEVICE, /*bDescriptorType*/ +#if (USBD_LPM_ENABLED == 1) + 0x01, /*bcdUSB */ /* changed to USB version 2.01 + in order to support LPM L1 suspend + resume test of USBCV3.0*/ +#else + 0x00, /*bcdUSB */ +#endif /* (USBD_LPM_ENABLED == 1) */ + 0x02, + 0x00, /*bDeviceClass*/ + 0x00, /*bDeviceSubClass*/ + 0x00, /*bDeviceProtocol*/ + USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ + LOBYTE(USBD_VID), /*idVendor*/ + HIBYTE(USBD_VID), /*idVendor*/ + LOBYTE(USBD_PID_FS), /*idProduct*/ + HIBYTE(USBD_PID_FS), /*idProduct*/ + 0x00, /*bcdDevice rel. 2.00*/ + 0x02, + USBD_IDX_MFC_STR, /*Index of manufacturer string*/ + USBD_IDX_PRODUCT_STR, /*Index of product string*/ + USBD_IDX_SERIAL_STR, /*Index of serial number string*/ + USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/ +}; + +/* USB_DeviceDescriptor */ +/** BOS descriptor. */ +#if (USBD_LPM_ENABLED == 1) +#if defined ( __ICCARM__ ) /* IAR Compiler */ + #pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +__ALIGN_BEGIN uint8_t USBD_FS_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END = +{ + 0x5, + USB_DESC_TYPE_BOS, + 0xC, + 0x0, + 0x1, /* 1 device capability*/ + /* device capability*/ + 0x7, + USB_DEVICE_CAPABITY_TYPE, + 0x2, + 0x2, /* LPM capability bit set*/ + 0x0, + 0x0, + 0x0 +}; +#endif /* (USBD_LPM_ENABLED == 1) */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables + * @brief Private variables. + * @{ + */ + +#if defined ( __ICCARM__ ) /* IAR Compiler */ + #pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ + +/** USB lang identifier descriptor. */ +__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = +{ + USB_LEN_LANGID_STR_DESC, + USB_DESC_TYPE_STRING, + LOBYTE(USBD_LANGID_STRING), + HIBYTE(USBD_LANGID_STRING) +}; + +#if defined ( __ICCARM__ ) /* IAR Compiler */ + #pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +/* Internal string descriptor. */ +__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = { + USB_SIZ_STRING_SERIAL, + USB_DESC_TYPE_STRING, +}; + +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions + * @brief Private functions. + * @{ + */ + +/** + * @brief Return the device descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + UNUSED(speed); + *length = sizeof(USBD_FS_DeviceDesc); + return USBD_FS_DeviceDesc; +} + +/** + * @brief Return the LangID string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + UNUSED(speed); + *length = sizeof(USBD_LangIDDesc); + return USBD_LangIDDesc; +} + +/** + * @brief Return the product string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + if(speed == 0) + { + USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + } + else + { + USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + } + return USBD_StrDesc; +} + +/** + * @brief Return the manufacturer string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + UNUSED(speed); + USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + return USBD_StrDesc; +} + +/** + * @brief Return the serial number string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + UNUSED(speed); + *length = USB_SIZ_STRING_SERIAL; + + /* Update the serial number string descriptor with the data from the unique + * ID */ + Get_SerialNum(); + /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ + + /* USER CODE END USBD_FS_SerialStrDescriptor */ + return (uint8_t *) USBD_StringSerial; +} + +/** + * @brief Return the configuration string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + if(speed == USBD_SPEED_HIGH) + { + USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + } + else + { + USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + } + return USBD_StrDesc; +} + +/** + * @brief Return the interface string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + if(speed == 0) + { + USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + } + else + { + USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + } + return USBD_StrDesc; +} + +#if (USBD_LPM_ENABLED == 1) +/** + * @brief Return the BOS descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + UNUSED(speed); + *length = sizeof(USBD_FS_BOSDesc); + return (uint8_t*)USBD_FS_BOSDesc; +} +#endif /* (USBD_LPM_ENABLED == 1) */ + +/** + * @brief Create the serial number string descriptor + * @param None + * @retval None + */ +static void Get_SerialNum(void) +{ + uint32_t deviceserial0; + uint32_t deviceserial1; + uint32_t deviceserial2; + + deviceserial0 = *(uint32_t *) DEVICE_ID1; + deviceserial1 = *(uint32_t *) DEVICE_ID2; + deviceserial2 = *(uint32_t *) DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) + { + IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); + IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); + } +} + +/** + * @brief Convert Hex 32Bits value into char + * @param value: value to convert + * @param pbuf: pointer to the buffer + * @param len: buffer length + * @retval None + */ +static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) +{ + uint8_t idx = 0; + + for (idx = 0; idx < len; idx++) + { + if (((value >> 28)) < 0xA) + { + pbuf[2 * idx] = (value >> 28) + '0'; + } + else + { + pbuf[2 * idx] = (value >> 28) + 'A' - 10; + } + + value = value << 4; + + pbuf[2 * idx + 1] = 0; + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/firmware/numpad/USB_DEVICE/App/usbd_desc.h b/firmware/numpad/USB_DEVICE/App/usbd_desc.h new file mode 100644 index 00000000..a42cff0c --- /dev/null +++ b/firmware/numpad/USB_DEVICE/App/usbd_desc.h @@ -0,0 +1,143 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_desc.c + * @version : v1.0_Cube + * @brief : Header for usbd_conf.c file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_DESC__C__ +#define __USBD_DESC__C__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_DESC USBD_DESC + * @brief Usb device descriptors module. + * @{ + */ + +/* + * User to provide a unique ID to define the USB device serial number + * The use of UID_BASE register can be considered as an example + */ +#define DEVICE_ID1 (UID_BASE) +#define DEVICE_ID2 (UID_BASE + 0x4) +#define DEVICE_ID3 (UID_BASE + 0x8) + +#define USB_SIZ_STRING_SERIAL 0x1A + +/* USER CODE BEGIN EXPORTED_CONSTANTS */ + +/* USER CODE END EXPORTED_CONSTANTS */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines + * @brief Defines. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_DEFINES */ + +/* USER CODE END EXPORTED_DEFINES */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions + * @brief Types. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_TYPES */ + +/* USER CODE END EXPORTED_TYPES */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros + * @brief Aliases. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_MACRO */ + +/* USER CODE END EXPORTED_MACRO */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** Descriptor for the Usb device. */ +extern USBD_DescriptorsTypeDef FS_Desc; + +/* USER CODE BEGIN EXPORTED_VARIABLES */ + +/* USER CODE END EXPORTED_VARIABLES */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype + * @brief Public functions declaration. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_FUNCTIONS */ + +/* USER CODE END EXPORTED_FUNCTIONS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_DESC__C__ */ + diff --git a/firmware/numpad/USB_DEVICE/Target/usbd_conf.c b/firmware/numpad/USB_DEVICE/Target/usbd_conf.c new file mode 100644 index 00000000..2cd51711 --- /dev/null +++ b/firmware/numpad/USB_DEVICE/Target/usbd_conf.c @@ -0,0 +1,725 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : Target/usbd_conf.c + * @version : v1.0_Cube + * @brief : This file implements the board support package for the USB device library + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" +#include "stm32f4xx_hal.h" +#include "usbd_def.h" +#include "usbd_core.h" + +#include "usbd_hid.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +PCD_HandleTypeDef hpcd_USB_OTG_FS; +void Error_Handler(void); + +/* External functions --------------------------------------------------------*/ +void SystemClock_Config(void); + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ +USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status); + +/* USER CODE END PFP */ + +/* Private functions ---------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/******************************************************************************* + LL Driver Callbacks (PCD -> USB Device Library) +*******************************************************************************/ +/* MSP Init */ + +void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(pcdHandle->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ + + /* USER CODE END USB_OTG_FS_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + + /* USER CODE END USB_OTG_FS_MspInit 1 */ + } +} + +void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) +{ + if(pcdHandle->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); + + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + + /* Peripheral interrupt Deinit*/ + HAL_NVIC_DisableIRQ(OTG_FS_IRQn); + + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 1 */ + } +} + +/** + * @brief Setup stage callback + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); +} + +/** + * @brief Data Out stage callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); +} + +/** + * @brief Data In stage callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); +} + +/** + * @brief SOF callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief Reset callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_SpeedTypeDef speed = USBD_SPEED_FULL; + + if ( hpcd->Init.speed == PCD_SPEED_HIGH) + { + speed = USBD_SPEED_HIGH; + } + else if ( hpcd->Init.speed == PCD_SPEED_FULL) + { + speed = USBD_SPEED_FULL; + } + else + { + Error_Handler(); + } + /* Set Speed. */ + USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); + + /* Reset Device. */ + USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief Suspend callback. + * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + /* Inform USB library that core enters in suspend Mode. */ + USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); + __HAL_PCD_GATE_PHYCLOCK(hpcd); + /* Enter in STOP mode. */ + /* USER CODE BEGIN 2 */ + if (hpcd->Init.low_power_enable) + { + /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ + SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + } + /* USER CODE END 2 */ +} + +/** + * @brief Resume callback. + * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + /* USER CODE BEGIN 3 */ + + /* USER CODE END 3 */ + USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief ISOOUTIncomplete callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); +} + +/** + * @brief ISOINIncomplete callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint number + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); +} + +/** + * @brief Connect callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); +} + +/** + * @brief Disconnect callback. + * @param hpcd: PCD handle + * @retval None + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); +} + +/******************************************************************************* + LL Driver Interface (USB Device Library --> PCD) +*******************************************************************************/ + +/** + * @brief Initializes the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) +{ + /* Init USB Ip. */ + if (pdev->id == DEVICE_FS) { + /* Link the driver to the stack. */ + hpcd_USB_OTG_FS.pData = pdev; + pdev->pData = &hpcd_USB_OTG_FS; + + hpcd_USB_OTG_FS.Instance = USB_OTG_FS; + hpcd_USB_OTG_FS.Init.dev_endpoints = 6; + hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; + hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; + hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; + hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; + hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; + hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; + if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) + { + Error_Handler( ); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + /* Register USB PCD CallBacks */ + HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback); + HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback); + + HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); + HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); + HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); + HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); + } + return USBD_OK; +} + +/** + * @brief De-Initializes the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_DeInit(pdev->pData); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Starts the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_Start(pdev->pData); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Stops the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_Stop(pdev->pData); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Opens an endpoint of the low level driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @param ep_type: Endpoint type + * @param ep_mps: Endpoint max packet size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Closes an endpoint of the low level driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Flushes an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Sets a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Clears a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Returns Stall condition. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval Stall (1: Yes, 0: No) + */ +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; + + if((ep_addr & 0x80) == 0x80) + { + return hpcd->IN_ep[ep_addr & 0x7F].is_stall; + } + else + { + return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; + } +} + +/** + * @brief Assigns a USB address to the device. + * @param pdev: Device handle + * @param dev_addr: Device address + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Transmits data over an endpoint. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @param pbuf: Pointer to data to be sent + * @param size: Data size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Prepares an endpoint for reception. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @param pbuf: Pointer to data to be received + * @param size: Data size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + USBD_StatusTypeDef usb_status = USBD_OK; + + hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; +} + +/** + * @brief Returns the last transferred packet size. + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval Received Data Size + */ +uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); +} + +/** + * @brief Send LPM message to user layer + * @param hpcd: PCD handle + * @param msg: LPM message + * @retval None + */ +void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) +{ + switch (msg) + { + case PCD_LPM_L0_ACTIVE: + if (hpcd->Init.low_power_enable) + { + SystemClock_Config(); + + /* Reset SLEEPDEEP bit of Cortex System Control Register. */ + SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + } + __HAL_PCD_UNGATE_PHYCLOCK(hpcd); + USBD_LL_Resume(hpcd->pData); + break; + + case PCD_LPM_L1_ACTIVE: + __HAL_PCD_GATE_PHYCLOCK(hpcd); + USBD_LL_Suspend(hpcd->pData); + + /* Enter in STOP mode. */ + if (hpcd->Init.low_power_enable) + { + /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ + SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + } + break; + } +} + +#ifdef USBD_HS_TESTMODE_ENABLE +/** + * @brief Set High speed Test mode. + * @param pdev: Device handle + * @param testmode: test mode + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_SetTestMode(USBD_HandleTypeDef *pdev, uint8_t testmode) +{ + UNUSED(pdev); + UNUSED(testmode); + + return USBD_OK; +} +#endif /* USBD_HS_TESTMODE_ENABLE */ + +/** + * @brief Static single allocation. + * @param size: Size of allocated memory + * @retval None + */ +void *USBD_static_malloc(uint32_t size) +{ + static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ + return mem; +} + +/** + * @brief Dummy memory free + * @param p: Pointer to allocated memory address + * @retval None + */ +void USBD_static_free(void *p) +{ + +} + +/** + * @brief Delays routine for the USB Device Library. + * @param Delay: Delay in ms + * @retval None + */ +void USBD_LL_Delay(uint32_t Delay) +{ + HAL_Delay(Delay); +} + +/** + * @brief Returns the USB status depending on the HAL status: + * @param hal_status: HAL status + * @retval USB status + */ +USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) +{ + USBD_StatusTypeDef usb_status = USBD_OK; + + switch (hal_status) + { + case HAL_OK : + usb_status = USBD_OK; + break; + case HAL_ERROR : + usb_status = USBD_FAIL; + break; + case HAL_BUSY : + usb_status = USBD_BUSY; + break; + case HAL_TIMEOUT : + usb_status = USBD_FAIL; + break; + default : + usb_status = USBD_FAIL; + break; + } + return usb_status; +} diff --git a/firmware/numpad/USB_DEVICE/Target/usbd_conf.h b/firmware/numpad/USB_DEVICE/Target/usbd_conf.h new file mode 100644 index 00000000..ac928543 --- /dev/null +++ b/firmware/numpad/USB_DEVICE/Target/usbd_conf.h @@ -0,0 +1,175 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_conf.h + * @version : v1.0_Cube + * @brief : Header for usbd_conf.c file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CONF__H__ +#define __USBD_CONF__H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include +#include "main.h" +#include "stm32f4xx.h" +#include "stm32f4xx_hal.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup USBD_OTG_DRIVER + * @brief Driver for Usb device. + * @{ + */ + +/** @defgroup USBD_CONF USBD_CONF + * @brief Configuration file for Usb otg low level driver. + * @{ + */ + +/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines + * @brief Defines for configuration of the Usb device. + * @{ + */ + +/*---------- -----------*/ +#define USBD_MAX_NUM_INTERFACES 1U +/*---------- -----------*/ +#define USBD_MAX_NUM_CONFIGURATION 1U +/*---------- -----------*/ +#define USBD_MAX_STR_DESC_SIZ 512U +/*---------- -----------*/ +#define USBD_DEBUG_LEVEL 0U +/*---------- -----------*/ +#define USBD_LPM_ENABLED 1U +/*---------- -----------*/ +#define USBD_SELF_POWERED 1U +/*---------- -----------*/ +#define HID_FS_BINTERVAL 0xAU + +/****************************************/ +/* #define for FS and HS identification */ +#define DEVICE_FS 0 +#define DEVICE_HS 1 + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros + * @brief Aliases. + * @{ + */ +/* Memory management macros make sure to use static memory allocation */ +/** Alias for memory allocation. */ + +#define USBD_malloc (void *)USBD_static_malloc + +/** Alias for memory release. */ +#define USBD_free USBD_static_free + +/** Alias for memory set. */ +#define USBD_memset memset + +/** Alias for memory copy. */ +#define USBD_memcpy memcpy + +/** Alias for delay. */ +#define USBD_Delay HAL_Delay + +/* DEBUG macros */ + +#if (USBD_DEBUG_LEVEL > 0) +#define USBD_UsrLog(...) printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_UsrLog(...) +#endif /* (USBD_DEBUG_LEVEL > 0U) */ + +#if (USBD_DEBUG_LEVEL > 1) + +#define USBD_ErrLog(...) printf("ERROR: ");\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_ErrLog(...) +#endif /* (USBD_DEBUG_LEVEL > 1U) */ + +#if (USBD_DEBUG_LEVEL > 2) +#define USBD_DbgLog(...) printf("DEBUG : ");\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_DbgLog(...) +#endif /* (USBD_DEBUG_LEVEL > 2U) */ + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types + * @brief Types. + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb device. + * @{ + */ + +/* Exported functions -------------------------------------------------------*/ +void *USBD_static_malloc(uint32_t size); +void USBD_static_free(void *p); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CONF__H__ */ + diff --git a/firmware/numpad/modularkbd.ioc b/firmware/numpad/modularkbd.ioc new file mode 100644 index 00000000..6527eeb2 --- /dev/null +++ b/firmware/numpad/modularkbd.ioc @@ -0,0 +1,362 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats=[] +CAD.pinconfig=Dual +CAD.provider= +Dma.Request0=UART4_RX +Dma.Request1=UART4_TX +Dma.Request2=UART5_RX +Dma.Request3=UART5_TX +Dma.Request4=USART1_RX +Dma.Request5=USART1_TX +Dma.Request6=USART2_RX +Dma.Request7=USART2_TX +Dma.RequestsNb=8 +Dma.UART4_RX.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.UART4_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.UART4_RX.0.Instance=DMA1_Stream2 +Dma.UART4_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.UART4_RX.0.MemInc=DMA_MINC_ENABLE +Dma.UART4_RX.0.Mode=DMA_NORMAL +Dma.UART4_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.UART4_RX.0.PeriphInc=DMA_PINC_DISABLE +Dma.UART4_RX.0.Priority=DMA_PRIORITY_LOW +Dma.UART4_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.UART4_TX.1.Direction=DMA_MEMORY_TO_PERIPH +Dma.UART4_TX.1.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.UART4_TX.1.Instance=DMA1_Stream4 +Dma.UART4_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.UART4_TX.1.MemInc=DMA_MINC_ENABLE +Dma.UART4_TX.1.Mode=DMA_NORMAL +Dma.UART4_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.UART4_TX.1.PeriphInc=DMA_PINC_DISABLE +Dma.UART4_TX.1.Priority=DMA_PRIORITY_LOW +Dma.UART4_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.UART5_RX.2.Direction=DMA_PERIPH_TO_MEMORY +Dma.UART5_RX.2.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.UART5_RX.2.Instance=DMA1_Stream0 +Dma.UART5_RX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.UART5_RX.2.MemInc=DMA_MINC_ENABLE +Dma.UART5_RX.2.Mode=DMA_NORMAL +Dma.UART5_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.UART5_RX.2.PeriphInc=DMA_PINC_DISABLE +Dma.UART5_RX.2.Priority=DMA_PRIORITY_LOW +Dma.UART5_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.UART5_TX.3.Direction=DMA_MEMORY_TO_PERIPH +Dma.UART5_TX.3.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.UART5_TX.3.Instance=DMA1_Stream7 +Dma.UART5_TX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.UART5_TX.3.MemInc=DMA_MINC_ENABLE +Dma.UART5_TX.3.Mode=DMA_NORMAL +Dma.UART5_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.UART5_TX.3.PeriphInc=DMA_PINC_DISABLE +Dma.UART5_TX.3.Priority=DMA_PRIORITY_LOW +Dma.UART5_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.USART1_RX.4.Direction=DMA_PERIPH_TO_MEMORY +Dma.USART1_RX.4.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART1_RX.4.Instance=DMA2_Stream2 +Dma.USART1_RX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART1_RX.4.MemInc=DMA_MINC_ENABLE +Dma.USART1_RX.4.Mode=DMA_NORMAL +Dma.USART1_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART1_RX.4.PeriphInc=DMA_PINC_DISABLE +Dma.USART1_RX.4.Priority=DMA_PRIORITY_LOW +Dma.USART1_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.USART1_TX.5.Direction=DMA_MEMORY_TO_PERIPH +Dma.USART1_TX.5.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART1_TX.5.Instance=DMA2_Stream7 +Dma.USART1_TX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART1_TX.5.MemInc=DMA_MINC_ENABLE +Dma.USART1_TX.5.Mode=DMA_NORMAL +Dma.USART1_TX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART1_TX.5.PeriphInc=DMA_PINC_DISABLE +Dma.USART1_TX.5.Priority=DMA_PRIORITY_LOW +Dma.USART1_TX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.USART2_RX.6.Direction=DMA_PERIPH_TO_MEMORY +Dma.USART2_RX.6.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART2_RX.6.Instance=DMA1_Stream5 +Dma.USART2_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART2_RX.6.MemInc=DMA_MINC_ENABLE +Dma.USART2_RX.6.Mode=DMA_NORMAL +Dma.USART2_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART2_RX.6.PeriphInc=DMA_PINC_DISABLE +Dma.USART2_RX.6.Priority=DMA_PRIORITY_LOW +Dma.USART2_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.USART2_TX.7.Direction=DMA_MEMORY_TO_PERIPH +Dma.USART2_TX.7.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART2_TX.7.Instance=DMA1_Stream6 +Dma.USART2_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART2_TX.7.MemInc=DMA_MINC_ENABLE +Dma.USART2_TX.7.Mode=DMA_NORMAL +Dma.USART2_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART2_TX.7.PeriphInc=DMA_PINC_DISABLE +Dma.USART2_TX.7.Priority=DMA_PRIORITY_LOW +Dma.USART2_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +Mcu.CPN=STM32F446RET6 +Mcu.Family=STM32F4 +Mcu.IP0=DMA +Mcu.IP1=I2C1 +Mcu.IP10=USART2 +Mcu.IP11=USB_DEVICE +Mcu.IP12=USB_OTG_FS +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=SYS +Mcu.IP5=TIM2 +Mcu.IP6=TIM3 +Mcu.IP7=UART4 +Mcu.IP8=UART5 +Mcu.IP9=USART1 +Mcu.IPNb=13 +Mcu.Name=STM32F446R(C-E)Tx +Mcu.Package=LQFP64 +Mcu.Pin0=PH0-OSC_IN +Mcu.Pin1=PH1-OSC_OUT +Mcu.Pin10=PC5 +Mcu.Pin11=PB0 +Mcu.Pin12=PB1 +Mcu.Pin13=PB2 +Mcu.Pin14=PB10 +Mcu.Pin15=PC6 +Mcu.Pin16=PC7 +Mcu.Pin17=PC8 +Mcu.Pin18=PC9 +Mcu.Pin19=PA8 +Mcu.Pin2=PA0-WKUP +Mcu.Pin20=PA9 +Mcu.Pin21=PA10 +Mcu.Pin22=PA11 +Mcu.Pin23=PA12 +Mcu.Pin24=PA13 +Mcu.Pin25=PA14 +Mcu.Pin26=PA15 +Mcu.Pin27=PC12 +Mcu.Pin28=PD2 +Mcu.Pin29=PB3 +Mcu.Pin3=PA1 +Mcu.Pin30=PB4 +Mcu.Pin31=PB6 +Mcu.Pin32=PB7 +Mcu.Pin33=VP_SYS_VS_Systick +Mcu.Pin34=VP_USB_DEVICE_VS_USB_DEVICE_HID_FS +Mcu.Pin4=PA2 +Mcu.Pin5=PA3 +Mcu.Pin6=PA5 +Mcu.Pin7=PA6 +Mcu.Pin8=PA7 +Mcu.Pin9=PC4 +Mcu.PinsNb=35 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F446RETx +MxCube.Version=6.15.0 +MxDb.Version=DB.6.0.150 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DMA1_Stream0_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA1_Stream2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA1_Stream4_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA1_Stream5_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA1_Stream6_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA1_Stream7_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA2_Stream2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA2_Stream7_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.UART4_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.UART5_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA0-WKUP.Mode=Asynchronous +PA0-WKUP.Signal=UART4_TX +PA1.Mode=Asynchronous +PA1.Signal=UART4_RX +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA11.Mode=Device_Only +PA11.Signal=USB_OTG_FS_DM +PA12.Mode=Device_Only +PA12.Signal=USB_OTG_FS_DP +PA13.Mode=JTAG_5_pins +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=JTAG_5_pins +PA14.Signal=SYS_JTCK-SWCLK +PA15.Mode=JTAG_5_pins +PA15.Signal=SYS_JTDI +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX +PA5.Signal=S_TIM2_CH1_ETR +PA6.Signal=S_TIM3_CH1 +PA7.Signal=S_TIM3_CH2 +PA8.Locked=true +PA8.Signal=GPIO_Output +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB0.GPIOParameters=GPIO_PuPd +PB0.GPIO_PuPd=GPIO_PULLDOWN +PB0.Locked=true +PB0.Signal=GPIO_Input +PB1.GPIOParameters=GPIO_PuPd +PB1.GPIO_PuPd=GPIO_PULLDOWN +PB1.Locked=true +PB1.Signal=GPIO_Input +PB10.GPIOParameters=GPIO_PuPd +PB10.GPIO_PuPd=GPIO_PULLDOWN +PB10.Locked=true +PB10.Signal=GPIO_Input +PB2.GPIOParameters=GPIO_PuPd +PB2.GPIO_PuPd=GPIO_PULLDOWN +PB2.Locked=true +PB2.Signal=GPIO_Input +PB3.Mode=JTAG_5_pins +PB3.Signal=SYS_JTDO-SWO +PB4.Mode=JTAG_5_pins +PB4.Signal=SYS_JTRST +PB6.Mode=I2C +PB6.Signal=I2C1_SCL +PB7.Mode=I2C +PB7.Signal=I2C1_SDA +PC12.Mode=Asynchronous +PC12.Signal=UART5_TX +PC4.GPIOParameters=GPIO_PuPd +PC4.GPIO_PuPd=GPIO_PULLDOWN +PC4.Locked=true +PC4.Signal=GPIO_Input +PC5.GPIOParameters=GPIO_PuPd +PC5.GPIO_PuPd=GPIO_PULLDOWN +PC5.Locked=true +PC5.Signal=GPIO_Input +PC6.Locked=true +PC6.Signal=GPIO_Output +PC7.Locked=true +PC7.Signal=GPIO_Output +PC8.Locked=true +PC8.Signal=GPIO_Output +PC9.Locked=true +PC9.Signal=GPIO_Output +PD2.Mode=Asynchronous +PD2.Signal=UART5_RX +PH0-OSC_IN.Mode=HSE-External-Oscillator +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Mode=HSE-External-Oscillator +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=true +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F446RETx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.28.3 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=modularkbd.ioc +ProjectManager.ProjectName=modularkbd +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_TIM2_Init-TIM2-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_UART4_Init-UART4-false-HAL-true,7-MX_UART5_Init-UART5-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,9-MX_USART2_UART_Init-USART2-false-HAL-true,10-MX_I2C1_Init-I2C1-false-HAL-true,11-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false +RCC.AHBCLKDivider=RCC_SYSCLK_DIV2 +RCC.AHBFreq_Value=48000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV2 +RCC.APB1Freq_Value=24000000 +RCC.APB1TimFreq_Value=48000000 +RCC.APB2Freq_Value=48000000 +RCC.APB2TimFreq_Value=48000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=48000000 +RCC.FCLKCortexFreq_Value=48000000 +RCC.FMPI2C1Freq_Value=24000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=48000000 +RCC.HSE_VALUE=8000000 +RCC.I2S1Freq_Value=48000000 +RCC.I2S2Freq_Value=48000000 +RCC.IPParameters=AHBCLKDivider,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,FCLKCortexFreq_Value,FMPI2C1Freq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,I2S1Freq_Value,I2S2Freq_Value,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLRCLKFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIoutputFreq_Value,PWRFreq_Value,SAIAFreq_Value,SAIBFreq_Value,SDIOFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USBFreq_Value,VCOI2SInputFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIInputFreq_Value,VCOSAIOutputFreq_Value +RCC.MCO2PinFreq_Value=96000000 +RCC.PLLCLKFreq_Value=96000000 +RCC.PLLI2SPCLKFreq_Value=48000000 +RCC.PLLI2SQCLKFreq_Value=48000000 +RCC.PLLI2SRCLKFreq_Value=48000000 +RCC.PLLI2SoutputFreq_Value=48000000 +RCC.PLLM=4 +RCC.PLLN=96 +RCC.PLLQ=4 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLRCLKFreq_Value=96000000 +RCC.PLLSAIPCLKFreq_Value=48000000 +RCC.PLLSAIQCLKFreq_Value=48000000 +RCC.PLLSAIoutputFreq_Value=48000000 +RCC.PWRFreq_Value=96000000 +RCC.SAIAFreq_Value=48000000 +RCC.SAIBFreq_Value=48000000 +RCC.SDIOFreq_Value=48000000 +RCC.SPDIFRXFreq_Value=96000000 +RCC.SYSCLKFreq_VALUE=96000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.USBFreq_Value=48000000 +RCC.VCOI2SInputFreq_Value=500000 +RCC.VCOI2SOutputFreq_Value=96000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=192000000 +RCC.VCOSAIInputFreq_Value=500000 +RCC.VCOSAIOutputFreq_Value=96000000 +SH.S_TIM2_CH1_ETR.0=TIM2_CH1,Forced Output1 CH1 +SH.S_TIM2_CH1_ETR.ConfNb=1 +SH.S_TIM3_CH1.0=TIM3_CH1,Encoder_Interface +SH.S_TIM3_CH1.ConfNb=1 +SH.S_TIM3_CH2.0=TIM3_CH2,Encoder_Interface +SH.S_TIM3_CH2.ConfNb=1 +TIM2.Channel-Forced\ Output1\ CH1=TIM_CHANNEL_1 +TIM2.IPParameters=Channel-Forced Output1 CH1 +UART4.IPParameters=VirtualMode +UART4.VirtualMode=Asynchronous +UART5.IPParameters=VirtualMode +UART5.VirtualMode=Asynchronous +USART1.IPParameters=VirtualMode +USART1.VirtualMode=VM_ASYNC +USART2.IPParameters=VirtualMode +USART2.VirtualMode=VM_ASYNC +USB_DEVICE.CLASS_NAME_FS=HID +USB_DEVICE.IPParameters=VirtualMode-HID_FS,VirtualModeFS,CLASS_NAME_FS,PRODUCT_STRING_HID_FS,MANUFACTURER_STRING-HID_FS +USB_DEVICE.MANUFACTURER_STRING-HID_FS=Team SKBD +USB_DEVICE.PRODUCT_STRING_HID_FS=Modular Keyboard +USB_DEVICE.VirtualMode-HID_FS=Hid +USB_DEVICE.VirtualModeFS=Hid_FS +USB_OTG_FS.IPParameters=VirtualMode +USB_OTG_FS.VirtualMode=Device_Only +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_USB_DEVICE_VS_USB_DEVICE_HID_FS.Mode=HID_FS +VP_USB_DEVICE_VS_USB_DEVICE_HID_FS.Signal=USB_DEVICE_VS_USB_DEVICE_HID_FS +board=custom +isbadioc=false diff --git a/firmware/numpad/modularkbd.launch b/firmware/numpad/modularkbd.launch new file mode 100644 index 00000000..43c4791d --- /dev/null +++ b/firmware/numpad/modularkbd.launch @@ -0,0 +1,86 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/68percent/68percent-backups/68percent-2025-11-06_112926.zip b/hardware/68percent/68percent-backups/68percent-2025-11-06_112926.zip deleted file mode 100644 index a0b90c01..00000000 Binary files a/hardware/68percent/68percent-backups/68percent-2025-11-06_112926.zip and /dev/null differ diff --git a/hardware/68percent/68percent-backups/68percent-2025-11-06_114157.zip b/hardware/68percent/68percent-backups/68percent-2025-11-06_114157.zip deleted file mode 100644 index a9ed4e25..00000000 Binary files a/hardware/68percent/68percent-backups/68percent-2025-11-06_114157.zip and /dev/null differ diff --git a/hardware/68percent/68percent-backups/68percent-2025-11-06_232806.zip b/hardware/68percent/68percent-backups/68percent-2025-11-06_232806.zip deleted file mode 100644 index e290d1c7..00000000 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b/hardware/68percent/68percent-backups/68percent-2025-11-24_143509.zip differ diff --git a/hardware/68percent/68percent-backups/68percent-2025-11-25_193058.zip b/hardware/68percent/68percent-backups/68percent-2025-11-25_193058.zip new file mode 100644 index 00000000..72b288db Binary files /dev/null and b/hardware/68percent/68percent-backups/68percent-2025-11-25_193058.zip differ diff --git a/hardware/68percent/68percent-backups/68percent-2025-11-25_194435.zip b/hardware/68percent/68percent-backups/68percent-2025-11-25_194435.zip new file mode 100644 index 00000000..dc7c40e6 Binary files /dev/null and b/hardware/68percent/68percent-backups/68percent-2025-11-25_194435.zip differ diff --git a/hardware/68percent/68percent-backups/68percent.kicad_dru b/hardware/68percent/68percent-backups/68percent.kicad_dru new file mode 100644 index 00000000..07b40847 --- /dev/null +++ b/hardware/68percent/68percent-backups/68percent.kicad_dru @@ -0,0 +1,169 @@ +(version 1) +#PCBWay Custom DRC for Kicad 7 + +# ----------------------------------- Minimum trace width and spacing (PICK ONE) -------------------- + +# 2oz copper +#(rule "Minimum Trace Width and Spacing (outer layer)" +#(constraint track_width (min 0.1524mm)) +#(constraint clearance (min 0.1778mm)) +#(layer outer) +#(condition "A.Type == 'track'")) + +#(rule "Minimum Trace Width and Spacing (innner layer)" +#(constraint track_width (min 0.1524mm)) +#(constraint clearance (min 0.1778mm)) +#(layer inner) +#(condition "A.Type == 'track'")) + + +# 2-layer, 1oz copper +(rule "Minimum Trace Width and Spacing (outer layer)" +(constraint track_width (min 0.127mm)) +(constraint clearance (min 0.127mm)) +(layer outer) +(condition "A.Type == 'track'")) + +(rule "Minimum Trace Width and Spacing (inner layer)" +(constraint track_width (min 0.1mm)) +(constraint clearance (min 0.1mm)) +(layer inner) +(condition "A.Type == 'track'")) + +# 4-layer , 1oz and 0.5oz copper +#(rule "Minimum Trace Width and Spacing (outer layer)" +#(constraint track_width (min 0.09mm)) +#(constraint clearance (min 0.09mm)) +#(layer outer) +#(condition "A.Type == 'track'")) + +#(rule "Minimum Trace Width and Spacing (inner layer)" +#(constraint track_width (min 0.1mm)) +#(constraint clearance (min 0.09mm)) +#(layer inner) +#(condition "A.Type == 'track'")) + +# ------------------------------------------------------------------------------------------------------ + +# Drill/hole size - listed here to maintain order of rule application. Must not override rule set in Via hole/diameter size below. +(rule "drill hole size (mechanical)" +(constraint hole_size (min 0.15mm) (max 6.3mm))) + +# ----------------------------------- Via hole/diameter size (PICK ONE) ------------------------------------ + +# 2-layer standard +(rule "Minimum Via Diameter and Hole Size" +(constraint hole_size (min 0.3mm)) +(constraint via_diameter (min 0.5mm)) +(condition "A.Type == 'via'")) + +# 4-layer standard +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.3mm)) +#(constraint via_diameter (min 0.45mm)) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.25mm)) +#(constraint via_diameter (min 0.4mm)) +#(constraint disallow buried_via) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.2mm)) +#(constraint via_diameter (min 0.35mm)) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.15mm)) +#(constraint via_diameter (min 0.3mm)) +#(condition "A.Type == 'via'")) + +# ----------------------------------- Drill/hole size ------------------------------------ + +(rule "PTH Hole Size" +(constraint hole_size (min 0.2mm) (max 6.35mm)) +(condition "A.Type != 'Via' && A.isPlated()")) + +(rule "Minimum Non-plated Hole Size" +(constraint hole_size (min 0.5mm)) +(condition "A.Type == 'pad' && !A.isPlated()")) + +(rule "Pad Size" +(constraint hole_size (min 0.5mm)) +(constraint annular_width (min 0.25mm)) +(condition "A.Type == 'Pad' && A.isPlated()")) + +(rule "Minimum Castellated Hole Size" +(constraint hole_size (min 0.6mm)) +(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")) + +(rule "Min. Plated Slot Width" +(constraint hole_size (min 0.5mm)) +(condition "(A.Hole_Size_X != A.Hole_Size_Y) && A.isPlated()")) + +(rule "Min. Non-Plated Slot Width" +(constraint hole_size (min 0.8mm)) +(condition "(A.Hole_Size_X != A.Hole_Size_Y) && !A.isPlated()")) + +# ----------------------------------- Minimum clearance ---------------------------------- +(rule "hole to hole clearance (different nets)" +(constraint hole_to_hole (min 0.5mm)) +(condition "A.Net != B.Net")) + +(rule "via to track clearance" +(constraint hole_clearance (min 0.254mm)) +(condition "A.Type == 'via' && B.Type == 'track'")) + +(rule "via to via clearance (same nets)" +(constraint hole_to_hole (min 0.254mm)) +(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net")) + +(rule "pad to pad clearance (with hole, different nets)" +(constraint hole_to_hole (min 0.5mm)) +(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "pad to pad clearance (without hole, different nets)" +(constraint clearance (min 0.127mm)) +(condition "A.Type == 'Pad' && B.Type == 'Pad'")) + +(rule "NPTH to Track clearance" +(constraint hole_clearance (min 0.254mm)) +(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'")) + +(rule "NPTH with copper around" +(constraint hole_clearance (min 0.20mm)) +(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type != 'track'")) + +(rule "PTH to Track clearance" +(constraint hole_clearance (min 0.33mm)) +(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'")) + +(rule "Pad to Track clearance" +(constraint clearance (min 0.2mm)) +(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'")) + +# ----------------------------------- Board Outlines (PICK ONE) ------------------------------------- +#Default Routed Edge Clearance +(rule "Trace to Outline" +(constraint edge_clearance (min 0.3mm)) +(condition "A.Type == 'track'")) + +#Special Clearance for V-Score Edges +#(rule "Trace to V-Cut" +#(constraint edge_clearance (min 0.4mm)) +#(condition "A.Type == 'track'")) + +# ----------------------------------- silkscreen -------------------------- +(rule "Minimum Text" +(constraint text_thickness (min 0.15mm)) +(constraint text_height (min 0.8mm)) +(layer "?.Silkscreen")) + +(rule "Pad to Silkscreen" +(constraint silk_clearance (min 0.15mm)) +(layer outer) +(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')")) diff --git a/hardware/68percent/68percent-backups/68percent.kicad_pcb b/hardware/68percent/68percent-backups/68percent.kicad_pcb new file mode 100644 index 00000000..bf8e76e1 --- /dev/null +++ b/hardware/68percent/68percent-backups/68percent.kicad_pcb @@ -0,0 +1,177151 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A3") + (layers + (0 "F.Cu" signal) + (4 "In1.Cu" signal) + (6 "In2.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + (47 "User.5" user) + (49 "User.6" user) + (51 "User.7" user) + (53 "User.8" user) + (55 "User.9" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "prepreg") + (thickness 0.1) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "In1.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 2" + (type "core") + (thickness 1.24) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "In2.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 3" + (type "prepreg") + (thickness 0.1) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "HAL lead-free") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (grid_origin 44.85125 47.625) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "GND") + (net 2 "+3.3V") + (net 3 "+5V") + (net 4 "Net-(D3-A)") + (net 5 "Net-(D4-A)") + (net 6 "Net-(D5-A)") + (net 7 "Net-(D6-A)") + (net 8 "Net-(D7-A)") + (net 9 "Net-(D8-A)") + (net 10 "Net-(D9-A)") + (net 11 "Net-(D10-A)") + (net 12 "Net-(D11-A)") + (net 13 "Net-(D12-A)") + (net 14 "Net-(D13-A)") + (net 15 "Net-(D14-A)") + (net 16 "Net-(D15-A)") + (net 17 "Net-(D16-A)") + (net 18 "Net-(D17-A)") + (net 19 "Net-(D18-A)") + (net 20 "Net-(D19-A)") + (net 21 "Net-(D20-A)") + (net 22 "Net-(D21-A)") + (net 23 "Net-(D22-A)") + (net 24 "Net-(D23-A)") + (net 25 "Net-(D29-A)") + (net 26 "Net-(D30-A)") + (net 27 "Net-(D31-A)") + (net 28 "Net-(D32-A)") + (net 29 "Net-(D33-A)") + (net 30 "Net-(D24-A)") + (net 31 "Net-(D25-A)") + (net 32 "Net-(D26-A)") + (net 33 "Net-(D27-A)") + (net 34 "Net-(D28-A)") + (net 35 "Net-(D34-A)") + (net 36 "/COL2") + (net 37 "/COL3") + (net 38 "/COL4") + (net 39 "/COL5") + (net 40 "/COL1") + (net 41 "Net-(LED1-DOUT)") + (net 42 "/RGB_DATAIN") + (net 43 "Net-(U1-OSCIN)") + (net 44 "Net-(U1-OSCOUT)") + (net 45 "Net-(U1-VCAP)") + (net 46 "/NRST") + (net 47 "/D+") + (net 48 "/D-") + (net 49 "/ROW1") + (net 50 "/ROW2") + (net 51 "/ROW3") + (net 52 "/ROW4") + (net 53 "/ROW5") + (net 54 "Net-(D35-A)") + (net 55 "/UART_TX_EAST") + (net 56 "/UART_RX_EAST") + (net 57 "Net-(U1-VDDA)") + (net 58 "Net-(D36-A)") + (net 59 "Net-(D37-A)") + (net 60 "Net-(D38-A)") + (net 61 "Net-(D39-A)") + (net 62 "Net-(D40-A)") + (net 63 "Net-(D41-A)") + (net 64 "Net-(D42-A)") + (net 65 "Net-(D43-A)") + (net 66 "Net-(D44-A)") + (net 67 "Net-(D45-A)") + (net 68 "Net-(D46-A)") + (net 69 "Net-(D47-A)") + (net 70 "Net-(D48-A)") + (net 71 "Net-(D50-A)") + (net 72 "Net-(D51-A)") + (net 73 "Net-(D52-A)") + (net 74 "Net-(D53-A)") + (net 75 "Net-(D54-A)") + (net 76 "Net-(D55-A)") + (net 77 "Net-(D56-A)") + (net 78 "Net-(D57-A)") + (net 79 "Net-(D58-A)") + (net 80 "/UART_TX_NORTH") + (net 81 "/UART_RX_NORTH") + (net 82 "Net-(USB1-CC2)") + (net 83 "Net-(USB1-CC1)") + (net 84 "Net-(U1-PA11)") + (net 85 "Net-(U1-PA12)") + (net 86 "Net-(U1-BOOT)") + (net 87 "/JTCLK") + (net 88 "Net-(J1-Pin_2)") + (net 89 "/JTMS") + (net 90 "Net-(J1-Pin_4)") + (net 91 "Net-(J1-Pin_5)") + (net 92 "Net-(J1-Pin_6)") + (net 93 "/SWO") + (net 94 "/UART_TX_SOUTH") + (net 95 "/UART_RX_SOUTH") + (net 96 "unconnected-(U1-PB12-Pad33)") + (net 97 "AGND") + (net 98 "Net-(D59-A)") + (net 99 "/UART_TX_WEST") + (net 100 "unconnected-(U1-PC14-Pad3)") + (net 101 "unconnected-(U1-PC15-Pad4)") + (net 102 "Net-(D60-A)") + (net 103 "Net-(D61-A)") + (net 104 "Net-(D62-A)") + (net 105 "unconnected-(U1-PC1-Pad9)") + (net 106 "unconnected-(U1-PC3-Pad11)") + (net 107 "Net-(D64-A)") + (net 108 "unconnected-(U1-PC2-Pad10)") + (net 109 "Net-(D65-A)") + (net 110 "Net-(D68-A)") + (net 111 "/UART_RX_WEST") + (net 112 "Net-(D71-A)") + (net 113 "Net-(D72-A)") + (net 114 "Net-(D73-A)") + (net 115 "unconnected-(U1-PC0-Pad8)") + (net 116 "unconnected-(U1-PC13-Pad2)") + (net 117 "Net-(D2-A)") + (net 118 "unconnected-(USB1-SBU2-Pad3)") + (net 119 "unconnected-(USB1-SBU1-Pad9)") + (net 120 "unconnected-(U1-PB8-Pad61)") + (net 121 "unconnected-(U1-PB9-Pad62)") + (net 122 "Net-(D74-A)") + (net 123 "Net-(D75-A)") + (net 124 "Net-(D76-A)") + (net 125 "/COL12") + (net 126 "/COL9") + (net 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"vias": 1.0, + "zones": 0.1599999964237213 + }, + "selection_filter": { + "dimensions": true, + "footprints": true, + "graphics": true, + "keepouts": true, + "lockedItems": false, + "otherItems": true, + "pads": true, + "text": true, + "tracks": true, + "vias": true, + "zones": true + }, + "visible_items": [ + "vias", + "footprint_text", + "footprint_anchors", + "ratsnest", + "grid", + "footprints_front", + "footprints_back", + "footprint_values", + "footprint_references", + "tracks", + "drc_errors", + "drawing_sheet", + "bitmaps", + "pads", + "zones", + "drc_warnings", + "drc_exclusions", + "locked_item_shadows", + "conflict_shadows", + "shapes" + ], + "visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff", + "zone_display_mode": 0 + }, + "git": { + "repo_type": "", + "repo_username": "", + "ssh_key": "" + }, + "meta": { + "filename": "_autosave-numpad.kicad_prl", + "version": 5 + }, + "net_inspector_panel": { + "col_hidden": [ + false, + false, + false, + false, + false, + false, + false, + false, + false, + false + ], + "col_order": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9 + ], + "col_widths": [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 + ], + "custom_group_rules": [], + "expanded_rows": [], + "filter_by_net_name": true, + "filter_by_netclass": true, + "filter_text": "", + "group_by_constraint": false, + "group_by_netclass": false, + "show_unconnected_nets": false, + "show_zero_pad_nets": false, + "sort_ascending": true, + "sorting_column": 0 + }, + "open_jobsets": [], + "project": { + "files": [] + }, + "schematic": { + "selection_filter": { + "graphics": true, + "images": true, + "labels": true, + "lockedItems": false, + "otherItems": true, + "pins": true, + "symbols": true, + "text": true, + "wires": true + } + } +} diff --git a/hardware/68percent/68percent-backups/_autosave-powfilt.kicad_sch b/hardware/68percent/68percent-backups/_autosave-powfilt.kicad_sch new file mode 100644 index 00000000..4a2c33c5 --- /dev/null +++ b/hardware/68percent/68percent-backups/_autosave-powfilt.kicad_sch @@ -0,0 +1,8 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "0555e65a-78c9-4198-a94d-afc4eb14f658") + (paper "A4") + (lib_symbols) +) diff --git a/hardware/68percent/68percent-backups/_autosave-rgb.kicad_sch b/hardware/68percent/68percent-backups/_autosave-rgb.kicad_sch new file mode 100644 index 00000000..43242877 --- /dev/null +++ b/hardware/68percent/68percent-backups/_autosave-rgb.kicad_sch @@ -0,0 +1,8 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "b20b0154-0369-4bd1-a7a4-7485a0c59449") + (paper "A4") + (lib_symbols) +) diff --git a/hardware/68percent/68percent-backups/clock.kicad_sch b/hardware/68percent/68percent-backups/clock.kicad_sch new file mode 100644 index 00000000..bae81435 --- /dev/null +++ b/hardware/68percent/68percent-backups/clock.kicad_sch @@ -0,0 +1,41 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "bd7a78ae-d57e-4c8d-8079-f4714c8f1856") + (paper "A4") + (lib_symbols) + (text "24MHz external clock. \n\nOutput\nOSC_OUT\nOSC_IN" + (exclude_from_sim no) + (at 128.27 99.568 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "0b078972-8867-4a81-bdfc-f286a00b7261") + ) + (hierarchical_label "OSC_OUT" + (shape input) + (at 186.69 76.2 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "fccd57b1-b731-4457-b9bb-32fe414af52c") + ) + (hierarchical_label "OSC_IN" + (shape input) + (at 186.69 83.82 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "fe808684-ead0-47da-b31a-21623b281a81") + ) +) diff --git a/hardware/68percent/68percent-backups/fp-lib-table b/hardware/68percent/68percent-backups/fp-lib-table new file mode 100644 index 00000000..1e1505fb --- /dev/null +++ b/hardware/68percent/68percent-backups/fp-lib-table @@ -0,0 +1,8 @@ +(fp_lib_table + (version 7) + (lib (name "footprints")(type "KiCad")(uri "/home/ukim/Projects/mskbd/hardware/footprint/stm32f446re/footprints.pretty")(options "")(descr "")) + (lib (name "Package_QFP.3dshapes")(type "KiCad")(uri "/home/ukim/Projects/mskbd/hardware/footprint/Package_QFP.3dshapes")(options "")(descr "")) + (lib (name "Type-C.pretty-master")(type "KiCad")(uri "/home/ukim/Projects/modular-kbd/hardware/Type-C.pretty-master")(options "")(descr "")) + (lib (name "kicad-footprints-master")(type "KiCad")(uri "/home/ukim/Projects/modular-kbd/hardware/footprint/generic/kicad-footprints-master")(options "")(descr "")) + (lib (name "Connector_PinSocket_2.54mm")(type "KiCad")(uri "/home/ukim/Projects/modular-kbd/hardware/footprint/generic/kicad-footprints-master/Connector_PinSocket_2.54mm.pretty")(options "")(descr "")) +) diff --git a/hardware/68percent/68percent-backups/hummatrix.kicad_sch b/hardware/68percent/68percent-backups/hummatrix.kicad_sch new file mode 100644 index 00000000..a34898f1 --- /dev/null +++ b/hardware/68percent/68percent-backups/hummatrix.kicad_sch @@ -0,0 +1,129 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "a78709a7-612d-422d-97ca-ad2b463f3c34") + (paper "A4") + (lib_symbols) + (text "Numpad Matrix\n\nStandard numpad matrix with 4 macro buttons. \n4x6 keyboard matrix. \nUse MX-style hot swap sockets. marstlib should have them\nUse 1N4148 Diodes for each key to prevent ghosting.\nIf possible find an SMD 1N4148 Diode Package\nAdd stabilizers for the large buttons\n\nInput:\nCOL1 - COL4\n\nOutput\nROW1 - ROW6\n\n" + (exclude_from_sim no) + (at 114.046 95.504 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "1a257982-b075-487c-a45b-3e42f3d00030") + ) + (hierarchical_label "COL1" + (shape input) + (at 168.91 57.15 90) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "2489cc9d-3f3f-49f3-b5f8-fca7de0bd406") + ) + (hierarchical_label "ROW5" + (shape input) + (at 214.63 86.36 0) + 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(at 172.466 113.284 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "choc_SK6812MINI-E" + (at 172.466 115.824 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "PCM_marbastlib-choc:LED_choc_6028R" + (at 172.72 128.27 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "" + (at 172.72 128.27 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Reverse mount adressable LED (WS2812 protocol)" + (at 172.72 128.27 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "4" + (uuid "a2aad63f-1a0d-43c6-8cf6-fdb19e9fb07b") + ) + (pin "2" + (uuid "7d2f0f0f-8494-461e-af9a-768e65a33073") + ) + (pin "3" + (uuid "ed11e914-cccc-4390-b0f1-3ac097656aeb") + ) + (pin "1" + (uuid "60e01e20-ed56-4784-aeaf-dfc61b27c55c") + ) + (instances + (project "68percent" + (path "/a3d0d559-cac8-4859-ad0f-79ad0c1a1a82/0330dd45-2776-4667-9e47-eb2dbca2bb32" + (reference "LED52") + (unit 1) + ) + ) + ) + ) +) diff --git a/hardware/68percent/68percent-backups/usbpow.kicad_sch b/hardware/68percent/68percent-backups/usbpow.kicad_sch new file mode 100644 index 00000000..407ba091 --- /dev/null +++ b/hardware/68percent/68percent-backups/usbpow.kicad_sch @@ -0,0 +1,52 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "3cb9f3e3-5e6a-4c23-8d8d-52b5ae63fbaf") + (paper "A4") + (lib_symbols) + (text "USB Receptacle. Needs to be a USB C connector.\nESD Protection would be nice\nAdd a diode to prevent backflow from other 5v sources (i.e. modules)\nMake sure D+/D- are differential lines" + (exclude_from_sim no) + (at 101.346 90.932 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "b8671ba6-87fa-4960-bcc3-fbddf17f4d76") + ) + (hierarchical_label "D-" + (shape input) + (at 177.8 72.39 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "5cbd4a5a-ac39-4a2d-a0ad-0c3ce3f9d635") + ) + (hierarchical_label "D+" + (shape input) + (at 177.8 67.31 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "80d42395-23c2-4264-878d-42f2e81a4374") + ) + (hierarchical_label "5v" + (shape input) + (at 177.8 78.74 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "b70746ac-3765-45c4-a69a-b93b10cc6628") + ) +) diff --git a/hardware/68percent/68percent.kicad_prl b/hardware/68percent/68percent.kicad_prl index 9b7e039f..8b71b979 100644 --- a/hardware/68percent/68percent.kicad_prl +++ b/hardware/68percent/68percent.kicad_prl @@ -92,18 +92,18 @@ 11 ], "col_widths": [ - 10, - 10, - 10, - 10, - 10, - 10, - 10, - 10, - 10, - 10, - 10, - 165 + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 ], "custom_group_rules": [], "expanded_rows": [], diff --git a/hardware/68percent/68percent.kicad_sch b/hardware/68percent/68percent.kicad_sch index 8d307b4b..09c84159 100644 --- a/hardware/68percent/68percent.kicad_sch +++ b/hardware/68percent/68percent.kicad_sch @@ -1,12349 +1,12349 @@ -(kicad_sch - (version 20250114) - (generator "eeschema") - (generator_version "9.0") - (uuid "a3d0d559-cac8-4859-ad0f-79ad0c1a1a82") - (paper "A4") - (lib_symbols - (symbol "PCM_4ms_Connector:Conn_01x04" - (pin_names - (offset 1.016) - (hide yes) - ) - (exclude_from_sim no) - (in_bom yes) - (on_board yes) - (property "Reference" "J" - (at 0 5.08 0) - (effects - (font - (size 1.27 1.27) - ) - ) - ) - (property "Value" "Conn_01x04" - (at 0 -7.62 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1tMDDdFNrDFOMfK8LtU+KK5gLgrDLhMtBHqzj8Yfj5AIUbyLqHjI0kKfr9TKrRqFUmx2qorrV0F1SCK5Kd8brGKQqer71cbWqNhqLvLptiaeK6Kb97Tbq5ieqmr5V3EJjw9OKmTOseLyaW9mCBLKaYb9rubTUQlBT4jGbEspKrTOB0bytDyUKqaZqNAkgqLvUdbfUzqs9haQS9KXjOqmKta7shizK9RiqrKFbHp6D1T7KtSnLdrfrwcXrKFa0EZ60FahC2iAr4qgqSLJb7qDIIp2UgbCafLR0eKnLRDNDaztCBysjEpCRkzJBHIwR1AcrvC5h07fhM7zztBEplrzbBMsyAV07KE8yhE0pbD6qVrftblmywgG6xMm6K7QjU7q7DIQgWqs6w8zd8JTAa7igxqh7bDSqure6ilsF/DZyRtS6SqGqF6TIl6ZBX0873b9SGwBA0kjqs79FxxTr/bWjharqj51aMMLail07xxzz26Hk9FryHaPqHKK5vrk7HTq6c5D6ljs7t6fzz7fKkdMEIavkpSOaZS04H6KYRs2YJ9msUb364K9VAzAszbd7MTx6ML26mcHJCSHahaLrN84qybiKNaw607bIJ68UG6806o3qbjSHlacBWaRUQ7qG7q07+7RKs7CHiySHAT2HeLAKxaKScH3UW6B6GG+AmGY6mabLwG/NZLBUb71MaGAUFExNvbj7aBX7DbfTVHgTSbI1oGJbeGdGe40ltsS7T77bri18nbjaXbAztSZiYHf757ug9GqFkHjIvLnHorzqxHE8g65KQTpGXDbH26t7c6lHSc46LqE74qk7u7QzyrjoIzaoMqKpMCtqjEGrcmyhozIpiry7dqq6ikcynpNt1ZqA6rhGVqVhZBShB6YYmn2rslqnsmRo2mLp5Voiao2r2ztB6njSKoZAJqf7+yUqGzqAOnZyKmTry6SNSzlmN5lTE0d7vGlzwzbIymljVmlqEpDbhCzax9NGRdYHwymZ5AnqKoFHlS36QnYL477zAzv7MnOaAVxw/sMo2YdnsqQH3nQb1VIHEVLHobrHamHmQV1YCVkb2s0GeLVavlMa5mlLsySl6m8VxlHscKRHmayGTbCKRasbMS6m2VGm5bmGaLkSoWuH2arG/milBmOmCWtAiWOrES2H/zusJGKXxbYX2XjpOWeaKpqB6bPTwXlHbV1G1aKaxW7nXL9Ya1nn9bNLtyxSSaJTCKobQ64WJXxpNozLTm01rKGD81P7AcdTfm1XFmNX9GYZkW/b5XG8wbMEr62avG2WnWOWzWCXCntIzqUmxG0momMm+nuqtbn0VgWdrdyYCjOcGq0rE3ed+cS4z1/ZY256ct71W7xQwDuktdhqGJdBv1S3bly3JqamctK3Vc2obcFA7d03cti345W3TcZ7Mz+n1sAkI8+0+cCVGIhcO24lh3/cU2Oden9mcWtbtNE2a8x2Y9QGwnBWxlImDyVXjXxXws4ajJxNS3pMw20XUmvnW8fmYnw7l2I8a9Z24Z69dWwHm8Lt9KA2fGcsj3VL+8mw0onJgn1iGF0H7VDWsXHXv3wsi358X9Uo22riQOATSXwnyXKGbmHdoOGNYOj9ZczEFD+XRGt35LRbg7WXVXsOP0m3Rs+cEO4sYLeViO/KhWyOybRX93A3G3UxQDj823ICSWVHz4MW8YqHb7NaKrtb8F0DT3tJ7JGPA06oTHHLzHIaYXOOqOnMccYZHt3ddJGJaCRHXGyX3Ht83aF29rw7axaoZO+cWJAPCPX232qVfWWX/XKODmeqcdh3ZC2rCcFPknlO1CKHWEY2LOG2Rp97WZi6dngHinm7sUlVCqKnT6qnwuB2zB07PE666XO6Wn87MRftAg27pXG78v82Fn768WSu3Xp6GqsuV0pnauxM+3K6MvzDzURyUuy7qk17OuVmklc7trWvtH76lklUTmwqeutz4cL6yHXPOjsXLPaHN0n6tXHJXrUbI2r2piS8qWZHxu1z1ZBvgaLmN9mWbN1OeGD3qx07KAIKkXN1oKtuSORPSZIPb2VvsuKKKpn0iH6BGXjbVPtUxOtGTXIuJxvuCX1kGbPXuKLrOGqt3ONPPO+6JmBH0qkgiGBbP8BWWO0thX2OpGLPfqivHIZaumkg9s5XkOiahOK43vFtMPDjlu0e7Z3KdPDGDaN2jayXgfoXP2PPF3fGslTL1YpurWjO1S3HbXXbWCoPUeqvZAI9XXRnmtgOtKm1A6RDyPkfruuORpsFPFjuc7z3PXlDYrw1o3gyFfkrpqKrLIUZ8mpB3NtIgk4NHfcVozbk/DqqRusm42KrlZBAKEPCeWUZ8uSMXtirtqw+mwI+OqKv7ewN4oEpY+YSYtfV5aVr2NAoQ/TwPDM/Jp/e6zA+U/xofvVZffNs4MxpdJK/oc3f359uwdTpNBSiYSmdAhcUoD6ftVmFt9meqSZrYYNAKRf1GIVljH5MZEAsulsGSfsa2/pBmGPDXf5VAeLqLvyAKOUfheU+8+WoqFdV2MbOkmdyyWAErmKXQfbnNP3YLYvZojkNlSvUXv8fj4Ji7XEUvE9fxPRuD+EOTqB4Rma+oQg1rJlolUDL1wW+91VPklDxQn8s+XhTXs5xB7b8E8s8fmJ9xmrwD4EZoOGCDUU4RsSOJ8PjBPGQr/9weq8P7AvhhJh4S4I2Q2t6zwRX8a4X1Xfvr3v5LQwQXvNmD73FBspN+aHBRK7Vn5LcPaiQOqBQiEQv8jM8gJJrcQ/7fQDWUTNgbANSp19NAcCNfoTCb7CCSO+CDBq3gSot4k+oGaGL6nj7Ds3MukeyEHhz5WDlSNg1jHZFzYl8U6lXFPs+hLjS5WM6VBXLX0bDNRm2/gjYIEPrbtd/IwQoYmrmQwBCFCUfFGEkF8FW58QtYcIQoXMHYYpwk4adq4OcFe5HBDEAKG7n0x2C52Hg7gexkGqlC9MBGQoUQMbyXN2BclIfi5VwHaZv0WeSTKUDN608yUH9B8ntwkHY0jMhMOobYLGh14zuwtDAUay4GK8U+XQv9uUIbCeZ3+pjGSsYOIIfdF+mJdjD4Lg5QZgg4QpDkR1Q4kdyGVvP+Lfyw5LDLBRwo/GaDnCOdBazHLYaR2pzcMqBN3duDEN47IZXhqLOHnj0+GUsPGHHRYfv0sEAjaOLw8IQJ1BEzZ0WSrS/O0NApwCJwkUbgk9m0B9C3hopINDpRuFqdBee/VnkH1rCUAqCBQmkQF0drS8TOsvDxuZy/YPClY2I7SLZ2hzrBYczAlod8M4G/CDeSsakT53xwVD2c4bILv6Xl6J0be2QsCuChmwbpgoSUYzCRlybaJvYv6TxC1HTLsi7eFg6sATCnDVVWM0UcxCWR7jxJgkv6K0eV3S5l8Bmto4ZicKtHjNzRk9ZDJ6MiEujqwmzOpFND1FdNeurTJZsGMlHqjhuGg/5rZDuSsZ9RLvWYfNx3bXUzB+wk8kzGBRPNf0U4J/psNYQ7cOBwosHn8LmAAtkaR9NUZSDBYDDFOLA02PMKu4ijuBEZQ9Ii3KF8lUGcPRVjsIg6tjyxoogIDpG9H4YTwUgYhsiMuHKD0OtwjEXfRyZji0kP3M0EaQZYktiSCPDAdEyzHCU3RMtZDEZAygGDlBiPL6FCLbEcizAgzeJGNg3GKDM6qIgcXJTuEs9fqpZUpJq3zFJRp++rELmSIX5GjKRprfTqjDxH6inGDYj7EyLQ6mdmCbIoXqBIGbUBvx+jDdHyQ15OdN2yghbnaT/7DjuBBIEuBRibB5oZRlvDQoqOdEFsRouTVqCXFZwlBdMmo0egxPQJR5tAqMRyMByVFoV9OCMEttnh0zttWmto+yEbn0SiSshtErwa6NkDykjcjYGScRnYljjGIp6f9qpKqHzNk+qE3gegX9wyAq2vEksks0Ykjs0gEBHavuMOaKStsq7biWeh1azc0BPrdMdfT3bQiUJpopmKeF9p6doo+2RQUMO+YjDbevkgILZEYmPtDJcMFhoITm7hMWx5Inyb9Q7EBT9GvBOyE5CaFKDPhjPRCkOLv43jKxGkoSfBwhxxZsJ7w2ceCPnFUp3xw/WphVNZgYFqpzMJ8R8I0aE9USZY0qTCMDESTPEVUldK5jPHgiLxCeK8URLKlTkRpdA2XONMSi99+x4HN8YuIk4Ss0JCUIzNQWrj7YZuRIpTiSI/bATkJn4ivszF06jtnJMMY6aw1Mp987KLIszvLxwEctdpz7F/CxFynMwBR2va/lEx+FzShpt466SXF84QEAZG7EgR/yjahcaJIEiLrd1SiH1CqDSSKLGObrozi6ttUuKvSW6ozMudDHLrLVzpd0SMsjGrh4ijKJ85J+k27vw06aZJc6xiPBpPQGpghKijMk0T4Sqgb16kliSkOs1Hrr0RyWMvZiBNJ7/0juC1VrGfXN7JSrh+E/jKMNwYThH6TzIqhoE24XttuX/YYQNPuHgyC6cso+tzLSinceekLPqUBMoFgyopBdLWQgwRrczdAz3A2a9zRGIo9hMsvemTMr46A7BxLGcduLQ789SSW0gARD1kD0NWqlAWHjBPh5iNppe4gObgxZl40xo+XC4RHKuHTSdUxPTOTI2zmJyZy3UpWj7NfG9TMxpc2Jlog56209Zrkk6bz0jmqCLGaU68WbI+K2MxeCswmdBKI7Gd4Jb0xCR9LsnUk/Gzck+rclqntymx27HXiDJNkfj9S2CV1lLPP4Gx4ZnwxGfImRnISSZGie9DqKQZb1ph8XAroCi0TO9l6vAImZFNPmLJ45ForOnwHHaR9R6yuO0e3S/knIGZKMqISYhNT9UJ8jELnO/K5mQLbJICgMX4lqTrVH5PAZ+UrmQWb0wQ18+BZdP1I3JExBjJ+SmNtlAzWhu7euXgsxKaJlkOshunVH1l9j48Cmb/spnXktSWUcNQhV4ivk2zlZ7kgCmx27kXSKRv1GhbmPdkT5HsXsphS+I2kY0Spps52W/JxQMMmcQCquQXLnFRzWOcYrFDAvkY61k5+c5eV8OgGgzBpyisBQEilZeJ1FecrimCIXH2ztUs0yxWIvAUAKjFNPC4S9LUa1zlWlC0RfgruyaSAmWVM8G3ItIdyrhjUqBj3KdliLe0EE5+ukEl7Iix5sShCRSyQnBLqFoSzVl4h5bApF50S0xRE1Xn9TCJ7ikJYmgYa8Ld5PpKidALC4IK6JfkxWpjIeRpQcZt8xMhIgsQG5n5/E3FhM3JmCCwQAym0X9lpmhIpl/o9pbeJ7i4hWZSScZt3y5lszdJxo91Jsy15FVTw6C0ensslndLpZVC7MZLnlkHLKEJC/hbhPBFqyY51AgIIsDthrddZjEN5inLCnXsIpn0nJm+W8SgonofCmCRfxSkuKBeIi9KfqVPLRREGtaPRDIp+VgcAs/si5cuTxb4N8YBKPlJNJU5dympzyisQRGxXBzBiw8RKShy0WfD05FipRZ+OWUY8Q5QCnHk9PqnOKhF5JYwQCoUl1QWVlK7PinOfFo1fZCBbyb3KsVfihmetYyNz3uUxLtFRK+JTCqlVXSJmg8m5ekpFXPSbWmpVkVPIbnKV9Yc87QFDMBmX1PJfrJ8nkt2VhV+0aURpTFWYXyj0mx8ika/LHoTgilSbPnCUCcgODb56dX1VmxMl6IJ2xM0BceHIR+CRJugCIc3V5LFwpJPHRNS/OjXJrEGLbFSQmsSGj0Y1H5PUN21zW9sFl8k6sNghWB4Y9OOgdwX11QQ1r/VYIQNWmw1kHd+kumLiXWschNCIVqs61ayBJUjiXZqCPRgdL5j9DESvy3buwo6FjdO1keZNi2pmGkK5hUKvYgkpqWayx17lXgrnSA5FiGe4qp4ooo3m4M3yyQPDj6oTXnDHFPU/CiqvpTDruBhaq9UtP0SYRCRHK2lXXKFHVLGVe9LNbR1fxfqQRuqzlcSo3Wmw3FgGrOf0kQYdSv1SIiDX4pVonqOGL6+aViXUpOQeCMgSdd+qSnEiAJpI1VY7O3W6FqAT0B7AdLrWGcMlcErJRPJyVGrMV4RXDbZ33X8FLVaYypXXAZXnqqNkuVdNDMDVEboq+84sQ6wVFQCM1iCpzFoHoAxdMCQ3G+VHwATKbymBoHroaJPmgLzYdUcZcFEJj/cd0o9BBK1Bq4mbjwXdEZVrQnBWbOmozFDRppPRlAuZLmtDPZsk6LAnIXXHTUcsWjg5/NA3dpucrtX7UZAp4a5as2m6pjwmTyyVYkuxoAJaoHyipgNW+XTrXVRs8KXOsxE9VotBJE5qprBWoCHl77TBmeo4WHt9YD3aZpKBRU5a5F6KmrfOp/aAtK+hLf7povKVxLn1yWyjftXc04rKeaC4xfesg3ojoNBE21bCoOHhQnN3LJsNjwJVQbuVrikuexq5py4MeJmibT4qm1obth8iwJXopyxvkFcVCTLUYx56yjCCT6zdWqpS2La3ldsexnFp1WjymNc47JWTVyULbhMV2jnqMyiylLiNAivcoOqR7zb1VqW97SbwuhTqnOUm4LmRvHStL9NCmt+WlHyZqi1NbExaKYgKqUw9Rum7ZVNX5lnzZAo1fMg6LM0pJJx7onbG/js18zxczOwer6JHrE7sUdO9dFdsp1eqE0vAeauTqC1IL0g4u7EYTsp1iK4aANJMfFrXV8bgZFCi7ZWiWREskMEQV+mlCPVyi8tfygrUuMrSK6gW0YtTX2pVnKDUpL24bc7m11djocxkXsaita2YMMVkWp3bTtpbpC5cYciDb+sfWAT0BQ2uDeLn53+71x1POyOtpm2babVmu6sMrj6onCkifLKbSHvD1J7AYsGoTfriMhStY9wq3xetPIFYa+5HqNKD+L10KrwVerIHk9su5brI9TifNNbWV3fb71mSv7SxoB1safdTpK2j+PcxBNeNiWmHXNpT1S67IZE+yCjrckurPmMm91XJp82ArtAPTeJtgrzpai/NO+ohWgrS5tKK1o48CQ00/l5Cf5i0O8TVw7psrhdoC+/Z0zgVeidMTXd/eWqZm3iLJI5VBZLrmCbMzSG8IBjgvl1wqEx1ywA3csb1Q6V56ujMbPsrE5iPl9CyJQbu9kIySxclG9tPPjGJoYDvC+sRVvKX26KN7e+5mCFLiIqp60i93S1rFUBLMW7Wwrf8w0lja1gKQoPSYrOkeNmpHW+iZwcr6MNtIm48OaYvpWm7tp/K6QBT24O58s9dUnPYNrz0wbttw+hsraIx5iGy9x2ivYGUEPsGvp3EjnhgYb1kGHteCHRTHDYNm7Ax40FZGZUAMjze9v2hqf9scpD6gdwlXaeYeKUet4DCBy6tPp9hw7Xt9q/Trvq2xL6TpaOo3WHsx0eqfJXq0/uxVXTMT4pba2+ekZqiZHa1PEoofJsWVxQE2j6UtjJMVwWaS4VZbNZUYPTBEOdYOWoytHqN2cmMZaxweUeLXaTGj3m5o1iLTVWSTJRRtScFtyEhAm11k1ifO2NWaDBqCapyaZIzDBHylSWoJb4bgHaZSkJ7O6cFLiM3EZ1pYgDYXrgGLGu1y6myS+2X3kHZtbeew7IaVg7H/G/7OToeuwOFSMN4+R47HKVg9GlpPqg9HepUP9bbD4jTY/DoOHJCpAayJDY0YT2iddxgm2rUrGCGBAQNQJhjoiejn3Hi5vKgg0H3ROIbS2K0hkaKrEZFSzFkUyQdiJ0BcaCNBkeTv+Ob1JHntlBs45oOs60bCj9IiATLwNXvSHWfKzkexTw2/SI4PGnnusbCMZydtuA6zqJquMTYAuFvXLWyeXBY7PVBm5dFOMKqlxwtvStzX+mjI2EEowywY9TQigfyKEpmqmRZs/T0BOmdqRnT/up17oGITp/qq2V50fp70SKJrj6ef047Vqj4+BGaYp2TsRE61A08jt6UimtM42S2RGaVlrHBRgZKvVYoeqjkLygUfXdSo+aXtjds6046icTOxZkzsZa3QlquEUGUDeVERF2OWJRZGDXFQw0BW91bGrTq5SvniVmjTjg9YJlvQT0hORH9q/p/3bacO3x6txUh5EzIb+PUd+ktivs2ttnPf4MB+J2RAmacyenbFuqac2tLRVGHMzHtKTuxldaXk7tiq6w2Y2HMPG29nJy2tXBSUNEHoiUNw+8L72eGB93h4U4Scu21BClRhcHZPoHX8b6KC5l5VpxfPWEqzhxyHQkcpxr7reG+y0/Gyp7F1s6rMffQ6efQYykGGuKpHpu1MhnKqE9fMl4j4AINb9S54FA/uotJc5j2O0ox6eCByNoiSFYavegosBNkUwZ1i6GaFnwJl6KwIA3uhPDCXd9OF+MwBfCzaYAGhF1BKmbIPpnW8p51LXDTdmpLfgjCj3UWYjjGzSzQhhjApeINsZytOEu2eobsOPmyzimg+g1qKW6RwU4Gpg5Se+NYMOT9lu9ISC4MsQkufW/g6CQ0uLaeLXBvgJVEm2gnaK854yyYe470WFDAVhxTFY3xFyC9Plxquxd0ORWLUVck7XChYNImI9T53zUkFeMGNdLUSyHUqoangmFhUJ7HBnXsaiXfgn53Hnqudq/mzsPhpq/tVrCVXnLYAiHaExlMQXk97a/andgCY4gYYzqpCyKjdWoXoCm+rXcYRU2m8jTv8+9ASWS4S9T9LF8/TTqM1X7KeeXDqkrhPCrF+qJmi68xdIuCXlcN1kZtpl9MnWPNTXUZi1zdMoF8RAWlemLOJ0lI4i2zE7rJfmPxo4aJW4FgdfOaq6p9E1odaVays0LouqyCpht2y1tn1Tn1PA/8rkup7obsW8G6sdUvnd7jjVsc77vS10HauKDNyzjc90dnfj0FlRR5pW004BzfB0jVqWMMOHu8XW6HlT2iudXptJVmy+EfrPWLlt6sP7qlbFuqHcTktrc9Leev7aYeR2uqYVapP82njUuiPKDp+DXm1jt5r6ANvZNq3bWWq7rj3q/MeHHKXh3q/+chs9o38oOxVEEbIPjWkDkF+KwLZ9wGqXqpvBa2bZhIoWkZaFs/b/tHWORM6ao7GepoLWpRqyZOkoKLPDElHjrhXWyLoCv0Oj6Z5mxaC3V9Tc6lNhdgS9nbHqGRS7FZX0WZGTvkg8yguiKJXZjv9zzVrRUMeJZw2d3XkCdiLV2b/pCh5Z3duA+TatVI3FuNJwOWCjW75its2NpkscfxtQXSVY9HOBxTJ1cjLLtx6y+dO8smXSZc9ug5hNraM3l7x5lm3ZaPujr5Ua4k8PTKCu82BDoVmRrnZxXrjK5BZpjuLYlWS25TWhpXqjAEbHioy7KySkrd0WQjNDQ94B7XYfGVyjzzNjkm/cbkjZ3KC9ywzhLDvXCD70treRicglBQarAJb847Z6v2t/b+tjrrQDhK2CFAXtnCT7fIUCa17I6ju2BAHuh3mlJgrU8ogqAQBtgLQN6O2FACwACAYwAANawAHALgMAM8E4CgAAAYmYH7YhnX8kePFLnWMIJFIeiUbRzM3zDLYeAGREMzcgSjaOfg1RxaJo4MepBrHDhUx2VXMdHtrIOjgHg1QsfuOjHTjsx09bceGPCYsoEjHY58fBO/HLjp6xtnccn0G7xOmJ0E6khnJnHs9Ku/4hd5JOQnO1nmeE+Sc1ZUnlgdoAQAcBSOiAcAPWHUFDBuAoAcQbiCAAACyHY9XkTGBS6RrZAAGVPIrQ5qDANp8gIMhdOdIwUR7AZD6eNgBndAIZ+0+PAJRxn7TyKNM6d7jg1YbTjYAmumcYn6AigNpxQl9Q8BNnVVMoPM8tyOQlnzd1ZyejEydilnvwTQK05PQjPxw0zkZ6XEYAKAzoJceyNM+tkDU+nJQXllM9PKPY7YOz8mMeARhdOmYe2eyJc4mG/AKYUL7BUEweeThcURmJF1thRf/OR7ZMTFzC4VIfPyyPQQoEi7sgmQegOLr1HonUA/PIofzj55M5edWJlSoURlzZ0Gd1NOUYL/EitAWBNOPYvgueOy4uicv80PTmqPM6ZdtM3dOLxiOi7IAdO2myzg+P045dTO2mAUhKEIBFeeI6ADTmVVtiMxSv1XSrnuCC8pdqvRX+r0sq87GdWu9XSrmVjDDedUvTXpZGyAsDrBEvyXDYJ1xFDzhSwPnumVmFwDNfXQKXPL+V0KWHDyOAAZsuH8dV3YTrWMKLtI2BwZSyapYROxgzcpOk37drEFm7ZjJBuJebnPgcioSlugkxjsvIU7a5kXi3a0FIeW9yOVvm3ub2t4nHrc91k3BIMCF4n8mtuo+7brOkO67eOwe3AfQSwpgCbjvM3ExKt4FFzoTvQYU70vjO9HfJB032T4LVu4jqdvInaTwt5o9roCgsKUgBIsM7QUFBMkLUI9+o8EunuxIIcw0GvUh5nvuAF71dzLHXeeDC3VcWqC++/dM6qewH8iT+7ch/uBo5jr+C+5KD5Pb5gHz93e8vf5uon6TuD7e4Q+7vH8YH7D2dEg+BRoPek909YspDwfCPoHij7e5A/5uKgAAITUfXBinpT8p7AEqfBwandThUI04pjkgiMasEOTiMdfNQmtJShgMJ+5GDOxPpSb8ooBDlpJw8Uz2T0Ezxwhy22kLsT2NA2qhQNPXiMuh07E8R4jMxr/Twi4oBGeqzDkY5xp8YkqevygnyTzMzWB8wrP1IeyHM5DkOQ3WpL/jwSK89KaEY+z9z7iCc8ShT+rUUL6+m2eSe/uiz4z0a7M88tpPKn8aHnHshxemwqXoz2FTU9Cf4vBz2TyEE89ZfIv6gBp/x9TQbVnP2X61+57QULBJEEoETzJ57jFcD4Un615V75DWJkoLXnL2kn6QUx+vExQb3HApfGkuvonwYqM8YDCfEoNLoz4FG5dCBWVzUNdHIGW9v5TPUsEOaUj2zihtvI2JaqEDs9bYVP3QFGCN9q8+eaofn7oEl7284hWYzURV0N9z4BEJQw7eQJZ6G9UExnEX3OkV4m92wpvKX+r0N+q/9eIferkAEhFY9lOKnoMLj7U5ED1OGnXSDrzmg0CVJmoHTrpHN8cgMBcfTGJyIM66S16bPJPzxGT8de4hEES1Gn3j4OcM+YvARUn7ijKC0u2fu3qWKT7k8hfefu35n/p2i5hu2fNnhJKT8a83OGf+2JnzL8ez3eCf5dpr4wFJ91itqqv8ifJ9F8vY3PXSVb/z9p8mfIXRv070IFJ8nfDPWPwT3WASphehSOv7Hw76N5BIygOv67zV4SoCISXXv7Z8qRp9BA0kNUBYDr4y+aBg/dPinziAbBjOEqCgcn1M+F+mfo/ofml5j75oGRifpPpP/T4JSW/RfqaVnyZPt+i+ufUXhn0EgWCi/BfvAAn6MdZf6/jw2v6v+X+t9GuU/hfkb1b9N/XfEXDPon6EEd+vopApf2oGD6Jij/suE/qn5Imt8D/LPZ4eOa687/yCCfmBTzz8k1+t/vnK/hXzv9p/1/WfmBePxr9p+V+efBG1lwv9p8l/G/k/5Inn82yx/8aOfkf/f9f/6uV/fXzLzP/H9N/QkF09i/b/0x8T6JtAADBAIAKEJOfdmFLgYAwQFr88/dqyADvfZKBf9k/IAMj9FATAPp9P1D/2n97/VAN/9e/UKE58VcCrzsgJhGz0/8e4Mf2gDqA9AL796A2f0x8DQUyCnBo/fPwp8OApAKICVKAyAQDqArslLhyA4gPx9qAmv3EDLEb/wJ8K+Xv1ADk/dgIigmvGQJj8U/H4Fv9xAvkDADWYEAmVIBAjQIJ8VwTgKMCDfegBMDUwTzzVhF/c02X8mmdXzoD2mWfysD2fIyGj8LoVwP0CycTPFF8bfQfy0C1A/wK79MfB6DMClA+nzyASlPtDwCDIMIJzptnN31kCsAquHcC3fXQNSDbGMQIv8Q/MnD9d9Av/yIDQkaTCO99A/L1wDCHHoCMxY3MAATc1ABHxKckfDjxR8vAbj3R9ePBpynFdIQlAX8YYfThiCOnboKMwlUDX36DhLfV26D2+PVxJ9+gsqBsChgtpmmCE/foKhkSlIYIJhlgsYKcNBgowS2DZgmBHk85ALoKWDv/WYOklv4RYLjhegsYIuDh4K4Pj57A84KYxWXB4I0BZ/Z4LWYG/boPeDx/Z4LWDgUB4OVIng5ICwoyAk4LmVmoZ4ImCHg/YNBD+kFZ0s8pgs4PhCAQrbymD2rZ4JP1vyB4IpghAh33YxsvdXweDS4NdCD94QzOBs8HgkPjyksQsgIeDxwBYDxxUQmIPRC2mRkM7FoQ+3wZDlfY0nhCJgiEMmUoQq9R1p7nJENODk/WYLG9iQ5EMlCRQ6XE89YQzEJFCVgTgNxD4AgkOi1LfEkJCB9nKUMqZvgzVxMgeFfUNVCkA6kLzgo/eUN09+AC0PFArQxjGxDvnboI5DmQxjEpA3nB4ILEtqfUNewlqL0JuDfQ7f3FDBiJf19Dz/N4IYCrfR0PpCfgqMP1CFQzQCBCwwlUMD8yAQUN+DpfRjHmD7nSMI+DzYSkPoAugzYJRDGMC6FO91Q/EP1DywkbyVDhQzTT59YQ0sPyoxQpsLlCAEQsMmCJQmYMqopfA51lCewkTED8uAQULhCr+TgNpc9g5sMJgJwjYNtYGwA+HrgHg90lDdZgqvBWd+wmV275jXB6mHDag+oMkBGgtj2R8ZYVHx497ATH2KUP/STy1k5AwnzedifUpG4lUg7TCn8hPW8JfDggN8Mk8lkPQII0yAm8OfCC/CqxiDAIwIEkCJiG0MAiUYbn0f9h/QCMexX6Cf3ginwyhEPR9/SCL18nw19A38GffLyE9GwLbHsDH/P/z09ghKMKADD/OsCfD2cQAJX8nvPb0Iil/IANmcbvbCK78WI9XwU9sUPfx59ahKXwQjdQhvxX9WIktgBYYIqvySQ+fMCJICt/MULAi7w/8JACAWXQGUCV/Y3wUjUgn4jTCfw0zTYD1InSNQjeI7AIfCzvQiI4iV/HAN0iiI23wICp/XSNojGAh5Fv95vciP0iYEXbzW83IuiLCokAsiL0jx/FQMm9pwJ8NUj6fL+Sn8FPAzHxD5A6wM0B3wiZkkDLQePz08Pw8KLLda/FSL0CFGD/wSiwo3gKf9SkXSPyif/SxEijNIqIK/CiMbiNp1RgqwM9gnTayOYj9Ap7y8iAoxgNjIUo1yPajWfH4F78iYbCOaicosHwIic6eQQSDgoqKKAiKfGVgfC9vNKPiCq4XwMugsorINX8/A0KLvDqNfqN0jDlTbysCKg3SJMhtIMoNmic/RiLqMY3LYDqDE3LcER92PTjzaC0fDH1lxbkMaDW9otAyEddXoxiEihJPDXC+j4gnRxPEWXWrzF0ovYGN+jgoMGOagDnHRyU87nWr2L1vomBGihRsV90BipnHRxWVKQZ71LpFnfDgRg9QaiIJQGwX7w6d8OZmCephPTxDe8KYz9TAFaoWr3oBfPemJSE5Peb0wI8NLGPAI7Gf6OCdDvMN0JjcQXpEyRgUR7D9dsYnQFxj+Y25D5daXHRx890YgGPq94Y1z2PBZYzGIpiDQKGOoiNcNdCW9gY1WDSh+YiswSgGnS/11ikYrWJ0dT+MpGtjuvWnzKhSgFGAdjvopZn81XYzJGRjBnWnxxi4YU2PWB9ojxyJjRYwagShQ3bWPZj7YtmTZQag66IPDzke6JPC3IXpymB2gl6LuwpwMoDrAlgnQGqgKY3kl89FAPOJ0ACYouPu8FPXkmzjIoC2Mz40+EuNCR84gmPrjZnST2riYXOGMWBfUTQCD8CYRiE7iKY2sHj91PXkk2gVoIeIQxRnduNF4JtSeOLgHIPT071j2IWNzt5XNWBlcV+M8Api14lGA3i44Rr1tDX0SXGCDNXJai29j4h9Gni2mMkLMRJ4j0KCYGANplb9KESeJ7ikAp+Kbiy4ruLRc240uOqgLY4IUoRShT+JbVv4nePxE10LgP/ja40DRMog/GBLhib1SqD7iO43uAgSNgY6IGigiKiz2wIE8cliMZ4+fTH4IEoDjhhsE8LUn4LYsPCchdORBIpiJnKcD0ZQE1YgAS0gZhjPd6E9hOkwQotBIJjucY8D2wZ4sJDnjeCSKCSgiExYjKgGEnoIbAVo/NFzoqE/nC6gRnFhObi4Yv7kPQ9QNRO/iLYrej0Q7IImC4T9EhGDQUZ4gePQT+cbnyxdhE3BKxilNchOTQCYYhOkS0gd4PnwiExRJLg9E4wjSRTUfuJri4YrCkMSYYcxMCS2YmzwhcdEthI8jOUKWGVdnYkbApjYydjG0FQEhYCcgRsC2N2k34MJMHjsENJEIEzvPhLhi8gQP1zjugWuj1AKYnuHHJ+QNpnoBigapKN4+CAvk3iuoRVwKSQgByCMTBiN1lKQakwmF0tpAdJMPjBkwpJRhQgG+MiIYYcZO6TfgUBOagc40lxaT0oRgGfjD0V+K3k6kqZK/iC42n0klCcaJIJjqAX2iiSNkkyBWSck4EMWSyYSkAtjAoO2Hsh4kkPzuSVklb2eTFkzZPeSkgJ5K2xjkuGMGJT6V2IuStkx5J6UXkvQWWTBknP0+TEEyr0Fc1gRiDyT0EmNW4JjwNbxKSjPMcU0AsCUBMaTpAP72GdDhOyHxSqkolOMJD0ZmFATsQBhWxTDGF6kbjyJGqAGS0UxyVzpRkwgSM83ldlKEBpk0pFmTfsRyEZTbk6FKFSLoAoi+TLk+lOCgYIvlL2SEvQyEYk1gAFPpSoE4KAqTTNaVN+w4YJFMhSlkoyEKBKvTPjtgxMFFIS9FgZUgpdNU1hIS9IeX1A2RzUngEq8tZMaBcx0kxJPe8c4GoUhSMkhyHTCqQJTnCEpU1+NggqKZ6HoSqQCCU0lVUqkF4BcY3ZK1TQ0rQCFcOU5+LeSjPFNLWBEmUBNLgBUoryzSxMOeHZCR0CPEzT9Ob8nlSBcTJPe8SIBNM5SUYctOjSs4NphBdSgWlypAGwAelChW0/pK29YITxFOIaUreNrTadGL33jfEwlPLSg01qE8THsEuGnTsqWdM2C10bdGnSFgByCE8PYeUjQVy0sfyHT+48eLDdO0pKyXjRIVFN2xWYalICTB4qkACgi0+bzHjUyEcJWgbFXEDPSLEhLwJQAoC8ydSjPSCKQDikr8OfT/0pIGLg54TYLsTQMxyHsFekwxkEQVPAjW/IWMdkOqhcUUDKVQxodZL5BmoO+NfSWoV5hDS/Pb9LRjsMsBILjX0rn3fTY0hSzyl9U75NAz14YoB7ScMyqAUBQMsqGahNU7+PQzX0zjOhiGkoslKBGM1zGXScEtKDwTX0g2M0A9vJ9ImhQMqjLcQb03uEq8Lg0aVkzz0hL26UOcIDM/TnUuGHr5S7FjPIytMwzPpMnUyry/kQgE2JkQd0vzy/kzEM1MPSQM2T3alkU5TIS88rHQGegPMorx+BlmLdOAz5M4z1zku4WzMX0/PTqN0BWYYRNXTKAULx6cYs5xK8T+0n4FCzE02lO3ixPLjPHAq021KK8os08BtT1EyrxUogPTFOCcIs9z10APMcxKPT3PfZ1iw/0/jzjj+iXzO28wvczOczgs0JESZsYcLNzoHvHmTzINMlnDXShvFd2kANM5HUn5tvbelOl2kulP49tXMXVjTQkTsj0QAUnr3SAjMTryxSTIYIAbA8mZrO6BW/dYDJSmkyzwOzTU0aguyp0g7MFjh0jpI6cHs+QTcRe0llK28Dszb2OzlXMZO+yjs4535TS4A51eyiY4zINTKQF7I9hVw0FNJdrs6tEpdI0wYiMhgpNbPAlcpIjO29kYJhNFTDU4cDcARAMYFujj3Mj1ghKPYd3FkpuAj1bdS0NBQLcycnDwFB/JDmSZzuAHliI8daQoAZzdCanIFAOchIj5zuAFnJSducjDxPchczKVZzCPZnN4EnHMXOZBk4loNPCno88KGAuguvjylm/ZrjkDc3RNBACdcrAL1zfvb8hJ8dmHgMmC6+WEzB8zcmQAsCpnaPk8R5I2rntyNcyxGKAbvQ3Mdc9c63Nz9vrXXKtzi9P3OkkA893NO8zckPOUDo+e7x99/co3MSAY8jAPNzQ8yXHsjg7C3KGCfoTsQT8dmDP3D9c+QmDSQOfXPPyD0Qn6De80/YOz6FI4gvLXRw82rjN8Hcn6DrzPc0ZioIVfAvIrydwsHWMg6YzvKLzpfUZiMgYogvOzyNfb61QDo+PmGf84873ITzH6JPOXYo82GFf5u8pfLnzKVRENtyNAjXNWA082fMGcC86fL5Dk8+PNw1SvYOz2wFwsvMeTOAiPI88a8n6Dd54/e/Kd8jMLoNOhEoQP23yM8+axcttcg/MmDLIe7Ak8vcw/OAKF5ZkNPzvcyyF9yR/EvOvyhgyyETyrfWLlKCw3P/P2dkAkFm3CyAfcJJzO0awBQAxgNgCgAUAIgGHAiC9sFMARYboAqADyYQCIKSCsgqIBqC0wBOheSXIm2ZIrbeCYAOCvwnWoKmVpMyB+CvkRWZqLPHREK/8sQu4LsvDN0iBIgI8OaDHo9OOejOg1JLaoUoknw+dfgePMWBr8yDGMh/wvQt+S1/HQpWg582sF+8NfcOF0K9XDXPH1uMIwsJB48xwvKRnC19CQjM8hiDe9yA8OEoRYI9jAYh7vHHx0K0FfsNyFBAO/Ld0XCufMoxfiPkPMLXC9inV9tC8u3x8gi0woT9/CvbCi9Mi+0MV9w4TwpC98ivKR39bCiwviD2MFSV8K0i2IsPzajMkOQCKi+PMYS088OHXgeFTPPvQSXEtmcK7Chop6L68pIvsLDhTQrML8LeplJcxiqYr6KPnSkCmKNcmZk29DC8OFxQ6o9IyQirQtYtRyiwvI1Dd//EYoaLlirQpiKBipvJOKxA7QuMK58r/gNyWi0YvGF0I+KLqLzizPKSQtqW5GuL6ipvOCT7ihxPjy/i03P6LKiy3Kyokid0BBL488aE7FmQh4qqK6+Jor8KASufK/laiqEseKfgIUjGhvi9Yrc9o+CmCcKdi0YLdyD6RQLOLQSzPKxLTPK3yOKm86kqMxaSm4oaK14H33hLLc983JK6SzPJ7geFacGcKIULalJKCi6f25Lo+EUu+K3izvJWK/C5kqbzWM5ortzOofPObyQih33DgFi/3wLz7AjANnh9CT321Ky6XUrL9XA2vLVLcSkbEhda89EuJL8S8vJlLcSiVOdDgQMosdLnij/M4Kt8ikrPysiy6G9LRiyyHF9+SsUsDK+S3APZKeSkTQph+fWeA9C/XAvNGCPA5wppFH8x5JyDvixgSuiB4G6IaDxcsj2qK/sa2Q8IQ/CFGgkkhYIRWA/omEhLLkdXsmWx7wad2TcFgA3CLKGiGVnoAD1WvgkhWyqvimMHCBso3cmy/uh7KDTIvM7L02BGA2sqyucjHLoJUtAHL/3fMsnKn+Z/hrLxynPkIhrM6cufjSyusrLwFymDxndBQLcuf5qLXcrgxjyzZGf4Ysc8rOQDy0j2wxLykcrz5ayi8q/kryuCyGTXyu8p5ywcJ8unLRyjsrLKLNQUD1ARyppiAq9yxOHvLq9AsuwpUMDwlzVi1UhxjgXLM8BxKN8B+jah1LCKB/Lb7fyFQJfnT8qitc6G40VtCrdOVEEasGCqzNNyzZDoFx/YJzjMG0H4AkQ8QYWiLlmee8CVyVC6pzUKLwm+OFS8cAzJZdHXQZgmhEYAzJdchSj1wnp3QESp6VBnWSq59QgMT1EqlKvILk8hANSsUqNXPkAFVifNSpWAlvG+MNSo/NSouh/fQSvB0GAbLLPA8XaysfixPM8FiwDnUyrrFFAAzMQZIXG+IMrVKh5D2w3PZ+NxASvWys/VpFb52UrAkMKp1pxYirxkRxwWvVsqsqT7GgCEq0PylgFKySX1dks4fNCgxPDCjcrZvHT0yqsKEyDylpnKxBsqDMkFzyl8C3MtJzdlJpnrAFGOGBLJn0Fqqp5cFSd1/KTVBuFfTcY8yQwYxPQavQ9Gq4Sg6rsAEaraqGqX9EpgBqmaoKdeq5ikmqFqonT/1hqu3MWqDiHtx4rWg1QrVzmAcAMMY/Ikn2PK7wjXEj8zqr+QurIyA3IJlsoi2GvCNqFITqimA0SOurXqvmBUDgQz3POrUgxi2er/q9KLxCbcoqgzzqA36r6KHqtSKWY//T6ohq4a8kphrKo25DTyUamaPSA1/W2jzyefU5NW8zqpplLyrA55MrzbaavNOjHgv6v8zcImVnQDPq9vOed9A0mp3DQK3vOVIrAozG/yXq4fPJj9A3gGxqHMyQJXBgohGq2ihQn32BrFo0JFECHfHGsegEoAn0hDJaiCrD8efEP3Zhc/DGpT8qoBqI19tapWqshncnGsA5w/KuC5qOfeWqmLDalmv59yaj31tCq4W2sJqBPZ33NqCal6sbzDap5OQCpanWtW0RfF6otyLY/NBGRwauQN8ILa6XwNrfCeiwvzBQAIMs9fCGkP/8E65iN8IBahPwTqOIyOo+qXq+3MLieg7msFBGalZLHEPa0CqEi4YlcWNqDQSgMLrM6/WqFrq6u6uBK/awup6TJam6qwDfCH2vIDjy1AN7qw66UEoD6qw8KiQmC0gvILKClAGoLaC2gHoKpkRguIKp61grMB2CofxHYiqNYBELN69lAehIUExEGoo/BWR3q+Cver6Qd6hQqUKHo/ar4rDqxpyrQkvbSvzRtXAnzeUOvRQAUQ5oCn30KqfBgG/rUgmLHhrGCN+r/k78xgm2cefScWvDfsTxC8K09WBo9gDILovAaP437HWAmQrb38RofF+oPo+RUl38QMq/KsMhYXffweYbA2ypBs3qnlNoCqG81Vwis4pakyqcU4iKfqaS+hu0hqgxV3YbGS+hoMgoix2qYboy/hrQRFa/xC8DGooVLmozaihpeKhUn+pT8byrfIUagGkRCQbYQNWsx9h4+53oanoVINztqogBtWADGqsm4xfsLhrdrHNFXCD9AG+n0owrq1RvsLnEdn1UqdIJLnEbsUT+r0aZGnn0Iia/ImCcaKfFSRAa7sRRoJ9vUjRp6A1aiJu309fX7A8bCG8blAiEm0yE98aFfL04bQXDF3EV4mkpFM8U/VKG98pYOxuCbxPPHFKa6AMepZ4RdJTUpcpqlSTQ8VqSn3qbKMlGAfcG3J6xYgxIMT20EUkOQgKADM31E5yYYZavjRumwZstSaQZpoGb6wSHh6AOm3twA93GnppgQe+LxwmbOqvprGrH3dJxWbBmtZtw9A7YFEGafiVYzpyxmt20pBJmiOCOa35G93rApmkZpI8dlDvSp4bmsmBqR2LQZvmbnmy5rAwVMARn3pYsODEBaZaNpr+a7opoNvqVcg6o6CBK3rzWDbKgF2PANK2nSFlkW+vhiIKvZSqkaUWsSvWRVQ1Sq3o0FMSs0qavPjNJa0WkyFKBDKreiaTw/dytK9X0twSsrEWiTypBe8ByvZbhK59FLhAAplvMqOczSXDcaWm3LvS47SwOCqFQzFpRhsW/12ua8WrFpkrBiOxhxLKW1FqBdDSP0NsqSWzVumcLoAVPyqeWB9kRdNgvUBfyqQSqEjxLPBKv0JMq4VshdD02ltUqs0osi1amMHVrvTmGZ537ijIZloYENkA52dbxW8mDdTaXO1vQa5CNKGmcyoB+MxbBsslq5zxwTyvxa0WvghEbO0hyCKqmwNVu0qw28IWqb/mgyWp5BmglGVJ2q35OOcpq8tu6q13YtsDEia6tv3oxodauAMm2strsE6239wbbbxZ9CM16wWtsraZyQZomcK2nZs6aq7OaoHaGmrtqGrS25iDnaJ2joGhaU4vPlVz4W9XN1A5OLgKkDfgoFxIg3BImH5r92rpyU0ygG3OoCahLosU85wH5BPax/IF2WKNge9ry9H2pp2/TxKBgCvaRgs5zZk0+SRB/bCUEcP28d249rfbHXEOW2dL2tCVPbMkdYSZ89299sFB7nanyYDgQiNqypXETL3erZkhpFoSo/JDsg7P1PRA/iiOzlywpD0Wv1w7g2n4lGlIMSGuKByYzJF4Aj279oUYekjmpY65Er4p8Cnk31pPoeOtWBajGQoFzic2O/QMYdI4zJC9cri/QNuRe8rbzvcqO0KH5r6LcP0yQBqMjtg7H2rpxfohuRQAfbIOrDukAcOtCXU7MO3gVs1GAeTsEFzY8moA6bOiDs5cFGVmBq8fAgWvsgmnMKjA72OyUF07QK3zqM6XOwxgM7v2nTsg7YyMY3C7t9XUIjbYybDtU6ys/3wc7rOmLqsRpMW0NS60Oppnz5g2hLtM6kultThggXKLtzYYu8EDc8E6gjsM6vyZX0s7WOwwJi64yIUttpWXF/OC7Su0LtK9Ourp1tFyutTri6+uqzpy7ukRTuG6wkMZ30CPMQAI8QvEKbv8zNsLLplq0uxjtPAEAwiE2hkiGjq6dqNGrr869QALrprmYHNHI6uugpsRgdu22ka7d2yKyY6NutCSE6/Ok/Aqrrup7um68u3bvSAJOkWvG7baC7ps7zOobra6FgDroi74gzcoMgbvEQLs7SXZcsc6/Oo0hJcGnScrecRGlqLKZLAycthdqOpZkx79XScq06g/M7o6dUeqHqtwSesntuUpYXrsJ7SO4nvB6CeqwqvUhASnv0K72g7v3aUevzXe7nOqZ2bKVnF4tp6TwXDPdB5O0kL9dmy4FGfZWe2QONCw3ZsoQ7j2iCqrY8ChOIILJ2wtwlATkD0KYB6Iq8oTIs06KFHR1I0P15l9y3tsrEje3XsrhsUFBPicAga3pN6VJJ5PN7oKy3oIgSgHRBN7+Ea2WmVSJPXt97Iofso97TAbCIyhne66D96SmJ3uDRnEe3pD68y3ZQmII+uPrt7o+lagjII+G3vj6M+g4hoqvVH3gMITemVjN6SyFiFT69e6jQChg+vCvGrByCvuN64+pUrz6NmRvpz6cQBPrr6A7T3smVjehuFN7fnIkkKssETc3fEaKplXAlOQ+SiTIxJAYXGhaoPhuYUDQYJFbwJ4VfvnKsrA5Aj7gkeXxQTjIFiquV9G2FAwFx+m+rXaIcDdox8DMgL0Cat6KBqM8uYpzz4y3619LN9jXFlvCaFq+SM/6sA19J09Tcl/vx9X08HWErlimKJAGSvcyu0xpejmsozNa4ltLoCGhTIQHdWnoI39IB+JrtzWOo7xAHMmt/pWc/Xf/scbMCXxowyPqgzLB9RPAjSe8YqqgZk8n+lZzoGyBm/sP80BiRHNjnK7HzQH6BlTwBjYGnEEUbVM7L1ddf+0Tywo5vOga/6fiRxqQzECgzNAG1YAapwHj0/gfFa7c7JoDT0vEAMoGv+ngtEHMCPQZ4MAiSgZYGaatPzf6xG+zLodw8t/rSbbQ/j0kbjnfDPudEXRwfcC0BvyMBCQs2wZmYstPzJ28LB+/tgiRqgmqAGAhgH0YAxBmT20HABwQb/68vFJq3pX+sKigHPK4Iai8Cq1AdfSRvELwKqbGzKui1WXbwbrqIGiYlcG/vA0GyGCNewdy84m5loI0rBuocUHmBmJu08SB5XmT8i2pPrgYlmesEe67msei3p+h0ukhb6+tOmGGpqwTsGH/PesGmHFmtmzHosqVpLxBZPRDyHQVwRBnzJ46Zsox1SYGzWXbFhkSsSgVoYNDWGQaTYcoBthshhxq+MW4aWqoW48OVzU4q/vULCQ94MaijBdYHq94Qj4chKIyb4e9zxgzJq+GcvZIC/kQRgEdS8ug/oMEEU2s6piwwR2Ee8ajBAxJKL+g90heKjBEBzyKMRgJrOrDIYHyGDS3LAncL+4pEdy7oi8kZ+HS3OOqtCCYVqEWdt3VrFAjsR4ZsnDS3NGuf8cyYL2+DOR0WvtDThbr2ZHMRr4tBGaR6jQV9bAqEZpGayj+KMFS7LouSAOobGsRHZRrGqzrOC4Ud/4/h3AJkQooRWq8QOybGo9gDRo1KNGA6vhsFHARw/IjwcreOrVHvcu0Z9JDCgmARVDPQd14EvSt0YM9EXT0aY75Rt0fs8hgu0dBqta9xtc9LAz0bpG9R4Z0aRnnaMbSGCRzuxKLQx1AbZGNnf0YKHkxxkf7C7R9vhfzxRp0fcaUR6keLGqaq3GxGiRi0ZZqrfBkfZHuh8Ya1pOow1LMpBmV3uGoWxm3u6CkyWvuorQ+5kdrpuxs0CLo+x3IxJHigYcaSQDe7vs178y/oJTbhxmhFb6HTFO2LLrTMcc36eh8OkurWxkAQzoxxjTS7HR0MkFHG3ex2AL6DNDWGISTxkcbL6O2cuz3Hw7A8fPGUfAcYqYbxm2j80u+nPg/HFiE8YjIacTcfrL3x5YafGU3NBRXHgtP8fAnowPPq3GErcLGpyKPdcd7HgoYftzQqKkK1KsJ+1LRTsJRfGB8LDbRjgX70K1ftSYV+yvVwr+x/CpOhzXQ1NPKDxg/u8pWKtBHYqt+e4zP7Hh5QrvrYADOM6CxMIZQk8KilGFpdBJqY1K8NSkZxez9Csf2SgNS650GdBJnCNr8FJ3ToOy0oTBtaclS2ZIOyumeEdsL6aBAL0mKXd0DxIzwdq0VcDs4KDXQrcPEjaMVfayd7y7JjXGASpnEybtgzJk+jWBI4vSbzhpwPEnu59ojSeV8uAvsyMLw/ZSaNc2XT9UUn3J2SfgadXWKfUmYsIJCj9wpobsEm9ovHD7NrM82LXRLooPzxJjIdSdshOURGGKm4pmSYigtJvpwvdMpt8k9gvi3Ke754cwa08nQgPEkCB5e6qZsmRGvEkOVIXQSb6mXJ+OUXtQc9qcaiRJqL0En9JgKZ0mJpmqaa61Jx1wKmbInNBWmlJ9zG74iphaZeyGIaTGJ9ppsSabZJJs/3Gn9pnjjOm6jRyYOmuGzqekldANzwKm2jD+IGm3Jy6fWnvXDXCA9EXQSc0nlpn6coQ/pjIT9gdnVyZK7qpjaCmnHpuBF6nnJoN0WNAOQoEbHdmwtwKmVgYNDWnwBBqgxmVUz/hoMoKnqu3GsiA7MxmmAIopxmVqMmfxnsZomfrbaJrKdpmT0dCOkAG0S4ftDc0RIDO1tULPsOH17Jmaxn0TSkFKR2Z1BCuHsKi6j5noBbmeXa9q2FvvrN2o6vn5rOkf2rctYCn3Bc6G5Uel16fE1tZH1Z1IP1nQC3/jF1nG0ASMadZs2bf9dU+EeZHXmIXzetKG5kawyq/LoX4DZg05I/NH/VGCcLDZ4CKz55R/2bf91nC/NLcpwCCIA4DZ05LJhr/CHDTzS3B2eEi7cmLT5DTZjWZ/9pJAztsDg5lPyznnZ9Oa0i0KoObyAhJM51/8YyMYI6gi56KDX9c5lQNKhYvZkaTJ/fagNrmVglcCjJzYyTpRgmunWZkzzfRwMtnf+JBFt8mmVWdmCSy7wKWYX2ysd/5xYyOJajZ5/n3nnx/dJvHntZ3/hbnxGoebtnTZtNDNrLEXua4CrZjOasD84wscLnKowOfJD95mJv0Cf0sGq3mu5whplZCu3ANXnBGkmvfnJ59ixOiJfU5OClc/X/mYy6I05LyZb5uZTYa0JHQEvmZa2mrRc+5keaFIU/Xef5Lf+d5UN8N5z4YwWgOffxnnmGz2a545fAhZEb7Z31CF9sFyEvDnY5+qNzYP5r2eFrEFk+dznz52BZx9WFh+YgWV5xhdZ9AF56poXYI5mp/nyFhBrfm9fEUZpdAQh+aAW1Z9r2eLOa7hd/nMFywP5r2FgkPgWEYVGbnHxcMCe7G5gjsa8c9Fk8YXGfx/PtD7qAz8bCgT0e8eabjFsyiv4ZxmiabHrkOJ3AmSRsxfNwg7DxfgmQJkmfjQTJScZMWbFqCb8R7F6xfflgJi3v8WKqaKEI99FkJcPHf5GxfcXEl18dPCBx5elgR9Fg+NCWpCJJCCWHFx718XollxYBaCl9xc/VbF3IyyXClsKDP8Sl93tomV/XMhQn9IHzqH6txEftME+bLitRsjmAiYtGEoYicP6s+JfvjpKJk82onzF2ifm74lqEP0gGlmycP6JEYn3jxT+vpe4mYWl4bhaMfH3jRC+ndxrkCfeCYL6cYsXiINd+dOhr0njlq5ammNsLAJ94vgnVweWxKoFGvDhp02tpcfeRMJ2dLUhWtJd9l1kLOWXLL+aBXQIwSdhwBW8bj18spjiJ+XTIkFYM4gqnOCL9xJ4yJ94zwa5fOX3Sn3ktK+G2aeOWU04FcJXHl8mAiCblrofV6GqtGbI9f0GqEpgDsvREpy79Ok0ZX8m2nJMdQ++le0SpqjyJZW+29inZXzVTlbrduVtlYpmOVwYbVFeV3prdSFhwcsLcZV+av5XpVnlllXVVxZvlmdlxWYx8EEShHS14kwJaLppi7Wl0BlRo1dLoTV4kb81h8p6lRgrVwpJhHK2F3nWSuY/xmJHKMCPBqgN491dcxnViq1RhLoM0ESrCkz1dTBXVp+ONWw18DD1AI4p+ME7rVhBDd04SBNcdXfgGEeCES4WmKjX0101azWxMSkDTXQ134GJGlkC6Fhji1wpNLX4MJ3jdwHV49jGh0QiLCJZ1gIxOklDhEIDLXyJE5B7TBqQ2xjb4MFNeDWkkZhmPBu14dfWSkM2VNtD4MWVMERc15UlGckQltasQ213NbGgkoB3Iiw61vtBDXnBV9G7WbOStZDXq1/NYmFC1oxOjWM1+uFWJk0BtcuJdAYkbDbL1tNcbXHsZ9YjX41h1ZLXTViIA0oyoKtaTWAEUoR9W31vWQ/WCwtdbMSH1+JE/X51iPDTXgUHDEVcCwpQz7XgnErxXXilNYBg3R1wxI5GSgXOQopT14DZ5Z0N3Nd/XtFi5EnqWCmernqrMOguEAGC5gFo3yCtgqXQfiXHDxFSJMSU436+JU3xAEmLoyXR+EQTfzE22InH43d1njck3nIa+q2WL+qpz4n+K9XNFQ9sOUNqMVcWsOEQNNnsK02ygHTYjo9NhP1qNopqMYjp5gmlxJ9ajMnHWDhESSE28bN9GQ/8kCq73/nnNyf3NDRUTOCzh8i2ye+CaUcWL5DchZycC25SJos832YbzY1g+SX7083rEMHzc2qyYUNs2u0wEPU3300zaYiZQjWBM2NfAzdO8P8zSv03oMNUMy3NNxzUySygYrZnDKt7BRlDjNrLYK37UxrfzQmExcNyEmpv0Y1gRsDzcyLdQ0z2S2I8bhs83NsbZxhGYczTdtXt/Ykam39N9xoEaOairdK2qo0yGo3Gywt3lCKQRouGphnHbZUkFVxcuExw1MIEnKaAYalO3JAXbf5njt6a3Yoztw7Y7Z9ts7buwjtw8uTcI6SV2u23tjtiu2LzBetu37ANjYoLl6hjcUQmNpeCXrWNlepYKONhBC7hrtp7YksHtpHeCApC7Wm+2Cy5pGytEd7HYULFCieth3p6sHbMB56i7eY3odkABB34d1+B22xxDHctT6d3SEZ3UdgHYp22LPHfO2Cd8/ueH123ZfUK8t+0IT8pMwzaO9dN4XY19RdisIl25QllqMwqQ3Tb5FkAzlvS3m1oIgSgnN65qp5XNhzaiK+iq1qW3UNjWAGo/Nq1oC3+wjWDIa+Q83d79ktwgfJDDd8rY1glqeLe13RZJLdFRYBkn1V3dgoXbl2cQBXajH/dnsOl2RvSbdF4SXH3ZoSpfObbao1a6PeAyjN5Brl3yVwPzj2RvUPf9Mp/DPeV3yA/ejdZFQ4RDCQo9j0J13PdiOlBcyYH3YCtnd1YFG2y94KDr2/CeQRr3y9s53U3JdxPfDwVnZLcz2Rd2vaQCI9/val3UV2bdl3Q9n1UJKO93rcM2d/fei2xWw0VG2cy6NvdFccQ0VFN2pd9GT93Hk0YJ92fVGqCL2rd9CJt2p93XZd2w/DAJDVp9jAti2BG/PcP35PZLe92KPQkF32LYOXexREpycJD2B9pPfF3YtskLb2e9+Mvv3ufNvZdJ7nDbcVX5x/7ZyG9ttnYQOgdh8qi0wUI8B9VLt9A6KAZmd7dQPw6F7ZwPCYRA6x2Q1PA9eaCDpA8wO/t7A7f2HrBmYNQQd+jbJ3GNwHah3r6ZeuYL2N9etx2YIXA74LwcUg/4OUdoQ+0AMdrWT4OxDhTcYPid0HZh3wdpgEh3LkKnZp2eDhHZggtZVndIPNDgQ8x2NDpIHEPaDsg+kOinVdr53L+gXYvCY1YFE5R/KnmUh8YscdnkqYEQb2/HVoXptcPVtDL2SqzoeWO5SseSbx8PKECWP7TqRBXxiq1gQWP8OWYjlqwpgxwtTcylB7ydZiY1C82ZbXJoKHe9awTZMMqs5kyAQCY1RfQpbj6i1Ol1ykG/s8ObDqRqSRoR9OmYy+Gjw8h8fVUxPMqXDpo/xirimqt9G/vBxt8CYq2OEM906V5nQa4ji7yM8fVHI7sP70tzxDUWjzyuSOVfWY/CORK3kaK8JjwI4MyNkTIexFhmoP02OiRu7m0hLWmo/aPYseEYqP2jhBkzaSjtY+CcjXbStqEE1GA7u3F0Avf1ECga7Id7aHUV1dJj4TvXIOqdDtVx9fj9oY5lCGdKklXroAE69Ut5d48hOZzFalhOITvlbsFoT0BSROQT9LzBOseZE9BOUDmHa4O5D6ndnqWDiHbYPlDjg4JPV6jjYSa4Tv46hO+CxgjpPPjkQqZPkT77Nwhq7HE9+OOTnnaJ3CT5g7mBydxespPiTwk5pP3Guk7UrOTtk8xPThVk4UTcTrE8ZPJTpU9ROTDljzMPeKlTYfqGnS8lJCKmo5ZCgXswYlFGAG9xuYYTT+vm8PfCH1dWmqoDkPNP2KQtfcnwg2vSJgIiS08aIuyL+ojHfaK7JD8La0IF8Jq8DmpsJbNERuPincxyZD9O6kpvOXfZq0+fZGo4+Kch0tMN29P4R4+LhJgpt06a7j4t3iW8bCWBdr8Cz3YyUm44FOoAamdl06tOorUrwLOVlSKcCgDTtWGzOTKc2NhJe1WxuusrRNyrHFuzkpv22XTg10MhM60KGPiZyfs7tNIzt5VP4kwk/lbPqztjHfjnjj7aVW7sRfFOFpVzc7uk5wNE5DMDTRRH5x9z3Geo0tz084eHEJ6sBsJjz8mFyy2Z7yg5nrhtDllmPGaWZ2qsrW8//ZKy04bFmmsTmfjwPz0QjfPPzxTfMPlN/iYvCQLYoAk8IiIiLEmV+6YV9P4+XSasy80oQFtPaI9yeotS4Us+GdsLl7Kw7kYD0+GcaRIi7+xcQacAiIYI4yZfoi84M7uxwIsM4eQqLq3CjPKy55zxInTWc6GTIZ7i8Sr3QY+KMgepowgNgsz78fG6xLmDK4DszxCMincL1JOXPSW1afQuavAs8IujCJAIbPu4+S8QvRhuC+7jXpo1NjMBVai4Iv1JuGtBsnTlS6UmmmIIpzRbT8i4NMSldS8lPRJl7JKhlNRi/gy6Yg020uo/Di+RnPLyMmQvlz/wjxd/LovOJ9sz4y5CuxAj+LkvMp+y6YS6wDS8svOh/M8tTNL2MjMuv63S8ynjbBi+XOJof3yMIeL9i8P1Muii4qv4zvi6GmirlM6ZgAZsSdyuqL/K94Fgr2MxkuPTh5jOyQr6MpfyoztCMBCXL8IB7POrxya8ubcqM5auQrgK46uJkqpupXx6spZGgDTB5ro5tz4xA2uxIE89FXu3UPr7M9r/6kGHjr/3GCKxhnvtMAjCTa7ZwHzlCrkgthyWdfPmq98+7j8TqxVuu9rnvDQVRZp8/FnALnimAv4qUC4ubwL7U6gv1c030YkP+kpFuQ3PWn0qlhK+G+U9sk/EjU96GgIvdiMbjlreU9sb6N5LRA2yvxvHY00/Zh6Gz2URuLgJL3oamsbX2nQ+vOm/9bnnRgicPPK3kjk8kwtm+5d6G9eBC9Gbm7zgankBWJpuLB9rYJi8+b3yxuCb32LHIa/GW9Vj5b9BtJvCbgDgpu0U2W6xj1KGxr0a/r8PwURYblhr8t/fQW5LYEm0P098zbtxvxoFXQZJ6Bab37EYFDPbBCKUTBvFjGPsESqA1vUb6m4soFborgRuiwoVIM9zb8V0h9CR7w8YItbhFIjgoBxW9E9hneQEAHVbmTzHFEj/hqoIiBkGw2PiUqI5bpc6CluGcdMeOOzLE40PqkyPmgVYLobyx5uy8rrnRbgZl2a3A6gZh5u6mrLUg6+Jm1r27lruO7+u45k+7hei7uGD2lZkYh71u45l274e4buV2p4chvVNo6oBYi6HOO0LgGrAOXuB89Us9MN7rNdOLBJpORvalkGDO2Kd7yDuPuJF8SaEGJQWujIWD7lBr/aIgIzXJD778XyaceLJILXuEQyDrDb97s+85d/1y+/Xv7C/b2fuYyk8Af7X3BfNpK4kfHw09QbGwuAfOXGZl7iT5q+43vO+7Waym36771XyYH7fRijvvLe6/uoZOmIi9wgUUuHjkB8h90aSpuhw38iHz+97yW1f+bPbVAq0ZenCBpTswfPhgqf0IlvRT1QfRS/+6fbbCIkpEeunaLWgftCxrBibQH6IpemrBppwgCFHpB7E699LEdmmyG+Kv/CmH9B8g7dH1e+Yeqq4jrEf3Cvh/CbvYqi9CLZHgR5+muS9zCaGWOsB5keZwr+eceFHsqdcDvY6R7of8V9R8CRCx/6ZL31HvRnMeMhBRag7iHuh9exWu2IktmLHje6/kEH1x5MeQuwJ5seXggR7CoXH5h5WhEC0CqDyR/AqaxXZu3yOerhpzPay6cn1R4IfmOjgK9LsHuB+SeiStR66d4nu2f0eQu2+8rGmn2jozojHyFbecNuggNofKngor07agMZ68fZugKr0ftpgp6yoPc3p9seNOjp+DKRH7zvf9gSwSYxlFa67tyfdnpR7a6MLyh+/vOXM6KflUn6+8GIMLvwraePEZC9sCunnKoehfHl5+G6uyNkoke6K7XM4eCnwM7/uWH6TtCQnn1x9pasygOBzLVrse+XJY+o8G6AnFvpXheGiQyGqWEJ2F/DIUX3GJ1o8l3vp16Tx3psMXnFzF+zIvepvusIZrPF9MBlXLeo0n0XvxZ7uAgQiMr6igcKupfte73rMopKsxYxfG7wchT6KXtl9xeklxaCz7WXnF+oQolppaZfgDdvpPGCpxKtFfbxeV7MoCp5wWleLx7ldVeEX0OWVe5XwUiFfRZEV/SXU4rKwlBsePTA2gD6TpfDlulrCeYIuJ686WUp+vHAaIYhEZZYm0K8ZYonIyKiZNiSXmhynJBXoKCPA8gfftGtUK1ZfYmxGDZZwnedhe91OVIjO+xG5A5N8xvBRuuk5cgTWm6MEQXI++GyERgJF3vC31N+UCnw32jbri78XzYe7If+rzfjQxyHfv6tUAoZG032olzfEyNN4BdYx4t5AfO++t5zJ66kOXkBWInMdQDyHpm7Lef7gDl1vp3gB5ct2fcd7ge9dDr2THiY5jqfuM3s0XZrFXCUF9n469xt5DSXfd7mOi37gidat31t/0L0Cth/zjuRmLGJrte2HAX8ARr5bYekUS2riQN759FDuR/Lt4wfE0Md+tH33kd5QTfam8sWLMkOt+1y23wD6GJFfN0YuXQH7d6VTAP9LWve+35B9qAp3gD4MeXzJgZA+5HwpmA+ARgFcmeYPiD6rJ3Hrf0HemYCiOg+10Wh9PIOIqDuxBFwt0ZuDJHnD7+qZrSJ5MkU3pD/dKZOj8n1rv30x+VG/q8T4o6CPjj+Aa5H5Ybo+vwxZ7OhJBwUdQwyn1T5NHsvCZ8FBKP/upKQNQyZ6tFCPhkYneCA3D7Q/THn9M1GsP9R8rfU633DgeIA1D8lBCHjXDPe83y0Ky6PP8I/U+GPlz8w/Lk/aJk7k71Ovk+7H9pwpvM3sAOPLC7zbK+HyP22n0/kxnUXs7LEeL7rGrPi59sJvDmL/LeMvvL84+6oluT/fkxxBm+rSvyz7s+vuyT+hrpP1554/oa7L6Bc+QTL5zHYvuODC+DPmr45Ruvot6zfWvlt+ZCARp94PrAjwUZhcQX3L8lqmYXArXP8Dsl/acjX9sY5fsXzV15fGX0l/+Z1v3R/1f8Xrl48Jpxxpa1eYlnJnJelxjca+OFpcCXXHVyTV7fGzv+iRZeVvvb+u+w+3b5fHE+2V+DfDX4cbe+EybuIle7xk78e+fvml51f8Yb8epei+iV8Ans2017z5tXv79vHS+mH8h/GKs8e+/rri1+97j+B6Ht6IHGlXtex+zZedfgDCb0E2/YQ7M9fwWUiZ9fI2SZbX6aEWccXNgDEN4WXMf0P2Ym6fo/rWWeKON9HMkfiG94mobo6rxIQgdLb6ct6NwSUnVNfK2l+mtV7D1PIIjqcV++hJORezVfmGY89NfvEkX2avfX9l/3JxY3um6p2nQYUxJi4PlJwZ9pgnp4cx6al/bCwbM98JflZxymxvWtlBzrfySfLaVeF7NN+bck+DExVQgP+wVEpxX6ixXsLX/Ik1f8OCj+vO4qZG95p3X6UmsqGzwqmZf5UjT+c6TXe9d9Eri48iI/jopcR9LlaDN/w4JP0zgKLqInSmTJAeML/gM337fwJtW0J7IK/1TXt+KLwKrenMCYUgUvc/l/KN/s/k3/f3AZ1P9H/RZAyb7/LfsP6b2dfitZOo5/6XrsmaB1v+X/bJoNz9/hM8Kbj+TJGMm+ck/sGcj+G/h37H+wpz6OqKvs2Ijz/Ff4fKhlu/qva3/t9CaHhzqLVjqOn9/kHP0va/nZ23/lrsu4a9JZpkeLS4I0D5yGBM67RaMAHh8RDzg3cH6gAxlaZ8RDwkYBAEUzGAGz3TbYgAqAGMrdAE7XbAEUzJAEYA2A7uoNYpgAwgE7XA0BkA0SCz3bVb87XVadBCRozkdi5ZUcCKlrBND+nJ6hSxa1bsA37ycAxzxOrZ6wKAIRI6OKLCuYd+qCkMaBFREQElTShDaNHD6prLgFhrQQHxrRQFsA66xCAxgB+xVgGENaDAYOTQH8AjNYS4QtY5rVQGENBiBO5ItZaA7gESHSyiYXAwFmA5b5u4P2I4RD9YS4JFDrrDxxERLtYS4EKALrW2Ls4GNo+A88iXQHRwlwAjYE+H1TBAzQFVDGdYRAiHBEMCc4SFZdZxA9wFmJeGJoRWqBxA3tZ9oRWIWTQ9YS4OtSVrUwFxA4wGWAlgEmrTHw5wHM4ANJwzhAzRBfKL6I1AuwRu6FPwqSCwEenO7rFcWJpLJZFRNAusTZtboFu8ZNC2xe7hbYWJqlAjoE2DeVDjA31CNA5wGxGbBpVAk9hWApQETONM6AbFYFsAivqSAts7WeJtaxNVIGTAk7zTAzRC+AxDYjAlDaxNM4GJAqngxeVnz2cW5BpAzoHlzbYFgbUIE2TU8CxNHuJpnJoFhA0lqxNINbYwUIFYJPxqTgPUAXQJoGiA1+L1A9oGQgqYzGQQYG4gYYGlDJpKIg3oHwxSso8NNoG4+SYFPIXYwzA8EE3Al2KG2AEHVA4oGaIb4EbA8oGrAiQFvAmBB5A0EGHApoF4gsTBXAzPQ3AgRAc1U4HsgpoFc+VEGaIJkEiA+EGLA2kFSAxIZiAikHrA4M61A0loLfKk50bUnZCnVg4c7Ck7CwTg7UnHg4M+bIEdSBC5SbLUEyEUth1rPUE1HAiay4XUGH1fUGmgqSK9sDU5z3HiYKzHU5KzRpxD1RKDIBA8z0mDQCG1ZGD7YEnzug8nzq1HbI+gkKBimJ3Ih1VrDeZEfzIYLjKCIQuqSSaxC+g/QqxwCPBhg1JJ5wX0H7bf0GF1PNLFcdMEhgz0Gx1fFC5+F/geghWLuNBYBpg4MEspUMHHxIvKhVKcwlgyeK1gjALFgzMGpnQoh8hFsFO5N+KwuDXwv8XKRTgSeKv8FqjBg0Hp15e+Ly4HcLIYWhKnoe+LlgvopAiZ9jCZSc5zgyMFMwGIgDJSc4Tg/ny6oGjSwxQcFGYYcEn8YKQXxXS6bJXMHk9OqCTxR+hjUesGtgv+phfXMFVgjQAWxdzDauHHzIYYYj3YCBJNgq3x9gsPwrJJqgRghMF5ghWKUYBsCcoYCFPg0CGraUO6QQ/sEAQ+Pi7HYCGfg25AQJcIBGuYCH09XEBoQrcHAQniSowJBKIQw8HnLBXZYxeZqw4R8ENg0DS4Q28HVgnODS9K0Kdg/MFLIdsHT+JiEKxCZzgQhfx/gvRArJMdpngkcFFkVCH7qWCHBgrCFCxFiAHg6XxAiF9p8QoiHSQnMRMhI+IsQMJA7+HcFTZZpL8QkyDngvJh4JY3BMJCCG2mC8FYxFiHsfSiGtg+iFMfXAJ+grsF6EdYBJVIyG3KS8HG4H8E6QwzYmQgWLTxW0yuIWYEyJByAUQ4MEqddjLG4fyGvoYCF3tOSEe5LyFTg3ubYQlyH0AOsEfgoSEXxFST2Q8kI8QgcGtsKyGQQksFygsU6r1QU6YgYU6U7UU6qHOYDsFfnC9xXEgreNIh8FSqGWEOkiXEbPhYkUmK/HcygXmZqH1QtqGXkcSj1QW0G0Aiw70Ai8IiAnuLZbcbC1hY/yjQgraNNCsKTQzTYsvYkLH+A9TIBWzbyAdYKX+RKBa7XIQsxJLb3+JZJ9FULYIwc0JOxRiB+bULZ2EBvweOXDYhbCY527W2KjvckKHQtUI6OE6Ju7baHDkM5yhAm6Q2bbFBrQwEIjQ+aG8CRaFhUKaE/Q8aHigC2Igw6bYpCZ6FQw/TaOaTug1bAGHwwoGFUhOaEowmTJowteBbQ18GthPaH9bSYynQjFy0+XDJCkMbaIw/gDo3V+gLbQxjP7dGGmbSSyx7P2LKjBfzNlJMi97E6Gt7DQouYbZzJJLJAghKXpEwzpJLMF3g7+ZsrvKHEKcws6HvaQYLMw/fbs7MuJJhK6EENGzaoEVzYvQutQYBc7YfQoWLjQI6HkBc7aKwo+IwlVLYyw9aFwwhmHK8XTxRxamGWwmw5DbL6Gmw7pBMwvWEQHbmGVQFZx5Qr1QttA7bo7Neh5AX2F8SLlZPfW7hrA17bknamRhwtHZBwsVYhwnwgBwx7Z+wxE4Jwn7bknOAHbfeegpw9nbYnX1DhwlUHpwwTBMHRUFFQ5UEinNUHyg7g7lQrk65w6OEiFV26BwuuF5mROE47J26+wraC2glSBFw+Q6knRQ7knFjb5QuHY8HVuHhwnHb1wkeGNwvwh5whU4uWKeH9QrU6i/Re6NOFUJQRZkYlRYkafRCRamzXXKEhOMi0PatzbwrmLb+X+YlRGEYn0YFZWzA+GxdE2azRLwrwhcEHP+cOb11VEIARVeGT5QkJoKOuY5JIEbgEevL7wo3L9BOqBOeV+EZFABHyeafyPwwIoGLU6r2zKurEjekHQIreFR5BcaEBIhZrw8EaSgBOZVQbeGLdT3KluDaBKjUtweYL1zHw7eG5dVlwEhL+FVFTka6eHOaLUa2o6zIhHG8ZuYArLoL0AQsqEfP+FAjB6CIrVeFgBHWYfwjubTRbdaqtOuZYI/+FxwF+FbzYmpWzc+HzzW946zBTpPzEPy4FVhEriA3KII8sYCIquZCIkMaSnbmpbzd94WjH1I7hLebkfC0Yn4XBF8gB2q6IuhwCRfubMRcxFcRIha6WG5zmIsUJqzG+GpjMsGB1CBF5FNhE04DnzVuSfJsIrRGoI3XJsI8cjAlThG2jWpDRzRKJ5jdaCbw05JPwthGKI4BaeI74JsIjLolzQkBYNGxHZIyBbYKYiJDLHhHzzaxFDLFeGmI+hFsI5ZAmzLNAxNC0aRI//waIgyBewnUzHjBxb0g6l6DjOpbtLdICg/DJZxwpzAdIiJYuIfb5LoEZH6Qe84DIs15DIvdDITExaxkTxarjQxhpuKPoPfQZHg/eEJ1EYJaRLd749I1JZ7I7H78vVKjXjf8YOLNJbDUR8YJLI5Gs/TAHYYGCY5LPV77Ix5EmLYpYbI2ZFbI15EOLKpbdI75H1LW5GBvNn7zI0YZtLdBHwJdCZdLTCak/eN6zLcKBx2afpDLNJBz9IdD0/DCoTLP15TLAN4zLcn5aQeiahvRZaRLHn7z9Pn4xvEjiC/Vn4DQyC6Lwppx8taBEuXbt4RrHZ4pBGd7z4HZ6ZBft7IuMGoGmAuqgPZ3I8om4IftATae5BlGAfLFzcollHYfcVG5+fIhpvQvzDFDlEQ9LfxclSVHqPEJK6lRVGhPF1qilTVGTPaQBmFEPygfeeTc1cM5PvbyaB1GwgU1MNwydL4LaFajSsfLjbDFGVjHvSZ4YmSvIGmKLBkPY1Ec+fy5GfHx5mFFnyTPPRjP+UVGmPdVG0lVVFbPA1ZBPEsrW1PT5OhbQqGohT5comVG6o6UBYrBfyyopJ6mqQopJo7J7cSE1GxolLphUfFYxlJuLuPEtEWo9rzcNdp4Fon1H2ohh7ORP56qo2tFuoncKhoiHorgAVI2FNNGOBVkZZoyLopo4p55ojTpLMXIov3ItH7PKLIxoh/JHeBOqUhO1GBDIFxaBZtFxNELzJffJ6hFRaiwRZL4JoucgP+cmpJyGVEtogmSJhRdEZ5W2j6o7IqBog578o7dFRea7pmhCNFrohvyPok1HOo6h5oSGsLqlUuYlfLtEBopdFfdNlGHFavrERQ9EVPUDGGeXdEqowDEboxp6/oqroro5oofo+7x5QruHEnBQ6KQMuFDqdUGDwquE0RZ/i2sEQoEYukhGQYjEsQcfhEYvgokYysiWoOeHz3BeG6ncFHHzfurJPf+FZUFnqsY2wjsYtjD3VDL5IIhRiyLT6oxkfEqEIkP47+QUAiYvYq0jWeb/vNjFAjQTFA1eTGH5WEZCY8GrOxFTGWIWTEu1MTBIIvIC3KDAJxff+H6Y5Gr8YrhGKSdGpmYlTGhISuYu1BKRLeBhFRWaOozzRAo6zKBJk1JZGsPNzHaY/Oo1CYRHbnamqCkZAZuY59is1MKgHeZbYgLJzF1jS0Aj5Eea2YoOqWUYkZuibkbKY7dYmYrurcY0Yq/8FlKFjHGpEMQ0Y6jAzF1jRwINInUZqYgmQaYh3JsIlTqvvKzHVYj2DiYuWqlYhzFsI0XrOYu0xalLJGhYu2pjor+YWjdzGs1TqI1oi0btYmLFAWK0o5YtwRcY3THljQbF21NLGsItcGC1auCmlfMYJYozGjFNhGJdPUZHzDIohI6bGfVOVoVVaMY9Yo7FGkTQBoY2Q6FQmgqlwkqHlwgeGVwzEDsFVEJtQ22g1kaTZvYscgY7Q4LsoajQ+IT7F/Y6uB8nRXLzwh0Fi/Z0GU/bXIN0ADZy3FtQG5GHFTQwZJxtYEpxLWHH6uBRBHokfxxLO1aWBDBrfoknw44lmH6uFui2oqix0OHupXeZ6qI4ynF0OanHV9P/pKpevJo4qaGx3B6Q++GnGJ3LnIc4hnGieej5p5FnF/9fQrdownH2otoaQfDnxxLCjz7Raw6lo0XG5tVh4xqDCie5OJbfiLTy4YFXGVIZAay4wOpxLPbBNFfw7aISXF49CAbC4tfxxLCtZFefnHP+TnFp3bnEYBW3Ek4z0y64tLJC4qnhelR3EupHOgC413GieSHjao+XHo48Y7tMCRZS4zaFEDRqbRFOJbhFSOKpHTdEO+OJbEbd/L70U4YJ+RPGFraAIp4kXHk49HGVeb/ah4+gLADHezIBPXFNkbm4hNXXEQVAopXYgU7Fw27FknFUH9wsqHPYseg8scJS06Vk5t4rxQZgIYYzhLxRngTvG5tfvHtwwnag4hjHg4mlEWvFjH35DZDn3VbjAlXPJI4it6cYs3LUWVnH7vNTE7MDVJVdPlrO5LfHE42lGR0VvKPHGd4ZQMGqL4n94Z4c/Fr4y/F46VvI34zlGHKWPIn47D5P4pPIP47D4wRGfIf40R42THPLUWZaERtFvrF5fhAFPf8KB1D8b7Q61E3+evI7MeVROtGAnH49pzUPcAmV5HZi1QA3EhyahDF5DI7MdSCJr+c3I3Sbj5f4k/Iv40R5v41ApkE5R65ItAlkEoNHqLGfHr4rjb75Ogk2o/fI/411EiLCpiR4EL5AzeUaQE1h5ixBgnB2Hszv5EuoJYipiz4kLrdTUAqSEpfEGgTfEAE5NEr8fgkeRONHvlL0oCE6ToRRAAqxTBh46E7Ao/TLwqXlTQnSSfWG1oign35JUgWEzfGsE8aAr4y/LyE8iQEErObNPCqx74swk7ol5jc1HZjyGddHeEnAnIElXySYprH35bfGWBcQkuEiqz6E+fH/+OAmiw21oKE56rxEsDEcBckpwE06HLo1MCmE8iQlfAwnkBHZj3pVDErXFnjoYqgo9wrDH3YnDEVwter4Yl3oEsJ+DkY4DJ0sZvgEQAKwNE4HHUY+oni8YHH0Y+0E6rR0F6rNBRggi/JmgEWYwFEoQSLB1bjE8AqUYawq+gqpZG5YYlDESvIOrPggOY4Ym+A45xSAH4hxldEKbEvkq2BH9bzWQA4IcI+E7E/pAb+B6RaIc4kOrU4Yd5A4lAIh1YuVPvKbEiErWQgjRJyBALXElYmTgpUoZFYYn+nXsFbVJYmTE0YkgkgMrYgsGprEw+iGjR7AjExiESDBpHwk32bP+aYmUlF1zLfDnzokpYkPAz3JrE5Uq/7Dt5NzGEn0I+EnKjQj4OrUiR4uTEkUkxcI/rKxDO+WknvEhYmXEq0rwkg1LpQiEngFJnCHE30HckoAoJsOxFjEjEnfIMmBck93EBlevTU+MkAzEh3LjIOtQyknEkwFOGgJFNiG7E1zHjIL5SjEk+gnEu/bkwcUnbgs+HcNNpFkWcZAfgENaDDa4kN8UYwHnGdzmkxATDOK0kOk/cbnNYOFfI6xquk50mekysgj3HtpzIk6A+kqczOkhNiUUIgGqgMokknJUEN47DFdAXDFPY9gonQUMmd8QUhSFF0n0CbiRpk5IZx8HvG1cE+pV8eQqj4wgrXYuvHFQ9g4PY5vGJk64n5k2H5pkyHiICCIAQgQMkBIHMlNk60mICCvog40w7j4gYkQ4mEYktbWY/QccD/wgcmfDSyDDkoEYp9VkZDkjEmOhSAq2BccmglU+F2mO2aLk/+HH1S2ZP5bah8jWoTOzSWC5FDkZZzD2YF5J+T9hQkJxYdwozk9cn4kaIpXk7+HtOCRZDk8IrEjOI7TkiRGQIrCjeXafxbk2+Hvwr8lm5EpBLk9BEJSLEZ3klTFr452ZrkhTE3k+UbKwUoAEIn4DIbcfKAUnjFIpUza61PTE8yOxE/QYZZalUtxoUgrbvmRYo6zYUj8ElCnmYi8mIwP/ITk6zG2EY8mWQXOAOYkBZgvP/K4UwrHrZbWaj8LzEjzZZ78+QMqWlfzGwIMhY/k9EYcUz4b7kyBGxnTckdQEBFtfY8lgU/zG1QL0oKU5LEwUx6EyUs8mVnZ6oSU3EbmoR8mDEbcmaUh8kX5H6C8SDvK/8OVrn41+obFCym5PfilXE02bWPB3yWQbQQejeeZCPACm8CYpEgLfyH8leymTYsSmQlQMq7FQSm8UmzaIvAhqmkmdwTjcCZSCJF5HjeOSxUx7ozI4X5bImKndjZIT3ffZHpUk8ZWCQKofI1KkZwnLALIsyg/QMZHZUtcbXbAeQFUiHADjc8nnIs7bl2bpE5U0qlNUmqlSAd8b4o3KltU7KnXI7qlXfY5HAAh5HhLCqAriP5EjUv/K58dqmXjM0kTUuviRQcanXQWKnORFKm1UuFELIqhCJAJV6Qou17QovExOva64IIBFFuvV7CnCWn4kosZboo314VkZn7TLPl7AouiZLUglE1CDcbEo1FGkok/qcTMn7dk/ol0AwYlvDBMTSCEpqKfGNZmrAVKcAkGk1rMGm0GEppLIioHgYUiTCAs1gerBBABQHYG/A+QD+rZNYrIEIGQ001YlCDQFNAut6g0gmkqAuGkk0iqx6AgBrk0m9YRYbdAmAvGndremmWAmmnnrRfpFA1mndrCPhOA2MhiYfYFzrUTBPAz1Ct0btbWtPwEKMf9CDrCLA5mXGloVf4FDrHGnRA/WCxAudYjbc4HJPZIEC0x4GTAk4ZlQbdYTOTNhf1fhClCDkblrWwFE0yqCg0rNY4gi2nw0gBC6YuYGM082Ds0v6LYxS2lQ0lNKGtKkGfOEkHmwbmk5Alw76owjaCkbWlNAotL8teDZq0m4G1QFWkdhKOl9A7dxjAgsKC0o4EUIJ9Z+0vrZSA3mkLAz9YIwZ2LBnTmkPUBXC7AqPqg04eiEg6mmJoHOn1wb9BlAl8zTA+uAabZEG1AS4GN0pEFtnUiby0q/i10yYH5xES6frB2kQgkQFnkRtJF05YGUAqpK50r2nSgiyiT0jOno04emx0jnKh0kQHlkBEEFheOmhAmOnHgGvEFQ0sl3Y8snVEx7G1ElvGohTNg6gmDCH1M+lWgnoIibdBFUxafpmgy+kY7LjY307Lh24PonbLP6l9km/rSBe/Kt0agbNAhfH6xP/rltA3KrMbpLxBAzK81YPIMpGY5VLDwlwM4O4PIemrB2ABkMDdRrn4kBniDTBl+5HWJ/9FBmwE/Bn2FHSrpE7BkxDYbyx5YhkUMsIHf47pAJDEQb/41rBtDBRge1SQm/AGXHmDbvKoxRXFpZIhl/YDAZ8MpAnVFRY5cMvikyDA3GhDHwlxOCAb6DHPIAxYAa1AmfLkMtLyUMpPIqM0rKBDbvIqM9zxJ+Qsa+EyBkk405ICjAxl/9YxnsE+hmieczoSLdhnyDe9HkhbglOqXAYpBfRlrNbhrbZFmBUUiBl/9R7wQE6hmXeXBnwFFRm70hUHdw6Mm9wxvEqHWQ40nX950sAfGMnWJmlcHvFSZDGyxkFuGJMyngD4z+lKbM8JOg7bKEpDlp8gcbxnQdw5S3IUr8eUEJSNIpmQ+SMC2HQ5ZCjGbwTCbw4cnSHx8gWhmdTXkiLecPxDeOLCSTU0bVqIbIFMnKZBEFBKe+HpmgDepnyASgCZ4g+rLHMW4BMyfjitdSjKebbwJSClplM75wVMz7yqVDZkVea7IZVQJrzM47x6MzyqXwCzzbeSplmTXtDTMkHyU0/qZBENdCx4ls7WIINwjMp1QODQKDbM+pkhCf3xDeMxAGTTpl+HfZnunepk2jdyYewK/IbTLUarTXkhPIIqaAsos7VxQI4PZM0bQ5OXDhHA7KUySK6EjDFkPMqI7fZdpmTMgzjQBb7JwszKpnMwzwPZSFl1gP5nBjYFlNdWlljHP5knM2yrLMmY6fMupkfeCCSbM55mZtIFKvobwa8sq3BDeNEYN+D7xfMnpnsjY5k+nVlly4RZz0srgJQ+HLxUsvo5Ks+ryksgO4H1eVlIspZn+3GaY4s5lpVQVY5os3pnmVflk3OAlkbHXZlos3THoNNlmWBFVmWteZlRUquzLZPSDWTKe606MSAesz67ewlcB6QfjzvfN1nes4Zx2k11mB7ENlNgT1mSQQZoysMNmFueXY9NONn1cf1lJsqNlyzMHG9kmlF65LXLNFPqLQlfXI7PfNmolQtkgYn4oa5CWkQYgJAbFRIBO5QoqLUEkrR8FvJzFYtkNFStnco1tn0lCHBVsqUqJAZtnFPbaJR5efJclTtmZ5GVjvPQdlz5ajT/kuci9s0JBIUxdE6cBzHl5AfLPo9UT7RTvKr5GMqnJPUmRlftmLoprBWlZvLLPAdmpgYLHl5LdmLoziTLbFdnvo2qLkxUfILs5YgSZCIrTs9oqjs6PLvPTtm75CODwYzCxalJ/ITsnWgNI4Pg9s0Un5oVJKZoydngFHBJ3o4DkbEiFl3szUpwk00YWo2aL9YlfJoc/TgjY2GCrsg9kCUyMpYFPwofszDnuo79mnUutnlFaDnykpO5/sqUqO8ZGB+FBtn4lZApOU/DlXE2AqHPXaTFI06Am5Mtl52D0Zt8J9n+XAjkUcih4/o6tksc/Qp4c/dGlIB4nScu9nFFQLZrguDkBFPIpCcswpaBAElvKO57aFEjkWnBR76c39lBPLTmW7McSMcxdFqc9QAhMknZhMkuExkqolxkmonw7SyCMkgUikdNMlHvaqHmqNsmuc+prmUVmC+c5NTecjznZMiC65MvVbbQrqBW4ENY9JGtaRFUZz2rEyRxc6YoJcmGnFrFLka5YIRu6IRLPElzCvxbHaxGIqJ5c/xhZc9ihU02LlJrVow5cqdb4iKrnZcwmk/rFLndFcrmprJrnw05ISeIG2mVcmNadcnDBFrdrm9crSzm0wbnxciIClCPdaXVaunJCIzCh0h1aYNEWljFeTgLrO4kfDCIrqrCrmGDcIFLcjEzBrAjQh8UenJCZbmIbA5CZ1JEIzcveIwbb9JbrTPLjc/IQhrLmqHrMYp7SE9bJcqrnp2brlvcp1Z5GGLwncr7nxc5Ibt0yjaZc9Iwvcv6I9cgHkH0Ebkn0ZrnpGYFAnsebnAhLtbpGI7KNA1bl3AzPKA83oF3EuOoUAGzlEnconhMyomH0pznH0+Haa5Cbk8bZjJSbHNmU8sbDggPjbR8MpjT9X8R30inkETVnkf0osmanHsnf07NkzciebvVePIppQXlezePL39UCJC824qTKSXli8x4okZeEYPzDElWCLmqK8jjq3wpwTZzPzqt/ScJOCY+bgdOwQZFKwQdQy7rLQQEo54Mjpm8ufJJIH+bodI3lJIJFJ44RjqBFcYRMdbbrq8koqu81ObK9KyBDsyjqUNKXkNFf3lC9OXltsi3nE9fzI1vPXKkhKbqh8rtkx8pzq+8zEpG1WLxSBWEmpckWSuuNPnEUranLzPzqbrV9leHIXpW8lkq0wjrol8+Urh8mnrpeI3k9wITHO8vIpZ5W3ke874JN8vXxtzeCkd7Mqn183K55IgvJYEbTrkgc9l7dLfIY9BRbR5fXkVdEKljsouqK8uGpXExIAFiRqIfdYpG58whaSdRkkYuaPi5kdHoi1frGL80XlWrADn41Ixr81Qkkz84EJNdJXk+lEdDudOPmRldvg9dNCSEkn9k78inr38k8l58q9qGUwjmC8u7ou864Kn8mvkRFUMIezQPmV88njl8pPkwcqvn5858l/5d5SXtf/nqcjXbt8lvlmcr0ZP86AVAFJi6j8iyQbFXjk986kDj85fjt8r8jBYtviO84TrG2CZ4UcqgV+dMfglFUgU9dZAW/7N5T184AVIFd7SKBcAVIFGurL8ivl8ClPli9D/nAFBgnX8mAof1O/Jn85EnsC68L81dPlcCzAWEdPfk0k5gUqC9iw4cuQUwdYJw8cqQWD8/1Lsk3AVg9XgQEC/gUiC0wXfVasnN87AVKCt/nV87AUf5MI7lIXgWnUk3mA9WwWnUy/m7tFSiak7uL0LdLq7s06n2C9Lqb8tXqAAmlYnI3ATUaBqmVwY77jIqfKxCwfrTUgcaJAPHQ59dPoJCtIVJCl3qrUjqkBk6Pg7IuPpB9fZG1GClDUBKmIpCgoV18SxwZC9ZGlCmIVPjXPpVCrZGTlIcaR9GD6lC/8JNCzIWI/NalbIjdFNCtH4JCwYU59avp5CmalHlSZF4RZZHBaUYUm9Ad4tCw6nxQf8YD9H4hm9In5E0auRziB1438b6lBvUaC7WAibOka1oSaVCqXU8iaM/TFG3U7FH3UxYYA7doW79RYVvU0lCsTY/rrLL6mwosfG/UwaH/UgSqSWCFYhNWCJAiKCJtOIQFuVfQporYIThNZDCoPNlzQix5bvaD2Zgit+o7g8qJtORREIBJATXLIFAG4k/hihINzdNZAb4iwha7OAppKuMsHXLE9AqDCkUbWAyYBqRArIYMB6ouGHCMtIdyqTcmAwiyEWKBD5x+JMSoxYUEXkwMgbHiElbkvZHqYSRFa8irkUpCKkVDJREVY8UkXgnIKrUiHEUpCDfy+iI4InOCoZKuciFD/e9Dai6HA6RMkXqihiCSipUVStQCGSTIkUq+TCSgi71JeFCUUfLIEVReQ0V35FEX4+DdC+UjaYIi/kWGMShptOPkVKVFUVTTFSSoi7I6Ki5cytQF1lKrMCGrDc1BF2W8SxiimZereg7+k8H6wkFaDJiqL4lkFcRxi7MWfXT8RGXPECQrJdaPncFjPnF66xKUC7MED84Fwh6kfgzMX0nOsR/nAG4AXF84kcEG5RMMG7ukn6lf034V9kuZbGVQcKemGXYqYIcUrBEcU6bMcWKNWYKQ8GlxRjMcW+NWcXtMXYIqYSX5a7bWgR4XXYqYcv6rhT2iGkkMa1JLmFScI0p5jbaIqwz2inikMazRSLb7i8rbp4qsLg4LcWe7VXHauZcUSpezY44mcUIIbaiK7L8XthScUQwwcXfig9wHi4CXthOJBS+VhGbDCCUtqGULTi2CW/ihcVWI6/KzBYXFL7HcUqDNCVMYXbyHimcIN7bWhuEGrZKoBDSl7COio5XvYkSl0jWbYRBES2dYISwcKGkXCVUSkCVBEA4qThRcUJ7BzawldEJriqwZm5K7zP7EiVREbYm9bPVwd7HcWaDASVv4bcVHivza9bfZxJhcCWMS7fTj7f8U9hMSUf+aMVkeI3zwIJbRWklTBjOaaABIeNk6Sz2nNuaZpIecyXGS9ZpXnIqnQwQyV6S6xqgtR5IWS8MnrnfMqOStyX9NfEjeSz66RkzDFKHJvHRMzUHdxJyUmS8+oWnK6C2Sj1BGShBDluaxRZwYyWFklRABSiolBSqJninUKW+Sn2AJShNBxSq3ZNk/KV6S1+q71MKXeSsLmJvPJnkPeyKSYRlEFDIxKNky/ENSyjaxfFB6ELUCBcffbynVTqUklVlQ6ROqWAfUSLxJJqX4fYaWtSwD4aRS0nlvQbif3QaWmPdIITS0x5pDDeKjGDe4qPcpDriI1Ho8F/LriM1H18RQIvCW94ifO/JmgFSb2fAaXl2ah5cbQ6XkbTAneTLfL5iP1EbSxGCSYcz5xRL4rzSmT6LSr6U5VEtGPStaXGdRIKr3aaVAytga9SxDHAyjwJnS1j4AEjqVXyVIlCgLQpnS5iKFPZvwwymImu+XNZngPIkHSmrwF2ah4KBfGXFKYwn/S3aUppYd6+RdGX/rNwmy1HtKjSkLrjS36W1on6U0y4NrLDXRr5iUeolE1KUlkuzn14iJmxk84Dxkk+mJkp8InNVjCmkJokSyoTamaJslPhcICSyhQDSykdj0rZWWVSxjF5MlWaDkjCl6zQvKcU8imazKOagFFSmE+egXUUpckM+W2Z+Uw2Xd+eFx2zESnJzXL6gU98luzZhbfkjSk+zXqHhU0uifhG+b8+U2Up9fSlpKZCLmynSlxzChDP+R2UT+SOUn5W2XHVItIuy32X4BZ2VijKCkU+M5q3k5dw1vCuYEE22VABduaEU5OWLRaizWdXAI4UxQVtzBLEVyxYoyLZIn5y6boTzC2WpBUhaVjYKlvVKhbwFfNAEcyTpa8v/KuUwfwwLTQka7aBbFzBxndyhBaPzP3LWUrBaCkYOVmUpmriLEykGUsRZRfMGrhyxRZZykOVsLZSm6yzGqJysUamyzuU+y08luBPPkF5bOJRinmUBkyxaxCpnnxU3+RzU5KlLCqIXXIOak9UlJBzUmZjEvHFH2S1PRuLDKnVU974S4DeBlUhl6lLP+V+IQJaxUj+VGLJ6n9UrKmDU+5HkEPrEZU2BUzNRKloKgal3I4gHkECpbdjR3jVLKPi1LcCawFGvp9C/IVbIkhUZUngrdI6hW5Ulakvyh6ktLVYVnbZ+U7U4PQk/fan7C5hUDLRFGnQeyEoo14XevK6lXCm6moOO6lbfA4VzLbJac/cYT3fF4U8oN4X8/DiaS2A6mvy46DfZAUBM4DmQPIbRUGHX1mgKLRXC5AxXUzXkj6K1MVQeCu56K7gA6K+rg2KwCamSmRgOK2sA7XcxUmKyxXEeXmW14/mVlk1UFH0ysnsFZbIWK1k6udE+oKy0JW/JcJUlAVk4rgfnJggLsmFwvmUYY9KV9wzKUagquHLZK0Sy5dNBLDJsA5KyJXBIRxWMnTYZSgVxUayifG6nXZywuD340GbdDuTd5blIE+BudRP7QivmCdTLehQJJSZtKnX4s4PX4TOFBryTD4r1Kl7ID4BIrm/UNxYrUZVU8T4oTKucCK1apWwlRX4kuXIrTK2J61KqMj6ENZXrCOv63NHf5jKoP4EoUjoOsgZUHFRX5CSaP4BiolAdKjG7K/cAHhpB6Z1KvX6ci9pXm/PpVKTe85l0Z/4ULUP5Si15VYCOLAvZdcIvFWeC0JP6bErFYqK/LWAn6IFW5tcfzP/WObuTFLzjKk+DHKpFUzK5v40ufJ6wqj0LN/TbzzBWFWZwQ5WF5a1qEqwoi7TLJCvxRlzS9DaadKkZUfOEx7NTOlXPKoZL/KrehQ9WFX5PfqYzMXDLWc6+XwApTTnZY+C4A3GZnEtAHx8WAE9ijRXrXQVXBIcSbngHa6yq8VUQApxVpwAqa4bZVUKq0VU3EggHUA1VWLodVVCq+VXIA0eg6FI1XkAjNm88/sU0ozKmlhceaehMoWlhJ+DP7Gbm4FA4IAcREKk9ItjthYNiGBUnpKaJ1WTgXbwo9Hor1hJGj8BL1WwgdsLBJe4KOq6NVgZNUJlC5UKEhJsiKhZIRudN3YAI1kL+qiyjywrNWDBZISkdVfbwhVNVJhGbnxhX4ZphHNUbpP4IUhS4KFqlMKEhI6F+q5ISq4dBB3wo4I5qoOL3eZ4JGwrbzJCHLIOhTagxBENWS4MNU8yYkJxqwcKYEQgKRq6qgrBO3JVqpNX1hCYjchdNUahfUIbAV4KdcquqbqvyI5qsmImhEUIew+PwHq7z6+hJdUGkgorPBP6GAhZIRQJTkLwhC6HfOVtW8RZ4KkVKkKtqwMJPqlyI5qotU7+QkLPq2lzlq/MI7w7NUga2tXuhS9U+c4tWOhe3wo9FNIVqxjBBrXmEQarMJzWKfwIaqNWDhN6zp7ddWPig6h9hOdXJqmZjBhOdWlhElqTq71U4atjCYaqdUrBcFwOq6jUMaj1XrCUdXzqsYJP3QTw5qjjVrhfWDcamEyl5PjXNq8PxHc9ArCa6tVuqjekbhbSXuobmb5k/MbyrBqhWCXQxMwJTV2S6VXVgeTV4oCLD+tQYbaa9uhqav0lWKgMkGa/SDepau6YgFTUU8XTXpUfVVZEcYQggHNx2a5TXhqHTWLbYzVeK0zVua7OAiISzXzAHzVjuPfTuSxb4AoazXua2oD+a8LVXQDFI0AzNl88qpUh+ElaF+LAJHnJtD6/C5YGmIPZmTFLWrTfGrXLLjapa20Q8iwrX2nGgwfLbyYxNS1Ggi41FlXJLUQrH6ZfzcM4krLOauBarWwrY+ob+S1GSiqSJ1RGwhi7IZVnQBRZZapwJvKi5a6oTya9/evhFa4wjcYQKZyBS8gUrSrVFnIFL+i2rULK64IFag3CsPGwgLAUkWdaoaZxwAkWK/CKYN+XbWja2eD11Gwj3TFP4BQfHyLa5EW5ais6S4LfInwY5bdyt0V4qD0UPMj5Yp9YEU4JWFZ25WBGeEGrURuG0U/aoP69aoKofaqbUQuQ7Uvaof61CYiIPa8f6ECSlmUqIxr2TDiLnarbVYuZ6ZHa/bVg68cCya4ShovBuAdFepg7XNeAUzFzwLNQxUhmXVDmmXVVKoHc5klGnWsqkLUUHUmbU6gmawkqnVs64+C1gSnX06wSxRXcnVC6unWtMMnXM64XUaau0F9i6lFMYwiCQc+Sq6oiZQq6jpnGBAHYIPd5yGkePLbpHkUewQxGo9SUUw5VzFk9WFZsSrzGTleclKDXxlHs/ugpNWbznsouLxNKqC7vTPK8kRFY9Moz4A7E9naVXrxG8tiXmNNXXK60bVQ+PhGK9I0V66ywrUgObUx6hopIi5aZG6kDlMXf0XbpehGE9C7VW6x/KSnQhZ/MjiIA7cTnksl9ERFSkVVMmxSN8wirnHQPURFJPWKstXXNlL0U0sxvX3gu1nDeOvXsWWBpykF3kCit3Wl6zPJ96w1kiDDvKCw7vVfVKMZR6iBr26pvLNXFRpXeVfn16w5k2DD0bawoxoF6hfnl61XUT6pvJ56vlkj64nX8qyBVxQDXAfHX7aOCIH6QnfOFSqoaktGU/UjDNYhJCe/X0na/Wxw1oWX6l/VdlevgP6+zUKmb/VTVNCS18Z/X8eemZpi4sk+KlJVE8jKWlQkKVVwgso/cDSZSFXISuxT/UCHZA0fHfQpIG1Fa6qv4AdwzyBpSqA1pKmA1ZSuA1abWNnEHNA2UYcg0xgUaBUGn/VoG7A0AGqQ7c8+XU5M14YXhJ2pgImKqv0KvwY6pgYKDIkaAeaSLQMnLwnCn/qXVerxVwC3b5VGHmLOKuBq7JI4C4fI7L+GzHxNP4p0xNILe6z9TxjQhrzs2BrglMY5pBKCLZZR5llBerUctNEohHQ2rSGnw7mmJbxiGpnwFVUQ1GskXxOGyQ18Gg+AFVLpkBgo/a6NaU4DMsME3axQ1RFb6IQ63I6RkR2JovAwYRG0I34NMZxuG2I02GtSobeSWKNYlJq4XKI6+EQ9D6G/mFCkOuI9BASIiG1WLsCiBoSG+wrHxTBrU+Io3fRREapFBI2+xfQooI5I1WGqM7GGjI2RxY+KTavY4wIFdCl3KF7l3AMnCXHppciQYZDGztq8FOXXIK53DvmcY3+a50jDGge4FizeRovQZoppB67/nZ65czN67b4WsU36xYbJ1Hprc4P66RvJ64SzWFCdi1hDdit/W9itg2WHLdqb2PckE/erxPhd+YLk0hrPG+zhbyllI3tBDx5ymI0LvE7roU/405VPXSnFQDlgVaAnxyA3LgmnhSH4140+ykI0LvaLF8U9434fQE1FyxE05VM/zQmo1kbONj5p5IclEjLAk8InCk5eYTxF+bUpkm5FhOFQk2LOUB7yUo7XKG7j7wmgvInRMh7FaaSlgZVmKvucqIIC4MZQPSCmNYqI70mvuauclI3cPG8nuFBineG7j6yY1Aqom7D6VzaeXAm7j6yLafzSmvw7QfF+Gucs0ZRol+Gkm543aRXeWwgL5zxVH6aPGlU0+PQU2Wm2Kb1ym01aIVkYamyL5qmzymHUfZ5LPcBmmjd5m1o4rEFEh5k3M4z4oIvk1jHBpDnw0ymRjdR5KmkfymU7lkRtc01Jy6oJxPa07YFBU1ZEqM2eUzE21oqgVvGskoCPTqKemw7JWG3dGpFfuXEs/LrXQEs3KwZO5JhDdE4mpQ31PB00myqqBEmhRgkmp41Ay6fGUm543hYsE3Nmuk2WgC01MhBs3e88uVplV7ocBS2YuUss0WEzUXSFcU2toxEJ+m3M1rPZM1LmzE1NORwKB1VUoDM4bq+mn2Vumo1KEQZE0ZmmU0coDvwMUsk0OnU4oXm541unVclk6gR5yUshZimos2BnDhp/5BcLTfMuXOU1+ohmqSlGPZWA6G4bo9Yq3xP5V7xcdJ82VjSWCbJDbp3m/kq0m4NpXmq4pdmyDqVnbXIGm1C0AcLeW0JRC0VWbSm4mh9EtnfC1cm4IloWlaHqUXzwo9OMZbyzM2Tlb80Im6EaTlbhYeylU1MWiIKsUnLw263k0vm/aKo9Y7Ufm0w0K9D2BS+H825Gvo3xuIAFTGpb4EvUqmOecZGcvI15bU8BUyvY/UHfRS3oK5F7LfDKnfyiYWh9XH6KWoBX+9LepgK3S0Bk8PrqW7BWZ9bF6ZUzb4QKzTW3iDn6tUyy19KIH4WWxBU4Kl47MUDH6EK9H4o/C1hlg0y3pijH7zU2YUqvPy1nbRhUUK3CbUsC75WvJS22vThV7UlWzqK+sWU/fhWIjc6nvUi4XyYJn4SK24VSK+sUc/aIjyKiN4rLNiqfUtRU8KqlERczoK27CTxSBLagyeYpRS/NTrZVUDL5HZvwNWtq2i7So0xdOTkkMsbz6NH3n9WmTyDW93kK4vIZbVXw358uvIdpJUrVbTnqZ4m/xi7A7qNWvgbYKSbWrW7q2LGPbUG8uNZFeC4K9WpgKzWx/qpgbI2J88Ip5DR6bnWvq1rW4QYkOHDqpDba1U8aa2tW0TweRTa1XtMuhnOAqokuc7JvWihkDM/61PWkhmRWTbxHoEQJJERWpZKzXas9OuqjzDxmhuA+BdWqxn40Fq0g2mTyzRFq3mdbKrbZEI5O8nG2NMizweCka3gs9phLbGLoUSyKZBEFnAlsSTr3YP1yYs34jHOabq/eEllBEZm2GdF5jvpNv402gLb58mcjGTRU4BEPdozMwkCElLa2NM/G3UC1SWNMr5xICyUBi2hNTudewlKcP7xZoW/5XtN3jc3DW0mC/XGABEVmtQO/mdqGXETeM362dDbgdpW57Y22W3xBZSac2ma3MZaqYCs6Hp5edm0RQFa0o2pSZHvBa1e2sm3S2xa2g5DSTm21W3kxJlZFKCPnZeXLJWTeG4R/Nub7OLi6x2423wUoaaGfaJo09CCosxDM7B2nQWMk4KbF3G21U2sSY+20bqk2tFnvM+9qE2pSb0ffm0W2os5qaz62LUBG2QrCO0OCsu0t29O23W3G1rTB21+23qbg24Tom4hGB6ne1KN2223xTSUCd2+O1i6Ey7mRWu0Y29ya3hOO0L2ke0vW03J92gqYPWorrt27EQD29LoM2r7KUYb4bE+abp8wI7yKvI23JQabp0ZcIX9GyS24K1474Kk3rxCoNlP2uPrrCwK2qWsehv2vXq9C3RXzLNPpVRJhVSW6uikxJoUlCwe5/gCoXKW077g/ONI5C+oX/22RWAOzoVIKh+3UkQOl1C1B31cO3o9CxB0eWjyW6EElpDC3NrUvSqFJC8YXAO9B06MYh0d9E14JEWh0LC/B1Aoo4ZgOtpbJCjhX5yLhXJWnhVHDD+rHCgn6ZW4RXZW5frXCvK0b9Aq37GzB0LLPfppQRRW7wZRVkoj/gUooFHVW9g3q5dVWa7Q06yJGaY+qaJqBXVhqg5OkwR/DOrTCLaYuWBXZOnZlarTLWToRWS6GOy6aX28y6raNW2XTY+1CXC07R2tx0Lhdi5hNGe3eOzf7LnbI1DTYIpq/Co1F5c+2OaeBrUXEXpyxQ+2QJLK51cos6UYPRClnPzRmOxe3sUEx3pOtq2b2/R0dXTJLJO2EBS/YS43QWe16CVJ2YXHJ2rTbnA2/cK4ZO6ZVSLSDCtGiOZXZP6S3/Fp2Us+zid2qM54XBpVACGa4lG56a1Ohs5+OxyYjOgx3sUV5ig5BYgzXcupO2tZz1MWxoOOtZyGbRy4crGp1y4Y/6mO3J01FQJ2R1XuLTKg+Y4lSOrngPlURCmF72WuYAfOKaCv4E1WLQG516cSVXXGq52YgEp5POs662QLc7POw66MzbFBXGWGJligYQVirY3FWQGC7Gl50PUtpy3OlSRoKFsXliwG7tij/gXGuuBXG353fChXU1WgSqMmACUH0CsIOrMvETivF21hAl1d7H8Uq6pVwPIPPbvi+cmUuiHCoSp8VFPOl1bqvcWbisB50uutR+bKTjQPOl2roHtWe0Hl13EhcK3zN8jsuh1Z2ETNVvkJl3PE4A76rWl0jjMl3hQQdJUhBV24uyxzh7aYks68BGP2WPYEu6l2zUE9l0uwl1jBc5bp7Ul2wSzyZEYI136uiOj6NRUKauqYqzBbThJbNYnRNbYm2usV3aRAiVcEc0I/rVJ1jBZ11nOVV2DhPzReipVw4ulSUWoIfbmujSUmNe10PIRV2kNXV0ufdtUR0Qp1+uP13HipN28wqklz7AkKcFXCW5ukEKWbO54cu/11OuxSSDBH9bRcBfy9bE+62hBtan7dU0XAVzbiuq/aoFFt0uumdVuwut3P7GV31hV+pVuiN0rBH7U4hYN0ju04SFukj7RhbN2e+Z4kP7Ct3puuQAk6+yRCIJbT3OiGTBAaKU/O7u5f2gFhru8VyDDfd3buznWAnYShfyE90lkC936QQ92/6oNhbum92JUhMiQ8CyU7u0e5JKiA2E8+zmCyxznCy5zk8HJYKXuvgpZuID1TkSxBXQG9wiFQD3JSqSB4GiMnJKr90Cy4nn+K0nmBKml6hIbuC5tJskge3KX5OGl7gex9210KD0Yewj2welg1qOu41HVW1yLedi4JuouhbeUsjFARgQlNOj1Kef1xMelZBNA90ZrAA1ztecCJK0oDjiYUVoGeMUGQJcTC8e7fTs4TQGsetYDhuFZS/AaT3Vwej1ye7zJI0pT1se9kJMfWWnce44INJYLyWAmT0Meq7w4y1OnKezYKNIV2lPwMz2GkIyRcexiQbAaZxvRB6R9AvoiMQRz0rodWlZOnzybOLT0Ce0xKJQHz1Se3kGF3X1Duer3gcgjby2tfug0iXEFMfJyCVVSyRG0xNB1CWNoWezC6Ge8NwjYEz0ANQz1NOAUW6FDunqe2T0diNL1cegzzFehFiieh25upMlyqepWlu3HQA/OfT2TA/gjRQH5ybJZukGJOF3tekyDN0rFnaQJr3Ze7GLYgNdBkudqRD0zagpejsTJ3Ns4ZeiMiriQ1o5eor1KdfL2nDImnjsZmBIuJz1C0wLkHeLb0eeokH29IFyTicL3Be2VLWoySwxeyEFUpeQBIuWgxrekaGGJE95/1CFAz0yqQPoyr2Fe970Rtd7QbQaOn+ek95ZxIb1hUG71KdO7Adewr2MjU/j48m7F+K4KUkGlvHiyyyQdSUFyB4aWXI+0ti5kNH1dE24FQyU9gO3WGRtEpjDoEFH0E+3A3ke+LXWq3U4M+SWn/DX3CfhWn3/vCB6fhWuatven3ARVn0jfZn3ONH6aWzfpRFzaQB8+scT+DGAJSjdd4P9Fpb4jVEZgNTOVkjdn0Zy+OaBjeX15zLRASLId6SBBN2sjOphCLTajo1YX0INXX0PvVBBqRHJ7OzMz4A1ZWlYjfn3pRChBK+2P6oNGeaqjY32VRRRK2fccWlROXB2I/uJNDNIJqfb321ytpmELED7W1Z0iuNAb5kDZDxm+7n0U+FHLejaP3+1W33khLt73zT5lA1YBoh+vxhq+x95fzCeBJjSb6aDQ2rbuMGqnkckVSG5+rjvNaJS4Q97O+1pFH6150mICamrfcZG3y2CaCOqh2eW+NCN+gH5wKqxYwkF+1oOjv2uLdICt+5y1eLDeANJWy0qW+v3V+XpGnjIhWPy+BVtjbv0sO6h2xLVBW3jZf1WSzBUb+r74EO0LWxLH+1Q/fpEJC+hVfjLHif2+v0l0ZB0eEYYX7I0/0eEPqIX+5hUAKq14bfBK1cOpK29LL4XXXEBXs8E6kAsNdBCOpRUiKy4WGCXK2EUdfp7+2CpxLWRWMTUcbyO2SCKOiq3+vSlGU+xXVaysPBWQ1ZwO8o2bsWWZyrOVGK4BqSFFTFWKoNOpoU3IwihQo2Vrkd5w4B82YH0UZwxTERA5ymobx3AaYP3EcIM+BiHNTOgNv+YgNBuQgMc+0T5vKoQa/+fr72TCX0kdNd72TGX2raZFm8BlX0rgpKaTKAX1cFWgOeQoAJpQsKbSSYZ7L+HQP4B834LyDQ2DUdj62/JhIq+ESKmB836r5FX3cB7AN+ixebSScD6tOFgGIFFfxzUJpVrNe+Z0dZpmCBhX09go6Z+BlX2Fg40iUBiP2sXNgNYdWuXWONgMKB2KKsdRHUVCIUrUBOwMiBi32pBygPhNSGqTHPpxBB2KIoNYSZeB+w0KMCMEuB5Xgh+mIOm5MS61DNubiBhmLeBEoPSBrCil+1zqY3VcxvVSKw5BwKbaPWKIZBmQbulBQWewXIMqByqIBBzqZ5B8oIZ3MIP3zSUaRB8kBuBvbpLvYqZeuDqKhdanxdTKp5WBBKFVBnQMxRSYNtB8OJMLMYNpByqLApJgNUB1BYMBq4oyBphZ9BrvV81ey4ysjYMTPabpWB5YPTzPAMgq1wP7ReTqRetlxFBw+Yr0VSZBBhIJbgxGblB1uaVJWIMQh82LJ1NQPWBkJ6F1JQPm/aYQM3cuoK3QKbrCZ5y2nLoOCdCZ44h+QPhggW7oh2HUP9A53NMw4Mt1M4MnB32Ia7e440hrGJ0hglZ5BuEOrQTIM91Dsh9HaYOGxHFK+BmENl1HoIYhiJRfzU50Yh1i41o8kOG/T9TaijOpHHDabNBjfyshppWUdOqJZG2G7KBuMFFhbM67HcEMXByeKguVe76/IQYVG5wMMhyeJaBsoN6hmsFvB74OSxNcEvM834wZDo3sClXDfTDayQvCS2RC2/XO4EangA/QjAK30Pfy3OAD+wh1OIX0PdxIJABhxf3M68fxRWixYv+rGZf8YMNeOI5js68Ulxhm+XQKm3oH3SMOfy6MOC60Fbt+0MP3UGAO9InMPJhjBXtCrGYRhisO/yy/33+4+ARRWsPEKw/0gWF0gZhqhWthuGi5h9NgNhtVy1hu4Xr2FhWGpcnVBh+lwYTdUi7CjDjf+g4W/+giaxmPNQkTEAM5WsR0QBln4r+jhxYgUsMMTCmZrAkPgnGpAMfCyq0zh1g3hc9R1HVUwbQIzbGjW81T3VNLGgZPRB8YrLFQMpwNKYvC3wM1bS11d8PIMvwj15a8PrW9YBvh2bEYMwCPF++rGnWzCB/VerGWZC2DI1e8PZZKf4lY58OqMqTDcjcCPaeT7D61FrHdMyKyBAS2ouYzhm/JQOq7o3hm/hwLGghLTwlBv8ORWR4Gs3VzrER8LGSM3CPF1WLHkxDCMrYgeIBDVCN8hf8N1DCmBwR5COaMo7J5YppgFYyLKwRlWpNMpbxVeef7/vdCOnJRfZ1Y5CMNeV9CIfbCMdpcdnF1USPW1CpnoVIbGEePFy6R4iPDY53yBsvCPR1HKIYDEWGwfeCP6YhiOCRibIvUfuraR35lJa70bqR7bzAoKkboRo1lPh4CMBM/aRZ1DyP/eVSMSYlyPQ2oFJaRgyNjMyKP4RmBQYuEKNfhiiMBM3FJkjeCOxRiyPIRmH370hzkk8v91k8oeFd40+o0Gq1oZIcIKsnb+WX1EqNFR7erk+hN6ayyLl25HiU3q5XlNRg2ZLPc3muVZAI7w5XkdrBBEdRx4oMxBOYDRoPkwwh+HH1DXmsXdREFLF3kv0Es07w+AV18Hm0Aas/wFs5jJNzHqMFsuKpzOeEKGJCIoQjBBEzRxvk6xc/zPBDUSt8k6N1zEaNglYwjTR+OQFsrO3NI66Mz89aPuurOZR83Pkbhd1UGrKdnS6dYQtRodl5AWErgI3R4Ac6ub/RkUJF0ZHqsmxSUfzd6NKjWGAsk/kKd8kcIXyw0kAxmAq2sK6P3RzGN/zPeGrRgMpjidGO7R8Dl2CaIoAI0mOPR8gIUxpYkf1Z3Ipq8/kUc7EorzAgJ+CyZS/wi9xeYz/JIxwkJuo+UmQiuxHnkuTkJjSgUcxi9avE/yQ+I3rUPs3jllFAkLKojAVUxjGMwC12a3zAmNVFU6CqxlmM4x8Aq6XcmPPR06lKx9BE/R2YnkgemNNojYn1kqWO1ATUm/NXBGcxmvLDE16NwxiZgcc3GEbRn6YUCu2N9FQkJwwA3HWC62Pio74nDE5aPyx66Dac26NRI9WP8xsmNBzaOMf5QiK9FNWbRxpApgQ8kqbRgMqpQdiXKx+UlZx9REGxzYnNR34Z7E1OMwQp+YOx04lWQdONlVE0l1+70OaCX6E9lcYK3lRwQVlJuM3Vb8obh4sNcmFsrTlOAmQVL/UxaacqESt0l2W+uO4CYcp9x6SQDxicqEVKePLmdcp1h8eNB8IIgflPpHQUYCpzCqxHtxpjCdxpeMgOiqj/laIgHUFuO5GI+OYernyLxwcOD+sDDnx9binxqPh3x9PIzxruP7+2+PvlHsrm5F+NnxvLyfx6eN7x6+PVCWozwVMKH6QE8DSxbBzABkR3C0LCp8YdcP7x9ezs7V3rAsbQ3I6Mio/qCiq7iLCaAJ7DQTKLcoMVE+PMVL17RvDcx4mKq1oBrF3q5dgEsuEvFVmVIIc2+O5zLL2kU+BhOo4+gJqRK2gTfVXG0GVRaPvaW5zLcGlFhP+RTvC3FVYgnycJsGqiJ+hM1TSRPsJ+nxTsFXFyJxaIZCPL5SJ+RPAcjnFKJwpo50Nd4kS5hPaJlaDRfFnH3zJtjG4rnI/BxzQXvfnzR4nERlBaxoiJ2Dq4RexOa4gJDIDCXAQoSvJ64iLE8NUxPS+GAPgg4QLbTIxNpMyQL+43RNqJ3+oaJh3F0J5xo5wKxPy4/RNxAjaCFjCJM/+cyLhJmJNlNTwo24rROxNAIoX5KXEfwgoLoyBW5zLPgiLzH1TBfBPFo/PI0CgqMR6JsRNdIKYyS43JNdIfJNWhdPFsNIjaMJzpO2+e87BJyUC4RMPBngRXzcJt6o0JOd4442iOENCZNmJpunCRYZP8JmAMM8nXyGJtPEhJ1nzdJ1HGZJ1oFRJq3ypJg4G4xcgIW4pLF1J1aAyKhnnZR3xUH0lD35RtD0X1a/R6gvmiGKXJUiRBTWxEXerPJrxSwYCpVZspN6/vK8MSFZqXZxl6qBig9oG4J8NgpoVGatLWocdEr7hqJKMhPIVGjUQLFgp7j4wpuTFyisaXiSuSNYpz/FJxuzHX3ApYCRtFNsyU8WEp9aWTgSzF4p9R4YEoKOVZSL7utDrGcZXgmGZDzHzkaTraRaiNqip1pcpwLEfw4IlcbeyPLIL1GaqS2o6xdz76wDiM4PTwmpYmlOTPG1qGYoFMgPZYbuRvvrFo3w6SR1kWWdDFMUpoGVTZGUkm1bNH0mNSMMplc1MppCP/cd01sp/SPggPFyCgU4jspwBHO+UCp8wTKM+pLInBHX2rKpkLqOpsLE0pjc1ipzKOkpzqI2RgNOVYrX0+prrpiYLX0q9QdG6poqgspv1zk1clNFUSKhzo0NO+1XK61xi52lEhD1Rk793Ie+H0ZKxH3BCS+ryystOy0eGxE+6crvYitMYMberlAX5MJavJkvUlaXLK8JptpzUXcXTtPjCDSL2TDgNUldaLqB/Rols3wLvORoZDs5KLXBkwMfRvqIgBAdNv3aPndpydMls/tPdKePKdRV1y2FIQZT5ACLmTB/rilFBHmTN+rR5SUWrp0vnMBDtObpr1gTK09PxQJbXlah9l9s7tODUWAaobPtnoijXBYhjPlVRaf4MNI9mWIV9NTOx/KmBZEUkdc3VfoubUPIMgbR8K9M9pm9PwRBDO/RhAatOGDMgc7aILp7Q05807ILpi9OV8rGUDTbR4/s9tM7pn0qkZjdMb5d/yQ6l7VUZ/CKOh2DPKwY9PYZsGPABHYO/Jffm4Z9jMK7QAIJlZjMAZyvn0ZrqaIh1k09ayMjj85vLAZ+UhClaimnVZDMwCpDOUZmAVCZ9DMIctjOZeYqZcPIQXz+dQM8Z6AJ/5HTPm/ALZKS4Ar7pj4oj5WAotaxSQAk4u6/a2jMwCv+lkZ3GN0yu9M2Zj6X2B863BxseKY66SSbB6Qpfpgo28Z1znAZv2AbshimLmhjPIk+G7N+eTNAFNTUi+DUpNDQ2P7pxdXEU4YmtRa9MTEhrYErJTO5xgwLaB+zN5ZxzOqZ/PKAktFYQZsLNerN0VYUGkU/EsTOpO9km72irX4NB4lVZ2HXvp0uPwZ8zMyx28IxZ0gYAkyxOPawrOlxjLNOZjWMTOI0X4ZpArmRT+5jZoApxJobOjpnkn5ZtDPDZzEmTRc36hZsA7kRQnVH7R2MzZw0PBJHNN32r0MHxlPiNC7MPFKZsM1GC7OjoEv4DhyR2r+87OR0bMM1hrIW3Z6sN/oIsNvxywSdzJ8YAqrIW7WNMOmQDsNf2vXK1Cu7NvZhoUvZyHOFh0HOX+toVlhqHO18boWvZuHMhhn7MYQeYVYzJsMjCyZFthh7Njxs7PQwbHPiqmUB457f1CzdHNQBrMwrCkcPs68dGcO7PTcOr/1C/foXLCo4XT9BcNdGC6mL9URVgB1cObSSRVE5xBOI5ncPHwPcPLLYhPlWo8MoB1R0UJ88ONOcV1kuifg1ZI7wEgeBo9hVXP4uno1yhPUSKRjVwwIfV14raRSAhftya7eklM4WSNGu/XaRgpnBRERVxrE8t0FkxCN0upkL8uovqu5htbCu7cH25tULzcwkrvgq3Otut9PChE3NVupJAq5koAG5ul2a5hPza5jV0cYx11V8CFA5uo3NcSk5Zq5sNwa5lXPEmUyBKuXXNa5niI57DXPG5kpP2upPOl7DdBdMLt0iaavYu8Cqz+57DNkwhvOiIDmpO5rmHV563PK5vXOorbjU95rXOVJzgIGuQvPx5xzQ9KRWo55vXPtTX12R5vXPbTQPwru7Mg+FBslMYK92jDOPjKykXVV2AAPWQX0RHulfOb5092F9IXIroNfOzVU/P75u91gSeEYZ8WEDPuw7KICKV0AnAg2Fp6A0Vk2A0t4m+J75sPDYegYZH5qD3/5jMntNYD04ZVfPtNOD3A7fNOBSog0f5hH2Jk7/NP5+viAFjfN35kAtge1AvBgyXXoex/OF8e/PNpqn15M8V0eg6aEWUHXNgJfTZVA8gurESguF5YkIa5/sEGwxLhVu9P4Mu7aEIDI12JMA6G9EJvO5tLmGhbP/wcu9cHfkvR127ebmRHR6E8F2fNDJR8XsFkPMzhVLbMF9YLEFwGGuglV3TjQGF9ERPMCeUva5CF95zu+kFcSyIroBAvMUF0zYlCM12HBeraTHQFaGFmiW5Cbr4Nu8oG6Fy9TyFk7z155so9AXgu58FvOeFgobMu59gFbVwu15mgvmFsFD95jQurbLwvRuqwurbRI4Me2IuWwyL2G5jzz2FzPiWFnQs7RtmFPeTgsEw0N3JuvgvSw8Iu97ebkaQ0C1+abHx0u86CzpDQr6Fht2DUYI42bE8AmFlQurbdm5uVSIuWwzL7fLBotOw+ItVFvJgGwnTl9uyPJ6hdnYcF44kXi87YTFmQbyw8WFpDAIv8Fuc4R5+u7FqpvWR+Zl2yQh3xS9VbyLFootaF9XOzF9tUC9dwJCFqYsVFwTxL5wgwhCROG2S2+QEgBqFo7O4t1i4nOmiV3h4ocWEH5vQQfF1FbX5gZgr9H4sRS1pgAls7ZvKY/Mv6EEvXbMEsP5m4tQlxSQv56AupKyJnEGktMIF15KAlmKWlkR4vwGv/ORkQEsJS9NL4lptMsGzuGIlwg3IluAuol9gqEl8OEElv7O0l3EvYlz4vEe74ugl+EsEF9APX9TvSGrJb1oIMNYL0D8icA7pTWrAUsWrLj1PQJ1Yt0QLlqewXqhpJ0kHqQr2ylo1IJNHYkhA4UthrKUuRrfDgSl0taallQGsTDUuLbQEHilioHWHKlIGeq5QalmLDmlo4E6lvzwVFm6SYXA0u6l7uIO3AOmhdfYGFHOxRC0rTpdrVI7fyG4GsuAYGpHVUsCeuTjjrEMvGl4GJcZRtL+l3tZNA9YQR0r0u4bXEFp8TIExqUahOA8Eom0/w70mIoHqll0u2EV9bal00vuYSmQUUK6HWrENShlk0salqraBSEsuFJK5OQGt/OwFgJWf5xMkStQTZmg6xKH1LsuP03UkibSlrdl0dZDlrNIjl6kA2gin1WqzkudBZGHx56LTuIvmG2w4Ekm4CaFoSUGFkgD9WWBJaEZ5nEDZqjaEMuh0SmRPmFkhPcVzVKtVSw3sEJsO6GsVC8VzVbUL3Q28UXl2GERwR8XHl9WEmw38H7l2WEWw1cvblrGJ/l/klrliGHzl3sHc4V8srl30GqkqCVgV6CsTqrGHmqPXMAuRaHYw+kkGkvGHu5frYT8RsIkwpFCTgmCsTbK8u+gtoHp7J2IJEkisgVoWLdMfMJPLLiKnlqAmUV2qDca+/wsu6yHlrFiv+s5PN0VpmFoSQAmUVzXDrlpCtF5xuj55+mHgVs6DWw3cs0SzFYHlritV51KA2hU8tsV30EIcdWFYV88tqV3aE0V2tUboUtVHxEWEghWSuywyMSd5wiL0hYiu9lIjVyw9tVPLJct+xPl3kBHiu8wjxxBrZkI/LN8JRxFlJjFjyssV12E1F5ytW3L8sCV+ytAVqytkVsKs+8IDVRxUHq/g7FAHl/ytOVxSt0w3CNIRVSsIYXaHUlR9V6Vk8sOV54rpV/St8wtzq2V+KsmVmgxmVySvfkK4sLqVZAvCBIh5AfcYxw9F1f2ltq6CFUGRwsVBkgJqu7u+v20+fgTaYeqtLAGEipQP4uVqBqvDViOEFqCZxtVhEufugtNIe9/Ptl+AtBKscSNVieH9VpOG92Dastw1avPjEfHeKvenXJ3KO3JxUAiyiU6dVjdCjwwKC6CK6tDVhvMc7auEzVjkuUJo6qejet0enGDNG5O0apXJWlp8GTN2jO55f1T6tOjIfWBXLEpfVy1LSRVysQ1mUWxeW2KGIu0Zfkwr16mQ0aI1rg0aw/rFo1o+FfQtbGiupzwiAwvV2jFXVJettULiyGsi+aMvj8gGtQRSmv/VrOP414Gu2jU0XXhfDh8I34BWQV1ys1r6tgQzmvg1p0auyEAL3Q1zHs123VNAuTg15dmtIUmK4L9dxl2KUuiC1vmu2jTiG817DVK11bTf5eGsNI7gxbs4GkQ4apGEMcPIY1mkmKGJxEjQ4pEm1gSI6OB9UZbRQzuI5kGwIuWs61omkpIlSEa17pT7Y5WtjOLmtOjUyGm5b2tq10Wvalj2vhghs7glQIrcGKWsz0rRKpjaEV35K2uewG2ux1xK4gw82upQlmu4RzGuNNPXy2xMxHcGQOuCYrWu+1zLzQ1uHx1x14ukgbgwy4E+igtPzSY+0asV1pZD/sd6yugSut117fNbbO0ZV1sQ69h2usdGAYyQu8utSEXushQ0FqN1vutarBXOUexpw6FUTAjJKkAZ5Geu1sVSpAoLwo6FEbauxfehX+GP6PMfLDAtVAKUzMyq2VUMWpa2jKh+I+vGBNYoabfkB71+7XYAp5Dn1revx/eYK6cfegn+GP5pnWkTz1sALCZ6qBKDY+urTfblL18+vB1eyYb0ZesX1t9MCqTFoL1j4qH1ztLE1cyZVVBfCwQW962FWeuutV2riW6F41NF/TuNb4bkGnybvfW85auNqAtZY6L9lGqDcrPBvV7Jg3I0KxDN1ml7UN5trUacht3lShsBkxc40NpG6lCHMUVWLhu4m0xIUNrgBHXC4AjJltgn8hhucN6trcNiPBCNo646umrxMGwhtuK6XQ/cMhsInfPrsN+AEdkPOwjDZRu4zHRtqN3mkI3fuvQVLRtf2plb5Gf3ACNjRsoAwxv+4CRtyNgMmWN3Rt84Rxu4zBRvlQGRumNi8bmNwTADgQSB7gY6AVMnQAjsWTxNCDhkSO/cp+NmjZkl1ssUlpatUlml6upVSPzVCvqkjKD0pNzQBpN1MDYFzCQK+HJt5TTJtfhTzw5N+mhdQRJWxNuaswFhJuoejsvsFDa4J2qaBkzaQQfYxpti6Zpvmc1HIA4y1EEQpmL0nYZrzdEQq9NyQGdNg3DRcGKCQFoYCv5hattlupvLVm66OBXMjW4VGIq8fuCLNiYTLN4/CbYOVgbN04i/Hb2u7NrLUEQ/3CrNuIiVN0kvVNpEtCy06v/uquFrOJpuQnM0hDNvgoPNjpuQnQZttNliSjNj5vmrL5tAw3IhPN1puTNkkv4GuJuzN2pt3J+ps3XLNatLFZt99c5uvN2FuLEUtjVUI5sG0t1KUwQ5vrN/pwnNrFtnNujGgt+D1XN8ks3NlvBoekJtaJKaAp4lXAfYylv2xKao3qHoB0tkoIcxOZrV8FlvUgNluztAMbKoZ6uK5mEZYlaBG55QxlwI3NXAMtqg8Y1XAL43C6YUrjJYMoVaiYhSOIMhlZWCxOZZ5mfGit5kbyt2BlHZIEZNMWSOr4yVv6tjIz3441tUImzFkM81uCUxCNGtvVu0UiOJ0M+1uKUzCNGt/URMUuODmR1ApYdVzFTYiAlnKGvI5YjVvB2AyAOUoFKwEn4hfOBMZ+t2gmRkf2MWUr1tWEpvbfE02auty/JBQVSmOt0gnWt1Sm0xZ/HWt1RERwf1s5ti0ZaJfRlvpqPKpIwKrZt51s2IrNvqm2VtzY8v5WhD8YcM+MptYh3P35UFQS1h5k5E5lt5Gz0Z5t9RkltgGum5hckVtkGvituIkmB/bGhuks3m5TmAcS7uKhR5ymXVf2PfVxNvB2faQd5Dds+E8EqY15dt74o3PVI9J0EEno1a15ovgMxtu2jRMHJE69vVYtcHpE89utYnMSaE49tdYuc4AFfdvG1z9uGEoiNWlfMbri1dufh7XyDt21tbtqNvTFUMaGtrduL7G2uXtiVvwwVxGd1tNuFEyDshjQ9uK+LfECs50K7twImhtrRZl1sFskt+Jtkts6tqHd+HwITGw47OtUtEtslzBWGx0OF+mGWdbj7VkX6VK6qUSHRhOcjNN5cdqJFykDe6RA3m4wImt40RSFnRhATtz4xKBk4aMKLUct4G06L6JzRt7WopnIid2E2hRLSrUxuTtz4y5kfzSTsLvaTsQxnjvlveloMLbiQ7ozvpqfTkYTvQVXE3ZhGX40ci4I7TsLvNGmK+azsrvfEhLvVeF+ovXTcdndmYEp+66JvBEuo3UCdZcBH0BBh6+d/jszhQQme0rztyIgp5ZpfhPzzUD58tKd6mI2/F6MnOb6d0R69wURH9IOR6md3+ZpfQ80VLIhaDfWU3v9ZxHIfcNR+d3r61d6LsVdqDpZd3+ZNdpZbdR3rzEfTWD5dkrsKp9BbKImj4y5fuYBfbrsrBCLu8pyJbdR6vrwp++QcI7aL8fOtBRI+butdOI5zvDLumPf5mLhdbvdPYhrFd0D5ibYrtPvFw6ewDRY50bx7Hd4hH2zbz4sy9BawdQh5LPet7ud/p6bd2hG9fVbuBI5zv2fXmrld96WhNpbtufZjoQBILvOo3T5A9h+G9Zbx4n0TTuHdgp5cbRTuddyL6dkQJE5drZ6LMylzMjXrsppszsldwNOudgDXTdqrpHzCb74UwVEEyQln2dwdFo9uRa9faILpdlHtHmyvyyd3r7rZIYMU9iHpvPDN7GdzC1DM7LvM9ycDE9/SoAvJpk++EBbHSlnsddltTHZz0OXO5ePnfLS0mLLpHyW7F6mLJ/2D1tS03I8qmG9eXsXIm6bw52Xv0SWK0OLOGnjI2l46a43t69tXth9F74a9+f1ivZXuXImnOF9Ry2jI23uvKevhGvABCa9x3sv6DH4WU0K0GvYvpFLNnTfZrnUNkX3u/Ik3vh9wFEIJzcP6WsFEq98cNQoycMwotnOUK666m9xFFVtoAMKO5cOiO8RVrh4XNT+wq0o/Y+NLLBAPtgQ8MC/T4Wp97iqT1oaFUJub5rvB7nSJ3ORNdZvv0+ImMgsn9as4tPQOh+d00NMDy1+fvvfVfxAaUD+Lt9yJOo5ERoT9pRoiIPvsn0JHGj9nUPFrHvsjikGUmSRftr96GUL90xpMSF4rd90xqdQTaWyG+w2H7Po7e5twNL4bw4B51h4S4MfsIJD4pOJinHj9xoZuJq/v4yjQYG4nwFyh3OJ3FPmpciVaBA4IgkS4PfufSjfumNRknr94SuLRaEU4YN1bQD3ZPerfGU79+nzjcGVnK5thrdNRgNprbLi2+JnBqFnAeZEq4E/9tNbFV1Rb6i6/uv9iwMUDj/timIXxW58/vfpIRb4DoYNADyQJYDq4oz9gEHqhyjaL90MXXeDdbAD2Ad+BIHD6w5suIeuH3pKvDEt4ofy/HfMQ47WQf4YZIa71C4ysYIzCfJ+u5qDtjsYu24319qj0KRvz74ZXSr+uOEgX5GqrGDj1zfdnF4oJAlqS4XN41VYyqMtXkrCdoZqeyDN3zsuzsKDPCPq5y1u0PFY4XmcNy0xPweDUcv7POJYItdnF7J3OmKDMT7y4BN/pmkLEXTs+wcpzaAKWD6L5GDtq2lkUwdWhDIf2FdkLk9mqqWVSfNHawwdxHS23huN3jP+cweZDi4BzvaoeQdXtBTvBwflD5xKxDn3bBJUeaxtCIdDNeyqe+FdKeDmHkDzA1ptDnF4GcHyrNm0pO5DsVw0GTwerq3G0EwSoc27MwkBDs0QBedody4Vp2bOAocefVyqbOMlnrD7zLSdEGyTDpGiuzLYcTfQoedD1YelDw14CPWjlVDz8ltWgmDnkRXz1D6YeCISvLNDgR46cpocdDlLpznFwenD+1MAjpuZeDrO1kuaHzrDiCSzdMJr2DjXCOSM1p+nV4fLDp1r3DpYeTgFYc4pG4ePMqrr5NC4eDUCKoRtY4fyjCo4aAQEI5kfYcizAxDrovEdg1Aaq/AB9FYjswcpD4Npoj6fxTDj1ovD+fZzDhod2Dz4csjiEdNDxdVO208gjDt/ovUV9Egj7Ymkjm5ynkSEc4vDbza+N0ZVd0YeBVCIlIj+fYojgAEnZmXuW9gFj2OIg515dfOWOI8AKWcEshmfUfWQQugbuysTuYK0dmj+uvAGHTR4oKTI2jqcjOjjA5+WR0fujvF2ejhkcwlq0foyU90zNyQcol6QdolwvIujh0fAekqBRjx/MoFk0dEHLVU3fA0dUjhVVTNmomw+m5PFp8MfUlkPyBjqyCMlgsfJj/D2+jooBBjlkupj60fEl+qMcd6/oxCTebP8v/oNjnBbVzUTy1EOJHWzFTwdjupG6zKBnD0YeZtjpq2N0PeZ01Lwrz1limCLTIZw0Dykuzb2ZxpFJ6rws+ZWtXJ6sLK1r1uohYRzAtIQ4OJGuzDtLPoGdmJzChZisg8eYIvsck4roQFzJseAM36JYjK+Y3h8Qw5Ii8xdFSgZPs+8frWtaGCIrsfCDZqCCxzuY6R4dWCI7ebKllw7vm98d1DVWC9jrsd1DTXBILa8e1+3NPWKgB1hQRXuv25Cd9IiFEY50Pv30Q/2GaV3sF0XCeOLVXtPZyLhsOxZHMO4NQf1NZHYO1+PYT4JskQQ5Fe95uiETh3u0Ts93hEaR069pifBqXB0294ic3xw3iMOoPut9977kO9xbvIi3skTytRCTgFELFcZFiT/RZLLSSebh//pBLKtwdLRPu7U5PvcKk8N8OgTyZ9tF7Z9xAO59jFH59oXP5WkXObhxWL/jUvtEog8MfU2XNYo1AMzll6vOgq5ygRFSJkh+9BQRLKL4+Y3Au8GrwAsd30yJLdWZRcfM91CZwRBXydwxDivwjcSK6BmRIoa90AAsaRR0xG3DHaze7IDdKeELVCLkim3CjamiI0i43DMVuKe5qRAr6QqKdj7Q2IV9ZvwvG8Jr+Tovx1TiKdlkUrwvGsgbsJYFbiypR5pAETUDRfnSKhrjWlTwf6IuNIBJTsyLh/QAKjTjKfomVh5TTnKf1EvFyjTgqchNa2oAQcqJtTmJo9Tyqc1++xKsanNBNT76Knjj+IbTw2KCq68JdT1adKaHycLTq25XTrCIzTjo1nTm3KDRVwJuJQyLmRYiJpAE9X7T/qeQuLacezXKcDT/jVDT0VyI3QivJT1KA9BuaciNAFhOR/6EzjnKcGYLwpLTuhqeT2CJrToxrRTimKe0gGfhTw6d7T6iJ4z32JHTvuK3hPydPTx8JayMkN3T1qdIzgW40zqPywz4oYXxCmdneSGcKLN6d35VCKIhr6fl+QGeEdxCeDGmBCy5O4uhOYWfs5IEtgXcH6VQ+JWiz8WSTDLt4AnX6hmg/RVkhdZwbGs43qkasUUsCF3NVg4Uqz7gBayOF3/XBF1tiysXIuj64yzbY11iij16DxpyEQS+OA+f3GDBNrqGJymc50F2ewdZQ2ARC7xWuy9E6cQCLyxCInbomYIABt1Plmx2fzecfNFbS9EQoQHw129YKxz61ySebuLwq+Kohz+OcIafPMOzuOfzedP3ZzpNFObfpQVhWqgBFMSJ+aQ4kTdPOxmeVOd+Raqs5MPMAWgERAJkRuf4gAOHejsPqtz6UAJi4Ay2QeprdzjufpgfDDtz2ap9z4ed+EQeetzgkDAcLURTzkwOTzxMDLAeeclMMrv4gZeeTGqScBAKzK3uKoYtz75rLAEecbzgSemiAAm83XMDNzkpinz2Lxtzieft1sjx6fYQPnzsjGXzq2FGSj1ygGkzXg/BpBMmcJW7zleeHSUrw3z8UCDzhmJDBp+c9zgiCgL2vxALj+dear+erd2/MDz/+cbZMSDvzkBdWQAQfgLhMjrCzBdoLu+cnkQL4jsJBeZ9Qhfjz4Bf4L5cgAxMheP69iRULg+f6wdBcZdUdDELvpT/x0dB4Lo+fdx/5gEj2Zw7zi+ckLvQS8L+hfkLzheY5gIDTjFXBNz5+cCLp5DVtDhdSzvd2FMYrh8L6ResLxNDKL4RewLnWh6Wtf7CSFhdaiXRcOgQ+cKL+v3CeUFQoG/RfsSVdW16aheDziYgoG+RcGLx4L0L2qB2LzdAYQrBclMRVAeL+RcvFzeeViDfsleFRcQLsPqBLrZu+LvY3+LgiBahQeiWLsV4xLuuzGLvxfHzgIAKWUZzBLhMhpLprIwLtxeBVF4hxL1Jf4Sl4gRLgetRL0JfK8GLwZLrxcVL6EglLvWf6900RXSqaAFLq3oyJzReDz59Ay0Fpe99TCDtLihfhkIti2LkpiDL+hfPFyJcpLysTBCVBfGLrURTL8edjL0pcTLgiDmAqpeZ9FZd9L0Rd0T+iRP4DZcuWkAijL80eCWHd5DLzPrC++ZeHLqdqzeVZf3Fq5e7L5JdcL0wyHCXZcbMUubnLjucgGE5f3FiyRvL/pfMUXC7XLjZj/Lu5fjLh5cSsXzOfLjZjgrg5fvL5FgQr45Swr6Fe/LhsjjlqRchL/MT1NOpc9VhpdhWlqDPL45TtExFebL9ideW2nRwru/T86H5dErwvpjz1FclkGlc5Ly1U/C2cvDQo2f5Vu9L6FiBK8DWVr6FwBKdDGYKctdj4XxVlc+hdlfs+GRJcr+euZfF8F8r+I1VAhXycrmcWBpKyFGpV/ASr7YH+hY3BqriQEarlOyoSgvZG3NCFYS/eiI5K24+qKSVKr1iL1zw3hnlOu7XNQXLBOOYajDDuey4Y1xTVLhQzz8WQIeesDur51eRtxdq6FBIh+rt1fdIbqvvu7FfmEbTDerzdCiTyNc1tWqLOr2NctteyCBrvbSLtaYQJrh91JrhhtpAUkJpr5NdIr+eiJr2OsMOzNf8Q51dh4OgR3pGGAprqzRRrmkTlrs6BRrheQJEL1eztANcFr46DWSfqo8WGhe2OINfGrtsgdrw3i/hW1dujrEgjrqYZOrpY2YkE86OrlNpizE+rG0KcMa6IlfKzxNfDxC4a8CZAMtKZni7VOvt/CtTYHUJyNf3L5STk5hnNFSYlnruOw+oovhXrzdt8PVnHbIoDupPJHFPrxp4VF38kKMtkrNFj8nb6Wp66YM8nrCoB5gg+8l6yGUnyq68mG2QorXWEBEv0E1E/r3EYRKC1Efr9EZIb91GXrqhFVDLkq3r8CkiIBx4gb3DdgbzNERhqPmluTQBAIh9fGYzq6EfCDfZYkWTkIr+66pPCky1Cjf6FE5DmxNzHHruh6nr2ikg5C9cEb/zHZ/HZ4Yb/zHVFbIrmAsrGPeflHuYdjemrRF4moyHhsV1SnXr6XwlPDPFGUqDflFN8hEDnWZibxB4t00TGhhe4obYcfmrzP54mb/6sVxZorQYDYohI6ttnPbdxWC/xFpt2jcxI89f3PATf5IrjeUb8sZ6bl9eVt6kRmFHDcPtv9fyjQlbulf0YcM1YrBbjDt8XZC0+bm9t2CftEib2LdCbw4oSbl9tY8Es0vTWTexbvzfMPFdw/tlIRmFBMS41rLfgb7TdXEu0ZpbjzeObsmtJb0Arhb0DuhjKLe1bxyusIxx773GLcGeOLerFETcdb+DI+olLdy18jc0b4bfcGCeh/PDLf55COvPPO0fC1xpoMb5h6Y03jMR1pyPqlV0u0C2bdf3dLQPsibcukazdy4YOujbxcKub6rH4TG9eebnrf5buFb7YnY7Gb+rR7b7ET2bkh5l4+iXPb9oqlb1bf3b4TeF5YWvNHEre5fVrEXb1Tf9buWtEb/Tc8b6rGEMbLfjb6kXDFOHeTKc4l8PQAkhjTkWnRvJ7h43iWYB8F5QEtHfubjbeeoADsVrpbefLYLGQKZ55hS9dvo7oLePb74kT4bNpjPGDd5jeHcio7re217LfBb1hEwDE9evrqRRXDQ4pc7nhRN2NndXb7CzBthLfVYpTT3r+bcbsifA3b/RxeY/nf3FGaBS97Bt1UyZELFeDIJClqmUvG14h94lfNjSnNHgdl467zXdEvfiegrpCagohV5UvHXeVU615Y/b3tkWeqngTHl7NU83em75SdW7jCBnIt3de7q5Ew57l4B753f2kiamKvfCdaQcPc7HS3diLiyATUobwiTj3gJ78N6x72CoLjNSd674ZaaTxK3aTnh26TxBPwowICIogMWnCpcPQJ66mr9cR005j2h+756kVM0q3S5tibbrm4XOTpleuTyrwzMCZmauEW4iZcI43xd6KgZeyr4ynDKQ+dIpD90feieSYpt9tpkJeK7PwjTVxhAgo4ppL5moZTI7lpZ24xclHIpHYlZ999ShMslfd1M1of53efe8JHmRWGqkByTrgL6jPw6ctWXzmJLW5D7gAYVZR5mAM9eCtT00a37rveY3GRACITgYmlPhr9xR/ebHCZlAHyHxbVLvuT7hCc6jnBshmaBkvuOJD/2xMf7vC5cJsrSwEeOWfF2dA8iz092k8aLQvuGorpQR64gurWfbGmsWWzkxcPUyjIvuI2eLeE40kH4G4UHkC7Wzm/W2zg9dL3M/szBcAEmFhWWpeHFxQ1a1EMDrg+7YYkIKy7w1yufLxdODgequZFCubCt6CWnFwBjLjqorC7w4uTuqvo2Ac9qj5zqH4NqERcC1BuIUVqhbmfez3kUcF5e7A+CQ8uzzg/2uEQ9UhJmfJz7g8xzgfADM+Zy6jKQ9geazYPNkudCH+1yMJdPa8Hhw/0QnPZiH+WLzOGMbuH9KBR7AMVmHsdrvM+ZxKHvd5oDsmEBi/wttT1Q/RHuQ/WH95xd8bjX2Hrg8VlYfN5H+1w7HEudZHvpxGzz0LmHv6IYzDYvL3dkblH7pDBHvQ+ZHBo/hHmiI6Gho9hjQQ96vY5wvTGI/13KI+mi5/YhHzw9NUF2c+H95yOaWo8THho9R1XQ8eH1SYlH2sJPhSI9zOTe2nFit6jMnZxMt3vZpHrOCb2yotI+000NHtw/tH3zwNHgQ/uHiwqchAqZzHq4+w4HKZTH62FnHrQ9jHxOf8Dn0J8PBYt7HyY9PVMHxWrxpfcSXVWS6vpT1k4E+oH++eNkrZpHuqE8FhkE/3LuPfLLrddwnr4sn1XpoQnk8hgnlE6aALXvgtNZqzVw6stliFtkdu5uI+5MktZeWXkniyTEY2E/+eSk9AnpRs1j/k6EniQfZjqQcJk9gr7ughvyyrE90n4jEbYEYY4n6jECnxk+VNtg99kiUAhCaHHaYSx72cBHEynkt7e3VHHTx8t6e06nE0DEr4Bq53LZ0LcWVfOazM4hU8zvISSSJw08udnWGE4lU/4faUt9FZehpPHKrJc8krZ0O0/cfQNQc4y0/YfXIg2490+iPOxRp4kPKFdpT2S4xYyw95L2eJ6caCEmdUGn+h4Td60/Y4rarXS0M87hbOikPLjqMmbmrZ0btEbdRdXm4rUJwPCYglT6fxOnyx4OnjnGmnv6WJn6xNlnvVEOpHHxFnmaXsUAXFVnu9wFni0/nPez5Gw1s+bo5NML9qPHhnzlP+3FJOjrdxkJ1QSsJ4708WEms9jnts8WEj9WE4jU+QykBwpJz4mYykTWtnmsJmtPKwI41TSIy308a+HU/kikc/an+c8REqz2S4+M/BE089+J/f6ky2EBHn1BBeEsDI5nu2i1opU//+Os9AygxLyjd8/pPSc9zn58/SgWc/C7s0LnOmA8HV0JlEn0MeUl3MdW99izfJw+riylwxhUJolq4cnFSbBC9wXsU/7rgcVaksP0k6fVqY8a5zL89IoqksFDcYSnxUteUlZpHgUOJA1NIFcjbyCyYphZvlrt8q7OOx396S8xskitTHibweq3Q2XKTTFc0lJjefiuYZbaEsVAZdITwoyxqi/udFmaDrBUkjIPC8kXwi9i9f0yatD/I7GU/mqXmArhqMi9aX8AopajrqyXy3ZfamS+06cIRIFSCIMX0zRepiy8VWFi/jNh4lA6+y/BQRJizrNvLiX/Kgop2y/00Mjo0XjYkGX07rEX/S+JgK/lBX+UkaXxXl+X0rNvWOhpdIF6halFzTFNb9rkbVy+2XtHUU9Ti/skmK9EX6tmgd76zeNG5A+tAS9SPMAU0JGNP7EgK91gJpO7GDLZt5bMaFX/i/eXjy+5X50KjMIwo9dTK/aj6XuwHsPctk23oCAD3h0G/q8Yn1vh11PXpvKZPd9XzRAjX+6hlZ3+0DX9NhzXyuATXode+7oa8SNSa8/cDa/+S8FuQXxJvQXzHhbXnOBpkg2nzX3zmnX/q+cnQ68FAAUEXN4jssn+at7X+ZtJN66969UNkCHeEkoGhNBXXz683Xla9aQI9jjX2QCYXlycCt82ASZca0ZQIEbpFbbqlKs9d52LPlJE+G+iYWPkZ4bLFn+XeGU23vAqYjG/r2+wmn8QDe1RNDolottgvknRMLdZ8KE3qT0JIEQLY37dauTFlOI9Om9k3prCdW3yI7k7iSKIg7oEcMm/F7gW0E33m+IbeTp03wVtE3wDpI33Dc4y0bpQ33Deve5G2RWETEYFfoKmkP5zC33HzbrMG1GkBwUy3yYIYjSCZuIEQI4oU1boc1W9pE6GP4U/W8G8nW/EjGIV+JH3nW3tzGSQOm0K32gxK3ibwYOKq9w32inMe43i039W+Ftzwqo3h281YuNqJ8+7heI7BRCAqq8k3vxHCWu1MHdUzr5Ip2+hAP2/ljVm/UdCW8NYiZiqddm8JI7DnEIqQI83xpEPSYG2rcCO8xe/61e3yYLfVnGnR3tG+JboySvteu8hbxu+e35u9LYxvM6C4O+WJxm9q3rbFhJim/d38m8eCnW+sI4WZp+VO9M16NdQC0e89biG/GkSe/nbiKB23rG/q3kMaH7bGS1dbIly77ETXNBnoTCaQQYFdmsV3tu+CJD0Pq7goW67uIWS9s3fG76+/miA3dpGK+/NC7KnTC3IWP3nUwlUwPpnQZqmVU6B1p7w3eScXcZYO/3t7oN+8UTnBNbL33ddUlB2gPpdB9U2B8APtIz/IyuC3+ya+9+woLkKrCeAPsDAoPmYWLUjB+LC73e4JjPf05++8bCicNLrlPs17vCbwZafonCoycV9kyeV7/15RNovv3CuvcyO54X2TkhOOT1vfy50G9T1i2IQBLB7WlnuoiP3h7mAnurLDftFiPlGIRuRrdSP8o2+RBJ5KP32IqPzp5+aJEGXQktHOzOFbozivjHk41VwxGiOtPZSMeOTtvcbsRN+xZtvhlJAGlJBR9wla6zozsdHtFLR/Iz1x8hotR8Y4tCQT5ynfmP3x96P7x98wnyZhbsKU1vApIub4J+RP2nf+Rh5KmqJua7PMSP0pP2PZFWSaLFJ26tb1J5iJixreb4J8ql/Df2Y7pmhKTx6dY6G1W0Cp76OL+aa3YDdmIQY743YDdo0m5xCpGDuQrbR9FeEp9hP9FmZDRbbYb0SAdP5lKHb/yP0pO7XxbuR924zZCaPex/0pJ6aaP7p8dpEpCWVSEptP8cdjnIP0H3DBzeDNZ933bTfERIrhLP4p5VPwyPw3VR9lPvzx4sIJ9SR4p8zOeLfePgE8+EJGi6vNBDyTx5+ovCyhIP9E6vPnF4jbF585SoKCTXYh9QPh5/UgPXdVUeSe2rWhIUgDSZYP0PdV2KxIwQcAhkOr59eVBH7YPkXQL9E3fB90SdLIBF9YvtF+gKLUFQv11LUvQl/WEM1cfP8xxHK3V6zQZv1UvooD2ogB/Kzoc+mmGuzv+5nOf+1+wF7qye2rNGrWEUitCKqBN850AMIycAPmTth+wOn/2uw06T0v4Pvl9mzAOTqvvHhmvu1jv5Otp0vGAw2LBTiw1EavgKdH37V+0FzGHISs1NMFv7CripuJsFvOMvi9rwEw5o73i0ub8F26EbUa8W5tKYuOvzJFA9N7xRbETXOvzEXbFy18SS2QKKF01+fiuNNjQw1/VY0N+kFzV9AS9V+rbC8zebWN9hFnmHESxN8tbVGFGvsFOebcN94SpNO2BLrajnvCXpp6M2mi5iUqYZ1M7hSIoUw1hH6vy2FKcT8U1voIsy820YllIwuNG9PYkSq1Pfkxw6lv6197itmEUw518eppouRkbjWDi/wbDv9mHttypBuw/t+x7OZbgi4d/Rvo++Rv4d8IMfPNzLTN8aFCWG4dwN/lF4N8216d81Fw2FCSonFpVpBPbi0vpTFtWEvioGNzF3AVF7KXEFNYd91vg99v4AWFyCjfZo4ioarvo0b6Zx99LF8GHLvnE7HFxmG8wspM/pid/fT+58aICICJwj1fBaFTDFW5HaUHy3tY+KeFeOWD+1w1a8V1wYhwflyX5K1OGv6+peW9kiXFW8/Vb+5nZEfrFeXNh681Nkk8FRquH+IBuGRSgj8FlYJgeoJD8s7c+q91/HYZj4+lZj46s5jjk/WKZnYKD4Zzjwlj9kftg4if2eHTl9vdg3yIrExGK4ye1LmXqHoG8l8r2qf6uDqfjxyafhwoAcE4bXelGlmbFaC8Qoz9Y01ozTMic4qf7woGfljD4cTT+2fy2n2fqz29c62mzpXT8dcibPxlhz/1c9pw+f1z/xc8+Q8lzz9DczWD3YOz3TcgFzGAlz17xDAoDqw7yIwDWEY8sYrboDz8gw7bkDqqz9new4S3cwvLDkJWkfmCOljFRRJO5e2s3csYq9wCL/YxDb2684L9aSXz9uf/z9+AlT9LFfL8zkDT/vc93seA1r8zFMpC0eor2pcwVUhfwL9DfymmwmWL+Lco7nouWWmte9bndfoWnaQLDZtf0cgTf0L+Q8qXANf0b/vFRNCjvJL3VeyDbjCKr9fFeGtwbF6nMwQoFi1j8hJ0p4qPYMr+hA9qSfA8793f5p1fyI47SAHb8Xfsz/WT2vQ7f47+Fe3b2sgl6kKCOvLrenMvpGTb8Df7j2pcoHVWiNK42fvIwzfpWlTM32kq8qqieewH+68wvwpl5kHgfTHmedukFCjVEHpGPOmE/970XFBb8te678fpvFQBfsDJnfpwRI/yL/8043lWINb+jf8QePXtk9hj4T85shNRuvWXCo+mnma5fn8dSLH3C/4xsDl5Xhs88LETloX/ybOT+YugVttzUEo+7LvcVhQoKq/qkc9OWsKa/gPbtMYkLlBQkmJ7aSrSLZ1wMuq1rW5h+Z6kxPYguc0LC3rmFVru3aSdYWPsjlffO/pZhMSR3bFKNUI+BL4kO+S3+ubNubhFE39jt2KLnFNX8G/qkIq//X86/iGHlBdPnd7JZ+O1cN5cSztJZ5rYNa/2CBetzP9f7QkA57I39p//AfP7BP/J5/ej0uJLbM1fUpxDliAO5zmphCtvZ2/rkGXDM3YD4IP+ds7vbGVAoId/xvYO5zHzrIMv+hi7jWF/miXAtZP+5/rPYzhXCV6/yfZ04nEIj/lXaH7QYKl/0vY37Ev/oc+vNDHK3/GMhvZb/oP8t/7fbu4xUIx/yf+iVcRo9/vf//HojtLLrEgnoU0cROLxwh+e/9vusA29Vu//ljiHAtr2QDP/ma9OkJ/9EHMdd5DU9HJpoUPzKXIACP/xAA0Jx3/zoOYMddr25/KC9hP06NH/864XhQbX8myV8IKhAQBnQAt5R7/2FAPj8Qx3gA/a9EAJwAj/8e8QwAz0cyANQAkNRsAO//CACmTx0HM8MhH2F3bgNAmnHPZywaAxiqWJ4vOmcsKih0jmnPHgCz3h0qL6tkhkduBzJhALaoXm4jKi1rPwZibmyyJLMnT2VXHw5x0QNKBQCx3mcqFYM8xhkA/g0UGSq3ZYpJAPAIWzcRAIsGcKoqa3D4ZY4TAP+rEwNZALYA7OhjgwUqSttGhg1uGwDHAPiNMQCnRlYDQAZ3/mFrDQZMbl6aWrNbAJyDC3cB22XoZEMhAKdGXC5JALcA20YIg08A9phza2zLRw10/niAwyRjAOjParEejSZuFF9bNwiA2LwpKh/TEMYcgOcGXUlb4QboVSFzbiIscOs1mkduU/V9sQSAn5B7AKdGZoNzAP4AkIDl+2gZU9MQgPa+aBkoGmg/FusbFUoGfzV2AMdXefQO5xLoRRBDjgMlfoCt/F//GagJ8HGA6YDQWiU0dlt1NVAAm/8hgMZbOwRJgKswCYCJ60EfO2doJRcCCvVf8lETa5YE9QjfMxomlTOA519cGm+ZBGtBAiD+M3U5d2sZPplZ0SA/FoYN9QA7L2dCmQP1KDtngLNZJrQ+8iJxcfVeanp3PHx1mQ71Z19PGSiGNXUTgKOAtmse9TemBRI1sQRAvY5NUWrfBQtrg2TUfbFIMWFZA+Itt3d1J3UgGUuxa/8fdz8QFNIr9Xw/YVYqPzDXVD9yQKYNXtcyQLFQRA1sPykIa6tUDRz4QyV6DSpXAzROQPpAnyV44BANAk9wL1ZPQT92T1FlDepLZ2ZAzgghqylA2KUcDTKlJkDMDXwAuADRQJ5/cUDEpRGGGg18pU1A3ep3Gi5AjUC+QP5bJgCzViosN0EywX/hGu1gSiQEC0CPZytA6kQkEUamCb4QRRspbaZ+E2dAtVtPTCnea0CgRkdA6ElzQJ9A9/ZoSXtAoEZPQPxJYMCqESn2PL5vQJUxSMCffHiEV9cIsEwMDsFwwP1pGcJovniEVHd4ME5gbElsrl9bXNRc3gbFbikVpzDA7pAHKWLA+cE/6mCxCLBuklWJBFg+8mrAi9oFIVoEB9k6aQzVXMEH2DPJfnRdE2jA7dZYwObBf0CqEVr2QsY5BHoRaWkcsl/BbI4ysR4sJ0CUwM/WRfYlSVnA+uAi1Qd8DMCysWGTOd4RwLwpGPZawM2Amkl7aTw0ScFofiZJe2lGwInA0sDJsVr/VnsewIHpA8DtwQHA3W8V93OTeMCRyTOtHcD5zhUxBxInQPvAzn86P1/dW5sGP1PpJtUPwFvOGjsgIMdJIEtRNiKRAUgmBF0OXYlvOSYEI0D9gJFCQmQQVRt5F8CUIOamNZoXwOBoEgNGjwIRUgYKAywg+8kc4ntcNCD0b0jIbAcBpmU7Mm9eJHYzNGpYTX5CDyoPM0vhHCCBAy9GaCkSIPUDLYJRb1ogjTNw4kgRaxwmgyFCM8lIrEJZfX5sER6CCkN2INw3YcllQ2EgsVts9wKzUGoU2whGAwMJfg91dBETmn/TTzpo223nf9NSag1vRWRUIPKIQNsdNBBZaoNfWym4NkMsOjKxPWE+Qy2CMVsrUiD+IiDcNydMZIhpLlsgwxg5g0x6Djd8KWh7cSCqN2ziRINvQm4A2kYmILeVUhEjIMwg6SD0sXj4ZFkXINiguEwcphsgpilJRmkDcEpRwL26aENuzgNKPyDoQ0zCM8k0oPcgyjoHKQDhA4MeghspOmpCQxCgjkYRZDUg9YUIt3TmIYMwg3EROKDnIJig1SkkoIIDZXhJNy8gqoMIlGFrW1glg2lDNbEhoPWDS6paBV/4XiCmA2UgldY8zHKgzjpVKScgo6YyINopJ+RVJlWg/zFc4BnTeSDON3qgv48U2z5AFlkiM0mgo6CngxGg3jNV5jUggaCN2WfmSiCUoPzyJqDgQxiggO8quxPTapEmLmhDHyDzRmq3MSD+IL8RS1J9hyNDWds0lA2gjqDPRm2gyDAAoMnbLSCApgd5EGC6qH6mEwMR8nzGM3xlAwl6ZbZ8xkr8N0MdIKg7fyRXQwRDKrdmrnpDbi55EVDGarw2IJ9IdttHDieDB6Cl2wog64MEoNi3daD/g3Bg6rcgYLpg1LcxIIyg6GN2a1YgiKDuay8pQ7MXoJ63RSDVswcg0WCDmWGDCWDJa2Ogm6D223cwCmDHQzJg+skCYM0zNXcBjTSpfHMrs1vvKsMGcxBzfF8Xd3xzZHMO2GNgr7NAXxwfa3dFxjuzJMN7d1WRAmZ0w0Ng6KlgH1hzXY5X7zvvcsMP7zNJGB9dVTdgwPd0hVdgnsM2J2QfX0NccxeRUODOby9g3q9e/WDcIODcjBQffsMDdzPMDal9YNzgTYVf7G2FBqRl1w20Gh9FtHwmLnMvyB5zLK0hXxXDMyc65HFfMH5DqU4fOVVJczlfKN4Zc0VfOXMl43FPGlEr2nwGPFgdfTsvZlp4biSiGZwi7h2neIN/6hboLIM8wAZZHuDeolybc44NJD2DZJ46GgsaDrNqAnSvY25ImyZqNfF89TeUFoNbCDng4XFb+w/jc45UpjcDUeDFWTiQe+ZdH1r8JXER4L7g5KAL4It9dq9zKhPg4oNagBSadP1kemm6JK9ZcRD9DL5t4ICQGYNttXkaeP1OallqEm4B4OEWCBoH4MBDDVJxWhfgneYu4Pvgpv515lgQzyob3hrRZmpshg3ghBY4dXVaZX0DoiTGYeCqVkFnaWcqZ36qUV0GG0A8BZJ+7g7KDucyENZwSpJs1yIQlu5KUiVnTeRH7Hn0VYZUCEY4Bg9UmF2GALADhlXXZY1VtGHJM4Z2EI1nIG4bhjIPQih7hkoPFuDdTkLoK6oT0z/6SGcF03BKZsct4Ni8CX5qIJbaUQIdXGUQ9sdptX+jeRCSGUecbdMdAxreONJbfi8jWE1jVzkQ0gY/+mHoASIxLjkCO9ItELvTZQIsAIigkIYBPlOjA9NgBgivVVwbELf3emoDEJvDQnAmfG8Qorw4/FSKfX4jPjv3LDMLYEkZQVV7IiIzbXEEkOKggXAMBnLsWJCmTFjxCJDxoN8SGXF6WnkiHtM2hlAEcPIHENAZSeDVXB0Qm8MgPGMQyXBikKBPbi4WEQUGW34ygAIZUzQEs0E6d0o3+msQxSRykLkdfqDekJwZazImBjKQnBlyczBg0FRpIwgCLxCYMx0jeeRNs2sRZpCEQ1cCBQZx0xRDDiJoGWKzW8MPw2GQvxDS6AUWbpDYkPHALpC1CQCIUZCKGV2Q7qDWkPetEK8JkPfecJtlYPkGM+DjeFXMFZDnkLdDQCMKqgeQqJDZGVuQpgM7YEUZCpD7A2uQihlBcDOQ/xCKGXJcUiDleGAGZyJYkK65NiMqXUSQ18MvkKRQ1JD5OANtOFD2M0aSQiMoUJHTe5DTkISQc5CScQVvHPw//lhAHSNdpGWVJpC35mqzdixTENjODpD6UMsQ5JFXtQhQhzxfYAGQkFCFmQ8GIJD9XCZtb/I+UOxyf+o+UO2yHi8cpnZQi5lMmmJQ7bxIEJWgvJCiBnNQErVfkkVxKqARUJqzDWD77Rv/G/oywzbxal4dUP+ze/oKX0EsA1C0cwj4cZFTUNhzKV4LYO9hMidEw2W+C1CqJwJmE5Ao4NdZBiczUMrKNCdr/QLDc1CbUPROTidfYM9Q7E4Y4NctV1CT3BknRsNWVXknCNCQLBZcP1CNHBjQo9gyHRjQg2lGXz3oMidRwz76HPcP/Tz3VnNc4PHufSc3XljMRNgzhTbwZh8xFSr3AvsLJ3YfdexrJ3FzXFs5HR4fBuDVFSbg+6lpENbTM1Z7WmOTRCkbQJFiVHEe0IDAvtC3zxYbB0DXqkkTLtEXQJnCbU8J0I9AzowVcQHQlTFqRGpxBdDt1iXQ8dDVfRDAudCbTxHQ7LEuREdPFdDw1nESHnEN0JUxb/YBcR3Q09CW1HNxSMApwOCcdM92yjzAoZJK8QWcQNtQxWZxL9EywK3Q7HEie3MpaEVn0MUSesC24zMTM8gWwP8ac3En4BARM9CbcQPQ+KU90RhxQxkYRk5FF3ET0NTAv64UkxXQxDD2mB9xFDDP1iGYG3EL0NTAiPBQ8QfQ26D8ByjxQBYiwNzaD3FkkVlrEDYF0TmWUcgtwKowlJMb0KYpfCxyMJwwkUIh0OOTAjD14SvQ9ZNItSYpb+Vp0MppPCkjHHvQkOk9wPEwsxMI+GPA4TDRkw/QybFiVicKeDCXwIEQSXEV0J/A65s/wPJbaFtn4X7xdj99MOv0JyAfsRBfa/R5AGY7LgJzMK8wRCD2D3tnPR1N70JxUMInhwcwnroyLieHQiJ58Bs6dzCpO1lSY1xvr38hDTpYXWyRb9oVxDiddw80y2RtQClwRxeNUoQ5nATQZDYnWiqBCxFQsJUDYIl/6F7vW1gvHXFlIlhtiQoIOIgNuhiEH1InMIVFeY8tEjTxZzDIOlcwjpNKsIh6LvhAERTvImMrhyONNzD1awEeUNVtuh8wgzs9GBpvLrDwUygSaHphnECwiNow8FywwzomsJS6LSxMsJ2ye1MpsKYGF3BwgAxcCUAg4lT5L3UVhyZwWuhyQkQ/Bp193iSgRcJtsPmHUjVisJdwZDY0qiOwzxNasPtPCzF17Tz1YNp+2iIRVLC4iFe6fA9psKew4kCCEL3dV8Egb3nXC/Mprx56GYDamC+wrOhQkDHXfUc/rynXbkCGdTGvZa8IcPuLaHCO3xf/T+cv7QeLBhgQcK+LayAVMFgQIUDbOQgvQgDnr2gvHcpvsLw9LEtwcJ+wjAstrw3XSsdwcLtXZUCSO2JPHTDyOyrhQnCs6EJaBMcGGFZwmMc+rwRw7D0SynboNHCQb3k/JgDYYFrpDwUbfEAONjd1bxi6MXC79glwmYJmaj1qJQVpO2s2E9o/dmhcA7xB7UCZJQUFBFXCeTp/C0mpFZAPBVwaIQU0aR7Vem07dmopSSB970Z7Y3ZCRnEwNu8YGTv2WFkr7S+A2q9BXElw+XDctjdwuXCcQNRjYXD3cNKGGLYvcNRvJwZKYQ/NEXDteQVw06lmaQutSPC2+FOGeW9bgX9CU6ltcOdvLRkbcO0/MmEfAncCJwUJhHdwhBkk8M/ycPDLIljw6TkkQVU6H4hgoiUFQbIo9haWSQ9k8PKTQzoz4SElWAoHpHvaNQYZ9jHEc+lv2nbwx3ChQAJvbvD6hhMzJFlZ0lrwv3YncNZ6CvCc9jDwvPC+C0V2P3C5cPzwnrZx8IHw9/p08Mn4EfDCGR02cLN+8MsWU4tMCi7wyxZKi0mpVvC67zC7fYk3lAbwvzoQ8KrwyCZ4sM3w8XD8v2Vw8AhmJULwmfCPKgpgXoCkyUUka3ANdg94D/U1Q1GA8ZBq2i4DEMlv8L5wX/CWQK0gf/CICN/GD/UQCMAIuAjl2A94E9AbryQIna86cKevKFsFmwIvG698Tw+vX/M9ehDyNMkUCMII8/MAbzAIioV6APANWj9tMLyjf8C0PVOpL688CKgI//UV/C3zFgiR2DYI3zk+7koIgXClfyEfDUpSoDGcEcYqOgxcCQNsWjTWJj0VfjA8GYIG1nwQHoAw/go8WQiAYmYrNv4qlk1aHAdufAWVCQYDU1IHaLhXfjBCFFNc1gwcWsJApgfSEuIaBiJhMP5h8j+CEQirCIl+atBauRMI8+1I8nQQZ4l9CLUImQsfQnFdLQiz/jSQCQi5CNUIvU5DCKj2ENYyQkPQOf51nCH7DeFQXEUIoQjauVoMAag4iI0Is6VaEkimHQjrNmggGs85/l1SOZxQIA8IsP5s1mr2B0RQehcIl/4yYRKIi6Ew/jXWFtIXvF/fGP4lCOEI/f41oXhyLaoUiKC8C6FP8P61AOJ8QB00BhsxLh6Ih4sUNARPIF9rnVsYXXQxph2ucYiPQDT4DucBiKQwPoiKAXjkCYi0IjmIpZ4ViNc0U1VpiNZ0VYjGV34I/YCV/Dd0XQkvwiLmYDECiQuCU4iz0U54cqpnGg8iZIkqlg6DHNEd/DgJGiwf/EMfJAkbiIKiaVEgmROI9KJviKNbT4jNAmFRPooKmEBI/v9w43zbQEirAnDRAEjmtisCYNET8giiFuUhQDPbKshf4KemEAlsFAWDV2M0CRSqW/tkkQjbfWhB5mBIn4iIqkXlHEjtGW4kL/tdpGkZatkHgxRI+RlUwFuDAPF08jhInwI90XNyZrYEgjbRcRlfiJj9e6Ny2z5In/w2vhYJIUjrDRZI0Ei2SNjOGxkPIjcDEHDoig/GLDIzDQFInHwPxiQQd/IsjSxxe/IXqD+nTvQrWwZHF25xXD7bSSRGAhoQL9szL0XmM0jsChv+RacjSNcZfCVTbj1Iqhk0SJ5DIdFYSI5DJlE4iSRI2I0r0XHyd/5Np0WfI9sHSMVqDOon0TdbXuIrbhOfTEjehyO8DOoCcREJE0iW6l9IrtsPchGnTm5wGXCqRUMObXuIokjGQwhI4dtRZERuO0jVSIvcBRZ1+mOIygA8kXLIv9tHB0uhYsjgOzNICGInSOHbSX4W6n+I1kiPSLOIqwk4SOTqbPFzclyyBup4yN8JIzRSwTrRQfIiLGRnKMjxyM3QPJE4yJVbMkdvnF7IqIlCyJ3LdMiJWx1Irq8L7xkODAi8cKwIpJsh/Co7NJkNB0OQSnge8XoiYFgjyPPqPLRMmW0HG41GAKQgvLYqsXgreVxk9lM0ZCtf4nF2YzYnyLPzDnBFdks2SQE3QW8nXYJK9iKTI4leSQv2M0jzy1qIZvY/MIkrS2knXzDQaZNKK3go8LYUSM9fKvhE/WN2KxF3y3Aoz3Y8tksoSitOfX2JaUitcwQ8XLYSKPjzBgQitmL2MSMQqznff8iM8xUkEwtdNm/In3hdUnXfL8je812/K11i9gAopKtVfSL2SzZaKNbzDgsHNg8wbYlq8z1w3rZVxEnBIEwYKL8xdKsi/Rn2CiiJK0F9SiVHyPnzRX1lSGH2Vii7RyX2TijB80+cP8iObQzzQGkeKKEo7itL1GAow916819EBYtN9iEBNSEbNzwotVCsGmAhJSi79nCCM987KObwkUiAqyso+zZ8KLDzMyiRYxUo9KtfyOD2MKiG81KgAvDAXl/BcwEX8L8o/iiXyMAOLyifKyidOd8NYF25dysqtlHfE3ZHKJXA3KjKJUr2cSjrIQyosD8LKIUrD8ilbxMomSsEqKG2FijNKJioj/CSQMRPP6haDgn4K0kvtnH4X/NRgMYwPHYr8xoOAajeqMgIpdBCDjPzdgjxxnGowajIcOipaajn8yGo8fgFqKJXAgDVQIQA9UD1DgALXQ4mdi2okQ4eqOQLXQ4JDjj4CAsiWygLHci1qKIAjai6djwLdAtVqCx2D8F6Ox2ou/NsC02o56iqCJ55QXCHyNLmOeC1dRM0DXVQWV1yDWAddQBopYkSykN1IZJkSSOgj5ZHgLAOPkBQRRz1VKiQ12+Ar2pRUFFrf7wXUS92Yw0CQNeJKGjdWRBApEI8tiL8KHxJ8iBoptAI9SWJb6i4QKQRNbCHgK11E3Zs9Tpo5dx89RW8AgUVvB+owDFl9k1FP5kHEUs2cvxuaO8pI3Vp9Q5oiOhI61lZAuphEEBrWVlS6jj2SWiRWQdrEWjvdQRAjkZBaPb1B/xi9j5o36jEXkoacmiYCjZoo4CSaKZo/fUr/E/w+UIz9UmrYLQvtjNo6kDX/3DXPdBRjC5A8cZ7aPZA1YDSQJgsHk5yPw00J0kHaJGIy2DbsEFIB2iNNCdowUD0CJoI0lsGcNJPKslX4CtorQ5o6O2o/2iCwxoNBHYMDWIOWnDQ6NI7cOiAIMjo28IdQLjokE4mmBjo/UCk6J/1WzCBxQjrUbVTEHiIkMYmKNivBxJ8L24MXqEbOlron2tBSGovHWhaL3B3RFZCfDYydtteSXsvaZkJa3PkDi8x1AA7QejeL1TARq9wdygiCS8vUExg+3MrL0iUPbcK+h4FGmhB1nroptAK6Lro6ujl+R4sNS9nLGYtZK9h6Kl3FspIrzMMD0Y4FBrotz5Vt2HodfkV9yKyI+9r6PR6YpRUr2csRiAL6NxiLrFibBPo9KhWsSfuUq9xbSdGN1pDL3/o20YTWmkFfKh26Pl3Tuj8LC8vZyxOMUM6J+jja1/ePuiKEHF2SBirL2JiK+isLV8vU+i/RmQYcvwbkEcI/Hd96IIYri8J8BHNA+i8yHxKc+icrzZ/ZrcH6IyvL8Jyr3x3JrEaemjzINpmGPLolmZzL2cschjTEBr6IhiIgg3ogBiHyQ66HejhGOPNPhjV6L5aeeiV3A4lJBiOrxzodhjYGKno4ZMmGNgYqBj+kHlaHgCdIgscd1p8d1zYQK9D6JNo0SwzrwMlS2dprwBw8pZOwAkaLYCbr1+LUajPRnjgCxia6zFQGxjRgO+rIG9LJRbDaxjoSxDo4UCufwuo/HDefzzrUxipCmPvUJiBDnCYy682yRCY6Ji7r2JbNOj6cLoI3TDsCNiY768YmMowN69UyUiYzJiYcOmaLcMc4E8Y96jTwyqlesc9BB1lYuVux3KYscl85X1XN8lKmKM8HscoCnjlSVdJzVqYgccHZRXlPIYGBEHNA8km0lnHJ8lgBgiARccVKRXHbC1KSnXHYOVT5Uv3eckfZUvlfccE1SjlLpiTx0WYuOVKmM73ScALTRopRDJNmKxGdOUdmMfHdSkseFMQwpg/jW2Y061PxyLlbZifx1mgbYka5V+ZQCcMTXT5GCNDmJRNSZQ3kIjgcZjXEMoBa80OyEBQgxxhKXmgr5CJaXqYx9B3sNAvAMlLUNktATwLUNwneK0w0LJyOFiNLWpkOFidLQRYmRg7ULO2Qy16uCdQ/vkYHUrg+v14HRgVUf0C1CRY5y1IH19onwgA0Ou2ZFipq3zDGYpJ/QlfXqsI0MwKSPcWoWGyAhUArXRYlwgWWJCtZNCOWIYVcljHsxUnDNC2FStWbND2X1zQzl9lX1omNFJi9xOpARUy91GWEuC8+0rQsV980JcIaR1irUYVOuCy0N4fRuCnJwEfT6i7ML1ODm06GmPEBbUzWMaiDdAKuxabbjAbWMtY7iRDpU9MKrVp4JtyfJtECgOyAXco/GhwVBti7lAiDdAL3n9tYFZ4hBdRL1ioIg/BD3UvWMRWKcEjPiZWIvxjxH3rQyAm0AtY1LUrWPdAVNj7CnvuPXxM2OrtQf4YuQa+PU4JIHtYhr5qplAMV6VrGlS1bP02+wOmT1jkEIX3dzBUG3o+DqU5xU1Q07Myl26IuQdvUkmolAEP3AdAbtjLGPWuWxg5B19wEJdO2PwwAdi5iL7Y5YBJ2O1VQzYJ2MbMQdibzhikVBdZ2OpmFdj8MFDqBZdiPw7YjdjlgC3Ys65YOnXQA9iATgCbCsASAUlGORdYOQibeVxCED3XPYCTWKFBNV0TC2P8QxllxQOLais4mmHFOgtEKxZubqNbIEkPCQINxWCLT6FValZdKV1noTx6Y8UhdVvLOhwLxSk4QQsXoQliEV1YQFfLHTxJXXIQTKtJQHrCADjfyy/Yol01Cx3LVIZn2KK2J9jI3X8LMjiVgnyLIitiOJDdH9idy2sZOjjCOKxiPHxgOMOyTCsIaPA4jYcHYVy6AiVqOKRhWjic8kvgT8t8OIDdYosGwEhhUTiK3WSLZcs32N02ObxTyzbbHOZq4jIrMDifYxrsWaFeOJbzNN1sfE/wzRDopVGNPIAdNWclUaj9OMI9GYYLr0s0Jdj44QsOKzjBqw/ASvZrOPMIIzi/JQS4f/U9dmxwgnkAmJ/dZJjGcJbxJ25jOIgg125AuJilYLiIPSbJALjwuPiYs6jEmMwI+gjoW0i43KV0AP52HzZkuNs4xzjp4RQNDziS6JpRBlUu9jsIobZ5indzDDYpCLy4yUJAiNiIyv58uJUIyrjCsHK40ctcwkr+al13CPqIjootXWMI0oiMznv6QRpjCNEIqyZ7QA+CArixCOl3VvYRxk642FUWYjcIzAgCiKK4/KsfCMErHFViuPA2IIiyuNkIjojTCIrXcrj6/l/HY4JVuKaI4Jx+uPDBWQijHEO4j3InNheEc0x1gBj+CMiS2HXEOcAaoG3rephjXDCInbiuiKucGYjNiIedBMQPuJ8bGkCO2Pe4nYjPuLMAG50JMEWI0ai1Nx+4na5vuMB437ibaMt7CHiYeMVVRNBXBGGI1g8sLxpRVwhy6LEY32JHNE4Y4BiyIU+YlwUm6Jx4+l1TL2/og24tKxPtFLxIjiFXFqdCOlvojo1SqzHozGY/pyZ4p3kaEkavV/B9KwPoi7w0p0p4lO8T0Cz4BAJQNCL8SRjCIXEMFwVseIJ4sadv2il43lchYVZ6Ynjdp1vVYToleJkSXqdZePx4z/DlEgiYxE5xP2GvJziPiBMkIpiS1zxAZxjRqNtOXXjb5Et4vJjDeINIAj83GLXoY3jbeM84gT8fOJOrFJikm1fwM3j7GI+IS1JdeKxIf3i4mLqhLWR5rxSlZk9/GN/A3ziI6IqhUPjK4CdJOuEg+PSYxPiHeN8Yj4g4+LcYnLiZEI12WqVSYlpxWbk2+zz4tW4C+OgSIDcSGVIaDqUbeTqiVJp0ZSr476ohUiUWIHAJmIr46fsi+LtxSwhp+zL4u3FHIFOlLviScQytKAcJoD5xM6kQZT74/w5ywX37MfjCjm9lH9Zz+VSOBgk5CPkGUV1DpQ7WRXE3yEb4h3kMBnX43vih+UWOZfjaB2qKOmJ5+IBlVC42I0hre1jy2mAGZdtKGib4t3F7IUH4pckQ1EOxO4ktxUzxM1d0ZTb4p3FzVCMaKklnyXToeHk8iKQyCZ5C6Eb4oAS6qlaozMcco3d4oT91QKtaJ9Bc2kHxb7YCBHWbHIY8RDQURAT4BPQErPi8mRyGUbUixhvDPWomfQaZG8N6M3wEnZjSBJlGEhkLgj59R0YQI15NHkZIlAOtdzMcxilZaBl2LQZGA44XpX1qaFkMGQ0iMgTTrSsiKsZTMgoEmuwNnCkqIM0GBKutQqJp/EoEqBl3yjN9HgTVGXbTa0ZBvHGgHSIFRmliH60t0yzqWgSOULWQsgShIycRIwQfmQijYdNkxhME5Us+kjV9RQTVmX4tMsYoGUbEbgTiBICZWAJZBICZFqVJvnnNKHx6BJzEfO5YziD9UUcFXD043Ccm/S9Q2f03/W5Yx+10Jzn9fVCQhP79WF8E2UxY6soSWOLsXFiJ/WNQt1Dh/X++Xf1mJ2iEkH5IhIwdAVil/RyEnid6WPyE+NCn3BZY3Jg4HwUnACZsjgyE8NCihJv9Uh1o0KaEmEhH/STg9NDCxzBRCISmcxUMFnNpWI1Y145+HURRXfNGH3lfCvcK0NYfIYTChJXcZ6k4JilzXn59WJbQw1jm4PR4qpUcj0aicWUkcV2cd1o2ZzBQVetdrEriQCJfZhmme9ATUwSiADdYVSwIK4oAAx2Eww9ApxS3BlVNJHdnK4S8uNmVIKdzCWDccq88ok1hUHIuFCWVbYTlAnmKPYSThKIJfwovUwGiJ4SjHDOVO4ST63YscZUgp3BEwrAPhNx42CI1ih+EsCI/hJj+FzAJPHEiWmwuuJZGWmcJAQtZGAZEROxEa6FWiKYqR4T4gW18fwo6U1SiAzcHWWl3PKQEomrQIaZz2mOE5e4EiRxVUETUInwrKyZOl1eVbCIlNx0Kfi8aoiY3BZUWRJeKcWVUd3pE37x/Iih3GP48QmOnJij4RNxE9Tw2gS0aI0NIVVhnYnFqiJeE/YSQoDpEjtZURKjmRyZ9YkBElMUKqiogq0SDhJC8dSCzRNOEq34EROenKJ17tX4gmkSlRI1KPkToRN94LYS1RNWmB3ldRMDEuX4nqlVEoHd0iNdEx8Is1mtqR0TWp0IiUUTTRITEqPpnfHUQ8kSXzEpZZGDjpwQ4LrVgxJfyPUS+tWwGYUTIgRJKIwhSQmJE70TpQy+VQCIodz1OLDpK5FrEnYSGxPKQIETVLj+wN7w+pz+3YKZWLi5E8ysdtWrEmGd0+nPvTWC7yNKYwXY3njVdXV849nkMb9iTxFfI2cSCOKSnGcTGC2XFcTB7NhFok7otuyOYXXYvyP62TcVvXzEo6Di38HNwk3ZhC2wlB9gEKJpQCQsV5jfIQ8SsqOPBAkIdxJco/WAcOOpAD/ZFxLGCV8FyKKFAKcTqKJd2EgsK3Sy9GLZJxLo43YwJtlRowCTwcCY9YyjfxKY45cSJaK3EnOYbyn0o4S19xMu9Bqj/yL447fQoJVolKCSI6EsoXMI8JPbCW1hdxOXiWDUbPSTwkCji3SCIUtU49mASLl02JQ/2OR1U3VDqXyin4P5dSvYdYWS2SZIxiy4kiCjSLxqLSvYjYXt2Roti9lvVZLZPxIrdHzwN9gAkkiSREBl2LKixJLTdb6d7dkGLCt1CJISgE2j+qIpAfSUSDl0kkzjZqM+2f7YMuMWogzi+qPGovSTntjZ2UySjJK22bqjXOMdo2g5bJJdo6ZsVQOgEsUDadiOomyVHqJskwyS7qIMk7JjOdkCk8PjtyNi43cj4uOwI66ikuK0OCkBCpVik1zjeDgqlRX9dB0fYyxNfAOVuaCFNJGH1XMZvwS6A6plvon0cIYM1WRqNDcYG9TlZH+J8gBr1SBJyYknOJw4dmQxuNKdLUlDuEvVvbhV8As4WpNlZar0sYkGsOplMWUEte+I3gwhZFo03yFNDAHI/DjCcVSYbBLuddr4WmUKkqlMXgNXSQ2J0pOEmfplkej0IQQCCpJJ4gY5cQOcE3ldcpHKOLaSPIQOkiqZppMhncyDhpODiSIEngzxZDo1d7wdDa7JejVvtbq9Q+mWkSE47VzXoJnB3pMRwuBcv7X8nEYYPpMROT9QAZJ+k7RdaJn5wPgh1nHrAJqBN1zNneTBuEMwYXhDXJOr0KxIThiKiKaoYZJEQpF1wREkQsfBJEJtndYS1X26YPXM3NS1fa1tgK3LIMmTnW2ArPmk/xRsxPcseZDNfGFCtdlAga3M5lm7becF9yztff9try20/BCjE8Ug7eCtjen5kzuZnyy5khN8tMXfLTvoL31gjb8tGZJDfcmSuqxjzDd85OJDWLPMDgOpks/MFBAlkxWT8xGT/DWTVZOHoeCU3I1Io2whjZOZk9CtPfSTwtHEnGUjBJ+5S32o0atQCK087CCS9cVVknF9RxWJkkStJ+FtGey4w82tpT99LEEXbSitpOx4onHFkON9zEpkH33xqe8s7elklRSQeuKr4EDCJJXnZbitzKxPfemSZK0TEpmTNZLYo71i8JVzkzex230xwt1hAKLBQUcVU5KrzSKc53zLfF0gJKNTQyiUpcXQqCSsI+EbkmVgcOycrauSwPwFk2OTy5KnFBSM3KJTzHP85liQ7dysA5J3fHoJe5MUSBWT5OB9CKvgLv2jknmTKK2TkrgBP8Pn4fcYDJR8wMkA7ePXklMkbHEZA4/hotHcYreT1xHw/DslgbwcYscVEKgvkjBVj+GxQV3ioBKLTTyTspUPkha9pQMQEI+SWPw/k9NlOkH0KfcYMgFToyPjaCI94vzjEySIaXQROThdwCBTdQM7AJOSFQLvk4G9sBKGJGTdcXTvaQA5YW2/YtBS79gwUol1asXlJciIuJU3FKgVps18ONjj5ujwoniJ0JL8IZ3ZKk2PE8npAti9WeDirClPErWQHoVvE6hSYtnSkjDjyFJn2cwF6wiBUP3YUFO/YvBTS4ykJL8SAsSAlJ2NNywPcbhZRFOkUkXpcJKkUxCVX6OD2HBSTXXKrOfDzKwZdbWgeOh62ShSuOPmxUuNRCXYUxzpQ8OGJbNJa1TrdQRTNm1jdSXAR1XWzb6EldiX2YYlAgGvVWiUDGNLjVxTaQk32bhYTaLusELi22i0gCddLNG7aJHDL/X8UiyVAlJOgWQJopVCU36TwlOCUpbQolMxJGzV2tkAIxJS0lMWvGJTCPTiUsGSwpKAUsOjo+Mzol7F0CUC48doo9yYwCD0aO1BIgJS0yXmQmyVbyI/dcKTAmL3Ig69SlMiUtMkbqg6Uj68ulNylapT6lJ82RpSSmIajBgFxuT6OKQJyERT8MZSTBUY5N/wqUgnvHzovXDtleZT/MOf5JZSs/HxIbw4z+SWUx/xTEhVtRCFHZhcsBW50OnlwOCIFBBPtKChQ5UxuCZSdlIZ8D8gKb1mUlX1AuRFtS5SgAhWUhwVkLj4iHmQmbkhqUzxhIhNBaHo1lJ59I5TLeR2yFOVa7H3vR5SC5SL9BgUvXHLmNEox3m2U9KJV0l0aG5TbiM7sf6MYelBcV+ZDskRUqoZsVPBIgxIoBShU/movUFO6IFTMam9ueq0KVMuDAn1AOke6AagAwSmZRDoRahpVb2pE/VCFQZVDaneUqfkqKG5UvmlVlMBYCwMibheUhUUNDR7gFKjteRs8YQJHZKXed6oruOZqTn0DukmU8+YyVLrvR5TuSLVU5VTblKNZcZSaVISCOxR17RpUwupXQVT5RZTYjSJUyu8wVKBia6xJBjRU2kMIcDXee1SMcRzEWm5nVMniHlSkVIaNZL0WVKRo1I1bz1G6JClYyKOWJ1SIKk2gZ6StyK/tFv0c+niEuxZ8ww4dJ2D0nBGpF+88wwwfd+8KhPScBMNv70qFYBVUw0rgCB0EhJ0lLMMOhTgfaNSS1IaEzyV1/UQfZv0UlhAfCtTsMAbDeXC6FUP9TB961LwVdCd8HxP9FtSiH2wfMRQX/TWFKyA2X36Ejl9sJhlY3FETED4VN14GHwFfHPtJhIFzMuDAlArgzZFDqW3DAlFZHUWEklFlhNjeavsfylHxEAA43BEARAAXABKcdHwCAGnqHAAVHGY8YZS6xznLIBJkURp8HN4XK38aPkJX8CRQCaE9DxH+B9TF3g1XD9Sk5C/UxUkdy2fUogIonVlhdEwQqjd8cwF1YWPrTOAv1M5JTpIgUFf+WDSrxX0ha1oL/Hm3J19/JzPQPoo7nQPFY3ATvF16LdBbCHVhQXjLfi/U0TR4Zwn+f9T5xV2nDX4E/Ffwd+IRpxI0rFYv1LfU2MiWZnt+L9StiUphEKFjfhp8HOAeJT8hWBY+NKI03aE71MQ2MkcoUmOhWAd5gmE0k4YMNOSaV7BZNOQ02I8/ShchXDTumk3WN3woSU+hZw99CGE08jSUoXruPTSJNIA0jyFGvBP0YTSGNKTqFTSL/AmzMisFNP/8XghmYxkSfwiZNIk034l4NIULcTT9IXDnQTSX1LWBPGFf1Lo0nF9FoSC02zS5cBHVMRIvfhp8AFxPVR40z9TPwAPUePxeV1zkVTTYtNPVXggEpCP8cFw7oV006Xwc1xxTEKdMEny01Ukc9ky0zTSYtLBQULT9OHI3C/xPaU9CeLS/1M/AIEleV3SgYzSrEkrkDyFaNIv8DDUDYBS01DSafF605yENNIs0sfhVPgNuPLS+/B5VXLSjNPy0roQ6YRG0o/woATK0iZwQ/jv8AT4pKzC0wbT6tG/IfaTYEB2jCGTnNM1XfbSiAhc+XbTrJF40vWQbiXiibGdKNI0ATagUolu0s8BSNPu08bSFYnY0k6gafBcOOLSKB1yKL7S/t3k0vgtRtPhidTT1Gjx9V7S4NJc03vAMAnhiZTSvNPECb7SMtKA0/7SbpAm0u7Sav0e0xrS6NKpdBYIQoSE0q7StiQkheHSafE/JZhoodLH4Pvw4jhpKRKdQQmZCF1c3U2s0oHSj/C9dHOIZEm9WP7SrtN+JDRI7fk+0znTeik6SJjTkAmWkCEohYgaABLT8OE+KY4IsdIv8ceYZtO60/7SGNN5XeXTXtNw2G7SLtPF0xClcdJpoPcZXtMJ0mRJc+D8EV7SudP102zQdwi3pe5wldMu04/x5xQ4hWbSWAlo1PrSotPa0mBY1Aj8hK3TeSmHgahJ0dM9bXMJ1dKa0r25sSm5057TmNISoPXT2EhO06Pw6SWUhFv4OdN0YLXSmdIyCF8w/VRtwWnTbAmnQCNV4oQp06PxVdOEhMTSdAhw+FNo/NOKCeIEnTDd08XSUcmp06XTo/AY0ovTo/AA023Sr8m80r+ANqEihaHT7dNRJDcFImnB0qtRYSmj08zSj/HG+E5o2dJd+SoIxyBGiJ7SI9ISodM5d0nYSfv589Pr027TldOwQRXSndOl8BJoRdLL0prT19NoCL3TViHZHdO4cgkSnBjg4h2rib8gidOBMHIc7sHhVFGZhAEJyYnJ22Jv/VVc9IF10wYZR+0/cF/S27DI8J/TwnDoQd9wvWSscT/9frCcQLWQ5wFSAV8I9HH/0sAyvwk/0znRJ0gccQAzmmmX4oJwhBCAM53AkDKgMlAzmmhAMtqETzhIsahh20Ix8KQ0HpCF0mo5JAhLKSvwSdJKZenxllDCBSgyLv0qiQ2wgwTNBZ8lyglIkF9SQhyEWIGMbKiu03TFKFix4bgzXohRjA6I2DNO0jVgSFndsJgyoezcTGgztISu0vOk2/DmUAAZKDLlaQ3xDUUhZZQye5SOgm3xKDM7IW3w4aPv3AnSwhWsNYgzxAipdHP0tDIEHV7SXEEhDPi4YqCsM8/k0gj62bDT+EGRI4VJDIUViSkpygjjaOnTlhi0aFflJFyu0+gz95RWQA7TSDL4WZhlWe1lwaTsq/D35aL5ZcF4M4SJYjOx0zzs2/Ho3SIztIgQWCRRQjJDpMeZdBQCM2XBrWjAWYgVhwQKM1/jwjIYUWQyCjJOoQIIGUncMjIzzfH8yAkRlDKdKHnxGjMkM7jEhfBoFOoz8vxiMgRlKjLCMtwJDWny0gpZkSPoYbYkzQUtlFgFqvB0MsozYohCqeMFAjMmMvDdKgk/JBoNljMoM+pVhAh1iKwdmDN7grIzRDKCMoEj/UgrBCYyLfXbSEoyBjMPw6YyrtOiMqgIwQid8GYzvAh0DbQy+dP0iOJx28hR0zwz3jOV8DYz/fxgCGlomEV2M0/wy2DiMkYyU5X2MugzLZWm4sIE3fDBMhX0KjJiyV7TDjI2U6qAfjMWMz8JUTPOyOQzp+S1BU4YEviqMthpF3AeM14y6IjtyNgzTDIA4bwIgBLOITnTqjL0DPozETPp08aIsfD4ILEzTjOAicjdF7EhMtSIjhAaYdEy9ZWqKPkyPDNwDNwzYTO0/H4N7QBL8SgzwRkXmZIYTPE/8WKYTSRVfFtMMfGg+C1wpkgkOQ00DcGluTFY/Yy86G1Fibg3QHQAtTJVcDeIcXy1Mv2NTch+WU1w2ZHV4M0zXxMi+LqRSvCeWJ6Z9ni38QI5M829NNUyPTPIiAM0yU373cysQzV61CTxMVkBcSZ5LTMy8XUzTTUmeU0yn4h4iU00hURlAAIhrTOeNUAR47hTMtE07TLjMh0yNOk76H0zttRC+OPwFbjYorFwzsPujcftIgW6SLLo8zPdYxhS8CWRcEMyqZzpNNMyrTM1M/D4kzISQI0ybTNGMJm4jTM6cVlQLnCfiOsyszxmcTmVKzOew0cy8iN9M2bp5USYGJ5ZfXAlNJ6YbvA8rTU0Sr2TM80yQHhw2dGUNzIBNLMyMzIh6bsNdbi7M541DzPXM0i9NzIjcUFwhzMTAFLo2gSXeG1jXTMPNcyt9sA3iJszg2khnQNxrzONMqrD8aH/qY8yfzNjMvsy6TSpnXm5LqxlACNpbwl7M7EQApFfRSCzlzMqTCE0unBAs2LwcqwFZJToqDUNMxRDgiV3tP8z4zKVHBDgZO2zM8lwquh4iIJApkkDMpLDLzKRyJiJzmWwiAlx7TMIEF1NnzNhcbMytyj6HO3pI3GzMmUBbzPLMyVwVzIEeAiz/o33MoFwvVjHeYSykLILRZczy1nliJpx9HBfMr8ybTLkslizhLLy9SSzbuLbMzlxRpM/MqKsIXByqW1ZezJ3MkSyzoHksvSsnnEPNEp8hLLws75w3RmC+PlINLL0si9ZWOmzM78z3h1ssoiy9TKJHV2MULMMsiT07XHWSeyzpnAjM/yzzzOmHIKznLPVcCT0wrPEswZgLXBLiQyz/XF+cTbJ+LMZaSMATuy4shcyFWj3WaczUh2iCEuJxzIXOVKziEUurHyZEhwDcP5wgLJzaclwrzP/MtFoorICsm+IN3lziN8zw3A7M+JJhzMs8EtIjXA1Mp+CKqk6sg8FszIhcAVo3nhVweJI4kysNBqz2YFziaSyTKkDOErx1kh8sxj0vYHeyeKyhyAlcciyQrJSLHyZLLJzM75ZWzTisgsyM3QVvSQYSzIDNAkA/LOvMzeBerL2s68z70nJiR0A3LIqs/1wDVl6cGqyNXFEjYrge0nqsr+DjeEesrEsRkyhCYqymTSxLaLJ+iGrzIwoCrMTATaABrNLMtypTAmu8PlIxrP2iLNwNPmcsg1YUrLfI9wgVLOnnRqyFLPq8bGzJrPCsvGzOY1dcV6zmXRdcYQiFrMgiY6zprMZaO3Ijkymsjay6XWesviyVrODMo9BkrJ6LRyzi0kRsjN1WtR+stoEojnm5HGydLLGOIWyCbNMs1mJ5uRRs2sR19zuJIVxgrNusrEU2bKMSZqzniTWs3GyxKgI0B6z6rKpskmzVbL5oP8yqDQ2cA5AaE0+s32AbRS1swiyJbPu8A1wezMKIa8zuLMnzcjZjrKq2AI06pSqQDWylKkbJD2ysbO9s+2zQzJWZE3NtLI4s76og7PKs+qz/TGDsjazLljUsvKyJmEWcecz4bM9sjVwmImxcUmyA7Oqs1WzSLJeso2yXRQ/M8Oy5aBC8UyztLIQsropdTLIs68zs0hucDOykciwssIdU7Ol6dyzozMzzcWyQ7KlaTewRrOzMwnAfKnLWLqyu7Lu1RFwfljEsFIA85LtuIeyfbNzUb00PKz7sl0ydzVnsqGyObKVcXNRW7MZsnSyTLJWs/OykrJpskC879KABAgzOgmacNOz2BTpNBp8XrKkFXkdzrKZFG0yBzjEs4+zWRwE2Ocz/JDxNPFhQLMhFRgTDnFfsnKwb2k7ww0zGYVlHG+zOZUfsbk1iUmOsnnpozLdGelwkrO/GFZlgXE4shsUQzWhcEyz/BVostTUj7MeCF1NUHMbs+IRNkD6HRBzlLPX4nc1YHMzsjsS7hzKspKzc7GeNYu5DbJzwXkctnCByI5gZLJkQeWzrzKwIXkdmbKmSc+y0WllcOQQx7MrOX+yaHLRaLVwAbIocvIcv0VpuK+y8bPNcOBzOHJtcZ1xQHIEct6zmUj1shRyFWnpsp+JRXXGsmIVtLOyOQWypHOqsyGsghOVMwgs9VgWHTfFaklJVIwRsQAvya8Yr8jnCWNQ4iVtvTX5BRnakHPJHHMPyeb0zsVFQAIppigBGMuVpJU8KAVINgnSLQj5HyN7gVDZEyAM6Zt0DcAu/HxzbVNoeLKjgTCCcvIQQnNueQlIMCl8cuxETdn8I+MoPHIgJU7JF+knCUUcCCRoQEZUjBCLUOIkSnKcc54cuCXycqZU83jMc4DkTqGLCCFkICTcch3IgD0yc2xgCuQCSIBFrxlS0uxzGRnic0F5dMX7CDgTziRd2YfJnQh6clJzOb2EyL4Y/HNFQYvcYVWMEzxygtjMQUZyIOWKc7DktlW6CcpyCiTVQwbIQwlQ4mfIsEUBVH4JzZQmc8EZJwhlcC5zhnIJVXZzveWkleyoy0l2chwkbHO6czZzXHOXvKpyWnLQJNpzBQj6IAAp3bx2cxfdhW3+cnsZOzQScs5ye93Gcg5zlnO/zTpztnP0zJYJosWklRgQQXN5KLZylnL9GQZgVFPHyLNAI+AdyXFz523Bcr8R4CmBc5FyYFjNyUlyqXMWcxJyU3EDULFz2dPFCFcBInLRctdZKXO+LVvIKXM3CGeYfCThcnFzIxD3xAlzQ/hTcKlIsO1JcwTESlHVNVP8l/kYqcVzniNlcjjc1iQMxPilKnMPyXN0lt162RrwNXJh5DHdpKIKcxYIPPmFbYjxdDKNcuVkhnPIkaIzzXPHYGZzsXPFCMwlenKsRSfg2QnhHWFzI73uchtZIXPMcl5ymuX1crpzpik1cy7sTNAkyJxyVXNyGalzvnN1c9W4rzK8c2xyLiSschUgvHP6chNzHeSic9AhPXJgzKgZpJRCAF1zzXK8LdwhFnOZc81y7FEbsnzYKPANKaYlCugXJU1y5XNddMlDpJV0KOpzw3L+cZfYdXK7CRctxnLacxYJGTA2ocfJSXK/4CNzKeFDcjVzB3Nbc7VzSnIOQIBZcAiycpvoe3MfPMtyrdiT8cXYFXT7ctFzc+HfyN0BK5mcpbtyz8y7gMNAOXOdSLdy3nGcpHlzFgj10SNyR3K7Cbyc13LbcydzucGlcxtz23MWCOU9Y3INc5tyKMVMgclzGnMNGIvpVXOkldURVlSr4UuwIYwfEw5yX3KOU0DznXIf+Asl/3NFQDNzDQk/c3pxk3Iscovpp3Kec+NyBBDTcy9zn3Kr4cpz+3KjcolznsBPcjDyCuT1EcTEO3TMvX1yAXG2cNVyPXMNCcFw/lJzc78QMtl/QV0F+rKLc8DyfyKcxOjzAPMrckoAKPOklHTg63OI8lBpG3POgfPI8VhZ6fFzCPJOCCkSG3IPc9ZzFgnk8t9zSXPirS7sSqLI8gER7bK92Z7SlJUurdhZKPN69csICciJyLVDXaJAgd3JDNQssK0lvcwYYT9sRmgHGLNwq3BmsQYDnPOs8nCxHPIKFOzyPPJc1CtxIInboMc5QZJ6vPtwAvKzoILzbPLC84RB2rC88rZEDkBLcVzzbPKs8x90YvJG4feyLwnlc14i+NVkYrfkNcyy852l59BOCJGh2wjWNZO5UNlzdErzhsiNcRYIzWEq8nLzyvNq8wcJSvN1CIrz8SHbCAT4HPUy8vNUOvNnWAkAAWIA1KR5RPhq88pjINXdma7xhvN/HUbyqvNy80uVi3Wlk6xBWvIdSaMIevPNc8HIF1SO3T2BVvOa2fUJ6vNW83LJqwh2k81zFiEzVfctNkhLcuWJb5lO8kyB83LzSB0J5vJxchN1B5OzCcIRcvMe8x9VkNUjwSTzh1U4knrzFvP28yGNspOuc4rzp1Srpa7yLiTW824J9ZTzgPbzx1QfSeMo1iWL0DhYzCS0LI7ysbGjCZHzxvNTc8XxoQkSYeHyqXTcU32MMUhXc/HzvFIWjUO583NSSN0JGTCcOYbyr0jnkxjBHCOdCPLzuvM9QfbAJvNTIzUJq4Bp8xipJvKzCLfxyfJ58xMizoyJ8jAo+vI58nHy5QxOCaiwhfNRCDAlDQml80DVNqE2SKXy2vJB87uj9PLiOAjVPySshGHz0fPjmIJgtvPjVRnygfNV8lYIlfJMgRbztvPQRbdwuyEN8wcINaVroS3yfVV5cUZxhvIh891UZ6O+JB4sOthzmU30uoGG836JWXQNAT7zA3OSeAiUHfOKAeHx2O1VfQgzxXHvUiMhnkm7kmhApvGQcsmTLJkznRkJrZNOyT9TEyGUvPCVkZhTnJ6p1ggTQaTABUkL8zdJK/w5taqA9vCfs+39ObkQ0+FQMvHETRLAVomPsp192AR4UcucvRjr8iDxdehK9Sbxm/PZgZjT5vXFQ5vz0/LznZ2Fo/1c8v9TcmHSvQfyZyEyiVPyygjwbDjSE/LBQ0PCKCDe8J2ci/JtrZPyoRJl5Svz45Hj8+ska/Gb8sfwZNKrEfpDWfGTY7/5AIieSdvzfcBV4H2dxkOb8qtgLNP3dHyZy5mxUPTT9R1H80XR7sASQIKc8/NF0AiEfkBUiOfyXcAQyMCIfL2v8g3Bb/PEiTBCz/KdyfrwwISS8ZvzgZkQ2FSIYAvz8ntVwAu98fPyt/KjnSfyjX3H8wOdxUMx8b/zAAq8aXwICApz86gLktMgCp/zUIhqQ5fx4bgq01CIr/Nf8gAK2ogr8r/yxlB/81KEOvFf80ALqInohMVcXcDykZrwt4HZgWgKZ/OkCxaJKAraicngDYFkCwHxzhMmgCgKW/O6iZQLLwRAC9gL3NE28//zotJvuTgKjAp/8ww9j/zYC9/zMAyECiQLatKy8UkJP32z8mfyK1ygGdEDe8k+07XpEApIlDwKvPBRE3bSq0EIC2rwt0Bu0wIKc/JqGRgN5/NI06D5gEh58FfzPAq5iGgLvrzbWWzxDBib8vQL3/LQgnvzjQjx9f9pT/ITQc/z+vDSCh/yj/MwCxILT1RIlAvyYgs28yoKggqg6KFCOJWcCwHwmo3wDHAKpvHKGWw50Aq/yPTwSMmjKJAKs9PW8e45m/JyC9TwTJB8vVgLnJHf8sYLXQ2b85Xw/tMGCxkpB/LryPwKi6j6C/KUF/J6CgOpS9LCCmfyWgviidEDSAofnJvzagpz8wTprvAOCuoLqxNCC6fzAfCuC1CFvr1hMTrwSoO2C4X1hUjO8BqDFgvYBJIgzPDOCjjdN/Jz8nWIYvDiC/gLAAuNsDQKzAtBC4gLGgsJAAELaYT60nYLAfEe6cbyEQvm8L2YhgvWC6IL25M6C/KVlgoGiOmofTlmClIKFPCBjVoKMgrACgOF3TmGC09B1PApCv1UCguQCtbwSQuuC0oK9PHxCwvTKgtwCrELS9JOCmfy0QsWCnkLEQtLoTHyKCE5CqEKugvj8zPkn5H6Ci/yg5OK4bBox4iv+STx7LiCYIRpJgvJCnfzVQrmC2zxZQt4kJYLV/MlC3dIMQuH8kWogQrH8uoKkQu7mRQLJPAMpToKBQvm8G0KnTE0CqoKCfjgHZvzPYHLCa0KmKkMQN0K4SEZnPMx3TlM8+/TdRzKXVVdkDxnVBIgJIF+OO9xgvNekvdiJZ2y4CAz52PPcNjAYDJcISMLaPCw9ajxrmmTCyD1UDKdIaDBwPFzCxAybYwI8BMK8wvjQAsLSwsgA8WQ4woteEACQiHS8qhN8xwoMkd40CH5IgxxJFxiCyQ1wFgyqWrwDYGvmJV49vGm47rwfAlzEMAKXvG7Cn+8MIRHeXOAz5SUMkd5e1DxqSMdOwuCGPgyOwts8IoZozKXmecKxgsMNMdEzfFq8JrxcjLWheMFWVBGCRgJBMSaMs8KAzUhqISohPA9wc5lIajMqBTxdwoaMz5icwVfcK1J9/EisPypbvHoATozBSA8qPsLFwtiiD2FH4hnCuQ1Lwp9BVsLJwpPC8cLKLnRU5qB1DJgikGoJtE68T9pAokXgtCL7wtCuNvxZvJXC9IBDDVAnNMFWVB6SGoyr0haoa8K6Ike87SEqIsEAY6owIqPQOiLgTM1wCm5mIuOqB1JAOH5ifsKFfU4iyVxvPDRqYQJivN1CPsLZwpaWdtJjeBQihX1WIuaChCLFohnVJ5A8Yh4ip5Sx+DayYcL6Az4is7wJwoDmJV4tIqQGQ3wv+AeM0iLHwtXVT1FDwvPCufw8LhJidAZqIsTQKUzjItsiNjBFIrBiZ5If/DWNDPw+wrbCu2V1wpwi5SLLwgQwM4gpIqmUgKK9Yjkiu2U4Io+iPwgrDTZ8ZFFc4WE8bOIygh5VLnwcIs88GNw9AEY8K9SBoUQ2JgCRaztrEBUcMCPvKY95IhAVE2koO1dSEXwSosNsMqL8SFOqfKKSEh63H6tv2g/cCbQ8xioNCNyJcHb4aVIGotO8GnpIeCCYNr0GotOjCXAYqNk9BqKJwiaipiposnXvADN/MIXzYmJpoqfRFO9XeGqKVDYRa0RCGzpHHmz+XiUEYUl5BKi7vwWivKKm2FxiA6Lw8iMBE1YOJR2i+q0EYXbSVqKkZSz5KrYGFHe3e89enHcTUqLpot+WCaKeJEDwaaL0Al6ioUBHooG3aB5VOldkCaBCovlrde1bIBi8dMI57178GzortCbWC6K6RWRteGL9ouu3bfxWem03AuJrt3Wi79pRpJByJ6LQsym6e1JW6CXvfLxj2kbYiixpou+nVno9KMxmaaKyYomipjopouxioaLlopzYemKcYteiqqL6YvRiiaLt6TsgaaKkaz5i8hJGvRhitdyCgRFi1GMI62/CSqLvopG3FyJGYuK4ZIAx71o1bboypm5iuWsdYXJi9585Yom3YFYuYt1ihsdEOgeikZMq6K/KF6LrouR0M2LgomE6T0xCkg4lXIV5sKGPJkYJt2HCRmLa9HXpCbdgwkZi2VI3PTlrBQ1FYuFSJEJuDC1iwOLiYhViop5tYpjLP2L66MOivQQVopVi5C572nViw2LmAzViv3RU4sjiz6K3orlrJOKqr1x4qqKVYsMzYaLfYtWi2ogeBTZixiAVYt1fGmKM4s29cHdReILi3WL3JyuinWLmYFYRdOx2+Uri1aKBxxFtbuKO4sndNDoU4vrihncp6OHiqDtO4p66JuKR4tGw1IoDYvbingCFYtlimeK8ZSvtOaLlYr3o2qLx4qIYreK24oniwnjLumni/eL4IncTDpJ6JXVWI+F3Ez0YXOh8d07CCaLU0DucW+Kl4udilncpnVRUzaLmsFvizuju4tvi9ej14uDixslOrX/igeL07WBi+OL2YuF3UOKS4oTi4XdzrRPtbeL2AN3ihkF94tAS7OKNYqAYb+K94u53P9NpwGXiqDtXwlP5I+KQxnr+eQUEEozPTBKvooXinU9NRQ6iwxIBYuF3B9BL2gA4+qLs6AQGW2K64vwS0ni14o4S4hLdfCni3jFpEmF3UKcwEo5wUz9eEqdCbWKvAUyBIRLyomGi+JBqsS/4QhKIaM/ioRKdoiMBUZxOvNsA3eLJaVWizCJ+EpHSeiUU5griveLeErYStBLdYq1s0hL/otNihhKaEsti3OhWEQKWFvSfYpWikMZ+ImX5fuKS6AphfOKeEqv9NRKyEqcSq5554qg7LOZP7mCSxxK7ooY6FGKgf1EsS+Loko4lCAJT+Uxil2K8QyCSvGL0qDcS8GKzEg6iuL9qsXnkIBKFCzzITJLEwiWi/WU6YocYXeKmYqe/R+R/EvASmOLUkuySohKHGFkS1hSWosySm35tYsZCMRKS6BczCWLQYqj8hgDxxIy89LM452pjD3AWoBIU3FIyvxFCOcE3L0c0N2cV5i0ApOl4SSmSwwpNNChWfYl6yVFcamNpdzH8Y4JMSVWSnZLvujJiEbNRktmCXaxdQjMUll5tkvOS4whLktOSm5LnaTlDIAoYpGrUHOZJIWkwY3ZXkoi/I6lRPnNGdLMa83EUgoMJ4msFR5LwoCkheLJQUumS9d1lfE2SrJAm9nEUhiFkeSdjKYwhEgQQdsFlktNFSJQnxIkAqixS4wSgMCoV5kVgwlBLdldkAVkP5nH0SHBPFJpEIqJwMCY+ZFLKMHQIMxJLNA28SDZASUYEcTTwUsLuOZLPw1TWeKVNklmSH4lwInARHY5PktLjTCACIWXFYFK79l6IJ1Q1ZjNXXvJsFITkn5LwoF4A7eJMSQBQsz9+UuNCS3ZrkuhSxlKJkoOSs5LwMBQSdOl4SU1SlhZiUqosD/ItkuhS5noDYkmS41KpOHakFaAbUt4EMFL2ehJS0uN5OD5S7WgIUooABON3UrtS3FK5L1dSN1hkJN+SRVLA0sOSit00oTNSvVK1ks5DE5KNUt0KFhYSQ0hS81KveDFGL7YBUtJS3xItJBzcF1KZUt5Sv0oZFI2UUuMvI1mBCt1CwXQya4kjsnjWQtLFUpGzQFKK3TVSr5Kg0sTSwUNVcAeS6FKK+IlLZtKEUtjS01KeUvrStFKFaNb8YtLK0u0SCXYqUuuJR8MwNhnSvDROsw5S6mMvdQnS71KcIlLSzgpAOB5S7CgWMFolAqgBLzpMBFwNJOGaDNLZdEX2MTi20uXS8PBV0sjSh1K50ppS5TiBCjZQN1KfUr9KE/YdUu9S4VKhPKLS8VKcZSTKE3ZvMlrS8xSy5zo87YMF0muJZls3eEbcsrz9iWxQLNKa3JfSkDLsUFTSqJzpUsdSx5LP0pwsTDLpkqyotQsiSRhQrVKXdlZS+DLlUrTlIpkd0qMUysogqSOg9dKoMrAynNz6UuLS0NsJvy92YdLv0pPS1GjSMo3Sy9LpJTODX/YL0r5S7DLBUvZS29Lf0qbS64l4YHXWHxTy0rnS9nBYgln2XUI4UqnS09y7kuRUURTUUpk8mtKeUuTELxk99gfSkZKsMoMpL9KoUsMKfDLPYEEy+FKOv24y2FLNMpqyGTy40p5S1TKmMvoylxSFMpncujKtEk6zJlKonKcym9KF1lsyoOJeMuEy3WpLMrdSmNLzrA4yszKCiUWDWmIIsuNSkzR/Utwy8zL8airYAmiLcAliGdy6ajFShjLDvD4pAOE5Ms2JaudUCjiy+5INUsQyo1saA0Iyi1KG2zWDKHIjUqwyxoM2UBSygokYSkNS81K0MqNbATKSFI80H5LVmEPS6jK5UqNbN8E2UpvUdFxvWyuDMbKS0r9IvEt+0piyyNzNoAjiHtLzMp00WFKEsqwy7pR2YEIyyLKdmGqy/FKFkvvyZLLGsrwy/QNvMoWy9PJmMo2yvDLsBiKyhNKCiVuy19KLsu+saLKVksSy/6gqMuey/tpe8mN2e7Kzcm+yqBJrsvMyzAM3Mr+ygi8rsvky8lKzci74bvhi0uOQt3AU0pVwF5LJ5MCywEl4vjyzfaRUcspS2hIgcoKJeslC9SMyvDKDUvwQVrKzcmJy6RK3sqwy/HL5BEDC8zy2qItlQLjhPI94QCkItWB8O3iEBWsgGlAJjXjglnLm3DZywAjD3Uw9d6IrSXmpTnKD4k81PJSwc1FyxnLucqj4RckZcoly0ZpqhTu6AlhxcpFylXKroCZyvYilNnImAcUE8g3SEZJ1Dm58/XLVI3lS++RMfKHJA3KzcrMQc4LR8i+iFVJ0UvmseMos8ntynOY6GDC+Ukogy0Nytl0Wjgv5K3LlxQpgOUNIyhpcdvgA8qdym/JzVFNyi8TntO4Ak3LQ8pC0PfsI8pDy73LT21b8YPL/cvBwNtZlfGDysmImYmgkuNZ4vW1KVXAuXUfbGoLVSnQqbCVtBGq8zvI82wJCB5hTEkr5cEAR0ErymPKm8kWDAsRK8oPQLflgQHyMM1JwcFpiMvL2ygZHdRTDE02wP3Ko8szy8IoruIn5CfKzVkTyz3KM8pForvKP02O6ePKD3AlSS3JV8u9yv5js8pPJRfKd8unynCli8rE4lQy/RnLykxECLihWPdkDYldIQtLlfJny+PKsqIo8FUot8rVmRocVcAXyifKTdngpUb098q/y7OVe8kjKdFxf0k32cPK92W0gbvIrvHpS6/Ly/g/md/KygAGSscSRlIy82owjMnjzHQj131dVPXMMCv0zR1VsfIuJLnwi9iwKrXNR1kiC7HYoJJ8IxgMNcjWNEmS+CyTw1AqKCvtAd05qCqOUrXMmCr9VcgraCsPiCmAyuW8yKvMlNHX8lrk+Cp2jPURjTLqgMrkjjjirGwZKJQYKrii6xAao2QqRKyiwDfZgEzEkp5ZR/LgqdSSU81PAIgraiG8okJoB/ILKLwsj1ROWT/z4vyucQeSnlh0KpSV11V7k4fJ7Nh3VfKsq+GUK50oAXHlhIvpsAtS/QItKK1z4HTYB1S2LQijBCrGKcdgW8zxWSZJnctVJROSwitECPL9hCrYhfUVuXDy/UxIs5J4MPwqaCpErNZJcCvSK+PMV6x4omblVxN7KMwqWCrQKiSswvFeCTgrDKPkK7vKGBAb2S6s8/IqKsfMbFCIK7IrewQpir1xeCqEhNiFDGnKK2ow4iuAhbn5eADK5EorgITKKlUoWipGKzZB+XBK/JMFewX4dHoq3CtsrdaA1PCGKigqliocK8YrbTHsK4FAJCrUK0OoqfBa5YYrzKBM8MD9FCuyKPEDBigjgYUJizjvglrlciBqLYs5dkJa5bEAxizNMDQq8CqPVV4q1PDy/KZlH1QeKoQLKv3PE8ygXCt15ATynCt21SBC8v0LudtUeoT68PL92PJ7RaQqIiq5ctSEFElYiPL8QisnBPYr5irILWyisSrGK8Isq81RKoiT8iq4lECCYirGKQ4qYSrSK1gqzipq0xXYSSpolT4qSlFpyh/SLPMOFO9DtyjXKTeN/hA5K5/hsfyY+e3AlIClytuNOSqYqReNH423jUUqmOivjDLAhSoRzbsoAKjDU8UqajAVK5/hS1EFKyYVk3CfjPryH4xAqD+NFSq/KGUrUUDlK22isQCfjQCo94ySEVUrPylnKLRcTSvuFYBM86SWITPMuoHL3YyooHC+gB+gTsGuYCPR7SsQTOipG0If9MUr81yWE5tDwmE4qX0ra+xnLXXLs2VqoINYKKB58swrPdUUkPbVrIQkKQwq4ytTK1kkjCjyK1+osyoTc3ZCNcjzKtJICCrEK9pzevD9gSMEjCRUCvBNNoX5AAgqwUPScjWpNdlZJQCNM8A2CEsp8yvm5WIKOyoO4ksriCxoCiZRNyCOJaYDWdNrKrtIqyvUXXUK8EybITMVTxk4Ch4V4yo+JOpCNqGLCTsr+yujwbkK2hSXK4Ct4YG5Ch2ct1X+SLqsakOTKzaANyrYwErwfHPXKhMrQIHavc0ZHnn0aayEDxwzK0F5HyvgrCmBLyrXKwUMekngrU1JPdg5QHuIFkgwotHUvypgkm8qVIVaCocqdyq1kpMrFyq7Kk9BYKu3KrsqIKv2CqCrkKryEPwriyvAqjCrxdkzK/sql8DRKuCr8KpPEi3SiKpvK3Oyb2SwqsqiskGWKtCriKuVSbCEyKuoqhirUYwAqzJI2IUamNAKJlAPBH8rBIQ0CuiqbyttWeVcBKushTiqFCqoq4CE7nHEqlMr+yqEqzzxQKugqg8xrCvRCDlAlkhNiYMFmGDecBSquyuauQNxTysUq3SqkiKYq88FP/NnWNoVhyGshdy4wP0IgdH9TUCnMCEr1dVw2ZNBgyRfM3sqFqRD4R8FlKrcq0d5QknsqmQLuKsAqtiErKoNKVSquGl/BCMZI3F7KyygnkmAhbNoBqG0qksrbzgcqvCqbyv4YIjAEqtSqmLtPQmMq20wYXGyqmyrC1kjBZBooBl7K/FARglzBLcp88mV1A9RdOE2K3ZDECvr9YyhOqhr4X7DVhgaLWHinZBPzbQBHVwJuEshneM2OcDQ1rEDEfqrLQEkbB1QUThaqqNQGdX6q9qq+qu6qiaqTMLpwLKLJZj7JJrlXDW8mJsgNXEemcxpYpgDMA1xIG2SIBQYdEEyBHHl7ImcqY6qtqoPoH/oogxJyr1zv8mcqKihPgQbWEBpXAzkSDl1aBmcqM8rAVhh5daqHTVGkXl0QGgICOtR6i3efEwZ6gxZSXl0KBl2q1xAqi1FqKSp7IWkAfaqo1WOOP6qEQQJdIBCjqs2qpGqjk0kQXppwIWzzYJJtaIVDWhJTCysTUqoiIVzoBqrr1Jj89QpGGGqCPPLsejhI8nEilCz4Yd9tbV9kklVa5lVhVPIlRlVxJkIjyubKdmrzgKkWAWraOS2xR2TXQTZqpmqS8Gi4esrGasrbLr5DVKlqr6sJaoDiAHYhavRA6FUgKsnKX4hW5hzuGvpuat1qy0K9lVvy7HoByPylKIo+8vlq9RNQ3A5wbmqhavEBPVxb2PVq82rpOSpU7mqR2mgaCp0a0CL1NHzxAQPmb2h2dkm4iXw3aq5qrd9KfOwaNcFmVOHfTsQLAznOVtQY6oXI4EKWaoZq6Tk3qjjGB24u3z0ERhosnTYyRd8OfNmC7nxTat7ON2ok7kZGcuVQ3Rz9fbZKZDzfMKUQ/Qzq3TBh3wTtM2oIxhAcRt8Hav8QFnAoZI0KDurEwSJUpuqxdH5cfxBY5lNqsWrIkxHqiurf2WcaV3h+6vVqtkiNsCW/IYts6uHtEuLZ6sFq+eqTasnq2OrxwEqBOpVu6vXq0xoVlQDlKZpTGjXmK2qIwxMTADhM6qbqgkhxGmxEIurJ6oIhCpMLHXziVd9X+G0TY8d93MJ6P2q3AQfqj2qRyJSBWhIHcrNq0JMBnStqserdk2yoGOl7arZIzzCQhGjNfbZ2B0pVZ2rCegAazRAPzDDq7+qEGimXd2qNCm3qpJpkGtdiDQpvrXIHPerDcsV6d+q8kzEKPd8W8kH8IExF6vzqthpjHTzq4hrKGt/q8urV31eIrIFX6C/qnMQCGl3qruZqUlYa3CJ2nRXcRhq8Bxfq3hrThG8CSKc7FGPqiyhb+1ka6tBh3y1ydJo1gVLsaM066tbmURri6v/yew1unUbqnurYGqU9bdxlar1lW2q1at2GQeqefAE8+Bqb6pD9dOxo6tqLCMjHakcalBrmi1v7Wxr96sRGbwJnsATqjQpaGuX8byd7lLfqkRqr6sMaihqwmonqzhq3qnUa1+q8GqTqr4FZavka09A5fCUa5FJfauwayRqEGqraKvwdGvLlRBr7gXCaoRrrarKaBFRTGrnq3AMLGoDlQpqdfC7q8hqDOSr8NxqiGqwaoXxmmsnq1JrpFi8a8hqVOTb8Pxq7auIarhrTEHm6XpBhGpXqulV96ogal3x+atAtCBr/IrPqg2EpmrivS2ql6o7q9VYa6pUan3yvfB4azRqFGsXmcbkqUj3fKG138mr8KjpnoA0KI2rCGg37Q5qB6vvmI5UNGrMat/wU6vbqtki0zwqaqxrvA12YaBqLmtvqwhoZ1X8ak4sc/X+agZrsixQQ0Nhvmsia83woAVMSGBqi5mqa2FrgVKA4H9IEWoV9JFrzmoPqlOUFmu5qs+14VMIayeqO6p6NJxrSmreI7JqUWqBIz+rdmo1qlqIyQgaaqerManqaylq2SJlYIuq83yWa5lrGRlrqulrhSLxaslruVKECFpqT6ucaT1sEHHDq2cjCRmxAbYsAR07EFMFqgknqkhqepM5qotZBmpJKE0N2pF5aiIhZWvVa1uqBWq5a80MTok5aoWqWSuDCm/9TgS3qa7omLGgUWVxEaAtgdnRFlzZK01qgcTAqWiwadBllCZQa3WAUHdiTWvtzdlATA3tMYGxbvmtamiwPWuo/MADODFaod1qQl3qBM1reSltaz1r7WrDawNqLWq8cBNq3WqTauXUqURjK6n0mLmi+Y8omplVC6qBMsQfVdDJRdEgcy1M82rkBRbxAxhojdirxATEsZj5q2p6SOQFgvEQ+NEpUyv9qiVwFsUOyNtqiGg7al2pfyOLasKV+ExTTVMq5AWZbMhZc2u7aqV0HQ0TTPNq4gUPQEFkZ2u7a7aYCYLTTaLYSgSqTF2ovAjsTDEdW3h7QkYI4gSEchmpnJlZ8SxNLDIdTcqYefBKEbd4QfV2ybRMvIzyxAPDrvOGikGy5akAUTXY52poTGQTW2u0EcQEx2srGCdrtBEx8C9LDUyi6R8qUgWHs3rFeMXSaKfZSk2Han9qXGl0TODri2tQygwNV2oEaWJpvkhx8ZL5HoCfWTRAsXF3apaYF0jw6rMz86kA4VwFPML6OF6oRphPapLdi/W/a5DqGzJG+ejrKYWmvepMkOsdqc+RKOvY6r4EhXC/a24FCZAOBUtrhMVb8KHJTgRfao9rbJiKagzwrfQbarYEtEC46vWELUFBBLaysOpX6SsqrgTucMUZ00QnKq4FxOsSxd9qBQSE6oOpZ2poUCDqEahM6reAJvmPKa7wRQRJiqiltOvosKmrGwterOmrdbgwaMEZXOpMGXQTIQNdIaw4POq0xQizrDhlNQcV4vkyqRMEdzUHFXY5VKiZgLY8fXyi64BCpmVW3VlzPzOkaMY553zlDPBo7FCoYg1sObghwaMzmauiLTLrYzXRAuLJjeDRSac1hJTULGllFBIOAt24EkHK6gM0GMMK6ym4YLWDi2VTxbgqkwt92bnoaMFkc33A+EhpnBILk3zrI7jzGHDI0rJLsBNRNav0LOm5qxkMlA4seutENa5lcgJsEgoLFAILuOQ03mWb8IrhWurP8/rrKbmNZVbq1APM5RCyS/O66ixpqzXolHW53bjjuE7FEP2EDCxoHj14lc1lcaqOWfLrEP2m6hJoIzTwlb254jSv085kfAua6hrq6IiW65wYdORvCvFk/DT+6suhNAuRuJQYVuvTuXwDdBLkBFH9nBhW6sHrlusfPQ3woerDudT1B/FbqrzrkvWB6rz1carB6onrS7EOqqHq8etxuFG5bzxXq8Lq+blRZEBUzurWk7uY5iV8AiKrDfGMdKo1Xurb8eTzfuvVuCwMgTGluc7qqzKSTebqiuAO6vnqohlEEqvwuepe6zrqQB1KDBbrJDRnq8o4VutV6ySpvOpAHDO4/OpV6m7rMvCC6vw43AQ+68LrW5il64BCsWWg69W54jTnOO25jeqXeEO5Hwvvq+O5UuvN8NnqOWg561RYNeul6zHqhEz+kF3rSesYCf3rABhq69Br4QyB6oPqKnTV6mqThAhqKYqSRuoBBLoCVuqWQQQDk+qOUinqFeuD6g3qZeqoCCwqpGkD6zZM5WQpaAvr/IqxZY+DBuokvU0NtuqZNFWZsB3W6wvrSuuV6vWUofWvg0Pq1TwllCPrC+vdGYVkS+sJ8F958qi169ZrF4ha6mvqTWjgHGbq5DQPHAmD3OskNK6cHQxn6+gMcRj+iBfq3/G+GTw0E+q4DV0EhEgm6t2U00DQIfbr37KtlLgoBup2JNvwFLHISH3rupMf8Nfq4etx65fwoAUjDBLrpzS1BNzIkEMJ6xgIv+EvKvRpujjgifvqfGkMNVdVx+vX0rcLABr8CCXrD+vzPIEK6bilZA8iv+vr63ZTX+qb6t/wl+rwaMFljqiK/ItZO+pYiSL1AmlD6kIdRnFwG2nqVfT36iEFHescim/qn+pvCmHkKXDC69/rgTORuXLr3RkH8M5o5QtEaFZl1IgjBW/qwWSNakLyAPHAYwdp3mh8lXE4eIli8qNT+BtnaIj0Nmk2A0ddRBun9ATyBBsvOLf0FSFnaSwhUwt90N1JOqkkGjBVcTi2qWQbTSopBEE5KcOTatuiZBrUGp0g5lx6qyNr5BrjXRQahqsFsA0cH6AZAmD8aDEXaVQbywv0UBwaJDlA8UH8NgJ0AMwaKwtwLSdcKYGgUBwb15yzsADwEzksGr5oC+BsGxXKLFkiG3wanBvfk6lst4D0G1D8vOU0GwACx2gOaJ913BpZQDIb+7kBkmpYD4lHaXIapqqesZNjXBrmNSobYhrSGspcSJQ0GuNcihowUEwaUTi0G8IbPJRKGxdp2huIVLoamhpjCqJAz2KEgA/BWS2DXSxwxZlT7Ixyy4D7JZXBfOvTsfIF0nXks7P9yEmX8KZoXeoZFcchxAV4AhUhYIHeCLYayvngba2Qvavu0v5xO0ke5R2pJwNOGsPAmYtZ8ZqTMgIrXBYb4+CWG4mxsZC2G/r4o0lJCcRoK53uGiyg4sPEBA7w/DThoXtQygi0fdYbRhjjIWtq5hv86L2qGoTvST4adASlTQAY3WiNIf4a1urbxQJBbhsntIW51VhWGrYa0RvYoXEaMnFC6zFob3DjIIDrwtApaHEbNhpyS5Y4NhroaqPrJKiwgfIEmqB+GzjJqRpAMtQCqRp4KtwF8Ro4wbdrthtTaLD0IRp8BYka4BMJGoppaRoJG6kbv9hS69EbhRoQy4XrkRrKCXB1ZWnhGvJMoRsO6UEElsvqAoEbzVgl8Z3qkRuK6aUalqQTaLpK8eW5WGp5O2hpadfMuoFWNM2N/BvvdW0ao13fSOaqnRuDXF0a8hoGYAT5m2lfCMaqzMCtGwar0LA5Yb0a7Ro9G1pgQxoUGwMaJaGWqgVtG3VJqTFo+BBOqxYxSRllaahBEavFdEP5jSCjSDKAkxpoMAsZMWmZbW6rfM07qAsacxsuq21z6uocSI6FyxqRSa+Dz2k2hTmzBnI/6Tpcg1m+qi1zmxucJf6rxCzjqEkaB6EbSebkOMHzaT8MIaoDzEsaq1wDMWPNMxsCaFfc9qsmLJyoA1U2qul1S3LrGilCixsKLXGqNuTnAZl1e8GNacrktxqrczOpexuBqpcbBxpJG7ehGvWmJWsahxtm5KjolxqvGzFpVIjc6E8buzgTGvHRHc0/UUzoc0CjSedICavVuMKFsxsXGqkkSzmnGodg1xtMSPeIExp/Gs4t5xtQQIYgnOsJkvZYJo226IplHliQm40hY6jPmH9Zh7JTva4Ia3k1dNKyMJtQmm2MC7xQmvIc18XjuQiaxKkQpQiypDQzmEfN5Ov+jSialKnIm9e1SJviCIchYrO/aV5Jrag9cPtB5DRfmCT1mbJp6Tkoc2nw6p3k2Jr0qbUzEOgkm8NwbOAnvESbZJuwmriaIjRdFVyjU+QEbBvx2QiOcQzpcJrLsrBEflKBSPJE+rP8wtMobRXCCaW4q4HtCbXwNkidUii0gqnlInroLgHVFPRyT7VWAYiJBmF7a3uoWasdzWxgFbiyNNeYG3Rcmny5cMjZaYyzRnULNGayMbPQmz0ok2g7MzC4YprRaOhyULjJCTPwGkg3apiaPWjEm4ToZJv7iDd4nTmi4F1MTn2h6HKaQHM5rBKacqgss/61uJv+HSczj2mqm+zptN3GUnKbGpqGucqbVLJU6qq87JoiJVhS3VK6mnKoepvkm04RBO1NUNPwMptkshibTugUm/kTAjlomkt5rnDQ6HKa4kwsmqaaO7JFtJ40H0V7swabX6HXRTaaTJp6CUTtVpppvQybZRyWm6SbTCnSwreCFpr8ISJ5mLMI6Pqb3DyEm5SbuGiMsxKzWejcmqDFBLPWdNjAa0WXudKacEnceTez4pr0EONFs7OWdCKagsLCmyZ0+RDnxefAva3Km9w85JuNcWOoD5h3sszzWSraohS0c+gLU8SQA2v/vGqk/Spv/TGby1KV7bXts1PxYiiAOG2d7fq8aJ00tGS15rxpm51ACZrZK2H4hXlbUk3sO43eiKvo6HFWpJma2qJZmsYVuZsj7cK1K4B7UwhBeZur0U3tQVD16B6BAYnTgivhr11Lg9io8rTFm6K1k+hL7PXpuHzKtZvc+H2VmuzATSoza2MafpgpuSnwFdnQyBtY8pqH8U2aQar+uF6LuuOeSI11NOuPaexc22oJdR2aD6MtKQDrp5z4mu2axgTOspaynZvZjZ5J6JrWTRuj6Hh/a4yhe2stml2a8rERUoLwR2q/Ef2bv2hxALR1s807mT8z5fDWdf1xJ+HXtOObw5vsuO1Tc5rNmx30rzIzm99qhyG0mpObaNTRqJ6yLZpMSbOInrPosyubTJgugBub5LJp9Hx1YbPJAY2axgtSdDqyEul5uQl94Gn9cRRIS5sXcdDrGPXJsmzpnZrzm/nt17WnmouaKINVvMea53T4rJ1TFUEfKiT1dMW26QubApsUkH5Tl2DCqg1wyoKm6HeaFWlrmxCFw5uGcueaL5rNmpLV/6iH8Qkpd5thiJebN0DA6m+JE5q1BOx0jPW4xbbpotCWdDqzXknTm/A9JOvDcOqhOrTq4npJAh1TSJuaoihjad+du5peCJ5IJPXeCNDp55t3m0yhr5tf4H9rnElNsyuaT9D6HGm015sXeOdFV411uGn1/5tjaEGzWehOKPYbNgg/mjDVq5pwW++aXvDLmqAqc5rDm2+aseDlU0+bW0m9mwFh3BxcsBBaLKuu85VxG5qtlWyZD1lEWtua/5uiaABbBFqm6I5Uh5t4Wwzpl5t3mlBbAOjQWgVwvwiTsuK8lUCfWN0YlrNU6X94N5um9CyaIFtLWKEZOLK4De0IM1kTISeb3ZqtmzFx/rKqvU+bTFsQ6NBb9vTtUzRawcJ+U1xbLUjdmk2aR2qrEAlx4GI4WrLp3cp66DxaVyEHMwea50SXQ+q0e5v3ahPyAlvr+I/Zl3QrucaBBTxmGTJbJ108VJRRvYRyWqSpPWQFAz9QHRuCbHUg+T3q4QpbqT09G27gKltKW+rgKlpqW3UgYxqEfESpHGm7qVGBTrQkmRVk0SkXsU60PyosNCGiScs2OXBCkgRGW60FM2j6W0L0b+nL9NSo7tSYEgFCKWmD8wlA/vD7+T+5ZPEJwNz1KBm5cGllEhlI6C5iXquaBDlVZlo4aMTxuCo7SSZbhWR4KJHKBlrGWgDg84HWtQZbhKjysR5bulvxGc5afLwAjDpaGzzkSe60PlvGW9MsF+w2WwFaScUo6OeDQVoEEsP1zlv6Q9a1ZuSmWugqIyzo6M5btBhOW4FbV7m08J6YePTlWWwZXlpGWgAlCjTxW9Mt3/mf6G5aL2j4jfAZcIzJwDtIdCT8NH8LPYGsGLyNDqrNYZXwHBisyM6qqhh+yuoZjojpW/pBjQkqGOJChlqT8Lpbssm4GZI1+luyyDwY5ALeWnFahbkhW3poPqumW49IfW2WWsnwRVpSqe6qHMn5WuoZWkMtaTlaoEh1WjGqWVq3G9QDNVsuK0HodVqOW3Ig3qoVW1w0yVs+BWVbzbiJWqpopho73Olz0ajtHUGjzO25GKZcvVvSoP6pbHVI3GHIltzE7f+Fg1su7S0dqaLc+NupfVoDA0z8IY0jW7LFhcS+jSIhC8jDW6NbU6k9WpNbNGNjc/d1FBR/Ff959HGIpT9AlFmp+JCKzyXHzLX0s1pjA/GhjamrW3sCuqjJqV3gQEUP2P8MfCkgRdGQvfSidX8lO1qbmFSIhDOTWHzFxIixWDLZwoFxiJtaXLCrA3e061ojgUzdbwg9WwCLRMUrY+OoKRIcpT0wgaixMNylK2CpGBDgRsRLWqkZ4q36xR0wganMrUcDl1vpGRMSysXnWn1a01s3QhalLaljWmta7nD7Wy9bM/HgweNasOsfW1MDMZlbeetauaQ2xXdbjwKtzNtbb1o/AxRjsai/WzDCP1rrGItaxMMNMHaM81uLWrvdvRj/WkUIP1rlqSDa0NuEJFKdp+RFCcdbWamgsxtl3Qk8cxNaVMS2qYiNMNt9jbDbm1sJvNn9i/VQ2ptU8XLOqBjayqhnW8tayb3vW6Op21txGKpZiI27W9EZeNonW/zR8IOy8Yuo5iT75d+FQiWp+MARzKQrwks0UpxaMlm8RFhw2myltqsDGVdbJsQuCZGpN1r9GKjaUNq0QPdbFjG9GQ9a9wK02yWpT1rwpNTak/VfWx6DT9TV9L9ayb2awLOoHNt+GEjabNtRmoMLeBvnGTXd0hLtgtZZdnMZYxCBL7x82zf0EqT1g5IT3LT1mzUqttk4fYoSndxz4K+8YhPxm6Lb8yhQfQUYgJmypdENOZqP9DLaNStAmelj4fgIfO+UFhL6FcWaszCL3Z593ECxSrrlRlndK0xR+ghGSVYTGZtVm1vguqTgDbn4m0O1mg1j+HwxwfWa0A0zajtCArTtmAkAwN1rSg9wAhRTcJDsxtpIhK0YRtsX2abau2tm2geTAOsEOQ7FJtvm22dZMdjW2x0ArhhBSzHYRFhG2jhlkeUx2BLERtpqyZtZnBSopOba22v1WQE0nKw46G7bwoDc6K0CqI3jKJV1PHMO2nTqfxUn5TH5dtqVvYmK+5iyHDbaA1lUiUYkHtp/apOipiWW2sbbboTX8IcgoDlQ2RMDUXPW2x7b0+mxJcHbcUEzWe2V6STBtMDqh1mR2s6ye9lDw3LBzZSB2x7a4aAcJMnaIdqv4JuVkbOyNP9YERKVJL+CBOqLpU4pGPQliQVKRMFLWxj15kgZ24fIrQI9iJTrP1n52//wdtvU6h6hudsExL7aRMDu230FXtubWTAMSzWu26naxdLdBDHbNtqucZ3IztvfayqhSdql2xzqjrn9xHAEK0ih4nOhGViPtLRcvNpIBI3asxV8EFRsXsFt2qmYOhpIBMsFjdrt27VUx/HFVd3byhqrsPSYwAQt2+3boARN2parKfWyi/YDxJm0EQkV1a3WCI55IlHmcTBJGuLY3K4ZsjwVFHEJdnhGCJmIyRWs6aqYi8lzhNpw9Uk8QaqZkNihCfPat0Cu48SY1kGegG50B+UWmY9gqOhxcW5QkiMhWYclXYhudPEI9EGqmXuYoegb2mvbO9t7UDWJS9pO6RaZMEgvaE5wbDkL24aYM9pT2oIoqQkn25PbXD0f5MSZ/lmzA+PaXMAWVQGCOGXhFaPbtirn2/BB4j3dISKZyaz32sEVz7WX20faMRXH2q7IN9rkSeZxTOn9CA+4Q+G9oNpwlKXzzZva+XB2cUyEm9qQBNzp5nEfoL/a6KX6IZ/be9tj2vPbvUiH2nPap9tv2y/aIDvn2sEUE+Rz2/8LOpljrV4II9vRceI9VeTamc9JekBSPcTEy2PcSKPbYLkT2+WsWUnQO3NhqplgWUjp99umxcg6vwo/2rvVPQhLFL5w6DoXkL1xyDpb25g6y9sWmR+gSDqAOiBY8DoFZKPa/9r0QeCaH2NLo3x8BcU6ZFWqJmAFxc5YpDoNIm08sR15q5REltwBrDElMJRUOyQ6tsQm8BHFZDo77E4iIY26xDhN9DqxM1Q6vq20O1HFNDoUCukj0ezaxSuUb3kJxRDlX4OLYr89OCkkCW1ZWRkMO9RMXL1GTSw7Z+x1IpM9XDsxG+Q7scTReIRZRpLsRGpEf+VH7W5jcAgiRIQzR+xPZBw6i2zl8DIRdcWHOOOryJG1PC04yyL80Gdl/ERxM5n0Ckz9Oc3w4kGpxHHA2GmcOrbCfhzdqSo7rExzEHP1SjskTBTlW5kKOjpNEwXvmXI6ZDsOyNRoFiklxXQ7Ikx6UJuZoOz8Mg6YPcX6O7RNPZFAKTw6KfF3tc3FqjpyaIMcVcV8OjDrGotOxNSIXehTW2w6HGrMvWh4tjtfg4ZMPcWWOppM2OTWO5xoDjpSTI05DfE8vTxNLjqETa46Aju6OgUzL2VOOxaJXwkOO04RI5nWKSRMjjsVQEs1pjrtlbw6d/CyRFgyID0lxUI63ZX8O6xNjh0OUyE6kjrhIVBpQTr8TJO4qyMgiLI7nTgsDX46ZSX8RRTbyFtDxW467ZUbIrbDijrtlSX4OcXKO23w3jpSTeY6eGkpO2s96jrxcLgNfHlDGSuVitCjxdo77DT/m0PFxjrgiJ9lTDuAiWE7/RkJJHgaLFgmpHxZm/TzUwcZAtopm8H4y1K4nNljZTuonKU7FIBS2htSq1Jd7El9RTtYnXraVTvbU71CdZh+fO/0umOHjCSc8toKFBsN9TtRfXsNCJyUnU07x1LnDKWbwvMaPGravXlbkj0qKoCFAVtDZSpa2ksN1/VsnMZFdWMr7FYSetua2qYaBtr1WfLDh5hoGG7aIzr3mEqD4OoLdK0YGfI224YK8HixCYHbvrws5CkJkzozO7XId4T+22YKNx0hjI7aJfDwbOuYkMgM68H0/ZijO+DqN4NOKJM7J2vK1KJFyzoKCGLqfEUaGHTqiGlnHPM71Os7O48l34XTO3I7N4WrOgdr0eDDmOM6RzocuFYIbeXlIHxMf70CRcc7HaiLWwJFhzpY68wEgEXdCIna4gRXudDVRMN0AXequ0inO04QQFrw6zM7zyQFZUTqZs1jOodgQ+DyTcTle1T5ceLJnEDvOu+EvnCI6y870FgrwsDqTztzO2Ys1GraoOuYFzvGBFXU0zu7aqoE6zt/Ojjr/RrVjbDle1FiaAVIo43NUTBoRQXgu5pFBOl7muC7Vx1P1WRbSQXAuz30BOvqBYC7+Qg52opqDzsh8oOJA8ow6086dAxravDrfKRdjS25AgUS4c2N8v3/C287mLpxlYckMOrou/UIJS3osSi7czubOkUFSLp4u7M7GmnmjFc6cLuQtBnzztowu8mN2zr4u8RQ7ow4uieJFLoQu0OTt4jRscmN+1jCqyS61kuouyBaCLvmjJwNJOqpqy3sJ+ErXD5I1VhZGTqpD3FqWwVZc1xROWy7WmE8ws4ZWGTiGjhsXLuhkltwrLocuj7wVgLsGg15p+lCGfzUoqzdePy73LsGSwsAVqppRBFZ4GiiGPbo3MiXs6wRXEFlZbehKYViuvfahvHxq1IdNdsyupLVdjiVcXK6mYiG8TaA2fIIwCyr4rslwdj4krqtEG/aWsgQ+QFZz5AV2QJoEroN8gQRRoSUGVq6zc0IYMPxPKkaFcby0PL5EVSpp2Wquovp2Nwak0q7IqkkhSZhZWWyu51ICMEKqyq6WoGq8ha64rtsqLtFEroyu4q60srH8EQ7jWOwvfTFAIxLiaeMk1j+o7KgR7IcyU6752Xk4PlJdiRUSSSSyYCZiaec7Sweu1pD4B3Dwb7kgMtxSDeJLrtBpahozwCQ2O0sI9mT8eJJfrprWL671ukBuu2ly6gBQ+JJrfgbpQiUy6DNSbsr4kBhGZdsLELfWShKbVhSKLkzxC2A2IFQ9pHeul679ViKUCNJT9XB/JV0tqDTSIiwg6XDWWfxkUmOJX79yXQuIOG7N0Huun8Uqbtuu2P5ifye20m7c4iqWWOkCbpK6NNY3WH7pT2hzruOu9/YxAVW2zCBWbqdULul/BQBQvlJ0/haBbG6sGhiyDXMtEmCgNW7OxA1u6iw3OiTpP1LfiABspsMEbqmaWW6n4nfKaulnUqOuy26ENAppbnxQkmeu4DY+opZuu26awMewANZ1bv5u+26oaUZSjG7nbu+5CLB6btZuj66/bpxu3OECXXDLCrx4MBDu927ibq5SgO6BbsOETDDHbuVu327z1gKKbGBA7qhpCjF4YCmSK27+aRbWUNxQbNNu9Okd1l1u3OIi/gGBeDBtpp9u+W7x1lruihYfbrAqSLEJnErut9ZXECB/HdZjbq5u9FxfaRbWGlxI7pOuq2kTTVEmKG6y6QckJ27yboHu57BCxs7u2m7zYGeKam7J7UixATybrpFumMsNdu+mqwgCXTkSArlPeyNtLm6G7tNpMe7Z0n7cUaQnv0Hu/O67btFcS4guaV7utNYT7q5pDu697pRpCLA67s3umdZMMP/mUGznIm25EDZX7pVu++7naWbu2+7hiCVvYZiskLtu+cCpaSge6TA7bsO8PWRP1k/u6ecL2nLuxDUA7sLuyDYOwhLu0G6M7s/WUYIUMjBuhnapihbSbB7m1mTm/UR3bvQezba5rHnuvryDbsR2+h7d7uruqWkqHqdulKougXBvElxyHvJtEB7l0D5gFDJ/7q7pHlg8Hqfu6O7c6VfugKp37vG5R8MRbvyMdek0tD1cYtIL3DnpZR7oHsZute6kKzOIZ6rF7sAepO6AkApusR6Lbrxuye6iHvbWAh6eHsJuzG6Kbo4evu6u7o5GFh6ybtXu5h6d7pcepvYebvsehR7zVgV2qMoW0hke6W7BHsaSSx6T7uXJNO6J7qhpIoZrkMie80ZHQiHuqZIR7qieiO6C7qsexjB5BExCPrzSOmO28AddHrYes8lonoaYTW7lv22RJG6jEjLuzbaJDSKeih7ebzAenO7TVk/UCW747uA2bDNgZnduvDQcHpgzG8aaHrO/FNVeHvWSfW7W6T6emx7invjSGiChSHPukR7G7sJCAhoFSDMeqGlulBGepJ64nsC0XvJYnoUgsp7mntBpXCMb7qpJfBB6EpJGPm6tnqhpFJIGHuWemEYNy3ke+Z7jbx0equ6M7phGW0RqHuue1SkInvqe1Sl1bq5usO65NyUNY6Jjnp+giDkznqsethECpojSEh7C2zrun27PHo+/U7E90rTWKF6pYqsKQCNfVilugrl2a2XuuW797p+g13hQVGRer568t3Ou3F7ibqJrAl6/numikKa6EhIe4U7L72XpFnlkUDrYBLaaXrdeX0QYMDwMuHj6ho7CbjZWMEKIdNRjTAnoWl6IPHTUH2in70ZelrArRB5eh0weXxZ5S9R6XuRkylinMElepl7yNhle3l7OXtZ0Za6mjDta+nKzVlVe5l7lXole2ZzFXoFejV76lwNm40DXwQpJdyy0bOxu3NwIv11Mq17PaGI2e0y80D5cEHa71iMSeiFQn0PQijwfkCeWNdZiJTHWgDZ9rO8cjvaEdjdey16+XHDWNM4zPwEEK/IQ3oDe9+JszOdevRAsdrqoddY7Xoje99boNndekWwM3t01fwjoZTIw3N7fwhrUT3MIXFPu7OJQfz/cyZ8uaTjWHtJOITkdVMC0aR+BJ5YqCC5pADZ1rMn4AVka3pCgaGzfXC5pfXFpwFCumUA2aVxwIN7lCtPu4ZYJv3TeuN7ghCze8N7k3sM0S3FRrJDpdCpcMLne0t7F9jnAsN6Y3vtek8D/TkTe2N7EdorXQz8N3segrSw9v2zMpHst+S52nt79lh08B7iJdtve4+4sXEgeg+gL3pbenB6aaBi/ad6j3r7w8+7i8z5cUy72XvtAM7ZHNCwOAdxmyjyWq3a0Dgg+1xUHxhnhOEsoPrqpNY02SxCXZ2kdtjg+n3b7JIvctHZ95IcsLnZMDTsu/D6dtjA+mg4IPtI+rD75xhw+4hrhqCeomj6iPr2oxOE8PobMLnZ75IY+gKTQPrfk8cZhcU4+uoa1gL0ONktxjA/QOj7bNjKW8LAePuu2Cj7uPqrIVD6xPsHYRsUNCjQ+gT7EPsp0EMdFDno/BgilXV9hdZtXqILKHT7opPo+tixANjhLcn0zkGEAONxJHAmAF0Ak4lD26K6mMSR2oP0HC0XieuKHPuEpKJ0NYuDuibbIimc+89Z2PJxKTIpQDFHpOmkftsmMJrxEdoa5MIsVik68hsDySnzfLaLu1kuSH3xchFoCK+6IvrTfVSMykCZpEL6ZoFBipmlQsVAtBMR6os8+zclIYo8+3B03PvaYQuLa1mrlUr65Yt01YQknPqq+j+6vPtq+lz6U+pK+wPQ6vqBQZ3JQvv9SbtYf1uZCSYx4/Gi+zexlKQOmQ1JoYulpNlyAvp8+3DCavs6+tr6TxLX8Rr7A8CA+/j6QPtBAeD9EzAHccv85Pu2+mCAWIED3GuFG9j2+hyxjvt2++D68dgu+yj7YaCMOJTRA9yu+wiJTvpY+mCAw8HA+176k4Wd2kbQjDie+qMxSDl++m76BrCQOe77Lvo++62jOqp1MOj7561o+mT7Nvue+jj6igAB+6T7SDhB+wH6rOFh+7XYtvvlejH7rvq++9H6FPtx+jTQofsO+yag1PsVADT69MK0+o8BUfqSk0EAHq10+hfZDDmM+svYFfzM+5gALPrGAKz697Ns+sG9XPsrGY1dZvvgwefQyFlaYrr7sFEtmUX7Fvr8+q3x56wNgIL6s1mPJM4a+vvfWhLFO0mG+zbaXenJKWCAkAiUezX6ffEDSL0xUwI/KkXYWZhJirL7Ffv9MXL731vy+tvYH0EES4r67ZgF+sr6lqRF+/UUmvtG+wsZO0kzwG+L4MA74/n7hk0eio9ZZdsx+wX6d1jW2yX7z1kmSMwcA/psSnu7FfuRQG6L/1rX8TtJhlmmegZVk/vJWCb6H7vj+3gR4vt9+pjay9hG2MX6nNtH2NnRA8Cx2+7S/BwHHOr7BeOgRCP7u1mzSV4ciNgRihv6HCVggRkpu7psWQOptfrz+w+6JFnJyVxLDNE7NA375UG3WWv7tcmNXXiQD7pQI/v7zhLaSvCdu/vPkIr6b3OBKJ36xfv9Wg3Y3fvX+gv7jVzECJW8err8HOf6YXDW+tkrgWilOdbJsTkLWPOivwHY+s/7cTmf5DmQl8Hv+m/60fpW4LcVr/tMIYNQJjmf+z/6Arpzsbk5Bmlm8R/6AAc6qLAxX/urob/6QTgv+nB0iNKgBnmR4fpDUKU4tAg5kRU45TjABvH6+GHJtOAGLUMgBwAHsvAQB1AG8AfZkBtRyfDgB4gHwAaV4H44chvQB6mRCAa8u9qlXpObNXE5oAcROJgGP/ooVRgH8RB/+oNk6AfpAjgGI+JxwiQd1PozoiltxWuwBmU5VTnEB6eFgTmoBiQGtnTQBgBSHCHM+yz7IAG5+q1Uw9pNYmNQVnEDUda7HAU29LQG9W2X1AkhvoozLd1toQPKDEwHdLjAqO3UHdNjLQGC2fxb1ByQkkkKOLyNr62WUfGL/Dnu8NVqWsi380I4CRu8B8N5R/s8B1wHhrtneTL7Cjnna3pAzI1y+jMtVW06umCFpElMBt1hKrt7WfQGeem6SFq69AeVLaDAE1BL1YwH9Ach4EIHZWXyB+0srlCOOXQHqgn2imuhHwznrR2SW/profttKrvT8/tJnZyOoFrJqQve8QoH8jlCB+awpoqy4IoHA2R9WUNJWgaiB2aI2koaB6tQlruQC4PEkQWxAXQHUgdKBklwu4H48BYHojg80Det25JISEMtcgd0BrUKeABP+vmawsOXUPzz7iyOBra4Tgb/+xhtCxy3OE4GUASKZC6426Ph+/IgDm3AY3hs9IDcSCK6LG3uBm4H/NWeBmdhHgZD29QG7PryZS8hcihKac4Sviuu1S0pgzm8nNErrtWxCTQFqRRKq+EGRvERB4gVZ9tNOfqzrJFl8AM5qpChCNnBxOytOQdx5ugAaIUUbGitOR5BkUjZwAAZHc1DqLTpSQeF7DvbPCG7RD04yQfzzO1AawgnOcFwZO1pFdTCC+GxBk7teQYRBhkGJIqlaT/c99vYSTTteQbNCTQFYQdzCO1BN0QnOCEGSlFHOakBZOgAaFiF9ipRBiUHNQdZcVUG1WhhBrFpntVc8WhINQfj4PSrbzhMeTC5N7DU8A4HRiLedbJSPgcPYypTzgc+B+v0GUR+Bs64sqE9Bp4HvQebUW4HTVUdB14H2PrEuH0HcZj9Bp0G0vJ5+gQj2b36IPDTQBgouY5Dc4Tw09/CKLkrKCUGkQbT2hQlHlpFBpwZEwYhcYM4UWlYOkCwFloZBwzty9phKVZaywcZ7Ci57BHr26kGLQZdvSg6Gwab2l5h2YFZB3QVX9r6ia7wuQfy/dYQari+WkUGcQZquWFbcwbFXcq5RwclB5EGtAiRys0Hjeka442xqVrnB0AZ6xNgmnUHc2h5BrS5Jwc4hNv4puC5M4qdIhkTBmUBwQcW7Q/5KwZJB4qcwu1rBrZaTwefCt/5fElB6M0G7wZquGpClQf1gIQLyrkHB4qdiGhHBnMGDwYU4icG/wbHaQUHPwdnBzLTNwcXBm/anNPJB8q5Ygo9OSSFGwecJZsGEIdbB/GhYcrNBpHsSWU6DVvwTwewi0HJ8bygSM0HN1mLBgiGA4n/Bhg7sIfrB3UGB/kQiFK7LwY/BpsHXYhT0y1cK7gII/u4QhGlyMJtl4gQBtiHGCH81f/jBmm4h2/7GsDruDiH6uF4h8LqEAZEhqaohIdxkF0GY1DEhlpbowf2AwugYgly6sKrGvSGOTyIsmkA4F9IdjjOWpVIZVv0hho4ccBlW36EPZmkaR5a88UnAOeCk7l0hxpikaJp6q4YYas3rLmj5nVvGzesmjVYaEmrPIbOq1G4nxtch7Wj6fRFWyyEPevEzGZas627gn+CRlsTjFRpDIZihlQNLWlMhhKG8XJtuWRb0yziTdfUZrFuWzetgVnFSalaHIfhNBJoOQj88B415GgtOR6B+0lChmnq0loc9Tetyonng+5LgWnD1OyGIaoX2PmjWoZ0AayH63Vv6l0gEoaTi5m4rIbeOfPV4oYyhsVThWWShsaGt2Uy636oO0ldrDFaVmnbBhyGBodSaSqG9rv2Ik1i7iUTmoJgeZCImpKAQ0Vi0sSpjURFROVcy7NZjS7ttD0wm86GmETacA9QyJq5s5EpdoaomiabaSkTE5QJ7rMIsmIo7oeYmh6HtCjeh0RyqLPDKdPorKlysv6Go+nFFXyawtymXD0VQXgzeW6HMJvMmwop/ocSm+JMdoZOGHNolzLmKGIRgRTUm7YkwRWPHDGGK5p2h32Y9JrUs4p4QtOrsr+Bc3n6cKBrAVkRh8ooAtOsm6UiQ0QmzOqIlghCWsGGViUkmqqyZUTxJQezIYZfuXkka0Q8m0pNS9rBWIKa6ijreUKanTO2KBDwYmhsmg6GnocEcqha6im+hySakptVhlGaJPQ6m1WGz5k2CEjr4YY3udMjsiiFhwqayYbBhtWGXnHsWr6G6Jpssz6HoXRfmJFw7tTGeYGGGpomm9UpkYeO9d2HdYfLeFqbQilZhqroBpvbRAOGiwmTeamHPYYksxGaYykOhiHpPpo9hv7d5jx5h8mGlYaBcO8zwNwjhl41nFrBh9GGIsJVhtGHaFlCiVGH8YeMJXaaYylOhv9pDptehqrSTpqkmhmH8SGoeNOHM0UZh6yzbpqBhqL4SLN4ssuGJASdaQGbOYZWVW1o44bBh5UYXU0HhnaG+zj6HXuGYiilh/Z5QZujh1T52sMhm8MoY4dThiNZsimXhhGai4blhmlwqXq/nbF56Xhh+Sn5QX3Jm5U69LWxed3cSZrpmt594tu1O7lYqZsleOB8iZuD3eh0VZuR+QPsyX2sEdmbd42y25h4NXlK2nU6G+mFmn+GYX2cuwBGG9x5m707mKEp+B060Ydlm2raFZrz7JWaq0Jfh2iZt+mN6aIgwEY3U96kt1PJRHdSottDOw2axfE9+umoXZsnwz36XDXDm7Q0XB2nZGc7TC3QIVf7yEbNmjyJGE0DZK2b6JsX6V4dqEftmkbbybPz2ThGtsHomtGoiEZvmpwtmv0hKEVlHFp225hHiEc9mndlsB2NeF3g+LqyHJSb5Eczmr8R6kxYRl2aJ0JF2aRGF5s/0RcJdIzLmxwIM3i2ZMoARFu6YSjqWslSdPBJNmDdmrXdaWjQIYebbEayujub2PQ3arXdldniyRj0SOvGZJRbZAk8HXWpx5q0RqXYGEYbdaxl3CnERzRH3e09yEVlH5pMHHhGfdhlmjebNXHiR414sFs4W6TszBxlqQ+bcXIsRnRHd5oUEMhGGGkvmnKxwkZCRlqzUMAX8GJHx5rlIJodEkdgu5JG5EZ6ZL+aWrJSRrK6KFrPiWpHC8hAWnvcvO0cjGtqb4nURrJGnkjk9NxGJslgW+a7L4FZ7CJHsFt7bUpGikfQyGRAKkeCR+WsCFotgRpG3niHmoA9Jh0NRbC6tkZJHCVSKYEPWGRBWkcjAUxGPWnZwGUkDEeTTWZGqKQ0R4pHjehV2PJHMvSzhlRHWFsbzIRHothEW005gPhKuiRbvlm+RvwcdkZvOmVxRkY2RnwdjCH4TKpG53UmRlXYQka0WtOCEvhWBvRasuk/bZP6d2RMW9o79fqeR+b0jOumRzHaqxEgc/nw7kYWRoy55LNSR1hHAJmUR4lGUUb1raJGykYT8ziatd1f8C71REbiHFCakltJRliz3Eb5ER7B1odSk1aq0JpkEv9atocQ6hzasJtw+QNazoeImphFQ1qOh6VG5anrW4OboFtTWxbxnoZU6mDbQNptcaiaE1rFRlibM1s1Ro+bAYeY2n+8QYcDWY1GqYghhzuHjUfY2pYISOtI2ySahHIVRzVHZJtRh/UdnyXZCZRHd8xxhryztiSREh0VcYb1GSVGg3X0mgNb8SCMmqmGJ1pk2sId6YadR7kQmYaimoVHF1qlaByb6Rg027mH1TONRldBDPBFh9TaDNud8HNHrNrqUbloqLP/eCzbih0Xhs6p3NtAW7aHZUeVhud5a0fVhomGRRK0aNKauOoc2/WHt3j/W3Kac2sA2pbCipuhqLtHSpuc2g1G7YYTW2Db9nldLUj5x0cPNP2GnUdVRzSzvYZVRpckVyDcRlTbA4ZGmgjak0f6mjdG7ai7RoOG7akg236auOpo2h6aM0bLWykpZRK87e1GIsJeRt1G4Hkrh41HHmQ2mndHjUas0HaaX0ep+YTaK4chsrjaw0Zrhx1HjUajRk95G4f1qe+qbporR6n5FiA7hx6bIMYI5Ze4jOthnOkyJLJ1h6n5XPBHhxdHUImr/ZDGEMbLR4DGrUdTW4HwF4ZlhvUZ20eXs4dH50ZXhqOHK0fP3beHb9LRm41q2Ssfhu744H1N7ZjHwEdPh0mbnxmvhrUR1vmXGZLbb4cAR8oSte0vhpLa/4dfhuH56hM/hy4hv4cK2/jGPLsAR2TH3vn5m28YOhLExlBGoEYDean4vI2dO3n5XTvq2y0BPTuNKiBGGyCKtIMr4A06294Vutt1mm+Ho/OI8AhGPE38+5XazZoZvJba0kIoRiqDQCnh2mhG9XSfA6HaQas2/K7b1duDmozqvMa4Rhfpx+pTcDzQg5sYe+kNGKlG2kRHn8FiCKnbGEbQh9wonMfSurRG/Sk+2xRGSoD8+bXaM3TKiSwz0sdcRyjrisc2YbaH8sYY9XmkF2o+h6uahyAveX8Fe+XrmyRGBdsl7BxGWsdF2g1tukdyuWLGsSwfOvuaiDEB2sRz1cyWYCrHn+UCRtqhSsb8xrOb/rN9BabG+sbyx8bGV5r7wvwIGXKJ2yKziYiyx9XaErM06o4k4amyR/TFese2xj1wGsbmxtzHOFpdiEQr5sctbN0ElsafmjmG1sbfm5REIsaxLV87v5rWTLLHZAmwu5+IHsfZ27pGbsacrL2TS1iWCWbGxXKdUOBbDsdcx7NokFtbSPTrksfQW0HH4ccy9I5MzsfjSVZGRYlWxw1wSFuV4OpkU3G0QG87nEiOcSMEUkkORzyyMca2x+Tq6sZhR+7ayI2/m/8KRCuOx8NsjHjKx8XK4wPl28Nw86Vm26iaqccQu1rHXvD2G/IdGEyzcatRtbuVcU7GGXPX2DnGQsbuxioc4cb8xrRaBEHxJXHbYLueHPKbGKl5YPc7TyDM6uLHkzq1x6dr4cdUsspgyFh52mtrSmCKxoHGZ0Y1YBnHytxJRq3G2IXlxgAMXkeKxylGvQKCxglGowO2x93G4wOmxqsRUYaxxllHdCnlGPrH0Lpdx/El6NwFqO0G5XredLDosZkF4sddpLixmMqYBhvgBGPGsxRjZPAEdxzTx5McMAYBQDUovimFVf/SliNNScVV08ZDBlOZE8cLx3GZy8ZLx7PGGwuUhk1iZAzWu26GhmWsIruYkDtsIYoBgiLuOY/axAqCQOf5L7RT2lzA+8b7MAfH4j1NZOf49XAL4W6HNu0KIv60t9sFwcbz5tWau+Zx2+AN8rqYNZlWcFl5wdDD+XLJKDtuhvHsd8aga9vHN0lt8ojMZrpSPAkRW8fPx3vH6Isbx4/as43byMP5QFkz226FPCI2QPPaSjxkCgdNqgguPcfGJfjLmb1xGFNPxn6YmQiDceIobfEKIoUhqUluPA/HApjnx2Y8Z8faDc/bZdFl8fvGm8c/xsMTwhHvxmGEx/AnxgRpfj3dIbPK4Cc12NlwEODhZSAnl8fVVP7srJkE6Xq6Gj3J4XUIr8ZSuw1VyCYGmKRYwCfKIIgn9YgXCDgmLzFwJqiCeCYuPOVowxINTZFJ1XkGyKMTt5k6mIAmuLloJvfHwCeu8PlH7yJNY5mq9QFxXDxwz1gKAvwgwxErpE1Ya1hgDO5wOUhJhPWl6EtVxHpwmYlN8TQmBE3MJpWk9CZ+gyUZaLl0JqwnAWhBcXWs7CfRAgWoAbssJpNY0cRGTIEFH/W+5RD8vYDIhvayTgVIaGyYbgRaBPc72AWawGLIPHAPWZOrUMGTBgIm1AT3m4W6NCe4BfGCrCHiJnMtO6sMJuwFEqXxBIhoWXCpB0bHfv2KJzSZYaTfIy048ifZwAon/GA+/TuqMKGege/x40kbSGxjdLH0BA3BfHsH8tQmUgEv8XYxoQTIuKYwqiZUScdYAsOYuSulfHs+BGIn8EUrpOL9tbtmJ40JK6WXWMYEJicxCPqtH1k1C3wQ4wcjAHOl8pT6Jr+ptokyJnHHQkm8JpQF2ekqJyukUNk9u/xARgmWJjImLiY8xuInjiYEBRWCriceJ1ImUFuTBqDNSWnJGsBbSiYzoJ4n7iZeJ6wIU7ucQRBgCibsJrc6/CZLpaEmRRpwiAukpnn2BNwEdiaqJqInFzueJtK5AFgx5EAc9sDOIY/wx1kvaqyAcZUrpO4FZzpBJ7EnCidZBNwFgiadLVQISQQRJ/cGUiYIatAhx7s+J1knISa49BImMOuaJqkmqkhpJxOM6ibJJ7NosQSFCbehK6Sw2domWXj4ESukg6WhBVDKaRCmJokm8k24IDz9dpFVupkmfie4kTUnZdEmJwkm6gXiKOYmBiY9WPEnSSdaJ7+6BQTRJ5Um6gUYSY0mNSfvuikF8SapJ4rgXgSxqBB6kbgHWIprPCbngA5J+WjWJziFzSdysk4E7SYeJvYmUSckhEYmnCe4Bc4TDlA9OV4m2ARQIzonriYg2bBoEKqVJzYm4NgkvPkmVif9JnhoWJFlJz0ncSfTJs4nfHy6BNpMxLCzgY/wRLhmJ2Mm2noNJ/4ErSajJhsnxidDJ0En5SYIa7OICSdMCHomaFBBcX0mMvknpPsnjoi6J8kmvgWdJyukBSdBBSknuSdyJyMmq2C49TQnTEGiyFz8gScTJtImqyaCCRkmSyYKJqcm6mpzJp2JRSf3JwsnByf5BHcm5SflQBEEKyeTJk0mJQTrJ+z9fiePADZSPtDOJlkmXfHMJm4F3CbivJImZ6XhJzRJ9wYTJmZMBEI2J51w4vy98CcmiyYGBLHwPyfmJ1uhgoA2UtOCj0EzJk4FAljCiFMn9idJiIMm1yaua7Qn1CcApkiIVyfjJ5EnXAWm4hC5ria2JyiJKya6J1YmeGlIGG8nkkSw2SiI1SYnOR8m45kERhUgOScopm8mWSeOqRCmjgSXJy6o+pmjJpQERoIAp6omBYsoIk8nsKdiibQRsiZ4p96pzSbfJhSnuyewp8EiXyfpJ+En+5tLJ6SmH5liJjSmlyfxqDaAoSbPWUEMDyaUpmWopKa/J98l7uElJ0TIhYiLiNowiKYaJkcJsSC6YEukOyY9UwwmqiY7J/I0Tmk0mRcmRSxLGNymAqf5LIKmbJmEp0tYKjW0QXThzid+AHeGo1O6dR+kmoz1evnQr6sfpJZB5cGNekNqvWrSpgX9kqfFe1KnD6Cl/EP5BXpBXNqiBQQNBDow8pAKpqXQhMgF/DKmZXqFegl88WBvpEqmvCCVwNpViqcyp1l6wlP0Glqn0qfxEFKnaqcqp+Izuqd2AplcwzoYBR95XbwZB40yI3sCC1cQ2zj10K16Fqeq/HYw0bLkBVjpvvyC8T16MnDbWH5A0gCqoTmBR2vWBL+plqfmp78YkQQ7BuamO9qY/IYEPTnWpi6nQulpCE84gPGTe4aL7sDSBc6nbqcceFelHqZ+phSS1v3+p2c66qa/qN6wy3qyBH1ZqLmWKat7aSbbYABp9EgbewBr86QRpv7BXAWMdH4E3p2ucbBpZdHhpr6cdCtG9EAcoabOp2+kasjiBUGnZqcus4kmTxDW/b6nZzsWpr6nSLxde9BrT0GSgKxJyXAw6uvITnWTm10y8k0+ph6mLyrwjPJNeIVsaRGmm9mFpyygSmnv6J5w+ab+p74tV3rw6rmnMLnBpzd6Waf7w16mVqero+LYNafmp+iE4XVRpgohVaa3gA7wwaflpnJoMqbxp6Wm3WDgu8jAJzjFpspo5qFB/DrTrMl2TbWkBadaQ6tQZgTtw1GnNKu6BVmnlabRpkUEWcElSw6nbrMgu0FwPAUFVLqQJac9fNxIXLJjp2xoxHr1M2WnI6YwXF0hOaaY9TC4sIHBsv2n1abppr2ntafzp1jr9aYAgKmmAQWJphkGpwCd4b0nbaYZBo44vnBtpvGnOlw5ccumTaYZB7NI8EmLp+z8dqc5gAunHLhe8XlHXVuV/Wla88obFTMEUgxMIVoroBVaM+vgc4iOJK7R0bHD/RgNtwVjFLsFg/zECbcEixVDBF38g8dXpz0ElonwDVcFp6YSCNCJW6HSrIfj96aAzIPGt6efBNIJrvCAqqcFYSWwaU7ImvDPAxKp7sDDBFSZb8o/BfBa8yLaMXYxkIUqKUcjMQTVqsenbITxYaMpRKsN5GcgkQ1dDeemNweWyyOo4Bw4q/gzfISQZv9gsC075TpJO8Lnp9KtLfmChCBmnlwbzEKofVkLqEBmV6eIFNtYswUnp8KjdilHIgIEhGs9FD2a8yJsiB3LocGqMjup7jmoq3MQCIU4ZxkpmKv1KeymikSU8dKt36eEhOO8H2FEZ5UoBQx5W0em96dHI1SImknPpoBmkQ2QZqRn/wXyNL+moGYvphWJ6Pn4Z5Rn/QXyNUYFA6rAZ/MFhcV4kfijDBVKAIxm1GYbzHRmPVK4ZvBnhYyl0j8IlGbsZlRnX8B6WgxnbITmivvKjTOkZvKTF4i6Ko/lhIX9xfRmG8xByGcEn9KdMSMF5mlIhTldbDiPpxgVmkjCZjQbKwVyKPSFiYpEZkcFf6e/BOUKnKxvp6CEt4lJSEcEPGdcZw3Kf6cJKAnjwIiIZl/gMmYJ4iSIF8GDBZJmk6ioNXBniGecZ0hIXmWoq7JsYwW94n05YmcmUeJnXCEmgeKjdBQC9O518mfSre34EIVYZo4k4mbhICBItGdoZ5nAEmZiZpxm+RCl0tyJJGYbzKxmutMcZ6KiOGc1XRJnpmdf4xnTT6Yya20UTok80i5mKGa9+OKFo9BWUURmn6b8hA5n/Gf/BFzSgQuCZ+xmbcF8CQqjp6cSnd04KGeqgXiEZEkUZipnXZHqYQzSamaIam1jBGbBZ7pn0q0iZ9jAwWYGZ05nsuEZ08hnpmaOZuJN4/H+ZvZnPmaCZ8KjmGdeZ8JnPRToZ8VcTmd2Zp0o5IVuZvBmR1uj0ulnmme3Jc5mqWbqZ9yFSWbSZypmYGZchL5nAGYshISZRmtMZ23SsWZyZqpnUWZTaI+nW/j0hY+5IGfcollmEWblZ4hmGWYlZtxnPRRpZwFnDAgoZ3pmy0l+ZvFniWdIhL3TwWaPpn5n/TDECM8CdGa90/+m/GcKZ27TrWf4on5miNmGWeZm8NzHBWfT1mYiZk4lPNM0me7SkWc35Z1JDqYaif5mxGZZnGqZfWYbzEFnMoUD2D1nLqw8Z18JDECnpn5nitH1ZiNmAmf5wYpmxmZDZimI/5q1Z9Kt7maFiHNmq6b9ZyoHs2esSkpmmGeGZ/Kg4wNtZ9NmgWf5Z6sFwCR88etn8wUbZ85rY2dbBJGYAGcwZxenZcBhZ6iqfme8mJVnhWck4iyYnmdKZ1sENVrHZ9tnqwXZvNVma2dnZiFmAWcPJjv7m2YViUbGV2fcZwxnj/ERZ8dnbIV8fIdn5GfifUdm7KsDYlVnXbkm8f5n8GcphfHFRiXrJVZmAuOWSFZnBEFjuGyZ3K1tZm9nGIXfZseJb2YBZ3J9PMfkZ+KneqwrKbqEv4ASIYDncSH1u51dwOfc5Zj6sSGgstqEJtR6p+JTTSpchbEtWyFg53uo0Ocg5i3jX6gQ5qjFETng58CCaeCapjRxcOYg5mcIr3EUkPDm/sHGphXVJqeGhTgoBIVHKeMqJfD3yOsFmOb21VjnU8nY5/rp2+DDBL5wHIRG1TJIL4lQILQtF0R4qnj1OjTKAxdEwKqEZgTmX7ly6TjmkQy0DRNEZKo+/KTnRIX61FjnfKbnBbdk+yvU5zPgQvVU5s8qDObBQLfrjOZY5t+IpIXVKZZRmqAVal9ovISPOQtY/p2aktzJF2U5dccEDPEXRJb88Qk85oCqPUSNGLZJXOcfiOcg3ogLEQcE3wQk5TSQXMCs5wZsZOcycBVrYFnISGTnLOYqNXTmUuc456VcTukMhI84TkEa9TRx0uYC5YchMgTudFTmAuVS5+ZKzIXK5pTnveKWy555bOawIUhJIucXRWyrV4gwRELmeUScqo+ItZAKDZ54gYyP2brmnWMc55lrbJlaZtjAgIRnKCrn2ubhKRTm+Oc1XXgCdUTU5onTOMmS56rn2+Bc09sF6uebAkrms1ji52dk8uaJ0zmAIJrnIb0tG0gsISL1vOdXQBEFzueG50i93SBkSI7mxRhcuWcrPNOfYc1Zz0TrK17nNufi5yxwutOBSUUpZufU5u3p/PQy59bmueLXIJjkLYF+5iBIMHFlSD7mu0k6SHfYQEn3RF7m0IRCDRdFjTPu50DR0ebnIcIRSQhh5riFIedO5wbnYed6ecYVyeBh5iHnjOeK546SFuYs5zjnI8e9hfxpePuxOZn7IPoQB5nmVPvq4OkxZPuEhtnZ2ee55hD7FPqkhoXnRPsF5477FehF5iXmpPo6rNnmpPsuBu7gMPooNVgHJ4RM++H6x4Vw+4AGJebY+igHO1ybhST6uPtCcKxEWefY+jXnDPut4/Xm9PvV543mDedGNG3nhedN5+3mBeZV54SQHeaW4Mn7IW0ikpJsdUm0+zLjfeZVOUXnCPsK4QshBPoJ2Nn791JUB6z6jHI0Bn+kYusc+1r7SgZXcCr6kiEsB7Hby5Xc+1PnBsQK+8ZtTYusObL6bIecBgUVlvp8KDwGlcWKxTzYiEQRBMvnYvvmaIIHrDnm+jL70y3riPuYHC0MCTSGZtv8+hws9/v8Oa2V0+cq+1Pmk+agtBPnjUmcJMItLKlT5i+YcfBW+9uKMyxa+/vm0gdn5eC0M+YX57NZFfF6+wvmJmGnJEvmMkq0Bhr7xvtxiL3FF9r75lPmF+cgFKfnl+cWBgv6utmjKbZb1+LG+yrJP4sLUMOUZN3qB5hLgSi62Dv6O0n0cLc1XwXi+rLgRFmv51xKsuE7NZL7DfuDxIiJ0LT7nfwg/PBP8kylc7HGB7/nK8i75rYG3+f/8afnFgef5+fnFgb35/XJEgcq3GUkHCyfkOyAlCaGStTYEnIkOx47wCiwRLo7pMioFtuiljvpIAhFw1qYRPk6VMWYFhPFfDuBuhwlWBdXQqshNjs4F/PLNju5O4RBiYgsOygXdb2AaBTy9jsKxOcUkjq/yc29t1pcOj46K1rHUKY7ljvilKTb/jvDWfDaoTuUF7QWfMSrbDtbCQAiO6E6+Rl7WvLDFDo72MdaDBeRO1xEx1s8ckJFXf0PQzQXsjtA7KOiKBdhMJdbi3iKOsDI11pzW3PxtsSQx2NY2TqIMY8DFBaqOmYc9wPXWpo7C8jPW7wW2jr0EK9bvVr5CHgXD0OR21IWjqQWc4Y631rppYQkMhd01c2UtBeq+uY7Qheve4DaGBdoFsf7wNrTxcY6oNsM8uQX81rLCab7pBbie5DaLjvEFvjD0NsJxWoWsNveOzwWLNnI2m47u2TVbQYWHjsqFvjCdBe6F8QXlyS6FgbF4BRmetTEihcY2v471Bck2tE6s8o429IXwTsPJRtaHjrTOATbdhd0F+E6rBYkGdM9bBdHW1jafDvRO6Ns5NqxO1wXnQnPJERZ8jtU28eilBfPITTblPjJO2EBvKSM2qk7ShcR234W6TsiF3KCzNodxZo7CsSs2uo7EhaYpOzaCk2EFoCCShfGF1zbdcXZOhYBAOdNKg5F9FnN7Cth7YMlO9jHgtrvvPCcPd0JFsU61Ma+RH2CpkWj7MLbZ/U97Y+HfQC+RUU6TTuskg8Fv4amgy068EYKFNLa2RaK2ypZo+xDOuFF8JmgR1JEaWmSAOBG8I0VmwzGdoDK22vc2toBRf06LMZUVbdSlX2QRyK7f3F5+pYqmzp28anaNRdQugOptRajVMOYJLui8kRZ+zpHazPLPHNNF6naO+e1jZS6lb2b57qN5LuO2iSAh3OkunXbCJWR2+s6rRZq0tzsjRa22pbdXRbe2/5ZvyBzmR0W7RdH5yHzbRexuv/FIfOeSFbalXU7NT0WYdqKRH869RaTFtfbx1W0Ee2bUaXQ8rM7HtpTFWNzExeJ20sSnLLw2zc7ffpzFjc6N5qXu6bFOfJM8ana1gS/ckS6zRelpD0XfRatzfRFALqHWODym1UlxudYLRbQu/dra1ggWZOM/NQFqTDCvUBF7TsW6MI7F1MXt7tyxJHzmgVyg42Y3Qk/O2C60qCk23mM3scIegxjPgnPOhnaDdK27DgzWLvXF9i78zo3pA2ZQxfg2YQkAxb8e3ORlzq1FsbbPaXTjX0WRD0ryG8XhdocJBnzizuF20tbuzs4u1naALpYu9VKZdox3M876dp/FrS7ELqtSD8W7ow5SjB6hQrfFiC6p6WrjWcWSBeQK9XI7uI0oWYqo7U1s7pAsJfSrQfAlKjG8fwiXWee0qVGXYj5pAiWrobVByiXKwTomuQjGvColx5ZDgjXWKVn6JZYlqXAmJblR/1pQGc7ud6GJClzkFBnc5FNRkWIDapyZxYpGPUTYb+nh4g9FPHxMaUghTCbzGQGal/hFJaow52r4hG9mW1xIJiaZ0NjgRRh4H2rfRAJhhVp8SZMZsqY8JudREiXwqKkWKrG1JdhZxtjiRSUl0BntpgUWLEsVkDkZmQsgqj8Rwxqz7HVFCCpc5BdZxkls0d44sRqG81RyfNHgpe/pnrmwVj8llhrLq0dh4XHmMAIllGb/XARuVmqG80IlxRz3om7qhOxHln0l0yWFcVSm2NEQpZUlx5YipcilnCX2JqagZ7SUGYyl0VoFPT8ZxrBxohlcEyXgmdqlncpvVmoq/XEbbLNEFYYuJemHHiWKGdql7319cX4o8IpSHJ0wbyWHGjjRDPVipewMo4cp0PianyXURwWl/dzDJeMJGaXpJaMURkcn0NilmSX77NTQeSW6JaNh7DjvmpKl3kcspYqZvaWXnFOGWFmMhB3Ra9xLJawLIyWFh20ll1mupd9aS/L1JcceEr4iYyIPJFmUFk2cEWZy2cnFREdhvEOlzCR+4cCsvrY2Gcal5aWBEFmljyX1RxWlwZn3pctxiaXGGdhlr2H4ZfKlwKWzWhveVhI82aNtNKo5vhqI0RnvhjiWq9DlGojZgKakXAJuRaWppZqm7GXqKrGljTobykSl9KW9YcP0Gwi+pa9hsIFlJee3OR5dLj+luxnHYYT8m6XqKv2tXBzbJYll8mWWUYulwZmD0Fm6buIaWiclztQoMS5lipqlpa9h9GXgmaTQJ1pIRQ6l05mSvnxl+mWqyEieEmWqZc9FayXMXFKQS2W7xOMJE2XVpbulj7070OKlq6WyPnZls6WF0fBQTWW+Jcg6ZWWK1k3psDxg2iFl7KXnZZ+9aWXJKuel7K5vxB6Z62Ws+l6l6Ki8FgjlvmXVZf8IqroNZaFZzGXxpvllhSXhpooljlIjpZAeO2LwZb9l7N4wZYaliqWjLLsYWKWj7QKeRtiCZYjZ2WWJLILlsZmwpbEJLxpc+H+Z4SWZ4ZolwuW1RGSlmiJDWlWlgAc58VSl9yWhpaBQbmX0pcHl8bhzoDGZnuW8MdTl4FmaZfkPQOW82e8mhGagZbGZvWWV4a8Cctmy5ZXh5eW85YvM0SW22cPl2t5i1DbZ0eWF3gOlyuWyJcfuSOWOZcvxY41bparl6FNh5bYloaVP5Z5l5FNE5a9l0R5c5efl0x5sZfgZoaXw4m9WF1mMpeoJV+WoGfAVp+WcpZVTFaW45byRNOpl3KslrBpA01SlzqWEVGDnbLxsnKNlyr57UXywIuWcvmwVk+WyFZCMnmWvuiIwnSWb5e1HXez0ZvtBsPpERgFIT8FLrHYkVhWPKFybJ0RNXuYVqEY2FdTscZhQkkrIL2BeFbjajGauFeWIazJnWowLDlJuFZkV4Nq/uJv/TZhCMUl7WRWw+iPeOkgxFaUVtl6VFZnmMohFFbRXAxXRFaEV7XKILno5jCWv0QAxHGkF5sVTZ9FbFdCRzVMNUSGZmRG6vDC3LgzIFtxc5HdPFYzWPOI4OUcV/1wcRA8Vy4kZ5uCVidFXFYuxuWNVOf9ST2bdbTJ50JXOFoGZXp5FDOKRm5k0HlSVzhaoyEGeJuJqkZ1oRp5eSiUWx7x+0WZUfdrBMjGeAOF/sdC6HaMNrgy6FuaGkiLjALnb2vDcXzwt0X+sHnHslaTKfy4hAW/m9JWAecSV3ebklb05xxWFceo0mJWiGH0Wo3V1n1yV1ZH8GwiV2JWFkfyadopMlay6YO1NHhmV1ZW7BAKVxIIVcaGwkpXK3WglhYdGler6NJalnHNKE7mDvDw6YS0q2UCVo5X+0UqQIJb85y6VlZXaZcD0mJWMHFtx1y95lfBBGlGWcHi3XrIwOtPIG3TqeZDxnlIq2UiICi6WPirZPUaJ4iBV4IJQuY/hLtZ4VHWfPflk0xi6hR4HlewW85YYMVuVp5WJOVrYNFXukD0fTuYdOsTIc5WPUSNIWFXH7D/ZXLCW5tz84lX+DMgWt949HkqVyFXsVbZKMpJwJY7EYmNOua5Vl0M77lZVvDoP6nhVnlFEkme9cm0JUV/MtAg0JZvU4ZLcrLSls2qKaMDWBVWmdi9W2IxMGrBLKPklJPmUtmqSC1EknVWXauXyT5lJap7qvVWRBdRyOWqMwWyxeG4latNVv1bn8vtqkgsI9lA2bWrzOVHA8BNx2Fmalyxi1qB+Dhqi9WCOKMX5rHAavMEG1p+jSxqrVZrWrqQUGotOFta99EwaksYjBY1EQOrztjKLcNYk1azqi9oCEXtSXBqm9Vfo0da5LPcarJAp1pxjSxr2elM3Qaw26rfqmylLUkZJEpqZtt4Fl1XOWoihFdZfVZCltmFRqGve1tXdGqwhTbbXSw2ai5rOiqjF2tWs6veMR6CK1ZVVkNXw1j2jHprJ1fRS7ahk1amaLRpUaQPQUerZ1fBSldX8WqdV99b51e/JCNWG1pGcQ6WpekCLFN6d1d1V/+EMLLbV5bEbbMM0cIoZ1afBVMCbIFLVtdWArAYaoxrb0KJYCJqIw1HAg2k/VZOLSjCMTHiao9XP0IA1r+qccF/JH9W21YTV3EYJs37V1BrIMOZSQ9W91Yb+o/svVfvV3DDb1ZyaqHozyQQ8IlqoNeDpdVWmmZTV38kiNhzVq9Xo2xw1wtXowQs2R5w7GoCawItkNdyIGhqti1FpINWl6ubVtt7YNfrVrmkN1arV0TFj7geahJr+Gqg2a+q6NYcpCmVf1cRGbyl/1gE1tmFUWn0zNLQLVfka6cFPyMbJORrNmqPW6TXANa/VpjC61l0a0dXg6Q/VutW11YcSEJq7VbPXMNX5Gv01vjDp1d2alCFTVnpaIlr0nSPWhzXC1eU1pW9O+lo12TXTSjLCCwon1fY18G9/CNGaoDWlMN/Mz9XFtqqF3TW5WpmKlB6NKCkauRI3BdU1qmXc1Yk2xLWMmqI19EZNNdA1jhTg6Ui1/+qQERw2CJqkNYC10zXFVfM13zWamt+SEBEPNcma7LW+MKjVlpqwNfRGFzWdWqChSh7w428avzg3BaLMkFrb21ExEzX3mvrV8J6MNcdVl8CbOCLSEbXssSpsxDW11am18+qZtfacTjWBcF9bMvwZNdDdbikBPhua7mEO1cm+z2NkWoHV0cCRH3G1t9WYRddjLTW11dimStWzNZxvDOgBtclME7XrZAha7TXCsQGjJ9We1bFbCzWJ3221miCUNfzqhylXJhhaw1WOIPK1ibXMNxRIvbXStdlvb8R0WtVV6CkD1bm1zNWrBdcfQtW0NeZGerWCmpDVi57Ttay1lHWgkVW1jHWdZhs1kHX/MUJ1q7X/MV011lq11b4cxRIz1a2xIIh9cQa12dWasXp1zdXK2xfs0Sg8GrzV3iVUpglamOrOdY7vFNYotds3bNXjel41vYpJax/yonW8tyTQdHWUdaJraXWadanvPRhCNZh16A9GFYYxrV6UvCBxDlKOFYtozXXa0FzEcRXsqbZKgsI3sR3/DRX64C+xGgxY2qN1jXXNB2tag3WddeE+4f19dZ6YPqjvxn3qK3Xzdav4S3X52sN15RXjdbNWN7FnjK9193XWqF913RXeqdNepCCEOJzat79HtrW1wtrWXAW22hJJIw/VTHbvttg6rzJIFss0RQCqOrmgWmlbwiHauPXqdvtSTPXB4qTFxexAxhnmPMXnJFNTNPWixaa+TtrKjSTFur5IOvr17tZKPhkE6vX6xfZjIx5yajecDX6oUhEjMdJPyJd6a9qyyEHF6sCxOfzqFf5OwJwlBDbOgyF2rMDBPhBhZpX31pIHHmptnDB84O7oi1fatctm1kyFE+ZjyiT1zbbIgWna4/XmxYC0kDqIQ3LugZVz9cjEdDq51mX7RNMT9Yb+pXqX9fJ2oD4rfQf1pcXroC46hLo8doAQH/KRvi3TaCXqxfH16JoBanQ1hTqQIgou2tYcgyDqV/XwDYI65vXidpNaFdqE6ir2bDZZ3j714vX09ZA2ML4u9bllN7aZxys6omUnuU00RAaXqm98V9AZVZpq4aELPjSlqXFRW2WkK8g9zxbOaR8/tzDqzHDDvE+hcLFs1msTDg35HzrUWiXmDeUCCx9GJZ8Clg3TkkeYesqxDfKNGQ3WJZKw8Gz1HxuJNWr5DaBiN+ZBJflxXlgQyOb0sSXo8XDwWENzUENlhjCM22C4kaX5cRUNlTwIOXXlhjDRWzgaH1YiGqlxDNsdUi/yJpm0cUXbFJ8ICsDqst8+XDFZU0ZqpZKwrqQXxwhZR6WdxTg7ftIRmVjlkrC9TNZuWw2BmrXFDuSYUjYNkrD58D9uJFBDGrHFZuTBkiGIFhqxxRqyEacTDZClwFonZM6SYo3b8pLwOuSj4gr0/I3bnlWnU052ZcQ/UuTRbnkBPPLDJQcNunXhZY6NxnEoUh9q5o2tGkyfUw2NDZsNxwFKjaENqBlEwSCN+w3ejddWPvLsjfGiBSGfDcLPCY3Rjd7WcY2L1htsrLhAXWxxVY3ojjbWQQ27L2H4uY3jkz6ScXFZ3iyN+o3fmVdLYY21ULX4xd54moWN9XEHjf3cvw3xxxuNko2WGxCGf5Z/JasN1w2YnEOlkY2ZgYNiEpmgTe2N7o3UrNuOBUtnDa+N7Y4uDY8N3ya8hnm3bg3ZrMWORTcYjeElJ1qVPEV3buqnjexNoD5vmoKNvZ8ATfmN4az6n1pBB3K8TfH4wRANjfSNvHEIw0blncVIOy9xTI2hGqpNu7gaTdiOsk23BhSdRk2qYYNtOYlSZZIlHBzcBkFNqmWqjeqfXk3HjauN6G0vVluN5lJpIwpEpo29jcLoWExRmp6N3RDhyESNs43pI37E3E2ZTdKh3aHnaolNwyM3oeNNu43Y8T1Nw3LAWlFcTPFEuDsNok3BjkUraeX2TaVNy43tTK08OU2SjewomY4pTdeNtr4DkLFNjJqIjbyRO7hZDcONtGyxWT9N79DKca/5sY3YjshN4PFWTcLPaIIFEJfMCpqwTftNxI3EzYX2HY3A8S8NhfYnDa5N+6M8hjNN5w3GUOafK03dja3g7XwouC+idQ2fTbxxZ02MzfMm4e1ycghNo42ZPBC0o7WRjeshk42rDYcN8uLATZVN14FKTaVQmXEAtOlN+OzLTaq0ns39JryNONJCMATxA03y0hENwuWBjekjNY0+Tc7NlTxjFqYNlU2rpxdNnU3umX3LeeWSsN0N4jJaNW1NgTZDIww1a83XTISjU83CTdbN3c2LKD6EAc3ykK1N9Q3UzYGterQ9tbBNjbT/zZVNoxLhzeMsl8cajgxNjU2MGWhNhM2dzeEGb4FXjZ/N3gSo3urN6w2YI0dLa02kLdUZDC3ULYcNtQTIFY/Nm5D1jdsCKC2jGSNNmE2dzfc8GC3lDYQwlYGo3uLNst7BWQi0wlJYjciNsVCXhzSNrE20WROGEXXMTbLE0/SPDawtqVCTvEIttrx5AWLN6w2bWVmBEi3VjfRFy3sb9lSUfsxHddHUItYp6Ez0CPXkOfktqfZFLddMOSHecHJxWzQ/db0V0/7tLbUt3S2LeasgdugZx2t1/3W2qOX09vFDLeUt//79LYboRy2oPpeaKPHe7CswnhjzLaN5yy3r9Dct2jmdcoFbBRBs8WzoA1N0MmHuR08pHjbaqK23TyrIEdq3Dajxea1IFpboP0JCzxStjNYnbnjI8K2aXF4yCFlkraFANtqkra/PHa0f2uyt7U8yrcx26Rog/Vyt4q3yTsrGZeh5Yl4yek6T5iatvK2HBgNlox4mrcnxw3F48VbPeXBcBkz4Dw6+/nQusvndjssIii7xrZ2jWwC+YBbmvPmPDsL8ZpWguo9xMYKzkZ75s0IE8T/m99qY1HIwPuY6rfKthq3KzyKtwDrgBcWtk62WreSOhfwDreqt3Z99rZit8q27rbatqq3Ore0J5U9DJCGtq1zkLWXoSJR92sKODNE9zzP8NJavcSnEbq20zxvO6gCmHhut69mUnWcSkuhVxCIGXHj1T1zaUnHg8VMoCWVVEtJxug2VTM6CdcRTiDzyq3Y9Vbxty7XuqMeWOYcw6sc4vCaPigNV0m25UapSWiXCbfehvVy1atptn6GoSvrKxm37ofZtt/LJ1b9ctWrObfYmvpbLaTRcwdXpyE9VkW2JJZy6kKWTdgDVrEtEmD7ygW3MpbzLXjyibfHZJxqZbdklh5aw6qAyvSXHVJ9q3rZU1csHWerKbbLs9spcGpLdIya1bedqyzZhCxMHZW3pOJjTSKp/WRJt00Y2YaPmETWRaPo15zz+1ZFo5jX2dr9V8iUvtf9tkKW03VihJxWmPhYagiTRbfdtwxqvtkYLFKX8bavS1W3Liu7q1m3FHOeKwOq47ZbR9EtpbaBSUqXvixDtvdXkFqmyQOrFbfKR19XPbaalvPhjbaQ1wktC7aLV7qWk7lo1tO29hxNVlu2xnMOlrO3xpczLcBE3VZS6fpl67bc1wKyNkH3cyu24ZZHt79yfIVfRAe3b8p1t7aWI7YdyjW377MZGQ6Wy7bNEA6TKPLQ1hYdgjkNype2XnAwJIhq57c8slBJtbYuAdaWtbaaZm23qHn22JxrjNmi17e3m7c6ZBh507kY1odKwMUjuTu3OCnft9jjI7aftuGXwhFvyu+2fpboLeJqr7e6l9ItY7b/trGWAHbgKgLE8ZZAd0e20Xm8eGLq1NZEFrgsWUfZtleZ8mnceaTkBNajtuNFwuvrtqzWARh7t1tK9VdyYVxTRmvbtiMN/Gq7t1mWU7e3y71WaptyIa23sHeBHBs9WHfxEQQkpmkftq6qlZdYKlm2v7fVl8IsKmrHt7WXSHYlo+jWcUYDt122M5YQdnm34tesslB2qZYtt2UdlHYyag22HZfkdoTzBi1plmB3f0rgeCB2hGrXti4sKmpMdgR26PKw1pFxJCt3tvMwd0SZ2dW2z7fXRBx3OHda16x2d7YUdx22U5ftt+TjjZZEdqh2oHfGmmx3v3K3twoHNtcVt8aaV7YVtvO2fzKidu9LQnZ/th3KCJKQkiSzXQVAdkGxBCTCdo7XA7eHPZgs9tfwdniz6bcLluh2I2imXPB2kNdiwl23J1Y07UzWSnfcPZIqSmYKd3uWjMkEdnzl7UzWBWh3WXyYszZTvmrEdh6bspIA88h2OnYGaiJ2b7nlUc5q17eI8/J2KnZnHCu3X6lE7dVZb7Zmdjh3D7ZidiHoeVQE1te2NnfSdjHXhPA8dwZ34Pn2d4RAt7YJHDlqDnZAVgB3n0vvVmBWD7c8y6p2asyWd3Z3S5RFa1R3yRyfgHnXi9j51y9FTiFgdqjWuuhPtpVqgHaIV1DimmbXt523Vneqd8F3YHa3tx2S1WuOdkgs5LbKXRMhq2k54bXWQl2RdglgYBhst4y3JFf2XLVg0XfGYa+dKeHD19y29LR2XRrQHdeMVtx5HuEpd95ciamFsEl3CXZRdkzRGXdGoxj1mXaxdjRX2XYZd13XzFcqcSxX9B3lrRkjUDeHmqs508lf1kAw8vm4JE/XDUY9hfglPyX6R2pJgPi3xfPWjUhRc/hNzcgld9spSk01dyJG5XYcZUCdikdIqLDtDXcx29kI4ziTbF2bmzWna6V2rXYjgBdrbXeKR65ojHm4JAfXnkco6xUiilYQwWQkE3XQuif1LDIyJKpWbF3VNSjohdrSmjN50CVM8axHKkg9dioCeceddwDL4RzeRsKqT5l1d4pH2KrblJwMgltszH13y9c2V0nHa3SzdwDqcyB9qEN283c2cUt23W1f1hkY6RiNbUp5rUU5uORG9stN2KL1H+BlJPbK5qE9uxMgAxmcpU12aUd/HK0ZHXc+Vwc43WzddjsRxzjrdtiYaUavSYfqRCRbdslwuRh+IlFwhVcrdBVsF8ipVpyLZ3d8Jd34MHYtdtBl7nBW9FQN5XfLdsj4pXaLd23HfucTd/fWtvQLENOV7Hj4u0phY3fBijd2uoEFI25i6VeaLVDqVXdNx2J0XXdimEBbT3fzbWJ4ochK9HV2LAJA9+j4bXf/dtlXN3fE0792mVbBLCb5sOyU6xnmrxlhPPdzQCIp4F/g+PuN1hUkkC0GA5Yl8PZw9+nL4SX85UCBnSVDFfcZLJUuBzEkyPcbJD3gi2Co94j3mFdo9oj2GPdhAPAtk8bBzUj2kCzHXdbNePeY9zy3+PaY99j2t6jqleH7hPbQLCj2XQcrBQT3kH0o9u/M+PfhJMT2gfgk9wj3WyWQIhk8MPbU96Cy8CwI93T2MyVHjZCQPeYp+7Ai8Pbj4IU8tIAM9n8jfOWs92sl8CK092skFCnD5jn6ufq9DVpaHyOSwwPAQ5KgGMjLc+G89qvgjslhcEhT/PcYZ65K5qBC9s+Ll5LU8AS9CGH9SZeStEJIUgHxv6fjMzRSFnFGwJOTD/BIUmCJosmXkrL2UlNyS5eTY8JYhUGKEvY3CEhS8qjtzC8rpegq90qLKK1xSCL3MSUoS+IrJW1hcQNKZAX7l8bLyivJJKL3W8189kL26vfSlqnwCaPsUAL21RHHTSL3HovPp5ijySWviheXEvcxJd2kNYncZ3LYKMQm+5RnVvfS9uhW9EOnylElBva7zbKq9vaqijb2bPEDS5r3sWc9VJr39vamPLSqrveO9iJmj8PJJa72gUJC9qGKkWf2Kxb2NEoEZ5vC1vZliUKW5vGxt4xyJxOSF9U0+6t1okH2ycoqdcH2N/vgKRYamBZi7YNyZ6qBGdgWzcjB9qhFDPnAZJH3F0L4F0Dy0fYkFnH2sTKdjM+YRBbecvH20bv8FmdyYuriFwDYKOQEm4IX+CWxVlQWBvoXJPH3nBb3xVn3k1lWcxn39BdgJNUZcRnMFyn3/bnRGAX3Ufc7sLNX6BZBIiMMJNqn2CAk1hvMpadasOyZ2OdaIfa8FXBWG1rzIaxyNsD8Fuja/ciF1bylwhb4pS9Q91oN9yH3AuSiF/wX4CkU3OIWNfZbbO0ckheiyGfIsff3V5HaiffPV4wWm5idjLWH31uEJV32gRh7wR00OfZ3WCQkjfaA2iX3Yfah9sDbA8AIJJ326hZTWtvhHYa4w6b74/aQ2gn3nKUD9toXVSJj93oX9GX8WmylRhcN99W4RhcOF0X200DPXSYW60rom+EJZhYEVb2Z+Qk3xQP3bhdrdBv3a1sV93FTCb0421Ao+fZ2F8v3ToBAcA4We/bh9k4XRNuLyKX27BcuF54i5fZuFwSR23aV9twXYRZbbXP3RMUhF0X2diQ+FxL6k8j19tylARbT9pT1jwO39032aZf5CcvnqyQT9mZ7S1s99srF5/Zncp33HNokJG/3kRbQJO33aMeYANXXoPvDoTXcTLT82nbZsWI5FrWDCRZstYkXwtrxY/EXyRfpYgAPdYNn9cAOyRe49iakyFWapLLa+4y5Y6APwlNgDpAP0HzvlEq0QA8OpCrboEYEVWBGXTrq2iUWmtq9OrKwvHJsnCK1XqQVFpR1PhBUdGzHVRag8dUWeDAdlBmJHtqG2+C09YXj1xbbO+ZYDr0Ws+Zs2DgO4xcXVlaEBA4W2ndoDYRVu/8X9tsfJGDNpduak5b7WLjdFy7aCth4DpMWK1mQtRzVHFpJu6E0FA7e2xAWK3xkDvi7vtvkpCQO9toB2k+Y6+FM8OMWPwhMpFQPT9cpvK0ILA80Dsdb0TX4D6X8sxaR27mpHA9R2qPoOfA0Dy/XsdrzfC9xADfbF3wOgg97UTDDdMHUDkQPt7pK6S8log7nA6uVloEf1oA2ABd/jNcXPey8+lfp0LsM0KTbEShcRnIOevpMD196LJmYD4p1DA6ANtbb5FUzmpe7q5VsDgekr+bqDgCXDCiqDt0Xuw1vJAwPjtop26E0ig5gl9/n9bqX1rnbbyUYsGtqmg/EDw7IQFvNgcfbWYUAUcCWag+W+mYOWdoqD9C00SgmDjIPNyWGD7PXPe1yD/oPpVaHpoXD9MR0J1ytTroODvCmKUJjWIGi0+CMJ4mTLTlRo/IwLCcdkq661qBX4Oz14aSAyxwmYbmA2QClevReDoO6vg68Jh4Pzg7zMd4OsSmhuwUNdLD6BaLJy7pF6CImIQ9Ru8HBZOjiJ1ioKbshrREmfg6hpIFRuKbOD8O7QXDkpk+IB7vrJYUmHK30evqKPicjEJm6lXSosQEnAcgOegkOJSfv8S5JoXqe2tlAWia0xQW7LSyrJkqAeifFuw4PRZKCe+wGFyeP8GFxpnv8FfUmNy1Vu+EPRpFBJ/aQxnolD+0mhVmQe+EPhiHxBgOFenv5D3YnKUiLu5npTg7Ha7EPVcChJsSxw7pESQEmOyibWL27JQ7SuEEOKaQRDqkmdQ7iewiJKQ7cJg0P8aXj4VEPBQ4I2LHajQ6qJ20Pw1mtDyUn6XBRgVO69Q90Jp0OJ1lI6IEEAQ9zul0OxKZNDz965AwFDlUOEbvbuuUP5OBruj+6ICpdJoUPT7tY6FSn52rbugXA5Q8+sbu7GEn1JpEOB7skhV0PLQ8jDuaB2ScrDhnbDcA0pqqgKDYQqqSnCw/w1y4OCidzD397UOiuD04Ql6Wl/bIneQ+n+lMrtKakwLulzhLIpyaFxQ5bWDdJtScfDAR7iw5Ap0ugAHqTDsMm42yCe7XQsKYewFO6Cwi0SdUPRw+mexDU5Q7nDq+7D2hUpjJIrBd2wEcmViYqR7DWkBg9J8dkhntPDqknMIARuw8PVw5jDvx7YXHjDrEPSHovaB8mfw8/WPksOQ41DnB7k5ozJhMPy7sEGKSmGVgVDssJmQ6pJlMP2HuHDgonzw9feoCOuiePDqoXoOn/D/cODNd3D0YnMw6keuUOLiCCep8O5SZ6cJR7Lw/vD+lCebqojgcmrde0e7MP+SbzITv78w4eJ0sOmw7jDuMHaw8Ajv8OjgRDDnh7MQ+LgAe6wI+0p1sPrNfgjskmaEwkjqSn72sZD0SOCiYJSsW7NNAlLYCOSI6HD7COiKdwj8J6gw6OD0GkihjQpvSPaaXsXCsOAI+PVGcOkSe9DmZKlQ4KJ0NtFuX6o9MPrw5S/ZDU7g5YpyeT40mXJbVw1nr6rSEPKnqeDtxBTfG4ITp7vuhUpqyP3hhwsfomIw4ae4wg4yd0JoKPm1n06dkmII78j9COVic2xgEX2Q66J6UPtbpLVPDR1SaXDrukO1hGuNEPoo9SjoyOVnoYDbyOeI/QRLyOkKaijxyCLI8rpakPCoP7DlkOzI5JGSSPyo8x1piOSo5tvEKObQ6dDh57kI96jgnXdI/qjkilJQ40pgSOLKUmj4MP4aWBezqPqo4WjyynBo4tGJiOqSbkjo+9HDkcpyUmGQ4ReyNLwqcv8O79UXtpD/5Ijo9K5HrdCiH8p8qP8XuCpm6PPRhQaQ6Pxo/ZrK6OYqaijxF3+Po5yU0EgdSGphywooAGp8FBSqb4VoT2OXu+jwNYaqYcseGWBfx0DRqmyqZY90GOAY8k2WDmQtC7wqqmkY7d1gtFiqfRj+D6oY46kE5ogY4kV+GP9LMRj36OUdiemLGPYY8hdKPWVCfCgVPEYrkPaXN6MhEWp2amjjjjepmO1qaJ/Bd7X4CbpDsGEVF7p+KUT8PbpuxR/XqzjZ2ISaYSDON7XZCuplmPd3qlj779/qFljylIXqYVjl1731pTpGWOi3t0FDwEVY5nekEyPAn2uXd7fwnyEE84mPkegziE26f5wUz8elAfuy2nvlPFpudZp6R9pjbxRaUdjw6mqUgiI2tZeNjrp0xJf8p3WePCSaemZMmna7sNpSun2pELy3TUexDSuBmPdY4noVOmJY8m+57BM6Y1juN6U2Bpp5OPf3uucQuncbnDj3/NjY4plaunhdv9j72O+3oeoL2O3Y+xp4Xay45QeGWmHqCLjy2OvC2veknd7PxgGCGnJg+LpNK4dY67D5CoA6bX6lOO2MCTjk2PW48PuuWmFvUbjgRlY6erj62nF3slpp2OcHpQIleldkrwSQzRrmhOdAQqK46Xu7uOGQeSBwva24+9pj4GW6cmD1vD26fdjvx6CUqdpxeOqhYgkDz84/EHp2zGgfeGhDKC0pfyozg2ymDSlg9wWDdUgim26dYifToMBDerSj+OA6gZt1Y30bieSVp3JLYOSdFzv3LQtiBOlDZzcaQ2eoP5t4BPAo+0NnzYjDZ+SEYIxJaXcxYp64VMNs8TgBnnCVe2VTe3SOw3n465xeixnarwTgZ9CZFPt2M36UjRqH2qSqNWfRo8GE+/j0I3FZC/j9pDmny91DE3jNnQ7HVIIUFad7GnNmVfqfCWJaK4t0K32ZfIlHI2FEGec59Lh3qKN33hB7bKNmFIlnNgd6umrbkqSX43jnbQT+2487CEar7YWjfpSV+O88vfj3o3A8tTtvBtejfoTzO2QHMz8YqHcE6ITxRPAHcsTkhlJLGmN0hOZPG4FT+2PTf745hObE8ot+xP67biN5Utx9GFl0xO/cQQTrB2Ak4Yc7xOnnG6ZAhzIHd/M642nE9gdkU3j0myORuWpE634rhadncjNq3EUk8bcgs3RXS0TyhOZgYCKaJ3ok6FCb5qPE/xN8xPbHZtjW45yE4hd0J84zeoTy+2jSKRN9hP2k82N1m4hj04duk3ak+E8nm2ApE9NqpPGne2fHk2OxO8T+RO/vGKT3+2fE/8OQQR67YGTxZOAnIUd5k2QBMkT5NiMBiZbeu2Zk+Dxd4IdnY5cN/i4oJUdi59Y8R2OIU2CJOqNg5O1k9bSnROQ1FUT1tLDE82TxJPJLYX2dYoAnYCTgo8BmoMTtoZsuTCTqhzfmUECzh31E4cGEFOiGrTdW2SHIbqTnm3jk6K8H5PWnf2Tj5Pp5ayT0ZPe1ESTkZP8TaWT5xOI1l9NnJPEHZrNzZlLk7OTzhPvBhJTjJrGE86Tw5P93N62As3dk9nt41XbjgxT4x2Rza8pMx22U+lKxBOGk5hToZPCk5CGCFPYHbyThyGmk9+dyI3eU8BTolO5obFKwROuLZRT0R3tk7bN5FBhZZqThyHnkiO1mpPKvAMCwhOAk+1TvvLwk67NiFH5k9GfIgY4vaOT6FPy/wzcmd0C0QXNlNJKyPOar7YHk55YK1Pnk7aGTRIdnfeT5ObRE4NTnZjtBAVThU2TzbGT61OLzcYyAROok7BT0NO7DbTdZRO+Mibc61OsU433d/chPIcNmESRneAT//p7U7Uyz1OKoOmdgJPpuMsN4vZeDdUGHKxOHfeT6i6KE/TTkaD4mtVTqSo7k7gT75i1ke7qmtPGLElT95OSgwIthyiGGRxT59K0Laq8XNyIXfeT2ULS09otoGMbrGk48VORWVNIadKvyMwV67ImsFgdlZPvsgWKQF30yO+qJlZDEyQyyS2505EtztOYWT3myFOXE+9tX2Vuk+sNj6OTLagETnglLZCXVU3HuHUt0l3IWMUrHokr0+ABjwJSuECt0zjH08a0O9OEiD6SW9PzLZI5p9xf07fT3y3G7FfTynh307skr/SgM9q4b9OG1GhiYDPsXcj1/raBW2FuKIkIrZqNtG1823Qz3I2LdjtbDq3Y7gH1hxlwqhragLjxnOIzxtqLGl2tBsiOrbVSI3Z/6RozjBo6M854Zq2HBjIuIMiWM5H58EBnzRAJx63Jy2fNd/5irZe9UU0BM94zmLQXXYAJdDqlcUJit1tL7VzLNXY63YoWeLItAd2tLttabXyTvK2y3eyV+a30gdzdx1NJMknEHIlWOmrmsvmmHl8JP60e+fTtMt3sM92tsXZeSPQzr3EB7XHbC63XrZqEdt2eM+qtsedRTXczhwZPM9TdkTPeMkhiq9sPrfSTsoPVstp0Ma3qRHnbJZ5gbYfofKxZspYzhyGTugxtyQkGM93vBUjvM9Q9uA9RIMjZcYaqlolVIgG3QdNK85aA2XWyNu58s68uldwEAfsXHLOx12KzmrO5PejUarOCs7KziAEnmy49j6i+xRj5mlEhmmtaD/oZKQmW/EQWYDFoiF4X0mnjPRlZWWIUIFa+VrGoT45UQdOtKLB4wVmzgbPs1haobdPyVtcHLSpJmUVB061UtL6zgNwLVp6zg8K/mVKeftIWBtCqD7xpcFjLCvC4WTFo/h5i04Wz+oDs5RchsbOxqA+8EbPhBnw0yDALs606U612dPKkmyATVu0NcbPjs9k6CCNXOxsB3iQ0Vp4MCCa/mUpCPzwgc5mz4sjLlpj0sKYRE/WzwhkcMEmZBEGdVrzpNlxmyOwtvLtvXDRzh1ajcxuz/ZlBejqGVYhzs6tI/QGrC2pzryCTltJzlqgQc/+qol4AfDFo3FU2Vot+f8agWKuzmwZMc++zg5aUX0a8ZfUjiM0hhHOsxqezj78pKnBzqWjSHne8BmITvBsBkYIAoYlz5fVL5QVzlHPl9TdRYtPPs/yqfrPiVu5z/XO0lHxWjzxp4hFZaEHKc9tZAPUSSfVWsBJ6c5Vz5IBKc7+7G3OrUgNW3pprc+Gz0FxlVrNzr8aWzjmoH3O9PONzx9AUYEB95lcyBdHtLXMGnnYyA5KnSt7BaPOeUrzIEwrlhgJuX7KNrRIK9/wVEvSzOPPWSVGcZrBo0pzzi4kSvBBcEbNC86BwFXgAw9jz5Odi0Arz3TKy88emKghkcpGTKvNRjDzQdtLm85EK8jYwgX+Sxti/oj3c4VIQUuzz6vPf0C7IRBhS8+HzgZoXXFEU3uB4KyhihlK+BYCrGjXuCArSxfpmwRSWFlx8UsJSIsF189DSswxsqyXzzFK3Pg9zaPMMFs6zSfhRdsnz6bLmsFsraGxwUG9SvmleZK6gNQnvUuc/FcDVNfxJ8VLOyGdkpWLB86KaOI9+84taJVKO87Yhd/P1UpWSi783QSfuEWJdUvTzyijuiZjzlZKy85I1npxJkogLpysd86PcofOlCoHzpVKLvGwLwAuIsrLzkQaN87qzVQ8h5LsYANKq85ErWugSC5cU8EYOwQvuEWYC8+Hz7NWUC6oLxori87B88AvQj1ClxKoM0opXKqin89Ey9GRHsgjZnAv787ILsCyJpZXzxgTz6drYEDLtpgTUURnxC7rSmfOI2cNSMAvI88aK0fPz0tgLqenyEjEsafO+889FTdYzUsULgKt/cVPz64kykHSo8ONl87nS+gvgmboSw/Pr8+4hSwvfBAkLvzYTC5tml/OLPGmZ88Bwbq5EPwveC4oLzwup6fNWD/OpMsYw8IuVC7oL8487GfkLsxTp1q8LrR9oC98L4tUpwViLmX3dKyB+aQuoMuk7CsCFtZcqIxSa+gkovtXii41S2TChJcSL1AueC8yLwAvJkrLz1Ivn8/YL7CXr4qe5bguZK1kmf1oyMuAL2KrTC55SsF8yi8SCDwv8i9EL2EV/Unnz3GIci730NgvliVfz/orsm2myu78Ui7EeVDAwi8whAVRhC6e4WytBzpFmM/PjjxHBGou50v/QN9mii8gy4YkbC+bBcouLi/MLgpn6+DyLp2M1C/qL/YvqySaLszAWi6wL+PNrSy8CKzLO4kWLnovRFPLIe4vYjDmL7dafK0g90YuXFNOL+Bm58+LSnNg55NhFAYvOs2iLgEup89IL1Yv2i5jur4vewRMosEu9C8fBKyKe84JLzYq+C5G9kkvGdTJL3rKAMKOJG1XIi/MUgouiqoeLjChP84VcQkuXsH+SgQualb6SPmXai8ZK254OS8aL6vPdtWOLxAvhS68ohAvzIh4Lxohfi96yqovVOYMLwIvBZrxh/wT0S82JL/Oy0TllNUvki4RKxUuj0pJL/U4DpfHznsJwziWL/ZKcS+856ooW5taLy0veS/bJCE0D2SpLm0u5yDhL40vr0RGLkIBCC+FLivhHi6Yib0vmS/T1i0vliFBL+NKDS/5WfEu8C+yKB6VjoudLrqYB8+hioMv9fkmL3AvC86TLjBa3UrzUOEpC/E/0TxSYS7qKAqLTwDdS1wubClvzzL6oi+U8SWGJtAcSt4vhS4/uNLrEy9LLinK/S5NLxsv8FINLusuBZxAAV/33xnhuZ3h5B2dJXsvveDvE9nLgqT7L5osBy85vIcubBgFy5VLCqGPEdAtcjHmpL3g5y/HL0YCly77Lu1OJy7zsb3hNy7XLmiMxy7ILWvh9y53L2+kgrYsVhT9nXFUjJ8rifXpKy8v+yrbxQiqhyXeCG8qHy9Iq8vI0CAfpx5xySvfLyyoWvaZMVcro8mfL9itkCRUKu8uXy6WpGQr3dSvL38r1nGdyqCv+yomzNwLAK+gr3soY6Q9jp8uUK8zzVyqTySAr+r2yVJAFKkj65N6QuaAgCoz2gqsa+hVKXrx0Kn+Z7NIFCqS1UWQxmcNUgb1R8iY6CEFW8yr9NvKIoEckKenaK+7yspJPZB4riivdeSBjDhkyvZIr5CuEK42tfsGJK+wqspA2vZPJMpgT2Z65/yqhyTRqCWW0K6Ty3Cv/ve/L+CvyKqh5zAqsEVpIaKizyBDeoclFK56ZoSugCsDy5yrPRQFUj9MUJQFqcKi7K8jKePxA8vCoyyuZK/7Z9iizKrArnpm7K9f5LSvjxBMr+yvoRsEq3IkUGhcrj8uUGffog0p7SgYryCEi/XO5V5JPsBql38ikq+zqwmRMIWaolyvCZF8q1NjxK5/L3iqgq70qliuzSHuLz1WX8odNYclwoQ8rl0ppFCPpnQqjKuBAHpJ4GcoYwvKE8kCrnnpHy98ryCE0q5n5GnB6SWakyaz+q4FqesqNJe5cMPO3VqPNQPKR7I7WJNZpq50J6edHPweFAsQV7tGbehLUel7UJ66IRiq5ZNRHxqQ2PT91auBCbO6dq965OJBvg/m5Q6u2YXoT927lq+x6Y6vcXquriudwIlZuhb106UmMfcMSuK8LPc7MigFSZYmH1nB/ZA13gmHu1rAquSXwZMnLq78/csJd7v1iQGv+dGFJuQjF7rM2J5IGbricJm7ka6uJ3/j2bts2VauubpxEYn9bNm0EFx6ThsO5cGvhbumJQZsy8me3RavwCGM/I+0oyYJdfz1deR65yYn+3Ee/JvIQDLmJhgtGKd+r0kI9bsmUVuk9C0EEE26hkgZ/emuFyennez0qa7hVXFclq7Br+h5OHtBrpr9aWnnSd26pa94Kvmufbvu9IL8CHn+r06ub1k65FGvQ7rurgZVUQ8Zr90OSvyNr26u/Pz+rjW7pQ2/umYoRgnTu7Wuxv0zgSG65a7C/b9BcbpuqKL8BgglriQoGfwiATWuYHpfeeb9VQl0elBlMvyBG0knZ+PRroOuua6oXfEEximlwTJ7Ya9R/Ffcza7mrsL9XsHHuyGuwv0tKae7SwNR/HEAia59uk8Qk66sESSAJSdjrm9kI2Wrr+2vcv3SMaGuXHuHYaW7MqSdrp+6ma7y/HOvz7oiUcUOZuWBr1J7pBBAewtVha+Puruvk6+Drgl0bvTG/cOufbpJr0PCVeXosP+66HEy/EhK9a9oEEeu/5pjrlgFuHqsEUTAEHo1zUOv8fwPr4tJUYkFr7eu8ntFrhukVNSnrn2uWfzHYBmv9a5h/d5o2no9rjb8ekj4ezTxDv2XPRWu3q7Mq7c9WHoFrhUOjv1LrkOuUvysEAuv07vk9eL8aBghrvuut69fr4R7V6/lpJeuGa8jr1Bv167trt/BjP0vr+evKa5PrtGpVHrq8AmutQivDmuuaf3vPCOuFJIrrrBuy69q/fH8oZAlrrOvIeWdd5BuXa/x/EbZya7Trp7lIG47rxGuK68Ablx74Eg/TIRvIXve/WBuFa65uyLx16Ugbz+v4B1brgrljeSY6ZBusvT+Jl6koG4OrqrkVTyKelhvzRj7TQeutG965XYkza+frnb8U65Frpj0pvwqAq+vnYhru8YQqqmqe98SPI+j5fcNynuvr96uxAKcb7+uy8gUJHeula/i5O7pFq7Mbn3IVG/cbnxuh0x7rntIA65vr/zJ4G+Abm784m/Jr+kEea6tyZ5JJnpQbxu7EShHQOZ69G6HTLhuAnoCb/RvZAiEpvOv4uRKbtZ7369/TL2uQa/Wrgivm67uejhv++TAbspv9G6zQGOu8m+1Kf8LGm6urq7wlSdabyMpNG6qboQVba8+e5avxyT5r52vDq945FpvOm5mb2Umqm5zwuevxG7npJ2NhyQWSAkkqkjfSmavkXsUb2L2vWRwiJ+6Z68DS3Ip/KYGbn4kdm6MbpUuT9HCp4ZvMSVObil6im7PT+nKVeTp5VnQQhAhj/yASMileyOgCY5t1lj3Xm455A0lSY9GgK+QgW/ruP5vbLYBb75umXtGkkFuAvreb+uxKY8JjoT3jC3Bb9KBPm9Bb8X7+XoxbrKmoW9RbpuLYW9+b9qmajEJbtATMhCQ5yXKOs+CtpgCzNkS5dazZVFMrikTmY8xWVzAmW4M/W17CGA2pnEtpY6eWJTxYq7+kOF0GbOdZ4iVajDrEWkJWW/tesg1eW7PQjN7pW+jerlu5W/wHMWPE3rZb6GLOuUu5bN7GW4/TJ1m03sVb0yuJkyne/VudW51irKz8Fc3e5Ov9UUHeibNq3uTrt3Q63oFwJGmKSqSgQDY6K0O/EXkUaczzdePR6/hptijNKrG/VSJK3vMrYd68vy+is1u56farw1uC3qwwuVvdW5g2WVuF3qsET4aHW+1bvL9dLE9fSVvVY6sEJ5AjW5jb0yv9EjTjgQQ1W/x/EelkoH2WOOxnShe8JOP9ljiqpvIqxozb8bgX3smrhT9fcHsiWaa58lbb5IgMpuTK65pipv2mpUYm9VmUp05oZsT1Fh4SJqGmx4pD9EFreGbMig02TFSJJv0/Odvzsm7b2otdOXbbhEpGsAbc/ibM9T0PZSaQpo43RooXHnmNI3lUVkl5GSbsdjvO9dum8jGVQabzTAiKfAdTovWmur9RQnUmnR7W+StzASJ3ag+jB9u+27VqDLZgE0vZSybaYYOKy9u8zAkzHvA22/umtj8NxwngAGW2PyKeJ6bIZbY/Fx4vJpGxQ9u463+mmklGigQ7jACE/caKDcdkZpA5CDuu25nb4BM8ORXbsVuYjuHbr32B1TY5Cjuj2DPbiduGighVOGad7uqK95o+25Hbin9HNlY7rju2vyXbt6bgZoA5T4lL4vqm/RuGi1H5c9vXeTo7tqaXqSXbzqauTTtKCQYKor6mjXJlO8Gmrjudv182JGbZO7r4eTvlJrvbodM4tlcmpjuu2WLUK6bNO71yb9AzpsM7vXJIJjWmlSbdeR4KFTu32/2jIkJBpvkEAdu7um/yTg0++QsD0DvzpoTGTXJgLssm5OWjO5g7qDvsm+kFJyaj2S8A9zp3prPy/W6t8lQ7pkk9O5k7/mEsO7i7tmmvTQA5CKIMO/BmpzuEQnCmyzuLA4XZCjvnO9Gmzpk1amebgFuPszJm7pEyhSmgPGbkA4xF7IU8HRpmpIQ6u/zUn+85MdaFQ9061PezIPd6ZqVO+kWwc1JzVB9BZtKFZdtmVl36Sh0Wu5I/cbu2Zv2RRbvRZt/9jnMNrAdO50h8A90xwgOEEclF3qBpRbGEfruuH3WRAM6FXyDO6zH+RfoDuzHaW5xSU/lT5oB2JrxFeQ8Wrd9UzsCWiHbxYTe7zRbuYQs5KOaPu/ATcBazdv/FtmEYO+Tmr7aBegXZUubncuXbMi8Hu8Fq1K4jFrCWwfU8LWvmozRoe6JI/zCwe8MDzwsPKUl8cXace7AFb7uuthg7uHvHHnb5F7u9C0aitnx9HQ/TKfYfO4p7unuRbR3msrlLKnmw4xa1xdQKvDldFqrF4BNL25YW53LucHsvD2ba0vXVOeK4e6I2LQooe7LyclZpBSx75HkB1TXbhJh8e5TYEAJqe5oR1L8j29I1TyYTW8ckOToCEocRgEq54oPm4ZGjCsh78xbUuS74QHuLc0FSsVvuLpp9JkIGst574qLUlqgNuCo+e6UNMA3be9P5deaOe8t76jpVFpa5Aik8Fs0DzrkwqT+7kXuVe8wWx+aWCsO6eLCKe6ZGuPuge5BS8tVve+szbHu1jUB7tHvpe/xodMp3u4j7oCxh+rz7syqgvEl7/nuy8gnCsjo5e8kbvjkA5rkmZPv9y2cS8PvF68xOjRajuNYbzXvEFsHWVn9Ve/1760vjeS+7zQo9hvSMfw7qFqT7yRuYyFR7lOb8fxHaYnoy+/x/G9xH6KR70Hk7e7h7xctU+7SRsyqW+6nm4RH5+4R7vBbYkeH7jvvegneroHUe+497yDLu++vm4WMf69ya2fu3zZZ2vXlS+/waOA2VeRC783uT67t783u1O/04VXu4e8jzYqLme5epSilQ5uF7gBv0WRcFCnudAyz5RRbxdld5X7vElshSp4p3e+v79JaOG22mZpt5mjRXdAfITh88eH7ocH6bTFknLZped7Qxm1wH9j6mRUNgNaYiB/wHjAeBa7wHkgecB+oHhgfj4EwHqMGgQdjGuJAh0l2eD0IzcxF6R1JxJixWSfNJBeP2xEZfDSVcYQfM9pF6arZxB7JKPPaIHh4zGQeoihL2nl9+wanBKErvXHSdJbYZB/5qsQncjvgaR3Na5z3xvQekiJUl4KRWnE0H9kHh4hfaNlwVB6u40Ni8mHeceQfWDviEItRHB4PoaQeXB6vUNweHsDHdDIQHB6RWQQfAVms4E7obB9gjFUHPB+P2lZohrRkHkZrJB/vZVIdFbp4O9gV9B+0H54q/lniHiEU3y1AMwSY1OUHs827sh/YQz0JI2KmyHZwSxkqNbQfkis11TUowh3Ru+va9JkCHxQfjCqJzoiN5Qc4HwA6oh6tdY8Q0nfqZSIhXgiBEVwf6mQ7KIoeJB7cH3IeOrL4HuQeMh8UHvogg3GSHgahMs4CcMzCUY58lS6AUvIaz1xwlh9tdV/S/pGbceE8gxpZQHYe1h+gUJKVjRfh+ikFwpUs9pDxIp2bcSajLgfOHsKBbVhWHvSVHh/Y++4fH3R7Y3+QopXeH9YeKht+SK6BLh46pv58lXR+HvZo/h7ATTMljBu0hcEejPcesUEe4pSXyr5p4R/rJM4ex4geHiEfmmlRHo4fXh8xH04fjBvhHnHBVPt2vYQGilPuTew7jJUs9xKULh6KlcqVvh/gUkqU182c9mrBlAc5+1QH3PfrxmYaqnzIWbWhkErnasKlZqDei4aLuLv5H7mKS4rAncBNA/qMBLs7rrD6+owE3x0RGDwGjAV8eHRSPYpxppkiRezfsqaLZR7rmNTUzfslHvs7oXFy+0UfEzrnOEhJBR+HmDeCRR85HueYLR/L+nkbtR54SgoETju5H0qLyRqe79BYbR829EAchR8IlAUeeufpjaUekkgKBWZjJ8oVH1hSvSm1oeEE4YHJG0EIZSUIlOb2YSfDH8UfTYrv7YMefR5FH+Kt1EWaLdMeKzTfFpMfpScyuB0JGYSti2i6EEWAae2KuLtLHnjhjoohJzeE/6ni+nwEBofBwHkeSx9zOj0eUZj2D/YCtpUrV6t08bO2t1mrjKC8i8N0XrS5qtYlK9t/GuDt/kgHHomzw/kolnse8h3nkSWqpx+eh3g36khUee6GVx9Se10qlKgXHgOI5x8Fts61hbYbWMphJ81Gx8W2jx7dssqIOGqwmhOzFqAYavcfMpftCXce1x6UqZ1xo6uvHzuagoBHHh6UXRXDefuqqSUQOj8ew/G9oUcfELNkqd2rNXTQsoJX+Wslu6xAbRR3ZBOqo7ubszYZux6WeQOzKkGvq/txXIqzmoBqfrsSCIKXgMjEavrzI9sdzS8fCJ4iiKeygMw2ah4tjx8BWdCfG6oeLFvbvlmQn/seanlsHZDiRkiXHl8f8lZrQBieZLN8qK8fnx8kmxdtXSE4nm1xiPD/HwSeWrJWa2+7XIuQWoCf3G63HoSe/6r3uyi0FhxpazcfBx/V9XcfWJ/6l6SfeJ/Gl+phqUmonwhyn0jIniYRhTULIB5rMJ5DNSyfX6v/H9+znMkIn78fPLO6SPOr3x8c9PSfJJ7NEahri1k0ngu0oZPcnhYdoJ+LWECLnh1wyBfB7J5pHYceIp4CqYBzY/lvY/txmmA9adieh66wn7yfX7c1u2izDIfklzKeoMU5uKieOZWWl4SeS4lQn3EcErbsn2KfwHYQ0eifCp+1l5Sf4nmEd/w2u4A1zCyLaZeSaxB6EopZRlcf8Hopcdh2mp9Se2lsJ0YInkSfkom+HaqejJ50nr2GwKlMa0SenYcfH/B6uyDGnlKe7bsGn8VXk2xBScif2HfWnkqfzJ+k6GtW7Gpanv0zU5wQnhqf4Hemn3pBrJ/1l8af3G/2wK6fip9vupKfaZZ2aiR7wHJveNTWIJ7UdtMDlGsinyUdyp+an5ye7vWUn/JKQ5eun3yfnjW+GmaevJ+Onu2rAp/2ngKeAZ4T84Kefp5Bn7aeRbvcSQ93lp8QnpUdoZ+0n1fw5HfOnu57bp+3RzGevJ/tSG5r7x8idzyezMFidvSfJp4ks1yeVUmxsos1XQLsntfFhTTJn8bWiJ4VcZt4BDtBekAhCnZmalafGJ/uPKye6Z7qnFCfqZ85cQ7gZp9GniGao21JSYyeeLIlmXGfep/Ystm6YZ7hlbp35Z+gbtKf+pwVnryeBlQQnwSfD8V5nlu7NJ+jzcdg7nsUnth465ORui9xELJa8JGexZ/I2N8fjZ8U8Z6f7x/RTD2fJp6FREmfJZ9/xdSe7butnsWIWWrBn5aVQ59EnmBWkZ68ntR6Ep59nwUAmp8lunDBZRyrMHnWPp+2Ky9FNWsSnmBz1kG9uG6ekp8DTJxlkXuDn5ifJbpLnxtQNp/9nmhX9WqDnryKau88t3Pz8MArXa0QSmEksMiRAuSMt3qm9Rzbn1jAKzCIHmyym55NMDS2qW9NKxufJRA7n6gfumHbnvUx70/TFKef/BBnnwl3VZQBTTufNLbKXHnbp55bniMQ2qEHn/IBV55Hn6mPVqpYbXCyhtRnm6WIKbNPnhebz5/ms4wW4lan/Jnwh7N/LlqzOJsfnxtr2QnsWkWzikfxJh+fAzK/nrOG8VnZwTha1CZJsniwry+1hjdrP584WnWGAF6vL2NoOYZgXmZHJW02lXkle6f7iJZHE3o4uhL0DLPxoaivKqniRn5Z1RCuV5hlOByoLBxG/WmwX65x65rQX+8zZ3oErwKyoxCircCIwfQrRyBf0FogX3+f8Ufo+Ghfb58WVnBfdpVAXxBfnYanM8zsmVerefhf0gAYr6Zw7I59e9u6Uq5+cCuaa27kXohzifAIXyReOxHQX1+eLFv8kbBe+iDIX7RepLL0ESX5d3e4X7NoH3Yvw/MzgieYX4SOgcg4XzZXpF4Zs/zheF5BccRfLF9ucMSzE43qr5tucovEOmfIOfdVxGdlffY5q4I7RfYMSJQ60SMR9iP3qsWUO4NyyfYaG3TkK/ekTcqpcfciXzQKkl8J9+/2S8HiXz/I6JpdwIPJBfcpkFo6+8Vp92uVajtF91dJMRsmOqApWfeHq587sl56O546a/bcOvyxW8i7939qqO9OpPv3hInCOj33B/ZDq5pfJfYsdFI6Me4L9pb8MjsBOnf3PMHIaaQ7fF8L93hNjfU19vLqSjusO8P2ilFt8UpfDY03l5XA7KQA4ho7ll8h9gpevhvmX232SVXsNTo7HfciX8QFejsHyG/3ojsycp/2h6tGO/Rkbl9vCAP2Ll7tHnPIQ/YWO/pfw/dL9rJNVjsCXtJNjDs7975TW5kF48Zyqff2O4w6d/d+X4KK0l+cpGP3jjs0JRf3VFnuOkZe1ffmahpfql9RXyH2YV42UuFeyl+9mGn0EO6jws+YtQUIuupfgInGXglfI5iuX4Ff8GwjlTFehfadlAU7ToFCX8uZETuBXihY5fFRO1v3Rl6ZqLfvRfcmXtinCztOgb24DIvGbBn3Fl5JO3x5ToFWXwfxaTp39hFQ3agVXg/2c/R2MdIkrfdbmVk7+CXuX4VebGRuXvmho/beXpUoICV1X+uf0XzADn/2kPAlOz/35u7AA9+UUhLCWS1e+RZIDs061TppYx1eNEAdXyLa6A7Bzc064A5P9I06RmDQDlUW/V9wnANe7/ThYyK1bTp/9AZZcA4FFUVw5Zvd7cUW9u+IDozHSA9XUuRUdWKoDlvdLu9dX67udaDBvGM74LUaD4tfy5XiDhLDUzpepVzPi2oTOzvnog80Co/ZhA/QGeM6pnWbX9fYVLrjGaQOyg+8BUs7TNh0D+UK38BpNOoOJGj376tfHFs7q+JeWg5bOidUkBY6DvpfZnBb5noPezqXXltfMdqY/Qs6/A5rO0c6HA4rX6kQMdyWjGnveR88Ditelzul8Ldf117XOwj5xhCTBXDq8ZFCD8iQN5s0u2CkK1/fO8te11/Dp5869O5sWghqYvAdlFYOKLrw6zdeFg4vO1rBKzRA3ghrUyCiD8YPAN/LWIYPP9gMu95Y+g/wlBxHVLrQF5de4N9gpedfdLoNhAdegLsrNEdfYoZsDtUV4OrfXmzY8N6fOnr7514WH11kLgH0VLxiC1CqgejeQR4TZOjfDZyCk4NQ2N9QiFjeyci436CyOZCY39jfCs/ktwTfQogE3+ar93QQB0TfIeA5kSKwBQBk32/65N9sVbutm6FE3pZAEAaU3yTe8s6KVdTfFN76vbjfZN4I/Aze9N5+4Yzfm6GhwnDaNN/03/jftN/k3jjfdqBM9kQGEuKi6fRVclX48BuAxN5KVDBgtN8K4Fzf2N9Z+pkf2fsj5tQGfhRUVH+kNy0ADGqIQkLcGUuZIt+siUSJ3PEP4ylxuN8S31UIksl+hWbYKmVyKc7J4MethQNktxTiiopoKwkDZfQgWMGXuBwYcSdP4QCIFCJWB0rf9/OlwhrIsViUyRRCcQhANTqA2omYYXMIQDSYkZLeEMuqyHreot9EiTRkjiLK3hCzFQgqZNLfCZ0TwmLfit1XEBCI+vHe8WLe5t5SnBLeJt4tQKbe7tSSIipk6t+giDYsjI2diaCITC0GBo/ZDt+K3jf9Rt6AZTZkIt+W3oEx+t7i38SJ0Aho39GZxuXJ1OPGzrhe3rPH2s9NKolwrMJKebPGUAQFsz7eeN5IBQHeC8dLx6mYPt7B32vH9h/WuUHe/t/jxuHe3t7YH0LfgQYx8NZx4KUz2rfG18aLYIpR28YKISmF0d8mVKA7WCbkIIneL9pJ36y8e8buONnztD3msKfHE4z0ZWFVOJDNSffGICe0PX8VWnCx30a5549GkFfGW8fz2jShW9posxfHVLx4OhnfT8Zx35gmKykvx/PawpfbxofHb8dJ37An70lPxpXeX8abkYfHRd67gKgnBfGmVYuB5CY13klkbFiXSE49HOyuyY3fsh4wJ/p19d9b2lAnNvPz2saXpCeQJCXfYijEJhQmFlQ2wi5VZj1gJijEdiQQJxne1nCTQJ3eIskimFSEyd6t36ZUPSGwJzeBrEEj3oPf6CetzyPe41g4JhgnhDo7Hk1izNh4kPLDf+bLSWzYJSxtPRtjX4ii5JZM5xRGVQ6EvOzRexkJBnFyESSQpjsL3uHoea0kTMnvAnL0LfIwtsL3Mav49C3HAwnE/R+xVLvfVE2e3QFVW99KTdmsXuiO8ZA0yYgCFxuMPQlJ6WXQM3m4MZZhRNWaOCvf/GjL3lOwlk1X3zX4895ETPQ9DXMz34TsQ4tzIc2JgE1GkZkJK97L35Wsm95nCIvftdBH3nPfgNRYhAfemMBGcyNVcsg5xMCErnNf3tvfrE0H34TJOe64TLkRwPJP3+feJjiU8sVuN0mut0A+tlTKFZcCe9+y8IA/RtElxX/f+empFXN5j7zxCF9VUD88TRrAX9/TVU8C4D48wXPfzhJL36/e4enUUCvfS9633lSEQD6NG+IJW1Sh6Ws8oD+gCeg/KOvP3pOQsNWL0FJNkD7/Vbveet2xkGFUBeQAP8/1oD/D4cJMmD4OcGEwID73PQA+BD/PaIxMHGkJcnjU2wJ63Nka6D7q49wp2axpwaA/1D6opNg+1D/DBDQ/uD/3rh9U4D/4PxFwVNV4PzQ+T8YkP8to/PisPsA/7FzEP+A+BD7ajVHEFD9D+Y3ktbuOTSg+6D65iNA/4BaX+RzUvD7gPuMgmnL07huISLc336verMjkRhfeq9/56E6MS8V33qZUahQYPhPEvGjNczXJLD6Kaa1zNcm/30w+Isks8PI+799i6B/4sj6f3xhwCVVSP1g/799J6RI/vD9IPuo+/5m+tnw+Ej4FiLEY9D7aPmTJPhhejkdAmj4JIMhYXo9n6fo+DwP2THA+qj+FDbq2QDLzcpaNGwITxGQ/zD5YBWLHR94jmT3xD1+naw/fMj7WaXHGF96wIUTUzylQ6uI/6lRR6R7on99UPto+NuBmt1o+Tj/aPsUZOj9J6XLpDj6iP/noLJB2P6ffJei/IZY+l8DScpo/Lj8LPZo40aXTCYEAID4aP84/Sejho85N7D/0IG4/UklndqE/mD4hPww/aD4J6RF5LDKOPzX5AylGPwnFnj46cFyks9+xxZI/w/BcpdJBYjoyPpf5EY0OPnI/VlVH4Bdq+YMKP3E/kGlpP6Y+H/gpPjo/xj4b8Yk+ZWUuj4Y+8T52P+veGT7NjK0Z7j9MpItU4D7BP5WAQT4IPvo+4KS/67k/SVSfyCB6SLfZPiQ+DKRVCuA/lkDKP1U+MbbpPoA/QwlYGue9Vj9tCGU+rnk1io/e4ejZouE/CT+A1VE+ZreePhpxl+D5P4Q/oAgdPno/rj+AKA269zyASV+JHeDk4Gn2Raz4J20JP8lNA/4+REDzpfgBzV9AUWtkFDAoafTUPYgi1aJpgd7TgKM/4z7cGlagveV2H1M+c8aKQdM+1h6i1D3AdNQrnL7fLexV5BTUYz+MQZM/rPL6ERM/F0BLPgs/sOP01fM/Kz5GAwEH9rptVHWJq85JGIDh+en1iDs+OOh18rQQMKBMRZaBIvVJ6Hs/7fO6QLfqmj7Rqcc+kECNcFHpBKb18uWJyElHPp07Dzt3xy8FxhGnPw87F9F+/Tc++CGeCMkdZnBXPzwmFxefHO9UX6ArL34Zkbn6PsSwVowCOI8/D15uZNM68f0fPyDU5CY3PjKDYNW4J5c/5FVtlvoI+oz3iFc+1kE4kgC/UIRvX3wQHQiGjIJh5z4ogvXylOE5QFc+tz7GCGoZqrs3PkUXkL68OXc+Fz/1CLccEAnGEE8/OfLNmYDV1hVkL+UJ+CBXPwxAj1XSejAaKL4gvj+ZyhhfP5oMqzN9Ca8+gj7Qsni6uvWIviFH6fOm4mnzfz8vPneEUepvP4IvpLt9y18+dzrPP/tUsOifP49Uy+uEv2DVSYki9FHppL6m8hBgVcH6PxBgswjkPrshlL9XPjC+ZMj7x/C+QXA4WZIYCrr3PvvO4I/J8tC+Oz5e8Pi+xz5Y1FmIdL+svpryzY2u85y+WNVwv51J3L841P+YycCnP9C++NQXmSXoW043FLhQ1CyaPnpJWXV2wBz0Bz7ZLv2kiv32BqhsqOfFVISFeGwCIFgfNVGrP5ihcOazFVK+zzgeW3K/ZdSzPzRUzbZSvoq+NmByvgvG8r9159a5Sr4yv6q/b5A2uAN4iXCKvuvH2B4EIuZRpcBT2ygBBlqtOBeQpd71rAnfOr6p3rYYSWT0pEa+rhjGvh8kqd4r/Q/4D4lyKFPa7fy4uLSkb9tWdeFarTjn0znfN0F6v4s5kUQXwfpxRZFGuGWbtqDoOiArF8beeTqB28aWv+HJuEUZJK6+m9jmvkNcBr9Gv51JdtTeClPadf2bOaa/Md6YwBQjwSoWvsI8elAn2la+Wd//oJZarTmRgbvaMRUmv0HJjr73xnvAjsismQ1F4KW9cBG/GCfDOWtgo9ulbKa/TdPl3l0hy9uGvn6/RKmBvlQMqd5FF57Vcb/iPGrIvr9guQA7Z3t1WpM4VeGwOoBJ1r7NMdtIxCZZv86+hQEuv+I9OYGWvkRATr6pvvaQxJi/gOTk6DvJv1053weyHkJoMUL6vxgVmDvxv2G/ub7F38Vspr4Y4Dm/lLF1CJ7elyn25eE4Ucw49jGSuPpo9yBu8AZFyoOiHoAk9lTVTb/1vtRsLb/Y+0HkzaOSU/evyDSQ+6oUtQj1vicpdb/pOSlu3/c0Ed2+mDTQ+9A0AZMtvoa8vWJtvx2+Q7//1a7Ja+CxPaO/7b6DvgO+Y76jvhnZ479jv/NAk77RPO2+ar9FMTO/DedJb//UemUJHjAjiR5AUmPj2SuraMO+GDT6vSu/ohD6vCpksDTAI+u/GR4OIZke3PZl7Dz2VCc65D5ajtQ1iru/kRQUSXu/7znj1LAX0SrF9a7I5fuL7snwnWVsRJJJgivpqP5l1fvRK/AZD+BUS+9Vl76wtZmL71XnvgykzfuCKjGqD4it++9UxfUT3bvnUvxGQRPdBfr7vhlke7/L+pbk9akmZS+/SvMuAke+KSt5Q21hA/uTrkBpL4ET+5Ovu7/f2DJLJ6/71eFVZG6Dr/vUz0C6iwtU/7/2cGFxYiskGE+/6opA1XICb7/rigevx9TUCFB+28TqNbQ7BEum/efV/8hgfpblt74fJCB/w+FsGU04ggaW5fe+ddggSo7l7765ZPP7UH91ZGoRUYsQf5wYVvBb+5Ou4H5XvkB/y5Ovv6h+/YsLVXBDyH+iybW/dCDBLAQbFIet48R+eW2E3kMLpH5TxOY1cPxkfrK/40CUfnIZ/NU6NTtpJH7uHtR+ARGKIAj91H70Gju++yQwA48GHxrFwk1SCwdlaQkGsjVHBiVo0AtsfnMHzdlhKjACrH8v3AkQROfhcKEJL93B0GRm8dRpZX940SuTqG8GCxs6yYBmIpkFGtyD4vVlDdsHMWhsgX3SVxB7BuJ/fH6RDQcH3H9cqyOo7H5w2CaEBzicfrNIHH6JjWcG70hsf8zklwbjSMXDP6ayf4yz+wccfzK7b87mgSp+8n4vWWIjMn6afv2MWn8SftPhoGw8fhupIEJAmuDhRvQzqLFalBnqfpyBGn8yun9WxK1okpx+P7j1B2p/iroCsRIrWn4mfntYXK06fjWIC9iy7Xp/Yn4L2VMGhn8qh8+tRxjRF9PeBUYTRkv3qJf2hk/Ib/fFRlpexfaDda6H4V4uX/CaYl5SXvrzlUYBX0wt1UfOf/iWXoZxXzCa9UYKJMn2OJs4s4pfTUdlcUF/OzgFhgv3yl6gWiN3Wfc1cF5GKV5Rh3N5Gl4xh5RHFWO9RjWGOl6MlrSbhO1ZXsuZs8xDRgZeuV7NzCNHu8kn9umHa4YmXsLuFYZPyZFfJJuIxlf2AZZispD3N/f5h/DHToCVXjFwC0b4pHZfi0aTh/Zf4pZTR6/2Tl6cHM5+El9imvOGPn9xfj33dV/AXj12b/Y7R2QlWfe7Rj5fd/b7R82GSV+Ol86yJX4h6SqbgV4OX8VWhF9B9kFe3YZQxpF+vYfNfmP2V0Y9d+l/I4dRh0Vf0V7DhtAkVX/3Rv5/y3lHh1F/T0dZfi5fL0Zn931/Tpon9tv3c4bneDF/n0aox7F+S4Y/R/F+Dpp/Rzlf45cDfiZfgO79fpv2snSVHVuHBV7V9h6be2rcFAGX4Maldtl+B4cXRzl/N5aPRp5e2MABmshzUCk1X3uWYMYv9ojGHsY+f8WU1cabf0uGcV5RmiM+LR2stK1eNmEPhqqkXV/TXsy1rLVpYu3tOMeAD3rvkcLvhqAPhMcO+D1efV6u75HDvLRDX4Esv4cQDngwJ38aqpd/136Ux4K1o19DXg4VJZs0xvAPE17FFt06GtsQR8yd93+L7YvptWMoDrWbLMYu7pBG1u+pb88uhH29zPz4L15BqiOITKXiDvZ61PkPX7zGX6DneLwP3Md7UB9ea1/SugSWm5gA/sLG7BDy+GD/+EbF8j9+6g4eLFJGQP5Sx/IxwP9YRrEsjOvkVKfvXJfreadebJYNiLDeSN4XmxXGDoRQ/yMRy5Tw3ocg1cfkVARozEfjkD9+WAWaVx0A1HL1yQKp2sYgwy7s8g+6x5j+f37WoMpWvyGi+EX9fEZmHVwPxyGWxij/ozV/f93JSk3Q/pxWEbmWDqyAJsYRR0C00g73O9NJ4P5Q/1gICBbPKA7GRbGI3iD/jJZY/j9fAhxzfxT/QFtRhiwPYkefiXBac2WRR0BbcP5B9JC7nP/g/y67gUbvmlT/NvAou4Kpc3m/XxV2SmRfXyrJhkdkqMz/xKLSgXyyz0as/hpJLP/iD5xIbP6SD9HGXP7BQTZHCFqjlTz/tbroW3RMtBD+Rg1pcP4Tdda3Ev4C/2j/8nNI/kz/W0hi/3T/WUfI3mKOBFpriBwOiv55xi1peP6NzVG3357Ss6Pl2kffJQT+PQUJf2r+rO7s/53V15QbXphzsXBepW9e7F8JRur+pv9UsnovTNmS/mlHTcGmD8z/5vSJhqz+OxA4/2z/0OrcWsWFwsU2RjeCM3hqFMPx4sjlHT6G+P5g9gpGsTLS7oXaS/WO/1j+qF/rytfnmv+u8rb+uv6I/2mWNv7qDyxb15R+/ycR/37w32fyFP+w34H+Qv64/j92jztG/lDeLoHGmwPL5A7I/mlHkkxu/2wPxpoxx5QPEf4ks9H/JP8cWlchtv4O/imX6cf2/oT+zv/amCGMahR5R1AeC1/Dzo6pQgUecq9uYq0ec7tv4icfb/tvQOJKbYhFmf7KiBjcr2/Rue7g/a3hm7BAB6Hnb0zv4n2F/5dvBf53ZVXuF26rUdDzt29+ZEPn5f84GMc5ou7JKAZ8ZCXEm0zv6UhKmM6bNO6FSM7Fj24GfO/E6bSfb/w40Ilfb7aaxWXxuT9vdJp+tK2hWf7/bqI2aCT2moQJFjjwbYqKwO9rNnBnkJsU7vHF4bnb5GLvRjbPxEzupijcGFX/ErgBe0yNw/7Bm2fwxmVHYuZ0hO/KfewPkpuSlh9mSO61/hJpUXO7bzW5Layq7uxPUpmS7+GatAfoFBn+vSzKmtjusjiPxE3+M/7LLU6Mxpv/4+oWlf8NN4Bh4sLE76yHxf4U7vX+kKlam0X/gWnEFe6aB1xc7+bp6+J4sFzuu/+d/oc5e/5oSSTu1f6bSevkZJvN2OeKF/93xGzv5x3yoHzvTf9V2FzvLf+3HXSwPO4Jf8tJsCSOmnG7vBhX/+9pTJtZuYpQl/+um2s2mpUcm33/XzZUJYnpA/6bScvmJ4Ehl+esGCRS7hKNp/57/2P+HBmhsIoEXDuOkY2g4R/wK7qubH+Y2f87pS8d2XHFWNSruBXdO34moRbUtjNSicUDoUAELv0JYi2pP+09ioO1LoAPzXn9JaliKakcAHeoSIAc+/FDmEaElu6DVgdmFWUSgBV79Ley1CTj6HN3EtccwkmHQMzXwAQcKOVilW0Z+jbdwupLt3UycF78/1BkAKkdAKxJ4Up3cc146zSffr6vF9+/LsQrY6aA4aEX3KOIe0g+GhN9yjiJvAPwICgDbYgxkEugE33dG4hAgr+QeLRJhJPyPHunF17/Bv/yr7qeWen+c/dL/Ba8g0ARuWe7uSPckbi28isAf52BRaafcu1gHJEF5Er3EwBpfRYryaLSN4G//U+a/gCeBQGALaZE54NXu9s1l9JMbRUAZEAsXuYS14nyTC257rBdWRgsQCWYR7nTRSIdiBQBTtwbfqZAMSfsoAzRaSuJsgEeLS0Bk5iKq8RQCaHYddAD7i4DVFSMA8Qs6FCFwSjItCG2kNZU+4+OkPWFUAxPuwi0VPDlANO6HP3YoBYSVT5oFAPkAf0A1KYsvd+Fp+AxCEOj0Bha13kFIZRAJoWq0Az1KqC1EsCNAK5chT0GoBhuIlFgPzUkziL0eQB+QDiXzPdzcAcekEAyzvdRgHB4kGcrx0foBjWA227nALoLBPeHoBc4oRgEdAPAFrLtNnwViN8TbC/TptL33OM2bwCU7zALSmtv7iJ/ug9UlM53AMr7sQtA4B1wDMe5wqjGZBcA3+aO/d06CnAOE6EUAw4B7i0IQE+Z2/4nsA4/uMNslvoMdCuAQ+wPXuwiN2/4BCkyAfGZG4Bz/cYYD4gPX7o4tQugTwCPgFapzzGoh0foB2Q1oejM92NXAEApHuzIDggEwgPwHBVFVYB5f51gEIDz+8AyA94BqkoI8ZHXE2aM2oX4GooDX1IqPyKQGs4Pa4Nm912J4li3OLI/G/8NR5/gbigKw9MuoJUBbJUVQGKgM+dAqAsUBRj92R65cXRkFDZfyc2ao8nRYg0t7o1xQ/YqIM5wb0hE3tMKDPDSv6pzQHJgxQIuQiS6YbKB8QYIVXK9uqqXU8UccoZQzOgssPWDFiQuQxplQo4iYhsGApva6Jg0egigyI1GCKTkGDIM3wgBgKNxPyDV0BxYNYXQ2gMdAcSEMEUDoCeLDWwhRFNB0M0GNoR4cg1FEF6IWA1kIepx0wHrgz58FZMSsBFhNc1CzbFuhpznM0G60VQwFNgJtwC2A26Gl2cv6gLZhQOp5hAPOZoNTIjFgMDAVSDesBVoC6cQ/7T0IGAid0BYIMBwGzqmdAYaDAoYJ0x7cSyg0iSpk6dnEdYCdpTl7T0dBaA1eKVkxjQFxg0YSLt4UR+YFBVkBmrFBwpbOaLyRZ8kXYXgNtdOeAhtMt4CpQFb6Bc8l6OVueYIBdh5XgMJmkzAf4ed4CD3TxjnY+h2INEeZOE9lyngP+wvD9ACB7w8x1w4ekkdo+AgyQDiwqnyA/DfAeSPD8BzM0CPQhaEggQowQCByEC+ZqoQM9ttKsHCB8EDyB4YQOhHuhAu6sD4C8B5EQMvAXhAh90lECi76xcRLvjAJDjYtrhvwE84UQgT+KYnCJHpoIEoFmPjJ0yYksLntgt5sj3avp2PHe+XI8wSz/oEpfsGEExSjRhKX6EBA/mGRgTb0MrhtIYGunYRs8jfUeYG8kkhxf3tHnyQDJKDSQKTQ6KR1cnTjXSBskxyyCSTSi3OopedqmX0GkjsWm1oO2kMRKCkCxR7otGkSDK4Xk03I8pIEVDn4tC5AsSBWi03wh15W1MlbFOhaQfpEbrKQPNaHWdOSBgPoH+bUxlCgYFZSpEUg9TYrOZCQWBJAUn8lVRQJaZ8EtpC5PZKBNPxjopxQJYWImCbdAzC9psR9BFEgd9FIA89o8PNDl/R3eLWPAJAYkDHPQd+EIlK5AhkYCsV88qT8D3ePT6S+YOUDP4o5kFkRH/UUr8SzhJERdQP2imaIaSI0El9IFLOGigVWQJqBLzhxorQSRusMlPSaB1kD9cSvxHKgWHMOc4GSMlnCDQOdHrpiHqBmY8E5JFQNiRCbMQqBm3pzfStQIcgQ27UK4sY9loHH/ROfjFdDbW9tlbYisAgY9NdAyKOvvANPQ/R3LBGSTLeIHVkpIgewi6JsLXWT04rpQsj1ejugUjVP5s4YcnoG/QIAJHWoCEO9Hpg5p3rGuJndAjl0qOR/CagwN09O+UF3gutZjq4XjSR1makF6EOXsRwjI2WHIBaHCFGD7AUpZq4hnpD9AmyWoGxNyZIwKgnjr0Lj0eQJaJ7KqyMJsbYK1uqjlNoRVEzKYDiIFmB4EI3oHRckyskGsAomKjculq2uCUMFSTGauoXoshzerGAjsvXKQA/rhj1iPQNJCEJ6P6yR0JvKZYJHpgfPgN8UR0d7W5ZzXgpKCTAWomk1ByZieW4bDhgTuaasDlQ6PBBWUClLZ7S6odga4OekNcDdAikKGnpZogaqh8jsp6D1w0uJ0SYuAnSuiKRA2B7acNPRewNBJmTA5BabsDIYG+wLB1tqTIhuiUBA4GswNhgS7Av2BIsCumC+oC0Wq2sWyOcMCh3hGjBLpGTAxz0JMDriYewMc9JbAqom6MCToFK6ylDgECVt2fsZjeCWxCe9IFZbNYzEdrZAetCLgQTArauo3pu0bqwOscFN6Mc4p0JSYEpwJ/svLgYOBxXoqHLLt1bgUTAoKeNMCPHCBtzCgcOsXcmnqFORxJoB7DqLAk6BCGwNo4yAmYXknAuUmKsDznC24DlJh8CTyy+qIsQadzE1gc3A02B4cCwoH1wMlJkvAquBhawmo7xwJA6AlAk0BItRK4EAjG1gVSTfcMLssy4EZhwxMFjLVYg9EdVq5tenm9J/ArKOowIQZ6vwJWJjjAu70j8Ds4GxGGW/nnA6OBbHpcmAaUH/DhnArPoEsDvoE5wIT8tBsYBBgSAWUYLwPmJgAg6x2wsD5iYlwOsdmggwUO78CnYZIIM3gfvA3I6DqQiKZHwK29FAgiuB3XoH4H4wNPgeOoWmW1cDdo7mrH7dn/ApqOhygulq/wLLiF0TdmBA3p5vRsINHgczAxhB3sDCYEHQJvgdxHKmBsCCqEG9wMPdhTA2wmdMDCEFOwKZgXt6RGeI8DQOocwM0QTagEmEPCC93g1qydgbKFE8QpCDSKhdE3lgbd6ORBp9BV4FPeiCdkQgn2BxXphdYBR0cQccEIKcWcDboFmeiq2B3A6BBTiCv1imwPSbm56fUcIiC0Qreen3dKFkNyOusDnUh0WRaIugg82Bg0QPYRuR2tgVl0AtY5cD7YHFel7snbA2RB/GsbEF9VhQQRBrfKOBcD6nZkIMNgfdpYpB5iCpiaIRHmPHWsfKONCD+RI7cQUQeUgqigCiCTZ764iQpq4gth4Uas6o6yIO7DD4gp2I70CP3h4IOdgTAgrvOeiDXEHQphEQR0gxTwISCkYG+zwcQbIgg2yy7d0kFKdHhjKSkTxBMCDVkHJwKhgah4EeBUyCL3BaINmQQnPauBIsCDEFfdANWAChbhBtdB0wi3og/KswgoT0LcgZ4FVE0sQW4grRyFxBGkE3IIXwOsg4r0YjlbkHDIO+QQG4N5BfyDl3R0Y082mS7KEgePo7pCdkDn6AfocFB9VNKoFz9AAzjvmSCUEKDDtI85i1EDjgEn0pbA+XqySGBjl6oLt4mKCOjAYUGhQccoXLoBKCbcD9GDpdnccFFB4cQ0UHqSFp6tDHXQUCKC4Y6eW0klmSg1FYtKC79CkoOpQYygnFBJr1kM5vvzqBlVUBkGnB89YFIVlEwMKgqHooqCeDQnfj8GAasCZGSaRZLgHjh8mAN/XsYB1MlUHlVAk9N3wD0Ko05JUE5tBfiIqg5gM5fxq0a9egFpoSUI1BWk0IUCm0zNQYMVNKaV3odUFyoMy9AZwNIEsqCjUGbBA28PrHF1B09sqUE5AiMcBC4Y+BhdxoabYKE2QMfA7zIdtNvpouXkqqF4WDYEsqozSCRoNe9FvHORINZpObh83h6nHJwckcsLJ1RDix1cQKhCWzItnoAICjSA+llp8fWOFO0HUG2oOc9Pag8v4huMUEimoN1QT84d1BHccLYAOoNVxp4UAOmHuRHJBSLw69Kagi9oY0BmXB2oPoehGgs0QFnoSmgxoMvBIOgnTgw6D9OCpPl7QeWg+vQ6xQXnBRQFXjlwDSX4Ui9YcBs0xLQa6gmWEZfkK0G/Txg+NdTAtB4qtt6DZhQAgKR0IyANssU0HErCnQeO7c9BMypVIyYuADQSTTJVA5VQyXDVoPbpnOAUdBm6DHLjl2FmfCugltB7dN8jB/tGvcKzeV9BsrBp0GM00fQdhCMdBMGk3EiJoPDPpdApjE/i8F1oUY2dfHhGG9aSGD2ZKJHU/RgOtdQ6Ea0XNrYYJlRoqjOJe91QHNoJYWseBqjCjGqS9SMHUYzQwZkve6oiqNcl4KeUQ2oUvNFKjGDu5jrLzvRhUvYMe16Mal5sbU8MqkdCda7G0EjogbSfRl7VQY6vqN+NpdLy4rn2tINGfS9gl7SbRHWpHVYZegGMnBbcYMQ+GBjNvwZy8eIyEbUN8K0dQNGAHBcIiNHS1qDptVYaEq8k/S9ox4aGxgkza6TQDMGloxNRocvYyo8dQq0Ybr3RqMRg4eIxdQXMGSYN9Ru5tcka+K8l0amNEqXtKMP9a7y9QMZ5oy+XrJgrjBTEQMdwNo13qmkvDVGFqNxGhgr2Y+NOjfyKPmCuMHnHU/WgajRFeeWItMEor0UwZBjEKkGK8+NrOozivM8dKLBXAYTjrsYJ9mMSvLjBAq9z0afhCpXmWtEE6mFhLajcbQZXoVgt9GzK8SsHSYMf8LSvQDG8mC4IjPnXxEm4mGrBCm0yyKcnRXWlujH2YuTwUpw9ynVXpLUIzB1/VysFmYIWwcZtItG6TRZsGGYlwxpNgg9aNGMzahjYIvWkVgw1e5GNPDImrzJqO5tRABSakyhJ8Y1zUkHYXzadq8TWpd+hKEkrgRv0V2CY171hndXqJjVNSxW1N/QYAIxFuadRTG+H4mkC1pkkxndg43Wf2DgcGgtBCEqpjV7BvCpCyjQIwADOTfU9++mMPTpprylFsZjNf08yx2tqNoXvfoqLHBGyosyAGHz2zZGWvOXaNuNLups6GG2tNjSte75pisaU4NcxlNtFjq+2xtchI4xzOmrtOf8na8PVRg7TAyB2dPte8edacZj+UXHNTg2s6yFoBcGNnVF2uzjTuqzx1ssbeAm6LoDtNLIPZ1pcEnzANxhuvKYk22MlcGjEgpwfuvOHaUXQaEYdRRk5Ezgs9ev4IgsaSjyeJMrjO9eAzxpIQm4JY6kxdRXwaiMvzpkbwZck3sSC6/kI1cHnY0gunhcJnaLuCcN6o4wdwbJdIPG5nRbcEEPFaxtyyN86AeDOsbMMigNs+vdKEXWNYN6Vuk8xirgpDeouCScFeLyQgghg9yCi4MnRg+L1CDAlddPB3y8+nDEyTCXuX8YhER5xTXAkSgLwS8hNPBVRQaMFVBizwSwmIFewwYe+LONDHiF9GIvBPwxK8EaZnLwT/4JVIDbkjCCYQCYwe84KiMTh0TMFsQVBUBxgiFY7eD9hqFITHwRk4S9kgEMgjqJHWLQhs4W5eaiF/9BC+G6Xr0ePPB5cxGpilISDkpBPKfBCWZJZJjLzvOlFcLcKGmDWnCiyW0wUcvHZwj3RDDTWYNzwd/xNZeg+Db8GzchqOg/gja4ODkLhp7Lx5RI+ZWtqG440tRG9RPwbfg+vBkSYesHN4PUTKJgy/BviRM/BGAjY5CAQmY6VJFCgyGMD16tIoe1w+NQ7eqLHRLYOVcU1wxHUvELV4MBXjFg4YMPeD4sE7HTWPP3g7uYaWDvXCT4LIIQAQiKymWCNphn4JywbCdfy4gLgCsFp+AwIbP1RTBMBCf/AqrxnwZVgj5Yk+CBV6sEMpXofg1iochoOV634I9pq1glghy+COsF74MlbAidJrBRKFt8Hcr0yOqEhffB/K8ZyLrBhKgCANC/Bt+DHqCqLG1XkVMK/BULU1R7yTDsARSdKFej+CneA5NC4IZpGBk662CdXAqhy1Xi/gyUYRvU9sHgEMAIQCdBdkHBDusHT4OcIc/7Lsu9GNfb6d+nzDADma7BlA9bYIg4PKpuGGanMcakY4LhEOhwSR+TNen2Y/YI9+liFJ7BCIhLHs+wy+RGuzAh+INeFMwsiEbv1+wa2GfIhka90JyJwXSIVYoe06zV8vyDk+CTXnpjIgOwZ12AEPUhkVEEsGuChYYzu7YI2UdLgjKQB1NUbu7J4O1dlaKPfOtaVo8Q/4N/zLAvPRMjUUHmwQpDwlIAGM5CoxCIdprijw5M/tf9A6esS8BUd0mIfbNEvy0jx1iH8I2FNj/g38IYxDDJR79wZVMsQ1UKVMQzkL7EMA6gcTHkU7d16q6D+ThFL/tS2kg69XmK/7ROIc35c8AN3gliGwL1F0CntEygBQRHdS+HhBUk+1PauAxCVi6d00bdoXg3kkZVdhgpDtwF3pIvBLCIxCW1C4LxOwtumRjyy/l9YByuG1km8QufBcxDa16fMTemDiQ1UK41wORSMMXSaCWMHkUYbRjKgsdQjDNcQwYh7+C3cGSIHz2qHJZ1IeRNYVgXEJHOk7g9KYBJD/houPGOIV8Q78YCWZVGJWYIFwHJmCkhsF07iZbEI+5NBLcUh5JClqQ3nTuJvcQ2EhgG9+SEsEJpoE/PJj8PJCd6LDIxZIQMQhFwSC0OooId15IfB1A6YboouSHqJQFISSQzEmXzx5JiokP1GveedyCX5c5SHj5kSQhthFy81NMtiEdO2rmmaQlUh/SJikxfhDdFGyQzEm2TYg/gBkLiBPtgNRC2ugOGS/tT2IYCQ2fsMlwXkIukL2GqP2GEhDpDFiZAqFhWDaQ0MhaxDBSGBkINIQSQ10ekBQtr59EDFIeiYCNy0N9KSECNRT2ll6RDeHHd0CGakMYuikILxCkJDUN67WH9ISqhRMhLZC3piIV04uqcCCYhNxCFLo/t1rIT6QkUEx3kjpghkIsYoCKWkh3A4IVimkJ2HoaQhjqsqR1gzZkKuBNiQiYQlJCrgQTEMlIcHgyc67zg2GLh4IHIZ1MCwq+F1Fn7rBh6KHCQ2chqpDqyGiYGEmBeQwwEdqdGyGTkPn4JRgz4hlxD3VwAkLzUMW1V8hO5Cby4fkOsCIXgjMh8/BD8EBqCRIeSsJvBu5Db47U/w73KwbUROOtV6pyMG1Tqg+SeR8PFtCNZX6R/jrObAWqrpZODZrmwq1megZR8aht5Go4UN9iIobTiWj3djQxEULlqhhQ+R8KZZsKGkUIpNrurTVQptx9DbqVSYtN1OCo2Mus36gWG2m1gRQ0Y2X5tqKG9G2oturVV/oYRt41ZYMQWfH0bZNWi2wmE5LJB9qtMWUxCQlDldYVmi4TuRbLeq+QFGCD1m3kakNwBm4nzJoKGyTFVDI0bMLWoWJtbgUmybVjKGVihE74C/TL6U5Nio1WoYAektE4C9CaGF7cNlARmte5iGxC0oROrLih9KQcLZN1S/6IEbaShQPxBjYDnFMNjBQ3o26xtJ6pcUJH5lJQ8ShCFC7cT9m2IagU0cKhyxsvKHBUMsoXg1H9Mh/M8zYXNS/6NpuSQ2uwxMqH0ukPVn5Q6SM/i12ZZ2UJ0jB8bXRqpnRY8QMmzO1gZQ8fiKFsPaoi+gzLMlQ7HoD/RCjgEQmAak6SK/ieVDg1buUJroCCbL1WPVCcTa0tQc5uALIs29tUWqHIm2QobUAcccE1DOWpD7V6TkpQ1d8iIZwTYdaxqob1Qs82ATVtRSpHAjiHNrcTEbgwfjYsNUV6OSKRqhgVCdKEzHCqoVI1OahIScLjZGa1WoV6bXRqu1CejgvG12aq/RAU29cMktYA9wuTm9QtLWWj5JTZPUJUak0MDk2J1DrTiKm2uoVnVAah6ZsgtYUUMNTjxQpuqLAwqzb/UJ0jGWbSeqECwxmRI0InfDSKXM2wssdiwrISzNn5rTahzZtIaETCB2TqDQ1d8R1C7qFytSWodGbGOqPQYwzZCm0+7qGbIM2FWsr1CdJwQtjk1JzEcZsQqH21Vf6G6bEpqA5w0zZw/iC1nzQzU2alCuaHADHhoerVFqhaNCi9QNUKlofTQys2qnwOtYaUM2ZLjQ+RqqLR8U4C0MlakTQpVOCtDaWo9UO7NoXLIKhJDIhzbdUK/6MbQpeqetCjKEqNS0zD7CRuWbMIMaH60KOapoMGkBhqxodb0UOhtPXoI7WuwwWBhbmzO1j1Qvc28FC/aEQ0M1oc5QwNOo7xHtZu0MvNjDQ2ostQwWWgi0O5hAX6FlofVDSaHpITfNiUzQ2hN4Yo6Hp0IvHH+bdFqQtDqkJLm0SoYAyGKhMlDwLYLUIyoW0hfihWdD4LZ1UJIoW0hVmhhdC5BI60Jyaj1Q/hAWNCoaGqMmItobVIwYndDy6EkMhnmBibLOhVFtRqG90KgZOAsMdOr3dQzbjfBYthPQ6Vq4rId06K9ERDFSyAhWxDUkUwEshIVoPQuehDOseqGuUNCoeE0Neh8lCuKHnYITZKZbIqgJlANFYKW0DahXYD9OVPA+kBn0KIHv/xMqM4MNh55K5TgdCfQ+DoV9CVebeW3foYhnNeej+kJEThtQ/oV/9Q7IADCf6Ejz3oAf/Qy+hfrUBZD+WzdaoAwgmS0ZUQrYRUizqMk8WK2BudxsS0yUitmgwvtqwO0SrZJ+jBtCRndaA5xIS6i87VjuGGfCTEKDDDrY9GTwYWbJShh0Rkk/Trs0oYWQw5rEY0RTrZHWwRqMmdGq247UGGGXWz2tkfrbhhr1s+QbMMJAwq9bA2Iw+s2wohZxdckx1Fwof1sJID1tREGFNbWRhC+tvVYOIwWtgR1PnM+mdujoPtUaPMZnLq2SZRLyg7W1atnx1DBhrGdvhbjtQoYbdbK62WEYiDBJAP+WAEJJZEmwCRbBV6xYYQFnLDCaEZnGEogJksFp1exhkICSmRiMM3OmdbAjqplBoJYBMKkYfQXD9Y2xtvRj6DAUYRVBOjqNDCXGEk+ikYcYwr3EquAwIzWMKfWA/QDNEzkZwKA+MItaMhacmoHDC90Kp6wKYXrWPvW3jCUQFXOS8YWkwlEBuhQtGFBMIXSNaOSJhgmFwmGRAjN9FEwwVICMInChxfGKtiUmLRhxjCk8Gd32GdixqdKgmBUNirLoE8Ku8VYBYjZJhKrEFRY1HlVT0EDRUfL5zMJjujMwsYInID6CqDMNWYTfeKcAxRV8JL+NEpCgsw25KuMQlqAdFWTzImBIIqvRVOioB5TLKjsVN8SIyYZCobMIvEt4FU4q6ilmsAqFT+kPwpNz4DhUkPIRQPM7LoVPW2GARCJSIVSLYPgVQFhhhV01Sc62wlNFkZoqF5VOJIVzi+KiV+Lx22EpXmGuFR5kHmqDIQ5IMvCrHiSqoNSVcYBAGpIYqJFTnvgRKMqY35dIir15ie2uEVbPufRVbtoEsIZKt1GO8SsJUKSr4SXRYSMwmkqLzDHioUlQKKqCwsHwOzDEJSTFWfbocVW8BXFUt77eulrWvSVB5h5qtpmGjMLHiCd2E5hZEpV4wfewuYcnmWLYV/kVipyhCBonywpIqUEl1WFU+BYKlCVWt0TcQFWELFVrdHd2FUGBzDTyJvFQ2KiZoYmIprDVCrChBZdhqws1hJmhuCAnFXFYUIUByqtrDJsrIsOfbncVNrKFaQ8ip6FTGLClwN4qwLCj1RBsPhYeCwweSFTBfBB5FWI8vy6KNhNxUEWFOFTdYSpXI1hs2VsWGwD0Y8vJKNJkJLDkSo7uUUYsSVGoqLeZ7WGGsJxKqJKQXa2JUqWEsu2i3kkVAoqTrCKWGasLVYWlkBlhKzCjWx3fnpKp7SLiUYbDmSogoLpygC3EUqx8YO4zKlQmMP2w3zUUUABSp0APqGq0YT1CKE5d4xDsLHAJKVAdhs7C5yiNEJI/GzCV3oJvAMuhzsLigNaVcEeb7ghAH1DSfjIQmLdhb4B9SojMH/jEaVVHBA4wn4xfxktKiqVXuMZ7CF4zLsMHfuOpOCoTpUS3DgJldKojg9VAXpU4EyRlVIDgGVcKm+kBl2BEJlDKl1tMhgEZU2cx9bQQYUwBFKqH8wV9wouH0qvmVEDYPF4ryr6czg4X5wHeOSFUSypX8EUmEWVNTmH8x6sLSV03KLOVNWYhHDp8qblDrKqRwrHghFVaqAKI1uSpkVUZy15UCOELOCMqrBw25KqkRGva0cJbKr79TbeTZVcVL0WFuSi5gRXYxHDKyq3JT9egoRHKq1YFTKoZVWY4RWsYkqElUhfrVsImUJYQT5I8UoX/KScKePO45Jjh77FIEJflUFwL2oMPKCHCJlD6cLsqn6lXThynDDyrsKUz8n6MA8qM51O8pkWRk4Uiw2IK53IFOERj2GQoU5bThTY9eOGOcMLSoKDSThMatWDr+cKW1vJw5sCsDt0wYhvQKqvA0Ct0afAGqLK6k5dPm6FkYG+wjzQ+VWtTsKtB96hEAwKj79QlouTmPjhYXMx0pFxBKqngmI6EshlyJTeBS44Vt2X3AJVc2OHCIFB6ERJarh6+UZWEiVQrdCOgQLhWHCEypcST84W1wu52IQVDRjmVQEaGi5fpC4TlZ5AgkQkRFxVOLhvc1+MoJsOS4ZJ1fjKOXDeyqZcLYrgk5MiyvZU8uEyeWBKr2VaLmshkaUBlcObKouEa8SVXDPOHf5Ro4Z5wjrh7RUmuHjaCm4Ydwmso8lVzuHXjCU4V1wp5ySnDIuEjcN4xPZscbh5VV4PL1sPV1DVVJDKTHRPPD9MNLooJiS7WLhsvqxA8P3NlNQ7PBGDUETb2HF5qhuWA1WhkpJdjIYP5qtYmSMAlbZVaqHGyvUE6MRWqxFCQeFaHQxuDjwz5kch1zTAo8Ih4RXg/lkwtsykxaulf8mc1fZMzrha5Rl1U+NlogSQIRyxX1a48MiTPC1Mw2ajQnaoUWwkLO21XBqaOIH9j+1XkniVhfsEEmCA6orGxh4RvgxVqMlsiaFDL254cWbR22TNR46rXmzzVvv4bVq7Rtwgjp1WKahLwqbI5vhq6p1G31gGw0BnhGxshIQ5NGN4cWbUagDJ19eFjm0fXnrVbXhNFt75jq8PYNqTw2fsDLVlDaI8KIaMLwqQ2fhknmiM8Mx4ePVP+qPgVJdj/Ey94Wzwvw60k8qJT+uhD4bPVBHhajRomrCSibdLvVN3hQfDD6rE8Pd4afVCPhHRtL6qCNQl4UmCO+qm9USsKxQm3ahS1ErCuvCP6rPTz0TO26FIEgfCBeFCLGYapSbFhsoDUsWqc8NQHF81UE2qPDW+HJ8M8Nkg1eXhgeJBeHoNXCnjLw0XhJF1B+FpGybdBh1YKeVEoa3S7Ji74W88MJqUDVQTZfwCYamA1U42hvDbfD18Jl4WXw6vhfqtsjZvVBSdAJrJI2/DUKqYiawKNlE1GvhS/CJGol8OFNuT4SPqZcxgzZoWkXmOk1Q42lvC/zpX8OaNiH6fJqDvD9Gr28JT4a3w8pq6ptCeHmNXmnl/ws2o3TVqzZ58KApr3whoabrpXGo8tQaGrbmOpqgc9r+G+NXG5vebPN0sTR/+HLmyKtub4AxqbJs5+E4CIL4VPw2JqpLVhJTFcSSaqg7Jk2VZEn+Ei8Kr4ZKCA/h/2JmByECO74UU1HPhfxtUgjBNQzNh3wo2UHPDmBGICNo1rXwppqcAiy3y0CPaarEbBXYXTUyGrVm1V4TY1VARDZsIUyG+A4EQAI7ARnBDJBFsCL1lCLVWnhLvD5mqZ8K4EcFFZvhsfC9ZRa1Rl4S+0H4MaxoD+EP8LKCAc1Oc2mV8TmrJcktnuebKnh1fhBZ7e8I5OiQIgwRTzV6arO8P94XbKTARIAivlIL8P2TH0kEP0wLU5BEv8MdqCEIw42pvDaKZt8MCEcoIr2UAOsw+GURGAES3w+SKkCR/za6CJgCGc1LAR3gigAj6CPWyDnKQlq5psXeEyU0n4WHwlQIb/CMhFMBAr4e4Ij30XfDKhGRiH4EYAIylSoc8UhGXBhHqjLw7wRoIZShGVCJsxE41GoRCQRP6oMW3EEZ4/ImW06VKBHStQ1an0QUvh0/DGwThTx14dPw3ymNc9WhGF1BZqrBbHIRkwjyzbFCNVatDw7wRR9CdJTetUUtk/oKQaVrUeGJHCMgzlHoM1GBjBnBAaKyjaoYoJjcz9CPLYi6AOEWpbM4RSHgU2pkMVeEYig5ZoAbUDLavCMBHq61Vy2nwjmUEi6HeEaqSKBhgdgA+gBWyBEVTHflBBxFs2pp4gE+N21DsgqiZERGtrwLag7iC4II7Ue2oj7xuKKkTOtqM1tcRFGpDuJi8jDM8gg938GVtS2wqiIkc6FIjrEyYiO3Xs21IE6dIj115TtUGPlSI9/Bf7VaRHaLSNIQxHZ62XIji2rLtW6trUIdDqso9WD4O8iHmkYCEjqWSxtqCPnVPagSIuDigG9ZREZWxKYS3NCUR8+9afz1zRFEUueW3OT7UBRFJlAzPCdQVUenYclREFORHOhyIv88JojLcGMdRItmyIlIE6C9hdwWiPJGq54e62Yhl+REGbX2tkyIzEm1RR3raLxH5GikjKUR6F1aSYV7y38MDbVjqkJ8PREYCLcRraeMkRPHVZT4/WwlSKBvPgg8Vs0CBHkN/DGDbeURsyRTgS7Yz/PHYUOTqKGNWEppb2U6pGIo5UPZ0BEgdH33+B2dLvgK7V9REGdQHwCiIl0RkF1MYbHWwtEeXTLhMoxgaxH0Mg0PuWIg3ad8caf5K5kG8gqrIbCZNsR7ATq0MQLhLd2k8lD4SD3P0+cLRLQWqYiZxXRlwIq1qOI9iaEARsqGAwWYlozJYih2PQqsT0TUUSJuItcRcqNt6SLiO3EdPOdVWdFCmvAiS3nWP1QsSMhqNdUiQawlVJ3NENwwaslxFK2zsNluI3KWc8po1b3iKCVkXQSahmeAfx7xzGkoagQB0URnFpjbiwlabKnNDluE4jNnw2S3WcIWreKIcE80Kg9a3eYtZNLtE2lC2qBu2zRcPpQvzEWsDbKE0wXwnreI8qhMlESJ7wuEvVqMMByoGXxcJGOt1NRtG4JyhfFFiYFoSOfESYOa2Qd6s5xEgSN8oZJBQqWJEjV1aMSOfiKBsfFqx4iXyiASIEQrFNKNWS9VoyjD2k3iKBI/cRtVk+JEx1WmTFotchULEjjpaHiLZqmImDgSBaddhh0SICSMVQ5ds00suJGP1VsTCdAzuAcWtsJG/7ltoUBIqKeBEj0dZ/iJcnuqrCnWhgRl7aiSPtqmpI9O461C3xHnS2YkWzQpLECw4d4HWSJWTKY5R6W2sJz7bjiNmodMmF5wvkjV3w8Jg9aIpI3Zq4kjopHnIJoagVRRz0TkiAmpJSLQXpRIuKRVcCgaHx+DKnsZI3Zq8Eid6okOx0kRbABh4bG4gaEnNEanklAKRqYgR+Ha7iO+oRRBPaeG4j6pEptD6nlVI2zWyT5hEFA0MZKGNPGiRI6s1JEVFmnlrOIje4JG4kJHdSPodjFIpuqHUigxaua1KotY7CKR7sJuHYLOA61jVI4mWiEi/NZpSIGkbdrTKRRUisJGlSP0kZFIvx2eUiY6rDsCUdk1IlJq0EjMXCtrAq1k6YZx2+spANaSnHsdvtI9Wq3kj64iFa2Ekd7Lc1YgtD3pG8y2PWIuIl6RS0jaWo2SLmkQPQiyRv09YJE6tQ+0J9PCaReDUTpHeO1fEez0Px2a9JCaFxSJzlp5I5yR+csy4Goa23EUiJDSRg4jYnYpSKGkT+ZPmkB1Dvxj1yzukVI1XOA0nRv+ae0JF6Lk7cCg4OtdJGFO0xkU3VLSRUy5baHSSJXhoL6EcRakiPZK3azGkaU7Xlw4dDzxHNO1+kSo1WaRFbxRZHcwiIkfU7BKRP74GHjxVnfNurVHmRa0ijxGqnnpkbnQ76Rtbx51ia0MYkfu8AmRJA8fjQfiJ1arrIjnIIMjvpHQpjakejIsaUlsie6rYyLxUFjQvGR+KY26GayPg6KBseyRakjahAdp0JkUqiI2RMusPZG+yNUkeW8UuU49DxYQXSITqG7oadKocjMFaXogxMHK1KKRX3RxxFZ1RykaHDEdCk1DdZGoSIZ1unI4cR/EiN7ipyINalViPYRlygbaC+PnBEQRAGLA41B5lDnCLAoMXI+ih/c89QKy0D2sA8IsFBNtB+1ilyNLHDVQVuR+88X6HI4T6GA3IyuRfSh65FutX7kV8IulYvcjuZAYyEnnqxAzbow8i0eLQcM7Ho90DiMr9E7FYUmmPKEvIpxW7iJLUxryNlduoJEuo9JhgcbWvjkYVWCPxWHFIW2qM7QXmseaIOoa8jvxHeRg0Uhdjb2KiaYt5HmuwCElZkO12csY29ZXyNbSOwJUysTrsRLSbtWCkGotDvwG6IvXbZmk+qD5CTxGNCBD5GRHFmSBP6ORhd4t6lZ+MEjTAhLaN2YGRGmEqEi+Ruf6XA2AWJv5qGkiMYR/I5s0z8iz5GUwn1GPJtRzwuys6KRcMKthLMrHeR38jeF73wh4jDQozZWsMZpRgJdF2/nzQsRhRZBJlY590CYTEQBdIak9EFHukCgNoOgxph3dEiF7n+FhTIQo5lwiCjx9qcL2N9L0wq+Rco4gIxbyOEQe+aVeRbbVlFFWjH71moo5q4N8i0IgUyxXbJ21MBRtrQdORvhgEUeBQpAqsqs1Ng26n/JAIQhoonbdM8EIEI7bjWQzqY6+D4vxzfAY3F4QvBqMJD28Ea5CnblXghxRDRRG2JN4O8UbO3J8hOBDke4oXVZgu4Q/T8xncdnAkEIt7iC+bvBj5kyuQb0DemMIQ+9uriZ4CHuEJA7hPg/xR17d3O7GuG4IQWUXtu6BCouiZjEo7vYhKQh6SjXsBL4NkIV3yfcht+D4eSuIgA7jIQwCMo+pTa4qEKh5KB2LTY1ii6CF5KKqqJJMQwhfSiDSGmELPyi70N0UKBDUu5jKLemDYQgVunrQg/gOEN64SE0WFYvhCVSjEd3sUVkouCoixCwlFFKLWISso5ZhIFCh/jbKNbVLMxGxRdbcBgjIENvpKl3fCwpSEx8FN1wmITgQ/juT5C4lGcNwGhokogI0cndoCG3KOk7q9qB5RHyiflFxtiU7vkooNwvSjv+7adyHwcXgm9ePhDclEVsjq2EP8NJRRncDSFfKLy8JEhJFR7i5QkLwqLs7lso3pCx0YgVG34NxSJ7yCruBSiXFFDpns7goQ9iwkE8rO6H4NUIalyZFRGhDOlHOlDEAgMogFRk+o8u7TKP2QrF3FLYhvwRlHnciS7ocoy5R3eVeVG0EPK5Jl3TlRJhDfwy5dz9IWyoxpIy7JGVHpTCOUTsEC5RGyiQrQyEOlUWiLHthTCtUW5ddxCIUEIYwgwOZCcyXsOqFFqok2CjggtVFxEInYWsBMXMZqE44KddyG7j6hOOCP2CFu745mKIV/qDJI2W0CcwFEMdUR7BZ1R6bBxu5lEPiIaLmI4UDp0Fww1EK/YamvBohz7DlhTHd1aIbscdohYZVccH7dyC2tT/AV2S8IgqEDEPfIWZVPmhkkwuSHs7F7IR/DG78CnJZiHfkLMqgWoolCAZCfFGERXDIXmoj9M6/EaSEavB2ISD3Vkhk5Ce6pHEOzUQ4WRYhZajMigoFClcNPJeL8sug5MwRkOdynMSVsh6ajbPwptA+ISGQgL6PxDHiG2flcuN1fcsgYPlie6NqNBIRzXcJe8ZC/0AG9y62DCQ08hL/cye5ZqMRIYOLQmEKJC6CywD0sTBiQ/mOXe9SkKtqKHUfiQotRTn4FSFLkM7URKQ1ch4QcCyiwLEN+BOo6rkkSE6yFHuTz3o2okdRen0ESGSbBF7nEmE0ht6j4DTT4IfUb0Ve9Rz6j3q44vhlIV1yT3ucGjDfgpkPO5A1TGLM26ibe5bwASzDeQ+JRhJ0o9q6kK77qhlRtRBGif1EoEQ+WK2omXuN6igNGT3y7yAYeC0h6JUn1GuggzYcuYe0hspCco73qmsUQmQ3huNCQaSG12AXUQaSbDRQ5C4SoakKbUemqA0hH6j/TD2IQHUWXkQXuAxC+NF5KI2oBCQtshvDc/e4vIRQ0U8VBEhTGj4vySaLUQpBosjRQfw8yGWt0fcmWQjnu+iRSyFUFhfUUm3E5RH6jl2DTkLA0bfXI9R1GjGG65kPo0XkYFchWmjd+5eISAoQeojQYrZDveg29180Z2Q9dRffdqs7bplr/NxXefuc+CPSELqML8E6KITRmxRPCE2aOf3teQ2kh3/deIRhaNE0aOsJvBHaiHG6JaMy0exYRzRrxC5O7JkOPUfF+f/uoSFvNGIDyy0fohMChVP893QbrmvkpgeN3s2YUJqz1hRh3h0oFrRreYj3SxOl0EG1o6Ow984etGtaO60YENLrRYECEhpayWG0T4NQ5mY2iRtFWFQQgZ1oubR/4DxtHsMyGqLfmabR5A8gCwTaIQgVNogjAMEDG2iYFkW0dvPd/Sh2jir4GSDW0Sto2aom2jdtF4DxbGI1oqiBx2igTA3aMSpL1oqiB52jHtGk/SJHuT9JzeCzZGyA/5nhLKAWWbRKBEWSw7aNfBCgWBkcuggyPR8QJZHlHzO+OXWddTggo31xn/nb6KCOjjcZMUW5imlNLk+Jyw3ooNJDRgpRWOpAjaRnEhSwSsrH19ZxIVg42KJfewNaM/uer2Ko9KdFRgWuSlNFUnR6YEKVyZfUJ0TVjeMytkDVgC9Y0UrCQkDHRw20kdHyQKFZBQzRsO7cVf9ylY1ShIn9GRASsFUK6B/X1GHIjLHR3MVyRhXgTR0TtA9FkoxJc1Ay6MMnIDtcXRfkDO8E5FT4uI/FNt4TOjqPiZQM10Qrgjxe7UCYchedj0rG9FQ3RjRVhdHmWWw4rQ8eXRKui1TYSVlq/GFA96IcO1+dHtjzMtJ3cD4st4QEIHpQDZLHsPfrRlygg9FwlhBPDCg0AyEei9tFu9mj0RoUSPRnCtRhoJ6Nj0agYZPRme8EIGwlgCaqnosuR6eiA9GvgPD0b9XHPRLCt09E3lCGqEyWMvRG2i9QEFlABHknorPRGeiq9FMlnz0Su/PHQnH0YR6pGBf0PSWOEsHw9OUHV6Ib0dnfTd0reiDearGEBXJHQYPRxejHQBtQj8LOXoqfRy1FIpCObxJHtC2D1wU+iWXiVjhX0XLkAHR9ejK9EYFmRONnosPmgW8I+bQ6JC3p1nVHeuNsghEVfR5Hr2kadqaLdkdGfMi5PjfogXRtPVO+YmxX7GnxjcwO5VEfJpVXUi+hTo5LI8H8P4oIgl/0Ul9V8EQQMcdGif2JihZAt/RIhZPnAc6Kf0dnzA26A38qpJL8x4Slfoi/RLo9Nggb60rfBLo8TIyfMz4rD2zkRg/o4+BBA4EW4K6OriB+/F/RmysLQzkwiwMZoxSL650VI0FgGKrHnDASqopoZZ2406PNaF52BwsNujk1AMGOQSonAo24Y2wuDFdpUkLCYlM0QyRYxti4GPXtsd/exK99kEgzn8yPOhklHMg03VWDHxfUUMRwYk/y0qQcyAYGOaijA/HMgZXxMijwGJ6gf+/beK29tGEycGJIMYKQAL+zCVpEgLDk8+Ml9OhK99kFqSQCy9GBoY69whH9gDEM6LIuGQYupKzUCLDFIC3/0cvA/r4A2wFgSeWUsoMXzM2S/UC07Se5GJ7ioYpNKchjo4o+GPpMAQLdwxp4AAeEY8RI6LbdEYEIpZ0jGnB18KpFTc9sdIcPYj3XREBLkUe4OqRU8jFLh2eDpkYp1YHjhywggwNyMVckW8MXhNWGQVAknDv8HMoxKyRrHDfXT6BHdqDNYByRaWghE3ruNMCKtQJ+gsYFkrT3OsvpKGQiIcdvAkglduFisZIm7RijE4nUEpgfUYjyhjJIWiY01BJBHA0V7AjMDpCqsgh1SPoQQEmoxUUnwHGKqJqsQS04WxiN7okwiA8NLnB5k890SYRyOljLK/UGx6X/geib1wgyMVriMQEXtxpcDqh0IKuOsL24/RjFI6bwE+BBMYjG6x/h2rxJ1GuCKCYmOYlwJ/jFK3RWJuU2DDODKxvw7yFQ/WG8YnIxPRjznwVLm0pisY/Yxbt0+qwQuE9uk7cSYxBMCcTHl1ChMe0Y8KhJxjujFVlgtODfdS/wOhUnybTALxMaXMGkxk8lVw7c/ADDg0Dah6fVYMTFrAy6MTyYqssVhQ6THrIBzpIUcb4x+cCETHj8WJMfMTQi8+SdXVFPwIZMR2kabuKlMjjGz81BMXwyfEEEQM4TGeAhzLKkcOYxpMDeTFP826elUY3Usfc5uTEbGNaAYUDO4xGpi9jF9RUuMXJaToG8KUCjHDLVjLFaYgcOfK0xARcmO0pr8YpUxJ8Qko7qNHvunqY4UxAZiHVqAwW1Mduif4EapjVw5rrE9McqYkWBDxiMQFImJ+MYqY4PE+0hVw72FQdWoyleR6r7EugQP0CTkF/A2UxweJHwzURx08Mg9O7g21AEI6SmLu4NKY/Exopi2VjImMNMbKlesmLJiNSwIZWeMSKYz0sqGVuTHOojg2AvsNYxVJNSzFjAj7MXcY4xkGPIouDv/SmJsMhByGHmh0iaCBEDMU2Y/8OPpikzbimLlJimY6sx5JiYzHDA2rSCpTYVaVfMw0rUR3OgKiCPMx0D0rARwDCzMQSTG0xHNCazEWmLjNkmY3WsOJiFzGTAhxMW2Y9ImN5jpzETmJDiLTdYcx7pjVTGeYRHMWY0I8xXZjtKa7mKqhgnJWcxHpitzHMtmbMU0VRkxCFVzTELGNfrCUYyImGJi+zb6mOpMa2Yloe2pNnzEuOkXDofEP0s7d1szGjmODLCxCGJ6YJjlvzfjQ/KkRTNZI6TDL0gNMFrMZ6WRDUhFiELGdLneMcxYilC0FiUTH9pDqaMaYnsx0wIWWhLGKyjhqkIcxyc12zFNaDGepy0S0otSC1zFaWGOQsjWQ0xIljXzEUmMoyCMYp8x8ljIyCUWOuJmpY0NsYlMzjECxRv6P2YzSxVZYPijWmKUsXR0bMxzRiNSxmWJUpvUYmCM7PBXyYIWKw6N2YhyxbJi1kEWWN1LHrCLyMtkcULH+eAMsSaY8SM87V3TE2WJWBhWYkWB1xjj0hFMlhelcYrZuF2ckXqSk2zSFSqHBIPqU4rGlcgByDi9dCxupY8zCxWL8sRcyOTknyCWzGlrFSsddHfKxN+kX/YBEIruEqbJKmGRhMW5DHDdLBKYcCyeLccXbMKxqsd2WfM8ILc6ji1WKxQXmoH2+jwjo1AVWLhQfVYjDmaqFuywd2Uhbo1Yzy2ApYJyw9OGqsb9TKX8U1iGrFdzxDCkNYgamA1if05jKFmsV1Ys8uMgC2lpG6gteqNOVVR9txyyxLU3vPBG9BRAh1jUaZF5BdehL1S78h1M/yomMN7yKvsG6xoT5Y7j01UCuNHXCN6V1jtqbHWI72h9Y2S4LngrXrSNATevXHDamCkNvSwdg1VCO9Ytt82scvygQ2JHfEDTaGx31jcjo1qEtjkmDX0xWGQnaYktGrev9bHt6ViRQVCeJwkBJjTANU4TCfjYE2JAiF29LGxHn4V9x9vViBhe9f6cZNNi/5I2N2wDnTJXE3txi0FfWMr/ggwVOm4Njk3o10HNLGGgi6x31jC9aY0z+se9Y+yWeoQ9rFo2WPAa8cQiIcfALOKsQIEEBzzOWxdio5IZqlVMVKdotGQrH55bHi82vkq7fV+hF1YcQBa82vknmwdrRx9haqxw0FZ5jLYqXmhtjVrH8CGCENbzO6soEADbHPjB9vpwDfgQZtiG1BtjDdsQPo2hwNtjleYWWw2rM7YwY0fIALbHu2O1sXbYtsYSti/bGh2I+0cXfL7Ri+iFmw6pCo9plxROxAfNaqy22ID5ggpUz6B+jXPasj3bvoaAmRC3RdjcayXlT5uNKM/MJ/NSgYbZlLsbN9PPmVOC+Ly58yfwIDtBgQfX0CgFw7WuGqXzWB4cYEhRR/83bsWvnSZQdfMRegt2Nz+OEDeuxCuDHnAxA0z4DXY3AWEjDeTQEYCrsQXYysYM9jC4px4gHsePzBfmWMotZI+fRH5jdqa8uK9jSgZb2PgrGXY8fi98icKxN2OVlqyMCfgi99i/5elAn4MskANIudgMdxseR1+i0DOIC+JIw2j1AzTIcOBZFAFGRRpJK7VbsTvzb+xSpJf8zljyf5lfYh4aVsUebH15BHzhPfGYGOMVK7HcxW2NgbkEfOVdjWtirElrsa6YrJAUxJQHE3xTqOJNAzqiQDjG2LQInPsaXzPqKGDjP9h2pGyzM7JGXotpjKqwX5wf5nuY+YMA9jK+ZP2O/RHbJQvIQAt37HvgjT2PNFQtQDUC9RCeeFk9Nw4n+xnQxtUjsOLfzvOQGB+4DiX7GT2OgcffYouxBQNqHHoFxHvsALQOoC10UBboONGJNSKBAWbjxGcFegO1SPg47RxWFI6YoNcBIcdW2J3OSjiUHGsOPZivA4q0CndjmsCS2NSoBNuE64qtjiFQWDQ6MDrYv1eLjj/JwuMSH0Z44+2+iNYDmx25FHrJGOPTgbjj6wxwt3/YGh9PxxxkhVbFtXxR3kWvYIoGYCeVQYSkZSt7nA2mmtQN/LxOIlBh15IiSmh8HQFZONRrNaAzJxZskGqKaHxlBudY3Ys125FQbnWIW9nSfdro51iEt58HxOznU4pJxgi1mwZGOHK9g1FO7OZTji5LJOLohm9YUt8PTiRkjKJEP8ANuNtYGYM55TSV0lrLk47iiYz8etyjOIsJr+8MlCPMUMwELONiItdueMBh1N+vZ8HxZBkLHaVyVMUMZBtnC5kg0/NGKyzj6GQPvgKcfM41rA24ogTAFgJzXHrhTQ+lTiCtL9OLkKI+DNnAghYGoptgLDaN04xC6hENqQZfOJSYb0gV5x5uERawzgMeccU453ELoDd4wJvgycRc4/loL4poXFogzgpkpKSWs0IMJUGrinmSiaAp+4akokbYTgKDrlPhdmsyKgfnF66H3VO84hDos1NpAhUxThzrNTSvCFTjSwFrTixcSUwlMBjZhPxTnOIRcWkMOxxDZAhsIztF0jOsAFRs734Xb7ZUEFKus4JK+HpBpGztlAWALw2EVx/LieXFizSFcc42Ju2RjZzpq8uNroA42PTBHVUaEDSACOuPK4nIayyAiGyjSQnoADJAVxMriNXFyuMuKj9wA5IGDgJXFxEBVcZVAcVxRrjhGyDDRogGqqNcEisoUThk2HewJE2O1xcGCQQYBqiAbF/WVLUPrik/Dn1jfrGvWf1InlRUVjoiX3LEJUYBs+9ZOlRwNn/rEpMU+sJsRgWgLanwPCFUcBsD/hSASqRQfrFdqZLkv9Yg3GwIifrHm4v1xWbEYeRFuPjce5MQBsgbjk3HAiUgbPJUctxT+MwGzQNgW1LA2OsQmLRIWSM2kKYFG4lBsO2pK3Fz1mpFEqZHsRbq0/qJNvRk8ohEGAoLJi347F3C9Wo3pbpOZc5lKIv/Folo6nL1aLHkjypLuSNVijne5O6a0Fs4c21ueFGtbdxPNsx3F0Cz+zgB5BDCxzsEpBAVTWcnhSGBomCd3bzm3l0uA4nK1yZ5IZJY6p0PcaGrPOk3KdX3F03VCbBC7dUQKgsZ3Gbpy8NuilRfopdt8nLC+zMaCwnZj+4vt/3HSSXFTgWtHhODCZ5fbc51adgplB4W4ohJ3FVkGrVvXcRJOvXpJsTZXC0TiLRQo2LatQ5B7J2UTvCHa1ouKc87B7gTw8canHROghwoUG922jXExSNDxJicp3GboT6EBYnNCGm6EJPL+JxpSlMVcFK5Hi7nafuNRpAJ4zdx2WIwNL6213cZuhCty+qcx4jjRG99tMbJdxm6FUtK4pyZSjvVasWkqchPG5YAkJqJ4y9C0ni70q8eNPuulARJOHKVCsQqaVxTjRlUfWNWkdnY4eMberpiWlOoHi+RhmeO64YB4ltY57ikMq/uInWNJ2CpOmnj2NLVJ0k8ZH7XuA9ScPPEbxwxNvlRSBE5KxHpYGuQy1l5pbpOqniGdpU5wPThh4vrWZudGHY2eNwwhd+cZOPHA3KQsDm8TqilXTaI2kknayeIvAsR43FObs4LNiraUyTgh4tTxHYR6PGxpRyNn7SETxYicpNZWeMJTnHOeTWWEArk6VcMDbB140lOlHjf9YrZ0JTiZ4hnayni1E6GJxN1lsnTjxYG1Ps4JcM08YHsKNOwvoysRZ/A48UN4urW37jUk43JxFCAl4sLh0KdNvGBeOGTrabAp6SHiok55eOwNtN4urxYmssPH6JyK8RFrRrxxmwuLZ+0js8Qo7ZI2ztJRyCUpxptClrJrQVMsovF8jGJWI3LMLxuIwU0iNeKt2Bm2cbxhjU13HQ3n5zqM1cHxZG0jvEAeRB8dmEPbxyadIEQF/ArTtIwvkYKPjEvGbpVHWkt4xh2KHinHqw+N02Pd4hsIqKdrvHLknY8UF4rVs/VFO3qb21PccRtAtO0Pjt1htEViTpT4xdw+HiIGa3QTHYJV42CagbZ6/hFEWi4WUbTyOlTIEuEreLvhNT4jSSY3jGNpc+M08YrndDx0vjIfHC+Il8awWXp2GkhRwIpVHm8ZHBXKCavjfk5KpD3Wkr4zLxaXjtkS9MhPcTxiPTyH7jafGcrT21gz4hSCQvidPGGQT08c1wotOfUctvG2+Kd8Wt443xdG4WvEhO0p8aOYnZ2r7iho7k+K98a1BAPxLviSKTkePc8ZT43JY1OttE6s63tzj+4rVsNWI3fHR+Np1i142B2WPiudbTZ2nTu946VqD0dXOzScXu8b0fZehd3jG2SS1gKZO74xLcG7lBPHx+LQ8dC7ePxjWASFaKeNV1mVY6l6YI9UXYgZ111i3476w/6dgRE6mH7aD0Sc8RRA9Jg6HkR2Vk3I5vxBUpcNQh6z+fJ340Bh3cjL/R+pSH8b9yAfxJ4E6WAL+NnnmDmOfxNLs2/FO6xOHlWw6fx97EJqa8/W03FESOLoyesZV6PTE4Dm+o9/EcEorA7X72PdoPgcO6BEJ4nISDHYqiDtWpeZ/iS9Y3+KIzqmAGvWpbQDXZX+KTFrH3Z4ihwRmxZoEN5Isf4uwO8h0+KRABJ71qpGYTOf/jB9Zf5HEzmbtXKCGx17SKO3X3+sloqAoKDJsg7VgQoeNqRNTOCX1cAlbtjmtqfdRhwubtVehLxwbAjkSQRo2+splymZ2njG6LD6cXmcv/Hv+IgCVYSfDOS91gx79kW8DpWRNzOzAT8Db6inopG/4sbaAgTYAm/imECSj3L0iU910AmGBGQtHtlRTOK6wBlTztgCqMDbZ2kfI8uAkq7S7aIO7IQJc4tT/Fqy0/Dt5cJzOcTpOg4tuD2YvPINfWlBsciQnIAN7hYE1AJ2VBIMrLoBYpH+MQA2kxREAmPtB0CU+2OAJU9IFSJQBMfFqMMfjOSATt7pGQHhVk4E9IOv7Br8SmvjANs5gHMih59OdoU7WCCWVUHS6qgSg/SFEmICV4E492GT1gJY4jXzbBkE396Vy9gOxWBOtLg4EyCkCQSTe42BJLIvefGGAqRj4dGCoySOuMLEVGNuJuTo3PwUOowLKcRnrgWBaNBIefrUEpckbz8ekyNBO1RiYdTgWH0MDDp9BN+hgNiboJSyIQX4tC15gQ0LCSWUL9agnuo1hhmoLDoWCL8lkzLHWMmroLDYWHqMREzbC1kmkTDSI6/qMfUaxHUsFgN/TGGIR1kjqkvw/Ro4LYkUMaMkjpfRHjRpc/Qs8+J0LP52H2JOnJ6M9GgQt3JpzBM9GI8wfNGXwTAOziwxLRlMLeQW5aNGX6CnXlhszDFIWjQThrJ9HWWCQGjIEJL/JW0Z/C3GFkq/M/eyx1VX57nmpOps4ZRGWgsgp5qfB4FlotL5+o2JFBSIIOA+C0LdqakYi0QmzoymFpULckJrB8ngnOvweOv0LbdGEb8cQluvxeOtujPMRgR1vX7fHQ6Fim/Pc8aITE37zBPvRnG/JI6EcRw36ow32Ce+jFkJxwSQ35gnXOCUp0QUJNYwnBZ8hNuCYptGJBPgsmQnZvxH3q8E/N+XwsPQFmtFHhs6MIwyZb8gRZ7WwnhlW/IEJxITZ4bwhLkeBm/dkJ7h5YZoYhN5CW2/MEJfhDuy5DvzHfqSLIy0ZvYIHwrsKRdvb2KkW7EhlezYi3NUczNO+GtIs1viehK1Og6o9eevvYmRYrv2kxsadPF8oYS+ZpxhOTCSAjN+GhKJuJwxhM3DIe/Tiw/dAT34EB3gRvwAhNR0p10+ymYyzCR1tbHB1AcV1zhqINUUmo+zGRnVCxa8uibCYBdBHydnZANQI7VJqnaIy0WKWNfi59BBXOvRNZpMfPkvKSwf0QiO4UTsJM51gsZ5fGbCcZQZuwLsZYxYpY3UWhhfOsWZrswkZUUi/Fjp1LEsRMN3xbFuFZ7LOEwrGPosHxbryNsRruE0bGQXZCmDrWw4mjOE0dYbH9qsYpizaMO1je8J3UZjLp+f08xJOLX2Uwn8dEzjRk87CNjcUmO0Ym1Te4KzcC8jXsJ4dsUca5ixnmk1gD2Mi4snFYcxA3CauLLT+R0FzkyzhNqSJz2bS6MONU/wi9gkusvom8Js4tAhzgRNAiaAtNXGgES8lZ2MGgiXBLXea9FgJwkL9jc/gMjZCJWF0vP5PoWgieRdaBRz2NDzr0WC8VgDjM6M4ONAJ64RIYuvKg5H+YcZFwnoLQIiYBdZxIxESkJYrpHoib+Ek6BI81gFgMROy/iMyYnskeZUbZSROoibt+RhadIN1vL97TpxgRE7CJLZxKOooRIyMPeLHSJUuNcInayXQUYwIFMWebZJFru3hTFlmlUXGrOMAWFI0C9dph/EcJ6HE1FpuI1AiVotEj+krhSxaAq1CUPRfXc6RCiyx74xhysAh7YL+0F0OIm2LTVwkHMCS6HYgc36ERLNxm52Bc6cP83LKQxl1xp3cEF+hYs0f6ow2bCb7jXN4SUTGpgV2VRCJLjUPGPsYBxak/xEGAWLAGIaS0qglqvkQpN2PHRkOeIg94DPUsZBzVc9xMU8Nwaw8JSMpOPfxkzr55DKTjw0ZOzJB1WDxZ4/FaUk4lg+sBWqWLRJon9RJGiYuPYaJd3VKZCWPQN1uI0EpAUOtPnpoJ0bXjxrRfisAUZTJ2z3aia7w4HWU0T1ExeeJBSAoyTEanUTi55eGxwaKerKkk/htMRq8GWAnvcZVBobG5wJ7ShirIqXhBKeDMQ3Exq4RhnuAQMsigUT+x4v0C14aOQGqeAjI9eGUmTcniwCI3hIdIzJ7kblLqnDEkaeugoreFQxMZnlZkeuqlNJwYkg5HsNEDE7auh0THarDazGiWo0J6J4TcWjZyAihQSJPHRkw9Udon+Mm8wXdE6mJ0GA7x5obh/8FI+Hie/USaYkCT2K3DbZPDqRMSOYmKVkXHvzEyLUOU8IRiX1TBiRNPTQUZvUkYk7T2hxsXw2LWQ9ccjYgDnliWmsCaAQvhoLJcxJxIMSTcjxjM8LolJJlY1m+sUVs8fQMp7UxMTEgdPXWJA/DXZ6hblBBFdElWJD0TugS5yC6iSIyJmoUy5LYnCpAUEbk4AKeLMT1RoZTxhievw4WJyN1fYn0jW1ibhPBhQbvVpYlP3S4tkrEqyeP0SeYn25gwnl7EgUEtMSRdyD+G8/KzPYgUdEQFOzfTx4ZI/wmaJDN0zyg5+lTic1PDGJ2jVw4lLV3vmHHE8GJ6DJgoouIBlngTEiS8x0TRYn2GhRaJ7EyWJhBCzok7T0m3Ok0bkGcc8kdz7NQ9iRxPekEKAj6DK4z3lQH0md+QtcTQ4m7JnFiTdPRWJFfQuYluxNIak29f6e7tg2/CZxNRruVuaRYa8TWbqqxOEiIXExJ6VsSDgQ7RPNiRXEoye1MSQliQzzriQh4I2eeG5C+qDZHhngfElWYlsSd4mF9XbiSLdcVOlfUzYkrxP38FfE/6JSDJq4mBa0Jns3JDZSd8SOJ5nxN6iX3dBDCui07x5gJP2idE3S+JaMTcJ6FJFMEf5+NOJssSJfBxdk5nm4yWpMtXZkWpezRD9MiwcmejcTdsEoJKLiXXErWyEs8q4mURAASbdXT5qvcBoGp4JNbmGCZXGencTwhFUGVxngjEnJowYj6EkJxMREfrPOuJTCTWbpVxOOqN+4lx6lCTJfT2COJiZi1fWJMJIChH5fh7iWIk0uUlsShElMBGViSdEgqIS8SBp6QJJcxPfEsRJ2iSB4l1xLfmGc7NRJbQiV1a4T2USfmOJRJhsSLEnyJMgSeagBBw0xJxU69kTTnh9EiYRQMSYJ7iJzeiSLrAl0WJt8jRxYC6iZQkkM48utjEmF1BtyjtPAJJzj4Ip7+MkLkengZE4E/BN/E06FiSaV9LuRPVjzHDAbV7nvEkt+Q0ei5qhd+NxQQS+NJJ5QhLKg3CMKfuPPHJJKLcQRHSDVZ0FzYIge9QI5Bzy2GSSRYsYpJBSSMkkeoEaGtkk3fx+CMhHw4ND26pisGjOVaBhAw9JKREV/om+ejKlmRGGZB/nmtQAy6V2g4HLG00baiAqMQxAyT6RHzdQWSSOdH52Mi8W9jciOCOCAvdZJl68ifw5oGWSZiTG/qDNkRkmYk04vvtZY5JkNNABzgnCt6q16G+eWBNbSE7SXWsiyLGURL1oSF6QJAVES8kyDAphUhdpuAjK+GxRIUgndM5eo3z1cvDqIrZWyC9pfy+kNOSURZXpJoTpxF5l4XXXqhlI8yXfBQLpYjVu4kik0jeuKkh+w4vnAlqx1UCyWKSUxFdnxUXhbTaPBiRjJEAtvRouodwAxeyngVREUpNRSWmBbshWKTqfChXQrETVJQlJ4KTbOrddX2SbnTEMyXjRkUks4E5lAikgoICKSzzJ/KxCAOy4+Fg6oDQQC5Z0z6NlcF0cD7cZtGbXDL2M0NJPRU2iC9hYQP4VuNo1VJw2iqxxypKW0UE4og4PQ069FWjjmXDNoqsc6B5A9FWjjNSbqk7VJkY5y9FGpJtSY3o+0cZQ09lxVjjj8BPo2Mc1P08XTr5nB0ZKktVJLKD3UmI/XtSdvPRMcVI52hqXA2jAC6OS1JLei7UlFDTDSX1EWVJgg1LtFljkVSb6khfRpd9ilKljk60Sy0diBeqSQ0nZpOtSQY4FAsmaTjUnN31LQK3fHOxNn1BIGbQ3qNq79b4Wt+jfzIi/V/zFVAkFGXJ8v6xNpP33FaMeesEnl0FpE6K9+mjSTL0Vg4U/rgjHQWlTo7XYEhM0arubH1+tHmYyB/aT0hxXOE2/Jl6HtJ7mgvvwtK1x0YX9FbOLSsWWSF/Vcgbwtadqxq4pIFaLS6kJ79RZMOuirdYNpO6OrFAkZkjSNG0kq6KQiirsa9JB0DYWSGDmuGkFAzpkC7VZfqJQL9aLOkppkBujtWgm/ViFibomn4fcww0i5QNjaE4MW36dUDf0ml/UcoSLo5ERGf1cnAW6O30E0OL3o3UCcyDUskT2O/uGQxYGTtdiTjAUMYGRS5GBbQf0lLhyPSdotE9JtstokbPpIvSekANT4raSVdGMxH/8DRkh9JC2tPhwUZIJ0Zy46P6JGSb4oLDl27NhkwSWx9tuMmDpNwyS46djJGGTbnD2DmQyREYydaq/0iwYAGNgyX+ksdJzC8yMkG7ADUONA1DJFiMBPKEpFbdjZwfDJOOM6Yolu16RhbvBaBgFILEawgx0MbUgJocX71rDGyZKgyRBkyTJ9GTBly0ZJVHMauddJRytDBwmZIFilxk+t4gaR5oFhQMgmBP9dMmumS2Mk5DnUyfNFQdBYmSr0LsxTNEND2UdJ+kD6okvRAr4BQLcYWdP8aBaUlBZ/gwLY4Wn7FjoiXdlSFqYAjQ60wskbjcC25OkL/eoWYwTxDZWIiEFh0LfLJCOJOBay/ykFo4dJP+c5UyQkt0FLWsCdfBOm/MlgnjCwSaC4LDoW+v80jp6CxafMziHYJOf8hjqmC3yTub/CwWLQTj0j2/wYFhAVRShe/8Hjo+rDd/u4SK4WdwThE6z0xtxE8EwO4eJ1fBZaeHj/gELck6Yf9/opfnkxCU1kkIWZoSTGHB/2xxOCLTExoO0EhawxGkjN7/SEJ3WSj3jpnm5OkNkvLCqIsKvDWHDyFq9k3I6Hh1ljpl/xqFv8LaI4Ngtusm1/0RFo/xStg/AtYhbApy2sDNbOrJypZu/61nn+yYjkhPEtQs+/59C2n5IP/IYWTITuoYOC2RyRP/akJj/Ff/5I5L6yUCNMo63WSr/53CwpyUtkoE6XITL9xbCzfetOOAnJa0cf+Rb/yGFulkw/+DOSZsmn/xpyRwLa4WfnhKcnXW3uFgsxG7JRwThhZ44lAAUSdbbJj/9j/YfBMGOMTk1HJQOTP/5jHWBFgAAoZQHOIrslNpGayR9kiABXJ1qcnRi0JybYhZnJ2Qs1VGlWNBQZCxQicIYTm6C4sS9CSmEpqxLE5AwnF2Etyb6EiNRvVZqWJEi1hYtEJCMJHqiQwossW5FvJOMccrIt4wndEPoAX7k4PJoTg/ck2nTtyVYoTgBQosCwk6Y14AcWE66kAgDztD7sKsnFqxOUWVYSm9wPvyVFqWEk+GPYjk1Ho3CqoHvMCS6/fhh5iAXSrUDb9DKJqDCoeSJnVSibMYlMWwkSYUhrbT/FhPEYLiQ50x1R8XVduAlid8WmOIqzrHhI8ocH9ZsJWxj1ESCXRSfBaLS8WOqQftqt5MmyauQpBYqUSAuId5NXCSYwqP6kF88IlCpBcDk+qLsJu1sPRaAXR3yfoiQcJefN1zqw/hsYdaYe8WjGE0gF9zgNmHvksCEYE4b8lxIW0iRttMVJna4qli3uCLYCmuFrR0S11eav5NlyIno2xw0wVf8nF6OUSFGFd/Ja9Af8nKbxD0UdYRoSWzYv8lO8Wd1hAUg0BlaSTH4Y3jayGzxC+IjQx+rLMBVm2PzgCTIe+06LJSVhv8DaAkUSi0IMClxRWA5qwdQX8J1A2oh23iu4oL+X0BR0RrKyR5hx6EdEHqKbMRDEyUHSR9CGA+Iy2zjZRJkVgZvF0/do85XtXoilOJoiH5EJOol1QiCmJiUWhBIUvAp5lYpKxYXVH2lgU33S36ZSwGYY0i0osYekGOG03QFRGSbAdNgoQpdIiF8CwzkYKWeybvaiGMuClOBlqcWYUpIir0RKnFGFL4KUOwRQpFIl9CnqWLwKfBzCgpMhSmYj4iQjCMIUgsBw6191Q2FNUKT1zMrSFhTHwYqRCnAdwU6MBYRTsCkGFLyiLOqHQppLi/CmvBCiMl2A6CILYDkimaFLcKYXtKIynTi9Ck1P2PqCk4uwpYlYpIjS9HmiFwlTpIffwUGhTb11fOUU5j+bWRQD5iVlIKfsJamKpbNcCmeFMyKUnUQgprhSXLDeFMaKdBEWcIgv4ZwEqRDiKRUUn/aURTlCmR3kIhmMUkMi+RSUrpDFOCKTvPEg6iRSDbgaFI4KSk6c/wsWTcbZG6iULvt4QrSdqBc4BgxFhjLyDLyKtXh/5iRVBhyMnOLAk1hRpQZ/RCg6M5pXVAUnR9pykDF1dP3QFo80HxK5wZinOPGzIT4ogKxr3CqHi+KbNsHcEnU9uIrvFI/qCEcbiK7xIZB6cZGs2LcUwt0N7wLimf9iDFNfvUOcdxRfB7FdGhKeAOe10DzAXDw7FI/8PqDY4p33g7inbpBuKVQ9HN0WxTl0j0PRKLMmoWQu3nhvim0ilbaD6EGkpAJTfilZwBHeO8UvREq+wZwrPFLVFH8EAkphbpvEQ8lP7aEUPdkpYAUTHpjumZKfN4O1OJeYiYzHHm16AJpe4pAE8svBYNDNzGSUvTwkpTOh5ElLW8KKUs4pSJTAfCClKUqOcU0OcAapg1RICCfPnWFfdUHIMLinp2D8iKqDbGQLJSrSl9D2FKdREde68oN+SmABRQIlyU69oVAUwMhmukdKbpEfEIGrgCLgVlxWPNRpI4pFxS87qnexNKTyUmIQoZTQ5wxCBtKa5FByI05wBq5gBVnehGESMpXpTniiT5ldKWt4C3A+LpfSmwzl80geYJKegEQRSgdWQNKdv5UspqoNKuheeH9ujV7TwgNE9C/KVlKjBPiUvgeJg84SmhznOWG6A2EUjE9C/IGFA1cFiUqPYW39zSnvaDiPB2IWkp+Io/C6ijn7zIZ8di+U5TKSnLmD1CGOUpkpcopl0hrgnNKRqU3spKxQAyk6lIn8kiUMspO5TC/I6lFpBpVkNbwobpFnF2oEXCoX5LYoDHoqSmLlPRunWUmcpnIQs+gJFG+WPmUxW6JFcKB6jlPvKaN6WEUDZTcmCKSgY9HN8UI8uTBxJQNunbKZnOI8peJSLikPMmXKdTwUOcSdw+3JQVPgqWSUNspB5SGRhGlAMHvOQIuc/10FCKAlMeyKsOXZxO4JiJ4zxFOKTa4cspZGR/Sn7lM9KVWkZqAqoNqKk0pGsKPuUuCpwhFXkgGuHAqeskZlqfbkZB7MVI4qT89H8pQFTMiJ8VnPKQOUvIincwv3IyD0ARMURVkoTINfSlZuBCKNOcTUaeOA5Knle3lKbIXPrGIYCLylKFxw/uJUvYp4PIhKmxEQtKbIRBSMhFTyKlPxE4qax0a4pfKRDroRV00qefdAOE9zhpzgZdD1CB64N1Mx5TFKkbxDqBgeCWkUyZTc4ieVLFgSOUqSp3pTNoCQlIbKe/OBypkJSeyknYxPctxU44ptrgDig2uHYqUHPUCpMVTk5xnWXiqRFU0I8I21GKkhVJcPGdtcKpeFTYcgMlDFgeKUu26sxQG3S3lLLbqxUM5gvINLymOgGxKNnmDcph21aPIxlOEIq50aKphlTWql8VJ+KSeUpKp55SVSkrT3FJA1UhcplVSUKkyVNU/j2qIYiGlTAyluERX6DpUkqpxlBkqkTlNX2CRIYGM3lSyIp3PUoqbSKW0pbUTEyjHlI/hDNUse6xVTxqnGkEdAL0UcM+6qj1db8KwcyCouIT6lYhrqkzgFqAGBA+6p+IBPmTYLjLHI2QNVx+S1QFDexGmXG/gOlcLahx5yyNn/Ad+mfDAX8g3qmJjg+qWBA3Qa9C4gamZ9Ghqb0RT76lwMsCSoLjBqf/OCGpqNSvbFE+hBANPOBMgkJCYamfVMCIbUwbLkgNSGGw0RCjABjUtWxzLwoeYegCx+ljU8mpiNTjbFp6J0wDTU7bRa4h7URgQKdJCTU8ZgnZAWan/gM5qbzU6VJnRgBamU1PbaBxmYWpLy4xak3zlhqSLUjAsf2kpamSNnpdsLUsNJitSEam01IzSXIuCmpYaSkdTi1OOUNrU+WpeA9v0hc1NmqIbUpWpjNTfvizch1qXfoPWpONTyB6igJtqRmE36p0tSw0nBt3xqeX0GXIqtS8B4u1I9qbNUO2pmtSzanJNgBqVIuW6pBEBnqnSgCNsaHo4Sgc4ojamtMCjqUHU5HeG0NVqpykFpuCseR/cZ8Rk6m/QlAnr14XW4sM4l9xyLUC1kQFJdYok0leorb0kchb8YkSVZc9X7goLM8B9uJNo4eUpt4V1IqmmAkZIgJdTeRyrEGbqd00ShyZdTGZza6HGsoJKCMSGhdwUZ11N2iCXcPAor0lwSimDTXoOPUydcQEDLga9sxuaEqkvtcDJ4FBi+pJhOEKKCepiJw16nT1JXqeicCvo69TreK71K3qYJ7Ndcma55hgA3BHYFQ+e4waDhwiCJrlPqQi6ZTYIggMBBX1OpIOuuBNJd9SCpC1hNk0JMNcGSL9SihobDBdBlZjdfQX9SIKEhWxewiKuLc2aMIA1SShFFXKd7HApZwQBVwxFXTZm+qaBpO5Z9uRQNOHoBl4L3SvGpN6xzHFu0lg0q5wrERMGlwNPVXCNOVBp/K5iGkdFMq1k5sfVcDj8v+AebF3+ks/I5Uo2wLVzQHC9cUMSagWVQ4E2DFc3t2I85KkcKDFGKom7B8xHxkDZAFASUfa8NKKyIxVJrYS24ZmLFcy4FgbkAao4jSwxbQbRN/Ao08n2SjSxGlcNJJ9nI0zhpzVByfY6+ziHKbI5lYX7jbfx+EiPcvutEkcCzjLHDhrGZ9so0jRpqqUpNrSNOaoNoLTxyl+58gDFAB59uRk1nySYtn1rSjlO8vxGcNY3jS4hz0tAdSA2tGH2kf5SoAMrCcad39C2YD2A2favDj6ccXASN6PDSUmRBrH+2vELQJpG3kY87HrTpHIN5SIg4awykAkjnDUMxWDkYJvs0xwYEmdDjr7Efw+GQTGlWNJEWEYOZzmiTS08jyNNsaUEXDnwTTTHGmZCzsRHU0wdIKb1hCRtNIkaf77UAoDjT+mlPcBF2IU09ngE6xBGnaNIkaWwxZP6KcwZGlLgRTWla0appiftziRLNLrUKY0jP2Af4pmnua1T9pH+PhpqMZGMCzC2SaRkkCYWzjSxvJlQH7JMX7d3YCjTTmlRNP18riAGYWvTSLGluNLr9s9UIZpSt5G/ZS7G2aRxtexpzzS/I4d+0T2I4RMbagm0dwiJ0LsINFHcv2QjTgmmbC25qDkMDFI1SQKQj2NOiaUyMZYWlyN4mmz30eFv39c5pHzTXhaO7EXLJtCPyO6/sZfo5NIGSFX7XppYzSXnJ6bU9+kcqUd4ZN4iWmR/nWcIY0/kIpa0umkos0N8Vi0+5pOLSS/p7NJuaQ/7UFpq6pnObRJPf9oSLfeGX/sj4ZYB1n8Z7uZ+GCW1NdyitPKIcg+CkW98NAA6z+nPhvK0q8Y0e4P4aZbUFDN/DdV4wCMQ8n1DTS2rq0nkW3YwMEblELPMIKLTTG0R5Cwk7dyTyWIqFPJieho8kyi3gVOgjVPcmCNhFQdEJoDl0Qn7BBOCmMRJZTUxNSjJAo/Cw6RxlI3g8r00p5GobSvSh4ozMUoLIEs0UbT7dg7/XtROLtLKigjSjOJfbRpQJvkq5GxFFYiS8Ix37pvsJJp4bSxJSrNP0xDrtXrYxWSJt5ptNnAIM0xNp/4srFKDNLhRhLRFNpubTfbb15DjaTVw1OYObSlnSG3VQIFI0kNpHropGl5I3J9ogKdHsSKNADZCByYRCO0l9RMes6RzhtKnabn4VtptMdj/bztOxeq00gJGuUEJNyAozn7OkHSHJhSM+XT2BO3aTj4NpG2F1wMDTfWcRqsHZdpa+lVDSbBwpivr9IZGUtIhdRvNNvaaY0/MWc7TL2nh3XcLLCjdBxjbUhfrI7QDadmLN5pM7Tn2mVNN7aWjtC9p8yNidohByTKL+0iu6pxQxkaHzV9+k3KKDpGWFPhjztI00h2k4DplWsb2krI0H1rHKdkcdSNb9a4vCMeE0jNz++O0mHiHtJvOkOsJJp+Y5Vg4bYS1+q+089YjXg0Om5/VKCUh0sRGj7SoNoIdJnaVrMZDp9bSOwi9NN7aZyJD9pqToNAmFygSRlh06zW3somUbk+B2aUO0oDpHOoco6WX2DaUB8IfuZYQJOkmI2rmuDeVX6xbSSDblEEeRk209VYkbTOOmhyFaaVp028Wi7TTkbqdLS0MP9A5GynTxuR1/SBRvJ0p8WmHTmUa50h/aau0nQJkbSeOlahEaaTO0rzpVQ5e2mc+NeHP50ueUmSMxOl4bQWcj4jT8i2AxROkeIxXWIuqB9pXSM4DZQani6fYjQoJUXTjXgbcHrmmF0zpp5nTt9ZByjMHCZ0vjCq/N59g+dJsUFUOAdpsvkfdgztN6LK25alGnkd7GlVdOdhIF0sDpdLSy2lgoxxaWNiaLpp38V1jVdMRRkdBOqJSE5q2hPhD/yZlwUgYgBSEAajdJMVMN0gugPLAxum3/Rm6QgU/+0g3TQCmY1NbxEZvOfR1Mh5ulDdMQKbE4tpabTjUCl2RXWCHC0rkyShTobRW008KXIU1reZ3TuogAVkYyFY/UQpboDcBKYhEEKf2DKTI/j8GCnp7EoyCE/TgpW29PoiXJRYKSGAkAYfT93un55lUnEk/Z7pV3FiBizg3u6awdf/oo4NiClUhFh6TmDfApl3TNgKKFIyPl1vGlpN+01Ckqg0R6V0U4xE73h7ZFdFNqRN4MK7pCEQxCnP5IN7A6uF/UMJ4qemVLRW6ZKecg0teixXg+kjp6TLUmC8KBpsHi41KjvmnxNnpFbxk6IMbzFeBdeDSYxei+emdVAXLrMuAu+zS1eekIZV1VE1oyZc3PTJZxI1Jl6dT0rnpFd9EDz/gOV6az0iXpzbQK+BgQM16br04ZcBd8Den09J9JML0rXskbJICmwjy16Cz0qXpWohTekEj2jsXRA2OxaaS0PRBTnIND3iBnpD+p6TxpsmwLG70vRsvECs7H8QNzsUgUyfENFlvPZkzH69qFEOr2EfTgxYIzWj6YaQcSpGnYpvYPZBi9gjNN72D2REvYvGi+9t8yBXCXU4torfMiy9kj6Uf6BfTZtg0REK9lSyUQ8ZTtTPzfMkz6faHMfg3zJU+mDRGO9t9kGxo3R5BcDh9P4YG17UKIc3tJmTkuKT6SMmIlksfSo+nHez+ZMN7OPpI/TKkgRhH76RvWFbw3h4cJLI6DForX05SwiMQPvC59I7sjLEVfplfSCuyjYC5ZOV7JvpHfSI3BSz2xbtSkTfpp3t9+kn9Im8MMeMPpF/TxOIKhJoqoBsGJGrYQh5YtRQmzhN7MvpJMVZWQfsQdCfIlT/pstQIsLnRV/6Z6qbvpN0VP+k8HnNMgP0n3U4x5v+Lee0f6f6EYfpMAy7jYQzTEKjP0itIioRgBkL9MT3H30hG+K/SD4iVHhlvjv03AZR/ThkJRA09bPuqIvpuXsT75X9PY4uTMC3OrwRxZSzOBVSLAMs1ooYpi+mQDPePJPBEgZZBZljz4DOQbAJ2ePwGxTsXQfYHaNhkIraUoicahFDj17yCibSXh4499pBHlXEGX9Av+OrQigYGCADkETkIoiesCcyhHqDIJ4cUI68e35stBHY2RQTtHiKnh5WMpqQ6Gy1dIajClwjPDeeHA2QLTokI8WBDpsRBnOuEgto3wj8egAZBLaHSH/EezAfo25rhgJGT+G8GdIMzKy4Rs3zTV2ScGUUIxXh9MDOUAq8LIEduEsQZmvDPJYgEHdNlvwrNwzKwbeG6QkHsmVEeU2UQiZsbymzCEdhPLRO7/DTUYq4HdNuuCdGyjtANeE6DLGBvqbCoZfgzfDYtnGztlVEP3hiPDfKjym06ETK4UNsvhsRBlvPFsGfgIsSeNQyJeFqDP0qPKbcIZicCHsDWmyaER60IJAqgzEeEMjCkwKSbPhspDkihl4CNt4fs8bzM3ptrTjzS09gFObLfhTDltzbD8MqqOzwSo2DAj57YpDJIti4MzOBtgyMhFmiAJSu3w4oRak8Oza88KCns4MjwZnllJBnQ8L2Gc8ONwZMvDwhlWw0gtnEMpGWyvgqhnbDM7wutQm0239suyCgWzSGa27XUIBvCgRkNDI2NkVkXKRGSR/TZFliqnosMnXh/rpAZ6ZDPQEcIg7c2HoJVpGt+HFNhYIrqe5kDn+EwCNYQdubCARmIy1hklDIjlmiM9Ph/ssxlAtm1uGa6WB02dQylp6jDPAEVTwxGevwz2nA4O118EUIovhmCCORklYTxGSDPSIZcgjIRlIuG74EyM7YZT+BEhkYjNG+PKbBEZERI2Nzbm2kEbTLEkZYgjUFayTCFNsIIrR2mwzELbPDKpGYcMpnhIM86RnLCNgQS6bS4ZLIzszamjMIQfcMwXh3IyihHvDOakjyMxcE5I4a1bdGzaZObLdpwrIz5BEqjMZGUoIsvh9iCOzY5CPCQXz4pQZ7iCLhm3DKq2N0MmMZX/iDeEmCOTTDJubc2goyW5ayDNiEVEInmeg6RzmoFDN7lka4awRNIyrjxIjNQttMMnvAsQzbhnH3CPNvMMuWe1wzYhGUjIreB2UUIRZIzGxl+jKyGXz0kEZPQzT0aKyMSEa2M20ZnQiLXg5jOqTLcM6PMXct6RkLvHBGXMMrgsj8taECbCLDGeRsJ4ZA4zQBCMm0uGcuMqc2S4z8aChjOmGXzQL0ZtwzqBJR+N7GfuM2qq/QjUPCLjOmGfbPIoRA4y18Tj0PGEeSOLdM09DbxkvII+wMWbZUZXXRXhnzCL6lDEKEhWvYzNhg7px/Gc+M8cZXXRAOA7CMl2EK07MgklhDhFtyNz8lZbd589STfdHdIEgmRorGyyXih7hGr+NMXBBMl4RbciedowTJ4kHBMueebVAUJl/CLpQfjMX4R7SSOGzdMBwmURM3vRJ4xARFkTIbCQKgxC6CIj6xHDzXA7KSIyJGQ7Z9kweiMNRm3mY62OYjKX5/JDlEXxMyKyK7ZzRHRiN4moVbZsR4kzSrZ8iKfmiJMrxKZIjNUFq5ibEWJMh04tVtwxGtpAO3IWedSZ/oVBRG54WhRqr6Qc87zFwUaaTCmOoNwEPGSIFBJlMSCIXl4EOURoNt4FE1TCmOuqI5BRUuAtRGXynQUYIINMRAnJsFGaTNEma/IpSZvkzi3bXuHOts2I9KRWJ02RFaLUo8W1bG0RQ7xjyRRiLUUTXYLc8RkzC4FZPiv9NKIqEZBuY1zztbzcQRA8Z2YcUysVYsMPE0nlM23GK8lsxEWFC0XgVM45MnxIAPbNXFOKHGIvlWisgkxHxiPFVoL6NMRplAYPaVlDLEbEUcqZcngtRF2TIjlj1M2s8xYjOLr9KFymV2IpFW4CYobZtiMJVrlXB3E0UyapnfWzmmRVM80RBojn0HI21yYaKk98YMGY9eg6HF/GFtMmHC4P1LFDIPj2maP2D3g9SkTpn233aUvtM06Zf2E04T+1LQZHYxBJUi15n9Q4NDU9s9MnaZ8cFjpnvTJo9r4ScHCatTMSRfXhiwGp7C68eHVrplHXkemSt0/6ZN153ply5RZeNtMlTebPTIZlA3j+mb9eea8BNT3xiwzMrgNDMizQb2UgbwHTK+qWaSDGZ50zfxjAzLfILRAgpSRUJ6IHPyTgNEARB6ZV9JxkBgzLpmYDeGHChmEaZlIzP30S3fILeR+iBIE7dIfIgW3K/klhc5YqjMDJZJ0lQX6LmgFLy2Og1it9YMX0jo8P75x5A66LjxZX631h6ajuJkXvs1wTJoRgJH7G2XlbOOwlBi4T34lZmnRTLLLvfOWZp3RFNxW/SlmQHyQoG9UUxZlkXgFmfXFIWZ+IwOoob2Nq4I3UCaKQIU7Zk0tJcFLbM4q8q3AmErlakESm3kaWZc4p5/p1XlH5IbMssubeRlZmOPAofhHMg2ZxVBH4q1cFgribMgW+VsUE5n33xlmTYlNXg4l4JZmCzI9wJ+3bOZ7syNRgbRVJwKPSMHQDszHNDe/WMvIPhQzo1jRyx7OzKEvLI8LPObmp+Zl/pidzs7Mu1SUczmYpq8A8GCXFcjcFV4fZnwJXKYuUlNvIacyO5l6zKDlPLMluZBNF7FyxzPtaMZAAQZZAt2GkL3nPbuQLdP+lncBGms/087lYLFH2K7dJGnjtz47po0gX+Wv9BBYi/33mTopeoWO8yMfasTVF/pnlOX+YncjGlN/wDWPk05/+s/9LNAl/3PbnY0j3+R8z7BYud1s7tYLVn+gjRimnu+xZtBpNFQWATTlJqbzNSaaE03zudgsZfaDTVd/tG2BX25/8b/4PC2vWkvMh/+NTSA/5j3QbWhU0xDu+vtcWmT/wKmte9E32/k0j1rRCxiuDl3GQWaTTqO72+yZ/jO3VVKWf86Fki+0I7jkLdEwhf8v5kDNM1/pZ3IP25f9CFnhfTD9spNLhZMzSYAFIInvOF9GJv+1ms2XIPzOz9pNNL+ZmzTh26V+0Oaf3/dBZYXSh/7orxUWRp3Yn2xG0KayydypaTIs3+Z08Z5BTvzM+aQIszRZ4/sFO76LOH9sf/ABZZN4EgEgLJsWQb/W3+OLSAWnQLIuFi37JBZ8Czoo45sCumlZNB4WV/tlJrD/ws2Mv7WDuf2tPhZX2gS7t103Zp3/8Mo5dCxIWaZtUJZQM1927RRyfmZP/FKatm0qFk7zN2JOX/LhZILSUlkdvwuqYTUnLA0woUAEaaD/vHgA13JGItn7zYAJlaXfeZru/qi1gKxbWG7sq09ruI3deIAMi3jUkwA5kWFCwaAEdLLTybh7ZNSPSz44LJqVW7vq0zcMR1JqyC79Blmta0xPJKa8Swko4IO7mjg3B8sosRZpiAOrCbmvSQB3rTYREqE1i2EYAh7u2yzCe65tKychfRUAeyWw6xDL8m+7k1sdkBG/cM9hmALH7hnsSwB+wCM9iouSl7jLRcQUD3c03QZALeWYZ8aAexwCauF+OXl8FP3Grh3spjAF7bRhuhAPPEBTY96f5vLM1VtCAq5ZmeUaxaVzSQQO4Hd3W0PQXu6B61OioAPTHY0+JEgHl3UuuIyAnD4k7TXUh/0WOWQjsIwBqKzKkxHAMRWYbdVDK8gpUVnUrMvaBisreAYSVaVkjvlXuMCs9AJNXR4QEPLNruuIKOfutaxxMQOLW8Dn/ibQBbyz1FBkXl5WdLSevk5gDKqAqKVU6F4AvbaTV1C+7nLKzSFZeYlZ9tIbAFvLPQaUL0JVZHCk7+6wrIOoBkA85ZA7wme5L9zLCE8sw1Zdikx6KqrN58Wh0DFZ08zQrwmrLtWbu0VFZiqAz+6jQh2aaOCBjofIC+MLfiAWASgPeeZyswx0SlEWzho0mQNZdhA6igut0xqIL6INYYMNouTlzAfQkigcNZIayDPwJrLRhtuI33093FE1lrRFt9Em5AMUaayXyiroEzWdQZRmSW6pg1lqREvgGeWC2GyT5bTibYD8ibdDa8RgSTX6CilD3uD/EEyuNhRyIg91GtLPIINuGEayFWr/oBd4NnDJLEwlxtwh+FDaBOjOLR8r0IwYaBIAFuOOs4cgMazwJGTxCjWc0UfjWNzhhLgMBCbWQ8XdqSnayjoRgwwm5IuRA0eYaydoaJch3LDpyfQinMNsJEhnHZqCOswNYhpFVfQOpDBhkXQZ3wDay71lTw1mkRes8IiqsMq1knrKNGKrDOiRUZwGVrqlDkIB2s3+Ip25ANmlSRjpLOsr6GfFF8jTZrKXhm+ReaSrazS1nzSW3QE2Qe9Z0siRmbVBCvWT2s/BIukM54Y9rOlXNms554M2ZTbiRTjkSPHDX7ksIZoKKa4EQ2b7ESjZssM4NlAxFo2W3DI9Zu04+1k1K1r/Cq1GccuA5qNksbLXWYWsoGInDSqNlow0HWVdOd9Zqaye6iJONOhNxs0tmAqk8YbNrOk2QP4QjZYjwIYiLli42cTDdp8pbNWNnrrNjWQWzYDZimzsqLoFKKcbJsjdZ2IYJNnBwwW1gzcLmS36zD1nxyI2cY2ss9ZQM4i/RwlG9ai7cATZ2xQP7iPrNc2bBszbCt04W6RrQg/WZdOW9ZiRQSNaGxEs2ZmiUDZvsRQBDzdGKeOFsrGIKmz+1mQbOq7vks16SXz5oXxkOghfAeoUF8erScwlslRdXPAgFF8SL4/nypbJ9yfdgoXm+WzfnwnDzK2Wq0yl8QvNN7Q/yiVwMoiUNwarxyXzFbPtanS+Zh4sKRgFRtbJayOyLEZZ3AhUzg1rLVeDUUKZZWVo+AHJ5LzyaN3WcMUr4s8DpdLiquIAgBpl798cGbLJmGsNZcQwlXSWh7FtRW2bcjLr43bUpNyqwDW2dpYjbZ7tg9tla7mC8IB1DAC7VgX2l/o0itkbqXDIlTS9ujqdVjqI28KXYqVku8nVxCi2ftslaZydQa1lEozsjD+1DOoukMZfq/bOu2UluEtZ8iNPtlDYVU2VsyHTq1ayaNAB/nu2SYAp0ksOzROmnbMx2r06U9ZKiNYrY5iHR2YnuaMRFRocNmidORoBEA/wUl3Fkdm47OJ2ZtCfbZCkzJzgLk1SRofQJ9YmPESdm07I3mqBoUoI+exttl/bMrMr+OUnZsVt8JipkFE6cWYknmAOz+dl07MZZkJEXDpKJFoJbzcwzWe4jJqZ4q5WVoy/V6yNr3cVcYuy1tlvBTbyZllMuI+2yeB5tczjsHzssHZ77VseaibP23pFbd/iV6RKdk87JwXlZsibeBuzRLIewi12dDslJ0URRntkMpBMAYylLtZonSFcCsXXo0l34NlGX4RwJb0aQ98MsjfVEkuzbdmXbPfpvTs3e02OzfIymrhVQmbsk7ZZIiKelE2FoAgF9HyU8CBneZs9LaTLzzZpo01YueYrdIpBFnsq4e81U3eYZ7LHrFbzKQaSvNw6lQFP2EUXsyIoqeyTeZ57NL2ZLzYwaxVog+YZ7P14mXs7PZNeydeZt7NY/LXs4wam1J5eb+1O+vKHzZvZTH0UR4Npj72RiPCfZmH0e9mbUhn2S0NFvZ0TiLOCppIYgdlKIRAYvNf5Jd7JvkjJ+NXm3H5WIGS8xLSctgMtJMOiC15w6K1lP7iePmI99HZmX7IPscNFXk03n1LR5a0Of0Tnzdom430W+YlCBlHtvzNN8UX0DkkUmji+p/FDWZNfNe7Gajy/2Vm+eKImQIoCHyUhy+mIlYaKikDkBbSJDv2R19Hexc7V+LToC3JGqEifQxs313Ewd+DQOdr1JA5WBy5iQdfVv2ayuNfmH+zAx7THxNlNvzBz02Bz7+acwAP5s4gQaBD+zvop39nUEkwcz0euq4wjGBfUxJiAogbYFcykkw4HKoOZ6IhqB/+yryaH7ErNFALaVIPgIBDliOIkpt8fKIxhX0EDkcHLH5lgcniI0JoE+Z5JkYOQociXwiXBHyTwCxgfnh1SaBDhYp/q/r0MObXzTUeOhy4BYWOLc9Awcn/mtDiRQR7mlnbp/zLc6MDiP+Yt/Tv7HbWWdumsypDn38y+VNYcsQ5SRjgDkpGNYaeoUI806ER+iaOINQ4WQ0R6BP0DUuS4c2dMe3wG4OVPRKjHpINiOa1gN66vcD9G5sZ0hun8grT8rux7zHaAnLUXkc3xBqRyk9aIwJiOeWoj/4Axj0YFmVVNFB+VQMsOXtF66uyHVMZIg5muLa95jExHNs/CvsZYx2gJOjn1MHWMS0clrkpkA6Q7qIKB/HnvZkxe80b2QIpNVrv0g7GuCGV7TFMVAJrhbgf8xosCajn1f0lgcKCO9RrFjLEGpckZShbdehBWTcjZzhmLuqCPXJo5q4cokHnclOOVKHUYEtPdvui4WIaObZ+L1wyJiXATS1yiOUcTUGBOxzQujYmJ6OQBo8Y51sD9kq9FS7SFMYjo5r6jATnPhwKOZV+aJoVIMIjkHFQV2GHAkEELBUq9iAk2BOQCc8kxKxyWCo/1C2QWF+Uo56cDvjkXcmDMX8cpIq8DR1Q7VHNiKqCc/BBEDdFdBMWPDgSCVIT+NcCb2SXh3YjidUCuuh7QNiaDwO40W0czuBXX5TdjpfneOWm3UgGtMDAa51NBMsY3ArH8VHNnTHswMobkMc2eB8cDJ75iNDajtscvk5TljqTnd11SdLUgj4EZyjLA5hwPVObA/I45ypzk65knPv8DICWeuYfg44EO1xLPnscu+BmDckBjpmO1OaDyE05UxN/6Yn10JKF/AgIEERR8DwnmMMpiA3AyOKlMSTmbFANOaOnB+u+YdkTG4nI0GCE9Yo5nDdDNjARwJORD+fk5ECcGfyNDH/MSMEL05Vyh3THfwLdOZ8cgom6zdJG5dHK6Js/Ain8OfhoLF6nPNOd+HIs5gSwNzFGnJPrvac+kOXId967OnK6JgLAyRurux6I4SnMrOeZYpk5oxyyzmMnP/CsXXIM5MiDkTmhnPrJtCciH8kZzlEGA1yQyPBYkU5nDc+jl0nMobnKck5Bc9JIG6xnJMQbI3GoYoliFTmH9zDOfsc5Zh+nR7LHInKKjnRYiI53/dNTmcnOMbhyc8M5L1JKjkFE0CQWVo2k55Jz7G77nICjs/yEp6iJRbJjdIN9OYiUARoj5yuFos/iyDtZY3E5nQZWLHInNc6JucgM5h34Sgw8WLNgZ43NY5/8DBa7WOFEseccyJuqpy3I5FnOGDq34DI5+TcRzkZHNJKCv8dpBvJym2SvnKIpsic/GowZiEjkbV2nZP+Yoi5KZz+jnlHMpNG2c5E5BPwmLE0XJFPvBY+i5GZzzzmLkk8sehci2UnFycjkelCouSSY745wBRpznFHKWbiac+c5xP4UUqRWMpGE0kN9KYRyS6TrnMzSklYw05F0cVkpKoBipkOc5YkclyuLmaXKysSkcyZKalycTkmrDAmZ0IUFYlVioUEktwmMEcqYax8KD5rG/0ON1iryUX8enBzLnIx2zbo5c7PA2KDurGpCisuctYxowLlzXbI+XORbv83AluiYBZrG+XP1viLcBlBHly1y7+XP6sWFcicoMVyOpBRXL5dmu4BT8O9hqvzroPZbisgPwEGVybjlZXPOBJ6g9VubZiFATqoNmUdc4WOmJVzF67/0GusTlcwY5TP5t0EfpiKuSECAq5LXICUryx0bQVm3SSEWpYarmvsK1LM1cowqSn4pabtXINbhG4EwEvqCLW6dckxmM6goNB1scSvzpUG5puGg5juaa10QSyqmz7ot4Za5N6D0K7p2DyNpXTNNBY35e5mM01hyr1woxCJgIoHrdJED7gNciVBUrdOrkqAhyueicua5WdNDUHDXP8IOfHR656rd1VhilnquXl+GCOnAI+rkD1x0/FfIW1u+RVvgQ+0yosItc565gaD30hXDDa/AxMLwmv1zw1AfXLhuRWkHCwVTjW44q8he/F2gkZO8/dA8Cu0npaDXHRn8OP5Dqb/oM37oa8VOmjy1MOHlDEdLJXTKBIh+Vy2jFllnQbgVMdg6WgHrnk+DOuZsUC65n1zQeRBQC8Jt1c/eukSho0FLoParisIG65VWl06Zw8nyOJmKHqc1Nz0zmFJG7prr4UVw+P4Zbm8xyJufj+VwGEtzcblTxyTbtMyYQEQYZV3qg8j5ucGcMa5KpRPohSUPOsZKg0epgxpS9lf1jA5kXs8v8QBTLbmdkk+kqxA2256vNpbEBpI0fv86N25dtzk9mctFGNB7cln6Xty8tkjUUROJbcoO5bPTNVxHgFX0WvQKgCkdyVunkATp+r7c725Aap1eZUAVDufVs1j8VtzTebR3I30XrxBtMPtyzh5KP0x+q/pAu5ztzXh7F3IduTnczAC5dz59GfaM95p7xaC8kdQPUnYFiQAvHclPieWyY7n28VWQB8ndmZpaTOZlt3wrSTzMx9iy7Yg/QF7Deitmcfi0Zw1uYqNnAl+p8476KBZxFIHp/kD+pOcdi0WbQ+vqTnAx3GGkDwGk5wKTQG/Xi+lvcrX6KBEggZr3OT+trpTL6S9yLfq5IjESnPc980uz8SEhT3Md+qN7Tb0Y9zh7kP3JVXCI49DJ8Y9VVzj3KHvqbFVVcEWYeMmT3PrJH5kkiRj9ziHHCZNwMXc6Ze5s7ArYp3OnXuV70cseMDy4Mk5tyYMRA8nP6PtRrub/2MqRi/c78E69yX7nSrkqNJUjKB5N8VPGYd+AXuT/cy6KzIQJ7mz3IFrFJk4B5CEIGsygtO/uWdzFmuwmSP7lzEjr+nA8x+K9GlJoHZ/iz+t7xFeEO9zP4qeMy4NIqk0e5bDyJ/ov3MT2RXWdYUVo1BgIhAUONNtcXxx0jzF2iKDWIVKdcZR5moD6cpOnhBOKdcCHB1wNahoSey0eaUNFR5FmhDHkKDUKzsY/QnBxEs6n7+fmtkqpoFJxl+5aGQb+SsecVdK6chFUmrbCgwFXG48nhc1jzes5b8iatqU4pZpGLCmraVONKjDyDK/0lLiJWj4BSv9I04yJ5tjyu5qUHVCeRM4wpg/YDAnnrvh+tiNnEka7/RMkp4YT7cdp+UiqtgEPHncgwmcc48qIYgXYjnEFPJtAROOSKq8NtCnn89lWcU1beMBUaQen5X+m2cVGkFJ+fiU0EAjP3fBuU87x5Ljyh+Sfvl6eVEMOeJaTyZ1SkuIF+sJVH62TYDNn4MsJ+tikU8v8WTyS6CE7OWBihDTJEjJhmCm23KCeWSZSop59ZMIaaAUcYZlUFZ5ezybXG5wnmeVxVCp5Kz8zd5H3hKeYc/VMGQiUUXFeZI+9qwlGcBgaRNOySPOcGm1AOO+GCpSGxZ3wz2SUALy62w8DH4/PLuHixAf55xw9QXmvDxz2TXfQvZAoE8gBnD0heenfDD8iEDPnkl7LFQPXfPEewd9sR4ygRTvp3s+OAULy7h71yOReS0NLGYCLy89n1yLReVPs4VYuSkClmVoHcVIS8z4ema4gXlD7PcVIXfdF5ht9BPYr7KpmTIOP+SAzYFQK4vOxeQaBcl51ih+qiwvMP2WXgY/Zx+iL+hn7MIMoNmPh+6D8HAQtSmuyAQc29MirzH9l9qkmZFA4goEGtEZ74UkztrAvfUMeAwRvgLAP1VHgcsf7wYAsvR5kP1W0LqPKmceD9W2gwHIkONrRbB+tpChCAX30f2S1KF15to9IZxYPymoXIaT15VRpkH5EiMiBIkhXtApo9d7z96kriI0TNApUtEU2jSAH9WUvCP6i6LhR6Y1qyVVr0aCeWWrYgaILUm29nO4zyi+IgDVZqiDTec2aXN5SbyAyjqUBNVnm8rdx1gMpWa0+PWibarMt50PsEXBByz98cc7ZHQD9NlZbuqwsoOLbEcEW0T4Q4JqE2lsF4zHYTqgbWaTeNDVhkDBt5lPjCgZONRf4PD4xTcuDV4hAueM9WgZLYqJYHiumT5SyzeXTdDN5LrM0/F03XyOHZLSO8iHjqzRpy2e8VJwBN5+hcifH/LBE1vk2BykUzR+1aYSEI8WrdHt5zFVSPF+pXveaIzDbxW21r3lH2jbeQaMDGWjHix1bVSDSlrW8mta4FpF2aaePneflLAzxXt1n3mVgjHeaZc8qWjby6aR8uBMZkW8mtaozJK5Y2eJTegh81qW0Hz2RjlSzi8andIKAwHzKfECJFVlpp4+zgr6tLqwS+Mb6JNLGC6pniYPnMVR28WH9ATWF7zivG8jCdlmj4ufW2HyoGaiIEM8c28sBW8PjSPmlyyHea39V+2UHz/4SJxzDlo+4ucC27zOPkueIBcDO8xd5P3jz9xh1RMLlWBATyE7ygkzJeKA+YMzA3xuWBkgY7y1vearSMj5TbBsvGzrVrltotZj5kHz8B42UkinIx8+1IQmtQY5UfO0+WsaP1WN7zmvEsfIVlgd4lB61gM7mb0fL10Kg7I0yr7zPaQ2fOo+cN4iz5BmA1wKGvCo+T54gzamstd7QvgX3eRQzAzx1mt8PmDMxF8dmEKT5L7znNY0GDU+dz4yLp/cdspY93kugvuWfxqLny3KSCqlM1kx8qoWX7zdZb1eJA2KF8pLx1Gsw0amyzx8Z58vz5YTM7Ba+fLtlmx8qekjHyZ8w5aws+c1JfLWEXzGGZIfKwjg4DFcCI3zrNYjvISrlVrPL5l0tG8y4jE6VBO8+T5h3iYLQ7vM3eVxhZL50zND3lFfP5lvV80b55XyDphyeJ3hJt8kT58N4BWT9yxG+Zc0lD59xdZvEPLXBlrF8s9c3IhTPlMLze2siwIL5FnidmkPHk69tedTdy55Ic2DXy2C+bzec75C8sJfGnDlNlnL4lN5U9M5fGueBi+T+8nYW8YxgZaA/ONjFN89QuR61NqDFfPsTHv7AxAp0tDvkfC3s8GeBTTx6PzlJaXfJqjv988b5gnzSfn2CPSlpT415a93zIPGI6yy+V9LCn5ZG50vmnfKoRDIbHr5zPyOfng/Np8byUWjWL/AI/GzfMGZpp40gZUfiBfmtQWw+VArU9xNWJWfni/PLGKt85mW0vz07gitU9FLB4gGsgcd8WZsWwejui4TqW+fjp3m8W0s+U5udtaOksJvna/KmEWz8kLcvRpFfmCwVMNFL8/BC/hDzclpUiVemwrZpJaGxyOb3WD6os78t8wVEjF/F0vW0VqUkoK5wr0IPCGK1d+SaBd35Afz8W5P3grnOBBFfxge57bKiKwj+WNYqP5itoQ/ltyJC0BaSGm0dEzzFEMB2NAqK6aL4LlwaM5oQLy+AX88/xvB9LUTsBKVdPkfXHmWsB7/ENxH6Vnf4uJ6NgJ62R8BLsDgeoEJWYAS13miwybiDXrYGq5RRu/nX+KVQAKrFv52gt896alzECYPraLgfcxy/neBwWvs8rAIJTNI0j4WcyHmlmBU/efXMKcST61zUJYZUVW1HSv/E1K0AWAMHbEEjW5dpDmBOy5JR1Rgh61t31pzH3PROZnIX6wZ9z0SF/IDetO1Ev5cYtGEhedn61FGQfDpJyA77i9ZGSDgPgLv5ngScaC6Jmn+RoEwzY6yt5/nLxzP+ea4ZwJZu1GtzuA0iCaOMo/5MIVXe6e9kX+SdzfAJtaxJ96nsg7+UvdVf59/zmxabcXMeP383wJW4oMbbAAt8CeDEBTmLfzY3m1bAd9qEGW5RK8z1lHF4PXmR8Q4lRumx4VkeKN3mWXg6FRB8yNMzbKLPmUEo7gF/AL9EJ8AsvmW3gwQFkgsrzJvKLwpLILKQFvkETfaFKKW0PQKU5RsTSfkDKAs59glmDFRf8yWAXYqMAWWAsg0w+KizBZALPAIajyKwWra1tAWNKPzVsX7Fy4ZlkVAXeuE0IW4LVBZp+DmVHq+x/mB6iXSyeTShMQeogHsiuseQFEyiiFn4LNvwdhQc32OCzP8ERdX0lMsoiAhj0FHAVUEJpGC00slRGyj4UR+OV/wSws3ZpHAKOFndQQSBen9C5RT+Cyhb8LLUBUAbFwOHBDY/b6IWeUSs03RosgLWhapAtuUYos/5RUSjpFl2AucBbc0yQhzgLLmmTC3yBfn7GIF5EEuhYKAoMWe1BBIFxiz8gVmLLrwZ04CkIqLl58E8bSsBZUo+xZMhCTAVOLLGBYoQ1xZd34OlGtKKn9l4shkh9gLfFlULMYISsyZlp4yj2VH03niWbfgiNQW/tUgV+AuiWQwSV/B3poj/Y8igWUUkspRYyQK0lk2+zcIcXghEWiqiXgU5LIAIWjZDzavbCQY745jNUQltSqk2qjo8lP3jNgskQ6pZ4W0gQW9LJI9hSLNIhnYwPYLGqN62SR7COClHitWksiyrKO6oqrZ0cFUiHeqN/GL6GSXMZrTaHyStCqIeSAENRRYSZlljbLmWYmoquCSyzE4KxqLA4bnkykFZYTpAEpXKFwrH6NNRRWjCpTpkLA0ZXsQoF0113A5emkLUU5o+TigqEO1EESSSBXyCw263Ap31FVqOBuq4CidRB7hZdpzkN7Vj4HUtRqWjxbq8aJ7UVGLafEz+1p1HdvOHUUVotFZ46im1EjxgeIZGQzPKtmI1XB0L0zynKC2tamXSIx7sAqbIYUEx947iiMNFPuLJ8HuovWkk+si+Y2HlK0djdEZIDKpMSEhaG0xEqCu95oGihQWYrJFIa5o51KMpDCBAErN5cNKC/9Rn6AmNqMkPypAGsI/mLxCxiHAjy5BeGCh6KVGiDQUgxRYIQ+o1+A2oLRSE4rPjBdaQmiqkQS5iQykPn0OR04sF/aiqrqJdILBQUonDRVjT7gXfqLpujaCkjRWO0ZOlyuANBWBpPMFmYKaijmkPyOMgE9XJFYKPNG+/Uecjc6Tsg8nTw3HuQS40RO9cvmloKLOnDgu9Ib8Qg/WZjQgtGJgrpWaOQ40FPEQpNHxaPhRDaC+TR/jSHQXKaN0BewC9TRR1JXAUZkKF+kkCosFu4KDyFFqKx2hr/QshrckYg7/uRM0T9XZdA7YKBcC3ELSoLyCo8FyqzgyHGgo9bpWoxMFmLilNEbguF2qESFcF2+sq8ATkOXUTeBbLRwWjg6Ti/x1cK6CgekSgLKtHYG3TFt64O8FaWgrwVRgvAhb0ebNRIGxPAXkQr+4F5okiFOqy6NGxgp/BR7ge8hiYKC/j6IVFBSiJN8hBoKOIVfkPDBfGzP8hvoK0NpwQtwhat40ChijFhQGDGj7nMQhIUKiYVyEI6pHKUmHcySF9YBUOSUcwuQTJDbOqydyYUJ13EZCDJCqSF2kLM7maQrUhW94FSFskKwHLx1Mleafo4aEI5SOupwui6WhesmVomT5T+AhJNcpNV1TYCJOUaLh/qSduIsQErmXa9OjgDnEchdWszOAhA0hiB+TmmqVmNOMYiRFYwRoEC+KCqWYdg2DNPmLlQ1XrgctLC4VVRAmgf1HBBAKGLdUDLIEWBp8FjBJDnAfqK6hyVruQpt6hyxbyFb75HDRx8zchVfpeyFc3wm8r6hg+0B/0aFwH8IKvA1giihUoMRqFb1UawR1UCzGjVCwqFiYIcwgW9S8hQq1Jyp+UK5hIlc0ksPG0Xa2/mhgTGfuwJ6jdIDqFBmdi+pR9AtWsJcR9A2lQdOREMBPBBZQcdEejQiYhnc1bOmFDTFsY0LozD9wUOhS6tQdxsgC1sl0AtVrIBWS6FTgKONRRxGN/s4oybGXRQcsmF4Mdkj3Ubn+heDFaw+PmzaQAQiOoZWSSgXXQrF/vULI84EdQpf4DIQ41PE+YP+sSi9awK/xk+t3gppC0f8h8GoBDJ4KPg66F2v84IXfQvpSHNk5GFrWTHoViEPrqG9k8Ah0dYrf5jTBqUYeqO3+Vf8noXW1id/jjChpRLqJOsmFIRKgAchB7JTgLSayjG1FyUcCjZCu2SnoX/qgpSE//YFR3qso/6HZIMIRkYY58V+IjphGcR0jP7/JlRVFh7sm3Qr+hbMbeYF6MKiYW34Llhfy4L7JtQLHEK/ZMyUdrC8MWj+DcCjA5JuUSrCsHJiqiwAgN/wEBSjWZv+bLkEYUZPhRyXXgxxC9sLQYWuISdhf6yavio/9mgXswtxyRoClWFHsKiVFAwuVyXCosdU244LskOwqNyfOkdYMWMLL9yYwuDhZzkwVCUXQQhhwAP9hSTC3f+Z2JRygaIXX/mchd3IoZsz/4NAu7VJf/fGgkSFmYW3/2T/joQrj4bTy9gUHgRlyTcCmDUbgwFckGwprRIHCoVRbe8xmSAAK5UbDC92hIsLBYXqwpFya4C96FU+59YXOwoHhXTCzrmiWyzck/Au9hK2GPFQ+qEnUInwGHwXUs0/6rYZQ0JhCUNQg6hTEFcL5qWIP7ViEqUQ5eFC8K7LYxoVSGGQ6QPJ6ILD4UtbP3hW0JWNC/LEWAFU5l9QnvC6vQseTiQWsOVFFmSCs9+BmNGQX55PHUnWhAlEDaE3WnABg9aR/U9ZZjRCfWl5MhqMTSQn1ZkVtrHAykOkUQZWcX6IyFJIQ0I0tiJEhRXaf2yRahfqJf+Gds51EIoLHggRANBeHNqeBFQc0DkjLgoQ0igi7ma9IoJFFdJDQReAi7jSxnomlTt3Wh2adkQ8FO/IL4iPJHQ0egizBhbizUb5sIowzhPxNY82ugDdmLzK2voHMa7yC9AiEWFFj0hGOQBsF2BIW5pVqG1BT0UEBaIiL4NG68IhMRD7XkUqLQhYhHaiPhFKKdDqXtwhIXkIpYRcSQ6BF9twHwUyFg0TqvXJpU0yJwg6UZzwRVwiuhOSgKKBxILXxxGAiq+RjiLkNESKOytjFmZBF+VsRmlfkP8InH/XNo9iELEXpMM8MeYihu29TDgkUVTEF4thdCxo4oK7FJTW2F9Blo8ngqVsX7aqTHsRTG0FxF8kxUkX6ZGTWkP8TxFr1sdCoGIucRZOII9RviLXrYGJBCRUIRELOrikDNF+6CWAVUivcF5PQ5gF92AqmA2LHRhjZg3yEmCP8OPkirfaVCKe+YXAuIRTwwsYFfCKI8TUgF40XkwKYBG8FJEW3KEaRSMmDxFNSLtbo2ZxjBWoi/w4lMhC1ElIt6Ra9qXJFm9jhxa37Q4USiA/kAGIpdkVe4kZcgCQy/kQ5i9HRIQt7mPwjWEByYL+kUogKOOK4iwxFhdAdxbP7S3kT7CVCFPSL2oZd4NuRdZDJQBLYKbEWb1jThbkikVO2yLVEVDzQUfpeor0Yf1tE4xd4LF0uJC4Bp+wdH15MG30xEqrWOA4PDmqDg+0jwFIMzyYCMY5+GiG0eSF6tKbIohtkUXFvL4bKoMpmq7yyNBnEovR9lKmbQZ6KK6BYxED0GXSi3W8neFDBnMtTbeUVkAw2bKK73GaqD94QORQQ421CeMK/JBtAsFIfsZ5KKZoCLjL5Re9tcI2l7F+fb2HH6NtOyHtacqLahnK8FI3EVJKQZyrpLAW5SCKEV2kcykl6g/RmHIzcFncNcHhtkxRMSulmVNpO6XDxhmQYRkF1RC0MlQwFo6pFEdq5HRyGS41NW6bVDjBG/NTVuo5Q3Ph1jVA1YVjKZRVOrdKhjko3faJMH8GUfsHIWVM5hjZUoobWkJkDY2TKKPQ4JUIYwmKiluioFtMGjD2ljugmioNFm6EY0UMW2C2HE9GxYu4z/UUK0kkNpmiy9CL7RQLZhorNjryM902XDQ8KTH3EyGUqRdlZNdC1xSUNW5WSuMl7U6Iw60VWDIAarWsN1FVhtJUVL0UBNlGihv6SdDE0WifPjkKGMyVFjzgnhlRunw1u4bU4Z7aKFPmYouh4Tqi8jW10AeRkmooa+cEcKoZqaLCMIjorHFDailtYAqLS+EHooxbAbwndFR6w7UU4ZCs+Wl/Kc2K6K80VVoqWGeei52kl6LiXS6bT10NubJSQ7XiaUX38JFWN1479Fz/CXUXofQpGR6i59F8psK0U5ay9RcobclFAKYmRmFos00HHQ97qi3jx0VVDJrRYViTvoPIy9tRSYTXRUUI5lYPPjkMVjDPEzJdBK6cfoz1XRvor/QEyMp9FFELzUWUYv/WEMMrhqQGLb0WJNQK8rqMmzEH3iMCTimwVRdF4+kwjxsZUXB0mzRX2iwb5uNA2TZDorSoGqbYcZcGLiMX9jMlRTfHXE2vGLrNbD0Jtkr+SdDFRQiNUVtay3RQRig1FDwtJMVyCI3RVULfIAFGL36rhPUDRSJi5DUyKh1zZRoqu+Uei0dFj3yrMUlosZ8Vaim3hu2QOfE3ouRGbhi3L5hKL1zbWuwHbOeSAuhpH4QMVCxgjGYhik7W3GLkRlwYqCDmii8lFBARqxngYpognuijHUlm1DpDXm0wxSCLRLFEoyHUWxYs7GRaig4Fr9EbhlhYtSxSTwuNFNUdfMVNySlbMVi/FFsOtbMV18lI3EsiHkZcGKasXGmwsxavCJtFJmKYFjbm0KxRgsYzFQqLzMTqYtQtuSitVCHacSsXmYhjRR0IrkiFowtUUUW0LRcC9BTF5WKK8HrRJvGaxi5Ds1pZ0FYdvgjqh3eVFFCvD6MVovXcNhLw3TFA24NkDuDMmxUaitYR0tUjsVQYsFgvtikbF9vz3QlO/KHxAYwXoIvvzbsUv0TTarK9IP5ZiQ7sXPYt5eu3iEvYI/ibsVvYqexWn8s8BMEyeEw/YrX8Tz0b5MH2K8LCF5HBxVn82fxYOKp6DA4qU+nDi1C8z2L4GH7+Nz+X4QJ88wt8FtoqDNLPFDyL0WOOKMRE/sXwNnJZL88KcwRg69UHOJPmI5/xCOwcrb4Hhr1l1IUnFeOKK9bjok5EWoWf/xOVsQhzABLxBo1bOnF7/is0aNW05xT3rQnZvIi2cWD61q0nqIyPMv/y01qGTI0+OgEv2Mpkz1Fwb/L92bZM49qCX0awh/nmcENYEgtYjky0kJ2gt9WlqIkGyNATOrhpiK0LJuC4XFSoiscV2B35xcdbS3Fqd0AQh/nktxVzSAG2DuLy2oK0limbzi8QJRxERcWztTnWFcRKURy/yg/a1TKUXEri07Z11tGhgqBPtpFqRK/0OHVAgmZMIGtmu1bMwQeKicXb3U00oTi0XF8GxNrbx4uSDs7ZDo+NvJoAUizEMmeS4eAF7uItRGTITnjsykTqZm8BEumYBhUwh7i7e6BeLBplM4tgwfBM3447AI7wGt4tvdLqkjvFTqSo9E3Xk7xfT0ngi/eLnUl94qdSUjUyEUQN4C0mvgIxwjMaE1JI+L/t5J6O7xdDvCOp1Bhp8WepMTSaIYGfFjejwcKT4sFqWJAHtqbqSprxhYS9SXPi7epDOpFqB84TXxUGk7fFp+LBLB1VKyYvPiu/QWJQsmKhpP9qXfi+PiPeKSUGH4tHxcvsmu5pnskmyWDgnxXmk6/FLEDV8VSpIzSajhT1JorzE4DivO5mSfo2MaoAp0egjyjrSVDUGnovZc60lwjFwSmgSx/R7/RWegoUlNioJkMAU60A+0kT+iz5Lrom2BqwAeBSuHU/ijjoygl3GIpookEqm6I1iedJBBKr+SW6JgMTgSx7C66Stwin8iQJY/olAlj2F90klhFH5Is+D9JHNp1+R4EtYyRiBBjoWBKwoG7dhAClVA/uIQl4JCUUGIdmSISk9JQcRGCUKNUIyRoS7zCNrwAMk9LWPaFQSmTJRlFAOi8EuPgXapMwlicDaBgu4HY8S84awllhLRDHFRTxHJZkoUKaHRTRgbZHnQaQSxIWeZA3nlBKXjomkEaT2reKiCIXTIPqVwRP/CBt8wiUhEuRPObUaT2J9R5DTF6KNStLNB/8xMzoiUy1CBmdESlOY7Hs4iXBEohmdCXJIl4vTsZmEzMrODp7Bk8ARLBrylEuKJRdM7Oi194e9GkgDyJcssvrRVeyHkTVErwiLES1AiCBkEZmcvxuvGkSxa8oRKeiW5EqldKQRWoljMAIiX9EuruTHY2u5oCkSlKDEuvvAlKRb2N144jgnXn8JcwRE6AMxLeCJQEsdgDAS4PpA9zsLzgE289g/MTZx5qU6vYHEtj6ZUXY72/NRW+m9ZSi9rZ0XZxGqU3va64XaceYpbPpvwZctgOYVGwPJ0fL2bxJi+kfEvH2MsSQr2LxK58LPblK9g8S6SugJICoqU2lT6VJlY4lu0hxKlQkvOJcYyYMWRZdoSXLEUBJUXUfYlTTBpAhIkvhJe6lRr2RxLsSUNewfeuale4lM8xrYRQZWeJaJGF/CKdh1vbX2mtKWcS/YlPBRSSV4kvpJXLQGLY1AUB+mQ1Am9hqlHvpTAQ68LmKQAGUwEGb2S+AEYr58j/6dcSDyoKqQmAiiksI9tALfPkgpLJTAwuAFtNYpUYEKd56VqHez2JdSkJ8KNCk0SUakoZJbJJaKIgGxv+SUkvlJaSkK9o9lFpSWXJAYFOS4sUlDAyZbSTzSMUsEYhgUCnEoMr8kqojN17BWRC/TTSU/exzwOySh7aDVEmSU6kp0+FVWI64Y9Cl5z+Iv51D3ESWUqPFl8Xc6kXeJGS/oiHAQf0Bt4jRmc42BMloZLSWjhkvp0GCEZMlKeNonJxkqWIhCgNMlUZLoaAWPKqVHlYTaquaxmqAx7V5pAGYYwiifwyyV77WeJCrwElkmdoGyWGDDtTANcC6qxhEBVCH/ANbNWNCsliVQuLgYkobGhWS5FECyp6XaPgzGJCFUUa4kYhC1irSiFRVWS8bmlB0RSQWIhCuFisEg6YxIByXw5GrJSldEcY3ZLWri7MB3JW2S0yAepwhyU37SAHFreAa4j1VauTF7lf2i2Sp66oxgo7wdkvLJbHoRREl5K+yUIiFbaPuSrlUyN11V5WulHKF9VXNYgAZGuIexBOQHOSoClY5LFyUgpF/JY38cBw95Kf+6FcXrJXBS8ClPuj4UXJ4OaMU/HPY2zNUR3H/xykOtB4wtOUfJuEyKDJ9Tshgzt6ljtpfli4jATuNEz7xO7i4LbCm1e8TzbSS27MltPG7pzJ4UDpC9xK5sFsKmDNQTvTwkrx3XCM2z5Si88fs5Si2o68SE57G07qon40pORDQa4lIZRaTv7VYDxDHjhU5ENHkpdJJR3xUlLHpYzpzl4Yn43hOv0SCfGbiUBidDnFjxeKdVFiAYMxTorEgi4bPjEwC2+E77EonFBC1lLcU4Rp2+vG54+5OmMSjPFXeIDTsnVbCl9ad1EzB+K8pZEmbjxDHi4k5UBHvcbnbYSlwVLcU5oW2fau4nMSlz7iZPE+J3+JspS3yls/YRvHScWZNgYc1tOhsSr+yUUtPqoJS11Op/ZLvEBUp0TkTTUw2UKdb+xH2i58QmnEAcj3iHfEINCmliFS2SlbgInKWgFSb4TlSlilkDUMvGUeUktmlSptOTKdKLqheL8YIwIvClVKdd4kxeOfSsEnXql/SdI4kfqQ48RVS7/Y61DyJS3vJ8BC1S+aly/DzNKFeIWTkVS5ZOkcSyqU7O2CTgI1WrxtEpZ4m8Uui4QtSirxRycPPkZNE68dObZUa1FLw043JwpBFVS7ROH/CjqXHO0MToZ1CbxnVLtdL+p06pSRpbXx7lK6mqI+MepaCvWPxaic7qUBqHg8VdS9BJKXi4U7nUp+pUinE6l8vjouGHUtcpQx4malz1KCPHECIG8TzbIROoIJt3FRJ0YtshdV7xUSdFKWnUvs8bQnAwaD7ibIAsCP2paqnPhi08saaWw0ssdvxSsXS3VKyaVg0s4dopStmliXj8aX/UslTtjSnXwpvjjvGTUoRpQdS5kyOPioE6GxKDrhGMzVOcV4WqX00rA8N4nb6lbFLn0ompzTJp74xd00KcsfBi+PNVu4yGn0NvjAaXiNF58dk7WxOxCTMaU4Uv5Op5S4ildylhCYzeNepZ38ZXxSSdxGgz/F+pQ5Sp2lrTsHzbRCIrWPbSiqlWoRFZE00tdpWRStSI/AxLfFiUqDpQ6nQ9OwQYlqWsJ1xas74xKlMlMJKXAJ2OtH94sSlThgufERUrx6CqnMSl6dKOPGdUpjmB2nGmludKo/E+p1BDPHS4SlX8Rh05lrJT8eOnMVqGfiEuH40pTBLn4sROqoYb3iF+NXTlqGZRooLs9jY0XB3TqqnLuliXjwE7t0p7ToYyYy5+igCpSL6xuERthP9OMOL9BoT0q1YM+nKQaUI9wM6J/IWsTlTMfxgegikmT+LX7nhMqNS6dw6WAQZ0L2QvSmzQS9K7LnlUx3pV+nZpJPAJd6VH0oPnkts1uCoSg0M69JPWiVa2bDOougZV7+ZypIR/43kibrBJkkKNUf8fkrWZJFc5EGTP0rhKce7IBlH9K8M4NnQACb27BK2lxDN8HcZ2czr+1NQJb9KUDn0UiQZcNFaJ4khJerZQELfbMFnEoEnASuHr7tSMBIQEvbK+ATCGW/0q0zsSTUgJmAS2UwApPMIcHYIzOIKSEAlXuyBtMgypgJoDLWAloMnwznh1TgJ3mcsgTkr28zo6I2cc27sl2pvvlgCQlnHwEWS8qgL8jTHXoqRAMRBmAos7jorHFucPdLOODdiUlqBP06CmIoIJW7s6PRykNRWHe2cLOBDLdGXhBPEwFKQ71IwQSXDj+4LHUW3KCTOr/C7KSoMooxB4EsRl+A5TM7WMsgurm4PZi5jLiyHGEGwZcYy4PBPFxVSL4MsfOuooYoJu/tFiZOMr/dqF0FMRXaiRCQkMsinMoymwQGYiWITJBPIznJ1TRlcHtdqpakMMZbAycNIGl1MmU/ESEkPSk0M+WjLJPT9kL8CZm7RtQgqS1KR2Z16SfYyrDO1TL5CENkXMzj2Q4Jl6uFvAS7WEsCUjabQ5XjK33bM2jFJm4yu92fDYMmX1Mu1IjX8ghqUTLiGUmXTqpBt9bQq730XtESezLCOPwd7RDL0heaSUTmZSh9IbRD30FmUdEpo9mlofaiAvSP0DUfQu0RDMnZld2iZmUpkm3Ylb0qj6HVFQdF/fU2ZTfiz7YdH1rtGg/Tj4NR7O6Zyn1pmVRmAU+ido7ZlDzLrmUJbQeZUDo+2+Z8yTmUfMs2ZY0Si5lwOgMforMpuZbMyx3p5MyaCiUzLVAl5JFtQzzL6OzeSS20YdRK5lyRLsrDM/RW0RsS0GAWxL+7lwEuNAuV9eex3uiO9bnymd0Yt9T3A/JRKWW+fSryVhXWP6Cv0tdGqIT4Wcb9CSskXoRvqHAvnkjTo5fW5JQoqzyJQX+XDtZnR0iVgvrHkijMt0leD5VODudH2/Rosnzo7maYv03gFC6JdHr79YQkJyx4x6+/QpZeroxllg2chcHK6MW+uBNTuSeQhi/oHbS1ZfL9W+kzLL4eQpzO4WXros9Y5b1TtromCz+p7HMVl5ujdfqlgSVJGSy4oWdujlWW5YCk2rSyhv6O4teyg5xU97NttU1l290GJKTgm10T79Pv6auj9dEHh1JXIzg30yqMUMg4EOMDMuUlaNljEIEMrQC1wwh9tDLeBD9g2WM4OlZegE4vJ9JIPWU+sq12qWyh9y/7NyEAysv4WZl7ef60tJVWWZsq6itLSAv6Itk02X25iV2omyosOAhRhwLQilrmS2LCBxkbK59aluTHkuPRbVljf01IR6spQpWv45OaHt8EtqzsrZeXMyhdlLLylmUoGhXZQjMkDY1t9LvpbsqOZbCeKF5xphwWiwvMBZXuykl5TkkK76nsu2ZbSeI9lfzL46LkvI3Zf8sD5sD30I76AsofZd7fGH6kbIA7FpUlfZXeyon68dE8XmvMvHxW+yj5lO7L72W09J+eb+yuAG7Lzf8XfaJevMCPR9lGLKZaA131x2C7fJn6KHK8WUywAJZdHzCyFh64HWWyvND+rhy1HOL99qwIjIBVeWL9awqzUx377asoucI4DDBwGLSqCxC3FOyB4DX36698jXn9fXXvlFYZmKumoiH42BBFZaisG15bfN0AnkcuVzqffYjlIepHW5i/Q7aurnJ2Z0tIgEKkcv1ZfiMOTlkf0hH78Pz4WTqGUXOmsza1hf3zVFEmygKw4+pmH7dspxquYDVjlFHS8H6iyAgStLSbjlYAsh1hEP3AfgfdPQq099oH4HPU5AX68n/uNbK5UINSTleW29RQI7rz5OUWQ0deVzSZTljnLEr5mnQI0HDMkfRJjzQuX7TISJTqeXGZBkpneKj9mi5fFy9bpEXKfGL35l8cdFoVGZcXLUuW3DzumeFbMLlWXLFEBBjwMeRly5mZBkpcmI4NGi5eVymO5NSwSuVcMoMeeVy5vRNSwX3SYzPRHgjMqJiFXLQWhVcuzuW1y5rlRXLewy9crn0TR7NF6sXLOuWuMUG5T/iiYlf+KDrwhxUy5WExQpi/V4KR5y1l+mTExD25HXL0OVuQEw5edCoR8SWSZl4wr0Z/vvkG/2qWSBl5srwyyfCs3V+LHEOf5MIgtfnz/N5yh3KAYWE+zJ9kVkuP2h3LwYVxEke5VmgBTyyfs4YVzlS+5cr/LuF1K91f4XOVZ9ozC1v2e3Keskuv2Dfv1k25+9K8zf4LOV79kZLVWFwQoD/5Q8uJftbLcHl5L847iLZJ1/kG/IVeIz4eGmOv2r4jLChf2Uq9bEXJEkLfnQnc/2ny93vBIwtVXuLC0OFJ/tpYWlwrrSqn/VmF7r8ucRH/2rfhcvRHl9b8NYUF/3LfmDynWFVS8ueVyBzVfly/Sv++MKtX4RJ0ESEavXFeFsLkl6Gv0Szkn7CFenAx7YWS8sNTh3/NnlUDJVeUE8pmOH7CtFeJJQsckY8rB5XryzXlJOJ64WnUhhflGkev2XPLBcnj5GB5bnCgHlccKR/ZCjCZyXTCyN+3TFmckxvxfHJnCwfIo/secnY8qTfskhQuF/r9ceVmIRsZHa/CuFkq9V/bVwtjyOTypuFiq9N5bx8tp5a3C8cFnPKFeWR8ocZLqvXXJ1jkb/aG7Bl5bAAz3lZq8ktkW5OiEravSB0EH0rV7ZbLaolCxRqknq9CuBwsUr5X6Ex/S7uTp37EAMgDhpaKvlzCsGAHqwGXftbxY+Fwa9t353wvGsSyxCNezACMA57vyhBffC/h08a80jkJ5JG2ba0+dS9rSJbCOtM3kBnk67Y2a9VlkSAIW2d0Q4BFL0RxhSlBxM/mXk/9e5n9K8nvmk/foMkX5FGn8P17xAMqDvEHBvJ7a9onTqIsdUsRvP607gDPmQI/xX2MwisxFVFJz+XC3DBNHUHEfJ7/M8N5uGy3NNhvKfJxgdybScXXAFauvSwO1VtO8LdrxM/ovkwT+sAqTGE4gMW/m4HIcxVPtfA7xB33yVh/RK2wTlOthhB3SYaNJTwORAqMQHHIrGDkYbeZFtjp/+WI/wczk3Keakmc1+gaFBzqVHsNO7gVeS8v5Y22COdBcNKFYKSkUCrTF4Fa9KdA2Agr6GTJEHpWA7cPNiuxhGUkc5C5XjQdCm46K5Vl6d7XSvE/EerSkVwjLg6mVK0oAEEsU8gqGBAGJHIOspeFQVuXxnpiSWCb7AaSUFg1UwVlCbSjMFUKUW48ygq0PJG2kydPy3FRe1grE/i52EuSbO8Gx0JIKrBUeCvMdK3QMQVwgrzHRSCtJSTIKop08aRhCLKrLKuLfkh+eqgrXfhRCp9epoKklkRs4dBVgghCdDhJaQVRgqHWQIwlMFVCkOkSbgrvBVLJBsFQRVffsAQr+nQiXCtMiUKisBSO58ZQPAk2dHFVMtuFQq8uKY3HsFatMakUgA4XBV7Mhh3NaxGoV3SostzWsRKFUzvK/yhgr+BUfKiGSB6ZEIVkUxf8z97giFVKJS5xIZkYhVt/ArXE0KhIV/wld4zOmV0FRyJUYV7rF0GnPTC96Nf2doVaypGyqGCoKFYn8FzwYwqfBXoqj1kH0K84VhKpNt4jSgyFRcKw4VOFY9BU6FBCQhvEUg2lLJ9Ejn9neFX9MPbpCCR1hUVuM2Fc4K+4VMfxLiBrCoThlxcYDhzplvJwgOFByKcK91ipsMxJi/CuXeiFAWEViJDxF7DCvRVA+wffs3QqHhV1MgEEIyMG4VffYERXSESrpnkRfoVthRJirZvQxFU/jMwqQwqJBX8oQ+iVcK6kV3FxXhV0iocFRRcTSqnyTxhX6XEsFUIK9uGCyp6QSsDnmFRRcPWk5MoItKUskOCF8Kp6Go1xBRWYpJfMA6JXeuYKTh4Y8ioaCom9AkVLIqDAzNCrDEpcKjNiOIqciL0hnxFTfFboMBMEBBC+qEKImjqbMyVogHRIyMhEHIdDUa4Norg1jfCquyDguMkV9cNIrgyDBNFdMKs/4pLQ+Gj0rD79i6JHUVUyQGhU+dHH6uIK9kVIFghLE3zytFWdqZaAAg5TRUO3AouG6kEGUHbx8IbWCGn7HqKjAhXfYMxXVEKVFeqKvHorA4ERUhXFFFXsk6EVDokPYhSioxFSeSiRetor+RVbkrTpo1KfGxkUwfAG+ivJFXt0Lvs5Iq+PTeCqGICtqEZFQ/YvRVWnGLFbnEYUV5fypRXpaDTEiUEIUVKQr3JjmdCgGlqKyW+g4rL3r0ir1ODLNL/qYYqxKirxnP7DiKqspLAU2RVlajKFfG3c4Vw9LNFRlVAXYkGoFAEJ4r92KoXCeBrA2S8VZ4rTVQXiqKsNn8a8VEn8irB3ioedJgGTdiueEngYfipnYl+K3GYD4q85IhOO+3j+K18VORgUAQgSsAlWZC8w43qTw9rxs3FFrZXLQeGpRcpCkpMtma/tDQY2FBgrLy3NjKKBGdRymjQ09p80CQ7LhKpLgEIr58R5EVSOo1xMvwXkYS4jWcHS2O/WVFoCCQaJUx7TpxfQQUNiu1oQRUkVCIlWxMKkS8PIN4hSujEHpX8ZCVmEqJ9pwSpQlU+mW/GIkr1ki1GgolSU2eCV/gp9B7SEWOiLJKrgGDRFBJW4SvJ8DH8COFQ/Z0nQKDxPgFeoMiVwpD+wYnwF7mEpUuSV8w8K7gYzOWHjADfMkWw8FbHWSod6crYlM+IvM2oQ2SvF5o5KvnmWXFgR5a8wi1Dly6MlEAN3OLavVZ5nWfdvRUqhvYRDXmy4dbY7yVQBSUuKeStclf8PKKV6XEXh4q8y3qAFKx3m6XFDSARSrilWHYoKVdvMZPYuStjuboEDM+GUqsR7u82g5XHY73m26RMpUp2MC4hSPRLi4Ur07GRSu7uUfs3u55aSsOUoZx1HiJAnhKu1skrzCj2LsSiMNMemfNy/SzUFwMV9k1SBOiVDcRWdnlHn/YtRk0YQ6x6P8zLHuqPSaKoZj5DFmQNySmsA1SBoiV2+ZFOP8+tyPAqKvSLzR6dSvaldaPDhKm9iJpUHSufCEdA3gxGZY+pVtj1qoftK5r24/E86iESihirmWEEYEY8KdFaAyAQpnlCIut9iAamtjzOlS4iAqBx0qa6DZjC84XA4mKQ5MYsx4mAwYcvaPMaVhahUGRvSrbsbkiM6BjBjzbnwAkYSPhgLMlO1x0ZV5kpDBtjKtV6QPFrnRROkHnumSkMGRMrCyX9ETxlTCSbMlFjYyZX4yv6IrTKqmVUEq9YBSvIEmG6+WrklZLRrjUBR3JTf4PZkbMrSBxNkqTARdCeAc7PBX9oC2QbJTUMXeERzpf3zsys3JUc6Gs8PaQIDyNcQIUhOSjQYtSJQwFBrAinqrKmPa1KylyWKyo93ktSdcl2Aw7bzTKiwINzK2bUae0uZWgJIqXMeS9Y8NoCXhCjkvhyHzK88l8VVbZXiyvEzNMqAogbsr5SBHOkErArKurkaYCm3zATw37AKmUMBQCg5yV7ajMlYMaHEA+XKS1xNd3G5b5KwtctAEEuVf/icYvHKpolLhA6QLJyrXoJh+LOVsdyc5XVcqgAvNVDrlpvMc5WNcojyUnKxrls9Sc5Xb6KkfqnxMgiYdyk+IFys9XEXK6rls9Sk+JlyvFkNy8vrlsdyk+I1ytCcI3K7rlbcqMGDdytrlQP0NOV4LK0wrDyuS5bY4XuVaXKSpWTcpg5fXc3rl7dzveKzcpD4kXK7fRcHNEIFrcqUBs1Kk/Z2fzHvAhWwWnLu0beKehBBGJEJV+ZjbMkxK7YCLZnWJTO5j3gUOZnvokkjFTjjihoShz0xU59Yr+GLBZp/KxaVHkI5YylJSkSh5CLv8ScyNpXn6TsSgIlc/Sf8UeEpnyrAFOPFFLS0kRgkps6R/lfdK3ggTiI8ErUAspiPhLZ6q4j42dAsTwHgvDERKoXUSm9gvQuRUbOPBQkmFDqihDRJ2nJJxPrYuM9gpxI3FzEKuPahVDCqlDYPFnqnGlkRiW2CqFDZEhEPHiddBihBDwDap43XWkqq0Q2WWE0/JzEeEsNlwqu3ECuBf4nBTh1SCFUc6JQ3MUnyEKuLni1QseIQRs9npMJw3oDxPNR6bCd8nhfj31oIpQq+siiqV4KYmJkVU+PLiumlDcFX4xNBnDuWGGS4MS9IyGUMzgNDE4acyiLIJhmTx7+MTCERVZk8RJSImKXWOjE0iUeht3miVxPanMUsPBVcirV4x/SzYVb0bbRVwE866j+UNIdE5PAeC0SLRFXkKtcTn6QnRVySqj3iSKpSqIsbR94Giq0lV24ncVVTEsf4O9UsuBoZAGnrlQ2hVC09cqEPSBFiT/BQqhwSqJYntUGhtNlcVJVaJFKqHuLjTiY4q8fiY/Bl4lXDDyGG0qpJV5kZfTHOKp1iUoq1I4E2gDolyKqTxvQkiciESdn6xWypqyLccYxVZc9xqEpbAMVQMqqM2GyquommKuDxKsq2+6lNCWHgtxJ6VTXQCSo6d1Qox7UK5yPUqy5VsyceFUBKtOVUMq5GJtirOgFdKuXiaYqkG2fL0bp5k0MSVcjE25VqZi+lWpPQN+CcnKGQWcSOlWimwGCGCq3xVAKqCZbO3V+ZM9udpV1EpumRT7ESltEqzU22TYLp6FKqqYuYqhaecNDjlX6JJaVYabA5VaD1qnxAJBiNlk9RXE/jQolVF/ANtOZEdeWmt09nzf7G5lv24H5V1zQHFU/KuKVTtPF5VMKqKp6WKuJTpCq9eJcM4n7GgqvXiVsq24436BeVUjKqTNsiiEpVyyqDk5fKs7uiohcsIF8S5FV0qt/iXKqhfYFSqQp4Cpzq2N9Etm6pZtdVWKKqFVYlnLVVUd0DkJqqpHiUtQplVE8S4qHZ/iiVfMqw1OxahOZ4OqpJxFbmSRVLqqHIZ1KoDickqsZULir1xSmpzeVak9XcUuAxxuB8+MYeu4yONIeFw+Z6EqtXNpQq9O6SKqFmISqtISXIqgQqWCqsVVD7gxVXc9BNVT+4zzZwqtO6d7iDWe8CEHBgJMHpVf0HUyMEbJuEm06BToYmwPhJciqS1WyKqEGJAMMcZUiqdmICpFwSemqgaoUyqMNjEKp+tBJ3eRJ0gxDVWS3Xd9PBbQFViqqcGRJqsqVQ2nRZV+8S5FWHBGpVckq7zu1OsW1V1DGKVWYkxtVRNRyVUeqvc3goqsJJ66q3lVJz2ZnNt4dBs89dmZzbZHXrFyqxehhZACFYX3X4tgiEfxJX/QwlVDqofVbgq3dVabE71VrqquxU343WxwkgJ+CAMOpkDeoceecDDu/FwHgA1azoeyE59DK2BhCCnpVpbVXmgbE/1XiyE9bIBq6DVi1iEPpzVHg1cXYSDVlSSgNW5JI0cIhqgpJ6GroGE1wjQ1VPS3fltVpq4g9SnMiDXkkTpUVZkzrToC2Scvk0hhoRIEVgEMK5NNVZFesFGceUinRho1fVbb0WayTN0peIqK6QzZZfJZv8XA54rBwYXzyksV7jC1gGPSgSKrxnTmFYmrBM77TSVFd7glwGqRQBBCS40KONpiIvo/WNVk7Iymd0NEwsvanySi5IqML90ZSk9CoGjCI4WkpPpvq0i+QQYKSnkDDIvk1ZRq3jOGvLuNWnW3HzNeEfZYIuNHqGhwtc1R5nS7lloqZLpZcDZcicsUWQlpiltavJNyrrQbbgV0Nx4sncjD/WjtyniMDm0juWFrX+sC9Cz6FMqMktXparnRkuSSrJMa1nUZPcrHRgajArVWJkG0Z8wn5/vqjcjBNWTc1rTo2UVeajZ5iJ2Tc0bsbVRhb+tZ1GIPKJMR/rXR5bujQRcRv8h1otYNh5V2tPbQgyqyYViYNS1ZTCiXlw61QzYzWEKwUBjDGFM6040arZJIJImjKDGfv8meXTYIwGDzCzNGSGMGtWmYJCwdTy/7lqa1Cdl+Ivp5XRZRnlnMKCMZz8VZ5b5g9nlyO1StWI8ubRvn/bIkeWIHNrF/yrWq1qkXlwWC0MYJRjhbqGjJDBdRxN8lRYLl5SVqmrVC+xpvosYIRyY9qrDqHWrVeUA6uh1dlgqpibvK10bB3BN5bVg3RCCOrINpJ8oawUMxCWFKWrftW28utRhMxB3lmOrtxwc8sfRn0xNnJm6N2sGpwsKwV+jY9IPvKNUanbP95VJtQbBixw8dWQY0U2mHy8bBy2rH/6lrTW1Vp4NuFhmJ5sEY6t+mo3C83lmGNqnz86rrGJtgjPlB6MdsG9wvs2q1q6AB+tRntVJwpl1YRjU3JDvyJ4XRqBCEi9gnFif4AAtoStKKziEJULapLE8hI66sn5eNY93JQmM2+WwTG+wU3ynLZVQlwcH+wnj4DN3dxAjurzdUwnAd1ef6VoS18KzMZ0i1aWddcB+F0RB4cHDbOEdKNsu1p42z/dX6zjX5Vz8LHB2eSccGdELxwTvym+lupwj+U0su2xqnq6yE02NT+Vc4xJwRfy+ll8uN7+WA4w9wYXq4nBWww28nV2w5wQZ4LvJ7/L48zs4z7yWljbbGf/KhcGN6pwSAg49nGIArViT67T9LIK4MVlsuCoBU96qGxi7g0hhB20W9XTamdwXTg7GFm+TQsaYCu+UtiSabGuArzcEk4JH5ra5HHaSSdiBVn5MX1RrjcgVlO1G9VhO2twUFjf/iEnTisaH6qcKEjjOo4p21hsaggJhcLdjdwef1s99VqQnDxmYo2fxUzKUpXzsr11XlKjdlL+r7JXjjDWZbiPXdlQvMP9UHst0kt/qy9lzklkR5PMtpHsey5ySiUqz2W6SRgNaAavHYCI9oWWQGqOZXR9GKVSzLEDXgGtQNTZJGA1v7KFPqv6tA5VjsJA1N7KiDVYGtA5fga3A1+r18DUgGoA5Rj9QA1+r0iDU0GpAkBy8xFlFHZZBbkj1RZWAa7O5tP06pVGfWANQyPXeVh+i+7mtSuJZS79I6VPI9v2kBQMhlVSyiba/UqpfpV5JHjB/fUVl8UCn5Wssp7yZNKzll9LToJI8spi+gtKqpKRv11DVFIjLLsoa7KB0BjRYqSsuNHhAq7tY1LLZIG+JT5+uwpXgxnrL1FISGvq+omPY6VTd19pUuGva+nvMaQ1bNINxYBjz4WdY0kMeAD9XDVHQMjHpN9A/6AETfDW4YQTFtEa6VZ/o9wjHdsr2cthKYmRrEdw2XsKQyqJRHXpCS0DvDExGsrHvoavI1f0rOopDh1aQjkavoQebKu/q5jysNZVQT8WN0r8dq/wjqNS2y+aMJo8a2WV/SiNR54C6BgxppJBPNlGNN0aw2+1Mreqx9GomyF/+M4YoSB1eZh4B6NSmuYl5ivT/ak5rgqziMayY1LZ8iWX7ARPOB9VSs4VbBS2aFJHBAgWIUL0lscKBh3GzchSS0UQYBxqSuYy/C0KInuAsGpbNhmDlSS5qH5OQ5xkucA6jzdCuNcffZdwOENnjUOvJ6smdze41y+o5HQcqnhfP3fZYiOULKoTLRCxzrctch026Zu5RvLT2NYUhSE1hxq+LiG/GXiIVCvpxLBDQ6jUrR8SChRG3O9FRTjWW+mihScajHEHszJKh4mtLZlnwZ++9/lsTVqqTxzoCav4xTczypK/Gq2SHk4iHOwz9fCV3yGf4BEAaBQKti8ZnUvNT0CC8lMk7VYcnDh2NumQnKg4e1EC8VghDWvkpyaixYlaYtyximpTJKGuEKVeSSG0ySYHZNTmSOF5iprkPwtDXPknKaiH65jhDID7jFIQlKas6U4+zV8xJDS3DCLAPdyRprr5Jq1KgUs+MAY1v2CzTVKmt7DPaa+9ABjynTXm0Sl0OfJCU1AgMvOJz1ARZetRDjY2oEbTXwKT1NUGa2U1MCkfbE2YUENdnY/eVzIKNwDYcuVmNdYIP0+uYRR4JmsLsXVyZg5Wj5LZi9CGTNTNFX8EUBdkx5hSjFZYRWczBHNY4C55/GoOUD8Pllv+Z6x4Vmo7sV+UTUeRlwGHHgHKSpexaXhxho9tJWzbQE8qaPDM1w20T87pmpArNuCXs17cU5kkD2LdmQiNb6cojjRzWjtWnsYOahEaX5Jry6ZJD7NelbURxKGpizWkCRHzovfYeqHfhIHETfX+Jh4cpM1zByo5lB4xnNSUCF+E5HkQ3kvBEgLiw8fQ5lopGIQDNEy+u4mHBxnIoggYPmoIcW44R+KhDKSHHHsGLHiUIZRxeZrX9mHZAQccMxR/Z8eJH85KvNEiCw4yaA/5rm9T72L4OR1FHhxb5rxiamzIAcRea0Q5iUMOHGTzLiBOBa98qZryFngMOL4caqPGw0Z+Zfxx0xQlEb+aus1MxMbzXXlwvZsv4GV5l5rZ5l1aJQDglK81Qk15kpXpOjU9hLSXYeySlMtBBSqpefltZKV9qQWLXeSt4tZyLXpS0XkuLUcWpS8sJatpZyUrq4iae1SUpOANT26Ht4xaCWv+HlJa7j2Slqs4iaexRdra6NS14SkNLUKWsWvEpagS1F0ymZkJ5TktTxaxS1YBEzLWGWq5wnPlSy12lrNLU2Wu0tWxa2FlggNHry+msuoi5yPaZEtF+lJaexFor5amzUxlqtIDeWuUtetytkCQhqWpWw6LjNXG8wPYUhrvpo5zNJXB1K1HICVr/Zq2GuStQXMzBCM0qIjQZzPV/CoanmExuxSNSaQKviG5eFzw6cZrSx5/Rc0PDUaCSRMQx5mGLyo4vzCcOZuVrTDUyZG6Sl5oeyB8FJ/ZmI0x8NfFaguZzi0HDWDuAXimrwU6V0XAErXUcuwlCNawa14ahPDUDWu9maUGNK1M1rbLzHITc7KB+Aq1TLi3QjANCY5UPkT6Vb0qdzXB2DJqika8BIe1raBhNjxmtepeYwWy1r6tCdWq6qMjKk4YRSU9rWnStutTG86LVLnUM8F1TSPmSng6Ka71rtogbzIP/iXgoduK7c8MGd/0r9q3gic48M0SMFiLIXbuDaxiaM7cQbUmLKMOl8dSlw4iypKV7twEmlsvVX+hncmPyzMQZ/ipgpBZmndd8G3t0JXrAy6v+1izF8HALNc7m0vG3+bP8ZMGJHRcWQpg2E6QHcdKVUr1C7jkdaZeaCyAlmz9nswXdNLBZtbUEO7v/wqOg/gqJZtbUUO6YdyFIQja4KajsNlcAEdzz/rI0Vm1pFwtf4ZOHI7mDa1fBKf8RjrmEO7bkGPRjueNrZjqsd14WVudGm1Mk0sCFZLJyXigEqqaif8gKb2VFRUm3/GghQNrcAz4rzGmtba/xZWb9isGqLJJKM7ajRZuAZYTr22pVXob/Hghl7QDbUCr2xtTyvJBZGNrRCEnCiEWCdgvaaO/9vCEudwgWd1grnux01pFhB2oU7h4s3ZSIXdPf4YRG0IZZNJ21+hDhJrc2sZOjwKcJZy2Ce/662rKwWws//+1/VpHjAAMcIXho6hZrgjObXJTVJXodgzQEYNqI7W5LLHhRrqjVRFq8MHzFLN/kHmpWpZwIKCXzJqSqWUh4ZNSZSz6wl+r3dXqQAke18alh7Wd8qE9o2pAZZvQ0BELZbVoAe7qnkCLalF7UmPO7Ui7k8e1s4Y414BvC27iHqqBMYerF+UR6sO7gcITNeogCYPh0gpzyfGo9+FE2yeiGFr28XtXAYIICgCRomv2pe7ouKEpQoS1iVlf2ollDoAnwKYfdP7UwyQmAbcsnwKe/d/llfbQoIB33LPuOAVBgFI9wKCsQ8BQBCaB9O7PLJQdVja8wBKDrcAlsrLdCtg6zRaMRNJe6nzQIdbiAq5ZgQV6e6BzTWJnPqSJaO/dtSH08TiATg0ELu7PdcOppkIUYqkA1c6WSBX7VEOr6ih/amh1wRRtgG8OrtIUVEDYBVvVrHS8dFWAdr1UfkXqyQByQFBUWiSAmjqe8R/7UfAKyBGxyZ4BzSsCgRgvHl8Ix/bRMqoReJCVzVgdV6QnEoyDruHWF92Z7nf2SDkiPdjllmOp4dRv3fc60jwVAE0KBX7gg648hrfcbHU3ICo7sg6036nVpTHVCiiHopY6nx1CS0aHUka2qASCA/ml/5Jq/BddP5pfcQ6vwlP94fCKFCZAPupFAAKAALADWAGPUi8AagooABpewgAAAAMooACcAB0APHkwgBkADoACUcESeXmJsTgX/pQvDGAIh6M2AhbwE8AELAqABI4AAAXqyAeYA1EC35g3NhFoPE6uIAEAB0nWlOtNido4OJwDTqCADNOtJAA2mX2xkaA/mReAHaACIATyA8jgHAA+QAuQNCAYQAQjhLPqwAGmdZ5AIYaIYAVnWc/SadS06884HYAVQQoADjcHG4e4A1YA/FRjABEAGwAMAALgBqCggAFUcMIAJjwFQBrADEADx5JEKRD0Q/hYECpAEGdV4AYZ1ezqxnX+wAmdfbANZ1Mzr+wCOuOYAIs6zoAyzrj1I7OvWdaC6wJsw4BtnVjAF2daM6xRA1GgKgBHOpOdWAAM51NyYLnVXOpudWYAO51w4BHnXFgHedUOSgZ1FTrkXVigH+dTc2SCYgFBgXUbOrBdYJgJZ1zABEXX0urhdeexKF1qzrfnUourCAOScDF1pzrgFK4uuudbc6+51zABiXV+gEQ9Lacb1JV2lP/qUutdANS6v8CtLqW8Bsup3APC64QAELqEXXQuqRdbC61V1HLqWXVaurldViAKzAaLrhAD8uqxdYK6y51wrqCXWiupAAMS6wRwwjhiABQAGoKBUAIV1LgB7ACqOGLAJk6rJ1AAB1Ap1zAAinUSAFAAIh6ZtJFMwwMzSQDAAFU6+asn0BIZwFAGjdZHQIZ1IzqdQAG3wZ8rKAChQXTqdgC9OuDdf7nUN1IBAE3UtOs7+G1AAt1NzYelhTAB1ddRANV14LqVIDMupAAKy6st1AkA9XU1uoNddy6oEAdvxC3WtuvRdcc6gV1hSkQACuupFdUS6kAA3PJg3UwxzJzJZKQ11cSo5IBktjpdXW64YAFbrK6B4AGqAKa6zt15rru3W9uutdQO6xgoLzqNehDuv3nMfABQOebrRnV4oC4+rWElV15bqG3XAYHndcOAM112LrjqyrurmAIS6wd181YELwfHD3dT86xN18rrD3WpuuQMKW6kF1urrhhpzuoXdcwAK91Frq8XV9uofddQUJ91I7rZQBjutgUke6r91oYBp3WbOuHAOe6gD1IAAgPUrustdfi6u91qjhFCj2upEACI4J11ZgAXXUYevddQ1VL11t9oA3UlOsldTWrXEgnEJw3WRuuoKGbAQwY0ejPoA8pCg9c26zEAAKU2oRkXBVIDphWgA6bqenXMeEQ9JohT51lZA9tT7usrEFZgAjQk7rlXUIesZdRq6zl1MLqf3Wnur/day69j1rTr3CDYAH06B26zF117r3eK3usxAIS6h5167rWNiburedfNWYT1jqTFBqGuoLdUwAIt1vHqZPVKevrdX+6+T1+rrVnWyetndap6t91rTq5OG2evbdYu6nT1wHqrXVYev7dU860z1lzpEPSAOt30bCQS4ehrrIuVSevs9VM6xz1M7qz3VVushda56xT1DLqPPVNuq89fp0Xz1c0BtPVduvToswAfT1pgBDPViuuM9dTsML1ScAIvWGSkDynGOKz1anqbPWaer89ckxKd1SXrEPXqutS9Zq6tz17XrGXWeevzda263z1cnCCvXLuqK9T26jD1fbqjPWheqIAK86w8IuHr8PXOuuEAK66kj1nrroXggAAAAKIiAG8AH66kAAFHqL1JEnkYqAO4HUYlWdroj0erMADU6sRqdTrhsjieqs1G06jjeabrGCgZusE9fNWQ71ukll3CtuGg9VQgcZ1cHqT3XZlHmdUh6rr1CnrtXW9eqy9Vy6rz1+zqTXWAeqXdbp65D0JXqyvW2uoq9c86mb1W7qXvX9uF0ktL5D71anq3rj50QS9d+6zL1KXrPIDVutrdSD6ht1/XqeXUHOpG9TD6pQ4cPqbXXiuquABF6tH1ESxWVo3eqNdV96gF1P3r3PUE+tVAET6g11nPqVPXZer+dai6vl10PrAvWYeoM9bT6gd1JLrUfUsAn+HpIUV91fzq2fXSesS9fj65z1gPr0vXA+pV9Vs6gX15PrIfWoepF9eh6kD1a7qpvXpRShdXh6x11i3rivXEeqGAB66v0AXrr9gaFOtQAIG6g71htdr5KkGAjddU6neEuGxY3WsepZ9Zx6vFA3HriUB1yH49Zm6l71hApcSCQihOBrF6yT1czZMNBtes19QD6wn1aXrG3U9evj9UD66z1oXQ8vWLVSh9QF6g31QXrxfUheo3dcj6sz11BR8UC/hmsIBH6zH1OXrBvXNeuG9X+BTVAv3rkvWq+sT9d16jL17Lr+fVg+oG9T56mv1hOBKfWi+sm9eV66b1s3rqvWh+pdDLzQMdIiHgo/WKIHi9XQRev1fPqQwAueuT9a36391WvqO/UJAAz9c16/L1/nrCvVJMXG9Yb64L1U3rC/VD+ql9SX6rAkFPAR3ig9DY9VX6rv1dnqZ/VAurn9Qn67n1SfrifWp+vV9en66/1LXq9fU5+rG9TT6gv1Jnqi/VzetN9Qt6wj1S3qrfXMABt9VcAL11O3q9vX0+pe9S768EePTg6PUe+qY9b8cFj1cQFffV2mP99YhCQP1gShg/XPepL9WH6rFinrRK/UtOri9TH66kwDfqOvWVuub9Wn6+/1afrGvXr+q09Vv60b1O/qf/UH+r/9Uf6iV1L3rT/UfFl0CJH6+gN7/ra/W3+rj9W36+f1avrF/Ua+pEDS36pF1/Aajkjd+pQ0Gh67/1E3qjfUD+sP9Sj6/ANo/rBGDh/An9Wp60gNnvNZ/Uk+qb9Y/6qQNFAa+vXa+pbdRp6xgN2frt/XnOqUDfv6lQN7Aa1A1jgGwGGooLQNl/rO/WyBpv9SdWfQNL/qmXVP+t59QYGlf1OzqZA0axDkDWhgBQNLAbbA35+rYDZV6//17kB5vXm+uADZb6vF1K3rbfVreoAAHIoAD8AO0AKANjvrKPXzVltOJtcKB484B3fVRuoIWEwAC71xAa1/UOLHu9TgGx71Anq5gBBuvyDQ9LW9wJV4WfXY+u+9Q60vH1qoA5nULOrEDc/6yQNdAbwfXGuuF9V/6iINe/qog32BpiDRwGmAN1BRpug+DSKDW0GhV1QgaHPU+BoX9f0G5f1xgasfXDBsOdfr6xQN4wbSvUS+rA9VAqGZwLQbEwCLBsV9XX6u/1AQaH/X2AB59Sn6gYNr/qtg1C+p2DaMGmwN+wb4fV0+saDbMG1fepwa92GhgC2DRcG5YNyvqHg2+BuMDbQGx4NQwbng29+tz9WL6g4NIXqTfX6urN9aI4RINu/rrnUpBogDWt6gAAkgAAYRyDcU6/b1Qnr9mh2bxBPPI4M71cwBvoBljk+gJ78Fn1QJhrcCtcsjsDQAXANDQaiTyCh3wwCjkRYN0RBYPX+kCwmA36noNNwbEQAXuqYDVT68k4cPrHnWqBuL9ZlwIkNL1SON7Qes5DZ+67kNVwbZnVgAH+9Z160XAgoarA3MBreDXn60r1nwaiTwW3AzCjF6+gNqyAuQ3JGGEDfYAPkNqoa8oDqhs/9dYGnF1kQadQ2S+s4DdQUKLgqC52Q3y+tGdXKG4t1PIbp3UWhqoDVaGlD14QatQ2whoR9Th6wANCQa5gBEeuSDUMAJjwq3qDwggAA6cOt6gAAIskAYcA0Aavg3twBBwutQPSBrbhSQ3VOqQyOUGrQIxfB3Q0F0BfFftyG5sE8AmQ2YgHTDcVAIaas5Bg2XaBq89etkXl1C5dj3U+htydVUAX0NMEhvViWhruANaGwMNdob3g1ihocDRKGuKA4k86w0GBTcDSwceRWySIlfVdBvNDe2GoRwyoafIAN4G7DX6G3sNAYbdg1jBu1DSGG4/17cAtMSCFBgWA2Glp1TYaOwAtho59Ul6lwAC4bOw0rhvkVv+6y91m4agw23Ot1DRF65WA8IYkmRAQMNdSeGmcNuPr4PXteumdXgAONw14b3XG3hocAP+GuNwX7p2KigRpEAABG7YAFgAz1JjEDXDQKGjcNrwaBw3bhrtdWGG5ENEYaQA1RhvK9bGG+wAaQaAACqDTh4ADrerSDQAAFXW9QAAJTxDU76l8NDQBXfVk2BKDQx611ItZRyg0xuraDbUQdxAc8qvA3dAErDeYAZ319Ea2yhLUnODYe6xDwggDfw2rBr6Df4GnwNZPqqXXWQGSJTaGzUNqEbgw2HBt3DWUYJYejC9Jw0tuoEDT36y4NZoblPWiBuoDa/68EN4ga3/UeBo/9f2Gm919oaPg2OhpmDe3AQSNKbgGwBaRvldfJGsSNqeSJI0ghrWDdJGkENskaXI2iRtlAJZGvT11kbVI1OhvbgOk6I7405diw23evjgD8QcsNiobPI1SRvuDRsGwYNA3rFEAPIGhDXsG7cNhwbxQ3hetgDeFGmEgzrhFg0jsANADS6yZ1c4ahgCdhuQ9feGlCNVkbBw2I+qq9WpG/yA+UbURiGhq89dDhEqNekaVg3dBqvDUuG2Nw72Bfjh3hqFDX36gl1Q4apg2OBp1AHEwbhWIyZffV9Xg6jUCG8qNA8Aeo0qhs9YANGqqNQ0aYQ1PhtsjdWGt8Ak0a0AXORqNdcVGk0N/9hgQ3mht6jT2GpCN1UbbQ21RrQjVtGg71m3Rj+CsNBZ9T8QXz1xmBxI0mBtndV5GpKNBkbNg1V+rSjSMGq6NQUb3g2qRviDZhGzEAkYa0Q3RhtI9Wt6yiNq8kHfX4hrsjcAYE+gjq5RqjZlDJDZiAGp1o6AanVn1CmAPQGisgLzBpPV8Ru2jTS8EH0PTReNqLBqH0YAaH8NvIalo3Lhv6jauANaNGobhQ0qglFDfVG2INjUaaXiKoBBOGTGqKNRrqKY3wzNbDReGmmNfUbTMCrRtDIH2Gh8NykbNo2hhsRDUAGrCNSQaIY24RtSDXGGhMNiYblSCphtyDQSG+asw0UzWr2EkQDVG6/MNl1AIoBFhpxjV56woGt7huI0PetY2E965kNNXqv4D9oGA4J+GnmQzYb5Q2IoDKjR5G+cNTgAOw1nRs9YKuGwaNjMbho13utGjUj66YNRMbhTbwIEvRA7GtT1X4aDqJ0ESVdSdGiqNQsaFaC+xoZjYpGpmN4Mbgw3Phq1jdLue2NLPro41nhq+QG7G6mNnsbFw3LRq7DbeGlONgUbYfXWRszjbMG7ONCshmiA8xrzjS7G0mAhcaEPVgRqAjaZgX2NUEaAI0QRpiAO3G09SKAAEI1+xtTjQHGgz16EaZY3hhrBjdhGhWNCPq8I1DAB9dfb6/11GsaEY2z4FGGlGkdYYTEbzvWLuFjdWJsFn1cSBlgAKRoZDYTGg71mOEuY3fFkWDUIgVWxDIb442LRuLjR3GknAm1xh42Vxup9dXG1mNIcbSnVqPKCGpUGql1l8bskDXxoWjQHARONK0axIBPxoljddGjONb8bxo0t1lKzuy2XMgF8beXV/xqPkPpG2+NXsbS40N4EfjRXGsBNgMabo1HBo0QJ/Gh+g38b5XW/xq9DfFGj2NqCbaY0ixpATZgmmqN2CaIE3SxsbdUiGgj1csbUQ1uushjXPG5gAlEbyPXLxqJjT2PO0arbQ9Y0MeoomVd67GN/waq/V4xp1oCQmvj1dQaQ/XUFBDWCIrO9I8kLoPV8xrWIP/G92NCca743expgkKLGtUNyEaAY1VxrqjYP6qBNxMajtx1rkUTU8GtqE/MakE1dRrITSXGihND8b6Y1ixt0TUpG8BNUsaEQ0MJtljVPG+WNrCbFY0YhrjDQ04AAAgtiGyiNAAB5EiNNEa8g2yJuzdfJQSkAAibzvUsRoy2QngdiNPMaZOVcRpBPJbG6nY1saqw1Enm+8HESpqAIkbeXVuRq8kNYm76N50bwXV+Bq+jU56wIN0gahg2uRoCjVgm/RNWUb4Q2hRop+JcIyya/sAzI0hBs8DQLGySNRkbTI0mRt8jd568yNggaR40bRuUDTuG5pNU5B1VjdEqp4PkmjsAhSbhYDIJsb9YZGowNNAbrg0pRtGdbUmjKNW4aVI1NJpXjTS8M/wuBELYBPRrFQLFGqmNJkbPo1L+pKTRCG1KNeXqtk2PhrGTUHGhqNEyaaXh/PO67sENZJNLoM5o0nVhLdWomv71vQadE2XRucTbQmqWNOUbh/WyJqmPIcm95NJsaWnXtRqOjdPYIuN5CbhY32JtKTaGAcWNNCaGk10JtBTezGqJ4N14Bcg8xthTc3G+FNbYaNE1oJrpjSim2AAaKa9E0vxoMTdimnt4evQ8U3QptGdYdGwlNKeAAE2VRscTYCmtON08a6E3YpsuuPSmmUNRoaXo2zht+TUsm/kNZSawQ1rJuuTWv6v6NLwaqU0ihuCjfCGkGNTCbPE0sJvsADGGpWN9gBcQ00AHVjfDGomNQzROqhAQNzDaUG/ScYEAsY2Rxqr9WP4dnATAB8Y32euPjUJ6ivgBqajw06+vpDeeG2Z1QCatE0OJoBTetGzKNmKbhw25RudDSn0R1N+0aIfUupqKTTfGwBNJKa7E0oIG0Tf6GzlNo8aHQ30JqEcIwmi31qqa2E0apqGAIRG4iNXCbdU0HeuDuhSAcSIrEBN43khviTd9sON1cvrGU1igE4jfjAC2NGYg7U0verExFVtVE4HybNk1nJslTaCG1ZNMkazA1+RoKTXUm9FN1KbGk3G+ueTbHdfNNDjRjk06RpQ0N0mhKNvSb1g1XJtMjcEGtt1wybn43ypqBjbsm0ONTrCg9WjpubTf5G4VN70aufW3BvKTZcmypNP0aFfXbpu9Tdsm/v14ya9k1e7HZQA8yY5NMUauPyteuKTUemlFNdwbD02ipvWTeYG25NZ6b7k12BpDDVimodN3XAb000GCKjQUAL5NqibeQ2aJuoTXKm5mNr8bDE0jhq0gBMQdxAt6b8U2zRrhTaymkVNl4bI01IpujTZ6m2NN36bJY0jRsgTfBmpdAvOF2hLwzMNdQSmndNxKbEU0K0BjTeuGuNNoybA423Roi9Q1tIMqaxBoPXMpqozReGyDNHKb8M0uJsIzbgmu2iF1YkLw8xuejc1616Nrqap00rJuMjW2mgZNNip0o18ZuBTQ8myX1SqaU03LerTTb4mzVNwKCl405psQ9ILMXcMwe1UY0e+pNTXiAM1NxybLU2gJhtTcsGutN1BR9M0ZXyuGOTG3l1qxg3o3UZtsTdhmvWAdGaLo2KZoxTSCmv1NYKbgeIQPFjxpKAdjNTwanM0spvIDa5m++NOGbyU2UpqBTT5mgTNbiak00eJtMAOnGtVNUMa4w2ZpvgACBeNMNpTrG2KBeXwBqd66p1JabTM1JJorTa6AKtNKbqCY3SJrwDU6vF4gNYxSICfetPTY+m8NNlAb200yZs7Tav6uSNTWaRk0+povTTXGvxAeWbHTpjjA6TQum3SNzWaAE2tZouTRIG5KNUqbtI1DJrGzT1m89NymbBM1bhn4QPlm4bNAIbus2TppmzW1mvpNsmau02s+u6zUummDNK6bB01XpriWEb2MZgomaTk0Ppo94osmybNiUa302tZrkzVZgBTN/sbGM0TBr/TX5m9mNDjBnJXdMBAzdamtDNQZBFk3spq9Te9m3rNAmb/03nZuTJNq2c1NMKbUM3hZtITeommjNK0bcM30Zu8zf2m31NY0biM3TdDCgASgGaNP3AwM2SZpsTVFmjzNaOavM3g5qWzUxmlbNLSwdNT45o+TZxm1tNSobS41QZrizZjm1xNzybCfB05tuzen6+9NEmaw00TZrk9Y9m6bNs6aXs0ypruTQRm39N48b3E2TxpSzdymtLN7CaQACURpKsbt67hNRJ4i+iyrFLmDmGotN6MahE1mZuuzeIm6tcf4FOnXVZptjfNWDXN81QgAYfJuUTaVGpHNKCa3M20ZvJzVMAWLNXKavE2+Zuxzf6mnFcGqwTqjkxosTSomyGgrcbBY1YZsdzTFmpxNruaWE2uJtUzSiG9TNPiaMnVrepVjYvG1XNumb600ykxZ5DNCFFEOubTABUhvtgongI2NwqhDXVmxoFADWmopNNmaP0CEjA55EfaHnMjsbpw0xxpOrHHGtlN7qabw2r9FZzeHmlmNcGbPc0wWBT5oa9W2mChBq82chvzja7Gu3NEaaUc1lxubzbxmynNP6ax43MZvrTWSZCvNU/Re81RxqdjaeG8LN9eaMM2N5uAjWPmsHNi2bJ80Jpp+ze6ERFu6mS5+h95udjbbm+7N7cbNE1N5r7jdBG8CNBaZII39xrgjYPGj5gLeb4007hqjzcwmmPNs8b003MAGTDSrmnLNLGbOeaZFEmwJnm3PN6MkanV3Fij9aSkZr1iCaFQ1SJqtjfUGrJNLGatHycfTQwI7G+BAP8lvk3ehqDzSPm9BNnmbnc1h5pfzY8mtmNQ6bl0Bp7IU3mVm27EaBbSIDgZsizRfm/qNuBbUU34Fo+zbvmt/NKqaP83qps0zUMAVWN2abaI0p5uRZaCAQdAwBbUhjlBsWoCz6zvovnroC2mhsZDabmhAt9aakC38Ftzjcns9At1BasC0O5pWjfQWilNjBaIc3U5qhzaHGkgtHqTiUCoFt5dVQWqxN4abMM3YFroLU7mhgtDGatC1T5sTTQ660GNcuavE0K5q/zSAARMN3BaIk2ZcGusM/9I3NRmao3VCFqu9eAWnQN10BxC2SJqkLXAWmRN0DDs/jX/R8LaIm48NihbjC0wFqfTcPm1QtWib1C0u5oILURmjvNhXB+dDeFoazYvmygtoRbTC3r5pFjWkWzQtVObbC2JZvsLcqmxwtqabY806jhAANiG2GNOmaeC22ZpFgP5ObXNaMas82OeA6YMIWrRA5maghxtQCszSdWE3N4Raas1jESswNBg4NNwwbnM0B5qHzWYWlIt6CbLC0aFusLeUWhNNOhaiTzfnC2uP6Oa3NYWbT81JFvmLaTmmEApRaVi075tfzRhG6otqWaNM1x5rjDdiG7Ucf+b5qzfXH9wMBtWJN5Ibui2mppYbP0W/oEgOaYi1B+ukLfxGvTNGuUti1OpqpdUL6mYtnQa183B5tRzaHmk4tkubbC3rFoBLRKkyYtjmaOwBgluX5Q3myEtHqboS0Y5uXTTgmyotyabo82gBs/zRwWsANDHhwk2axudDQp7TyFxQbOi255vxmDU64lEUfqRFbKnEfTaXm6bp25wlIWbAUWDR+ASxNAuaIS3mFpFjUsW9ItTBavs0e5v8zaOoHwaVJauS2Huv9zbyWhFNCxayU2IRrwLTCW/jN1Oa8S3JZsuLXUWzJ1ASagk2hJsxDWSWvZNIbr3XhWQBeLejG4rNbEb43XJJoqzWWG21NfxaiY05Jpo9caWrdNPaauM09JukzXtmjrNQQaak1HZvqTezm5bN7MbDS07QynAGOm+bNE6bic2zpqmzbum9v1npb3A2dJosjT6WnEtOyazs08JqmTXy+R0t5BbcujOlqZzVJm/dNEqaPS3VJpPTZmWifNsJa4Q1JlvVzQcm8v1KYVrs185pdLdmWoYAr6aRc3Pptmzbd68XN2JaTs0DpsmDcHGoxNeogKy2swABzWWhcLNPyaIM0s5vHzdvm4stIpbOy3EZptYt1COc4BObQM1A5rmLcUW5FNiparC2tlvTje7mictWRbylzSupANPtGyjNWZaSc20FoFLViWostKpaKi3PJoteG1CHctfZaic2ylp9DTxmrfNx2a1y0JZvPLXymmV8qxhec1Cpv3LeGW4XNkZaqk3p+pbLSeWpTNUuaVM3nFrUzYSW9gt1xaLwiBJpCTfAAAAAEvqWnhNUSbpNqFpppLWaWxJNFpb0y1WluLzQsmsItGSb4C3/FsfdQIVdlAm6b0y1U9Ny6DWWnbNEZb+k0HZozLXMm3tN0Gany3AVpWzQGWgtNwZbYy3DJu2zd+W6dN3kads0vZvHTWEG+MtbZbEy0D+v9LSmWwiYTabSK0tpvGzSKmh7N3FaKk3vpqbLYdmwsto5bTy0llpErc8mtWyQGah8BVls/LdJW38tYqaWPC5lp8jQdm+TN/0a2c0Jlr6zZkWsUtkyap5HIZtIrYzmugig5a7y3DlofLYJWxitcJbvs0aVohTUhm4DNKGbCc3zlpBzYuW6LNy5bli2rlu5TeuWp5NeyacU1sZtnLYDmxHNgVaMS2LFuPLSpWoCtZ5aoq10prIzSFmoYNDla7s37FvvLXhmwCt8WbVS0vlvZLZlWu9Nulbcq0tZqFzXJWp7NpgbOs3Nlq/TYVW30tTFa1S2y5o1LUSWyCtQwBKI13FrVzXpmjz4jKx4a7UluMzZjGj4tBubgkBDFq5UKyWt50/VaDM3lptiLSi6v3Nexaii2JVoVLaAmvtNFlbIc2eVr2TQNMf3a3XKlE2LVsVdYHmt1NK1ajy0hVqFLTYW5gtoFaCS04Ro6rfUWlWN2Wbeq1axvmaKaCIitGeaaS0GxtpLWoGGkNpYbsK3I2Fwrd06iItrIE8SyP0idZkfmxfNNeaB80txoXLSdWknAycaRy2PlvCrZtW0UtP2axxR48wOkDeNBfNjYal83fhtjjUdW7qNMNaUEBw1tcretWoStHOa9k2U+GYyAL+UGtmNa4i0Q1pXzXjWg8tpKbO43lxvhrW5WxGtxVbya00XkqsRjWlAt4Nb+8301qHzd3GwCNh5bYa0gRrAjb3GrIA9+b4I1P5tZrSTW9ytl1aJ40OFvarRBWu6tSYbKoA6ppaLT4QPyhuJADBxl6GALR9WwsN+ea1PWF5u4AL9WwsAU1aTEDbRGsgN3g3qECha6a1LVvRLfyW0Wtm+aCq0pVqKrR5W5GtnOara3eck0kEbWrGt9tbDq3Q1qdrYTWlmtxNaGK3s1rSrUTGnNcCqSba21QnILU3Gh2tfJb5S3M1pdrejmpqtG1aOa1R1tGwtbWtpkcdb5q1KggDrbjWwWt5+ama3O1qvzT3G2/N5dbAI0DxqHjc/m4Ut0uaks1tVvlzVcW+otyYbzqnNFo8LTXcDH6yX0TS1Z5v8LWAW/aNYhaoC2hFotrcvpUgt4Mz860lwgKLX+BJytKhbDi0MgHD0WtW8Otbuaka0blusrd6oXVRBvNea1Y1unrY5WzAtx1bg60eZuOLWFWletqpaWC01FrYLelm/CNREb4ABeIA1rZ3W3ywzP0QkQoVqKzZ3YBJNZabCE1YgCwrWkm2tNtpbc01CJvqzbMm8itX5bGy27ZpnTaA2gZNtFbgG3p1tJrX6W4gtABbn61sVtGzaGW28tbaaqK37ZvqrYMm9itC2aEa2n1s+zf1miyASyJ1s15Fq9LcpWzitoDb0G15lsazcpW3BtEea4G1Xpti2D6E2Zgk9bWnXVlpAbQpWsBtPFbRc0mVtezWZW1vNCqbog1r1p+zYBmtZEzDaOM1zloHLfvW7oN+Va061u1uarR7WoRtAGbEM36QH+zX5WiRtFFbkc3J1qXLUvW8ytsDbtC1bVt0LaRmmZKsVb+y0aNvtzfPWniAx9aYG3y1svTboWg0AeOaec1bBpyreQ2qF4LlbXa20NrbzXvmnUgxjadK3iZrMbRw2yhtxlbMG2mVtlTbo2mxtwMarq3v5vArVfWoYACebtM1J5s1rS0mg0qI8h9a055sNrTTwAvNP1af60l5r/rcG6mGJn5QMm181pPzYHWhKth9aorqp1opzXI2jOtCjbIq08Jvybd781xcjcbsa215sBdaU2rRtIdaKm1KlpPrXQ2zOt2SbWFI61po5k02wutdeaGa2aNosbY94TptK5brG0R1t3zSVW47IDTaDC1FNuXzYnWigNJdao03MyrFrdfmiWtjgApa2P5sGEGdWsotpxaG61VFrArTdWlWtmTqE81NFoSbQ/WpdAiYko6D40F7rdnmtZYn1bjY0sNpNrdaWlktuTb601KpH7QNkgY/NyzaSm37FqCrRs2yZtoVbpm14NrWLQY23NNPzb641/NqWbTjWkZtQdb2m0gtuSrR422DNXja7qzfzjtrfzWlZtNBbS60dNtRbWzWiFttjbc0125GOoHC2/2tOLbAW0tZrWbe5m8ptVdbtm1C1tgjdLW/ZtOjb+G00pvPrcrWmJtzAAVY3igHvreSWzwtUOKs6BNRkebQbWvPNhTbTY1ZNvirf9WzJNBFbqCiEk3qUB3iIZtVLai61tNvGbS38QltctaZm3jltqbSyGr9EDDAF+zYtuKbaq2oFtBNaUW0HNuVLalW2ZteybjVwKGED2Ea2gFtJrblq1lNtjNaC286tqxaSW1CetjJqkoG+Q/zaEW2tNqSLUy2kWtBLbJa1bNsrraG2mCNNdaZa1h1rCbdq245t+Jaom1nNu5bfGGpMNc8y4Y2JNpu+P1wgpgDzbCs36xrSbeK2xZtkrayhAfNtyrRbWzCej3AOqB+tpabbMWtVtwbbzW1stoyLe3m9et5batWCqLirbZDWmzAozbzG11tvpbRa27ptnja5m03aEZMA62/1tNbbTW0utsUgKHW9xtRLaem2R1r6baXQHokbbb4W3VtoLjcXW6/N6rau43i1vDbTs29dtUbbWW111ourWcWxWtFxbm62alrW9arGhCtB3qUZkpkkuHkamhj1/daRC08xqHrQ0tOgiIxa8K2A1r8JVlxelYChbd62Ittrbfi2o+tgpbDm1jlsILe/GiL117bgwT7Rp7gEYW3Ftc9ae20L1qsbVU2vRtFRbOW2ntturZk6zLN8Tb7i0l+rzTerAbK4jza0K0f1uDTd/W6VtFtbYc14doQEk6Wuit/jbZK1ulvAbRw2yBtZFaFI1ottOzepWq9NuHaKoD4duuzfxWmjt1Va6O1cNogbTw2njt/baBG1sdrXTUQ2zjtlHbJK1bZrDLRQ2n8t1FbMG1QNuY7TO21gNYnar20FSv7fskgXxtpya9K3nJvk7Rg26Mt0qbGq1IdvCbb/6z2tDDbT8wu5WvLUDm2etzOb/k3Ttq1bcS20DtRiaE5mEBq07eQWvctuna4O0AdqOLUB2y1t7tbIW3mdsMbWRWvtMu5aEc3+NoOLfB2yxtfnaRO00puILfY29fltebxG1xVoi7TI2yptLHbcS3EFu8baF28qtfjb2G20dpzLR2moJthnbP00b+olzapWmyNdhaE22sFuibYrmlWNPVbk804dpe+CDW++Qb1a8w35tsA4H7Wlp17zaza0bgDI7aVw7ssVpSwa2UtuNbX+28dtyLbe20NtvrrVZWvfNKxpua3P0mVbaN2gNtzraJu2uts1bcvW2dt1rbdC1KlEG7fzCYbttNaVW1jdpW7Ru2qdtsjaMu08pqy7W3RebtVebl20dtpjgF22ndtMEaou0TNoZbdu2plte7afMBTdsPbfG29UtaHbzm3x5tTbb/mx6tzoaBRQm8A0AKK2jrtX1aeY09duybThW0etKBCkdDGYHbbQLW/9t6zbJu0Hto9bc524jN3DYOiS+ttu7Sj28btJ3a3W3Adoq7QQ2wrg0eYQ2BKtvjrc02u7tbeAHu2Rdp87Wt2vtt4LbNu2etvM9RT2nokePaRu2OtqO7RNm2ltScbNm0V1vbAHfm3dtD+ba62y1o27Z421DtThaW62ZOsojQ9WxrtI3Tys6G3xfrcamkatfRaxq3fFoSLZIWi2t8jT6Aa+5ulLYUWx2tq3bou3rdtjbU52mbtzyb2hh4AxIbYL6g6te9akW3qtsQ7ed2yPNkTaau1Jtrq7WrW9ut1zaBW2jhq8pNfJaaNubaGPVits67RK27rtUra4o2wFvfbWMW/yAlSBv5IcKmR7RF24Ft6PaJe3m9tZ7Vj2zctCZQyPaQRBHbSu2nCtx3bnu0atuZ7SZ2uNt0+aS/V9sjI9l7qXPttPbHe2F9qJrQ52yXt6Lah02AWnAgkEYRPt+Xb+e0+xsF7Tfm4XtVdbmW17Ns+7Rj2o5tIFbj22nNpnjf925WNqbb+W1XpvTVIi3WF0RcFUm3PNvSbYW28Ptxbbeu2KQDI7VL0HV6YEIbu3c9tHbau21HtdLame1fdsx7Zb2mftbMt+XqwIH27VOGw7ty3bje1E9rN7ey2zLtM/bSdIs8h37df2gutt/ax20F9sZ7ZO24nt/nb5G1bdud9a/27vN1PJt60HdqW7d/2vnt67a6+3d9sZbbs28XtMban+08pul7bUW9Dt6Qab61ZOoIjaSW6ftoca4A1tJoI7W/W0tNpWaWG0pJurTbD2v6tm/abMRJEpiTVR26BtlVbBc0fRv07VQ2zbNNDaVO2idrZ7eX2wSNBA7uO0hlrQwC42grtdZaD00NloY7UJ2vgd5XarW2Vdp+zfdGmgd7SbWB3Udvy7Xx2wrt7Wbiu35lo2Td6WxztrPaQo0z9vhQIvBCltA3q2G1edtdLcoO90tqg7/y3Gdpd7ctm+EtXAau9F6Dus7ZI2uYtaXaum0s9rbzdYOk/1cRxv7xQppYbZ52hgdSdane0xdpcHbBmtwddRKgiD8ps/rT4OlxtDPa0e0L1oCHSX2i3tK2bChS4poFTdlW9Rt7DbQc0N9rT7QO2l/trBEGU0sNrEzTp23wd+laX03CDqKHYpWkJtEg6Au1SDtQHZfWxXN2Ibve3YdtvEEWKXVUZA9fC2CJpMzb0WkRN6fqLM2DFokTZ1GsttTQ76TiTjGRLbtISPthPbC+3O9vYHQYm4IdwBgBh1rTCXbZCG3YtnUaf+3RDtN7cX2ywdZ9a3e0X1tq7S4W5MNieaGh0aIEGzdBJIatfhbt9C9FsCLV5659tV8arE0W1pfpWiPYEtU9aYO0z1qkbYzWlYdty41h2TDpwTdMOt+QrvMdFJQdviLUb2vwd4w6Jh2aDql7ZsOrltnvbEw31DuB7S68K1q6hVjh3B9sh7a82zJta/aKB3m1q+bbIm+kE0YhJqLt9qdbff22Ad//bYu2fDqhbXk2szCbHlsR349tg7QfWk3tL3b3h0gjqb7VFW7ySeby/h3DNrv7YCO3/tNI6T+3D9pWzWEUrl65I69+159qhrWfmmAd7I6i+2Pdp77ZwAEXtkbaxe3RtoyHcgO13to/brq3j9uTbZlmqEdivaDh194kk7egJIPtcSaiB0lZowraQOkjtVWbRi1m5tmDYxYCjtWo7pO1kNtk7QE25gdZg75B30DvWHfg2svtA2aNR1eCjkHVf68Qdig6mB01VpEHc9msQd2Db5A0fDuErZwOiusa2bNR3ujoLLQoOowdtZbxU1Fdt4rTRWpjtiHhHR1qVpDHVIQVCBVnbtO23ZoEHUoOoQdRlb4x3BNt4baE2uUdVg7iR0vetQUDwGrJA9g6AR1Dlvs7Wd2oMdEVaiC3Q5ts4hmOjzt4Xa0h3J9piHY/2xttXw7La0T7K42CY2m8t+fa8R0ijuBHY32uLt5NaBlI5doZzakO6Mdp0a3G11jrpHeOOomNXOaKA4Llw/LXl22cdXFb+O3yVr9HQWOgCtcQ6tB2KprBHX925NtqsbcB16htOSHZvBEgwBa9c0ItvT9eIm9n1iRbde0OpvY3voOlg4waAsETVjrxba8OyLUsQ7kx06tsbHXqmlHIV46FC0fjtDTZIW5YdR/a3IDInE5HSB2kftMuala0njsVzZRG1UdGbaYWw6qglzJXjVod53rbx0a9vILZdULXtHTqKw3ojuB4ufIVohc1b9q2G9upbcOOn8do47Mh1BDtLHbZmsidWYpWo129qonbiOtkdtE6/x31joSzdUO7YdxJaQADeurgABYAS9tiHpHNQOcTLLB0W4zNl3qNUDD+mOTdUG1tw6SaAa0x9vmAFFimLUJ3rJK0FJtS7fOO3MdcY7uG2Kdu2DRUOwAdlXaex3iTp01BfFKYtgIbCh16dp9HaUOudNCw6KfWEjuDHWT21Sdf6AZ2Gh+EsnVpOr0de6bdJ0qDvzHSV2+V1UIanJ2WVpWzWZOsKAdQzPJ1zJt47d6O7cdtVbQfUBTt5jby6osdL+aIm0KjsTbUqO5CdWHboR3jFqZ1JhOhq+d7acJ0ETOETXDmtf1hubte3K2AtrSmYFK+NNaFq3sTt57ZxOqCdwE7aR1jjqJHUF2jYtnJRbdrsYAN7U5mykd+NaJ21NTtgnaT2+CdjdbEJ0y9rPbXGGxMNWU61R3+QBIIir2x5tD7bJZwQFuCQC+2jAtvEaSJ1xQAYgPr2pptv7blC1Ujqd7XRO4sd+ja2p0vhoqWoMQH9tjw6He2H9tozQdOxttrVbRp1oDon7ZqmlMN6babm0HGjtGpI/Aqdrxb2h3FTs+LVamstCPxbag3GjpkLfK2lY0yjz7h2JTpRLeFm7wNfU7qR3x0UGnZIOjPt69a3p0SP3BnSGm1Etx0aaJ2NTrhnUP2uCdVXbfu1jTvQHX4m6CtoSaAADiok7zc1IVtFXoMgYAthHaSB1jusNHTaWoGdcrbHehvvnNHRGO9QdVo7UG3GDt8naYO/ydag6us1sDsXHe2W1Mdmbat6hUzqQbUN6hbN2Y6Yp0mDvo7buOhKdTXrPA3/ju0HcmWjIwbM6gG2HxutHYIO2Mdfk79J0JTqU7UmOnidLVaNK3lls07W+Olt1hg7rJ1oNttHXzO8wdZXbgp0ljuOnebm15NduUqx1PDscHTpO5wdB47XB2MTsTFH3omzEA46Aq1jDpHHdxOoWdWObFG1RVu6FKuOsLt/lbpW2QTpDzc1O+idS47sk0ZVpepGuOpxtM46rZ12doMrWC272d9I67S2vlrTnftG/IdWY6tZ05jp1nbzOvWd/M6Gq32zsCHax2o9tCE6T20EzsenRmmm+tHThgk3YhoAANLkzpB7bD9Hgd2E7i026jvNLRROrH1DM7Pm1Mzr1TToGWQdGs75k1/VqqrTLOnmdcs66q36zsTHfRWpOdws6XJ0KQzN4nkm3gdAY7+B1lzoXnRXOped8U7q51YNuQbQJWsOdIU72Y3MGWnnXQOzWdXM6Yx2GVr0nYJ2gydUla8531zpcncDESFN5s7oo0VVulnT5Oo+dAnbRB17josHUbOp0dTbbr51gOk8HT/Og6Nmc7dp3SNs9nVM29+drU6I51R1q+km8mmBdEQ7rR1RDqxnTdO6btEC6re29KS5zYHOuOdmM6E53wzsqHZvO+LluQ7ku2mNrSHU4OpBd/47N508muIXZmO/nNQ46ZK3lzqfnbrOl+dCs7Cx1GTuqbSmOn7tTdbm53JtuxDe4W33tbzoPblOaUebW8W0zNo1b8J1m7T+nRNWjbQlU7pF0ppGGHeBOwUdwc6uJ1djvwXT2O6F0ioDNF3ozs7bbX2kOdei7vu3DTpObYqO7xNhM77ACqxtQnTc21tIdw6N400loWnecOkgNwRbh63uzqj7cpOk0dG1RrJXScj+HTtOkwtZC61C2hzpaneHO3VtiHou3guLuCXRdO1adV07wl0WLtP7XjOkRdD07k20qxqmnWhOzeIZKCE2BiQIh7Uv2gtt31aUR2kdvWnT6OFSYVNbpfzY+mp7SyOqAdDU6Be0EjrrnSgu6Jd5ubYiBpmNrUGT6avtBPb451d9qaXcgui7tDI6AMxVLqF/OzOz/tkA6D+06LqxnfX2hcdkS6ya0FzuGXXRoLpdi3aee2sjtWbcKOn8dm7aw2299ojbdXW6Ud+7bU+2HTpQ7ceO0RdiubMs17DuynavGoRI4laxoCEDoMSO/Wumdo87bOIltqUnbK25cdZo6bl229o5nVGOrOdj876y12TsY7W/O5Wdq6bcs2ujtYrbvO8+d0U6AF3cLsrnbwu0+dis64y2XzvobaHG0oCGSASK2kDtXnVCuwwNss6gF3yztPnQbOtedRy6hF3OjrTHdRAldIuXaCh3/zuxXYvO3Fdy874V38LodnUxWnsdv2atK0lTqpdc420JdGGaGF25zqYXWf2lFdMObyV1qNpS7e2Os1tvnaUl1cjp7HbjmsqtQq66F2bju7beYuxOdRK6RZ1H1Ec9iJm+ytcC7sF3crvdbVyO9mNK47pV2KLstnVSu5ZNOK6dx10rrtnW9mgZdV86+J0e9pcLdqWmCtOA6Xp2SLonUhqO/y4lkpPp2mlqHnehWked4Pqx52ltvKXQ36CZArq7LJ0ydofnZRWm2dVc7qG0/LuBXaWW951g2ag10SztCDViu41dNK7TV0nzpGzZLOwMdSK7jZ3nZrDHfGuu+ds86iU3WztsnQp2ledQK6wF3EroSHRdm9nUhwgKV2lztDXVuOk1dcU7SfU8Nv3HdGujstrS6S/XljurXenOlIdwq7Lp15VsQXTyu8tdAE6wO1ljuTJBqUHtd8ObY51J9tFXZ2OxVd3Y7fZ0aIDeuGCKcGdWC7613yrt0XfOu/Bduq76lIrrqmLRyu9ddrjbax3pduHXS5OvVde67a13sLrnnYwO6Fd/y6S130rtbXcOu1Kdjc6x+22LpbnTy2tWtFy7pp1j0Gk5JlQCStlTr2u1FLtD7Sv2zLgEfbGZ3R9v8Xc5xQ3h/aAxl0lwjqXZMu3pdo+bxV24zp7HQq246gsG7bsTwbsHzUkupDdW67LF0rZttbT61T0AKy79+3YbqmXY0u5DdQ06CN3etvrjRhuhOt1E6ZK2d9tw3WKO+AdovaWW2D9sOXbdO61dGU6XC2ZZv8TYmG5MN5466I2bD2FxPCOnUd9y7iB36jvpnc8u9ftxE6J50CRqWHrFwT+tBK7Rh3zztvXSUO+9dka6HR1PrpBXcJu1Ye+eVi53V+q6Te5GuydgTbbZ3zpozXRfOuZdyK6FN36bpmenyOyMd9A6XM1Frtinb6Os1d9o7lO1ZrvAXT9mgXop4DYrWXrtU3Teu6ldgC7U13NrpAXbXOy1djs7UF3O+uaje8MGBd2SlBx3aLtMLVqukntCM6+V0xbvNUGsiMT1Mq7Et1M8Bw3UlWvDdqS7mV0yDsa0EREEhdgW6Gl1QlsK3TquodNJW7omX7ro1XeCWmsdOc7tV24zukHbtGg7QrE61/WGrpM3TZO1zdAK6W12gLq83RWuu6dTc6Ml0QjvYwEJup6tO89d9BdTu1HeSGkPtUPbyC0w9rKXfJu22N6JDhW050G6Xb1Ol4d0y7Tu0nruG3SOulztNptUlC2uNqXV/2hDdYS7mN04zqo3bquuuNsCVwB039omXWRuxDdl+bqt1tbs5zfduzoC226GN3rLqe7SKOrZdQvaJR199o+7ZxAG7daW60l33TpqHS4WhPNPc6XXhB6vGgIUu0zNy/aSl1ELnX7WtOtbdbS6TRrWtRBPDiO+qdcpaH+3vbqo3T2OzCeQOIPF1PbtWXfUugnd+I7KN0Q7t5TZgWBpAzI6Lt0vbqu3W9uihdxk6XJ3gBTJ3Uzu57dSW7oB3/bs2XXAOt7tCA6ZR2zLvXnSgOk5d427bV3EzvgAIJux1dM/bBI15roHnR6uiTdeo7vV17Ot9Xa8u/CteA7qB3HwDDdfmu0hdnC7D50wruPnWFu0tdGg7rN3ZrrwHYru/Xdii7hO1yrptHcWugzt9K77d2Rbqt3XdGyaNSu6MV1vzqNXQZWu9dzu6tN2ebst3d5u5vt8KAJ12Gbp63Yeu7WdJu7aV1prvoDY+uw7d2UbF11vgC70eHut2d/a7kt2Drta3cTu5PdZpUPB0EzBrXTluoOdr27Vq3g7soXelu8DtoQ7MJ1GjiL3Ybu6ndCq72d2CLuVXYkOgzNNe71V19rt+XXOO49dXs7eV0JDtC7a3u8GdJc6r12Fru5nSFuptdUZaH11DbuD3SNu7jdb67Tx1oKCm3ZEmvywrvqxN3khvcXYPWrxdK06j43+rv9tivu86dHYByp2amDMXbROvBd+G6ex3VCXPkl1upUEIS7Ei0l7pKLREu8Xd8o6X102LucLQJO1WN2S6nF3EeH90QpG91dfdbTh0BFo33ZAWrfd1w6d93jzG/3eDO6DtB+6vx3edpP3Q/upVdiM7sU3/YU4+hAe/4dPi7yN3JLqJ3XTu2fdr+7Oq0frsTDUD279du1sOrH+g0XDEjugsNxS7oe1gbvHnRBu4GdNnEw27QyF7LD9ujid9e7Bd39Lt73ahuris3NbGD0kboFHaYu/LdG+bad3l7uo3WX9KpdDPIap3jLsp3Zduyrd127ON3brqt7Vv9PKmNUUP+1wbuZ3XzuxjdGy69t2r9CFraxuqUd7G6wd2yHvw3aNu19dOB7W60aAEX3YK24/gMSp5t3oxvX3aIWzfdVw6nx3+ruX0qvmR7d1+6El3wLt23ddOuA9C66nZ3Oht6IBZ7ffdybIM92s7osLYIejndVi7qu1bDptXQJO6iN2qb5d0orrj4m4kWRdRU79c2KLrKnaMOsjt+Lj/2CNICmLTbmpYdIR7Tq2N7uQ7YF26LdNXrEj0tBVyPfb2niN/B7Cj1l7vCPZDusbd0O6BJ0ERrh3dc6L/gAbISfrK7qzzRbgV1cn0Aci3xbtGtjtsGgwY4xt92Y7udDaifc6ABqapi3aWN7hDhQ6A92c6wj1N7oQPVb2iY9/TYouDMkC5LcxpHiAcx60D2Z7u73Ywu09dJK7CuCrHupbI1y6D1Mx7tj2b+uCPVyurPdqW6hD3sxr+ZLxCNY9FDkuu2jOouPXpSfedt+62U0pboAHUseo49Y9ATj1aQo2PR8m949CFD5j0ILv2PUOuw7dm87AT393FHdVsG0E9Ox7rj3NbsWPcUe5Vdjx6JKgclqxWpW2hE9Wx6Pj3gnq73S1uu499R6Hj2wntAaJse6Bc+J7dj3fHtuPb8etE9Lk7/pi8QhVcaSMMPtbx68T1gnvyPTceyE92e66d3PJoxmEyerFsX5A863nHvZPUie6o9A67uT3Enr+PStmqgm7wMhT2vHqpdYieq494p69j1EnrpPTY2mE9XPBJj1tDSxgBSetqAVJ7kT3OVslPeqe0vtMp7N7DngEFPd6S1k9ip7RT3Knuc3QsezA99x6+T3EH21PVoCYU9uJ7KT0cnvmjVyetU9jK65216Zu7DHKeq09IG6bT2enrFPfaeiE9vp7ml2DLqJjToUAU91uB5T3WnvldUqerP1Kp6aT3Gnr9PUAOvTNMVs9riJnpDPcme209qZ6Iz2EntRPRqe/49FIqgz0snvzPUa6lM9nx60S0+ntLPaae9mNbBNMT1uNmDPXqe2Y9dp7et3cZtpPZme5VdAlxKz26npBPYWeus9GM6Gz2OnpJPXyey0AFp6Ez3tnuHPWGers9TW6jT1Rnrd3f6eh4txthWz1unoVPQWehc9RZ7uz0OnqKPWWegjdZJ755AdnsuPXuer49457Dz1Nnr5PV2iQc97p6hg21noq3Sieic90p7mz17dE3PXmes89Bp60z1XnrqPW+evk9c/Dcz1zntIrU+ezk9L57rz3xDv9LeAmGc9akL4T2PnpHPQSeiqNPx6+z0uTuPEPGetSF2J74t0tD07PReeiCd6Z6Vz297ugvUVbScYddx4L1/OrAvYaens9GZ7oz3zLvVzTBe0i9/dwsL3fnq9PYkuiU9hF7Dj3MVoYva+naoGD56KL2IXupPX+egw9qS7iL1TZEYvQ/QaY9Al6qL0Hnv/PfSe/496F7YL3rHq7oCKe3c9o56j90g5pQvbRe58tNraTz0gXoxXZReti9qp7Gz1QXo0rdxenJs75aPT36ntYvR4e5C9vZ6tL29NuDdWZe50akl7VL1IXr+TRxe6E98l6nL3BrjLKtWe37ZuF61L1ToA9nTRe1c9WZ7zc3eXv4sSxe8M9nK6IL2yXqPPaJejC9WAFlL2WXoCvW5eo9dHl7p93KroUveJexIK256az1SXsMvQRe4y96favL0kXp4vaee+c9Vl7or2XntivcJemrdBpaIr0sAj4vWye1y9gl7ar1IDtunaZesq9KqxWuUqXqqvYue/C9Ql6Or1yHu2rUBevAGzF7Kr2pXvAvcue4q9WQ6gJ1anrWPT2ZfLgfV6pr3SXsjPbNe/OdGxaPz3ansNtMlehC9rV7vT3tXtlHZ1e7atd56emj6TWWvSle889gV6Is3UXoyvY/u7S9sZ6Nz07XouvTie/a9/V68L1jnqOvWLu+A95Z7pz3iXtevdhegy9xZ7bL0hXqIvXyeuaM516C0SXXvevate389316Dt2ZXoZPSATF690N63r38XoOvfDema9r565L0ynqQyCVnNG9QN6Cr0g3vcvRte5Od2Z6yr1eXQmvaBe4m9+571r043vivXyekbiAN7Cb1RXoGvV9e7G9kF6Sr0ynsDPVDe6m9+l7ab1LnruvWTe5/t816NuA7XuTmmzez696l72L0i3pjPRsWl09ax7Ab1S3puvdDOks9DN6bz3bVvNPSze/m9K17rr3Pns5vXFezW9sZ719583uBPTTezG9JN70r1y3rovXpm+ssOt7zb0C3stvXTe9W9XN65r0bFvX4gTe3W9V16fz1W3vSHT9ek69Yt6nj3UtmWpnle/y9+t62r2G3rqvR9unS9C16Q73/aItvR9em69tnb6b1u3s2vUJ6sk9v4QVb1pXv9vYjeh69Gw60p3u9p43QJO3ltDXa0J2X/JN4CGVADdebagN1LbrebVQev1dYx6y80KSQrbUj2ikdv27vx2aHptvavWjtdzd6TxCLtrbvfyO2ntq+aWD1d3o1vSZe9jt5CTW71MHvx3Z3eijd497ub0YtrMQAPeme9ay6240aHvnvSxu4XdbG6B+36HuGvYYe7A9sva1vV2rtCTco4Vo9os6GGDXuDuXaT+NXdym7Nd2/1qbva0uE/AxDaZ5117r63Y2utzdce7SG1Rrp03TGuimdlwjAG0Qrss3Umuv3dGm6A90WbsTXX2elWd6uaxK2APstHT8u33dxQ68x0Rro83YbOxPdum7zc2mzthzQFu7ydwW6Y92hbon3eauvhtKU6zO2lHudnaxAsTE6e7Cr1DXuOvfou3PdU5amG1sro49W2Oh3dOC7yF1G3viHefuqOdQHDHG1tRpYfZ3usZt4w7vD0jXrtLanO9J6VD7Ih2aXtCvcqugAMzkr6c0Grr/nQfO9TdyD64V1EPuSncKW59dI07Gj38TtwPSm2twt5h71R2wljsrGQew2NwG7Ud3mxtRHX12/1dwpsyJDqDh4PcPe+ntHY6/+3d3qOnWQ+ztdWCIkxCD3ogHZIelnd0h62d0cPsXvZ9uqzAl1YvH0U7tI3Woe0e9m96An3u3vedUsBVnQW2BV71U7vXvQLuse9W96dl1ijv77YgO2h9B97Jd1NHt0farGhXtOS6YZIepKxwtYev/doBbH23kFsuHRIWkVACiAy21lBvAgCgem/dg17In0YHrTvVMO3PdZKsI0lUeG2ne4emK9c962n3RPvRbYfe8ad19biI0EHrQnVvOl+9ZT643Wq7uHnXfemTdlj6N+3+rpEqC4YK+9Bu6QH1IPufncAu83dgs7Mr3QPqE9RJ9OB9eQ6jN0f+sQfcuW/3dLA6PR17zoEXWieg59+QaajjTPvgfU5upR9eD7Ln12ju/vdpu9B9f975W3w4UofWwuzZ9Fz6wH1XPpuTRFuttdR27se1QLpUbVdm9vdsq7qH0I3p73Zxe1Dd6C7sH217pnXf1O7Gd0d6c92+Hsy4KJa8R9aL6RV0YvtP3SJeq3tzvEfG2wvty3ehmhF9Bx7PL3CHuPjPI+k59ke6OF2mbvDXao++PdU+7873ebpGfXYuoYA2IbCn2vTqSQMSG1fduubvp2pHpOfd0Owidxua5N00HuZneYQQV9ym9sL2glp6XQUe7RtQz6On04vrlfYhAlcgxi7lX1+PtL3Vi+rA9uT6dH31FoAAFLn3rD6KvOe2p1d7BE0zGmELdAqNoNL46d1hETox3TK+u0tlr6Kamfeq8ncweqO9Tu6QX3OpvUfYe2pPdGr6ifRxrGFqZ6+qKdHd6XN0f3oG3QZOoKd9l6Q91RVtEgWG+gENXr7Z71RvpTXePuv8toWbHJ3xvpG3RpW/Vtyb6ak2pvrXvem+sfdn96zd34rsMnVA+jB9sibPiSg1M++uG+nH13r7S334Pszfcem/19tz7TO0/PrCtOjUht9Kb6I33NvtH3a2+8t9hD7s326+vBfcIuqHdxr7MnUAAE1zX2zrg2Ah9OwQtpVbc818Bq89TjgIvNik7AZ2uvpZDYmud4siwaP3UG3pbfe8+8zd/tbe4RWbs5fRWu1DdN9ThI0fJsPfdNe499wL6Pn201vPfZ2+7Vtmj7rF3pTrn3Wcum+tAAAFKiNmIbgk1y7o7rU6u4dNqZagy0zPtpnVJup5dH4AXl0P3p3fSxmgBt/TgMN0qbtwfcmust9Mb7dn0/3u+fWp2//NfBbAy0YboRXRxW1596H7h32Yfpd3Z6O3N9Ug6AM0SdoI/a/ewF9nDaCH1Zvs+fUHuy991H6GG0adroeL2WgF9aH7QH0qPp2fZPusF9v97212ATqvbafmHIe2F6D10tPp9fdk+ordue7XO0NEBnLQS+1h9Tj6Bp1qvpaXaJ+ljNRjary3KfoEfRuu3Bdwj7DD3xdtgUjp+il9xe6ir0L3pifTPmzqspn7GX2KPqj3Vwuk99KD7fo0cvqVXR++yI94I6XC3YhomfTc26g8t7heiDJHrC8D0Wn6d12aJX3/TsP3bH6mVt2u69Q34HlvcKTMnYtkM6j317TqEfS4+mptmn7zPWxfpCVAl+kYdD77kv0N7vU/RLuwu9UR7i735Pu0gAY+on0YTZPx0zPtsPU+2+w9NT68t1Rfo/bTBeMJsCjBAj1KFpdvYI+kcdxL6JV2dPoU9spMNr9EX7br15ftgPal+hWtz+6v30mHoubam2xxdTq6QUazbvrwIv25HdFB7lt0N3q13U1+hlVMRhXD0qHt53Xwe9A9Mh7971yfuDfcYm1SMp26tv2YbtUPbt+u/dZdbLP3p3sfdYSszb9iT6pD2tPv2/bJ++q9Cy7KDp3YrO/fRuwd9/YAmN1s7u0Pdve3Q9u97DP0iXu5fe+u1wtZd6bm21cGAIu5gead/+6B612HqAPQ4enXt1j7lPZwzLo3ageta9nh7Bn0GvqEPcyuwok6P6Bv053tU/Xbrdp9uJawf3KjpvrQ04AiNHTgyI3mvrA/dEm6mdqFbPV1Edo4jYs+1bdCH7601CJv7nd7ukNdzL7370ZvpHfcx+xzdrH63P01vr9MHwWnn96a7IH0O7uj3U5+tl91z7IV3Vvu7fYQ2rxdUv7UH1v3sfffx+vFdge60H37PvF/RZADTtdg6eP2y/sc/U++099oL6LV0Tvor3aH6oXIxv6zP0ODo0vXZe6R9yx6GG3KNvt/d4O/h9kQ6Sf3dfpQ3fJ+kBYSQ7wh1e/uwXT7+kH9b37c00JdtYXQ7+7SdYN7OL0YtqcYjQuwVNG469P2O7v63Zpu9l9Qn6cP0Nzq0fcYeo+9GWab61xHpA/Xsmgs4NayoXyMJGvvaxGr1dCz7YP3o7t8XW8ulkNixIEk2BltCfQLOhB9JH6+P3bPp1/Rr+t99xLb7n3ytqDFk3+/pwLf7bvWu7vOfYx+tt9H6aR/2UfukfX3+vxAkbZIXzgfuH/UpWtv9Dn7jd3y/oE/br+wldJD6Vf2dIAHQljsZSYhH6bs3D7qpfQL+jD96f6XP2Z/v1/YI23u9GiBBuCV/roeIT6DFdUn7an3BXvuvb9eghdnNajuL7/uhcOVuwl9sM7ff3YvrcfVSxI42pBxYOi//pU/bOu1YdZP75b2SuuBaqAByUAEj7NV3O/vBvcX+z+xTf6QDQwLqH3Qx+szdzn7Lf3EPo0fUeOor9nn6391ptqL/cuO5rlgBa4f0VPsWnUEWpH99X6gr11/ui/e86+G4yBaif2R3pgPbgugADEO7JV0VZp7rb0+qA97AHhv2cAbD/W1uin9E27C/0+9oV3U3YFrt40hCOCLfvIPWY+yg9pS6jR2c/vL7aa6Frt8v5Hv2+Pue/f4+3H99R7mV1HqzBjt3wZQ9536dv33duP3ak+gr9tt7YA2nCw0AwT6L79NPbdX06AYEPTd+8m9NgHRNqVWOMA+Ie7b9Pj6In3JPuFrQDuoXd6T73u37Lo43Qd+nVdYgGdh2RQHK/YHxGz9ALKuj0gFuDQAj+2r9dAGR61OHtfqPoW+JdAgGsf2dfpG/a4BjT9o675W0Ke212ORelg4zT6X/01HofjVwB+49kQGYj2TbviPSfGyLl89YpJ1q9qSAwouk596R6pX0uvr8XbQeqQgTQG/BjKbrH0SiWnbduQGDP2jfohfZn2mLlKg1s8aUTp6nZG+oQD7D69ANvntqA/k+q5t+w6rl1bToSAzV+qp9dX60gOP3ulAmuys6d/AGgj3wvoGfakWkQDgAGb/246Bt7WwBnID+n6vD3jAcnfdo+6I9uj6E80+ftA/cHdYCC7ckTH0vNryvStulQDPQHZX17oDHOG6QJf9336030LAb6XY8Bm39OHaQQPe/NaJCw28EDJb7IQMvfoDvSI+0ltm9bn2RggccAyMB+4DUIH8gMwAes/RSgcygCIG8d3Igd+/Rve/EDaT7gd27LsyfaLuvO97/6jD0v7rz/VBWnUt8ABcQ0xAYZ/V7u3/dsz6b73zPuI7ez+gED9f7EP1FTq93Zv+7ADrL6N/3d/uV/bh+3gtxn0xQMQPuM3av+5R9nf73N2K/uAfTKB5vd66ac3Uq4Ho/bx+rZ9PC6pQMsfr1/Wx+2f9hv6XQZp7pN/Sn+uX95v7cANGdsv/aaB0h9VwGToBC5EtA9H+wQDqd6rAM93vS/fgG5RtboHPf3Trr//f4O6EDH/7gu3eshqKDHOxrd/P6OAOLAfCAzHeuxtnYAL13Tjo73ZI+5ADcf7Lu24vIjAzg+039a/7bQMK/rwAwG+j1t7n78Z1S7oEndiGr9daE7OjSyQuEQjM+uRdHQ6mH2tOrC/SounJt+wGt5WGbA5LZQhbL9Wi6R90wzuDAwSBhsdhQGfCAa7H6qDWB0itSr70X3//ouA4a+ogDSE7pd1sgf8Tea+qZ9eu7Pvo8gag/eru0kA996WwOqAaV7UWhSxAeoGcwMqgcNA13+40DW/6CAM7/p/XbD9Fy4Ca6lQPRgaHfev+48DMZalf1UfrNAx8QR59y4GGwOofoPA28+vMDRoGRf0mgbF/eeBr+d1a6sq0GDvs/beBv5dP4GHwP2gat/cJ+iYDSM6oX0+iUQAzVemT9aIGz9257v+kgXukCDZgA113gQex/ZiW/sD3oHBwMF0F6UmCKM79OEHr116vtqPUsB3G9Dx7neKkQaQg7hB0G9b/7A716hp5NfRBq0DY/6cAP5gegg/gBwN9hAHxv1F3u/fTDu1NtFYGof3B3VmsORIH4DKO6lANo7qWfd0B4UD3za8XaQJQbA0iBpJ9MYGqQNegdcfc6Bg6lBrbt9BaAb8A+pB1EDDIGWIMsZucDdJYFSDOIH5gO9gZp3QRBhy91n7elxEKAsg1hugyDGzq/v0uAepAzgASUdey69D1TgZqA0a+l4DrdaaoAxAc3iFkxNvd1r7zvXbAZYbdU+vYD24HRaltQASwk0+vp9yEHDIM4Ft8g/oBzp9J4BQoOJQeyA6cBlKDoR7bIPHLpnA6cunYdd9aGgPgdtpDd13FoD97b4f2VPqig7sBvodqP6KoMH+FuA1jevKD9+6QwP4/qag3yAFqDft6ff3VAZJPSsB+otlEbRINOrtjMIMRRdwQBaaS24Ts6HbjG8atvQ7X23SvsBA7GezqISGAK8Lk7pBLVUe8kDeEGCt3QAYHA0YmsaDExEyULdTuGA1ZB7aD+r64wO3bsGg1N+5MN/L6nV137LB7ZNBwDdS37FAMrfuUA+BupaDJ8aZZqU9viZOduswDdPaLANRPuog0ee5ldY4oPwApcGxA85By79Kr6Q227QcevaU62zsiPb9INQwcog9d+2GDdkHa433yE57RDBi795gGhR0pPs3vQD+4IDIu6Dl0XQenAwJB4r9QkG393q1rKg3KB8fg1XKeQORQaWnSEWtA9/Xa5C3zySyAycBmy9eIHzgMdQf9/b34m9tHMH2v3JQZRA6lBkMDTIGJv0sgc4LTN+9jtGMz/vBUAbaAzQBi4d9UH+12swc7AHLB44DQsHpP1tQaqA2lB6U9zK6OwibAcRA5j+3KDIsH8oNowcKg+TB4gD+T7boNNjqa7r8y8KDa+6aoOKwc8XakBlmD1j6RaxQzIUjYYWnKDXMHki37Tt1g7jekGDgaaWuXZQc5g/0+7WD0ab+oPLAf8gyV++otmWa1gOXLovAwp9cWdkH6Wf2PLp9XYKB96DCkHnQ1TzvDHfuB60DZv7tf1qgb/A6eBviD54GlwNujuvA2c+9v9BoHYV2/gbX9a7u639K2ab515wY2ffqBoF9RcGv70lwZ7/YeOwCD8OEWx12fuT/ZxByUDUEHSu0wQaz/a7+qOtUL7XZ3Jgbhfb7B3O9iL7aX3IvrurAPBijNwf7D11sPqq3ebBko9zoGjKjRzvAAyn+zeD+EHt4PonrJfVOO90DrD6pH0oAb1TTyaoud2YGC4O5gc7gxW+tR9PcHVO3Z/s/fYJByb957bzX3x/FVlJDWa8dNJbT9QoBrAPd9WopQvnq7ixrfpUneWJVWUYTRsL1zQdVva/+3mDR37oEML6Hc7RiuxRAMCAkv2egaBg8behW9ttwrdCKvsBzQghp39sf7aX3Nntr/J+K3HwyJbMEO5fv7APsACwAKAA8AAz1AWbFvJFTeWebWEO5KiBgJ2AGp1uSofMA8IfZmZpBi2DOf7mQOjPs4Lc9OsgDeobAOVHDvlg2cOwA9y07kf0VAca/SpOhegdw7BYODfpTvWdB9qDBUGd4M+gePsO+wr2D+RakoNawdNg1ohk+DTwHc/2iIY4TT/B+KsY2ASZUJAemgw2Bgid4X7nX2MAaa/dC6CTAa0HKj11Tq2g6MB2MDr36/f3IIZsQ5Uk0Fwx0HKY0/fs0Q6q+nBDUF6roPntveA8X+125ciUZEMAHsR/fIh+gDwOalEOQbr94qUS+2D3sGw4PCwesg11+gODwMH0IPJkkSQxrB9RDzw7fEM4/tJg35BoqDpYHXgNJhoTg4QeiT6Lb0pIPLfvrvW9B6g9H0HJXXmdAX0Bj+yGDuMG9v26AZqQ+lBo79r7FB56rSHsfU4Bs4DwyH/EO3bvkPbBYcoQFo6jYMDIf+g5UBmGDgiGwr0UlsWQ2x5fpDOMG1kOBtrcgynW17tRMGd71ZPtQg6D+mODlMHdH2ZZsXA0c+8FdCQG1wPV/vZQLX+jJDvQH6+WwXk+XfnB4eDvr7n33fLq+fVf+2UDvc6FPoPIZOfaP+muDHcHVQNdwYbg9P+puD1863wPIVu+QxCh8f9Qv7232t/oBQ46BvuDXOFBV0KPqHg8ihriD9cGx4O8QaLA06B3RDEa49Hl7BA/A58mmztlSHSb3aIbgg9fOlF9OKGAwNRgYog84BqiDIyG9YO57r3g/qullDKYGQ/2QAbU/VEhwJ9NrayX3GUAYg2yhlCDxkH0QNeto1sWquweDlK78UMjweLgzxBwsDpxbiwPpLryffUWgiNWTqHV0SIYpvZsgKRcbq7Um3yKy4Q5/Wzm4evRDshCgaYAw8WlSgRSo5vh/DpHYLoECUDvyGLf3vjoKAM6hzUDDJ776r2oYBqaBOj1D9cqfkNp/vAfVjWp1D9cq4UO3nrA8A9UvbAoE7Ac0mLpP/cLe+lDk8G8EN/BGlDTGhppt8cBfIgx/uYgzKhh4tLLx7RB5BFjQ2WheND6sgaH0XIfD/Xbej460aHqz1B2OLQ5r+mS9wqGrP2tFqL7RF4UoDIJbeXXAcBcbSgAXeytcH6O0oAEQAGMAcgoUAA0UMlwjMoOgWiNDo16W0NH4oS/a1+9ht3aGzPK9oaAXf2hwdDb0AR0O3YjHQ/7ACdDsZ72jrxKgEaJouztD1o750PE5EXQ/JW5dDQ6G10O1oZOA1uhj29iQsBQDTobHA98W/xtR6GO/2GgbPQ6uhyf966HU33Xob0zVF0AtDFHMmm3BoCzQ/QutMDZCGpz0vBGrQwoWzND3YGE0MNoc5QzRBiG9QAgIMMZobjQ/Wh7BDcGHGb3bVv9PEhh6ntUGGS0OIIaTQ+WelOYf6H00M4YZQw9mhsWDfJ6D5rYYaNg7hh1DDrt7NkP9noTYMRhmtDYqAgMOXwZAw0je8s9VZrqMOOxtow+RhgjDDR6LEM8vu/zfUB/VDtMHVENJIeSAzsB12DKsHrH1mrGeHgYhnetRiHFENXfsjg0Uh009+sH+YPSIfKQ8T+wVDpP6GMPmIZEQ8Jhhot877E1yYyVrA6K+9oDXQ6Bi2Svq6Q9nB4F8lX7X6noIcWHRABol96mHOH0lIbrvuZhh9DiX6gwMpfoEw+LBz+DksGRMOQ/rug4eADMkTP7qnWMwdoA6khmKD3SGtY0VSoiwz1B8ODJiGdYNIIaAAzToLD25MBksP5IYiQ2phsWDMSGJp18tppg76B5N1OikFv1uLqdg+tBgiAysHG72xQYqUnAaiYQOWHGIPcwdFgwJh/H95MA7h3YgfKAz2BvLDgHaCsNXIa/g/n+4iNiYbMQ0AADVzX33QcZ/RX+h5d0H6M4M1/rkg64hlSdeg7b53PPvvnS1h1P90b7z/3dwa9Q/8eqbD6v71QMy/ofg4eBuuDo8Gp/03Pt2w5WusMdB2GdsNfgdI/feBlVD6KHRf3b/qBQxXWAj0Hv71x2KoeVA9+Bp+Do76L/3jwcBQwyhodNXa6MF0SoZlvUZe9rD8n75dzfzoPg97+vTDUcHA4O57qlXVH+vlDc8GBUNuYYowxOO0olif7e11o4Y3g1fB9MDn/7W8U44dAg3ih77D92HIIOPYZrnQDhzFDIlaxAMVACeAD4AMWAPgASnVwRosAHjAEAARAAnAB4AG6dbUENwABAAJHDnqWYAMOABwAjCG4gDsAHsAAi69HwqoAUEj8ACBgHQAM2ANABrtiYAECAJgAFMN8TrUABMIf29agAbiAiZIGi3hCiKIHwUBotTRanGClerqHZqAE2cZuHtM20DoM9biGv11PfARChm4b9dfkAEQoDRbF40WYUdww0WkqxCT6jcNaps1AJe4T3DfL7NQAxocDwwACeQofBRSvWcJv9wzjsJXNTRavECu4cojdpm1okkeGSrEGQATw+c6UwgkeGw8N9Qgjw0rm53DnjgDPXDQf9w3y2XPDsR7g8OcnDzw+EKePQnuGUJ2agDIxJ7h/R91qaY8OJhqaLT9B0r1kI7i8O5KlcLUnhrvD+B7/cPx4aNw4mG850RShXcOJhoABNpWgz1yYbC/1KoFHw+Ihwdws+HF41FCHbw6Jhq9Qs+G48M24eXw+3W25dg+HSAMAYGXwyVYnaky+HznRQpuXwwACTeAo+HqYPH0Avw366s7d7eHogNV9Avw+EKPsYd+HW8PrNlcLRsAOvDb+H392agF/0pPhhfdBAIL8PH4ZoNO/h8fD+cAG8P54dwNLnhs8dM4BGR7sFBAAC0e4PD7cJc8Nzvs1AMkgT3DC8b/cMAKVzw7y2i3DXeGE82agEqgK7hlWN4QpZmClepVjevhgHEej7261Z+rII0mG7TNViAiCNJhpKsWkgRgjQ+HNQABQFYIwACQIArBHSoMXwB4I366w+oej7KgnjXh4I+EKdgitBHkw1NFpLgDwR9utFI8hCPaZog/QZ63ltJVi9QA8EeHw2ADCQjCE5B1xKEbVrYX+ttQEhHgoA/4fY/Ho++/Du7rWCNqxrCgOYRqQjTZITCPUEZjw3E29gjeBG1a0lWNxALAR0r1J974AALgc1AFcQdwjMu69UPSuIM9R4RjkD9KbXcMeEeA/WugUIjMu71vXO4a7wx4Rs+9weGbCMeEbJnXXh4wjHhH4K0EEcEIx4RvUtBBHgCOZZsL/VJsEAAtyH+8MV4fOXT/hygjmWbwhQ8/FK9fHB4vDxhGVR0W4bfw5h29gjjRGb63MEcEI5lm4fD7RGb628EbsfQZ6vjdAm6/XVUzGqIzfW0bDE2H+8NdEeIjaRGiiN1EbvCOu4cyze3Orud9uHciNU/pp/XT+1AjyxHiI3/vsojYB+4D95ANhiPERqwHXqhvACueHNvXbevYI3MRzIN+Tqf8Ou4ZydXk67INmoAHqyCTuEnfbhrAjz2JsnX24ZuI4vhm4jT+G3CN3Or1Q49gX4jOIa/XWQEbeIzqhvVDoIRfiNmvtQIxdsZu+sAApHAEAGsALYAYLQFQALPoRuvgLaAAbVNd7rsQ3kFCIAPAAaKAaABHIDDgF/fcQAHJ1pTgsXW31oJI1wAeAAv77LQB4ADwAPAAMbD1zq4I0OADM8hUAfYGd7qGnAAAA14ADTAByAMIALJ1ZEb/E0MeHgAFyR6kj8AAeABOAAq9XgULEjOJG8SMUAEpI0SRkkjKAAySMWAApI45AakjtJH6SOMkb8ACepYnIFQBV5Icke5I7yR4cAApGhSMike5I7++8UjkpGKgDhn0NIzyRnwAfJHmACmkeFI6KRy0jEpGKvXLuhlI0QAXEj+JHCSPCAGJI0QAUkjUjhySPykfVIzSRoUAdJGGSNMkd1IxV6lGYd7qOnDJhpsgBSGsgAY2HPoBZOuCTWRGzOAJpGMyNZkYqANZyO0jWTrO51X/QacJiGtINmIbPoDreuHACrG80j8ABRKiURoq9VU0Asj3rq4K1ZOpNI82R0UjsFasnXsgd/fWTOu1YFAAsnXJAFvrdaR4QAd9a73WmEaVzXiRpBA4pHGkANOCxdcepQ6AFQAUw0FkaLI/qIEsjZZGKyNVkaTDTWRusjFXrKgl3ut/ffsAdoA8AAGPB5OoYQ0ScH118AAsnW/voFI5eRzudAABFEmd8ABvXUEAA6AFk6iwAYAAmEOLkelIwZ68cjlEbJyM9AGnI6SAucjJThdyMGkcCI9yRi8jnZG2yM1kc7I92R3sjyox+yODkYoAMOR5gAUgACXXIUZtddiG/8j/ABAKPOpGAowuRkcjnpHwKOXkebI1BR/kj7ZHuSOwUexDT2RtU20UAByMUACHI7uRuMjBnqlUBEAEwo9hR3Cjs5GLADzkd3I/mR4ijkFHWyPkUZgo12R6ij8FH5uj0UcYo4uRxsjP5HE81/kZG2DhRtqSXFGeKNskcxI/xRlcjpIDSyPlkcrI8IAasjopGdyNskdm9aV6igAaQbpcDqAG9dcOARMNl5GgP3UoDwKGyR9kjLFGTKP2hHMo8IASyj6ZHEw02UYq9WrGu91xlHTKPOUe/zVZR9yjL1BPKNgUaMo09ANijw4AsKPyUc4o/hRzyjtpGDPUzMCcAOxRqKjilGYqNskaIowcG651x6l3yPHkbAADsAYcAyjh9gBgAA4oylR7ijJThqSM7ACM4mgAXx8kZGGPAEACgAL++p71bJHmKPuEYgo6RRwSjTpGKKMtkbgo7RRxCjDFHkKOeUb4oy1RkijLZHoKMdkZEozRRvsjElH+qNskeko6V638jxVGZyOpUeEAAFAAl1opHCyPFkc0oxuRnSjW5G9KM9KHrIxUASgAq1GIKPqUedSJtR7SjeB7tyN7UalI/ZRoyjjlGnIB+UdcLQFRjyjB1HvyNDUYEo6NRyij41GxKN0UaQoyhRkAAvqAjqO3kY2o+uR86jej7LqP2QH2o8tRuKjb1GTqNrka0o5uRyyju1GIaNSkfSo404Y6jwNH4aPbUcRo9yR/Sjy1HmqNo0aBo6uRs6jCNHwaPqAEho8wANEW3lG7qNmUYso09RoKjB1HZqME0feo0JRsaj3VHJqO/UYq9YEAQGj61GiaMg0ZJo0jRsmjnNHDKNM0dho8TRrGjpNHyaMgAF4AAS6+ajyVHFqOlUYIo8wAYQ6y5GMaNbUYuowLRyWjOgBuaOi0b5o+LRjWjnNHoaNM0baox9RrqjolGeqNTUb+o6UgdCjYVGkqNTkZKo8pR4QAxOoqaO+Udpo25R56jjtHBqMi0dVo6DR3SjONGrqP6kcZo2tR42jLNHPqNs0YQoxbRir1KwARo3+JrIjVYgE19yjhMQ0dOAacK7R6yjrbRI6PC0a8QFI4YcAclG7aPy0Ydo8wAQQABLrsSPekblIwqR/0jSpGVSNqkapI+GR6QAkZHtSPMkdZI8IAVGAMtHZKMLUaAowrRyOjIVGQAA+UacoynRwKjasabSOG0dYo7bRgCj9tGQKM2kdRo0HRkajIdHTaMTUfDoxzRm0j+NGp6NkUY6o8JRsOj4lGF6NN0c9o8PRiKjbdG8KMd0ZtI4zRnuj91G+6Pu0eYAFYgbWj3tH+aN+0eRoxUAUuA3NHg6Or0dZo2bR9mjfVG/qPrAAfo9PRp+jodGX6Pz0bfox6R16jXtHeaOY0fVozfRwWjd9Gu6PL0fao9k6zqjVFG56Mb0f/o3fRw2ja1GdaMgMbBo/rRu+jk9H0aPAMbVo+gxsBjktG10Cf0ZXozAxtejv9GEGOSUeEAGJgdCj1NGHqOuUeso/TRyhjR9GaGOn0YYY8wANJAl9GcGM+0Z2o/gx2MjGdHmGMuUbpowPR4QAzUACXWJhrSDb++7Oje9GlKPj0eEY4AxgAAflWRu8jyjhf30hAEVw1VRmgAdJHYyOQMewYxpR3WjoDHayP+0eEY8gx1qjX9GSGPP0fgYz9RxBjwjGsGOE0d0Y2gx32jBjHb6PCMfxo8fRmmjAjG3aOsMZAADvSJsjpjGLyPmMe+o71RihjbDGj6M0AESo7vRuWj7dH86MgAAcgEXR2UjvpH4m0BkaDIyGRgkjcgANSMRkfpI7BWzINwzryCg+AD1I8IATxABLqKvCwVsadRFRlwAbABpgBjADgrXUOngAn0ACI1RkZ1IyyRvJjzABKao+MeIY34xn+jFjHAmPTUfyY4AxjCj4THc6ORMZkY80xrujrjHaGOCMdso/kx4xjtjHTqN6MbwY44x8Bj+THUaOjMZYY0Ix5pjS9GTGNtMdgY19R82jm9HmmOe0agYybRuBjATGI6N5kaYYy7R9xj9DHVmMgADtgBwxuxjuDGHGO40eYAKzAahj5zH/KMeMauY8QLO91YjGJGPCABzo6PRvOjQzHrmO9Mf4Y28xy5jEzGnmPaMemY3DR+5j3DH5mOS0YQKq0x6Bj7THZ6PHMd2Y9cx1GjlUBrAAj0YUowCxxWj1zH1mPDUc2Y6QxzpjJzHhAAXQFuYzMx+xjsLHHmPXMbOY73Ri5j/dHwWPd0aegC8x+ljoLHGWO7keigAS659AWdHfmNSMaWo6hRtKAFLHoWNcMexo3CxzljwLHXmOPUfeY0yxnhQrLGT6MMsbPo8yxoejILHpWNgsc5YzYx5mj39GUWM7MasY4Kx/Gjv77KI1kRpQnWNhmgABEaeACckezI2RGs2AeiA4K2vQB6dcQUCAA1zrHXWcse3o6qxuhjHLHFyP0AG5Y0kAXljHCb+WMH0ZHI6ORhyjUrGPWNKse3cMKxsWj+jGaWPgjCIY0ixrZj69HLGNBMe7o5Nuu91sFaQk2fQDIjTO+/99n0BsQ3fQAoAJ9ABpw1KBhwDpseCTZmx7Nj63rc2P5scLY9SgT6AsFb7WM5OrGAE6x1J1w6HFyN8tudo2yxtVjnrGg2OG0cxY9ix6KjgbHUKNzzI7Ywqx9lj4bHKQDysbcY2OxzxjOGA42OHMe2Y6/RySj8TrVHBVwg29Vt6kSd5xGjcMZBqyDYMRm4juTqriPqfXQIx8Ro3DWTqviMnsZ+I83fJjwq7HxF114cEI40WggjXeHzcPaKldw9iG63DwBG7cN14abTLnh4IjUyIX2Pu4Zswt+x73DMeG/cMeEF+I0HhpSFYHGw8NfsbeI1Hhs7YCeG48OPEcTw3XhmPDyub/cNv4fl7RbhivD3VaCCM54Zg4/nh9Dji8ahmw14d4I81ABPDomHq8Ol4fbrfXhqAjT+Hm8Ot4ebw+3WnhQo+Ge8Oj4dTwwPhyfD6hGbCNj4dQI8YRqfDxeHHiOJkeLw4IR3YdFuHgCPJhsqIyIuZfD6+GxONoUds9RXh5MN2ma98OuFonY9amygjN0Hg8NqcYQnOfhwfDl+HzyDX4fYI8Jx0wj3H6/8NP4fk40FBt68F+GqONf4d5RpKsC/DJVifrB/4aAIxfh0AjvxHgP0GeFc44vGlYAvxGECNzDF+IygRhM9vxGMCPqwF+IzgRgUAThHoCPj4FYIyQR4wj5BH+8OUEZVjdQRwQjWS6f8OPEZVjcwR1LjSYbznQcEaNw/V2i3DGXG+OPSzX4I6gRngj7uGkuOptrEIzYR3ltUhGYuPTftQI5Vx1NtChHgCPKEYtw/Fx1Nt6hGK8Ol3uDw+Fxy/D+hGTCODEZq46rGxeNUCgcuNq1ok41YR9gj9XGHF0W4fsI2rWhQj3XGXCNgEdzwx4Rrwj20zIiNsgf8IxXhoIjfrr8mKNOBl3eER4AjHhHoiP+4diIzLu+Ij3q41uMwVuSIzOxC7joSb0iPWpsyIzLu7Ij1qaNiN4kdQIxMR2+txRG5iM31qG4+URm+tlRG6iM31oQ4wDx4iN1BGWiPERoUI2Dx+AAbRGvuPERs6IzDx2+tehGY8P9EfCI13hzLNoxHncPg9q3YzfWqYjVEbtuPw8YWI93OuvDL3Hqf20/oEIy9xrYjOxGBCMlEcwHdgOv11xxG3iPKOH+IwBxt4jQJHg8Pecd1QxjxpAjbxGhJ1nEe+AJCRgQjMJG91JxuByY/AAZnDJoBcADxOoIAJrh+AAHgAbnVnqQoKEMANwAgmJaADw+CAAAA==")) +var pcbdata = JSON.parse(LZString.decompressFromBase64("N4IgpgJg5mDOD6AjRB7AHiAXAAlAWwEsA7DHAFjIDoAOAJgDZaBWAGmxEKIE8tsyB2SvTYcAhmlLYAzPSmUAnLP6t2ecTxwBGeQAZKTZgF8RkGLF4BtUABcuABzC8QsMFDxgi1kCNjXRAJy8cCwoaJk1mNgEhZgBdEyIIS1DqcMjsbT0mePYAdwIIawALXj0dJmNcEFsHJxc3Dy8fP0DkqlSIlUz9HPBEyxk5eSlqZTZu7JF8wpKcMoq2G3tHHGdXd09vdl8AoOwLQYURsYzdHoSk4MPh0ZVoxkm8guLSynLKpdrV+o2m7Za9gdZEdblFBA9eh5LvsUmk7uC4lNnrNsPMPtVlnV1o0ts4AZZNFJNJRaESpDpNOMyMSdNT5NTIf1goTiaTCRTxlJ5EIZMx+L1pi85pRNOiaitttjNs1dgSpLQRTJqGRqJzqDQuZpGdCLIS5Pw+UwpGqNfItUiZq9RYsMV9JQ1pf9ZcypPrDbQqcTqFydPJ5Nq5QrCfRlaqMtTTb7/RahaiRWLMd8pX88c79oSqLIIn7OdzZA9+Rc5ZmibQc+GaXSGTGUXprVVxU4AgBjXE7VouvT8MmaSkZLk8h6PED+UQQAgAV3MwrIfvLqcCoiIUAANhKALTMSj8Pt9CBL1cSso1q0Ju0gFtt/Eu4myUlE3MknTMCm9UfjqevFQLvzLte8TQmCoMsLgPf8cHJPRjSeS1hXrT4JQvfxWxlDt03Jbcez7TQI1pbQyCkN8x0nac41nOdUN/Q9eHXY92ChMCJS3HcTzgs9EMvSi5VveVXWwiMBCYehFCIj9SL0ciKKdRc/wlJhuX4UDZN4Whym3XdBVreMbUbVZOOkwFCSDJVwipBVXTNHRqFEkivx0ezfUoxiaIiKClOonB1zOHRWLjeDbQ45CrzTXV5UVEMuhGSgLN9GzP2FJgHMcgznJwbz3PAjJVOi3y63Ypsgq4l03SYE4cPMzVzXYd9bIShzeyc5TPPS+jElS7B13k7dcu0htE3YfSfzlEqyqimLo2q4j4rjRL7N3dsqMyrrFNa/cmuwFqQE008dP6pCUIM4sSXJWgVsJblVMRSaxNeST5wW9r11cnLVva5iNORHa+vPQaFrlJhFU0ehhH7PNBjIOLxP0eyZHmgFHs0fhuXnBj1qeoCXq2z62N2n7CsOl1gJOs6BOUQtrtqmakrh3ZHvejKJWe6Csdgvz8r0/GhpdAGWWgnDK1oSHbrnE4f3awCqGZ1GPIyagyg+1m8txxCfhxIr9mWnQRg5DJnwUcIgKqvdLE17XsIpfQyCYVJyZZ2Mle+lXk2CtCLHoPR3eGFVxns7cVVtqFLEYEV5DoI0fa7f2BWxtnlaxB0Uz+4Jg+0MOPV1/UVWEibjeTj3fSkb2M796hs+jxXeoQ+PfhdwFgU0LWkfkH3iSA63SoDZO5AbqQm59hV5AN6sYPtyuAoKg6uY1i6teoBrddbq3UmHGrpokudm5StH6de9a6LtrT/N0gbOaT/Z3ZFWlvXN4le1oBujdXqHvwe9aJZJTe93ayDMe2nHHYnrXE2M8RjzwbgPIehERBP2FlJMWaN97S0yjvA+X0q4c0nmfN2dYr4PmLiMAwIloFTShndT+r8ZbLQZipNSLER6H3ZifTB15z752GKZXWwF/ZWSFnVBy5D4ZoyZtQ5q+8/6xwARgoBechAFy6L7WgWcc4wL4fZARtN1qbSQYzbKzNxEO3QUw6R58gyh3SA3LhoxH4kLsnNGmMkZZeUQW1NGVD6FoPHlI9WbtTFhwjiSJRvCqZzUapQhSIiNpiJjgYzxRjvHB34M+fgZ0LZ32sTdGcG91EOMyk9XRESUH6LHsffaxi3ZyHdtSEGD9LbyQhsQjJwTYahNyYjZGn9tEuQxno6JxS9q/RYT47cSSUlyAIVAima9ob1RaRuFBnStD5Pcf/QxpT4kVNnv3fWQMgnrz9KLChmV35SxcTLTQcs3gK1HkfPaqtHRT11EDBQ3o5bmzkDoHchtO7pieaHM2LchD0HbrbIpNzzx3MToM3sghqDUC9mGBuehS6jG+Y87kAgw5819sikFvSwVOwTmU3s6L+Bpx9nIZFZcizMkRjQOFhcEVaxoCGKlyyJGrIhUS3R3o+4L0BcC1FTMeXlh7m8T5w9UErNiWsgmPz6CUBVKAm+/Ll67IVRvWZNF5mnMylEiu+LAHeOhdFUMeCamknvq+BplMsiaq0BjECu8ZY/x6fqxhMqHm9nlYquebyxUSwmSOGxmS4GHI3M4taMtCl4vdQMkKxqRiKr9YlQh9A1VkLtdgNxX91qqQBnQyV7LpVxtdsa2F7DzaSxDIk6y1qpmzTUZmvJbknW5M2qC2Np8oW0vLVIeRUEWXKODcExtW8ZZaJ1TolthaYklJLYZbQCrSXmNpNFat6SbXTIpPYxaG4J2RtydmjtccvGyrRUuvxusB2lyHY0rIMyx1LXCa2iU7aY0nriWe4lzzTopNZPKDdUyM2Po3MIl9Kl81XIYR+j1WDnqwqqQC4GdS1WzWaSBlySMFAdMnV0yWPUDWns9YusxyTyXQyNKh6mTbtUHqnb/d9kjP2euyrCkY5GPk7LraQkWL9BFnO6RE858sCPus5d45gANyj0DIDrIGZR5CqQlYHYIkm3hCVk9ha2QhS59txW6mD4mz1qcUPhBFpU6WKdRXyfQiVUh8ws+WwWonDPOwkxZpgdmDDjAvuW7QOcVP7BM/QMzPmkVwv8+Xa5Ym3PGe01bWQIrtMsr09Z+LQkuSb3k28RTeEovQaY7BwZzAqCeZk2A5LunPPpo1RhzytH2p6uizB+dlg1NW34ARLT6pmAMCtZM5+mb36Opzc632rrmuFda6pjGZXqTYQvr6JTgaVFkVq/AxxEa3qQZc1NrtIV2ulS62F/QfIiEDdgaG/jT7urgZwHm9Su3VnTaC55hQIXB4LeJCMXLtaLuqOSht1pSzRttqawV57+3XbBe0F0CzP3tBUf4Zm/d4sQfHr28wg7HmvM+e+3C++SPt1NtR6459M6+l4yx9DnHVk4eCAR7ezdDad3tWzQsyJbwnvFqh4CZg6pyhGjOtp3rabuOXfutd0DIOOfRoM5jsp/P9b0H4NUyrMn6n/aaSFptbTsMRPRvhtls7+m87a9pwXvcTsGGtkTnWQO5k7bu1ladGPIfU759pweMmTtLcAzx/ZfGNECaN6DxmFz7du+lUZh58pvX0hCRkLDZYVfKaZPsOP6rZNyeSTQSyHduclJj1g+UDO/RAQRbnguAX08HFoOqUOypw5J8ENX/LHii+xdj/X55Tf07CZyz9mvOpS/RXL0XAfBc4U5yj53wl3j5TcnpVJRGML88B1r4vvPmWsvJ8UJ1o2s/Tce4GFuP0mnsK54i4LmrV3g+5Ia3vLnxvKeBRP1cBgefEpmtzx18k/uvwhsHUcM6NeAXVC9j8yl5QAZz9ick8Lp98CJb9Jd79w1n8w8INHsX9CNmMS9P84Vv9L8FJyRZwxctc9k78ck5JydZdaEoMO9ICF9Tox9B4OEB95IfQ/sg070t1Acw0XIZdcNRF0Cj8qcoDmDMtPNxhVd9Abgmd60kpsld1eBSczl0dGN3dxCG8EMugLkOCzQid54HcaJVDD1ydRC38tDe8rZpD5UOC4VDDM12chDOcfJsDO138M8yx1Uywzpf9SoVth0KCUCqCBDp1ZcncKccCisQpXQoJ6QZBpC19exNduDmcYYdc6sOo9cUYXDDcGN5dNCmD0VFN5A/DiDyg7dWdt5IiOcwMoiPCoCMIuQyBpCECQxkCDkpcAJBNndJ96CpU58a4F8rZLZs9zYB4qwjZAsDhRigJxiAUjQCx29Bjbku8S8yBvVZwK9/FuwDDqUM8VQ3hE1m9EVMJ9j3DXN58z0GVji+9yM9ioxUVC4tjB4J8mVHi/QVii0hi1YbijiEiV8LYli+RniASCIgTJj8JD8NCedPDZipMKA4CakQTqtxcQ0QjlD6taiXDwcGCxCRiYCrYtZlVwFEoACEogDgIQDv5xsICCT/jESL8tl6R8JAieC7om0ttc1IiLDDVGSFBiSzUmVe4hJzs0igMsknCaCXCHsC0+SiMNjXjPNK1jpLIuDVt71kcsjm1MYOcnERDYS50zcrhNiFVtj+01TYp0SR0+Dui0puS1DXcjTGD/iBcTifYiYzQKSR0jD+DhC3CMDPIj0XSGTY8jjZ4bCr0rT5Dn4H1jCcBnDQCHTDTCi4SoCjigJfCAUyTkDMSEZBDkzsA5dJsij/j0UKBEi+UljC4kd0MEzsisNciiz8iJsId0yRj1QsyyjyNRTbZNTeDqjHFH8nSCjSyOzyzzTWjdZJjnNyD1VA8qS9SXD+j6SCVhiv0ZN9AQxdBsJ75sNoTBUtyhI4U5NsprZli1zq4/jPUgUl0KAJ9F1SULjc50wVc3hZA+0+YnyItviTdwV1ioV3ydBPzvMsoFRnyniDjdQ7yBAHyEVaAILTyvirykxrjbzBBFBy0stzzS5QToKgZMKQxp9xh9y/RDzULcCgKqAQKIs9ysg8K0T5zOSdSRzdVUzxzjT4SgYqBFA/QzVspAIXwfTbUsjhsaT1pwDLiFcjUtzaLvTSLiRyKEi8yuT0CIisCGiWsTS3zeLs4BKFQyBmBhIyCJSA9KCsSs0ZSiy5SBifjXTbyAY4KrY9y5B691S7clCCzwi8i300yuKiVYLOsozv13LrT5yG07TUCVDHSjl1D/KHK4NgLQLSK3K6LDChywd1K8iQyEqwykrW8UqMhF0wrYzbF7d/SrLbsgzXDKKYjS13yhJSUzpBKbc8yvKhFCzttNKFSqL40QwFVhIGBSKGLZBUiBy0NMiGynomyJLHFjk6qXsYLBAmrRhSLDL8KIrqNWKcSiz6jer6rDIBrNi4VFLsM5yzLLsujor7VQ86iI87L/z1ybysF755VEkVQ5ML5FFgY08dQ3rhlPrusaBZNB59NOK1j0LXraUQstYJ8LcCIuCZj75uR/NmAHMBdEa/zX9rz7lobUa/Res8c3gCIm5rMYae4J8QsSbe4ULpKOVAKDtBLaReVAJ1RlRfQC9Vo2tmaBARVvrNjytsboilqAalNfVxhtMObWDVKdrNKOc8TVj8ritaUG5rYzV4sPlVIRL9AlyRsOcpKtKZLjMnlxawEBbfr2TN0WLprYqmJeTQzLCJNVbyhr4TsQwtZxSBzgMGyky3o6DFqdKLB75wQe42DqagJtYNSgjeCOr5quq0Y/KIblaDsKatZ6dLZabPKUc7aAJ4rk6naTaCbFMugI7EadaWdMq91c7gzzDHb+SHkUaQ4S7JaVrSayrVEq7eA/bNFFb7KU7ocnzG5hd1RZMDR2rdcE6o0Ha8rC7G7sp3Zwg1d2bqRaQ6yprKqZr2kDcFr6aJzG6h7e4zoL4PbxqY7Iqu7sT5aVz872yAqJMF6r4Tsfr+yY7JJrrQjbrly9qHq6ri8oVYVtxmAH5PQQ5frpja9zl1QDRwg5MBwkZObwa77IaNzPU4UeQQKJ8op+KkbIGzQSRYdTjsGbhhaYsoaoV8GUbPN+8Ix+KyaCL0HZBMGEVaHhh6G97fi8aKGgwXwRV4HdAwbBVFMRReGssIxtBwHSHtLuLAHELwgwF+HOaV4371tN62KjwOLkGB7DJ0GIgQszUBw9NtbUM9a5rMpDaDqlqoGSRgGwFxHFAZMrbJSLLHoa7iyZ6C6G64NdGGAWRQGmGuRTLvapSsie6o0A6OHEqAGwYQK2CjL1Uo7s6dT6j9Sk6tG57vGYmgUTRZws6bStTR0GzTD6M2z8SMmKHWRCGzIEm54MqSc3HOo67Z6vGKmCHWCcm2GO7fTpTqqOc0mymWn418GDQx7HwjGJ7kmp7kEPH0nBnS1hGHhNjHwkYLF17L7Gzt7ndWzA7uLhnFEPl/GSCqiaNdq0dnTmnFTuGYg4nb599Oig9P6MheiarVzImALyH41ewFAyxXlQGJGhaCKvnSjfnQZtwBGuajaGaPnS0IgNQjQsGG8SHAWqAjKjKiHEWRgpHCt/7PmUXFEiaKxsNabh8CRYXvR4WWGlLOmZ9660LUG4NAJopfC+GFJwWN8dRewAZF9Wb7HJGdmiUvmjLQ4FHWWlHZbpr1HXhAzLGg675opyQ3bQWjH+tLrKSxLgCIkLHaW+qYXiQhWJbCX/mkD8mFz8yEFsqbKZmBnLnPmKorIzUIwAmvaVHVH7SqqVoarbL+WjUyWvy4nDKbgeETXIq47gcfKWz+mlbynbW4W+0Om8mtrtSim3H9rtXDrSW8W0Xqncnang36p1mDTAz9TcrPGbWYXM3zEopcmkZHDQnrL2pI3+7o3y3vnRgzpDHSoLrgnXWbrsipn7aeq02rHGXvQKRql+HVm82tYN63Wt79ctnd7IX96GXeL68yNCWmGz6eCL6Tnr69rb7rWdWF0AY6BQ4/m7mTX36HnLLF37qRM3nnquGQoU5lAQH4Cnw4KIGdQX3YHL9BAm5ygkHD21hoW653k5YZNK9W8KQSXk5MxhJPM+Yq8YOsWoX6XBktzgZWD+8I8KRp9UVgQrJmHxhcPzk6al3OHIVn2AZSpEoRVc8AOIWZi7zaOow2iP2D9UPl2MPbxX2wEGO/Qb9L2e3HnNxTmn9pWh2g7g5Sp9G/210jQVWJrTHNW6SH25m65eP5GiCOPjXmKRPLLaILXur5SpP4SZPVc/H33ZBlRnWOSQnfb63c0ImKOonn3wPYnsI9CYOg3E3CnN6UnfK+6nqNOg4PPsmk87C8OumCmorHnim87znS2j2g54P2nZZ71tAK7836njOydqqZXzO0upDIvoYyPa3HPemXDG2Quy264eZOsDmW8FOnHzKzX47w2TPHqca6ug55UPkgJqkBOzQt30jp2C2cizHQNnnCuyk7zEZRnrOCFjm5aC06iD2o3Qvk5+vX32Pxb7mlyTkf773XP3n0Pn35U2HyTQG8JWSCPLvRS4GwZLz1O6WXqMOYUCIn7+x2bNQCP0UiRB4+YopvQXyDqcXXZhIFVAewL+ZIxyPmPPuSDKX4eaWLn7RzvXZEl5XOsWXBxNrXyLBsfXRcexHKwKLXuUvtvoe+PHx8xJNxW1HxOZZgueuqfz4GdxlsIBxLpySTH1XqTVOkvZnevqfSb5GbuqxWuJc1Ki3ZSrXNvReOf5X7N+I9XlATKJnKuPXaCFem2tvlflRyR/X5WPKp3/PZ3AuI3WeRbpOkfygTRxoknk28vRzSnFf2e3YAfYdqmLJew6mdSEva6CuzO5vvfB5HefQYut11mwnMoau2f03k5kYZABBHxeeteAv+3MDTP0ek/9hseeVS46fwY1nddZqd6ZvQ/4kU+ZMSZ1eIWJrtqJXme4rhfgOlrC/RTJeu2XWyjr3xZnm73Lk/7GbXYANMJAIzyqWKfCeJ/uwp/6L9BGKgOPeQPMfAR5QFQlBvvv1nyv3T9gJmAgfxgfywe02IfN/FEbH5JYfELtxkLYOvDt/e5d/7/ILyPwex+r+eYiRyIRrl+L3OfluBZD/8soM/O7t6xuL7k2QEvF3IAIZ7CcXGNRPdo1k0Yd8g6W/RUOjSX5CU+ewbFTs7i1Z58lqE/WAWAjIpmgVKSA9rrkjcYlkRenvLAUZCNB7kNqYpIJn31oHUEquNlFzrNyYIv9EkbBUkCSGvzR1t2ihSep10To29GiggnkMINP4XRkKzvSqkH3gHu99eSvOvEf1v6pUxB3pAPtNQ0GNMQ+JAzAdfzkYR9iqKggRhV0qpx9X0cg6RuISoDdgWaAAvAZn0t7Z97sevWrkwK3BZhi+8Ai8rWSnb1kAuFfBdlXwsHwl5Q7gkgi1XYGv1JB8ZJnqgLfgbdtBQQgGFmC6CUDe+9nRcgL2/rixf6lPdfu9yZrEgdwp5PchAL+o806hZHM8qNQJ5f9QOPNbfoogoAIoz+B/VTFYL1CnFBhXHSjorhGGug7+SFARk/2Dr39GA8Fdag/3mETCUGNQ6HCAKgYipcKQA5GjsOwpnVlKEqAQcZhgFkcKBHQpiqqzWzIDhyrfDRpJ3iFTCgw/mASnWBtxKdz6hAmqsQOS759FhlTOiicKoF6c7hwRWXgUgCGJ9Ra9/YlMMDYEKpjKdna2g50cFOdwmsI23vCUQq9CKAIgtKmbz85xdDOVvR6An1xFvCYghI5QYYPCqQjY6OdV3m3zHKMCgRiFYCKMIMHuV/e5vP0rO1MElsOR8I7kTMPpGlUHBbrJwTFXQFr8xR6kZql4Lao0DuBYRcoTyUHavCH6+Q7QMNTCG6ZRuChcbuX02Y1VtmVQxUTuGVHgUURjfc+s30yFrcb67fBUUHTkZCAyOYI4oeiNKENlb2K5Soad0fZUdXYgDJUCCwiBNChh+wCMcRXaEICIWXQjfpYHQanQCIj5BSL+WgpnBdM6Nekfvw2FncthgIPMXeFmFrCoK3NYIOmM6wMpVhH/NHoCMv6WBhm1aPYTcPZZti6hHYnCjGOLHNtAQowZlLCmuFJjlGJQ9UVfRdFFkXBxtB5IA1Vx/JcB3wiun8INpqcQxBvCwCOORQGtoxB5agfpweF0DWRA7XPoCKWpLjhIirCIOwM15qjQ2PAnXrKX4HV8z0dYgiESMMENwJBY3C3r211JHdKR84ssouIuj1iugJVVQebzJENsU2OQwIUCPLHQFeR6VAUQW2FFNMrxQdVCeYhgn2CBRPTV8UWSpHyCz0+DGQMkhapfCroTIn2lnxkHT1tRuE+EsIwYBmhqk+wiIYmyiGW8YhFoxducIeRUSVc67e8faLSEASKqs7SVosjdG5CUJCoBgLCh9EHcyhIEt+MGJTGljLApKGgLPDkx6xyKXyaCgZLlj/JqyqQG2IONxphjAQWGRJPCl2KwpuxtY1kGYlOK+xSUKKUft0I8kfwyUxcXyaykJ5OSC47xfULCjCm6Sn24YlSY3BFTAkbJTHWvHQCfDEsWSZoMyVaKDoGTyQSqRYqlMnF+jpxHUeSXGBeFsSykyeXBKSQMAPx+eAYjVkQK3EiSsEBU2eGAhMk5SIR3bcqUZzl6WtWJoo/KTPCTTkY0WKeHwb21lH3Z3xOos9BFIrSekxBowXzkyJDbSDNRjicia4O8QrS420ZevDejUFusNBqbJaYuM8mXoLE60ncMYM3rYTzBNU7xHPCCkro9Ap04SNKLmlYj4+YE7jiFA+lyxf0OZRqbNNE4UitRl4safCQykfUgYxUlDJEJnZATJulfUPB1MGSgyRkU09Gitxb5ZC3eUAxcRBU2QzkDynAqcR/RvZD8gxJ3OKQ5IJCf4TqUYygbPxmJ6NBqsKRMReU6EX9v+rMhnPWKzFrDYxuoHvIoGgLflsx5/PPq2OZDSyKx/ed/o/0FQSExZCFOYdWO3Fvd4phkbwjik7FJj3J6YY2X2LBGz8cZ8aM/MRXHECzbhA058VqieFSsyZcGfAreM+Eig1xzUyquJSF7siMB3Fe2WOMaFHj+pXA6Ec7gYGhyuU8qG9HePv5otHxJ408S+IKSLS3pX6LWd+Ncq/jNpTfJNkxN2lZVqp8MrlKLO/GSjYJpI12SmWGlnMQ57osOQ3grHoSjBmE3Ls3Py4etbZpaFWWhNsEMjo+LOEiREn2kLivZ6KcSbRL9n0SXZjcvtsxOmajSE5RqZosJGRmGixqZfZJoJP1LCSPxLGOeTRNWFotpJJoxPMTNnEtytByEqxtvLUngDzqGklqXdUZkj8qhSs9MIlDEE4Q5MEYPtBmEllT9AFmmR8PSCEjJihZAU/+bfBvRYNUaKoYcNzIMDbhlA9mR8DhFSB2SDZLM5kJguSTtwaGQYFUOREFThARQyClhhQts7NiORf83UEaB0znQssA4GBUCnNmsKKkc8TLKA1AWFwYS10uDLOAf78xueyMBLM7JjmrddwCteUUpKsYAKQwiiAxtyHka7kA5brIOW1MUlPzZWEi0lFIqEXhBC40vDEivKGkwiN5bcolGoroDHZCWpKOjjTLKnlT5pxZHOVXKNQ0LzkCHfiNvzQXFzHRpc3wWvOrrKKjF3FAJTekijqhIOs4c6b20ulIS4RsrEhdgq6DxNIO4QJ6UKIaYijN5X6bJe3BNDJLx5GQmUQDOcExLMlcStKo3EfDaKoZ5Ivwe43sUqKslVAc5IjHHYyKjsB86apjNiHYzT5cGNhfXhaWuKOgRM50YotdGtyelcSvpXPGnJw9QFxo8ynTMH5fzjuP8/WRjz0nMgDJ9IUuF9QkgUgRFgqc5VnDkxe5vccCxWcLLOVL5DY8NdUKnHQWQMPplZcoBjRDj4L/JqY5kP8q+6w9qaqcKhQRSwypBqQVNW5owoIUnLDZBIDKQynkhZYnlsC3hecnMhoL+a1ysBaiqBGIxR6WcCrIi1gWlTnGg0yqUDPvpfosMhcGWcDSEiZB1xZQ/Wi4QBF+KWVlK0uObRJWWLGes7egTiIomepWVpBM1L5j7S+gPF9KrxXUpoRSqDpLKj5dSHDq3hQ4dmVJdDM6WFtPZUKeFYbAzq3iUlcEleeksMWNKiUEK43sTVvEFKe5gfYpThIFVoM9WkK1ukIFDjWq/OsfNVU3NNXxoPp9IMmJLS7IfZ2l3lcuReO67UijUGU0MIoBjXYZhlaMibkfLyInyxFADJSoJGPpIpQFCyuSe7IUkrLYljqhUKGGqQXxNMOyq6gPzfgMzDlkeeBWCv/k8wjJfqcoBLHAVvYe4UYi2DJgFSgrTl/8/rpFMZRIoo4BFDzF5KxQLq/Jv8t5f/JWpeT+8TKBtQj0gZCQ3gc68jPuqYXAcWFbNaGFlL5QTrbJS6rsklKyxMpB1uU45eSoxjuwipt6peHIqnE2LGVDSlNWUpo71SAU98S1Nys/kfxg5j8h1f4szDdSB1kCcVUBMlXdLa1/i0DZNOLhoKZpT4yeXHN8WlLPUR6tRKArWkMoa0hqjpVEpMJMq3OpaMjXIn8QMpfpNqlkX3NJl5S4l26u6auio3Zc7Evcg3CUocX+K+NX06KIEmIl1teBCEoDdKqmXfL8ZfKCDTrUYmRLE1OfZNUpqhRdR7IiGH9ajL4nozoZealsgWtzmkaVN4M3DfZgrVATKpV06zVMu5AwxGU7yJeh/MDkdqKhTM7tdOt1BzE2hkc04eApC0NCABTs1fkpMvVmlUW/QwsTmJrHpgIyowuWRLLJXxaBcowtWbrIPUcsEtfQifOrPWFTr0VzIAErsJwpdjBU1W44W/PC1kqrGoxaLo7MYp0q2uu7e+RJ3DWlpRiVApESqOEq6Le2+i/4e1MmVQo2tVwsLeCKsX3DBp6GuGSRvEUwEPhyItOWiJVUrzvFXrHjUSmK2EjC5fIsJekMAlGq6NAZfrYZGO0hVCJjIkuZdssp2qa18Gr9OlolFZRiR/I4NVhM9WvTvV4i3Ld9tCr1ytpNS/6fJt7qKbNVnqTMhSoXneCCNkza7V0tW3ibPt6KfUdxNGq8TIdpow+eaOPlxDXNM2rskjsvkE9ntskpzVWs0G3aCQEi6kKdSa1WYaBey9tQcv81HLmZiuPWMDCi3s6uZteS6ICmF3PQYt2WzdcHSZRHYkto8osdBQexAwZhmW5XRuoQVy6eYoFfLVWMK1tZ5dwVUrQVvPVr8WFqkfrsRVNnS6VdIFD8o1sPHNamdqmPWEDFBF7zEBGcgDQzoY3aMjd7yfSquNG0ECeVU3MAlNsLUHZ3dO5CgU0MW1QidSK23TfDteovrg91OjgfGvWj7biNWOxusbpO1dy/xNGhNVpL2n+6hxge/QMFWgl2Cnt4Sl7Qpq41si4NwGwvbrrB2iC+RQmuAiYMB0DzptMervcdPB1ETg1hGmqtPPAnp78hKuNavAJR0+6bFMMliZjtWUC67CQ1PHYAIJ0lz+JGMizQjDJ3A7isakYGLaMklXzHNonZzRko73p7t9bO53Rzozlc6Q82mrQDpMC2VagsFk4SInlf2i7/qAB3QPzJX4y7tdp0BSJ1h2JK6UthPevN9jGpjD5ZoilsbLuQNrpC4lYpsdZiclwHTdBu83XFqwMZTVJK+fYQT2RoUGdyewgca7v/3qgZAu5Jfk7K60y8FFESKvTuJgMkhEkJJEbfgIiobi+VUe8nQdgKmAH49UcxPaaxsUp6mDwdZPIIYMr2j05DEjEbUph3YiMNH2xuoQatg/izt/4m+fBM6ro6TVh2iTEYZK7j7G9F2iw+OkQn2rH9xWD6eDEKG/a+9gooCS9KH3R7ocnh1A3XIn2E66djzbxTPuBnBGvQKuHskvtVEr6dpFe9eRvsw3GZEZwkKslLqNEjLohJO/NafrW0eH4jSMFIVJNv2Gd79bhvTQdmyP9j35nOttZ/rSPh4Atry6A6MRgO7lz2fLVLcHR6MAdpFYLRBlAZ7VDH5U5yeYgimIaYsVd0QZJN+OB4YsuC/OiTEsagk0MqWxLazGaRmOK64edDT/r/qIVBYjiCRkiqCwQaCNFjSSpGNcbh5GsMDZ+g7KEGSTkVRjtxv9Z4p61LK5xcOmecVlGIe1htSrTtj8O3ZiGiy/K0o+8fcFNw7GtzS2qhtE5KGbDxmUE3LHBNw8nWyqtrnttDU+KNVwJ949MYRUm8c252mSavuNUxHmVjdA45SfjY1sONWRN7e3vqPQ4tjtc8MAG1ASFL/Dg+5Q4on/ZQTWT1S2+ZiN0OAygTs+kEz1l8nttuQ4zVHaMs6XxyC9r1CRcJgNHnQwWk7UzbmqKOWaSj2pxUwIbcmHM16cEgtrUfe3uH3jqNHliievm7LWjRyPzdpM6OYHoDAC2kPsx04p5OOKugM6ixzzJFAOExoLS+EFJIwJ8VeYYAsN6z6ATISHVvMmZjN/7g6mCpYqkBw4KYh8aWPQFGouUkciz+HCrecdzNyAKApIejlGbSn/U2F9ZwRe+xDNnDh9PJrRai345NnOD1i/4zwflOxHPcEkTMT/kEB/4oTzOGE7STqNp6QTvZxRPx3aL1i0ThnDE++tFoALKyLivXB4NII56wksppiPns33uZSzfNNgnoWTM0nzDdJqwwycY3jn4zNggZbIR+xl7YdrekpqKbzMmQKzX5l8s9r8OicAjAFhUPma6AyF7CUpyI5ZWiO8GdB6NEmoSD8LTmAiJ5sNl/ox2p6yTNOIYEZVVxJE88KRAowJNNMn6JlQRz3O8mpBW532Hgwc7aXtMM6XNbxoi4KUUR7csKPmvRd6bOQ/6ujkx8BCXGu4ZAm1Ny5ocyD1idZUgjymlTwuzM1nRUQKWTF8uBW/KOWakfFifyebfL9VqlolHpaFZQrkVsKwY+paAi79oVga046JaC0NxpjlCpLMpebMEgHdeCsAdlk0y3LlD4lxRB0GBrl4gUrFpPXfIBNoDK58J0tEyhwhA8OVH2Wc/WnnOSUJDXFwyHrGCtwC/LMl+QzbU3rbnB52V7uNsXlVlr3FOFrOURtJMKn40TKDS4OpdX6qHzcZCJRjPpMoXPeNl2TJaocs/mXD54xLo6e5PZWAY+l0unqvmXuqB9I14PoEckPxXJr5l/1VaoQshqzzco2Kxacav5o4KI9bcojnVNlz2jOmwKw7sg6hCr15eTrJRaP3UWhE5py81+loSHWTs5LPvYhbpgcWH941ry/KnyUnZm1Al8bUJaOQiW/Tkxv/sv2STALyekAwY7Detjw3Rj9PF5dDaC1EgnKwwYKyaFB6SyiQreOgIBFWOmhXjF62XcTbeCk3YeEYUHnrJmI42Em+NwlozcctY2czNN0OMuM4XPcaDm+WlLzeziS8bZ3ZzfjhFpvJIRW+PX4yquHPO4erQI2G43gX7p9nwIhraelbGyLnCLktmim22RPoXjxWhzOTRBKsS2BgUttWw6wb6aHl5U+3XvoadPj9GWuTYBr701DtXyqzh3C+dZu2YnY87tvG4ktN6OHaTnGoTP9aXOxFaUVke+Lkoqjdz/tImrZmJtevB2SbidyPuEbAtO3quyt0gbSgvIq4NbS8rgU+bwtanM7Jec5Aqj5mDLBw++8JYfvM1PX5qL1zI1ncAFl3CWJa6o79ZJlt7lDRIUem2x75g3HmgYztQRbQ5BbjyGWM8uZBkuSzF7TDJfgQRUvVm5uTlELKGAAG+gQVgx4ColGUB8xsoR94cBsbPSn2Buas95A5YWGwV97pWx+yip3vxJMKQkMsLVq/zb2T739xgHsJXukrlDclDLOOK3vy3ut3BpW6OcZNYItyYNPiAAM2Jcqxt091qZNr1sNXIeNFSB8iP/xiq1Rscz1vVbHOpd9Y3YdQ92GqunWdDpE/2hQ8QcYc97MxwufJEUtmGOrzeyw3hesM7npO7D1IPSK4dBqIjft+pX+dGtcnY7kPVvGfe8OyFZrqdj1QtY6gZ3u7SDxRwNzEeDXZN2vKeUXbt62YDAC89B9H001dX0dNd7Rxh1HpCRgYAAggvdZzVmj52QkruwYZ0dmPTojY8tXacVsvMY7+toOI49kCrD/8LajEh/q9M86fTfOs4xmUmsl0c8652S4cVSfCUyL1+TG8wupsHHQ4u/JM1yDBL/sElGZwfKQeQksLC4FThDoWcHxVnkbRTuWBPgjxyEanifOp5ccUy+Wr86+MEkkv6f0cMnlNva+Pw+Ml1+z5FoTj7uCdKLdrtdwZLgYDVfl5OM5qDb5sF4GKxr8jzftM9sZ8XU8hVgzq4w0d2OfHqz0E+wh/wVFjzDD6HUw+c4sPXzAwNpy1Yy4gWfbAOKuwHY6gvmA9ppaY8U9gt2E5CQ1uUzI+rVyOwnppBpx+bvN/c5rz0kU0HY2KIvwXX5hwoY5lMvPhryz+x7ESOJlgcImFhVNhaedXbq7bz4F4cQJr14huyRHCA9fbuePSdtF5a4c56wjdyimESokE7gchPcHlD00oy9gvtEeHraw7kJihsFPoDnWS+ECiuU5YlMksjMcq8ktXqUs+Tqm4q6kyuR4aMKAnAQaBtqJTijmU15/eMwyF3YnNfvL5giyG7VMygS5OLU+vOvun0RS3bnkSgyZ3LOmWQJ5ddcrVMGxKtV3llFPdhZEQKalUG77QRWFDiz3Egg/eeuvSsA3DWj1gMDuxtngl3Zzg/2fwv/9GyONwtgUzLZNzFzmF/hejeZvz7Fb07KVB22EmC7fAul9XtdeGu80X2E1L9ihfS5nzJjvEW64pB5p/VjOQdztejuivWHUh815zWJo/ZCcqLopRo7MFLWsrbWO1xa8nfOu/pUR4k0C67f/7BAatNPoZZJC5uarGogF1c9dt84DJ9kFlJmpZQUA2X5I4/c9a5fbvQ3l8ICKWubfSuAc7F4e/+YxfFZn3sTX3Ipg028ZZXfReV/q8mPDBAY/+MW0jcJ5ofeYT3OW7Ftqey76QxxEMAiwpuopB41zc+wTZRda7UP+Q90KAw5sLDiP07A++zaj7euyGqHuwqWDx4Y3eFigNM9mDJ4m2uzdFtsS/xZDo3eQMDrg1FZHNEvrnIUND0aHvCjHeeqVwbOHtg3KGFmWETD9HP/VkONKGR5T67FU+8Q7bS6bPdS6QvEmDtQj9iTRRMjBLTepe9kxqeHdpv6XFgVj0BZ+7h2ELUjmd30VCd4OyxDH2jl7ZTsRHwLhnSC5B5U9RfRoLBqPoe/s/bWw1SXiz9MeJjl2k31jml/e87c7iyixxIGE3fzAt30hbdr9x3daTePH3bYvL0klAYD2hXCnsL3O/Tf7ByvJJPmLhCMpT36ZCT4S76YVdiWPkCqKBtPyjngLpvrOjmXVpteeorITLTMQMPQOCpfQCgFgRrsQM321vyMFgfrvwMEV1viQhsXaPO90fnLDcGgOclZrUGQ3PyJFE94YPzeWtsrB3WaAjnRbOt1blAb1pZ4+fT3uoab3PBXHCGtPgBHT3s7hcRfAbe3/7yLtNsuyTP8vF2wDbkswpU46h7bQSYlxEmsvJJ7Hwc68ssGNFJh8QdO88hr6K5l1qn3yYcPBfbVrh4t0j7ksneR5EQHw0KYgvounPplnnwRIb2bX23LewKw9+pAXykjFd/9f87sVmfmvNKb7Fl133hCYn2uE0xy+KO/u4rC6CSKvkqM37Oviy2d5z7Fc/J1fr81/b6PpVxPGYENjo0k6cs5mGApWOeNq6G8gG2sx5b33h4E8mWJMsFDaWR8JvWZgKygAy4SF+4KyubNZhgK3hj/02vQnHqP05XD8o9mPIf4zO+WFa+WBwwflXQX42UipffWH0q/78NuARZbGNwr+c+B/RW+tOXvnMg8xQafNbsPtVtBt5WwnMrhvmv7Tbr9q8xPZz8255EtsSfVMHfnAe1416tvifkv15+T5LfB0w/wgtz371+e2klfWzE93wc38O9AvTvTz+oI5+I/rfG/lP/oP5PuffDAOjd1o/M/t/b/H5saOl7xeMPjHYPo/ytXacVTJ8AV9PFff3Ic1/LnyCxjqOeButi/UvncdidPXzNMDfSZzf9l+TwX7syYQe2b9LfK/3ndocaAMAhJ7Fo0Q8XmZDwt1ZdfpSZZinHTnKgo3ay08MfmSM0whg3Ajx6dKAigy/JEzB7jf1Cec5ApR8WU4hkJkzC6iO9vGAQOml2OZM0iwGGFSS4DK8FPiG08/NBncFmWXfH/ZBgV711BlQIBjKIxnEUCMp6A4X1TUkUH5lmduwYN0b9J/CqT90//HQSoCPBO8VzwToPN0wdRvGDQR9ArC5FPYDxLDDoCjPP42T1LnUr3sCPpRwPuda9FtyJ9rFEnwJdkEC82JdS0TgKNBbzCSC5BVIEDz39UjA3EP9QguQJSDbCaHioE6fWqm68rffAJ0YJA8xAuQISVdzUd5rWt03cvAqoOxcISE60n05NOIOkcvAyWDXYKXFwNvd6fTUxCDerVIGOgx2MiwsCP3BANGVv3TuxQCVnCNV6CJ7d9lo5Mg2LjA8QfEezb8MVSax+Z2OcqHg9/RHZzwtXmd9V6caOJEgRsxPImzmIrgmTyAExAm52VII/Wjzn4IyE4nJtI/Vbw2J3Se4g49ytVpxeCc/DPx+CbnBvAhJ+PWT14VbiQEgr9EbcT25cPnJkmRI4AocCB9HhcDw9kdg00iJJCCArx78ZoHW3MZB/VAORCSaZkkJZbuAIIVsgg2twfccfLJ0FJ8QzANs8UjToOzkRglWwS0LSbf29t1g5kTR0BHXIKYEeQ9Ljj8gvEoM5NR7D4KbwYvP7Ti8n/RoJf9VfQ4j+CQqT/zzsm9Lay6DQvYwLdJLYbMlBYM+Oz3L1lfOe2v82VKclyM0QmrzG46vBGDmDGvBYMSCeXQ0MSM4eDr1JFNglv2419Q8MgrJNlIbwd8PTUgOH4u1d3yT82ZDZWuDqQjV2jCgFB4MFlIwqYQZw6FGjxfJDhBvByUvgt4KeCmabMLIUmPUEMGNEKNMOEgJ8BmxLDzgrA2NkBFKEIOExdOsI4VDPCZ0WDthGAg2V6/WTysCGVWwKU9VQxYSTlnFTRWACtbZTnh8i3PAN69FhTsLMUqQqXgxCzxekK5D4RYcI0Ux/QSAdtK7Ffz0MVfRkMWFywz7HlDd/WLjADUmEd1TCTUBDlzsI7R8yjsyg6cN89EKQsNEd7/P3kf807C0RVCDwl8IUAclW8Il8OQ53BFDORbwk+omLA0xND2Qrz1pcIA6/1JAoIOeFItQWar218tSB0KEQnQ6bhdDX/HmnRRLJevhs93TX2x9DcA0U2aINlYgPf1PTZ3zG9IbCbxQ9sbRb3uCTnUM2RsWIhYma48nNgJ9dqbS722JEzTMzKdoKckBT4m8KpzbwwQ2Il28bgK2Cacp8F1wzwBIt4gRROnYs2ki3bBdR3xcnIZ1EiHvI3hXw98VPDbDXQgYF+8kSWZzydew33SxDhQAcIPDyQT7hZDV8Slw8F83cG0LdNxHr189yQS7ksjgzRAgn9ltYIPgiKg8yOcihDZixIIl/GIN3D4g1cMwEVIlUmAt9CU8MFDYIgF0Edq/K4GSjsXeCylDL/Ue1kiPSb530JPw9R2VCvVIf1yjxIkKjgtIXb/2edf/ByIp8rgGXyFYKXP/EGDV5OCP3C2ojPC+ZC4AiGZdyLVlxmDCjJAJotygmcKJAJzI0MPNjebAMxCtgiD39C67b7AoATnAUKvYww7+QjDE/RXFkxtwHcjm8XdUsOOjVcSXRe9eI7j1jNHWE3S28stRYzcpQKA7wT9Jve6NeiZhM7w1lFjXjhWEbvP6Lu8PfUIA90njG6P2M+lG3SaNzo9aJBNvpOPXYNAfUh2FclnUU3EZM9eX3HDfhScO8iZo58OOjKDWQ1OFgoxQ1Cj+o9f1XMRQLGOv1URaIKW1VVUn0c8coi4wBiXKEvXSjtpIUKyjQI0Wgei6RUeSlFz/C6SKicQi42+ix9HvQwl6gtF2f9qoskNUwCIEkCKpWfDLzZxj3S8M2N9QBfWR1kjM22sDgJc0Ixi0ufUx4l0I6ZEwj5qbCLwwCY8Hw0UToq/VTkadJvR+scAx8JNiJdWGN4CBpJ3x6J6I13wOjPo7m0/x8WKBSktvpQWkyc68eVDDilLEGnGNNIq/nPc+aLS1pAFjZGx7wLAnBSvd049Y2ScmCaBhMhHXSsD2NRI5gnJdyzKS1Lj2GGsO10t8GTAbMcVFekTjM4vMCMp2zbLB+oAWcWLrwDrVc2BppaOTyHM0Y1N1aj1/TPEcYDzTWgNBCQ0Sj78I9CCFJD2wn/j9gB45+ijiyYzHxGlKYyAJjihAScybcPaQJh6i89RKISEK4m8z7dI6OWAFDuYzKJyCtY6ARTikYDOkjo2TBuQfCRXO2J3F5QIuIihiaG+IqiGg0TQViV40/H/i3wwCDboE2OL3ijug3uK3xVzSCJniQw5fx5jjYxBIwhyoFCKvVlQI00J0rY1pBtj6fJr0cjvCZBKA9T6ZaIfw/rHyPB84iAwN4sI4gJBVwRvfZVODyAsg2gMIxBPGMkoSLD1oMWDPhOVRUSW6KuJJjdyg/hVI3YjeDkaPMR0JV1c4lMj2A6AwUT/g0VE+IUzdMXHxPNc4j1l8w6HGGZkzZKVbhoQ6zGMSdIqmVZIq/K21Uw9xBPB6kzE9ENRiuvGqifjG6JcUHgoompDJI543WjxjxDehL4MHEykPEsbEmkNgdbaCmItDwo+xOgZvE4UjGRF/BmOCJYgzkLCiZwqRN/sUozhDVIPPT+IwSD/DxNeodE8UIUQv/QpJd5a3TixqigsdRJCpV0BswVCwLJUNASgdOpODoGky0gbM7w3hx1CWo0UyolSiP9EvgQA3bWyC45c+MVwOJBImqRgSeAONMPHZsmminw+2OGSFokUiwDzfStTsjGdXuLLAVJekBZJhvEgM0k5XRiIoD6432CvhEkJt27jo4n+FuT44oePETsWfiNLMsyNOKxpRIvWEjoybTNTzjlAkvD+SusCyxppa45m19g3iNmyBga4zm2DiazQqXNIb0ZuITi7jDiLrMlELLAtoe4+GIOw/QS2CsRB40GmHjGYlN0BNx4veJ/gKAMomzcFULWn8TaI/2I8CpwoZN7NiUjeNRNXE4qxiTioiczpSj4yyVijGY9JLqtMk3yOhSsyXVUzpb4koKNjikuwKYEpUrNieYYEj+Mkd2fDR1qTFY5SOgswUwBPLoBfBLyF9WYg4FBScbf1XfigIoxxAiSk1ZxfUBAPuyvUx6NBLiiik8AN3jLQplHpBdAZehBoCEg/TM16vKaJ/cf4nQWRSWaZ1JPp2nGhMdw9knVPATco4i0X0u4zYhIjYnZlK/oAXM4MMTKgr0WujGDBgIqRQtAH0eCC4r9B0CDAQGL35EDbmVLgRQDLWS0PopiJzNAlRtJ+jGxYGL4Cq0krR1kSDYFIAZW8GrTLTBbDlhHE8OCGKLT8UpIO7g5tUdLJTIrC33gcqU6/3OQaKTbRh8PIrBy8igk8NNGC50z3WAN0feRWiSVwiVPB910y5H4ottemNPiHPBILwjwVUrD6EafEkU1TJki0T5jZWXtMFi1YkWLSUxYmdJ0ZpjHkR+1fxYBLliqojpN1TtA0DLB1HtG1PxdBk3uPbSQsJ2LokbI88Kx8vUuJPTARxcIEUxNffIwmiqLUNPmD908lQbT0M1NOdiHRJwzIiPY1DIIzvRdnTdSltP2OzSLkt30Oj3pfNBkAgDYyPYjCeMYIsDBMpszeT57HM2oydVISOqdUUWRhIIhA4SK48JEoLUUzaQWHnUiWnETKBtZMtSMrMEU1tJrNdGPtCMiJMhTNRozM/QM7MVEwcLGDSQPN3k5rIpcPjTVo7EOAy0xPL0SQpzNyP/w3AjhP78FzSjOvFJrATLXMP4U51cyLbPlN7iG0jCx8SnJGKNSSFDMVM9ZH0+zL0zAIVIJ+c74qQQ9SLwpVKBEZM7LMKCCogDPi4gMs1I0yQqZF1AttQtpPTswEsyNrEesJTLKzGojoNtTp9e1JBki42cC6iqXGCLOtMEzzNrFnuXI0GcKLUjMetyM50JCyg6JcTZV+XFizjS3ZBNPC9r/RhkmypXdhO51OEy5O4SxLY6NDBtXaSzAdrLE7NCVQrZ5Ukzo8SgIjBlATS3MwjLY+z4DlYwuDLBLXV7OvsK0hHTGRzLEuOBUrLd7LqFbLJFWByjMq5OOzLEXy1xUAHd7NhyI3fy0RC/3NLSgg0FeNzCtF05N1HjKUwKwjBFEJK0zVOVHRTD0F43T1QzjorFRFUGUjMC3i6Q0bLNS4eInNYFPrRVRFS0k+BPVUL0ncTh4nsr5zhSA1bh3lSGfaJVXS8M4LTBz+rdawMcqki/21TNsyXJwgAcr7NatVHRUK/Di2ZrKfS0tVXI/MLMDa3Vjc9TWKKzWtClA+sr3UnJ6iFUz1NiSZwnCHcEVQG61xU3HJZMQCVksNLWS+c5WOVBOsIDy+s1smcV9DtgsbLS0ncqBPOyLY3aPOSkPQ7MI9oDIkCfB2QAdSqRo4tkGTyMPW9TMy9XaHNjMwoFy3Y8ziF5FwZ/qV0ADVaOJRJLzB0g7HLyEOZQF3UKUY4CUjg6AvNooopDUFGAoco7PzzENETyQwc83hVJA+83+w4w08uzN/CMIO5KJBlUYNxloeU3ZPcz7IiiNvBnwVBzU1nwYxnJyTgoLIytgk1CynyblHqQYseKBnLPSmcuxKCwk892HU8ppc+05zUs7nIWlpkiTDbyIoVUldA+ZPLM6tivR+LNyPRN/KgTxsZvMKjFc/fM957wCvLKgBNEYFzZZY9d2gyt3TpMgL68y0k/yNU/O2Aies//LxFC4J8Da8N8xChtyxci6wOS+0S+Eq8B8ypE/dHQhrxwiFs3AuAh7Ifx1w0nsoPJsCNs8As5FyCh+CxQT8jNI4ys0p5gDiAILhITzJEqHksUx1R+wGMkDSQsRpjJPVVbi64yROx4ic672LykWUsJ3BO8gsWjJ6UfOJTDbDdP2ClRUelEhSxdNQtyYO88wu7zxC2MwNA/YG9RqRADDFKQNHC+sVZoX1BxlRzkCgaiN4DxcdXBYbIilJitRTKHmCo7xC2D5At80Q0CSB/LgtFp/C8ugHUfCs/N5Tz03DKySIi/oSSS0zT2hSyivTL11Dn83nNQsrC1aTySuQRJgqzaNYUN6zocCorH1xsTplAKakpXKySdCl5BXRJYG4EgyEC9pKQLYM06BMKpNaoowLtQp/NKCw8lQ0JU7Nc1E7ZiC4YLKKICmNz6Fd5FwssgLYyal19PcijO9zyiuYokl5dI5h2T6dTgoYLFcNYsRoOMC9hoi9o2eyTiCQND1UgrJcJO99o47QDcp+1RYhyU7syYSNRiPBuBcloyZJHXU+Ayj1vE9Cs4jBL/izYTbTISndQeJSUMKW5kgSk9RCkUSuwtUSxLITy/UvC1uD+KhGc12cKTJD4onyBo3UGEYfMwIsJL24EIrxywi1DLQ9KkKItvgjKJqW3yC3VlPxiDi3q2pKkNFkg+L0iiVViyZir4tkQcNUVB1V8NYbJ/9xUrIt898IS+EqL7pU6A2lv8vhw656inAqJR0S9hH8R1S9jXlzRYsAsuLAS/IS8k1pdUsek13YU3liYMpNPTBES/jW+ksS43NPMSi6YuZyhPS6GOL2SuoINjBpEgv8EVi8lXK8LEDYuBIY/bYoyJdixeOyIyEykokZgA44rrMybdgrE4LivkvDLz3SmXeKuMe4tjyyA+PJxLnLXbwrxtXYyMETIGCsuuzdIzoDhKSxNtJl9wcqDhyxPi2FkDNY/JM18K88lsoVBuyrTIUxQaBYV7AJINsuAtfQUcpryYWSYkYUGysdNJZ5ygZ3aJbEmf3TBdvK+Dysps73SDLQi1v3FLZIiq02dWObdPcDd83W3NK3rdzUxzAoisJFK0NMUuZzjy4nOiiQKB/KKKNY5mIyyDw8cspd+rLziyBWSLmPyyH4xVIlyHc1splzSuOpD6TfbLVPaLEi2Vi7K1rMqNZJ+i+0sQLpfQcrQrPzOCqQz5S7AsgqlS2FkA9L3VyI6wsMz9NM97c0iqxSYpBsrtCTRIhNAwSExMtwjBwuVnIqVspyMzKHTHMuHYGKyVw/gBCigk4zhCg7J4zEUxXHIKnsvoxYSHkjVzkqgIBSrwTSUpstDFZKoG0qRvkjOKQMoodQu+yaaQwt4zjMQytyZwU9OIsKy8nStpAIc6yuxK+IxPNRoK8QN1eTrMAcAlgnjXFL7KnS1vMmtVK+NyHiGStxPRiyC6Y08xcTVBKZTiQiUDhNhi8gpKwFKRSs3josqf2fLL81vMiqOCIVIKL70n8pfzzKuyo5jq42VNAqf8uot5iGivnBkBAUTTKtT26NovIiyCnrEsrDUwUztLBfB0qGL/K0kDaqDStVMzoJii7QGS7U3UtfzoGI0FTTUEpYtsciqxumL9qGf1PwTbTd3NmC6C22MEqACqauOB3aWNLOK79OhOvLFqvMFUquUsStNYJKme150g44zMVwoeJbHDi9cWzKj93Nfp2YCeI2cvb92kBM3bKpI7QtbhkUZTPkyni11yBqIoBSK6c3q7DD+qpy6GrBr/9ANibiGy6MxV1HC2cBRqOzRAgpKqYgankh147iPzxQq5dPcSJq/PxKJLFU8vciAs/bMvKSQ5CrxF8a/pwizOzR8vRNMqjco39Kag8ySzaQT8u0NmohUror7YqHn2Rjw9Cs4JRc7q3JrG6MWr0D8ozrI/SOTKrKyqRiwASgS6szCu6rsKg5J0KLyKBIajvzJqKPdSfb9NHdBys0Egj/CbsDmq+okWr4NHCwmlwSps8aPWrJovYvmztqi2pywMLdjlWzDqmo2Orvaq4oHh+nbaL2y2jbjLur+ypP29AeQRflbDrMeOoKEg/cxMRrg6KtNf5XgzMLF14s4/nRZyPDOqZcRGW/h2NUeZOtKxs6kEMBCVC2MwnS/+BsKXL7E1vEbrRPOMO+88ReOpZA8rNEL3KMfRksPKzU+vBc95/Y0O79zywLITKEqvqu7qcbY22pD2arc05qkQ+xNHq2c1kO3DFfKYpZi1arOq38TwzUpC8hg7zxIr7Y/epP8JQs/xNLAMs0pDqJMfOrv9yoB/2NTQJHqtFNH6j/zS8tQ0aqmLzaxXGozkhArztqSvMMtFoCMseyq9FkwhODTaCubPoL76rIyBsgG1kMuqd2Qer9Dh6iBqICFw9jPEqhCm6sScY6nvI99YWe+D5kJif8KHVyaFSVm9REoFHvUQYpP0JARGTb12Jq0cmncF9vdhvBK80trClsdwaAkbyTo1FPJpu4DRQ7yro2KT+zoaPUS7zn1VuAYatAxOwLSvCgeHFRcavePvhWhVHxRIlGkmsXyQ854VFNYWD7DZLsBTkriKKczwIOSvmeoUCL1GgNHSqOoaf1XqgsUxvx8/Ufq1lKgytLOdtFS+2JYaIgAuWtLq0Cqq1L/bP/LPq+DIJup9DSwdGaqmMmYvvguG3nyaT10V+tkF362xtSapNVSWNK4ErAr6Yaq/hsmsTfHMgAwQGi/K5qAaYlCjLFGkzRgb4yrGROrZGghjl9pSwFX4rg6kxtAy7fEyR3BCihD2LLwwh2sIUUnMYiANFsXLEeS7griJ1cqsTSvskMyYEP9UnMYZzuIrYBzBNdeAvhtNJ1QqFXCwlA0SLFD4DbLD8wnKu6O5twSKxIWbWAjZrhCcUytyMCzUtZ3srkSdXETdnGrMqXyqpGULxCfEkXFzdYq+IuCzEG8MhRDacpbHTjvm1xrRyESZkJ8SL4G3CRghmpv09KMkgJt/jTmmVJXdwm4+t6jqq2WqVJzScUPhwD3Woql8km15tlCQqamhXdtak1OyaZi24kjIM6KdxNriilDJZbMyTqMzVRcKpqmSwGzARZ1Kyf1PfdYyonQ2r4GraplCuyPlpYSbcI+sYzv48Fo2JAw2D0DLfYghpd9RC0sucqxLLqDhRFLJtxRzh1JfDasbsvFW+qCQXzFpBd+bTB+UjycyFKJjKp1ozqgYF1q+ygcmFRbzzm+1ohzfW1TPeTtdNXSCk4cjy3xVgQH5l8tzsgK1QyuoLkBCtM1bHIMbzi35pKbmQb6nLx6U0nJBbrGtlITbVTfVVpyUcpeprdqmtxpgpvpHNqbdyWJVQKqvS3eq5r/WwCvVyDVSlv4ciW6JvsC7WmCugThciR1p1EKlqvFLg4dII/NqaV1UZa363WrHavWg3PBA5cwpu6zim4lqAp61MogortMa3NNCu2ytvhaw2x4xdyaVN3KablkhMstF52vPH9z2ct1W9CDyzBqyqj2/VRBsKQaPOGboNHNLEKyyj3wAV0aaQvUxqGsM2+lpqxQoPjJ1JhsVwAlDgneI11IfJIUVQaEuxRF1KDvcwIKJDth491bFLSxb4WDr0Sz1G1pmwKkIXFMSIOxhqQM2FIFFJKvNYDoOSTFaaqcTyOnHKKtDGxTwAsPYCvGFJKmSDVprP9emvirl4lrIuMFIRjuQ0nGhfKfLMisZogK1FLjq8aCzAWvRabsJtt/LKS4Bj9lVSgTW4Qj67DOt5127HDw7Bqs4jY02fL+PW5Ga6Dow7+NSWH9gZ2rJrnbh6xDtdLpNM6U5bvyr0v/r3MNynMdRk9TUFa7cgCz6VDYeZNvArYekBoKsIzatITOK38OmVfOqaQc1A6oe1+bE04TtzNgu9jGLhB1NFv74Hi26pk7qhHM0cK841VyUrUUEroUKSU5Qr2aC+SYhBKr1IFPMkq6zFEBSfktDuWkWugliFzHKhYSdrrChFGppeuojoL4nKdujRSPK8yTG7nC3ys0br/fWpSLM1EKu+bANHts94Ma3IuBpXU/Np3zp6oTt1yieReG/U007lIWdGcoVqxadBDbqlKY0/Kr3aMW4WuUN+u1UrLoaim+t/yIKp7vq6x9DzCarO2wl1HazUpV2mrzEV7rgLNcyqMGKnurrrfi/urrOQzxqtbqBEx3EiyOtXUgLtoqnuokiM11KwNNbtYGqLplaYu1psGQUe+Ytu7JW6UzY7qWrKrdcEiQbsji2Es5K/bo6wrsvV9yR4zOzRVT4o57LWlNtuyRuqWQplnszNXdbrLKwVdagVMXrrq20iXu9biaINs1lheuy0stLmtTNl6eYJ+357rWgihAEtelhLNbO6rlFuk8reHJY7lOtzKMaPM5nIRFa2knJStJ6umr27LOo1BgES201oKtYWlesPbbet8vOaOc3LqZjVOhaq9llemVNdV8WvTtnbArd/ntaBrWzkSbVWmPupI1csqunbMmyvWZabelPsXbB2wiqFriK5PrBZb2q3LjV7uyJou7CuqxmCFG8f1LutJW1iswxoujipJ67ZdwS3aA8wJwfaMG0PJt7LSyPJJUP244O5Lv2/VquakUuZqANOZGspHxJ+iA3LSjC/4lWaEDXOtn6Dm96Lm6ASg0LZbfo2uuZtTm4g1u8ZeifohDbmyGJObT+qg2nSaWyFuRiXEs7rCqx4/5sRbfZPAR27uSgTsj0XegUneaSYhbS97pO5/pgUfEujK3rQAnerU6J4nFtO1aff7or6v0zNsOJlSevTHlE+iztb6pnA5pL17OzPsc6sq1ltKj/0+HqIq12pHtIFeWhaNapxkttwKycMqvpFbAw3I3NjIu62Ob6r2mlvlbKB1IW6bsymUI1a2MyOvicpK4hvsKczcrwMLjJGQrfUZicQcDZZ83QAo7auvzwSSGu7FDYYdvJCNa79C9QY9bxsWFG6691YYFRLa8UODBZVBilCMG1ekNqm9PJUkqUKKO7mWiLqWW4o0tN+mcPK9qi2koDU6cNNqOq9kxAeUGP4KUuiLSoSxu1tQWvfIwGyxMvGO7vCjS3LbzWQAd7jTBssGCG5ARTh8bHbIprfEQ+wZFMGm4CjSqK2GSPpoqguAzos8VB5oviJWDNAeWU1WqFD0GbOsfF7gcBxnyazHS9LpM79BtAssGPSlTu5aXypFEUx/S691tK5Smx3trLrOoVZJQu7wYi6Zs9l09qEGy6yGH5ik4q1geB1Lo6KlSi2CRgsu0VCVVcu66t1bv9MfvV61LSQr/5YwqYiPJVTK4aTDc8khrUs1C1gxzrwFLov5xC674I66ZVL0E+Hy63PzhVvpV4ZrqDEmRrNUIKMkCbqtAxGEhGWwhcPFsW2/wr/5uw+/v3Ke+4xtQyIiq7y79Q9Kxt27Kcsdt+55wuHkXqABg9s6SgYYgg3CF/NkN8aIB3IfjQXhoJUPrpa0+sCtmRr+slC4BhBKT7UMj4YqV3wyqAz62h78J1yuKgUagTNQ+Cs7o/6gIdhH5WWZSgjNbDHroGORtymJsoG/eQWGQ0pYdlb+Ru1kgjSYejJkkVW9AfqGmRjUZwhqIg2OOGRC04ekr7q9zCXxMgM6PBENXI1tdG7+5MLMq5arsEUQzm8YVL9zIDMDQNnon4depx20Md36mbMXQvgRmM5rK0wRxfrlq3KMjlt1IDUvzTHp8b2MRGq24/miguVb0fN7DY1bvCLvpVSBAHMM9/s8ieSvdItGacVUyLHrZE9OM9zuwLoOTvqSsYJ8708vtqt0sxkYID/R4wxgH304dtKH9OsgY9F4xgMZQHhY97te1VampqjHcDbAZFHxcqHs7GQx1caFiIdTAtXbC7cofb961NpD1jqB9BPAqOx5JuBAdwIwbLTmKjq0b76fdivYG1a4OGQiPQujLQanRanr5Hrx/UG0B1JZnpODR+x0djqiUJV3vAx1etRxtPiyCc/zwOtFkUHwRpkd/5VBj2DXY7ld6nrxkOjCd4aUJ0tBkIDQUwqasmXP1rddzoDQtInRGj1tzxPyAkvtEHByBjomSeZKRgm6O8UpjcaHLwaQmSxvsP8GjxgkCVcxqKItLM4PGsZ3S6xhIqiGhJ/UE/yepdicjpyRyvo5GSwNIZVjU0Rtsxb6B7igonqitglXQIgDUrZGdSqcd0m0JqoZEY3Ohcapa/x5nKImcJ+RD6U12VoY3H2h3qs6GHJlzqMmCm/cYR7C+/kcEALUY4rEmtWncNoGd4nSYgnvlERVmG0WeYfdqyMvUeJ6GxwyFzxgp0ZA0n5DdBsf792b/plUYp/Yb1hr4I4Z1b7R75xEHf2pFN+RADfhMFI/fdqMu5ap0RPTqIx1Zx7QiDedWUTniRdE2JcDJRL2I3B5suqm55XA2EatEnqZhROph4mrClB+UGvQgSZxObqvCBabYn6p9cqraiQb1BkMWptEYHrcppkpZbaUV/h8TUkCer46hBz/qXj8puu22m2DE5LZJlJq8debjptQz9RRSMAYmTshjt2FaEhDqZHHrS/kJMnu20e3+n7DCpJ/rI7FWrvrQZ0acaSvSFpIaytcnKnFHHI3qdCMTpSpJXb/J0gdhn3sCoxzIVRvsbvcKR2DPmnmUO8erJoGoNOabxlGSfajkYBI0ym+yTYat7YXUe1YxhIE5LwarqsqeEG2eygPIKcGSQYoLpByBiFm5BpDEHhkJlMbgw6q6fComhh8Eu5kq2boarzebQXolDncgwYsGaJ6y3ln+KGwtDhpG2WahRDGZwdvVpZmEfNmaO0Wb8rOh8gpzYmOhDlVRJOvwYzbBJl0HlQWicxoYBeOrktrGrp6QH26uKx2b6K/UB+CUm3Z5eqSHxSuqp9m8ilIMyHwpg8Z+nLu3qwNmtO3ouMmeRkmc+7UMzOcsmk23yddiR2mnpbbVZpoaTaxhiHpAT3JwK0rmxi42fz7TazzvlHiGNYdZBGAI4MNiQyutwLmLWnHqCLGmmmYvaWm1KblBEWNYfSGvyVmcB7n2gcAMLyMB+FKn8uohoFnoDRb3uH+jPFORot5xMOWY2WQXoyD5WCsLmM1jazFkjPh8mxwZj5q+aLDCWE4xTNLvEEdAYn54+YMioR/mzGM3C5Gk/n4R54x8Khp+2N+8UR742CKVu/sNFNIfHEbGZITR3v47ne+maCxQFkkd5ZHGJ6cx6DkmBZpGN2QqSU7rAs+N+mBdNLxZH7/ak106Jx6PuwXSFrkerYzO6GaQrkFuXWRhPh7Nj6L1x+jSz61a++alHR6Vovc6Tcs2oCHLUaHiVGO2cemJmT6yYdsbvsTUcPm8e2rwJ7WBonpb6J51TBl9CpIiM3Y558ufzGhov/n6NLqmPJZ648sCaeGAG4RPmahM9PN4TrFizOLqyks5tKcUzbpMkiszYuu6SoajSNLCnFjp0Mzg2qTKT9LE8zLmdlGkJZsycao3ofq18MJKmz5ndEYOmh6veoSSXIm2v8yA5ySaDmZ69LrXY88OJYycEhzbG97kCrxLSWHnAhaD7tJj+oQJWCICtyzgZqJpqXpE+wyNrcXGyd/N55mpu6TUo6QM4XA7MUY6GDussHCw5Q2CqVq/JkgcPGzJmZO+wRksi26ipFwltJm+q2ZJGiGyt2vPaPcy9qs14WslzHwFovmqTccp0mvNGhko5M2VjInaM/aQJ1no9byvDSyjFZuoRnBAK8F5I0rNZ0waEg4aF7JMrL5usExrjKprramY9AFZLogc4boIovlr9Qcrxuu+ZpBAPdyo+X7dBFb5onm1hLxSfS89wrxgq0lN8Gg6gSZmXASgXE8w7xGKoQXLppBfUXnS7FZVBach5KKXlwlZc6HTBwXDvFbuk+KWWiF9OfDLY1dOmviFCyhYinqF8UuhX06RqtgTxxxha6X8x32EStQeo7vB7Wk5GZbIfw9TrlXAViVZGqAJMaoCnkm32Go6JJWaqWXbcrBf1XW4FUhWrV6BvuUXiEtgd2XkCg1aFwqEg6u76klp9pqbgSM5otpjFm5ZH67lkFaMTMKL0ZbH088ryoEp+lb0DW+cUwecVAx7b1+TjffqebTgF5ZoXxfYRi3kiu0vfrF1Y1gMcP7u0uaYtgx7KgyjW5+YtfTHcxjab2XyvOkGRIXvfFZS62Zv5oOTTB+aarHF5HGOhMIhq8upWuk6c2bG0fSJPk8Mi5leGW217sdvS6RrIdTnmHYhYkw81gGfAzTDRpfznkmxdfsNEM2obynmFmlNDG1xrqqZa8Brmr3WdxogexmplsiQCGf4M0AJnsY1Ucinior0C+LiM7UcSnZs5KbUX+UvbzvW6Yk0fMMzRuoafXHvb2J5mTF25bMXKp0UF6AIAUcHyBlwUiFABYAAgBXAAAa1gBmwfwDAAPAXgFAAAAMUsAglspBoVy8NgAxgro5QGeIj1V+LI33BatF+zTZkKBI2bBC5EUB6JZm2o2WN0swhAM65jZUBWNnjcGM+N2jZEbKNjOr7R3qGwXI36Nqjck3+N7jfoko8OwBQAVwLgCgAUAIgFIgLAbTex4KANxRWgRcBlDWqieCSD2HlQMjZ6xToI0AmgTN6GFXowwEXA/LAIHIFs20gevAs2Q4Xxk1xXNqkfc2s0b5VVwSeFzex5wgUlHlAPNnilPZgtrIDVo+7R1tdAToaLYbtz8ackda6cZJCS2twoygi3DNECky2OCCLgtwwaW3DYBbNvTZtgPN6cqS6C+Y30/Ict7Rr+xbNzUHdgQYR1rLDTkmrZNRLFVLZimPqCZCa3mqUIUdajQeUCS2j6McQi3IOMsDG2OgS90daZZJijK3AOAzcs2CksrcrG6EEXEOT72srfBgHNtrOLMXN2zdJAsSjzdLhMxJLYDGMwM7elmmezrYYA1gjzdyx5IKqGO25YcoE3gvcNdlkBLtmWSrIvcV0Hmwxtj5DGWAdrrDIImtzwZ63vmYQTG3ysLkCe3MGOoIG2LUG7Yg05yAbeEgTgKWmwUVQMbbBK54M7anj8dkCkRgztv+OHgmtySDO2rIL1DG2JNwnf82zBr2DG2vis9iZ3X406Ah3ieEHajJtMBM1T5LtwLfOQadtXUu2DYY5KZ26AORn62rCz7PTgpaGQE8xHgY7eOBOsM7YMBvQQWCO2Xh07Y53esaYPu2XKQuA82NeTqvu2eFRTFN3b42Xe+lXkVregZ1m0rbULFAULdN2vYOmia3edlQH525k7zeJ4uQTzGh3mqHuDh3MxT7egZkMBgHx2xTaCH52DAXiHx2PqYPdhhba53aggCdvsH52Dd/3Yz3SdlbYDVZfW3ek1z8fbcBQ6UlXYD25sDzeBg1dRreJ4suYYBr3SoLpvT3oob3eb3X7IXZCwi4ZLDGpDd47YsVSUGvY5oIgS7YIgGAOPZGdSbV7ZeGNpLPegYVcgwFiAdd4Eb12d2vCnCpjt43eh30Muh0u2eFa2Br3UWbnbt37IeSGb2QKIkF+3PyB3aEBqGD+K93SUPnaSVOVZUHp25I4/YpbOt1PnOga9nCZs3ieA0HC2md/Rk92gDrHZ92uyMokGak9ibaZ2BZLfaAP89jzaD2sdsbfIg3wndt/sOtyHaaoC9xqTE2f9tnbv3QtunGB3n9qA/0A4UyRfu3AtpZgQPh8mQHF3PWhfcmafttvYkaEdhA/Vo09+7eOAy9o7CBQ00VfeOh19ylXVpx9ixWh2BAe/IP2AiUg7XzyYN7YchSDtWj4PjttjYYOd2oSiDUn90Hcp10MjHYD28bQQ6shdAYvdT4QKBXfHs04GPd8YPNgQE1BLD5cTm3HHbBRcPfJNg8JFvQEnfQzHD/mCIK29xVWfA79n7DEj6dyvI82lUDYeCPYceeG0xe4RuIoODD6KCezYUbvZeJojugAbyWD7uccOtYBNm33LFCPZm8rowA+BHRgMvYIguQWg9V3xD80moZsgUQ5O2b0aI8HVNiKQ+u2md10AihK9xGIUPojkLA4bOD97ZAohjxvAqPIsn6miO4DIFBSOX9tI4rx69qCGqK/NxI/UV2gprZkxrD6I63CVjtI8QpMiRI9dBSQfHYrCC9raZacBtrw/aPwgTo+CPEkfw6Z3ToNlWMOMc2rBFws4Snar3PkDzf2YOS1nfpBInF470xRt4I473QTz6lz2BDHY5sOAkVSGUO1Cpeit2XjxgE+Rx9t4/+P4beSEu3YCk/xFxhgY4BX3Stm4/gODNdOOX3gj2bYM33NQYD+0ltk8jI33NELE9bMt/zHGOqqD8pkBT96Hk9haTsVH6sYT8rdKhmTsVH6Ol0T/a5PxJXiVc28IKyDFOWaXsFn2Ytl8MVO/4pA5i2hqBzfc0gYNTyS3QtrXcVPygZ8BhPYGJqie2WLd4/VRmC0o4uVEYFU5s92nJ7ckIDj8LpCwqD9hEn3MtjFFFOmdr2C2n2T4NzL3WSErZ/2uJV0Ce3GARE5m3cDNg7KI43Xk97gu8qffOoyaUQ8NOQDik+/FrT74QzUuT3kF8O29tuDq3pT3sD7QDTrhzi2WT+FANPVcGDy5PGuAQANOqjrmcbOJTj7ECZFTmU5hONcCIEVOBAZU6S2gURClRODNDU6mPhDyXYM09T8E862eFUHfc0TTxRGHOU0JGEtPjea06YY8IJ7bpWxh2zY9O54O/ZMSwz1zb9B0Tl09zdi91GzaP/Tqmt5OysPtBDOdVA49YEb8qM8Qox94s+HyEj7MJHODTp70WPCaayAzOKVLM++UptqY7zO79iRlLwDTjrFJB/jy1CpPOt75cKOkLxTFlOQt4Xbv2oJ4YBbOGj4fNdWDzkg6Qu5Dtvb7P4Tq3RylVz0c/hPcdN2oPOxSaHYGUgtii9KhUjyLem32LwDlKO9QRLYouckmC/S2kTj2EAhwrHLftaHzuhjL3EGU85C3Wz0o6q3KMYs4yxUz8BF7BXznG2x3vldrdEvTsCyHUvs6/S/CBRgbg+G3TjrUFEOFzvnaXOcz4c7jdkocc8YAiz+c9SAJ1bs/LOOzv0FfkDNHIzx229wZo+QBTj5E0t9Lg0FuP2zpLZjKFT6U+SQsLrsHwSsz28p3AGT7HiRhEI1LbpOZlKY9RbB4BXd1PqO604qMKtrk+XOYThBgJqNz8oGKvBDZvC9w9zx0+UBrYR1AB3y8A472IfcO86vPor9UsZ2wdwM4ouZZAvdDODjlXDhTodtjYg0HLz7NTOEzlC6YvbgEM8UwQL0k+x4bLqg64vJzxy74uZZU6GHObYf7dW2ar6K4chFjui4Sv1IO8DL28L4vYivyTtrOhPoruCpuurNkSM63n9oyH+OnNiU4yuSCCLaIzGL9K74owKR1sC3e4aK7KJSrx1sgvIbj7fouEt58Givs4EMBy2bYcK7Kw4tlTSkvor6oqUvitjq76u2D5S+L2TKT7Pq3NL4c8+RF9NrYzF9L4GELhOT+LY+p6b1Gw4QLLyptEOSrv06lpidtvblg3Nm7YvJ9LsOE6xjzvNAuJbNjmgwCvt0YA4POt9y8SEXTkRUdPS4MLfhOAzwsqlu6GDW9OhBXTrZZqWCr3CR3HTvGwVY0d+8SS3LBkE5x3rYAK4Nvkzts95uLttveGAQKAk9+4R6026jBh9qXdp2tbwvm9xUbjnbnBLrlM6wPUlrnaS21bo05DuRomE+9AmGO/ft3i931Gtg2D6XcJl+buGgzuldxbeBu5bjO813Rtrm6hueb6Bhz3o7wdUQpTdjLDgKpbvkDL3SUe1mjvm1Ju6d2Fb2BQ9uwWNlSmOY78C7BZ476O/Hx4TkPdiODbjRSYt+dqPd5O8bdB1ruLUYveKGB7iwMRgl7x29KOYGPoStu/I7u4rC17q26jBjpPvYr3h75XfhPa9mzmjuVmfq9f3hBVO4X0B74Q/XTo72GCOvAUYaITvyz5x1APR9608slPbUA7MQ0rrsGNm2dfnaX3tdta9Af9N1A832+76u4vvV8Cs/5u+QbQ6SUT91u8M0C9lVyzBo7jLGYTksB/b7vH7i+7f2E7nW6/3ig129XMjbpJQAOd7xCLL2wDqY+tvUz+SBltZ7je7gfGATU6OB3bqg7QOyiQ+/2R4TwhHpB/7oO8EeQ6CU/Dvodsg+Pspb0h9QOaD/+8GATdxg8sVeT31E9hUDpEnlupbuGjofbMHlDuuRbQQ7FuhIEk/2BbN7m4L2fD1O8QfHD0hXeuG7ztnkelD1+7nB5H9Q9Tuf7DR50Pq0kh/VuVHow+HukRRQ9PIl7/ZioPtZha+x48bInOcfnDne5yNYntYPXuGjhx53uBHgI+pAgjg28RRrRno/pQ+H1x2h2Yj1O4TNywRI9VxcDwvmUeej9I4OPE7wHeyOrN/+69QnL0ekKPH9wviMf7HgZXaXbH8x8cOLIOo+BvYHpncJE2qUu6mfEjjo+0enHno5MhZHmIoqfhj9dSlud8DZ8mP8HxgACeWDOY9kfGn2p+WPwnraaGPSbVh5ie9jjXgOPEn2cGiPTj9e7Sfojj3XAPSzbh56PFnnJ8XpsTt45EfjZ/4++PVbsGi1gQXwM1VuEzdm7ayAif+9OfHr4i674bOUo/xYPkaO69Qbr9E+c3s7+pzRecT3K95sm9l46JOUUHXfZKnj1M6IvjNnQs5YNMEF6t169mkAUHzLnrEYAEOYLZpA6AHhWxO6rrl7FQm4NF9MPmXwV6shLjq+B+PuXlY2ef8wUV4sQEzoY+BLjD2+H1FfbjY6Iz/d2+ETcSuWp81AVXgwKpfZjule53b4FEufAhj5q9n3WQQo/LvpNIagNftG6zeee/Zx17hTpzlgzV17bw7vaa2D5HilenwP5FwuaHbi4L4kFXLGpe0FN3J9eFuAgkheRgA17ZoPT/470xEYax502aQeGxpu7LvtANerIGV4LOswa18vhnc1rZZOvURN6y5+z6U6MHTXxUEU4srwU/KAtXw16v3FTog5jfzXgq4/J4rlt9eK9MAc53B9bn16dfzL7K4g4BXt6nwhFT2c+LeQ6LPaXPEoFc+d2bXoN+qv67ul4JwPXwUih95X5QFJ2XTwPAFe2aUuGPPc3pE8pe23u8/B3j37LK6uGrtmgFffQe1jtPozjF5XfabB7ZGvVcbzQ/fgrqSCeVejdN59fgr8V6J2XbsN9psC3qWlu2L3kt8Vf/TiW+LfiUdUqe3vt2Xe1fldz08B20ry95tuG8e8+Peu3tD9h2P3/t7te/UwE7I/OWNl7zx0dyd/dfodpa+9edC+d/A+sL1d8Tvydr2+PeCcbp8MkdHoj5VAanlQZZ2P3pN93lfd8xzrfyXK9992h78T+yz37lO6feFB6t6lp8RFS8g+E7e99+5wrSvczem4eE4LMtd4D50LQPmm4rvq0lt/zevyWu5s5kPk07YPm71y5jevi9c452O7mN7BO79vYassY3gQDk+EkhT8g+kdA0Gt2h3jD8ykmTjnZnuGP3zYXvE96j45fR71Pai+2P/Xes/J3o+3fv97jQ83euJO/aw5998T/9y6AGveGOM4mN7tvfz+/fvvj3wL/w/79rvcU+liIr/72bP3QHkgivv+6ffnFcr6AeZ9p98+NR7yB7M/DPsD4QP4Hvr+g+klZB4M/4PlCOSxMHxT+GHmH/12v3xPnV6oPwrGAwa+jX0A/IeiPy5QvvhPrY9Y/bXnB4YfqPsm1KOWHhj4+x5HmA4DvKmTba7Jpvsj5y/SDwbmEfxPvj/YecDxN4UspNrshkfj3i8hwadDmtAW/ZPpr6XpYR29+r3NHkaNU+X3vR9kwDH8z55e7X0ld7gov/95E/a9TYiseKXsV8s/Gj5IxA+jeeq9Hp4rmH/5qgIVA83zzsNz9yw1DwFRbfCQLMnYehKCG/E/Gvnn7CfSv5UDh/zD2l5tex7ex/0GUHyD+0ajNeLG7BS4B779rpno7EAPXv7w+MMroEd6++AjloZh+CcdIESO3JKr7pfceLG5NQr4cH9GA3DpY9Vx9voL7SOTXxH58z2nhO1U/EUUo9kwrNvr9Q/pnh05l+QP5u91fR6GYVZdSfiz4L2trmb7s+md2C/zvb4fmqW/jr+V7VfXrmZ2PftvlN58WAvg78M2nr4X/fOXjt6/V/MpAd5eOnN+L+de4/wG+V/t31i+YPqPt75pikO0v9Ug13uP4S2ovsjnb+0bxeiE/rjNLcDNu/iH7v3EGGTAd+mvkm8R+liCm/ORUfueHov2tvN55eWL7Ovx/PjMc++URtqB5sfWPh0+NP7Lsj40VCtuk6LfJ3/oXZ2/Lit8neXtwh5rOeTyd8bcy3pt6AhJ3jaWx33NDt50LIGi17ivuwFt6WKOPCDvIc4fvbZRX/cd5IHb7CcqbQ6FXfU5gAlvbs3Rd6mnAV7LZIbbZhTc6oAw5K2/e077nH/5T8RC53ndq6TvRvCHPI4A9XMj4f/bD43vMj7K7ZP71TeS7/oOnAa3N95wffEQW/ea4vfAhivIeM7DDL4ik/PTBfObM65vVAGOMSH5n/evBRfRNAdATy5c/VAGCcIbYP/Fj56sISjegdt5hXAV4kWSb4Gab/56sCH6NvECi9vTQHegCyAgA3D7qoOvzqnHK6aA0zBH7Lk6znA14DZOT7IA5d6QfYT6PGaq7xPPVhDUC/b+nRq6aAzzDirIgHSzTQGwFdB7kA704fvLQHk/TW51vQPaycXc6PvMAE1oe+Afnaa5gAlL52nH94GvPTCKASa4rXcb7qoPP45vLwF2bUvDqnFy5RfatLnbWQGB/fWpR8HU4fkWs4fvc+75nHQEaAloHjXdt4LfKs5G3Fk5GAj94HPQoYGaQc7mAgoSEA8c7WAwYGp7Bd6XIIq4CvHfif/Y9RLvFt7AOW+7/hTAGDApbDN/XAHFvW/gy3Aj7EAloG+SOwEA7CgGQfJqjxnQj4tAxNy+XCEJJAi4F/iSM7+naM5fnC4GhHakCWnf85RAvQL0A4C6FAxYE+7EoEGvDXAiKCoEz5BYGQcdXZlnNk6DAlZjdnWt4LA/K5mgdQHNvAV6JIA+pRXD96K/XwF+XAYGQfcG62XEmhDvBb4y2cxxWAid7Ygyzj9XOAGbfAkFZvEK7lXdEFQlSa6OBYt648HCa7nXd7ogxVRPPYIG6A9SCwoRn7dXfa7Ygj5BCAgj40AyD4q4c+6JAxgH37BOwjXVgELAoygeXf04/vLgFKAXmxPbPgH+gUn7GzZAwpvAv51dS5DLoNg5lhazbBbXCp8gXC6V/Z3aDlJRxR/Wv72g9TCGwei7g3bnYOgkISTbVv5WgkmhdfNf4JbP0HPgZUDGPP8T9/F0HvtaFCSXDuICvfZDegaHbj/Ft4Gg9YHT/D95vEZq5z/UV5u3CF5x/Zf5xg8hq4g3rYwtdMGwjWr5k2Oc4+vCM5M3CC6+g9MGkgUIYA3SwJxgigA+8Yv5rbHQrSzUggYXYBhxg/3LdgbP74cfUFq6Jm4uA5MENgzbZn/FUgtgukBAgj8gRAAUFdgtoE1nPTZ9g2Q5x7L/6kpOMF4UGkHinYMEUqVIH//LC7WghIFcnQc7DvErqOgikF5bSMFB7dT60g2fZegsezGnFYHBg2cDNvDc6U/Eroj1Yx4XKevaDlKRQjXDH7z/dMFQ3MgHsIFn6dgncFXAxKDKA/WCCQT04dxIG5KUSCBzXYBx8/SD5weVIBZA4A7ZgssG8A0BTNHNa5PgkXZlXV8GRg4M4bgkjzTgyMGhgprjX/H36RgtqyNAj8qrgl0EpENxSogweB+gvRipDboE8Qji6HgvEEAAniFhwIkFKnNK6mITjAhXCc48QoHin/OYHwAk0ESMTiQvglAHsQ08i0gDc4DZHiEhgLLoNXNtiy7IMC2WDz4NXd26PgxUDN3DW455IyEiMYByTXXkH/gjsqq4ICFsgf3aDlQQwEQD846DE0Gk7KxCWnXCHBgztgTAjFgGwMz4kQsvbnbY8EfkJ86pnOFA0ZYMH4JFEGIfel7BgwNSTXVIZI3diE4QCS7XvO+A8Qv2bbvdhBW/diGycYUFfbMErGHIMB0Aa7zG3VK6V7KSGlQAvYE4fL6mIDIZnbQLY7bRwoqQp27s0Pm7KQzSFMfaAhZQ5SF6QxIxS0e+wNQv2SIqAvZGfUlA8Q2mjPA+T4nkAqH2Q93aDAKqEdlL2A07cw5OQ8UENmM7aJ2eY4UQ7Wi53W/hBQ4ibJ3BPbTbHXYRQ03aOZKx4UQ2KG13Uy62Q/N6InU3YAcJE6W1bhzW7OWB9Pd4S+nd3anQUUHKQwqHB7IwaVg7qGCQ5z66YYGCiQkrBUHH94bmdiG6AG0S13R3KbQ2HBK7U3agKY6HKQtja9QoBhK7T0G0KcAy77ODyhvInhBgPSHMPVPAXg4yFj0O74E1V0ALQqyHN7X9SrQviGHfJUAWQ6couQir7TlUmHig9OIj7cS6AHQcr72Zv4uzPAEOgg0AhQ9SApNVa57/O6FTfFogSwmKHq0GvZk2B46+Q0MHGPHY7n7NKHLwL/YPA6mGNpNBS77cxzDPbqHgw5va8wgSHP7O76bEVnQIw62B3ffnAWQzIAN5bWE6wuSEg9VA7Ig0mE9Q0o7q0X1KiQ8mGoHaaoT/diGn0UOHetYOEUsAg4pNLT7mw4MA5SUJ4JTNOF2whA6qPNKE3mVA5MHYWGCGAg76PN6H72O4EmPPH4XQhWFCHR6G+QyByCHab63Q9TDeg6Z5a/KaFX7LWHTPOn6JQ1nSCPZn7CwwNTv3c07RQlIjUdFR4J7b6F2Q7mE6HIX7KQ2TjrAuzC6AdyG0KE7axPfQY/HRqHbvJw7nbf2FiRRw5q/L2GEwr34dwiOGGaPX4jHUaGg8S45uSL2GfKW+G0gTH7GQPYapnPsipw22FrQpp7O/JiHWFN350AYMGJIA6HTPJJCdw3h61fWXxyA28GXQsZ7bKcKGtw58E/PShR8wyiGyvJUB9wj6E9HWGhv6c2FX2WK4avT3w8Q8lwR3NI76vLmHbvXuA/wheFmgy140QgaGIwvY5DUaeHewsnYrPP2bBw+SFUHLaZsqOSEcvUo7+vL2GDQgF4ZLa+Hd8F46WwxOFj0Kg77MJXZswkFiGbUIbkI6HY0vVeH8wkH4InWiiAI+yAF7dhHcQiiFQMG67w2BmHqYYA7/HEV7wI6TCIImG51g3yGoImv7Ng2iGGBHRGWoPaHMQnsFdQwGGcQ0E45/T+GzwpF60vYyE0I4v7kXehFtwb647yKaEsIp0FebfeGFbALb0TXhGqQuP6w3DSGRwzv5xELGG0wtG5NQgSFMwmME3g5SHJnP/5FbNYJKIyrYXKD+GW1J1JR/Z8CU3SMGeQ9S75g/RH+Qzv59bGuEKwisG7/HTamIPhFqQ1wHmw14ojbCoEJ7P0FciST7lvYKyjIxNAhXB8qjIwDz1XTcFWQJyEMAJO78Ql0G+EEwHdnfEHmwrfieYEK6jAiyFxEA0CfbSAEaw9XTrsGc7zAl0G9HQ0FkQ9SEmgxfATBdUHLZP0EKsaopcg+K6jIhPDJQsyGuBdZFglYp5nAoHijIhm41g8gElQk0HD5AWF+AtyGjIop4sA1Ia2Q7WhqA9UEjMLGFlERGCenCtAiHYiFgMJJHWIqLbrI9OhLQoyx3gaeFjI3C7IXTaH9VW34XXVeElYajzeI+lAgo1ZFQnZF5HJMLbUvEv6vIuRh2vai64vB5FORVq5GWGJHXIr8gXI+JFsXQVEuXNg7R/a5EjLST6FTAS4PIl97qXES5fI0Giyo3Lakw39BURJnZyXZZGgosf4VIpFH1OC34aXECGQo+FERbPS6jIvDhGXFm5yQm0SbXHf5WXXFGDcKyC4XIzarw+46OMRl7vvE0HCfbaFonEYpTQvc4kogQzCCDWGyHA4EfwdAp+gp1LKnO445QhNEmA+gG9HV2Ymg7/AwHJV5Xw82GmXMUwTHctB+g+FjO5Y16wKEtGbET1GzHc54ugpqF2vJUAo0P0E35QqR3PFaEug2Gjf4Z55JfE0EenKBjvPegzNouFIKw43gpojtFLIosECGQF51ozeEgvc7YWQgIje4SF5UfLNFNQ7u4Tgku64oxNG1fYA7CHVNEk8Xz4qkVz6OFbNGE/Tf4Bo/NH8BHWD87PmQAwtMwdYJu7DDUGH5oqtHoAnu53gEtHJIDl7W7fMCkwltFN3HhQYQ82GdoxgAYw9rrAYoSisI/nZ4w1eHDHPnz3QkmHNoidF3fODxc0fNHS/C+6nOTaGLomu6HfEuglo2Ti0fDSwE1StHuwN9HUdEMALonCBRVQWHAnVNF/IHb7e+Y0rmwk15NfGWEWQmNGQ/RfZKw+BHbotg523euEsYtNFFfcWHTw2CHoXUA7NqUmGmXb35f7RzIlo+pyTokc7e+UjHVonmGUYz9GfGHb4uw877b8TWw/I+h523TaGw0P46gHL1CuPRwoenJlyBwtypDokLC1wpvB/o5DFRwhlAaw62AwBeOFdfbDGK/bu4GATmg+oo7BkApeg1DOtGvotQ753aCwq5cB6g/KO4ug4T4fYPR6nHJyF0rFNBRwhvLTwp1IJEVA4WBDogtwvjGOHM+FxY4THOPYQTYYz2iE/ckhfoktFXo/jFRgFj7QWXAzqvSnTunVTFvog2BTQpqHfohA4J2OoF6Y/qqOHOW4FIiDHSYeE5OHPyJDowg6HwnzLGY4dGpnGZ7a/SzHOY/37+WEtH6DA0TG/EuhOQxdGkQ434uWaTGEYsvZJHTTCtYsI7NParFLwW+EdPejF4UAo6sTVNEe6AI7lHBNHw2XDHxYcZ5dIljGWccsEpIwNHFY+xFfNOtHlYtF4uI6rGjsc0HbbBdGNYm66f5cA76pMjFeo40H5or9HrYyzYhI4DFr5G652g3tGxbei7Og7HGTYuP4eguzHwY5JE2I9HFCgvi5d/VbE1Q+i6eo4xE4Y2nHD/AjGBbfG6ycH1FhY8pFoKWyH3HGjFx/WpGWooTEMYm1EZiTaGsYh1ElgwNFo2F1GnHeBFwYhWFRQ2DFQTSKGmYeaEdoyEKenJ15TQhhoBjND4J4YzF16O04q3YzGXKK/4EfWCFOQm0RLwEj7LoP0GdYROxzXTjACo82H7vUBBo7VqHbgFUhgouW5d9Z3HfLaEHO3aKEKWHEzcfJd624nCbXo9miTQ23HnQUG4qDdUrNomA5T3YL7to3tEm4x9EbQ5tGAefSGR43aHNoyCBbRKXZHQrXHkNLjFwsPRHY45yQa7C1B6g3FEa8UK59I1eHg3fSFTgs44ugsLau7Ty6TItvGkYOcGsQ2yEbKUlaogjI4ugnl5JorEEmgm2BKALZEiQkfE1Q0DFng1K4WQ08hDIgs5TAifGfYXcFjsJSHmw+KFqYik7kQifGwoUmzaQ374T4yjHjQiEKGQv0H2YeKG7ncyHX4pI6ATbq7AokfG+MWr7FQ+rGD3RsEwov/i2428SKo97CIov/Fq6T07JIfFi24sUjLXPGHwI3fFvohXF+giw7H3dmimYPQ5O1BszHHBvDaNZ9FO1BN47YzAk3AKaFvECEgunVeiEE2vYKwj/FOQ/ZCKoa3EAI53bvIT84SohQCO4yvbvIEghe44Yay7NgkWKDO6dQ2fZsEz2CRQ/qFE8BglsYOKHDQ4w7vIBOwo4wyQN5QgnJmJglzQqgk0SefHLQjogughxgk433YZ4jQmKYnaHGtBAmIoGQl02WWHMEqnRS7HPKrwuFDCCKg4FmVmE67AQlH2BDF7o+gk00VPgvQ/gLBbIPTVzT6GCcJE7vIZdCVw3yQfIQA6P2WRTAwiK5eE5Vz14kO46EgvjdwR/GpnFEqP/VwmetJUCm7QDH+EkUA2EsDGm/buAN5LSEc7GDFREgZRj47PaIY1InEUW35DUaBIlEpDqYY+sSSExUCagZvb4Y1IkDKA2FtwHBExuFywxEoh4Ow1wmhXQDy0Y3WEiE/0E1QsWFikKIl4QONw17aWZ4AtglqGU3bRiPHYOEkjxOEqb4JYaYk1HXT5eiMUhZEzBi1I4/bvtbnYBE0HhyYxv7xE5yHhA5TFO4nonu3f3Gv7AYlXEjCxhbY/blYUIk0xRu7/7IzElEjEHFIub5q6T4mYo1442Y4T5/E1k78YxzElEqokEHCljAkvc7JwrzElE1iYA/fzElEhbivYww4hYl4kPEnx753AImk0ZOGxYq4n81d2ClwpLHbE+VZpY8xzTE1gx4IHdo5Y5WE6bRwmm4in4LYhiy9HGQ44nJolX7bUHdY1fCnEsVB0ASuF0cC5TTE7hSCPajGQQ7uB4kyeGsEyyH6MJn41QhUlpE4O7xYQbFCkxGCC4ZJ7jY1IkFEmQ4t7KGH5EyEkFYpo4wkhDCDPFbGpEpDqAolgwE4eS4JEn0BhHOeAgULUkdE07E7HfgnREx4lLHZ3LTEuAw6XE1BXYwYmzgEhGyYO7GhkyrzVHIZ6fExuAR46Hi1HD7ExuadgbEhZ6+o7Ylck2V6ZosYl8kuJFroD3QHE5dBIEtdB7PQYn0gJ1Llo/GFjE3om+k0Uj+k1ImikBtGbHYEnRnAzHSae55/E/mp+vF55/E0LZhHD57Akr7F+vX56VEy0kAvTGp1E6XY3XUF4oklojKIzSzI7HokDKEl4KI7sBNE2snKI71EBkvqbmgpxHbEwmjmgnF4KkvCAGgc0GEvOkk+ZZRFkvfkBrE1MlskuVGkknYksXBbYnkxLDk/T86+cXMmBE9P69g8snhEplHgHWUnkkrcmI4nomJEsi6WgyomOZTHE7yLskh/TzYhYPslKYCLZE4/Ummk0nGEol4mwkiLZU4m0nS7Pv4Xgp0ntkxFCxg9omq4Yx5Jgkolyk/VEmoncnDEvnENbA8kTEvMEi4qkmzE1pES43MknTdS47/Mz5jIezDro7cmuEr8jCqf1FZExfBCUf47HkqInzTfK58vD7ayUz1r5kssDxokSlk2YVHt7DMkiU6wQVPVZ6yUrrBtAlgybPCSlCHMI63iG2HJJV/inY2RSyUwSlcIs7GuEqpC+SK55NopykyleE6KY9QlXE2lJnk7tGt4nynzEeiGevQdFOUxDifAn57aUnymfUJgmvHSclOUjMSnAtqrzoqImMWTFHLopcljIPigKwjdHJksZAaUk5HLA+5FjE3ZHTnKcFdQgHIAYFiH2Y7/5jIWjhP4vy4VkiSndgVFpcQhUnjIAk5f/BUlVIZUAGAns6pUnVQ1PFK5q0AalQ3a8FCkq2CVkXvGzvVKnhU2YHn7YqkxufoTBXT8EcklERwGLkH17dMqGLPwF+Q2SlYUCj5mZIUkdU7D7m42SnOrZ86wonSldfNCGqUiSkZBAb5e4MAl5EwsYHPfIGEQ/imFjNTylHeAk6U4/hMfFXFbU6TTzTeM6a486lwGUGl642Sk5Y6gH5QkSn2Uy84QosYlVIcSS0Epomtg2TH+nTjBIHLFJ5At3HR7MKmk0Yz6dQ2anwsDO7CEpakxU5qGyyb0kkWdNI07Zq5cEmbxyU93alEY6l8UIIkwKWqkmoRThIwyGFNEr8gwKfQmhwWSnbbQ6HiXdqmWoISG/cc6HqU4BzNQ66E14vf75U76nOEwTExuUqnB7I9FM0yxTkNXwlow8GmEZP6EhE6Gm00Xz5PoiSkI02Ikfopyke6AvE3o39EDUwCBnozImjUprEe4qLGzUqam4wpej+7OsxzUtWkTUqmlzExOxZEumk7fLDGpU0AStEtamBMaG6v7cLoC0q2n9EjTEiUi6kjE46kjLGn7sKKYk6UpZEX3eYnekrabD5ZYk8YtYk42RfBwPLYl/UupDaw/YkGUoRrHEsdFXEvTCqEjB5z402k5ow77IGdqnJ0p4mp0nynaku0kHxD4lO04PGgHfnD1PXGlEnX2GJYL2mwQsEmWUylxk0qunq0hiorUng6uY1KkZifBGg/ZEm20k6DyPdv5v/ESkOMbOnBY5jEa0vunUHAknRQJYi7007AkkkqmnSbPGZ0P+Ki0rWjsPWjjYE/KlwY7LE8nZkklUgqlmkr8FjIXSklYk64iUifZ4EsrhVYtOmvsUOF1YoGl4/Vqm5wlrHw03mnykqOmkeDx4qkp2nYqAbH1nIOljUnuFxECanzEEskdYLWDo0gOntw80nuU/6FWkm5Tb0uvTZHTbFR0skC3wvbH7UiKCek47EYM51RNPWtEt0sDoukkMkt0kZbrAiMlFHDWkZBQn6y+HchKU5YSwIsoh5Ur6mV0zClUw2Rn/UpsEA4lunQM164dguqkIM9xFF0lqlGU46A+IgSmYMtlG0vdMo4MyCkWYrFLO0tF5Y45GkDZMvYMXL2l8mMG637UmlggzRmfE5alME/i5M08OmEU7qnR0vnFM40+kRQAvZUUgRnd3NMEiM8bZZg0Wk3U4XF24j+n6DXCltIuWkl0uP58UtYnGGAJn74xal1mDl6jg6iEVUhuy8QTvHc0gbIb1RqlsQq4kWKW+JtUqIk24YmxrI1pknke2n9AmfGtMpjEsQg5GdM6wkGA2SGuEupCwFGd5XI1pnIg7t4LU/pExudzEEFJ6kvIqZn0wua7+wfL7pDVgQAkwUj34qZmNo06kv41pk4CEa6OQ1KmdMXc5XUnymAGH+5e4dCFh0sjFFQ56lA0hLAzHf04VoIiHK05emlM977V0+5l9YETH10pyla7XYlek0YlLUhM5P3JDqXEsYkWKUODMwnumdMi5n2wgemIslvaEgd4l0gMZmr4Zh6T0oGnuwgnCz0qemyEQkQEHN4ifEsupb/ZfhAsxFl8yYx7hUxgCdMlXDoYbA66ANanUMV9qMHAuBZEtr7S06g708NFmsCAg7ZZa5m8gQuFP0panEUQR41HevCpU8kklkvZG0ksKnoZdh5Mkz6klMiKkEorRkVMkFm6M2+mKoHKkg4pyn98BkmWbDP5TMuPwP0vC40s9Fm2Mv2m2YBxnBIqClDM8S6wUmi5TM8ZkA3UVHzMxGieM8G4CshZk+grCmMssGRR/RG5NEpqgRk7JEZbKZn7MxnEY/TpknM8pGlIqZmOsorZc4yVmmQ2zR1I+5l+pGC5NI+5nmHNf55MwKnLCGC5FMta7pDUNl3I5ZkbISTAv/adgjI1wkHPfgKd4lj4VIShGrklcFM0w1ZLfRZHD4q4nIYDRk6AhUkmUdy7T4rC5ugNmhmA70nHIn2Gr4nExREgAEGAhwFrsr8idUoqmNsoBjCpE/FZEjEHy/S/GfI9tlIiYekJ4P5Gjsq6JJ48gFnMsYljszSmUEqIn0TO05IQ51mewIIFPMoAnts+yA5xJ6loozpmmYNkn8UbzRrE2lliPaEl/s5tl10u7aPsi1BQYjB7boT4lKAWumSY6Xavs6zZ2vZTFfkmNxPs5mHPEx9llEUI64s875zsvNnXMUMBrs3+yFE5LBeoclnrsomG38VAlyTGxkb7BllcTGZS0fFllNEjEF4/QuFcsydmlENkl+YnyGPs1XClnOeG8gV9lFXUOESs9tk3I6Vn2/P9ljiUOE1HVmF/s1iE0kukGIs0zAyEhQ6/SCDn1svVmoczWxCQXRk/0mIBj2LlFq0JolKAXJg9g2dn37I+heo8I6yc1WlOs19kHUylFo4rjnzsiv4RImjn98XHH+ssYnrs1CkJI1wl0OQRmmcmjkHs9JHKo8LmhXAAl/iHJHnsmfIsXbVGvs29nxMgm4ec8dkC4OimKc2mhpMv9kWHTa62orTkAc4sHNnKZkgczxmuoz6kxcndlLM51l24mL7OXNtlXE4XbLg+cFd4nrmkKVrmzI6LlsMXy7DsoGkC3UpldUqImJ3ZFAzs51nCqKq4L40AFXEm9B1Pa8GfEm375PWZnb4mNy3AbpkNsxbke0WF4bAnSGuEv3JGUZ85X4i7l8QX8EY/frBjEo84kIiCEfwilAc/GCFI0riY+YjW4fstdnvgnAH2QpmmNcUuCgEoDnRc3kDv47FHNc7dmCPaDk9ctOTMPcS5Hsu8CpnL0nkcrBREMuTF8c5MxEw3DmTcj7kYsjd5N5Gkpkcrbn72A5kPAajkXc7OBIcr0Q8UJonbcpeHUs2bmNuAg7w8p7knc/jHwsVlkXc3eHSPITmzcuIj8Y9v5AY/bmVeRY4X0xnmE83OG30+K53gZTlCkoPGWst+machHniguEmNuLdn6MCx48nJWkskzCDsc2sHhsriaI8yzko8wHiUouzlrsobnSIw5LOcvYYuUwClM0qbm6s/xGLcpUDqk1HHusznnO0qi4/XWblY7XYkMXRbnBUdT6SosXkUoNnlhs/VmjiCUHNEpLn7cuCjrHFTTo3IXmlgGpE43C7ke6Kg4Go2bky87NnVbcLk/csrkI8leFR/Krnq80Hm5Mlmja87RoRbJrlrEg7lQYscGzcsOCPU8qnekiw5W6epkKk29Zn2BEEtMsYlEnZ/YdM1wkwKQ5I9M4fm3sxZn9U53Y0UCkCo2EAEXghfkJnFiEanbnYbpNsy7c3TlKuRfnjs1vnz849QQcUAm5vPvk2/V+l/gqImCpFPmHM/ezX8vpmnMoUkT8ulkvs8fkYWfMkSPX/EXc08hu8wAnic/bm3xImEwHfqqs814E6gj6lN86PmBMtvn84XHEOIq4nd8sFGfkoGn984Kk2Ma1mICknjmbQCmfEl/lUXYSmICmfmOMwA4L8tmg6Itxl7830BXRP1lIUo/nvtDuKRc3o7BbDdKecuLn0Cojj5k0JnX8i/meMunF98hfi380ikBU4fmP89Nl1Pa/nyROlnJM4fkf8za784ybm/82VElsp7lACynEVsp7kUUoVmdIsz5H8eSLUvQgVE8PpRu3Qh5tVJl4sCmmKnsNF58IyvbQxbdA6IoxG2Cv2RdEsxF/xevbBdSakSvZBEWCuFICKNBHeUowVrw9ZZYI5V4+C/fB3s1gyEIo/n3waJyzHMhHRCgMYjohSwB3YCDfLNulroK14WCmZTIRRhGKYYw7AQbCj8IuPAFPQIWqUieE9HL17uCoIYWcpBH4JLIWjAFPDCIrRnAQYGAM3OdHZqAvipChsHSIiMl0EzoXHQcknSI1N63kta4eChillM5ZnQxfpRUQ1tldQ9ZQn/XvlhC9lkzIpqlZClPIGAxrjl40oWJCmYXf/VIUtbWfnbIyCa3xFvnEgkanRCwoXjUrIVGDBZGKQ3fnUkBLAN4+oXHI4850OBbEtC1oXvskdmlChPaToq9kC4+Cbkks97dfLIU7CxGksfYwW/2Y85/co/ke6EGHeQsXl2C+M7vMnwVB7WPFEsMKE67MYW2/UHnE2HwX72HFlS7ffBA3eYWPClKHVw2EX74EM4JwtYVvIkgniXUEX6C8EVVC4yj8fYYYoleoWeo+M7SQ/IUMiMgEE4AwnRCowbN/OW4M3a4Vki3m5is54WNCiwmA8LIWX6Qn63xRVnRCm3CKihyAfwomCOMTe5A8BFmQTMEVx3QXaUiqEWi7TH7QxHI7GfTT6y7JEXk7fT6oituDGfYu68iiWDjCvqEXbLEXTQl0VAMLL6wigkVJEuu6z7UkWzQm3ZLC84mefa1z9CmIVtg7Qn+fPUVMig0UxwiMX+PUe5WIce6lC10m38yTk3uC4U5SZz7XQq0Vxo+WG4wjVniimoXZ7b0URihoUWMvL75ilZFdYk+4lfRMVciTDF17LIVPnaWGIAmsX6ioh4tffoX6iHl4VfT+74igW49fTTBOi7FR/8qEppXYLrTVZYn2Xd0XOi236IHUgU0xaYXaw3uGwikcJFfFb69i8IU4PDb4BighixCw77mOZcVciBPad7F+4qig4VUPc74FC2nZXfE3kFCnMbawzLDXCpXbsPZ76b86oWkHD74Vil4VRwzYin40oWtCuH6A/LIW/C6R6Yo1sWDClR7Q/RkXni3OHzwwIVfFU06FwrR5Di0fIIHMuH4i+wVRw0x52i8LrZY4n44ovf7Yi+x6FY3sW+ikrF1A0kXD0pd6ylZCUOMfMmjw/3bciF+mTwk7bwS2uF5wlUUsw5UkrwzkV18AbF4Mi4VuSO/a7wr8WqUjh5TY1AkPC0sUSHL8EFC/8X+/fX7yioXRcIk34si6tLGPbWAQigYU98oRkqciMVdio55UIxiXcI/+FOi0jxEw7357CmmKoS/36CNJwXZZA2CwI+466Cj0W2/R8nISqiX/Y/O6ki9+4oCpYUtU0xm0i99qDg8A56ChCX5/ZF77C3Y5usizF3inIWBcyW7HC58U1/Xxhvi8oW+M5gVCiiUXG85oViCZSXxbIMHRCkCV8XfgXgShsEVSmJkRigTL0AhJnGSuMWF8jUWebc86l8nyXmizJn1Pa0WcUvTjIStEX0XGtmkS78U8Pdv4WC//CXoejnri/oVb8RXTLfH6gTS6iQ7ffcUTSjIZ7ik8UTSidQlk5+7v7I/mBMeKXLfb/aBCpxHkYgA5OCq7nSzF8Xn4CwU7EsFEcPG0S3SuM5Qk3h7Likiw64ng6C0N6VukgAniPEkUHLQ7nYHNe75ipI6iw3OEYgqoWp8AoKIShH77SuIgjwouETS+1i1fIKmmi9vbjuUOG8HGsUZg/jGWPEiU6bOSUwXH7GBCyaVG/UlF6MkmVciXvYp/JaUyg0KX7S9aURS5cVQykskqIiaWKAQ6Xe8xKUoiEHa2goLlH8y6VJUxCn/Su6UwXYNlPSlyiyo4mVKud6WLHfi4jQk6VukrEmXwNPn7SzC7aC7Ln7S+s720orkZs2aXbS3PnFc2aVxEB+kWoyGUJ2HAW03LJn7SuxAI3DQWQTN4jB84aUEy6HiSy+6EvbC6Wy+IMka8Dgi3Sh4Aq85u63rW6XLiN9G+SY2a3SgM7p4kbYWC2CGeigXYJiwIUgkHWUP8SL4xy2GgP0zMX3C7chmgBWEN5OPAxy7OKzQ1PasSon7RSqz7b3I/lNUfnBzExFROCwbjLc+sV4cquqfndr6sHGOVs0U7k8KJ+ExyzTLVEo74Cy4iav0hm4PkW6UQRHB6j7JE4osTLCEi5LDAPC6VcBYPZL7fMWZiOARli7e7uileUoy38UnSr2U7fVfAXomWXLCSnmosKGEosFyG1fXB4iykTlWw8xz5i2OV9ynsWJy+qW77M77Liv3Fskly5fZNOXWE66VZw4Hqr3QQ7PfSeWlyhzGvStOUwMQQ6DcS+mlYQWiaUv6UlytTyFc07DAy9uWL0KUkQynuWeC0J6wy/oVOHadhoSlH4CypDpLw/R5VCq4LRYquFGSk6V9oVFhESlSwby56Ux8t6W7y83l+y/ZhUXKlHBy8a7g4zC4lyzGrn4CKV3y3uU6IwwXA9Z+UkCtOUhEr1l3E0rA7kaJE97AuWwwINlRc/oVHYMuUt/R8XbkCBW4UjJExywWhkAtLkJs1RVWeNVFZ81RXyYeSU5YPWWJy4RWc4ovkyyjwSmyhQWjyrQZWyurm4K7PDhfPqXAK78Sy+BvmWXDyVqK+XHUdNN6Vy5CLk/eKEsoCwU35TMRofUMbRKwiiPM/Al0caJVHI2GlOCjXCWKt/n9ClXCsnDXFglL8WCGE2FY0m0RVC5yR4cNHZcsiwWCNSDgdQ1oUlyncBbNWwkhK4BUYg4x4mAuFLRKtW5MEpUXxPTMAQK2wkOQGiXNfFxRSfRfDRKwkTm0kL6BC/RgHMlT5hK7H6HQ6wQxy97aWyvT6krAuXdkKvEmAguXNS10W1kd0VBK9h7by4HrhKnB77y4BUxK4emNxCfYJKlXCmChUEKKo/mfkbRHN7W+UTK/KXNfS8U5K+s7k/SDjUPfoVFKi+XnS6pW7QpB6ZYBpXBgFXkPS0JWAq6jEqsk5XuCLWhwkr6VdK8BiCckbjRK4A5/8wg5q8mZVpC8VkYK55WTK7BUTPTMDsgamUGXQhWqK/Qark+VoY/KoXWwCkAJk3H5UK/+WR0Ug6WPEYUjSo5VMKlZXmE+bZko6JWmnYemfkvpVeie5XKI+3klyl5XoC264fKyxVsy55W/K5xF+cpFX+3cJHeswFVgq2gX/SmpUq8hv6tK+FWbXaWVIqiK46KxPmZgU97hAwxWXK7FXyCsxX4qlrayXfLnEqz5UyC4SbsgWnFMUhZUPbbqXAKplX5vGvnuKxOVPZTSmdIt1EjSxpXQyiYUNKvWmFvOhGBCu3G0Kss6MQwFVVy3vEVhENVKueK7MFMfmAqpvAJHGblH8o87Dco4XtAWTAC3ZflOC9NTZvY4gzKL8X2YcrA78g8WUmObaH8/oV+5SQGrUmtUrIrJUNkztV8+HAHAQspUcy3YkQQwpWFqz7l6ShvKBqW5nf8wFU4TY87PM6pWVjSuEgC035cNeYgQCzEWjC9SBNKs0nHo1QIwM2Q4+8nNURmMR6ePI/ka8e5UqPQDj5isAlW1DiWySh/huymGVkqx7zji/iWpipVwc0YibCS3rAWC9NS38pw5W1IDVLEGeXuHSQ4lqtuC2/bJ4lqgQDdqlSXOKIDXJ+YemwFZ8hAa4Jr8IgW6wqpNUyydAV9kPp7uCKdXGvI87VK1gSnchN7u/a9Uj1O162SpwWzxNU6OSqBFwqwIFzYsP6Qqg9V0M2Z57q6NUlkgRGrqmBm9HdBHXq1FgPK2GBLYCjX3KrhE76BpWOKzymDTXkWUHWr6UI8jUlqixW0IuYUJxKtU9HQCUlC39XCfcn6nHaM7ga3/YDohlDgarBW1Cn44VqweVNC5cU8vDilfHG2Alyxf6WKeN59C/DUtbAwWhDVpWkarznXqxTjh8jREBCnNU4TD8k2C1dXMq6RGOC6pUSwWlHmInXZcsMFJDCsClcsaFAha9F5InSawbSXMEi4GSnO7SazBEqi4XkorUCGebC4XG8nBbYrVWIlgyjk0bpiCeypcI/Snla//BPw3NFbPN1wV0unmsGYtFtanGwNo4541a4GmlZIRkDqonhcsMW60fRtHnfLliUPPTWdk8rVSIrxUnHHtGTambxyMS46DkkbVpUulmjo6FlOUeG6GI6dGNajqlovWcltaod4yEgE5LkrliAeX0m5Usz61anbEdqjbUzKQWJdcrqFcsZlXqkiZHf/DLVC4QfnZqrlhbTdtVNvLYXda1LVT87rVi3KTYDMrC7zaismFUpU4Xgo7XC7K4XLa+8SKAu4Wz7JygsgMc5vat1z9WFa49qkbUdU+M4Ta2HVRgSnV7UtrWAeB+kTq8nXQ67q5fcjLWetS6kLq97U3oOjkdyO6kjam0oD3DdX17YrWVq96m7qvf4vaoQkQfbnXNam7YJQtrUxa3W6pQtrVk2BMmlEb37k6+epnvebDGHFLWDa5kXk6uAy/g3VF66lggEsOqHAlXbWhXdsktQgmmNa/J74iOpV1A/HWA8Yz4U0o7UE1SKE008nWq8ZqEDcD+FTatWjaitmnk6rjraiqirM6g3XW0qGHs6mjZ+3XPHlalyYJkumzVkt1x9XVbUy0yHWi68lxV48ZXJaqdEwM3dHq03LVy6jnba08nW/apu5fQ8nVk2IMX/QwA6g6niizQi2lR6sbXaEm2lnauHVIwuGHc7JHW0pDIkBEHLUMpDHXl6z2lY6l8K+fYolY6t3WB063Ve6kOm1EtrWCUtg6X6W5VXamnUx0yvb3awL7rfROlt6hCkUYjd7s6ly4Z0gXU863fZMYxvVWmdclzE1Gx46irVBqjnYrEwBnp6hfhNwzjml6z7VzfMFlna7dDHyk4m16wDyr6+Fl96+VgEqdb6ostrUs6lOnH6p341AyTGj0trXnnIr6T0s3Vj0UflmYoEm7avnwIUljk2w13X6iVelgGknW388KkEGnmnVyxg770rvXivI+nok+nVCkUJ44kjbVU1PA0Kcs7UpESdEGAGVm5aoXSCHBVki6q0xHYGknYE0XXjuf+lC6Z7WF66o4US2XXf6pdClYyvWF5Jn6CkoA13ssUksfJvVCStBkgi6A3R6wJ7b6p343hbrEiSs7UpbL36ak63Wj6hX5kMnA2T6qbHUMnA2z6njULYz3Wk65bHMM5fWEIDSXsMjfX8k3bFuksPWBfS451PR7lQ6gw1HPYRmsGr1CWKhN65HJPU3oAe7SMvp7Fam35e/WMkC6zYXeHd7HSG144wM7yXp69pxyy18nKG2ihIXDsGA6u9l0Xb7XgGnQ2GbHxH669vXu8o3WASu3l+c/vV8gxzZwU5bUfILMC6q+w3WYwnF+MmfVEGmAW9GhfWJc2XZcsFfURMo3Wb66JlkUs7UM6l1Vs4g/WGynNmq6jnUdSoo2AGFi4qCt/VmXO2VcUt/Vi6/xWboyXXM0sY3xYOQ3E6pTD0ankm7a+za1YtQ3LaxDiPUx9Sl7XbWDNbg3Skkg0lTcVn53Gjg5Q7d52YBsEja6zas6QhmsnCE2CQL340OB/XUMfrGq/HzLTG2zB/8ObG3Gy4I3nPX7GWcrU24JJ4lPTC4Qm4EpdG+0kKvXbXAnIMlJHFoi7agE01oqnVOUJehEw+I3xPJyicSZOUpG6/Ws6CimPYxRlY61egcapMnSGxDgq5Yg0QmypDoCj07wct1zp3co2SYlDkQmognaYzDnla1k7tM7ulypNU1sgdb5Ect1yPLegEyYJA2NahIzNqiel23IQ3VoTMFYG5I5qmzC4NU6A6qVEbU5GZo30skvU6Yd2EuYzYhm6qPYPKwhBEzE012YSlVicsXn5CYaJrK4Vkyc7U11am+lGGl7aLissJgGpxxYcRLGlSxrWkrMJE8HLXn4m6zZMEwzn68jbUumhCnF6sA2eQh00e49rEjas8kdajnbHtKs1+sXz6N2M3WvsRLARE5s1ZgOll7DTvUbahMy3jH9EpExrVQ+SsiD6lGGDmrnal419j1mEbVa7SfY+0vU7TmviAW/Es3Tm4/iU8ymHX6gW4wGCr6NcIw23GJglAoTC5om5Yx7izmHla3rlkPPU38ZPU6YYoWFVm+SjMPb3wA64XKDNO/U2/Z03/C0umJWaQ0dK6s67s/3YnsTSxLQzvnTmkDGLC8rUHc04ErgkHXkWMaj5qjbUWHMU3j4+C0vEDvk9vQZnwW6Zn7IkkEja/fAJYldlDYunrywgcH2AkJU4W9/VPC8rWu7LiRk6yi3yRChVX8yi1iRSjn/CoQ0jcEyiXnSCEwEEkheQ1nVaGmgCDNAAlf8oG4AWncgIogAUnsY4Aa3FEXgWxm6Z6jEXObAvU/m5qEe6hOI1HeXUUqEC0WIOJUcGjbW3Adyi64zXXgWnKS86o4C66nC3cWua5XMxi0uUfJU24yi0E1Sa7Y06/WIESjl26sA2qMoVne4ow2CpaXWI697AvbZO4+62i1G82QmIcHC1zRW35GfTi17eJDpTK2jjmWjE3rQ7s1uuKxBvEhPWCiwc276n6lF4hc2MVCwmy0wc0iKEsl2Em6FrXCS1bTWaEPQsA0c0NS3l616GaW6TD60g+Unsc+xCy4ImpGmC1kAjK6REyi0WWpK2x60y3qKfs3ww+y0JEWaGu0yi25K8s2Tm034wEIi1JE6fWNany1z6ya0BWxfVoYunp0Wu76R0xi3UC5mFtEpa0gmor5dEs3UIWni2wGh/VWIYY5n68C0nUOlmUY3OmFWhoWvmvAESW11Kfm1YllWjUAVW8U23W9OJo80TENW52GAG8C1PZJTGgG6c1/eUvG3E7y19W9TFwG+FDoio014s0a21K802hgnC3zyVfXmY5y3YqsR6qRXG0xmgTHuWg82/S+Ek4W+SLhA/01sm/h43YvllvEHC2O5dskX05y1w2ww3TmxpVU2xM3TmwWj0AyOjv0mS3uXbnnpYhc3yPLVmKWxc3kS+hmZW/60QMmm3CqRq0CkuBmDm1q1mHL41GWr14qPdBlLWtm2U6IE2DWj43QwMw0YWsa3Qmgi0wEKa3wmuw2UW+a2OGga3LW1w3eW0m3iSxMJomifkoojbH84cK3UCjSXcMyi0gmhylekhK2IWs56Mm/i08UCp45HeW2AS8s1cm3K0hSxyX8mwq15I6Z65GiW0/WyKnN03S2AWt+Gtawc2w0MgGwwPNEpW8+wmWvrUUGiLCZm2p62U3q2JW8bXfCunovEGQmza5y0FbNtFhai20a8fylu2+WGLHK47gHOa0xmg7Uk2ta0vHAAHdEvEJGhFzU9xZC28FDKkP6vlzpCp7W12kO0tG0G1087LU822nnSU0NHx2gl5Ro0W09wVwXEndO2EUPlV/W2q2CqimUpW0C3tgvDktWlIK/k2o0RYWC24C4O3nWte1LWlC0cKjo36wU20pShe2W2gY022ssLqXNClLW8i3jGpa3O2i1Vu2ra1zG3a16BGMEiCunpHW8QUJyunq62jsr2Klq1wpYS4+qzK2iW7qVm6l5ByWhLL9SlK2yWoaUy4nXbezRCgjABHHIvb2bWbSDU2MPznezZIkUC/mUF8b2bIofj4h84LbezEbh2vQ1WCOgGUYEjRVaM3h3uKC1UKymQip8Jw7xspE7MOikDN/UikEW72Yw4xMGuqnh1MsfqrGozY26OyRmTos2ViOlZFc/Yh1mOqILi4ih2xxEbal4nQXO7Ox2rmc+1GO7r70A+P6V7WOJgyQn5BSpx1BDSlGYConjezP8SxUmHEFmmQh3wJNrsff3agZBxhxQwGliOoBQm6lXW6O50W63KGn+O7UkAA+kVvA4J1rwyhGG6/x0xCsW5o0sx3TI7kVDvQA6xxdNL8fNy1WOx3K8E4NxWOlx1S7Cmk1O31Eh43fmxxAMbKfAPWy7WOLgId2lRW7nagufqwt6yPVZOmqG+krs1QwyKoPwJj7/skWlZOyfblm1PVeOxtI4mM6GQ6+DI8nPPWlWvf6gZBsxN3Kq1JO/5h+i+q1ZO737k/c9HKOj0VBE29HVO7Imeovmkgwu50EqQp0x64w6DO5w7DW0Z3HQU94AYofVmOk6hkmj2ngYmQjAMBelFE32ktOv/nLm4p0uUG4moYu51ni8s1r6uZ0EMI4l4YhbGgudIInmkjFTOk7ZWwvU2RVfN44PT2DQs6Yy+MBWEPWy+mgZV+Kr6wulnO+GUfW1/VHO6J1qwo/FnO+J110xIRJO734fynfAbOiWDJvDDl1+JJ3OSVfXWwkV3TOkl2YsyF3nQCcU6Y1F3HAMFEFgcA41OjsS+wwjINO0y42Y145wuqEmwFevYdOnKEuY6yb5OsZHu0nw31PWOJKqQuE5Q750hwI8Vzw48T5Oj52+k+H4TPMl2ggZH66i6l1iundrYSrJ1tIL3mUKgZ0dpA+EIHPGVnO451jS2KC0OxtLxuuhnHouJ1tCnuHsOgwKhHAeGcSrJ1twFVm+PSV3BXKUlBPJJ1yu0lXOumIXx0o20WHcp3YQ7w7dDKt3ppK21ga4p33HegFUVNN3XuVp03G6DVGOpF0u2wYCoul+h+vE36xOrF00Ekp6DqWfZjO3o41ohMzlu4l1kagO6+u8s3Ua1XFpOvrDu0737F2hl0Zw/35k3Fl314WJ6nHcI0cutkkPkCvBmfC92HYyV6zuxtK8ulZ5yvAV0hgy47YI513OiyuGRCjB3TGGtD5kvH45ypd2fO6u3qaox3nQVh3LSrqGxxBh3hul4h5CkF2keIoWuvPV1l2yoVGu9o7eCxF2dOse2l4f51niv/m5WXE7FO8BDJymREbvPF1btFN6dsB92eu0ClMOv2S07C7XUXJJ19YawWqSEV1tIYx5c7OlLHuulmqU+8Bxuzl0LPYn7sunt26sonV2O3C3DI6D1NazCUMQ7/6xxYE7A6u51zRFYLtAzmhiOrfgMOmHXMO351Hgid2O3Ke7DUtK68OsEybcrT3COkK6bs/x3pBDlmSenmkOu55Hnc3R0KO4i0GQs9mueyrG0669n5OhLZwoByG38SN3aet9HZKq10KDP4Uwiox217EslsbAAV2O1FpzXaS1uOviBYoyAVrXIR2OZealMg2z3nnI34t4yN2GBC3UTIlj7eoXAyqE/tliO4kiLnJt4N27aYpuidlVekQKZqo4V2EQJRdGkz0Pu3NzH4/C1PO1gSASnfnOuxBX+4hz024P8SHssR2wQtBQfI/L7x4e1F343z0yEUDXoC17mFeg56gcqy26Or7jYQ+dVA3b1Ck7Ey1xe2x1j4DK5SW8HmuevGzhusDk7IJN12eiR2FGoR1sbTa57XO51Fe9EViq510rype3Sqqr1BmoYXuc/x3em4T2f2/J25MFugJSvr3te1xncO/J3de7QWA3Cd39eomGiO/x3Deli7SyuwjAMU2XRsyb32VEhG2qpr3zexY0aOpdA+gPLnWKpb3rel1WGO0H0KsEx3OKwH0He/Y103Sz2ne4NWqey72NcgJVJutH0UW3R3WbGzjDIlB3b6HN1ds012lykb1NA473yQdLZD48X1XK3T08gcYoLcsR0MNWvYLs1X1C6IC31q1dn+O8a50rQb2q+3CEtsnL26O5DDRiCb16+h8gX4nd6ee/J0b2CxlXs891eiTUCG4oL2q+kVVFO/n01oHYFRe2H3oOQS1A8yb2LQ1kHne2H1JYndU3ejL1pmZd1QO8P0yyTxkveyb035FSmcK1H2BkqVW8Kyb0RekRUA+s32e+wLVm+wy6qqs9VA2UuzmggPl6+rX3qXBH1G+vBSyo8WV6+432uO+31xubQU4+q32+UpR2q+//AWM9R3/OsA7lmvPl6+gv0tSyN0t7FpFpbAh3++1k7Fsln2o+kP3s+4P1/xc42E4JN33KnT1tOmXV2uVFqnc+KEaW/x2CGKg1fbVJ35O6NWM6zKHOujwSFivKF5OoiYdxCR1heoiYtU8CGm6sR2PGQiUlKq3X+OiDhY7fGn/O31BCsZ3UbO9zVsk36m6O3DX8ioK26Oyg4PK/6FhWw/1AIpJVmDBiVETcHJ80yZ0wBh/3Offmnv+8cop6pZ3y+3TDoC9Z1G+/6He6gq32+mhzlQ9miK0m91CAZv367Colm+3f25iy50wB5greymvWH+6jH0A9q1POxwLZ07q3YE96jYB/q1X+x4iwwx2mH+42aWK5GFi8pOS0UO9kzW8X2ABzs2LW/J2gBk53MBzQODqMgE1Eja3vUJvBSmna0wBu5I2+g824uj3GagK2H76w/1iB+G0Puod4Jgm61m+4VSr6q/VG+szYvWh93sszSk7gMunR+jf1tYkvLy+1gN8u5ZnvUZgrkY4V14BqtFo8lLFOBhVgfymV3v+hwMXW9/17ETSnI2vDVETZua77M7BPOiDhq3HV3nfJOScse6X5XWb2PeBr3vfE11iOyAPyPaOECB/BLIB211X+l2aCHFJq88mAOKcA5konY7124jlmGHHBVn+8MEA/dCV6+4VSv01GWRu8SRLong74Spv3csOhXq0oGyMBjfZgK9f0bBiQ7du002nc09UWYqIOa2dh5XqmAPUY7iX3q9/1OROH66HAQPpBkYM+urBSlRHdpi/SN2c9SjlxPZ10QcMErJPNt0QB8eGGkjw4NBvnyXupeCRuxoOXwhQOvqg83ZHMy4Tu+Gy2/bWDyMd/2R0CTVkwP+WiBrL0ru/53OBsFEbuogMtbcSWhHLrXrBhBhzYqkaY/dYOl4IU2xFKgP6OgrGTUsT3BBsI73uo32u7Hskvuw/2cB2TWhCngMdYcymava4N04N+FKatIPYh7+Fges/2SBrTVOB2QNhHfTXfBpQOXHYoXfBlIj7a9D0/+0EN3urD0QBvQPKI9clsqowNSC9oXEeswNr5Ki69CpwMC+80FGMJwMPB46BgU96h/iZAWGBel1BuDekFajj1eBg90i4ZcTVBvwM3XM25zBnYPt7UT1mfVvCJ2fj2iKy7jgGOlWha8X2u7dIkhozl7+OsGiBKBSkXgy7gEmoMNuCsR2fYa602ah93SzHJnPu0TW6OhWrd3STXdE2MPawd91Ch53bDpf9kVPMUONht4BRhxTVmSqvCsCFXlQe2fYp+UKS5CgzUk2Z1UuvUzVth596mIioUiTYLaZmT1r8ItkMTho3gqUkN6AHQqh4/S0Oua2cP+glNVfHWeDGHVup/8Lcl+a+gMFh8ZHHqI/4Vh9zGoW6dgQgtMMJmcQHzg2EEVhowYSepoEDmonjQcP5C7CoU7bh2pENy4tUF8RRw9gFX0ThgnYts88GV7EcPymyYGUgoCM5YT+ktqv8NcSVq5E6kmwjRU/m07P8M2cCgl0rZZ3wRhn6G4o94ThhLbqIr05InSMN+8kgmDXF8PkaOUGJho/VpAg+XZh+oSvCxM75hnMM6goD5Jus8PJ3dp36wI/HGfWD75h1+Ld3Z7apS2sP/QtD7e4v8OIoCM1EnIHYThjsPURgO7ARqzgVQi8EDhvK3G3RuL9h2myjhokX0fCcNow+XG47evZzh4BwxOv8PLh2wkU7PSNX7RX407QT4Th2cBXc1mlifAiN8QRY6c7NlWURhuXBfQ0W0Rhs4TQsXZph6jp/8zO4fwliNUjG0XK7DiO9YIu6SA5MnZhvB3uyiuVXhwSP2fc3b5OhWq0fFz6Ru/igKDP6HdEpsN+q2IkxivyOdmv3Z/hkbYJkse6y7FPw4mca0jnbnYjh5WV5ylB2ZmEInOfNL7IR+cNpRgfZV4GyM1yg+4Th/MDqI4r51A1vC5MC+WVfcyP1q7d5dyj+GVRsh6Py4QLGtCaMdffMNt+xjGjijiN3JOYlDfNMPWfTe5jfHiPw/H8VgK46OZRszEzSnKOiR7TGLStMOBsPcVX7eyNyRm+V7fJSNURw75rRtSMq8/5XnfLSNnSk3nQR8N33fYyOIRhA6fivqOWRqb5XRgiPDRz6XoHMaMbhjFX1PaaMSPI+lQSkiNHh2CXkHb6P+R4VmjB4QJxhiYPUqnKOMRrCUY/AqOhDNrFYy+KOa7VYP4ynKMXRkBlWBksOG29cEbOvQJTu14Ojnf510MQt0c/P8NRgdEUGwPN0ER5SPvqg8PqYX+yXq3/l/hmiQAE7WZTR2mx1IWJ6K/VqMIR1oUyStcO+1OGN9ur8HoRnGEqSjE6oxp7JwhxX5/h1yMWM3SXzRwo5c7Bd3ax/8P7a5IWCxrlkD3ajVea4QLhWV+kMa/aPRu+LAB/HmNKtGQ6ca08NsxuP3CBa8PwC6+2XcB6MVGvDmSRuVUQ42SPNhpmV/h6WMxS2l7/R8HF+c4GN8y1KVgxxP2ZSyGNThnKW6iiyPhq6WUmxrgV4UgiNKAV+nhgzSM7hoQWGaTqPHEP/iGytY2Ex6QVGynKPgGLgUM+isPhR5QVsU46ODNdQUnG7MMJR1f0Rhg2OoRi8MiA4yPloCZnn/NsPEoEiyyAnoOfh5onZSh/4jW+COJWGr2hXNEGbx4Y50cwCN7xr4rqRhHX+7IKYUqXV6de7cNHHNZmnI1+N+RJYFb4qGFBTHGwsQ0317xrkSWpZ5GQM+COvFL9Fcgh07bhsjjUMQ94hAzeM0OdIVenTH7nuS+MOQqUE3x9rWIQs2G54NWiu4l4GIUA+WZmW8ZZA9iPGRkrBcR9M5rXP+MBc4QHxPP+MIYdeOSA1+P2EWoFQRqdFBupQHzR9yiL/VEHZqhnBjsc8MDcbcMJbEO33x0RMcXP7VnCtK4M4YGCe0Cz1th6yl1qn+Oyx/X6E6v82iJxxi/gq06iJ0mjrq/wFKJr7Ljq106iJvUBBklBMNR9vapR6940RoBN3JMSMvnV+Pcan9npA8BP6/EM7ZAz+PqFLiOv60WQ/R+hNqJk4Etsws5WJzLDpBdhPbhxiwXnGt6WatsP6sfL1NvARPmkfqNIW3/AL8UsUSJ+JNQ3EZmL47cP+uGq6KJ+COwMaz1zMvePyMSpB8+8pP/WrIGbA+CM+oKBN4A6cz15M95HA+pMjbGIG5vVBMpJw2OSguxO/4B+B080a6iJptUIotxN7xo+hDJrxNKJmBhiRgoE67FahdPAwGUnWWOmXFRP0nPSOQm/LXlvZ8PlJkEgo6nIxHx8pNQlVEEn04pPe+FiHf/UOgz5A5NHC8EDJnSX2o6jhNGmxW2wRgi2vLTjBIRtsOJnYROAJuiZTUpL0KsPSMHPdYH2nfCN7xz2AcXeBNXJr8wjASy1qs85N0JvpOqR2zD/synW4Jlajo0LJXKgtsOhbBbhfA397FJzoCCW3UFmfb5SVq1mWiKgLaOZH+1nqoyz/uzVV3EnrA1XIWUCO53bMpwThiylRVE8HrB/iKWVk4gySDIuWUd+gvjfKU9jKygn3spywXpC/v3Bbbf5MHcQXyXclP2sDY32KlTSutHY0C4JvB/8+8T+5OVNioOfJL+qVPSQky0Rq/VMa8h8nSygXDN3GVNJ+41NgPYHHW8qVN3wAD5Ws4fL6p7MCcg53kLxhBjksQ/4rx+COPGeakbJ7cMwBKTk7J3eNX4P+K4gw+Pax2zhCAxZFnJveOXKTfEwpgnDH3LJPwR29Zq0atXbh8FY466hlwRvePXy+akzUtsNu3P3JVJ3PCYXbuHrMrCPlprWA7nPwHcgtsNH4jU1tXfvihpg0BKkkUEUR5lC07FSNxp1Skha4ZOtpzTIxAnFOBpvIFiRjUHaxlZilO75ncRmhNjGP1Nb+rC7/sYVhC3NW6hpp7wPK8SN6RkwGa2aSOBbUNO5MA5kKR2RP9p0FPXA+CPpp/JWtx7NNiRk255p3rBwEymGyxktMdQi015phVg4iimmYUBsEe2z251ChtPGJpyN07VtMxScIFCvddP8WxzJJEqoNxpsjE4B6ZVX4Q5IRm+ZW3pzTKToyKNWJxL2VwxO5xRtsPzp2j4mfC406bDdMqpgaMPxsFjrAs3YbvPHxLXa3Yt3VtN3cxs3hi5NOuRoDM93CqNXplDOBR5NPgrCL6h7ctNr3Cc1xfctMlYPKN5in9OJ4aDHFi8tO/pyq3li4tOAZtHmskfL6YUZ8AjcCr6n3SDM1cwFAti1tNnkpTEdi0NPIZi8V7S29Nkua5VbRsdOZiS/V7R4jNTXFDFHRqdOVeWaFnR5dO+phFUIxveNBptcUNi5NO7pl+VPR29MZIlaVvR09MmCt5VfR29MWZ36PfKwTMNgm8X6xx9M7fa75Zp19MiY18WSZ8/D8YmGOKZ8l0JutLNqZgCUoxrNPaZ07niPDGN0oKKGOutNO7osR7akxR5X4BLNzwkmMwoYdNiPRGX2ZpfnUxq/bbh1FowVHdoMx5zMLcTlXESn1OsvWJ63GjdNSMu6NX4J7z9BweGhpxfDn0/BM0Z2zh08iWNi8mFDtZx4Oyxw361YxWOiZt57TPaX4cJmZxNfCSUvpxvDpPXHiyZytOO2l9PPQs2N3ErTO+EN+GaS0NN3wjSVfcqaZE5FsOycczMDpyUMop09ilVY34ZBI7Ms0SxUBx5zMjnQZ5OSobN/efLWh/OBELJ2m2RWyu6KZ31Cj3f0V5p1GxBiljNZphfiv0sOUfpgL3qIvz7gHAXD/s3OXVR41PQEaa0pi2XYkrYibB7Mdmz7AXDUdNkkdR7na85vL1FihbjmpjEH853HOipzWERo/e5Wwc1NXci37FfPDkC4Eertky+5Lk3LQQaPcUfUQXPHqHrGWZmjN8UPRgDikeXlpqakji8dw/p5YRMutzPFpiq2nRucXLpitNIhxcNZppVCeUwYBha7+xmXcyl8hsnNaLCY5RCrNP0odDWthqXMOQFimgegO7ukFLNYIzIXGplvZ1k/TVInXnPVpMI7FC3XMflAL0Wa1AnWpqRWYekDPh54NwRo144iInlMk0EZYLkhFSZ5plwmWmRFp6zXMl51N7mphnMGCsClEUOe7+or3OCkcLrse1MNu58rAOC/l6KZzFHCvPMM67PPMeAzL7pR8vMg7TmUe44Nz+7IrkNCpIm3xH9XfKdSOO7KJ4ep1IZNfWnPGHZVOrp+T4CZgySwjNTzCZ9fMhwYqWR7Ui1SpvNDwu66G659v55dIonoZJfNYuujOS58vNCpnb6skOXPOpkUmUcpXP17CC6KWXfbDHDXOLyP/aHfHXMepilMrStaPqp43OgHOzPh5o3hkynTCaYFPMGpgul02MXNq6Ub4rGMlMf55z5f5wVPCYGZ0ZYJNOCp44Dv3Fz6X5nAQhasOUMFi458007Xf52+KRWpnNS50sDbqzz6pyqVMk8c26xfW/M8FyantRx/P6p3u43O4uVSFsE1JEsgssGb8Q4cv/OV7Knx8iXTPUaQQt04AAnq5nnMfwROzSu2At35zgt7ixAsBIK2p0wwcV35ye7jyrAv6pt6gQaQ6OJ2BwsMcxeVEFifMkFgvM/HXlP/QvSlvrb/Nquv16w0DB05uf/DBF/pxP5oagUIx4hqFprXPZqPO650sAge4ynx5nguv8Nknwe7AlKF8kFsIjl5SF8iDCar16AHFgzyF7wv6FyxR7I4RHhG9QseGlzWDcKQueozSn15uIv28hCkTg/QvZC2lFUpiwvzu8RHmCmwtW4kNF3JVwuovTMMlFghiwjal6mHCJ2lF/XNlXS8Pl5p85LI8EFpXI554Ueamz+g/MHLBIuxp/VOg0BRONnX8NSppxEQAvcEnFhPbN4tC1YXWn7OSGYWQR/YsFmR5Mb8x4uE0FHVlpqXPvgo/NE68eypvdd76FvqbaZqBPgpgyT9CVBkdp7/6h/PrAwQ7Is8yqfMDXaPP9ueT33ApVNroKipMR7AsSbd5Hqg8hM8F0LbgQ0lOeFxVSR5/ZXv55YsEZ4SOCFkPa63D7YVFt26sOla4npk4tLYQ3Eq3fYuInDb2YJ0EuXF6kWkfT4vw2eMOUfSAt4aX0kE4S24nF6fCaU5j4gFm05H50kuPFv4sWEnj4nF+yGLO5yOfFrOBdW0O7v5ifbDAyO5sq0egclx9GoZ+0nDDDO5jsdnNolz0W4ZuQtoc2KP53UouwjBWlJR4gvEl3OWKFu+m3xJu6E5qks2/Rs2k5pYsXs4PZefUEv8wnAO93dkv55+MU6l74Tt3AQv8ljwRJEiTOfFhFTGPDqOWloNH853qMnFmbPUZhUvf42eVF7fYvAOBMmTRuIv9CN3YoFozOfFgDA3EszMnFo0sG5qQvX4TDHWFnguOMAGO9fQQs/2OnmTiiotL0Ys1eZvf5zFkksICJA6lFr0uBZuoHrFgIPH7MLOBl4hyX7PB7Ml0oixZvp6GlqMvdipLPclqCapZ/YsCltHmZZ8vMil3fYcKV4url6GOcPfYu5l+GPjSiUuKl0bOAS7Avemm4Dox7Yv9CUCU4xmsux5qH4Exz4uNlmWPNlkTkEK3UXGU9EsDZzH6lFxLBf0pYN4lte5i2qbNElsosvZ7suTlzN3TltI63nfmOoB4RKpDfjGbZ/Yu+gJFM30yWPHlgCsdZiZ6OOFGhmHU7P8loahzYy7OPFg2DeHLWOvF560om3POylyhm3G34sFl0egYWJlODUGUXG/My4ylsEvo5y34sfKEtIdZ2ORl+EumSqUMFSAL2v072PbF1PjBUAo5pqpYuwKUvGQIjCugKT4MRxzwuCGIEuF+8vPqSyN4DFqXOOMXTVeh/vPmViTY5UuLVSpphgd40l55hlyuQQbOmCazysL8IoVch6ystubLYhCqTUuV3u1vwuTX6puVmKa+IVS5kyuaUtTWIljJNwemUFdQqaqo8ocPbFup6pYvIsGayPY5SfhGahuKuCGZAM+VuKsuXA5ml5rRnQMDkpEw3KzRvAyT3XCR3kerKucsdYEdF7lU6bJJReVmYV/J7qt+VmT36Fy3bBVhT1xF+5UaKFT1RVoUGLMzYVxF+Kso6yEuT8TrmZp8vNm7CYHDUi8GR7Yki94l4tSp5cTO0r5PFVl9wm+g/GrViqtSWs/n6pu3HpU5tMylpquIQunVxVtqvWQvQ1xVhyDPszb3mViKDnpv30GSRxi/BwhMAC7qtpCgKGgCzyuc0KAkS6rqsYMQFRE7KUW+VwHjy6xpVRVqILK6ikXWV+WGhemkUuVoUH0WkRTq06BjvVt31fcouLO08W4FKq6sZYDgE8iq6sTqAGm8J2mu3rZqGScyCtYKY6tw1vEV7V86vcfLvJXVjuLGfYK65Biu5HnEPWIqK6uuQCZ35gK6tE18QNRVllBEw1ZUgljB61HWwk5WzytCHcnaUBv6tzRTy10B8Guw1tdMQwTwvbnIQOnOhGvTWivUuVoKuj3bgMY14BPG09cs6YAsxtm7AvzV2Wt7VnGzhu5IlHJxqsEPJMvAurmvbV3Il3ViJGb3DQONVkqu+fM2vlVmZQF0yhF81glTtfX1J3VkGHZBnvb1PRfak7ZmEVhOasy1xLNWZr6uXck3PQs5Ws5O3+79WMauJuHB7fhoatiRdwuPWhyvn7BQsey4gsm145V+Z7WsDV26NBZv6vW1ucsl1hgP21w75RZnGvO148VxZ1at51rcsF1xque15h6vyymsZViekm8ras5V+jm5Z8qsFVwOFXlvauR1krO012OvlZoCWNV2queYiR5XVo0oi8r8urVtqv4VuCV7VqeuHZuWsGZhPYUxv6sKFeVk0xqKuOVmCvo1xutuVxkmIVta7dVpuvsxyutd1hX491u+50s+iWQQh4wZfHQ4ix0es/YDiVi8wmu2nSt1XVv/hwKsX7v5jXgApC7PG2xqs2V0bGsVrmuWQObFq/K6t71lCsx1sGR6/c2NxVjkrtkjDWm/Cu6vw7I4k19SAOnRTUg5h+sYN8HO65oXQpmkp4w5qKsQkIMkI56yt6YcIF6VyusaXNyXh/YBsw17OmFG/quI1vyVjVvut32mUvjVj+0YCv8nWV6auZx/humVnON4NuesSKvat+1xlO01oOsZSugWb1g6vDG3KVHVt0kt+4huH1qY181mR4IOuKtGlB1VLGm+ts0eE6NSyesCNsf3P1pd6apg+KpM1inWy6Rsg1vqWWl1yusp52WrVmht9u49HQMeK4q8w4MTFiox42Jn6kViyT3ifoNFuqVMik4c2y8onL6p6W44qniVS5qxBpAb9WWl+KE52Qhte2qVMrwkbO0/TUDYFgRhP69LC47fVOWQVR2Hqy0tcs3bhmxuBt0oQsFWxxxvl5tW58UThtxFjoB7DBd2UVhOJNpxIt1Nz1HrA1StXV0Hjk/KRsZNx7YsajCsy2CTFvYuBG719msvZzwtjNnbMnKhvCwjdYF77A+UEfX1P91qGEN4Hg29l/1xA3DuQkI3b75fbQigN/Ov+7XU7EVwGOAHM/7/XZetfy53a3lPTY5Zm6XIt/0HBNbeuPSjFsmnMxvvfDuu3lLnZNB1FW4tz85BY3+xA3Jc5hbSCU0OUZs5SCR1kHTd3l54pwG1iivbFipEjV0H6TBqXOYXFEro/TRHdN7LLqI1lW65yyDxhuuGdVonjuaWaD+B4/h3EmVvHIi52mYYLZf/ZxT+l1SSqttVxQ+P6GfZLVukm4GE2SfVuVjZAOzO4w6uVAJOO7aQMF8F0xZgca2BY/Vu9UoIn3Hep6o0CLB0FvGGV7AmiGaUgs6BvwI5HQ01sMKlsri504oFqNSz7VBQmZir7lQbnZWZUnZo8sUgWY1Ggmt461rR9zQIYD+X97WNsxQ81Xl1gi0yt5XYUwkwFQt9TBEVzzMdYMz7etnZtE6gmgeCEJPhWCNvtNPtn9c7/4XQbT2bF1YUYt3Kz4IxZGQ6i6D2uU4UiJrts5STJPXFktvcIotVnCi8GqmPoQaJwtP5t6gK56ki2sCLVsmy24Vtc1dtlhei1vCr1vt7RwubUrVtrsAzMsWw9ufIS5mvV6VsqxOaDntr7kXQVXO7ektsQJ5ANxesXkE0KKqh+sGs2tkOBCwyP2/MnTZVtiKMtK/Vt0pDgn6+w9ttIDXEYWWXZtt0B264rMVft+quXMnVTZtvrDjN3i317BAhs0DKEU1jFvcIhClowkmMztui1o7DK2XtySn5k0UWY/O4YQtyUWc1r9tb8Z8g81vp6qmNfIP0xhm5BlQSPm1mli1rtuzxNq3AnXUX9t69vu1hDtMuO16K1jDuZSNjbi0itEYt2HBl1xXZa1gmie/fZ1wt79s7N+Us67ADu+tlwlft7QB1tjwnHoi6BtIJIm21y9sWoNkAO1tTvdtx9FvOw9sDtlvVxE8zsjtxs3Wtsjtq6HdETW+juztgnPj67zt8uOc0YO6jtstiu5+tmdvqlFDHx13Dt4cWzPJ1w9sNC3Qvp181sCGB4md7GBT2d4TuQtw9sj1dIXDy6FkgIPyl5t/O5vtwfGDfPiDAdpbBN3ajGX07Tvuymi5ad9Ts4qk5W1tvyJTl3dsh0eMM3KlDvttpcu78i6ChKdb6bSrtsOdpsvDtu957l3Dsed1fVHl1lQ+d3+WbtgLuXl2A64dnqv713DtbtzGVPl1dv/hpEnn1rttVHMF2EHdrufIZjktZ9rsjdwCtdtk90wM1+uCdzKQbNiCvQdkOCcqbnmwVy9uZAAyyANvdENd10Z/8+bG7t/Tutd9CvtdtpAP02BvddqMN3q+FiHtxVB823n5InITtod9luHtkbg7Z3Burtia6NuohtEdu9m3Z9bsCMbw5UNlbs0dhSULY8LuMd97O7tk6BtIK2Om/FQQZXMd23tgQy9asmAodi7u7Nq7ug8y7E0ahDsFFUbGgI4DsBEGQ4hx4Dsqd1O2Y5ta61dosPAdgztlhsLXGdh7sbHP3PmdnrtYIhsMIdgbtxCoD3DdzLsc9hDsud2UMY9ot6ZVzdu0pD3Moe/HtLtxI5FVsjurd6XvrdiLsOa7buh09oUNV+nu2cTzXJd0NF1V4YUZdpHsg+5PDXdmclWV8ztJSal5RauTve4Wr6/oI2GR9zmjTF8fOS9xrv8pk3ktdsFGeO8DuK9mmVdt1XtbbIJ3J4TXtv2nXv+9x0PIvTDtlYKxv0dqbu2N9btm94B3+dq3sR87Ntrt9S7Sy8nsUK7gXRd/dt84y5Ttdqo6qNjuNPd0NHk+iQXF9unkequ9se9xikFs0PtJHOf0JN97usEev7r/CrvKewpk0O0k6dOSlBGg4i4XIL1VZa7lGlbPfuqVao2V+uMR1gLMCmy2v1H9i/ukKKP6N+8/vSp+73EyvftgHGC4ip3cQArYK6041WWP9vRiDnfJEQ7PfsPwbd7D+x/tH2V9y0Umn0R4fX34OmfsR4DuIkUyvmf944gclI1PgDr7IIUs1M399sPnbPi4v9soBmZVh2wXZ9ER4WBRSqp1PgD6H5Oc7zYR4KxBN59zkNdhSyQD2NVat5q4S1L7WNtr9EiG1NWttldNDsqX3ZqpfCcYdduzVrVthp447Xx81TPga9ErV+FS48Z+NTt3dtsYFX5vJ7NtuSDK6HVy9tH428RVppfAbKcCE7t8QdkYlb1U6pfAuwm30ntjFujsFJocW9QeBKR/2fVpyT0Dya6/VhSDW5hEUI9j3EdxTxOBQjFsKDu04/MytslwFgfyl/wdRVPf2JO/wc/vIWVweHS1OSBQYrey/3iD/aHWQsy3WDhwfTqyTuKWa5uYEyqHiD/3KxDpy3iDqwXNQp9HqDtti38ry0lD5ORWR6wcGDoaE4CYwfzFiaGM08QfESvmmh66weFSbyNc05QeZDkTuXt5qhZ5CaGJ6r9sUU8kkydtPWidfROa1vtt+wJMOqd4IfMD0OXR1oYcRDtgOeE6Ic8KYPZmdhIfivdjMm06wciDhDN2djIenvcMvJWj5QyDqQMfh+QcWkEc2vtulCcM4OslDkb6Bdkts6DiXNhdulAq5CmGh05odSRlAuNE9ocBuPcUHW7QfU92wOEur9sSD6V16m7MSCNcAu3m/wceD3+7iwtgfc/Zh7Mu/wfbEU6OBBvf4KQLOAhBzjmidW/jY23/VDDyTkP0qFnZtvc04PCG3HDmhxWwqA2wjgYeOB8Qff4BkfGm7Qctm1A2/E+odIK2f1JtulAolArO2Y+oe1DzYnq0/Qd/Dr002wpfBAio+k0G7Qd9TLoMMG2EeQQfj4s28Qfsj9m3+Dm9C7Eng1sq9wco0eR6CGzEeVq0Q1eDhQc3d8W1J9lYfiS241kjjge3FsBNUjnYeqG5W1DDhQZ82pBkpDz5A8/bW3aDvUd625QdLvFlU9Y5QcKDjeFEMkocvD0hl6k2EdtsOllUMqGH6DqUdGxsnu/D2JWeGwkCAjhMkrueS7mDgNzfZv22aj2pGihoO3nD9X312yTsh7dIWsm5LsUU0mi3YmRkzDyTB8mhUcLD6SXi91RnBDr4faB3TvaDweAyyQztPdriT9Z/nZ7DlPhLI9u4N6rVvht/MnCBrwewfBDNOd2agHM72tAD+WCY1LnMOtnAesdixmTm3A4R4X9DJyuhzzmw8dMuMF0IujAdx+f4fZgFza4cPo3bm/qyLj87amZw82Lju5KG24jGtZ5GDC3BNsIjmHbmulAsojr9tcsoygX3TwPWDiR6/5+/UlDjmWjfAkf/turO6DzO35dr/Bjj5905kpsh6nXYlF2rrWzjuUulk/rWQTkI0OUmu2QToCcMmhu3tIBgWuUrY4PUShSHYktS0DsoCIRCIUvPfrZnjzh4DomzZnjvAfJo0Ylnjh8cTkhOUvjmgXiI6YMfj0sfLo2l7IwIBGUqicHZjtcc79xScw7HKn7kjFtCcoVl+zRhsjjifYKUs0PaD+KFkA1Skn2zfucT4SdMB4ccR4IgcXOnS1kDjSy+E74UR4agdhi6w7PjsoD0D04d1HLfuhD99GVgvfvU95MVud4/vVsEc39S1/tqesDGnj2/vRqGF1Xjv/vy1nTuCY1/vnQIr7rmnyfZusAlvj4d579z3zti78c4D8crTvQ76nm8AdgPY61EcmAeNK9r4QTlAfD/NXOPmlXYOTtAdAPVGwcT9sOsEJGErEgs2v9i4crWv/sx+DAtWvRbZ7913boiz4zuT76Thg5MUQcDHYXIMsLUYts25T/R3853AM4DvW5yMP50bT31K3jnYe8TqCAkkIVknj5aenTr9Fh1gcu5ThVjsskacoD6Jw0jnKc7T8gPgFnc0bT36jcZywN4qlacRj461VTlAebT3U2YslaciDumFNTvfvOKCSsPWjt579u3HKymWE9TqkYWnZ/UpNQacX94aeYTncfZEgmota9RTKHKafZS4yl6nQSfzTojj8I28QBTisY5E7+EbKnacMOzIuOUx/t63GKNYI654HT/2CeU9id3TxtONjnid8z5Yx+vKkZ8ztW5vwhrVPT99p2sgAGSTs/ZZ9gJCyTnafm+mckBtDadLvOS2qT9qeVHDCfmNjada0LlsaIomd1gMOCVV9E7I7BGdCsUrVPHS6c0xUcdj52ArAfC5D3T9z1va52fO0sd7VM17bOzkmGz8hcHazu+meomYVZq42cZCwFG9tgOeO3Dr3nFx/ur0ftEGe3Kfh7c60bVgOeVkToCY62OeyHUyEPgxOfEjk6vFUmoKIqZWUV7bX41BDkuIQuacMpYGy7U+/k4Dn0CXQOwd3TlEpgusL3Ozwc7Fzv33Oz+h2gcldV1z8qAyE4XV8zsGiQ1hS3WT9vbizuoeP9nGzJmdS3Mtn2caWcW6n+52dn2MiPJDuucq4dXVG4pue2Ts4FI0moJGE0Gn5DnAeZiBdOW6rfaFzn5i2E8oe5z/idS7EmnHzvOeTzlAcY05WVa7FdvHzjIK1feAOpwmoKxMIQNvF3Gc+gU47u7TANPT5ufaipzttz4iY/UwgN3T6wSq1iWl3TlXLIB8lhbC52dKqCKN0Bo7boLied2TjKdQQD2eb3S2tTz32dNW0OfElvfOPOu6f6+l2vbzgNyDD/eeTpfafHztlT6N+QOhztOfjT+45VfQuc0SG6c8UXOfb9vBe4zl+cF0gEcfzkIkR0kEfHz5hgrSiEfOzrlmU8k610LsF1H672cY5AIM3mujF1z7ucPmjEd9z6CfZTxCd1zxBhVd1CdSz3Bccc/BdfUmedmYykfzz7r5N00SdQQdxQqm+THrz9cnSu1kdgLnef90+u6MLp85k8xOeEQw8sCjzOel4c5XYGh+fP7QBUSjzOdCLqxciLoudiPcm0SL5dmcs90e/zuV6FwjUdPTnMbis8aMqL+TmTTjHKNORXlwL8hpiPC0cGLwwHWjoef+uSQ25YsecuzzE3S2p6eELuW22z3o4/2L0dUK5edBzpn7q2qec0L3Q0s/Z2fgLrBnHzh+CikqMfBL1yMMVuMcPz3gu6kobG8Lz4x2222cflt9H/d3Of9zvJ5eG2OeInChVFjxrZZLg30lPcsdPTxRd+vMI3qLzCv0Lusd3Twc4aS8RlPTpsWxPXp7kzwsYnyrsdfLsSKCjG5v9j7BecdJ3l6znAccvYIVfHGM7gr1R3cewrWP9jgi5Fv0MH2nAfXh68lqUhFdd5Mu2Szu8wonWV5OpXKeHnATWsnGKcewf/DN/ekmPci5DI24zV7EE6d1fb93uxwlcBe9d2pVu5eNK/FN6ah165T+WGJuMcMlCi5ARXQsc29wVcwGAAllVlAezxEc7CI1z7UrjeCbh92HMr2NmeanqdYcOFPUewRpOzhigIMZZOLF3Ffsz5y53hx/senIBE7x22fAOOot7F8FfoOGavHF41ccXS5MBznch0gUCOP9jlePJh4s4D3leKD+du4zoVelp0QuSrsVf5z/pGir2JgXV+tNur4TTNp1OBKr9T2HAztPgrqdkvV0gcgr9dU3plAccvAhMPvU87UrrfHLqohOhz2Dq+kzgG4z68Ol452r8Aseeo2FeFPz/VcK1ykvGr6BKClpD6EryCBFQ9D6ErvqY7AnD53Lhc4hnDNfUrlld2nPW4Bz91eOW3SM8r+h0IUsUsCr/0YHRu+ffpr1fBrutf+jcNc81ynaCr96uDK9UuZrm2ATm7UuErh8qj3RDOErh1cgLgTPUryfbZ0zDOZrsdhVDy0W5T2DridvO4Bz68N1Ox0VaruGy1r6fMD7etdELhz6ErkJsk52VdkrmDg96jjPUr4n4zTj3ZfL/tcXruWc6YaWab3NnM8rqLFc5lqNTrl8Delxe5Tr8XMi5jQ6irlZhR1lTNhr6VdAPIsvgrucA/TrHaB/IddRVba3VlzNcOvdb71fcFfnrrLvgr3xg0btst3r/mBo8rssIrvGwfy4B53L9zEWBWcUiA4Fffrky1Lip9cFhu77zfIDctuBIPzl6lftrq2Ej141fdr6V1Dd+1egr1/aPyodc2JCbtur/mC+kz+VfL71d7yjetBrhdc7tQrNurlde3l8+drr8jePlirOSr96tvlpVezlxg7X16lcPlO+t/lzNccb5Htcbhz4gV3Gd5uYQ4Ctgx7IuOCh4Sv+t6EI/Gl4uuEsxlLc6riZvybvFeZun3nUr6BLN/Jd5AY9Tc+tqHuEbj2DempeF3Bs9cGb4mM0zpDeDAVptob0GhS/Ow7LrgWN/B/MfLrk5Mom/t12b6i2pu+ldSr9EWMWFDVeriPPfZqo5wb1KSHY3DWhzrDi5KzZtwbsLcKVrW5Xr9zf2ksRswrglQfLrSvIuRxcXNt9dH4uS01HdyWorrFcyHM+HSbmtempggeyEXLdX2kpd7EhWd+O41cab+mXabpQC2hnP7Ur1bel94zbGbl1cQ+lrecr7o2S3UVfdC+vt2bhMkN/P1fOb9gVOb9dfeNibfMFeQW993zcOOwftHrhIihNsGiIb+DdQDovkbb2P5T++Af5wbY3xNhKdfmDrDBq+lfvrvi7pNojeDbwJM8r0BSb4kNNervZGPh0na7JwVfZwN8PcnI5OCr6YO2r8+NurqG5zt+GemBEzcJznAcIqcRMyJu5d4UEBNvJr5envHCeXI7fHeBBfS/mjdvy7lrbnp3RPy77PBNfXYG5T9vm0fE86nLpFBKqU6mRAiXfPkNId2J/nfQV+iM8rlGkhnSdOSrwHahe2dNTr/QbLXJdM2PZnepc+7eXj9YEZ9rndMqu3lrbQVcOJwJ2GNyVe6YbjP2snleS7ggWI47wJ4V4HFo47wKfKal5n9lAcq7hx3X9x/sa7pr4o+8ve67qP73by5RF/EqVJc7wKZYd2mSp8vfGUEJmay8vfTlRVM274vqksonc/zrsAM3YePT+wVfj5Sx1erwHbI+lfvLr/QayopndIoGvf+pha7eBV9gMkiQGgb/+zSJ3nd0b0sxRgYpHcJ3KeA3fhOhzzphXxmOcoDviijKlausbUM6940ZlH9mkAWhmSFr43cTP7yA6G+p/fHqUFduz5/ek7VkF1Jq/fvbP4GGJx/uu7GQHBA3NfXmBxgpr+LdfPLLe2J9bf77t3d+As2HeBI853sqa55OtffDRUAnfA6vdVHXxNfrmO7mouvfr72VF2p8vcE3JOOr70syIocN10o4/fXrn7fMonAfn7+j2A77jYJEfOP5bsSY6qaRFF7j6TMFcoEONxi7CHj8pBkqvfv7n/eVw7yUSHgA+yO22d6Bcijd+9g/CHDvtd7q/euRkLVgDq/e00Ey0yC1jZX7Uffk734f3e5Ae4HtyPeKi3dWm3inc+zfvP73/fLx1fc0gOvzJzkjwsJ7/fp0HfesnOjeVgcih9U5oFxiGkC17e8FJJomeGfFnfXxj6Skmjw+GA9C2xH2KZYW1bkyH8qCmA3r3Pj9krUzr/chHw14D71gff7oBR1ijAGZL2+Brq67nQJoo+u0M3emJ7w/xQktddJ3idRHwS2DrysA7HHBO5rmkBvUFuevA5aduH3AyeJgg8yH/9kKz/4HYLpw9yHl/tuH7hesK7w96YZv4ferI+ltu1k/e7w8j7gwV5+kY+fGAAlKqvI9xHrlF577V7OUxlPtTgMoZH+bZhc2I+AS8n7SH649O7lv3XH6w7v93RVFHysYSVtvdpHwDgHM2VP1H+Ce975Y//vAAlGH9o9H0DqXCHxwtL/ef15HmSzls2vneH8V5vos1MTH/I90s8ANpHlUjidxtdpHsmCgp1tdFH8AyG2xkvxbm16Gpu85sl7/ch0EoNIHoAesgVyNJDvksyHjMSetRHaTryk81Q/Ruzr/o9iCbOCRQsyPLHtdg/rgPG0D1kAQcRoeF5pk8DtuKH+3Wk8BII0nuR2U4fSUc6GznyOynqk9Lm7gtpHo0Qmi5o8riwsMafGXbLHnWHJywjOTT9kpd5K6EullE/EIzs1f52I+Yn2aE+l/Y/YKCc3Bigk9E+m9GQb0k80BnjOe7JU8UqDU/TKpU/bERQmobyk+eFUe7Jlpk/OKY8cyZ9k9PHIuUKZvI+Cnky1b3P9einzBgjRwjesgbFQUuvTPJn4wzkYuaMCnw5K6F+svJngM9mFpLOxH4VTSw1AtpHnvallwTcYnv+LZT23PXHhoXuFqTeOH1E9QcvzP2ng2DnKu6OxH3E8gGtTe3MBnO9d72eknszJrlwSevfak/T1kU8WFxbhHSgFVMng/C5do8tKnjk8A22zc7n3k/Yt9beinxA+bBu8vJnsU9H1yI9Xt15XUGvbsFnnH5g/Sk857/GOKPf08olApejBms/ZL/12ynvB3Jy2YNGnnnkpLt7sdnyyTMxp2eUvAo+7B3U/ZZaBIlY/Ldmvc5v8xkrcTn/FvUHK4OUn54/FL2puUnys+YNyk+WVE7N1u8M+VqjeHtbi88vhbkkpPdk9/+vreyrk89CnmC8Cny8/Ia0NddzW88iVzDWEXu24ukwdTXngWOETsmCP7d8+Lntbd/n0HmEaugA89hs+rikBH7bvDpPnYXso5oo/O5SdFnb8Q9QX1MfXbns82nzymu5jE+Dn/wWnLpC+mKJV6hV/Y+EnzymRVrC9knvV7a9is8fnnEMCn+k/vutIsbnqpA8z7lfsnhVO5V7k9kTTIsirxi/Yr3UPRnzM+4euFMCn3M8XamyTznuU/AwS0ORkEs9BtjVfdbxy9iXgHfLn9r0PKze1FH9DKl4gydO4+0/bKEydxXvBQik4+1bPe4/QXrSkpolE9OAtkl7HmQ/Qb3x1uhky/mkOg072+yv/KOPD8e5yt5Hq7lw0VwWnSZY8kWe8TlF0a9SFQ7Ge59q/GGOAhK9iy/NXl00RV9XvNX5eDHLsPPNXkjnMzsyUfSTXZT4uPOJqva8jbfbWKh5Y+cqHgcnHC3t5HpxzMa63szh7/eXAgTUGX46+82c8mnHOK/WbZE31F6N57XnxPiI/cPnXl52pXqVv/KEYqvYv/euymZkJqnbb/KQIGTt0nYKXwahIiYOedtga/rXhatbg7/cNXx1fnXplzGesdvnXk6+LMz1c3Xk1cTMhtXnXhK/rHHOePX8a4ZpzROPXrhw7AowePX9ILJyhi03X9QquDx6syHuzDOas3FjLvVjbXgddnU7G/hWX313M5q9i6pUH867G9x4CxPJe5q+x1ka5BD+q/g393Xw1ga9TXpGuaX5elRRE/3Jb7wHsIDXH5XWU9oKBhr0ijKfC35ySi3veetwJlzPt3VGyn8Knv3AjsBTxRryYH6krXcFN7XhK/hAyju6np6/NKrW9835m+53OUVs3thhql5UVc30LaLOputA33cgQwkbbm3kW8Ib5c/QbkUUWl0a8y3pZVZ3bW/J+WyO2i7G8q37ZUhTvVga3qyPq3zRd5l+W+BsrKP+LvQGxy5jMMX5G+IqYqPcnqN6Od/z7/KdO/RlvG+3oi/NB3++lJlzDd032EaHo3Dd03+WkEboO/03pGF2ni1ZvXrM9B39IKll2jdnH07B7naNtX3R6/5vOstsbga/93pc+jX5qyr6+s8QqN6Mj7JzOF3pejOFhk5g31+L9Tx3Mh7yu+13lzdxXycyVwvfb+H/W8Xy7cVLXlG9Tn0a8Y3uc+jXk++Gb6s8O33TAMj46XHXiyAX3bc+e3y69zffc+KNaM6AKnetk3pyVrdm6/h3q8/nXuz1dB8/DcnoJ4A/ALetwYG/gykLd93228EXga/hWCrG9Zga+Vqr10huwu9DUJLfZnlESWSBCvfdns9jX5WU7L+u/Q3yBt/3yanIs4psMS/5RDUHx5IN9G9twQQ7w9iB/0Py7tc32zg0VgSVM3rfijYxisT3qHN9NpX4z32EZ6xqm+4P2hth3le+U9oh9EZWnvtX74QHM+2NA3qo43LvhvH3tR969pa8BEObfbb1h8WIGQ4C9+W890x7Gsa5W/j0m5vuSmu/jXuP09Xhu+aN0a/w38HFx7429kgT7drX0lZovcJ2qPtMkg+v6+wPyvth3xB819sm/QJF8llxsm+YPpgUIsv28WPxHdWPyf1Kote/9OLLkY7x6/c35B1B3l53E3fHeZ3yB/YOn+feA7nfgn31TFZqndd3hW+bXWfcDXsu/r98jN83he94Pvm8aV7ut/3/YG0uwB8fST2AjyIh5abmQ8PABvev7PTf7PlobSuoze3gFLBwP9c9bPok4SOyzdb3u5Ir49evotvI9PHfpRHn68//EkIP9nvVRmIcrPMYrZ8rMZm2Ut5c/fTmBsh0P6dhdYVTKPolV5H77f4VpCVbP6TAoylh983r0ukHDh/LPvW5NB0C+KNdpyTZgR9v3rRUWO2J+ElZOVR7m6/eJU1kpP2RCh2dJ9bP1kUEC37c8QVK4aT0F+XPwp83P3o4V+mH1hBffk1+q491CPyEN+7lN8vhlOkvgNR/PxLkKywF9UCGpG/9/Z//K4S6OqrZ9UqVnHYKZY/wvuxWDP2RC4/EZ/oBHb3jP86/dp24/TPhZ8Jcjm4fYsV974qz5aqmQ+NKksk+y/C7f7y8dgowOV4asILbECR1hy4x+vP+ROsOvYbRyl18y2dqOanvGRqc4e/LHkwG1pm/PvzvI+tB/nOSF7/ci/P2YEb5c9+5XJ9eimfOgyJNoy51QtRvjXx5nrQvxvlmhq5iAvTnh/ihg463GF158hv1aPQPv2CGwNHmX3uoRW6ELWkeVR3LHgINlowb4uFl1/dRh3Ozzft/ivteUfuFE9fPy6Pnn+19L7QLMXosILLZBkcaKbk8cg8jGAt5c8xDvHkP7XU/KxpGf9ykt++Lg+LwP9PxCF//ansLe/4JKu1oPl58yHkX5fFD59RvwL6ic7eU5v78P/PuK9Q+FCl3nvW/tOJi/IKulsuvmKQ8/WF/2vut8MP+18JYFF88t+18ZBSxWoy9q8BB36jcP2U/i5irFcqyC/DIEd8FSuK8Ov571Cql18Lv2g/LvzGpvopg8uv8Kw+9rY9hBUD9mV8N8PLrbZHH760CcgB3nv2TLPewV8g0Ts7VP688Zvy1Nk4l9+bI6V/cnj9/8O9VHJv/mpOKlV91CQD89P6xVUfj++RNl1+FntVFj71t8Wy/1Vdv//tRsx1HDvwmir+yNXabUGSPvoQmh30GQcqoSPCNqN/7vNkUxC//Pxv+lB/811rnzpSjSYdJXLH7NOxez6uRqJRC0E2U90pfRvu39q/CsDgiVKmV9KUPCimR+pVufzlJtOkz9KUD/22RraYVv0ce5vJyOAa7/cwKAAljHP++lEF9zu7b6lufkOMZ3qN/LwdRG3r0GRkYpj6afd9+5uHDN53dq+hgC+FS7Yu66nnj++Wo2s9n1r9LP0z8jRJB7w2bj+48ChU3Kiu+WYZEuPKvW9dfFq5rl3U/ufhAsNvi5QJX0zcyHulKb+5LAgq9L/e+IWUsPZc8GgyoMy2a89vXl6VTvyNTxft99ufgmq/SkF9uf2lIXflBXpfm8fNZ4D+RqQr/qPm9/uXWuGov8r/7NuLf1f3Nx823g6ynhr8oytD8onzr8SvhFRSs/7GkDr0ADfx1NlHkb++OtY95Hib+G2+VXpf579grpH9Zwb70Mf5b8kfoQ9hf7LKlxp5VI/zfZcpqVFLf6L/1P47+BqKZ+vHpH8E1DWUKvrz+Y1QAdufm8epnPQ9Pfup9Fc6AdegEr/yClT9Xp5n16p5N81f6eMhqwz/vbFi6N8ns8HfqpORqMa07VhtvPjgCHU7XgftTwcqqUyatH93Cp7IkK5iDnX8mIvfExHwcoxSRJMJHxU/vCT/K5pw3/RiHpf4WoAc8MbuYtsj4u7iHhjyft2fvCfVSeJy6uG/qMCWd26sq/qD55Chb0C4jKS0UVs3P4x39G/0L2efzX/K7d9lS38P//s2L29zpH9EZM3dK3yNQUNNL1Q1in+svobdufxX8IX1x7h/xKx5ms4Nu/3qeFo3OGYXuMS6/nt+BPXC/1/mP9qHRF+m/9y6IM7fO2/vUASVr4NB/u399/waa8Tp3/xz4Zv9bjKQLgmJ9ZNkf+PumyR6/cbct//3/HLtyTDPcP+KWAD3zboP+0UUsNnPT4zb/if02UqUPh/mIpiMmS/J/nuD89pG/AXPv8i99b/kBxRvbfyn+k9v9v5/1TUvXqlji8Yy/b/xKyE/asPLTzX94wx/dWgddfyahLXscDzlhG194DXW3Dv8HgEN7Hv9rfy5XBD1bfyOhc3txwxb/XiFxVxFXd39p/3q1UK9J/x+UE7VxlT9/QmgbtSjeEADg/xgZFqtt/xSwaHETwz9/Q/82X23/STAPyTavbf9/2SXtCPt0/1UkTMMt70bwTfJhrwyObBcKoCzARh1Ad3MgBfRFVUP7Fv90glZOEp8q/08VOlkvGUN/IU4vJXAdBQCu4Vb7Pj8XWgUGSnE0zSr/ZM5vTT8bAwDysHRFYQVZ/3qcLCtdZVH7GQD6TgMdYncV7AxQCqUx9xUkd7YuBRUFCgx6hHjDch1Z/2T8D6VLXyD/FZEAWUkdQScVJDEyGC5SjUN/VIZqXy/JTFQRQx4VJPdMVGCsO1lsn2EAlWIxqGy9U6tPAIEyetsjrwuWdasW2w1/cecmmSgtImdzIGSAy5Msb1sA0QCp+UxUSQCW2Tn5GQDAbnmpUm8NAJCJRZldqxb/VQDSkzjfDQDi83l/HQDzDhotGQDn9mQTCbU6gJlKUP9Tl0JUBo4mdUN/ETVWjzFvGQCWaHotTudXAJfcT040/yr/EYp6UFBrHhcVJElVXP9R5xD3QyhNAIGA5ml97EGrIP9MxHxYMC0ugMthVG8h+QykF2EbwwN/LoDAtiXjIdsW/zPsadk5d2+A6Ahck1SPDKQTIVBuD+NDf1g1XI8q/0G4BFtCj3+Aiw5akxc9KED10grXHZlZ/1ghFIgFvSpXQygqjiwPGyFrgI+A4mtvXmeA5alfuST/DahtES93OW8ugOJQMFFB5xUArWhYhzVvTftTgP6Aw2trgODAGBl9/TnnQyh5dkg7ZydDKEoUCxM15y6Ao008a3SHd4C7wEJA6YDoYHKOMp1wQN4gbjMCOyKvfVJEbzdxNECtmmU+Pgkg/2hAky10T2BAoBcfqQkJbUD10gHueANS52gsPCBDbSUJa4CLT2NLFPEFAIJAhhcBQNIIGBcxhwUAv0pKv0QXFQCjXECtSgNngI+QADAlhzSAmmNTax0DZ4COQO9LdgMFAM+yFU8zO2JA8H8rO2uAqbZaFxUAx0CvnW1AkHY5A171bUCAQOindUD77HinAADakBT2W6dwQMBLYPY1h31A+EDF9SphYEDkQKkXd8dwQLwga5UWYVn/f2AeUA5hduB8QMlAonlvZ2dA+htwJ20XLoCNtj0XButwwMyAIxcrEGuAhkCzFzwUJ2cWQNJ3OoNw4W9ApRU+XVEnHkDVQRANdUVrgLQUEFsUsWlAl4DBv2thUICl0B7AjkcmwN8kF+VysGlAtTxlGXRtPsDLYBB2SJdoezLAw2AqWU0mMsDN2DgedWEcwOrAzek94XBA4TBuMx8Ne3UoQPToZWVGpC2aG0CTDTddCgCnUiQVb10iwPgocmMan3JAnNNHu3ZA/URf60I3U4Du034fDKcFwPPpZuFmQKrnRcD2SSKA6JMT1WHPDcCIINWzFQDBQPwrBR8FANFA5R8p4W7AhCDGmzAg2+dXg1orKEDEhCx7VcxtQIx+TSkJJQoAgt19Gw6wWcAHwJ1Aq7c2lyrAw4tg4yVAMoDqDnQLK2NpIMtAzyl8XzbA20CF3R/nQyg0wK8fYkCXQMsla4CPQM0reGdDKB9A0J86N1wgwMDxeyifEiCQwIlnfADLINXAuXsDwJjA6y9le3jAyOhA80knQyhkwKaeWKsHQLPAwyCLQLcUcyl3L31A4/0lCyYRISCCwNyraP8IQOnDHhFPwJhAvACJT3kg2j5S8yxAlSDCPQkRDMD5sHjeaslngJxAr1FFEVTA0KC8n37AyytBW2HAmLUurzQXSyCsIN4A6cC8IMEAwBl/QNZAqn9XIMuAhJ8VAM8gpOMDwIeA+l8AoJkrIvsJQKQVJq9gQMzA3zl8twaxGKCnwF5fFUD0lxFRYn8oQMmpLj8hIK/A2J8GsT/AxvcZX0ixC981D2+A5sCsuRVfbECwthH7XNd9IKqggZ82wJJA8E9yQJB2SfdqQInAunc2oMWgnQU0gJkg84DEOGWraiERBWBAg/B4dX65IkDoLCFBYbl3XQykSpBnDzPjdydt+C9eeakLIIPiFEpqqW2RGGCYGDnbR/cW/w9oDblMj0N/CKAduWXbEKdt+F0wX5MsgO34Sq5kRQ2ZXGCjMWu5O30YYNbBAecHuQfA9E4p+yBRPSCJVWCA1ucIYKBoB9ttQPtcQHlf2W+A0y5P+TAJU8d9UkK7J5RoCR+g8sDHj2gsFIJw3RIHZSCjsCjFY65V9whgxSw7eSz9QmCVgOhxSj9EYIyApgDCYIxQRg9pAKr/GTV+PSEPMmC+jXKfdaCYYIV3d0FRXzJgmoDdoIYDLr5ZUQ/7GGD6YJOgy2DmYOVfFNlCYPVKMF1OfyNg4ICjDz5g+RF82TD/aCwhYIr5aE8oQLFgqZ9tP2+AxDUF9wcPEPcTSTWnGj9vihchWlNS/w1GBswuHTtfeOoYnmVgsvddxDcoeSJUuQf7KuDWEgt9WJ8NRiFBF48m92zGVHYe+3S5OMRvimqKLVEVX27gOW4fT05/bODFjiMPcqwq0TgHMP850hLadT8j+znSM+0bDzngy+BHnz0/Z8dgKWBKR4850hPfSH8iZwSJCgdMl3KsUdhgcV1g7uCW/mC/b1M0gNHxcSEVkyD/YtsEb053Fv97MArJM1db4MoxFYUPwzTUZcMxdyTTNNR9OWRgooDhhkeZW/cIEFXMB/dsLUN/DmVexzUHIP9XdkAeLXddOQykTQlILUZvFv8SwzeZIFMYELhTdEUwU2lAlmpyzRMSFGC0YXDqXtNb4L/gwdNX4O9NX7l0DxgmZFlZb2hXR+DibArXf3dDfxyOQDgqEyrXE4CaAC82ZpUZdTTUXtct03g5NNRbLFf9WktX4JMBcW4ZIxYQ299rIQpPR+CyEJpPGBCudnJrQqcQEJ1UVk8V0Sr/SBCbfS5PGBCRzj39fk8IENr2IWU9QIgQNeMN1wfAm4Bk/HAzGADvmED2FvVDZhgQvo0ZnVPXFhD5EOPzfyDmUHC6RZ1QowYQgI12aEfXFhCtpjADV9db4NHXcu8rX3rUbhC67wYQlW5G7wfAhFQYI0d2AMs01FI8ZQMvPk/gvmh1x17vTdp7MX4zDxC1vlXzeMtNENzcGQlMxVAgxBCQKSIXae9UEKKuOe9dEMPOaJDikLMQijdRo1QQhN4HlTLLRRDE0F3vfYDmCTh1ZvYj7yr/ff0hWV2lCgDztl3DJJRL7xoQ1yc82wgAjUBbvgfveJDOJGGdIcsDP0iQnvY4eX7PGCZYkNWfIoCEkP0DTZ961D0hXL5VpSkQm1dwH1cQ3JDRu1QQpRDFv0QQ6tJobW3PAeBF6AsDM8tDELG9I89o/yQQpuEtkIEjbPNkYyAlRBCE3kZbMCUIEIbMc+knz1QQpxCgP1ofHJDG4PC3R+CjTQggj78aEJ/lDCDAkIdOQR4xs0fg0dcCDljdS+CokMsfPhCdkPEfPZDbLBC1cHsxENnNWv8XwMfgp1t8KzYgy5D4UKfrMFCG8mIvcQD9YDPFADUbIPewFmhqL19fTRC43HURSSCTwO+QsBsYEPcxHeEBKwAQhN5uM1YbXBD2FX+zcGC+kNsrKI0+lzhQoVlEq2j/c7ZLOBMglhDTd3seIJ8GEP4CGMkVLxxQ1K4hTQcgzhCxUN/XCgC/P1zlJ09NEITwOjM3T1Pg5sNbx3SQhglPqHNpCMsl4PG4CNF45VoHIPQ0rRvRIpD46iWwdDlp7kDXbuptEX4+AXM14IA8UElX81FzJeCXLA3g21CE0KPsI3gRo1s/euCQdlXwTQtYgO8JAcC+9jblP1C4KDvZLuVRJwEJPUBrkLzQ+ypK0KmQ/8ImJRvvS3MIEM+QJG1RN3qQs9FVkMFQhpD7e1QQgAER0RmvGBCE8HCBf/9M0PtYSlVgAMzQn6gMC0A9HA8a0IjRLVDM0NyVSKCjr0fsGlEhw13gy+BBcHTzdhEE0Ls5ND0xqEEndeD+PglXcNDG8H0bHKDvZzOJWwcZJwaLP1DEsAKvCMkSoIYsOp5bQwqgt1C37jbzXfspCT6mBckQ+0QQpExGoIAQm0Rb+Rj7FRD8Zg/KDqCnZzPQze47Ty3gpj949kXzQ9DGbi6tNfNeJ0PgoqCwxRIvU+Dm9WcQ9gtu6ks4Xocgzzzg0MFI3yXgi1BJhxELXoCy4NdSXMVqMITQxIUSEVXuX69q4KuQjNCqMNgKSxVZc3anbMZ0XSx2ItDMpD1RUtDu5kPQ7blmYRrfeuDSiUWOUZDD0IfIXL5L72ng4NxW0I9feeDV5Wn2Pt98MNYhQgtZ5mwXDjDmUKzfP9cfOk/yJGEqCyDQx/VoM0ww5jCEMFzlctBUxXjqZIRQ5Q92Zadf6WIrQNCE0MsAn096oy8w7tNprW5zLzD/oQDQpN9T4IIQKe1/4hTQsLDpg2brbN9kkhikbEda5S8wlq5KeSEw05dKqX7FKstxMKXg0vAjAJgLbuUcsLhSTb8933rgkep5pUmQ3jcy4O6+aokJ5WYw3bMH734w1hJ0uAgeDwtN+0MwzVCXr1MwghA0EUswnekQtUk1SSc0qBnNQPNq0LDDf54goK6+LzCisMOxJlccsKdSEhE+wz8w/Zh+EWTzILDXaB7JA9CcsILMBKtiiyCw/RhnIMyg+LD5uQivKlc6qRqhGK9H0LCwiEhsoNfQxrC8PRUpZvNCsP7QjH9SsJF+cIF0XgCFKrDkWSPJNmc6sKpGfe01EGYwwL4LJxmLODDrwlrQhYsA03rg6op2zENXR+9tqSKbGEFd43jqK7k6EytXU+DFMOjnM+Mf4P9pbBFagLrMOW5e9lv3dIZgmm2TJQcE0L8xAFdIASAHdIZesE9nH+Nb0NOwDZD5fxJw1Ld/iwTQsMkLj0vxWNcl4OQRFb0W90awlt0R03PeDnDOVDZFQdc6zB+odFNc1yype7MMSy8w29YJK1LXILCPqCxRYPcDPwEpfbC61yypCyBvb2FuDnDknRpLF7YOcKSjOa5O115wigAz3lkQ+uCIP3FwzBMUcMJw3ktCpxJwmRF1EItnWnDXaCvnIyNT4IJNUjMDEJ9wwlDhTwpwgxFc7mVLDHCvJDVLCDMMcNB4XocHEN5wtdCT12k+UXC8cIHvXnCAxkNtMr9ZcPn/QvFDTxywriQ4CRCQrbDSeSa/K082sPBwgNDEMOaGWHD0q2yjFHCgFCzA5JDJcNDBCDccERRw8rZwy17vXHD00PcQyzD2wKL1MM8fcL0YAN8oz3jqPzEE7Xj2apD64K6ZDOVsywDw5nCuMMHwtnCWkMI3OsxgHkwxfM8bcO6KOmEmNxRw1PAcOXLPG3CxcOzras9JcOZg4utLMMywRuI1MLcwsfAhKGrrds9NcIAbRfZX7w1w8vD26yO/HXDq8K9EYc90ym9+U741Nybwuplh62XLDHDLcIuQjHCj8LrQh3C6nnnreB8XcLjZRFtT0NOwT3D5uyXg33DQ4Uc3KfDA8IJbD/CVIIeuWzAtu15wsxBDu1BQ6PCWiCvreGcKmUk5YLc3zy7w7UdOIJRwqXCotwVwuXD0ULCwxXDsIKwwk1BVcIgvAzC38PFQvPDdcOolQXC6JTogjHDHJkYg2lCbcIfIcN1dsx3Q23D5OURfAnD93i7/bR9B8PodBitjbVHwpTB0hTx7APDXoTMfNAjsCPIg4PCl8MUgwycUcNIwMd1RKw5w0fZvsz3nKgjNB0MlGnDKXBTwwyDT8Nx4PVCMcPVFPbdKCNvwzLDg4zNQ6HCUxRyNCXss4MN5LnDMrwTQmkp8oKAwipAVmF2PLgD64I3nYNFkV1j7U+DWhSs2WDCl4LHZQidOsMHrXpNT5nLDZIjQ7AirbyD9QAD1XZ4g83rg3CFew02veOoYuRm1WbDT4Mk5LvJ4AJaIiM4KnjOvJeCm4G98flcb8OKNbbUHr1Pgqbl00XyIoNMstVXDaIjjzQuw9jCTomJsRK8E3miIu61P0MelPgjciOWTLID4iMKhK4CciNKIu4CaiMqI7X8WiP6qDfcIdUawxoiFqwuIoXRs50JvHojOiJt/DoigvwzneuDBiK0HeOpRiJDXSzCJiIurSn4GiOWMF7lxgJ1iYmwHq1rnFoi7rRerMZc2OUiI1ucKiNAQUkCudRTqX1NKQPE5JEiy2z2A9LDAUA5eEedX/xTqCjEmPiA7HIju0ylLYkVLMJyMeEVyRRXwjD9Dty+2M29oiP6qQn4vYAZFHoivyCt3Tz8dYkAMEa5nb2iIriR3aXdvG/DeiMiHBmsl4OKNCJUWay4Iz4iOa3Uw2jM74CY7JAiVCWlPPb9oiJEmbjtxD0zgRyM47ilrFkiTrwYXOEiwA1gXIkiVrgQXWTsMiJJBX0C0FwqQBm5TQL1rDIj8SOrvMvCNiMenJEidiLqtLYcMiP2I2s0/CWiIo4ivJxEvN0A4UxwDM4cWiNZIiBduzQaIm4iUNwinfUAHiNi+AOsniL6IsfVwMQ+I+yoi5VhdEUjAVD4DSsDoyPxzOYkouxaImWwlMLi7Hoj/ZUY3Kc0eiPC6BNsc62iIkMioCLhIzA0+9mGiFwiEjHsqVtDJp3iIpZEbc3K7HIiEr1O5aNUAX0tIpYgKwJbrdYi7SM/vBND7lUKI3+9GsPJI7Okuu29I5q5NNxAImojTiN03CesGiJrIzjcWiIjIu5DoyM1tRAieSOeIszF9z3e5PTZPkITQyUixyPuInMiAUJ3QmiQ+aB83YsiFiIazC4iViNfPC4iNyIRQw4jE0BF5KD8kSO9IDF8v6yJIyKRuHy4IzIigyXS3MHDHSKJQ7YjCiO5jccizblqxAWN5yPGgxBspCIaIxzIKsRUfbUjIiMQg5Uj2WVUIwHddyJdhblCLiPPOVMcyGxGI+yph6RFQ88iMyKdHOSDsyNlImx8eiKG5TSCbCMfIvoROGyJA9Ui18lkrbCimiN2vPUjfH3P/eIijSPMg6cizSOsg6cirSNGxIysHSNHIqn8YKPDVSID3SNlkIaD5yKD2el9/SMVYBo1rjnXInUjc4JOibV0Qd3uIvcjwd0Zw3ojS9wqfV4iUyOqfFwiLyMUomUiQtU77fMiFLHR3CMEtyJBIzp9liKIdWile42DIgyiFPxaI7qRvVXgHUSiViyNfICjb1g+g7sjsSPnjPgiHKOYvEUj/+xYrPPcm8iu8YpsStwtydfdytwlItDkefjLdEUjWrWazJQjmCXUUU4Nu/1PgpERc3AA1GXCjgAxRcSVBph3QiskWiCmxO24E0JgUUQ8Z/w6o7WBdCIwsKEif1m7BEp5C7g6owtNVm3PIlMVgczAJc8jiqOcvEUjIQk0gvx9XiP1EG31Tmw+I8cobJTv/Sij+9kf/WiihcHoo3jVwiM6o5lln3yGAVUVsbT6/DqjPF3nrJd8OqL0tdb4AD2fHBflv1CIed5Uj+1YFdwlNyN3EGihXyIw5a58aKAEtDLMz3yeosVAobnOVCFUQaIPvFVkgFUho+zAeOWffAGi/C1O/d6iTEQUNeBVIaK6wLm1bvzjEGihVJCK3bJ1Tlw+oo0cGCKGAF5BxYw+/M6iBGFLhBlUOqLo4XzF/vw6o7018INBvQ2xAqNtfIq8aKCIyCSt2B0WbHQIvLjteKyFPsOcmPwUwxT1bFGjHcgL/X3YT3UJo5wUkjgYXdZRADFXzCKduRE9ae1tRzW+otpheUHj2TGEQaKplSK1PW11orFNR7krA7kQgBVzI5GtxaIxRWLtBzhBo3bcZCVr2VUFbaN+nNLtS/2nFOWivqL5o/qp+Pjy7IAdOaIsOB80g4JxohCNq+TK7RU9DbCqfZ/UK22wXPQQUvyO5XWi48EHbPO5vZ1SFJW51f11omUERq1KA3WiXkAapCOddaKB4PoFL9x0COPBFz1v3SWAl6CEhFOcQaLMycC8Hf2rozJUWIVd/YuiFKLdncujQU1ZvIOiSeEUdQP8UaN4gNXQpgOronf9G5xRor7IuqLNxPecWhUv5TucvSFfHQGsStyJgZ94P2x4XI/gDn1/bJ2cY6PRFXEUPXyJgXxgyhzA7EejbwLiVZLcWhVx2ODtykIKFDDUrb19oj+A1PBvbIkDegh3IWy0BUOLo5k1jzhprXuiuHFIzH28ZaLc9WwlxSProwcipSKJnNujQ8N5rXujH8UihQWtgGKZYF4h7EJ47TuiAwK9rATtr6NHotMttpyDoyfZ98GFpGWiGzCTQjT4vQIwYiK0hoT9AleiNGyloG0iNaJl2Tejidmjom/hY6PKJeycd6OeOePYowJ0CdGgHlVuddOiw1UTAkeic6O1FIMjKGILoxzswyIfojK9tx2roiujnPi87DWia6O5o7hcf6Iboj4cAGM+ohhiMpxAY82jaB0lgFoYOkIrCX29egl6wCl0daN7o2kt1virIkeihGKgIyej8pxQLRsj46O75Vsj2pwXoqwDhci7IjBi/ZjyjartBJw3o42jhyM37bxiuvyYY3sslNwPo1OiFpVEnE+isyBAfXhjQEGZhY582GIsYj2jRGMVzBesP6NYOU99awPLo4pw9zz9PKtAfDjPI3uiFKJwI8+d1GJvI6ujKEQt+GrNlp16CaednyMHo4yjfyzfPakhb6LA/NhicIy6DX8iEZlk3TF82GLEiCCDsUMoY9hFNWSAbEPd/GKJQwJj7HmHPFOj41WwrMZcT6MXFAitomOrQVBtoGNQYz88Apwfo3NseILUImRiecT0fLQjMmPDdPQiZGI1wBMkaKIKYwBixmM9Lbw5pULKY4H57H2roxe5Ge3vo9vY7kjcfPpcmmLHo6ACUGMSwC35DmxHo/F05sSNQyhiiGKkow2iOzV2o2hiqGP0vfADxmO//EJiJNQ/dLhjImLV7aoi2GL4Y8ACqmJvoz5iV0N7o/Jo3LyOvcui0mKQAgVdMmNroq690AOOYvJiUoOeY98U8iJhYq5ine3AYsW4dEXIAh5iamIBvJYjjGPqYuF4cWwwYhJiXsNaY2VCu8xwY72xlESSInpilsGtndIiBmKzXWDDIWKNox49YWP6gjBi1PH3gnBiM6I4VIJ00WJiYkxs+WOaYmj8kmJL9V2i76SJY8yiJGKyY6Hdm6KpYyuNr6NpY9H0+PxKYxvdeJy0Y/3I1UTafTui2QEr3bHcuWMrhMJt4mP1YoKjKGMF9afsw/xnojx0PAIXo398fALBY4yh4qLWuL0A+ph+RE7wwKWh/G+4xTjRhM9VnP098bt4YpDtfTsE+U0beBoV1oPzYwbgc2LUuOD4IziAQkGgBU2c/SyBZgQEURPk+fz9yRoETgSMVH14bfgGUMU5m7kDo9tiOLiGpLBQKfQTY59Cu2LcoqL4NlAQNZaAZ9lFeBBhw50MkCeMCQSh8aRNkIhONOoR4rhzYhLYDXi/RNRCqqCdbLRkpP15hMU4vLQW+dpwYQORgZlVRXjDTHdkBGCT3LooGUFQtSwsOEIzeQcAECORafcwVQQAZNgBkWmwUGU0LnytnT9j84FEQuEFsIWggE+gDhyi+M+YVoBPoMBR2QQcjTeAoOK5LOoRaaFIhUDjGTx0KCYdiLWRac7YlyVXYunBpyC/Y73CfXlIUOjh/2LMcanl6QVMAkjiKGRbefasOEGRaIyYA3jco5hIm1AjkOt4h0JwaJtQChmo4kzt04A44pPCxQS1BEjiK0IwdAGIx62Y4nxCfXhVcIyZKOM3yD+EwulhwEGA6OJLvaUE8fliuZFo/4nmfHQp8wBfY65QVM004kaJg7ibUQYAN3l/Y4AFsACbUMjFwOKxKPDiJIFEtJEEU0D7ADjjfUIJBWDjBOPrEYTjMIDQrcziikLQ4ly4UUSbUYn5QILQ4od4muEM4yfCguL2RMMAm1BoOKL4t2PY4nTiZ8x84nMUSOMoRVpDCONYnHjiPjh7rRDjQaEi4jHImNzQ41fAWCgvgEnhW9mc4gTizONWONaMAYiGtCrjgaVNzaUFCiwy4tEs20Ia408ZkuLNBYt4lAFjzYriEiGX2Un4tONzBb6gErygBWJshdBI43wgsuMBQP9jauLmlOt5JAJJeYri/Il35PVR/YGS4895S/ipeDz5FuKq4zCA02Jm4vkQNuI5eDDjTpxN5HDiEVHG4kxJ0QWauZKBvqGVjVjiP0JUAIbiO617EJLjauOHyTzc0OMxyODjvpDqxTdjPsnngb6hVHVJBEzsSOP07ELc0OJc42riJGBJjETjcuMykN+tbwHJIErguxkAo1ri6UnG4uFN8vhZfHalvqHrlFmNNOKsOEDi6wEkwBbEwug/YqHiAiAW+X6giuJNnJCigOMakUHibqVWBKNQsugvgWHASmyFfcri2eJVxP7i+F1B4hzDqOIeAQbisZ3BNKkEAwKa4smwBUPC4rZpQeN7ZK7iKOKh4knjSQQiRBziizEMnT7iFdxI42ihrY2xBT7I/OLKAVkp0QWEwefFFsD2RVjjIeNN4rsMtOBg4LXjeHh9jRHjqGWs4z94BQUbiJz1pmiCIgniWqVV4jtIrUKfYgbiqIUDUCU89OPJ4xbA1dDC1X9jJ+Vq4+U5uiV44YDiteMxqdziIOK14lh1N2It4+YAreN24v7x4+PcvHzjk/CJ49sNvL3pBXDiteN4hTdjruMKpc844k3I47diuoED4hjiVePTYnf4NuK+49NiT3QarbLj6+SqoCN57eKVEZtscpF5YwjjIeNr4vBRxfgYDRv9WFhD7TTikeLnBCR57Kz04wHtG+OHzZTiF+EbeOlIRr1J+WLjHuI9gan5N2Lm5b3jBmiNXdtioXid4g/Bdky6KddIT+NyYH2t0/F3JEjiBcmoLIdiWiVq45q4BXhTHZDjI4COFLNir8Of4kYpzAXVIYp54xiMmEbi+pBN4j2AkwwNeStiFOO3406tOwSIrHWAT6F5pA14j8QywEjiZUTwBaH8ajjh4j7AEE0g+GyRErFQEoShMfkf45KF4OP6TZ9ZhPia47uZ5QRnYvuwT6GgnA+UpPx+UVASdK3u4w0NUBIiuR9iqwTD4qATMCyhwzsF4Mzv4jnUovgrJBeD4xnmwOoElKDtueATI4GCPKsE4DHLAeMZwcgrY87ZheIrNfcEHuzEEo4VrQRmQmcY8k1vBHT5BBLf3S8FyKlQE8ASgoS546ATFqVwqb0h8+Oo6d0dvwRtgLfiYgGQiPmEZ31q47AT5QR8uOFICBPOBKsEVBNsElXIuAQJtSgTE7GzBYhweBMbicZN+BPwgJwThDlKBW9YtzXcE4iZCgUgEw9j+hD3Y2xCbbiXwD4CK2PrMHm4z2MoHKsF24F/Na9iOPn/Cab0u+Lj8Z19MIX8E9NiR+NUREHiu+KzcDWFAzBmQo1ob0DuJB0EDBJ3Y/zDVESD2SX1FbjF5J8FbiN3YloSpIJnlF0Y6f1wRe9t3WCFBNtiSun5gcB5sxEdVTsE9AnCPO/tPBNqE91hR2LjBCvB73mzEaf1OwXa1QqlI2WzVJSgUaELo5dizhJ/WPBil8A3Y/T9cEQywLbjt+MWLErotOPz4wZovDz1hWXxvuL9gLy5jYQ7vZ/iBuiIRAP07+KUE1aFt2MUEyJFtG00E9C1uoSc1HgSIrlSPbqFWXjh4gINdfQJhPYTTBLKTFETh2PcExSxlmWqhHOUIhMQE3SEbJEg4vCYqjwXhEaIAhLaTNOFQEGhBKDjfBM/hSESxLi5LKpEf1xPoUIStETwUVAToJzv9SWF5O2YE4Y9LwWORSgTkhJbhSxERhPSEloT3hMPYnISMEQFOXch7BJ+hFtx02KWwMeE8FAq9PbwtjxZEx8MRuHZRP2QEzG7eDNiLMWqhWsVD2I6EyJFURPlEsLkURKxEndjy2N4RJ/ijWhlEiOFkC09GKYTuoW+rbt5W2OYRLMhZBwf4FYSX4WIQ5aAyYHkuJ38a+NgMGn0SuguUAQcOuL2hO5JK6LnYkX9bEQqnT0ZU4MeE4iY5wRMBTm5cUVguEgSsgDfYolESYUo479jyUXxYLATz9lSlOQI8BNQEsDi5kV3AggTrcMcKIICf7lIEgO4OUT9SesTUOPKA8x1KOKw4w5Ff0ya4mj0DNQqgVSoKRNI4z/EuSVUEqjieUStqX4S0gCD4lewOgCa453Io8IGRCR4//g44uPDIUR2PX4TBIBlZA4Df0Vc41DM5AkoUQTjMDzhRbdAnBPolSpFk8mfg2riBywixK/NU+jU40vCVYTAYF0TkYFm2HVFW2R4EsdgCV3WRJd8muLOg01FQeTh4/moy81bEicSneMBUaoSBkRH3ACScVh1RPQJOTkWwBCFDkSOOTIhFsE4kMcTFRgowqPjS+NeRGhVxoXaQYYidkUJ49NjQwC3hRdtPZx1FLRkVxIaXLvi2+PpRGxIK+NeKH2MwgL244fj6AMhRJCS6hLApc8TjsNr4ohMwtVoad9oA+NVBSHVEpGh4xfjpWJREjwQTRPXJBu0ekW/E55BvBRbhNuAoEOTYw0T7jglgVvj6EMFxT7UZFF3tIrFgmlX4xAFo0RiHJUTuJgyxDXhkxJLaaFlsQNOkScSx2DwnC0C72Pj4wslqsVIUSCSwyRthBrErEkt4k0iX0SiqNySg9lUk2vQa0Hj4zmdx0X6UOCSrNnEkr0Q5oDgkoyBbIR72UWwu+KwoWHE9iVftWvjfxKQxDsCu+PhYbokIYNIUWYEVrhntE9FZZyVEpTAlyUVgs8kX/n74jTj9IJ7LVASd+NTRVyTBBI3jLNEjHjv4yrVsMQGUBg4xBMRBOtFP8lZ4rsBbLGoLfVJwpLBEjrECyMRE9cFYMXa0O/iRimMRdOVjuMVhItNLMXJcPzYT6CTDCyFpTQ0eGNIYBL0xYqSEBIwQmdFAiVQE5AwQS2gsOhwbBCg44iNV0UZEsS4EUzCk3scOxOkxIBR2di5E3BNsQLYYWwT6BIyxX1BCxOa+QlNPsWo6WwSOBIidNqT8jifE4sTfsW6kp8TyxJLRflZ6xMA4rNEKVGreUDjJEKzRRm42dCg4lsTZpK+ktkT+kwekmpUexI2k1aSnxMHEodFtEXz40cSZsUQ1OHjldjI4iDEMsCd4ucTx0Quk1U5lxLhsesRLxN3XGqSgAVc43cT80VCGJwTDxLZVUmTEjA44s8TqDkW4MTjn4WS2LI4nxJk42yE6Vk5XRTiiM0lxFqNKOPU45Ml4ZMPBaSxdOJck60xauJpEjd5PJL4LcziAyxPRNpBCRXM4jjMT0U+yScSnDhjFOWSPZLc4n1Fc1R4E9NIRM17RWpFtxInMce9scU3yAOTeIBQdRGC+aADk6LiJsVftM2SEuPOkpixiuIPwd3Fic2S4gbJesVr0Rc1s5Py4xWCc6zW4wZCT0WMMeWTKuO3LSLFuDmK4hzNV4TO+fPirDgFEhuwV5na423MMamyrJ3iWiG7PT8StwlNkxGIO6wtkxfRs2kWzW2TveNm43yS+Exm4pbjIcUrVX4SfojvRbSSK5NPmKuTopODAZLiDuKQxK4RkuITsDWFNpPz41SlcpJ72f9U3uLu4xOSTpIHkqd9FsT5kx0MPuPKkhO1AeNIfT9FPsl+E7Whv/kak/ASoeJI5VrNvZMZ4pCVHZJy48bi4aF1FQGSmPxR4wbNzJKy4DHi3uw7k6GTxuLx43jEHJO94zoBj0SHkycToEjPVTySe3zZ46Z1fJOwURni6/3zRXXDfhPZ41Alf5K/k/+TKZNU4k2dKqPRxBKTQePUUeJ5EYNSk0HiWHQykkE0SFNFIVBS8pIvk0upuFIs4tyTWSHwk4nNnhPfDJA4HpMVUJwTedx/VRqTPfGT4200s0XLkiKTojQAUjYlFsHROJhS1ZK2k+1gZGWxAupoteLX5ayS4FKh486AJnhNk5BSleMQU9qSd2LdEorEUZKNaTqEOsQxkpoSOwUixUxQTRIjQ2eShgMqEnxFyFOH4oSS15P+2M9i/OT0xbeSd2I6EhmSAwNtExZtdpNZkw9i1Lj/RcS4AnnMHAVNU5IFOBtjucTbYDw9QpHpxAAFtfW7YmOTbMFMxMMT/KM+ksiSsFBjEyLFVzwOEmfsMans/F/5ThNFxX1ABhO1JCh1boJqondiN2NlxJJSneIe2C1Bm0RfCBQSa2kV+aeEOy1ROYrj8REghbfg1gi7k0dEMpJf9OHifomNxb5Z55KUVRvEA/h4Ev+J1zw8KVnRNlN3kqaErPxAObNoIaLbxQbg4eN/QAfiPCnZkpwSVkSvk6zojlOBGUlsTQQiuNs5H5MxVNvE9QHBkt+S8VUsxK2j0FJI5ZltLMXcuG7i6wB54zPEcMMB4qD9LMVUpUIRwFNVk7uZP32+oTHj2FOIxeBSpsw7RHpTxuOG4uGSKzUFGJ7i7lJOiGYSR5IxBW3EEwRQiCZTbqO7xApU1uMeokfFij1WUt6iJ8WMofuSV5JnretRQhiLgCZTjpUcKMcQzLh3k4GiR8XJhXpSTEisJYE5xlLdKJUjBVLmkt7jsVOvxMQkmuPe4y+kjkPhsA+SadSsJeFhVBO+U/vFtGJIUgFSnITDgBGTueMoUwe4AeJ+4qFSIKDSeG5T9mGSkr7EQTiRUnlBSYQ14MMk0VPoVXFECCDJk9ICCVK5ZMSk3uJgOA+UB4CIuRZTgE02hNhgp80W42lSTQTeIMHNFuMZU82FXdiTkyuS2VNhqbwT9uO5UhgkoGCcEhVgkW1JJLytJxMPkv+U2CUC+G5TlYwOJCTYQVM9UnGlcB2GiDHinlNzJQWsblLVUhAkmSIbU7Gi41JlsCKlueOA/J2phDl4U6HizFNMtGJ9IVLfrAeAC4FoEisYaaI0JewUblMx40mF4oVo40DpifilbFMky1N+E1JD4ngYsNdgnBIP4tK5vCStHIESb/kGJL9FeFNx4O4dH7ATeLdTppOdZNWg8VKmk1UltGMv4o4Vu4ClhX4SkRKIpZ50D3mf4oAStSX9yOLiA1EDXHokkFI6kmASn1PJYLATFOGJ5fI9d5C5EltMXiRmEfXivRBekmsk17lfkJkSrOWvUt8JvpJ3JNTF/pMdJf0F0MDoEwtcqSRp7dwSWBLpJEc5vePuVahM/mR8PctSeZKfJTdSyxP1wwYkT0KrErGTvyU3+esT8ZNzJBPByVLEuFsTZSQzNAgSuSwSJbt9qZNVJZ9SBxLZPF4kSq2945mS/iWeXSjjSVm7ZPGdDVKLE7f0QNMCXJ8T6OO9JclwtpPXEgO4nSU6nHcSPIyQ0wRo4eJlkrUk2Vmlk32SsNLsBFWSmaSgk3hS7xIc0waTKOL1OW+lW2QAErIAjZM+pGjSDxJquQaMN1L9dQzjAN2Y0r8g1xIs4gMkZ2ME42zj/yT5AVzinOJrJKzTTxJPzETTuYS84oOSayTt4g8SAuO/UysdBOOjkpmkFuEwNKLikzxrJQDSrZIC0q9S9ITs0jPZKNxeJebDFlJzku9S4iC7kqpAXqS9QGelp5NLkgTSb1NZU51kAwKPxbOTeNxTJcYTFlK9JXklV6FUE5M5tGjI0+sxkuN64tRk/NKxUjusgtJOAYlS6gV3Uv6SoIC5EIUlgrl5QcNSlyJTJHjTNlPW46ilBNOnktaMRNKxbVNTtlKfUj7x+VNj5bUkP1OOUoClsiQU00+TsH3K06xT8VMrUj3RNNKRUwgiGtLAJBtSn5MbJERQ81KB4jElBGn+U++tcSQu0o1SSY0JJbDSzVLfrBiwjBm94rkQIFKfJaFBX5ORUsjSGeLe4hBS7yRXU0Hj+cBc0hjSKeL85XdTeNIKdIslljB4EzIAhsm40nwkv5MKo+HS+tL7UjcllE3542hSeiQp5CXjGFI3JeKtWFJovaTSTqHQUrhSitIq0tnjydItJAHSRynFLYHTJOVt4t25gSUB2BbiDePHKIrSz82946TByWXQ0qRTIpKBpeGCAJI0UybSMdK14tNE4yXmwURTqBSTtbilyNNB40xTeSVJ0xXjzSRJ0lZTqJKipXMkruXW0+WA+jmmJMahadJmJLrUAiQZ0+PiyyVJJZMxh5PT40KT7iQR0+YAVFJE0+U0MJLik7Ck9TC14pKSgaWe00OTLkHW1ADSJdPTYnKShyWsUgqSfdP500DTG+PYLHol1wQ4klKlwdOMMVvioXmh014o6hPhec7SqcJitZF5CSXKgQySD5XR04ycu+LGvE8l8nmSuahxFKUGJJXYiQVx/JdTuCV0eGxSBUzW0nMTHFKD0tlRGgWVEk3S+Fwr4zxSJSTHoZqSqhOBJZLTKhLApa7T7/j6Qs9V7tLaI8JSejWk0l9x62P8w+TTilI+UEY1pNLL0lJSTeQ005BCMlLqJeK4u2JikN9S9QE6nSdjapVM0uPwR2NKUhPSu9IBIt7lX/hbYqdiDyTaeHdikkHJZZsDtRKuEhzSldlnY3MS1GWkBfUT6hPOpPiA6pMn4sBlsIRNE6STJaWrbCfS31O0uJAENgRGvdSkLxK74miSi6TFVEviAqxKpd6VfhOj4gWl5Tyj4hPjnWTx+JyJk+OCgq+kUsWT4rsN7GT5Xfgyc+OcZU1SC+OQA6KlSiD104iSwqRaIZqSZZGU0pkNQQI0koPisUmwUDfSm+O3pBDhmpNYkqOlPfA30ziSBaRlkEoToEjTecukfLCA08pk9HXQgwATlfygZEGEX1PyebmlBAQ+E1yNs1SspYQzn+NssSHUBKXEM4IzImUsCAaTH1JSTeQzX1O6pfhV9+K/U2al1DOxE3oClqUrKSgSCROdZPTZ3MWYE338fKU4kHCS8Jg+ZPRh51JiAXm8NaRsMrASyazspcIymRK+5OqktlNukqW9ZGXcuJ3jG4gAFMBlPaFsEztgXqW0uKMgT6EvHV/8NaUcMxGTQ720ZVwysgHPlQQy6aSrEqDtwaS1oesS6SJEpGhx/dK9EZDs6jITIhoytDLr2WwTgril4uQzhQUw48DDRqVEPfDjSOwyMwJhuZOTNMJlMjMo4rZpcg30MvIytNMjvQoznJDXEwPdzDIiwS8TE71iZW/UrZPPsXUUwjO2M0zZUMyaM/S0rZKvEnSl2jOk43PCJGR6MtzSlOKAZNRVDZJdLRgycBVfYt0Va2W+XTEz4uMC0lwyT/BC07KMNaRIsO1SbOIdk4xkrOBdk7okrKWwU0zZEtLEM0Ez7yFS0mbw9EJi07zjnGQeU80hw5PcZCskneN1LFB1/aU0waWSE5MJpUTj8TJyMwSAUNLq01LilqU4kJ/Fa5I3wpalOgGOkWuT8uKypYY5ZlJ60k1B6jMTUwQzWBEVMjHIRtNIMtlRkuIm0j+kCmXTk9uSVaVvVGbjFtM+pP/g8TIrUz4kt+CmM0Soe61VyY5EN5PnLDWk+DMO03flAjJC41Y5jnyZM39TuXxnrKQzkeJ20tNTYjPHk3eTRqTJcC7jbNyuMtftbuK+0jIy8NBW0q+TnjJlM2+Tj60lwkwygFLB0wekLDKAU6+sqjPzAWHTweJBM39SudMIMw7kh1OBMplgyDPG461SdaXVcaBS/61GM+qkXVJJ+HEynTKd4zoBQGUJMpwToEk206TQ9bnQU6XYZSTvpF2YCFKkIjWkF+HWM9njI+V1M5kz6zNtpKgTedO2Yymke9yh48qiEjPzw0XTDjMpcFBsoeLl48UywKFl0tpdKaQMMgxTVJQSpLHZIJOrQF6lvDNAkw3jYmTAEU3j3HxKpUMBf1ObeRSsmjLJFdRSlqLaM3VCo+KjtD+lz8yj4jFEJzP/jahSfeKUbP5lBzLSEpfTRzPlEhAVODM8M9USjGTvpV34mhPz7IMylRMP0rYz8DNP0tkzpDNr45oSnaUnbXNjaaUSM6JTaaUhNBpSElK9pMetXRPQs3IzxuUe8fQD5TJMoWYEclMiZB7ZBLPacIUyx8B/PEpSbAL/M8IywxJjEiEylhIf4Q4TSDIZeZAz52OfpREyd2NaUnWkynxzErpTimXuMmVTVtKEraMFfVMWzAnDmTx9M6FlV8I+oJriyGUDM6g4+IAZUiesVmWCsfaT9TM6ZKgtM1M3kn1kG4FEUrNTQjOX4GZxkzOvfFZkunHG4ktTgOQgibMzK1LZuSaTb5MvpdIYsOHLU5/Mgbj2ZNj1yzP/fVpl1HjHMvVS0WWIVP+SkdISYDRkmzImpFlBCiThUsJlKkFwxe1TuzP9pNnE+zPx44UyOLI/02PlvTVMshxSsLKWpHI43w03065lbLPVEoizHLLIYnnxrjlcsgqyT9J70l1kqLOCUy/Tl+D8sk4SrRLGZYKyehLtEutkh8HiU7lMwrOisxfTP9LhsGcUtLK9EpKyd5EbeP0TPLN8YKiFu2IItGeZb9ggMjV9M2QmsuSz7FVXw4Xl/9OUs3mQwALUshftZWTj6Q9jtLNJpJKcjWn0snEy6kFros2S82KbZWpcrZKV2BCT8ORfCJjiKTKDlRTkOBJi041ohSUNWPBBHOKDfUdlklBS0jB0KkCTDD2Txrh/VOdks8n84/9S3QFDOArSmMIh5Tl1StKiw8LkGUF/U7xoCTIiuaMynfmoxNdkd/za07+TvOV4YAuTssJvZdOsS5IKwnGymDO247cse2RAjGbi65NfZHRTzTPsLLTkJ3Bm4s0EFSVv4A68euKILerkdrOTksd8QbIuUTVTZVJg5KGziVIH0mIAOTSss40lFBEa/Q7S0rJc5Ndg1uNjU/DlcbMu0yWy/1OokDeTYzOrNcGSArIVJMUTyTLjRUKy5JkqgCKzJVJ65JmyblKNsnrkrNmnU2tSuJg/KFlTUrM/ZIjIarJ+41tT8OXoOaszAVMtI8WzQVP/kqWySrNR05syyMQCINsyJ1NHZDzRMdJnU4DlQhh4EkrBXVL+ZUGyycNGEuWyrdHSUhUT22SOOMqkzCXsEntlPIUGs91N22TU8OtUH2IHZF2z/FKmssm4ShJos6LlLUCTYulAYfS45IjIqISLYu2yaHBSqI1onRIh5WSzWrM+JNmycxN7/PjkE7IFOM6zz2T9mOcErrPRs+g4W2PDEoGlvp1OsnYSSuRGHGpSARQ2QavND2JQMrIl7XBUYl0ZMxLCslvYThPuEmHk9TNqQOjtwuVOLMsSLP2i5c2cIhJksP2ycTirE7xI97NufGoydVHz5LMz3BKn4ZTTE7mVk/OAcOzW5EldJxPv1bOyKZhnyMsSRlkZ5PYgO1KyAZM1Q+Qms19iJjIpQGUFQBMcszpU+eQxBYWS0vzW5P+J12GY4mGAFSSPOEZhXOPy/C7ltyjXEmzTouQRNfPiTXmB5NBRatOhgZZVouQjJWnTnxKBpOhwb/XfEnZVt7OZMucS1iQABZkzblMrUu3EQiQu4y6joHKnMy2y+OTRsU7SI1PC5YTdnLN2ZQyQMHIlsyMyNQAsElsy7tOZQbXTHtMCsm9AsiN9Uk5S1uSyDA+TIrIu5BSx3LJdMwPkHJJrUrDhZuUAlZ4E3lLtsiFleFK1U2bkw+MZ4rtSTyIlMsBgirNybahz4eObMtyiMNPHUuqDwHM9oXpTq7Ih5TthzlPrlOfTMIB3s6ti9rOMckYSO7J65dE56IQKE3uzMeSeRaiyT4LscxfAK+KqEl3kxHMEkqazWnluI00TyeW8cm/SIbIpmfxyHFLWs/i07PU2s8n99uXCcxoEW7Jp5aJzDrMT5C3IcjEKpU+zuHMn2eAyVhIpQMPjBLNvs9ByWrIqU56zngzSfWYT3rLco7/TP7P+5RuAGlNaUo9kjGHXYzOCDeRt+Cq98ROA0uZsC4B6kxNUY3CmbVhExBP9na/kh6TRE/wysiSJON8SppKqA4fllqQ+E2+lYWR4tWESsLjIFNRT513OFfoU1EESEwATKb3oFSiYOjMOkiwV32mdMn0SS5W0RU8FLpJHM/INV1IYMogVMGNukyoyzqODcCITajPH5VFyfBMaMnUSnY3cE+h0knKFBa8zKtypA1QVKZAQEvwcgnPhedgT0vT+ZP5yInJQUl3lpL010o0S5rK5ZCsJ+eJKbIYBKQ1yswhSwXLPdXKz2dJRcnWy87KKshM4HbKh4hzD8xTmgbF02eKF0ylzJWNF0/4NAhRuUbsSLzOBDUlzc7L4U+1yBuBD0yxDnWV5sXL8o+OrQJelVGWXQW3j+Lwf5dsSk9P3/XlyLXPUwSQydROqbUCyZL0AFdI0rdK0rQAVCk1gsj3io+RbcMcyufiSc9ZyydI90nEzlXI30lgzYBWBcoiSODLBcpJAIXLKAVehaTJ/WCpV+DNWvY1z1sxEMhy9zXLBs9PigLP/CMah8+LhzbTUHXO20hQyDNVX5Ilz5YGuvD1yyXOL0iiS9+TGMgqTQryoFVntq9OIAxAVkFAD4swzx+W7TBm9u+KaJb3AZrL28PiSB3LJwg0S7GR1E09jvmBIMurNkENn43xzhUkMMpfjNBUXRdNiVJNf1PQUhr0ms2l5UhT2RAPiZ7IrFMaiZnIPFU6Q6DNXst8UeKBWc3UUHhU+TXazCpSZcIEdPRJ+Uj4VXtUrfDyifhSe8f/TQDPgmUlYT7NZ7EuUsdOSUm5zWpX1EAfkHnNqU6GIwShXslAyxxVMwetj/rNhFVSoshMY/McV+rA2c2xTKJSMgQtjV9I3FfCAlRPPYpYU2bF6cm9i2JRtwOoTDtj3VCWBXaCcMyYUVxVTotwzQXPWUYTyBpKhcykVlhFhctG9ShU6AdIBFBORc2MV/3KhE8CVgPOiMuES7xRX9H/jwEIrFSA9iXJ2k6kgwdTSMrOVMoToQU6TFqQKFPGD8jMUldID3+OcErSU8POFcyoyiYCI8nwTIIT/c3hSPTi+5SEVqPK5E1oy6PLStAjSABWC6ZjzmBNlcgaU5VAVcvP8HZTHoCjTsjKRlPUBERPc0g8UAMFHHTTzc3K0Yjl59+LhctaUAOjBE4zzcmJrNMzy1ZQs8oETy1R5lI0JdBOREvFgRfhfUoAS3pT4gFty/1L25KeU/8MU8vhUi7xJE2mDFZS1w4VybuVmlP7xuTN4eRb1JYGaudmyPTgfZJVwrDhGk96TYvPlYYBhmXMS8l5j49RS8xEVpEgOeDLzP21KFX1J1jPZZXLzEPI88tTTsXOsTPosv2IV1WaUzR32M0/0dvNhgcVTaX0MtWaVq0mDMjYy4aX1lTSxuXKWAkmUo1Ngco+dcFW1oAcT6oVulJKNFxIiuZeU4iGOMmhzg3APFTMQBAMRk7f08WGYctzSXwF5FYCE+QWY4uQl2ZSNMyU548S1lE8hrNISwSGUdjj280n1krS0Y/JpfjMuMyWAQiQB8pHi09WpIWFk3NK1rJpjpXO806vEPJXc873jbsK/FYhwqyEM4qMCdvKoYA8TsVAPlaryHDitkvGDmZS6ZczSIrmwJZrzWfKcOdnyx8Ha88zi3OxllS6Bl5MpZCh0+vIG9aGyjGNwVYbyPZLr8AXzXZXx86Sw/WyJ8ru0VbIg0b6V5vNrkz6c1ZX4COyy7PRBlDbzM1MGPJwVdvNO0vU0OfKNpGWympx28/95M1OlNU8U8vUbk7BQ8AQeFF/MeuPMXPLykPKG4n8CbZWK8i7ieeQmlFGh/LPePKPzBgGm0nulIZWBaU7SIuy2lSHy1uNj8k3y83A3k68CUfJzuHeT07hR87WCLuL9hAWU+IDVMt0oPwMd8ibyZVKL8hHzifLe4z/IMHRRYV2hpBMDeeDsYfNBDcsyoIK1lQWg4eIkYP+UDfMZ0sFS4ZQZRIBSoVJ585dAFVPbM64U8aTn8mBTs/IG+XHj0VIjFHjTMdNlU90UpfIrcvzy5fMZ0ynjy/Pc+XVzUA2q81jJueKYgnbyQfIP8xlCIfJa8y1yP1UD2XMccFN4gi3zx3B389RRbNV4fdWS2eOjhPhUyGWQU3tlcfMZuVOzS6j881UFvfOmaJSDbpQAPbgyMmiD8ygKn4TD8hnzk+MryZvyoApTcxSsOfMgHDNyfYzP83T9ILKq86RJAtgMUj3jRfPisry5kLJdld/zmDI3cnnyS/Ibc4oilfNhwbgy23N5FG5FijP9BaojQAoa8qPiU+KYC1nzALJSFE3zS7JkMtTyuvOXk0I5hhn78u3zQ+M2wx3yZ8iVEzQyhvMn89dyg+K980dsdRXCNRfyaqVb46vNqfP+c0STW2QmlDbzV+LsM7QKD9LApOPzwdTyFUpyk/PP89NiKDKv8/YTqDKcFVIYpX1r4n9zJfOf8tCzNFS/8zCzr7V6CeQLcLKblU+YNfIk87TUz+SuLB9jmZRZ8kILYpX0C12cL9O5lIr1ylPosi6UcuxOE3oSnpRsC+DyfFXwCnNjePJOlaby/rK9E9wKIcMnYhV8dvOW830T2nAItdbysPjus+S59/JHYmMS4/NzopSzaPNO80GDGlLiCgoCMDPFFF/MgbI37EaU8fIICmlzR5R8mEFyUHRRYD7BnZMjgYJoyFS0FJrjceBt8nwgcqyM8pZFMFQU8iIyY5VuBLdTlpMkVaN0evKnFbch/zMMEjETQ1T48VzzeRSOwUzzLBKU8pxxlxHyMxEDgenQcQYy8Jjt9MRUL+PZctbzYzTHUvYltvMzcbjz+XL0lRDV4/IS8rnUZZVkOLq4UvMeCiEhu4Rlc8Alh/OI/HLyo/QOC7oKMgsKlZmCcdW9xfXzBqCy4EDzChIcVaM4PFL6cmWU0nBn4oZy3gufcggzK5S+C9US1VW3IRtNFrMXs2RUgQtWs4tjSsEEFE4St7NUVRrhyPM2c1RVL9CduSYTLVUtgefCRgq7gp+V0QtmElYTSsDveYjyKfTxC94KnrNalIkLlgoTE0eUt2I/sxOCZZUD2D21f7PhPCfzLV048h4SlXEwuSA8J7MA8/WAhcA300DzAhRoCQ/cF7LzY3ih9BgGEtoKj+TeLCG8wgC2s3ihLEIaU3oLgwtB5SQdeLKNCqi0Cb0OcmMKL6Xw8ntjgwr9YA5zLnNTC/qo6DJgM/MV003P010KS1SW3L6yepTCACR4NnNY8ztVAPA2crpSYNWOAHMTcwvaAEldsgv8lX4d8YOosjsF2gDHVGfjd9NTCodUTRNIs90UzNIDsgt1cg2PVKTjUZP3owFUvZQo0m5R8vncEFZTYhIdcQpVgDincnvZmSILVOFNV1KwcqoUPinQkvByORQQ1VR0iHNStXkVTUFvE6BdHwsIQWPSXWTFFIcLgtKLEiYyK1TCPNzS3jMCFUfFmbK+MjTUsuAFM97ZWpVfia01eONcbJNUXkBrksEyT8xPCtkBPjPE48LVM/LhMgu8k1WhIHgTnxMY1clwDOPF80z5r1Tj8DcK32LXC+iL8+NVcoTUdwowC2UKM5JYi3BSgtQP8o1zETC5ERnizXJzVTCLdVP/k9oANKQl4u1ygNWzwGoUnXIovaCLMOjHMthTwNTwrWXifXL7C4cKK3KPVDj85ANgsx3VUNSL+dRS1dKw1YrTbeO106pVWCCJM+YAFFIwiu8KGAqp1XCLeFOsOBI1F1Us4KRTrdPi1BIgx3MMU+LVZDiHMl3T4tQYdFiLLFKYi4KLvdKztcLU74EgknPlGNSL2byTi7RPCgCSApOXFMAkEbJTc+PSSNXsizQKVFIkitTxQJNtJRzVZIoAk7PSZIrDgKRT0pNUi1khl3LGs9oBpqiWBJyTG1UFoSdsgeHipTtVj+A0TKqTUAuaUpy5WFhb069U3iHyEi9z1yWqVUSLRnPDCvOVQYIiC1pUudhx1CR51eK4aeb95JNMnHNVK4gr4uySPJRvxe7zCvLbCjEDP1PcMztVkIgpC64LeAt3xCLhRpKH5YMLlwsa8zT06woIQffjJwtYIZM5LPNe82ML7gt/4g8VG8AzEYEKkDizCw5JKBLME1MLswsm8iwV5Qwo00qTgFWLCycSXLlRC3ihywpC8zEK7nF8BJkTcQtsQhzz9vL0lZsKOjJFctzV2wvO84BVsIWsPWkLN1TCADFBGQpGMuqKtIplUi1QgNXHCsyz5IiA1I84/TgpUuC4S1XmJGlSUglBiqyDp5IT2T6L6wvHktZTQYsQ4X24uVO2UxMLmVTss/ZTQYqTC4VTAnJjC0ogCAouUrcKiWEyw37TlxTBimJzoFX8tRHDEnJLlAsNuTNSc1MK/WB38vKy7ovRinJyP1TvTBVTgFMbVXJUaeJsYVHjoIrqQZEKAXW7MuqKMUDzUhBTgIvWMwxyInSzC4FCQYvK1SdyzgrRNWpF0YX3UgbkNtVTJe2KHgtDi3mKboobtKTAbOADsl/ig4qB4LwyjhR5gU6ET+I+ikbUjJiGNRzykDl/4VSlyXJxE3/hsos885Zks4sAxeELj6z7UO/xoNNRCqTAuJE5UjCYjmUa1LNxnvJxCwPUYoV0wAkKhDWoZFTyMJlaMqTABuFeUiVz3XWDCnBhoYvceXkVz8ABMoYzZYL3VHBgDRDVikbVg4rMsklSg4vneScS5pQGtaOLd4r8iYS05Y0xskMzDXSDi5OLG5MFitOLq/lFiubURGG3QLuSpYvK1fOLYVJraOWK9JhLi0OzLlPLi0MU14pfir94D5JeIS+l64sfE3WL14pbiltSsrKji8+ws7IHiy+LCrImeKTBeIHFcgpywDTpc/M44VKqFbx4KrMqOJI5QYpZ41+TanI8lFeKcwoFTUeLu8OyEvD8O4p3i/IKabQPigey/LRquM4jR7PXihBKAPP/NKxV6JOjCiiZs4stExeys4pFJBpSUwsa1IyBUiJf01Zzf4s9nXUKNtTKM2oKG2LkdUBKL7LmE4fUiKzRtEAzKwqkwWBKLnIp9JOLwou2EmMTkEotQU6yEDKDiseKThJecoGKbgHSUj5yCEqcOb5y8xMuNPUA/4uhCzhKpFDz0n40UHV10Ne5KvL4tAZRDiwuitE0sIIICgXJE4pEw9YzU4sa1BsFMaSxczhLoS1XivFy0rkmsdRQp3PREouKBDF3zcEKsjXuiwOKokuQwYpyXOQRC1axuvhCExbz3tS2mFQLVvPCNMpppqg6M52ke4s4k+7yHwrzi4A55fOHi0kKeYGlMijShWAodCyYhlLq+OkLREvqcF2KHvKZCnTYpEtfkqOzZEvmwPPSJuOatFcUtpL3is3V/EqwixUZi2M16CztHbPPiqJLZ4HWMiMy4kpoVPPStlPvi+JK9lIFUvJKfAhCsv+VitUySz7Sf4qnRc2LfYoF1fJLY7NicpPVwujkin7jAjwF1LaZmYrTs6BL09Ul4liLTYp2SqmLEdKQS7IlHMl6Um2K84qdSRCysdI7tRUANMy7MtlVf+EPEvsyl1ImS1kLr9XcSnNjWnNkSjVk6EuWS+s5uEqFCjZKt+Bk8tg9QUr9dMMKDktssDxTf7VOS/hK82OSSy5KVQuPizwzYAQzCyRKHkug83MLkkqUaAYLE+WKS6TtZhNGCsLJKvFEslYSaku6Q7YTdEvCSi+zH7NES1pKX/lbC0RKuko9C1MTZErxuE4TbEpfi4ZK9LJ+c97UcQVk0x4zh9WQML1BIHItov/VR83rEhYzVdQs45YzV/O61BUDuXM2M/Q1VYoxioQ1RSFao9wSDjJINOaBzou1XEmMjtRMBNmTfwvsNKj0nxNuM5w0+4vGMsBzidViYfpKeCWv1Bh0j7ShMkUkjdUyAT4y/jOWNQLFhHPQiiI1PUpZMjB0MtVHOA8ToTKiS24B1jOc0rI0E8CZk9zSjDTpudmzh7IGtV45zYt0cr6120vKMlmy4kt9QKDS0glC0m1LljBi0h2SMtR72CLTXZNB1InIDxPHtVNLEaASSktLOEqbJNpLBqG84o7VCjml83LTrdSbwaWTCtOcNUjkrZLFMh3VmIsE4qrTrdQPNeeSuIt91Amp55Oa0rNLMzXVMve880purRbjS5P11YtL9ktr1GIVhtPq47nUJNxm4i0yk9QyuF2KZtKSSirU9IQW0l/DjUpyS5gyK9Ny1ZU4AJNii5Q1w4owknyTVdS4cfySo9NYNXR9IJJLOIw0pCkXSwXAw7R9SvXTCout1QzREpKW1B3UE7Exc+WAC9Px1Q5IK+JL02NKOPMaii9KCGRKkmvSZjS4cTwLqpKD1Oi9fAo0Q7rUg9hn08cyzdUIyqoLaXjLS9VcWJKMkoo0XIVX4kfS60u7o2virJKyND2Lv3PjRAvUDnjYQjhLnTS6JZqSeEvyEQN962IiUtU0DuRXsx/S7TXIadJS2LLtNOutsUudNGyQV7P4uZ00RzjJwoSyDMvMOS6yxLLRNMagCwrv7UtLrOT0yx0K0TQ9lXzLDhJo4IXQqmQ2CnM1tTy0s+2UaOGs2DkLBwvTNcDT62P5SuUL6nAnCuM0mo3yCoQ0y6knBZgl8+z1EbypKUs4E/U01dMLYrLK1DBjTfi0urPzQdv572NE8s81c3ktlM9jSso9pTlQKsuv1QLYYMP0ys80YFD65SZzpzS+KHNilrPAtDMQNE1XszhKtdmwMzULdLVa0kcLyEq4QpqFdUq9Ek9hX1FVSlRKqzQi9ZRLpUoqUqFM5UvusxrV+soNCijyjzVgmCYKosuGQSjENnMY8981ztnecpLL1nB8uQ9jgbMuNQ9MRkp2imW0/gq7Aa800TRNxVdKD8Ejiku1q0m+CyeKT2BykCJzQktYtRtNGdla8r+1X0ReizhLkv25MpETwMv3waF1C4txtROwAYrLijYE9MsritHLLdkoEiGKKbSXoLAS+gjdtF2cMQuqSmK1kYvek7byuLSBTfuKObQlgEISR4o4/W0RKQqByhh1nwoGS+p5yrQlqReLwOS+tb7LbxKRk7O15Qsgcr81wLU9gGnynMjENfi1QtmhiqfAjDXdbK8L+YDR1Zgk2cswc6HzG7QfIQ8L4fJNtdeS6ZOR8ya0pgnIc/L45rTkZRTScfLItY3giHOlyunoycpJ80PFgrRmMS8SqfMQdUfzafMBUjbR04NPE+0DMHX1yxzjkrVwdSvEoTLdAlK0bj25kxflXrU7yBdM6OJY5UW1wpSfEqzxvzWWys9K/WwAtWXLobMrNBXLR1ME4zDKObQhy1GzvJw1tJmNATJBhBK1o1IZMyPLBrUQs/RUfaxgIDghuTOt8t20ZQVwS6HgHfPgtEzM1xJd87y0WLA9k/8TMbRbcOyyzyS0ZPEIHsRlswPyv7U9RQ+LSp0OtT/1FuKBnMPKG8vlYS81w7WRY2uTE/JEtXnKB0AwU3K0Wtna47qcFzUD2ceS4PBSUdO0GqhlUz/UE4n+ym+iZTRPYfk4N5MVNUG14WF3inCYSHWzTNbjshXryxHLVjh3yr2AAawmUnkc6ehY5SWKl12gdZGFB/Nsiwi18REx0+SoncuJyxGJH8td2JwikVKbtSnLkC0fkgM1kLT0cN7jyNGH1EbhusIoUqM0dbXDy0FT9bXoHLxVAeN4NDj9v8S7GBuMlst6pPNTSMsvyog8idL15bPL2snd0r8F88ufy6BJFqTfykvLbXNjecvKPpRwU/ihIbVUBRnil4FZtGgrnu28tF4hELKgYUXilrQ7ywXSvsUxtfd4hzPsdMi18cvUiwo40Cr+SwgK3DX8tbAqizDxNJa0XKADshOzacoGXcNyKTX9tJQr5FNpNWu0t8uIysJLmmzck83St7WZMnRTWswktFXcBAqGoS/KrpRMU2o5CIDvymfTCpL+tZ/L3JJVyk3EvNPQsA81y8rGNDCTebD/ylXJuDO0k+HKVCt8K1i1cDFQSq+A3KW0KkugSorJgUnLWGSIkrPKQHRu02vi+KHMKpUTEiugdSfLq9JdhPAqBByqktK8iCoUqITLpMpitWLdKhM7YWG19ctpSjnK6xQn4+ZKRfm0jUySzyVPyvoqW9kjTEXL72O4mV/VyrXvyziyTeWEK3qKGstZi/O0JCpnC+wSH7X8AzrLB7MHNGHKN9LFC7wrdwRvctHL1CqjC3+10comygRL8ZmhdBZz1kv/CEwrHRK2swe1Qst3sifKnCPQ8xRLmQjny00L5hJgIOnLLQs0SxnKawvlSiw4wczCyjnLkWMnY27KRfltEI1pLEqetM/LEsr9CpbKr8o+yo1LCLWdypzLKLQAeB/TqEvydfhAicJ7s+J5+uDwEKMKhQv64WCZKpPuK3R104n3M6Yr/HVCuBGTqLKzdI+4iQSaCpJ0BuHPDWbK43T1OToKWXQGyvYqpHQA8UNtwSuddHQt4DNGCnbhxXgOcyYL/nWbeBvdYDAp9frgvuG7sxsKxHRvE8qEX7NYtZZsLEs9Cua1oXz+sv+zB7U13O4SySvgyeUqQSpWdQo4BPK6s1ywIawKypJ0mjh30/Ps/3TJsA/SfEQpMAQq+SvA9JeBV+J4SmD0iTgVCiSMAkDZQpiyWnRurTezX9KtdDLLKSoHddO4bEr4snp14/JGCnDzFXQ7IisLhfRDgcLob7MgMiMrdiujE+xV5nX1dGjyARUDdBMxNUrtdTZ1ozgdKmeMO0ijSvYKNOPq9eZzdJNpeePBQEAXCrN1TLiGi+izJvSLvB/TrKLgsK4ZWLMzKhcq8IpzK2H0XwAZKn/TUfXsqZMSvMsB9NgwpUqCbJb1FfhpvAdjpLMp9C0EFgobKsRYFLDes2pT9vRiVdsrnXVqOa5ztgty9eaZC2LSyvz1MLjXK+R1sclyyqr1kUR30jsEyvQH1Qiyb2O9QM+xbDNk8w50AZVyS78rnlBBc2T1DAiACk6LFPVdlCnyZBMuiyCqnEJuinZ0hK38cpHLQfT6Kb4LWvRUgiwr4jJnKmUEkjJJc/n1Fytc8rr0+6KyMmATMfXNxXzyrAym9FlTfOMJ9MfEuRMqM71ATypqMi9sLysIqr1KqvSciVuLzbNJCh8qHJXxi1n1snJ4UG7y/yo/K8mL6A0QVXGTXEuD9MGhJxJ+NWT1vlkR8iOL0KrUVDxK6vNR9NGFRFIFyfCqb8lOkeaSe/THK1HLVfXbgVZLMct8DS/QaKpBCnf0uflXUwGKWAyOOWwTfstb9TA5a4rudUEE3pOcE1ELkGkZk+nLfA36oqHztvPNcF8IhKq+5OwgMQUqSnGLJvXiDCIShWGhDSMKg0oGS035ePAAwaGLhjLUqpiqHjO39XjxtKrlywFSRfXXSO1L4hxSq/cxljKB82H1KPlQc8Hz7fU3yPMyYvNK9JX0dDRQ4uy0zfXVoYKsTjM5YTX0eFFk09Hy6/URc6azZPXGrBiKKqqm497KtNNJ81X1KyHBk/2AvwUiq/mBxZLp8s31zoHtiuChQ8oSqmyrATI3HFKrKuy58kEs7CCB9JmTF+TT1Xjwpf2F8/Cqd/jZk6OSInV48VcrKtL9bSqrPrIV8t0jYfRvyZfze82YjUuU89JOoI4d+fXMq2dKBGN3cRKqEtOStZBp7Ks1883yy/SfgwTjJILmDNyqCtP7yzyrZzyPS0sDfKupQj3zhxztcANwp3N7gX3y1qtJoNrSF8vt9SCBFktD81X1YqrW4jfKTqrzMhLYFXQuqiCz98qHAmf18FUAy/Rc6KpRKTNTM/MYqoqqFtLz8z6rSwCxU6fz4/T+qmtoy/NR9ayqP8oUkxqq7ZJjM3BMIXHzeRZTS8BthdmrdatJdJX1s0P24rvy9fXbgeDTjeAo9LEiU8praIfyWAw/5CKzx/PpDYmrEYjlqsmqgqrn8hh0J3ROYkaqvkudSoGxUhmAK5PJN/P2qkZYxIsxDWRB4aooUkmNuaqJkouz/nQ9RY6KHYux08P1fJAVU/HSF/W09Rqzg/S+qteKefTKqwQqOKrsQ9BSf/OVq1R0SFJnMxOrgqGBSkALtav6q2gqSmwNqxBLnXVv2FcyBeMcqxO4SFJQC1yqGGh38zAK6/ROgdSKpIKN9PyqP/KsDX6hlqtICvd0D4jaCW3ipwL19aJw9dMqQKkMXfWGGBgLz7A99aOrLeMUrC6qPDQ4Cob1bqpzcoyrtYF7y6gUwnwXKmzy2eNLc9r9YKvUqk0Ta3IX9KqqZArC1EX0DKrQyxa84LDgMPPT+ajUC7Wr1l00C0Qzm6s0CrsMkauCKzCTO6tvizic4oKr9LoEiJKsCqgMvKuXc1KCiarYyx+qzfXJqwwzheWpq1gxPAsuw+mqX3A4kvwK9fX6o0UKv0M6q6Oqoyth9CGUOJMn4m6qWtiUyziQNnUjC+9iW9izDNMxs6q741IKC6q+qhUq+vRLqgCry6oMqs4rxfWMqwUKIKtkIf95esq3q06qqGrtceSZxytL9e/Z0aog8jZ1WhWKyqUqm/SQagErVnPWDMerkPKedSeqziwUS1urKyEl9UsL5Gqiq+EqSfX0YcEsDStOyihrZGvrKqKNa9D6NUSzDhPoagWrcSvUshcqRau7K6X1LLnSUz7KdNj0a12qPTUWpdYMqgxDi9/05oCx8v4SwcudDS3DL+Mni96gJKp0q2yw6vTXiNFyNnXiuHI4HKpkDZeB9+Nzin/1DAUIBXHKQQwErLJKtQ0vKgFyImsMkSSxLpIRC40M9qgW8iKq2azpwaKrUQyjoCLyXGqGDdnKeA1nokkK9vQ9DQXLOjOO9cSRnFGu8jsr2WXZnMXKxkpdqjjyZEp39KJqehNpKoiZYmtjKvkLEmuIo8CqsLlSa0K4SLN1ErEMA+MlCswN4jRlCpRrOemg8ybK9Qw39JiyJ3V9QFoZZSuqaocrGnMVKgW5AxJMa9/0AihPs3bLEA3/ZA7LKwveoMDpqyoca+/0CgNNKgZr4xNMStwN7XAaUvEqqA2XQQti9UpYDIJDSSscSijM92y0tQbL4I05qlhKeEoZwdWhFBzFKpRMo9nbsu0T/E3TKiRK9s0OOHts3mv1jVPgEyJVKvRM6QFEs0YKGcB+YbUqVhIZwDkDLrNrC3FqQ5IfsmMSgpmEEBSE1UqATJeB62IRa9KYkjiXjK4S+02rxAYSgHLbDC1AYIw9K9xMEXOyC7AkgpmxUerLlRIYTCrUeAN2amjMs6R0M1hLzo0tQDozOpOOjNhgepMP44QIAOD8Mg9SXw3yeLwyxpIIjS/8HortXPeNN8kQsyJKfWog1DOK4RMajT50evNbjF51Pku2k95Nfai4qilyKE1MsknLrIy5xfIzI1x9asQEKNLukh2NZoBFisS5ENKrwT/J4NKsxPtNfWtQc/pNYw3Ww26Stav8tX4CCNPkyliNU8GFEyGSY43/wCITYZMjjS1ryqr2av+005OmMpjSKwxgzTGTjcOejNCo8ZKZLD1rAOAo06Dis4wyCITT+k2AjPC0UOPDaq6DuZPpkpcNyP3IcpXSfWpzlWTSlNIdjOIcXcu39dCMc4jo4sPC02sMXYWSNxKrwQosA5M44v8MRNWkc9LEXYyITXXzUM3LaxDhLxIIipqYWrkXEzWT9o15eLTTkTOba0dBNHIHKzlDsWt1sid1kvw9kozjiw3e2Q6rItOHars5NfNdkpsNl2Uc43jMS2rxsmjMMyPjqtdLMtKrwNxQCkstw51KRwxik6GywuLnDOdy2TLlMzMxtGjHy3Tij2ubwdOT6tLPaztkZbOVMzGMDtLy459KfWsB2CJySuOWjdsMZ2tdsmety2tky2uSRtK/antNiuKAyq8MBvzbk2bTjozupKDKe5JCasDre8qeSm1qe2o9MuoEE41DuKyyPYxHa1Y49nyrwdQ4BYtDMyMNhOpcc7DrA2s9s7ZSQ2rCqgKzrI3XagJzwDko6lAqMzNo6hNrL5KQORjqgEqB0s9rFYt+4m2NyKGtiiszDwwV5L+S4dJ9a59qW6vzDLr5g6teKN+sv2prakpzV6vx3MKrTiOqDIHgnkQf8wl81OvyucDrieNvM7MNbWqp03Trm0IxRf/zIIVjDaCcJeKZ49OMC8W54iAKYuqs66ALZYw5+HfyO6rAjaS8hzMPM5zrarQwChh0+owMk71zUCS86kbzhzIWxPzqHzPV4wqhxNXnqnXiCI0wOOCTPzM8jGk0N6qfatrqWAtXdbDAljPDcsCymphT9Y+rQ40+MQRSPeOzDIVFndLCIzFq/cBG83tLkI0sQgrSh0pvjbsYDxIQ64+Nhohby2LTj4ygq6zTGTLQTdv5xHNQzc9wxuXe67zjH42XgaRzifl35IKZaxXM06OTtYzwizvKaDhNa+aZqIoZSBjqHYoHA5jrObJVavCBV0uWyPDlz3GsJFQLYpiXJc9x17NO06TC8E1elEPy/o0VAAopf0sGjPMof7BT82+8t2tp4FWz25No631IVOr645dM7uvaKjdzMzCe6l+r5o1cgc/ZvJM/q89xLFFB83+qMHWxWV2g4JK0Ci+MgeokMxStQev+87PjQXMh6jzUo+LwkhVqRLIqihBqZWvMxZBrxuuOgJl5qJJF67Hq4wtcCvSN1XFqCo0joWRJ63mxV+NeKNPVKeqCU4aK9I09aJbBxopozdkBz4NEkyfjWeqwrUyS5+JITFgdAJw/c0pwQwS0y9fjl01VajHqHupVamHC1xM0CE1rsVA1c19Ef1RFa1sdkOrwwoBM0YQSchky2oomTQVqsOtETBCZpfOJssJNihIDkmHq9Ix5OVPrEetETbt8BTNR6jvrturT63FrIOHDMg/Bc0OcCDGk70t5soxNE8QFsinrCxkJkkWzXeqxa3vKv0pVanzInpONMv9L0pnLkruSvSQVayhFd4tVs7xMFKk1s/TDl00pqlvLz0pmTL2ABTKz6qJMkoGlkkwcrE0RUBN5UbOL63/AJKv+6ivrf8A5Ke7qJHPqTRX4rgrw6/Pr1UBtgczTm+vyTN0kAfMFM7WN5GFjYo9K383yTVyAIBvP64pMKir36pLD4k1aDceSnAXmjJ8sCkvJ6vSMtmiM01Y4aeunML/rD4oZ661ZQfO62FnqeaQJKmTrFbNxagEip8rwLGZMyXC7k3ri4ipP62eIa3Nt6kP00pICLZwIRYDIylywaMyLnYOrf6vn6yFRk6vgk1uN6zG86nbrtYyN8prrW3Jz46cwg3kgkw3qwBp0E+dz8i1xTZU4eLMr4y3q0gAD6iQKg+LDcJDolRNqjfAakoUsMrwL4k1vEM4sI3i96s8y7wN4kppNzSDo6wPqok16JGfixJPmjAhAsDiWK8I1RZB/ed9zAcJYG/ihE+ocILHMjBoB8tdTVky+KCiqpu3yTJNpwZNP4yNMVqENgEbyT1J9rFagfMj9ay9T8k2kvDHr/WromYMBQfP7BWDMbOAh/MNrnk2J+JQao2u1jctwrwrja+CNyNN7y44Lvk36EDoyMsu3DZYR9ggW8nnDWhoYPbly82u3UY4BJ2o+kv1wihtLalFNAgTFIStr5LkxTO24OjJBk+AbJOXJy3Etyk3ZAdoa22uiGhAaRxNdyxZN2ECIctGTcU0ywYOr7XCHa4pMsyHv8/OAuNL9cGwl7wpbEgAJreswcrktrkxowxdrnkzhTFhyLyGEy8EA6hu5k6fLZYyaGtmTd2t6GxqRe8ro0iFMuhpJ80wbaRB/SjNLL2vBAA/cBTNva3FMjBhZUizTChteGhWST8wyG5t5pfMrS8pNPYSIc39rdBuyrJEy9ZK2G3+wiHJ80vYb1esq0rHrCMnL+YkyGM0fAxflR0uPRDIbEaGkcn7ryk2PZBLTeMxSw1Pqf+ohTV4kibIh6nkAbYDXE7dLOhsW3amyC9NeWPRhnfLK0uiZIRoFMpAaYRr9clLjNM1pEA/52Op7rFEawaIFs034xhqM0N9LSuPKTaYa1uIZ69jUu4qoGmjMbcA78wDKOer9cWN5NlI64+AbsAX565MlFk0ZG/+KiU2OG0xyjRrTMLwSDOvyTG4aQ/JM63IbBcAcc/WMRRt1qhnr9GE+GmMz7OulG6oaTuK0ZAEaNLFlitzr79mJQc5Sz5O+TDUaYrP1jDXBnTPe44+sEQEMCc5Tguu+TNjgSCvC6r8wWHLB41rMXhtT09rrIxukwV+SYUtxTSelelMv8ikaFvxv87szFk3zxHOqGRuMGm8zjY2oOYMbyuo4TazYKvNtcunjrhsIG79tFzNjG7eM2dJKbDsaMes3MoYaULR3M3ONpRuyKkXi1Y2RtFlTJeMaG+Rg/asshS3q2hqHMyxTOhr9c/lkPswRGsdzXzPmjT2BVGRjclj4xhumbH8zfI2X4XEah3NmGs+xELOsOTNzMUzzcOCSoLIpGrxF3eIvq8cbBcpEC2+rMWuFUfoa5Gq6zBwbfBtDTE04GotiCxHNdgJKkuPqN03odVfjUgvGzIAjHAp+OebMXjND4xty8fEphaXqSo2+tCxRI9LUCz7gkHUAa/ty2s2zAPDKuwzXwSQF/JJUGn9Zz4NwkwvjVMyahNKSF3OrTEggl4wMG+aMUb2Pc9BrVM3y87dzsxr1ym4oWJK3DSDMrakqkqwyu0xPddvS1iO8zK2oyms0q5zMbJDRE0ryd0xYmwyqOE2jff/qHguSTWzgLKpCMpyb7MVSS/O5hJpeQfJqs01HzD4T1pKuzPkAwqrSS7WM3biADdwSWhrtzMDJE2skzDSaSNIKM4tM4aHqG7ir9Ju6OPiqwSOTTbMSJhsghfbMBJv6a6zNnvhaM0kKYUBNOS9w5KuIm2nTFKrNGsFh8RGKqxVzMWpWYIAiGHITS+ia8zNk4a1Lgs3tNO1KxxvYmzbzzwuizbPD4OJvC5NNvJqSq/8a6PlPeHsTXwsCmwLYPwtOMyTN07nIcy4zMKBIIVnzMbm6TFSapcomMgDMkppPasBjKsyfOCtKw7OTTZStZ0r/zLtNSI1PErUj4syKms6rkrRwm18sY8vWm+prOKI1kghj/MxI5X9SJdg4TU71wZMQVLSbWpssmsYgDlXMm9KTc8tJqzqaEesV85ianCytk1Xy+02cmvkaFx1bTAbIYap6tB6b+hojy3+MZpvis1vLIpqCmjGq4yOkmkdL7fIhdDabuykE4l3zDczJAf3KZfJfTQ6aM9jzI1Kb/l2zkosjb0wzbJrTcaqmmXYRbRvS7VtNJpttG7cscJqFkmWzbGLHTNDAFbPmcH6bSPDbk1xifps/OKDKG6wE4KGamRvq7SGa2pp86/WNOejzMibi1Yw/fDSq9HXn61GaaVKO07ib/LLO04WbHpus60NMVrnis45K0sxJmmbiEzJWmimbXtLSzBSbX5OLGt3N4pt1m5maC/MeUj7itMykKYsz7zwumgybMrKcm7MSMnPB4wqbcZq7G1tMk5rQS/CalHDLs1OqBOB3IIBKYFPImq0yF1Py6n6aNZpnG6braMwYmr4RQxqh8GnyCVFQDGFBAdnycpnTYM1s4S28dxppazCap3IPG5LMMJ3gC3czg1j6ag8yiGwAzHSsTzMimrRYWIsvM/2bvtFLm0KaWZsHwObrtJpUC7Xj6pqcwVQT3bmmmysVbhtdBYCaO5sEmzXquEJwYW3iwLIqm6z4TutRzFeCC3OQmhqakzJiK33ji5pom9VqfppsmwRrb031EcI8+rNYzYRQB7K6hK2bBnJ8RROaHBtOa5LN/JqaEguNxJubbacqPZuTC+crqZuimjMrC0o2msDI+GqDmjRq3MobTT+5/9PdYqObujg0SzuMGhVDC+xrFeq8crCbnGqsTU9gZbDvKgEUT5pluYQcfGo3TatAXspONfObLhOCauKbp5uK67kaQQG/8sBbRxwbnFcaaWr8/BgrQVKNczChrCRNm0hSJizmgMhyY6q2bahlo3NtcvnSOcwqE+SKumyLzJqhlIv6bMXNiUXUi9qjjU3RExnS5dONTOE49dM6YTPMV5SkUhhb9C20zYBF1FM2rfPSr3iAm2Raj8j10lCS802zgcoyoJp9jTCh5IkjaxUErs1f4CJzz6rVjM25VBLQmn9MA5ssKkYzrU1OCoyyr5OtTYpVTbOwLGnVeHJ20ylSpc3LOVbjp5Nsc0/MJuK2SsFsDAhLmjyznUzjm27TzvnpTHgdiuOfiqXM80FtqwOy/5V5Tcpzv4qFrSYtU5s066pb7WjL6hKyJi34CTSwI5qBbO2d3TMNi9Jbi7njmwFTyU0KWi2Lti2BKA1hSrPNTbWC67OtUmUs+jQQNWqyDSzFQFGgiEsXU4gssCSncknVBK0LBFhzvxBVbO/Mr8oDklP0ZSxKwbxSXZLFo6paEz1c46WiHCwbY/7rkrU9eJlwItPN8tLxv2NJm9WiCpC7dHGqyyLxLKS5aZsJq7StpPGhmgmtpNE0sUWqWhjJLRCJFktcjPAF6tVOyAuTHaLvzP7wt5t6ODxZqlqeW0WaZ6wGqaFEJOstwhwsZ0t3inY4n8zhFLuTOUXfzdTQAIpaIDuAkKzBW2prlmQnLelyAcoOipYsgXy8MrTyeC2KhWry9PNDLGA40RM8m9ksYlqIqncti0oqGnUs/JLWkuzzjy0nxe4LkjJzLU8kGKuvLCZaOhpTLEnV2KvLLUdzSkrErKSCjgrbfMSt1OPvC4SrDS1FWsSrBC2sJJnKpKv6WpXYggWqmvEsUsGu8ths76U/OWISSqoZW6Rb2puaWp85WVtr0PcKOVrg8VdSjwstLfSY6MtpfZ1KenkDUN1LxptBLCDQ34r2JLhs6LTia8kl5puPLZHFbxM/Cpisw1OmM4UjPixXhJzSY0pzLCZbNwufLDmhrVqXEx2s+pgVqhuxzptBLVyNF0tTifpaNOUOq6bVdcw5KAuLG8t+bftw7HzempWsFOA7g5Fp7qriLQQFZxPqSuQst2zRMndzQVq9Wl7z0JpnW+QymZtQrP1aC5GybNI4htFLyr0jBC15WyvKq1uoFHNql0Fhqs1bO1rZ87ta6LUbWpCT9y3wUq2S/8DLW2ThM+r87Y8sV4Xu6umbVVp1mhlI/W3HsTVaVbLZm0EsmGEtq22M9VobUFFaM6z7ylYJtuKFm/8tzVv60oCt1bElmolbBC3Jq8eSOjxHWk8h+Os5RfstqK1Vmy+lHS1nWzHqtZuHLE1i8NraW7StJ8RDG/StOVojG7dbFVAFikzqo1vAKs+Kq1vjW07TzC3PWzZSfLITLeRynOolLe9arkuvLZVa7ksRLKSD31pI20Ety1rx0gLq/1s+yOuz6xo1Lb0g6xorMqEsQFs7U8Hjj1oTWrualKxNGkgqoVOMpDb5M5tZrBnZzlMzqvEt8RAVU4nTlG2EUeQyputQ2sjaFxqkLedNpzNXGhctopuACxcyo1qNNISKSmzU2g/z/5KordgKaFN3M24sIVPPG8stFbhIU6OF+NtXSjCxOK2E2sGbrNseLb9bSAvV40eh+9hfM9ii5Npp89eajVu68hNz21uY2jXrESyHwIjK7eLUrEc5uTL8WuQsliUvm/StjRx38m+rXSx4JSqS1JoKkYFAkMsbco54N1v4M5XsCpB3Wrty1Avo2g9b4JLv9bzaCtvbWzXYiMogak4tpVoN6qSaxNt42+BqKWNBLZ9bbApXc/hYNZtomgEtxNs0miYsAMPWxVhY9Joy2rDyT3P2LdTi7isvcuNaYlrka00scSrmKsLVdNucBHiw5+KgrfQa2GtQ20zbIhtf1XDa6LNzCllaBByPY+zbOtpEaqQtetuKCgEt91ruKnxERtpxa48txtqMyvzlbi2/08zKUy3m2n4qAS2W2+Dz21osmleyftobsb9b0PIzLHVbMFpLKylQc5QmCgjylNs9nILKdS3y2gxK1U37cGPxKFplLO1aGbziyx1a40ozEk41SizdW9FrkyQugXVrRQrApTDsUKNmskUdi6Viym5qyOw0UdV5shLtEmdttXOea/ztwTGQWh3tkMCFSuR0WO3qkzBazQuTwLJTDyoXbEYodmqks4sdr3HLwRVKYxMn7eX5LSsPbadgCwtOErwdYcHvIwkqhB2/bKaUXSsqaOTtp8Cw8pZra2wJULVqvBypPQ4r9Wq97ADBlgtKEx9tKFHt6sULHmzFjKXLt/VebDRze2u3TbptDAI6M6sT9C0K6kZKGxO6bUjwjgqna7psChknarktoWyqmvBzp208PQzzRqGEylFsMfg3agzVbyj9SHdrYCsvbfmosGIJ8rC4iWwIso6afjnc0QtcA5JY4rVttEQJW0zYJZPOUA0S0Rr443lsC9ur67psI9sQigiLMCWTDIdb4TJZbbLJELIoi0ZtwwTRM0z4Guxb27EK4hoH2voyPhKSG3FsVCSWk51rm9qG0e4Kr+OzbPlN4NPv4kttERHDWkoaLWxL2v2AjhVtbCqd/gsbbE0D43KjatTtQtFLivbk3W3IoLASAqv9bB7ZejKAPPwJu5l/UtATv9qcAggS6RL8CYmxl/KsxKjtH3SyxN4b+k3TbXqlsYtwTFk4WhlXU1YbcW2V2bTq4hIDuGVstSvYE9XD3u0920A7XhJ92rebPhKM7dpo+zX3Ui+q222xhAaTZBIL7b3wvWqJK5PB+dtsqsbtxoNiSo3sDJS/203tnos/UowS5dsPSg6ScRLl28EwEpu87PtUU2vieDXaFwVuklwT4uwQYSgT/MGN2kYpBGh8Eh3dzOyEOrA6KDpsYXA6Fhsk7T3ruqv5E5LsHduXkuITHDtZeCjSJRKT7AZzT4vBm8dtCDp/CsOFV20EhSgTz9iC7Q45qTLuGsW5V2wQwdIr9GE0sVds5wD32wITs20xoyXYvhq1bT5kAvL+G7Ak55GIJVGSINGSOxWiwRrtuNTtAJUwOrEz29qErBfQ4RoGKrDB6zA/BDNLzDnSO39AmOuH2pGyv23mwSslATNzcNTsd8GxCoTjx2xz28zTiRtlUaiQ7qsUc+jtSJJHE9zTJOziIG+TW0o4GwkdqAmUOyUzV2z8O57qaFUCOiKCuRp/VVUxeVzRml/rVTApxd/ruiWLac84fZNQzb3hEP0187zj0UA0wCJziOr67QahJqWkc9vqMWxjtUHyqkAZs2o6Bd2kcrUbvjuT8RZSh+t3bOo75DKJ6yTsyTMJ6zy9G2111B0bs6mb7BI6yBu3LVUxGFKa0kbTVTBXlUlb6Btt7EbYM/OYGiY67YP56hY60Jy8Ol/zCWxx4NsFEls2Ogil9uLSWsjszyW8O7ALx22iO2ZSnbNOO1vb7ZreOxuou5I42y9sMjsWUqpbeTq1FK5KS20AlMXzI0UuUueRz8APkqZL/jqqOufy47IrID1wSCu+St47zx17G9OycdHJcXKyu1LZO7EKNNuROxzET/LfrdE7tOoRSmY7E3BSsypz8Tt6pDFLghxJO7SKnuxJ4Ck7K5pRDXDtjspwUpg5V21niA9amdJlHE1A3508211sWCHZO5Ob2joxNLrq+dNuOidKGFPb5dI6Oy2QUlh0vB1FOnAKRmzeOn46HTrjOgE6DFNBoEU7DAkoCla5kuxIsS9B1FPDBdI62qwKK+HZ4jrOOhyL6JzXQQ06DutcisjtC+sWwMNKqewtO7gyEzhOOgiT6hvLOXj18e2WOyJa7Tt/sFhKOitt7W8YKosJnKk6EopWi3Y6jl0j0hoUojoDOkBqGZ3o7BE6azvBO8M7YpMqK3k6YAVAkqzY3eyeO9fJQ+MaK9o6ZDGXcko70zrgyyKK55CzOrjKeireOt0MTRKZcGo70UF1ROqS1ZzeOzlhM6OGi7MdejpIswXa6zpabOTKD5RNO6xja+PelRtsZhHt/NTKbZ1WOr78uGoLaoc6b0l/Ku4Zxzr92qk70wqD2r07IxUYSpk78EkCC3UTdTv/Osvs+8tcjC5qRRz5O5lKFW0PO1oLZduRvSmR4FqeHUo6PD292yo7pdsLC9Xb3BvqO6EqkzuaO3zKVhM1Ozo6jdpmOtc7ado/hA07rD0xK2pSTToenDsKvBxmEFn8ndvkut5EgmrJKyU7MDuV29o6wCTpa/7a3jrAhDxSOwS0UaMRtfWvYrqEtFC9uaRqMWyXGo7agFqwwDlTn3J4SrRQ2NgmE+MLG20qQX1LUdq1bL9lo50GE7NsfxuJa3MK8wFMCljy+LK0UIoaTEqwWuy7xJAtKoMSjyq0UDt0dEvPKrRRp5Rvs83ajbQiTZsrwTsTuX81Wdt5O+SpGFoodElAxn37Kq18FMFvWE5qs9zrAIIyhSr4PZwVVUnaE3l8L+yOpe5rcpwpWwtjFstf7EbgThN6CzKcEMDV222dAjh2ypn9ieIQ4Llqe2OAHWihfRP5a5qdyKFqCyFrwB1yVcjzxWoQHQU92ytDnOGhdZ19CiX9CB0M0FezlWowHK2p0lJ6uwgcvSXQuw8cW9lPKrC7Dx0EaMoKNRJ6nA4dHJKj2h0cpIK2k/fbwhyFO/aL7WtgMLHYr9vP2hIdCxu4Ou4dhBz2IG6LqCxdGLq7hDthHf1w8zMlWgocKGRlW/FyzJ1k8H6KKh3+chQ70jP0HP7wIhLAO2UcQ/2Sm1Nr4VB15bQ7BhtVHRpVoYv8wPgcj4NQSotrdRwhuiw66R0Hgmw62B2AcCvaD4kI08IcK0Mbayw6rPwKSyjTKsqJHcq7O2pLbJ1TVkrWCGU1YDBtnQdrUpVZYYMBU9vuG4G6zTWJkxSM2RzpuzDTrB2huqsTUOOyE+G66ZKk0pG64ALyOzdr4VED3RTSm9uNurG6hbpKHfUQpjtPawm7swGlk/vbrBxuPazSR9ruE/aFhHJlZcG7P5LxG0I7mqC7KqEyCItNHY1piIvEu7wdu0ypG4rsPcQpArfaNOIFunxKmRoS40ToPrrZGrgcBSzOWh2SZbuJ+Z/rku3IDAgLPZPAOL27MKqXSzkc6cHM0+vq4bq0GnkznUv0HOJtQuIL0jMdrvHps/L5MbozDBO7Bo1xuggLdRqe7TCbUEuWyOoESx2Owp9K6ew1AJP4RbNDu6uai7qX68Ycbfl7u2WzUR1UkOyzZOvWHJnyFOrSuUTpVDl9G5YcXrulOsk6RbtfkxPFd2xokeKUKVKwnVqbk6vssxtt/oUVuxja1Ownu1ZS02zCAIejSltvup7Jw1u425Mdkbtc62+6TbsE2iocLbtiWpA4O7ozqyTbFRyMmXsaSzNVHf/EY5vEHJyJl/LbG/odVbtDOoYdGbu02407CVPB9SqzLRwlm1Zanux5um5TzNsWO3Hh47pnmzEdk7srm/u7unKHMquq2BxzlAHym5s+HAbhy1NXMrwc77ri69W7m3krqhALtbqTQlRaKHrYwaJsKeOG6yUd6HWHq7+7/7pIe+odrbtm66i7pg3kM5ebshyLUz8ame1HYAT8gJvsHRB75BrYHNthcOs8W5sdUmzPmjm7Zpuq2w+7ySEbm+raGuz8wBNa++pHHCdRpfJg6xccHTnLU19EJxz/4FJbeZC7OqNQXAzOqmMVAJy4kaXyxRs3HUaabOLDQ+WAf7FlG6NDOJxQZRUbykJsnMmzatgZss8dDrrPS0jdOJ13Tdri0BvAHcdxrIpL2Yt9L2zAeRuSoTp/HJ+EI/Jp63x6U1I5OyCcMxDyqx0bFx1MC9nqWuKMnLjavRrgnOaBFlIdMix6IsDmi5raLWlse9gzZApO8DEEpFMUCxcdOGWSi7tyZFB/eMdzVeponPx7RtsXHP1I8zPHcu5dF+WJgySazAuvHJS8S+IQaoScO4JaKk9Dcp20zVQcfxPwA1J72KzUy7BrDx3Hcb86XeuzbfIN93OIayCcnjguy/vjG21HHFNS5GtYWdYb+9Pl7ZgkYVJiCphrxByjUFwLXtsBetRBbJMT7EPdOJySetu77rqbk9Y6f4PmASW7NfKI4eldOMFyOmkzHMN8ndmFvHtbwsq7iHuwixDd2QAAiwOTMXucFVTCb1oiemmJe2Wie3Gd/tP/6z47frwv7DR7rHt6u50yUuNzQvft8ngC8sE7WrtUkO8a8BtauixA3HpK45xccsEFukTr7rtTwc+657vAHVUEA7Kbk9a7+pivSvE7mp1pG6/LWsMhegZai7pZeusAP0JeO1DCypwBUgUz7+o2nLg06+toUlad1SnSK/O7bZ2aSKx6xRpWnGtAt5pJe+ldjE1f2h467ly0WFQLIBrFnEeQm7p6nMSJynpWOkxcyOE9GjJ7gZ3c1TmbcnpWndSU2tLLQ1mdYIVWU6TCVp01ABNap7uBnA5rNlJlelAdE6z2S7frWrrgMcoywMoDnf7DLavYGr9cqRk/kjbaC3vh2Pp6UZxI5OCTV6EQ3bRp/cvEG3GdEzU6W6QaA5zte5CTdrzdKTjAx3Mm21mc3iG060wLU13b2ATJuDN4hQBcE7CGigwa/lzUSpraTnusTW/EuMrLzFadF/hKEk91RXpWRVvbfAtkRHad/XD74oILGZ3/uqhrwZ0Uy756+9wJUKgR/npGLMqd/ckLo8F5XN3fU7US1+KiG5pdF3o6kvVcCF0biHSrj9pIXdi12DuRwlxdNLiWk91qnp2WFdJrvWvGXaF6iKsYXPGKP+MSPNIJ/kgRuwqcJzDfuFG7BFysQmKbKXuu/V66AqsLnKBT8bv8XCSAYhT32zNrE5wHe2ISKbsjnARg6ko+k2D6VfjVuqed4IOpy9A9UlqfVdwTiDqnnclxvDvIOwBdEUFeu3YbP3tmetvaA3oZ5E4a+2qenV/gzwrY05edS3M40sdrIPoopGozrcKY+sg6kjsTnFyxapvFBVOcaFW8OrI67lzFaf/q5NIfnHl4iHPBGh+dxXvKOnqdWwSBm7TTE53jWz4zd1yyXdHjATIlkhRcBst44p+kNPvOOy9cNF29e4kau5x+kEO76V1ce9Ir19r7ne5sQOtKu9vYxPog6pBc/3vWO0j6ceCf1e2St922UFo73Hq6XBfQnHrnSpuc4PoJeuz6/xEN88u6WFw0wLdLeTMLnJI490snwwudxENpmsrTC5xs+4N7M52I+3HqKtxREG7SlTKCzLJdUuuk0HfD4iG3KMe7wvtamxE6C6ygXeoaanp0XHD66Boae92djDFFq9s9Tp28eTe7pN0DelQKSNvdnZL7N4r33NL7vLLU3UD7ChgDMz167Yt1quJiM9iK+mDapl0MBdjb4HxQ+lxRKlvDZGr7pOvfiv08JzAs+ppakl1a+yJyH5w6+kObAULI+hcFIdIgetz7x4uTyaXcx8HkoeOa3zyu+5j6kHqgXYNjZltm+rj7MHoMXODacHqQXKxq8uv7MzV7NvosUuSDf3u3GjiL9vpK4lVzqHrrnNIBRFPoe6hdceH+Ulrq/PrYe2Od8E2nM3iCagi6TZBT+uqWXIu7rxuw+qzbJ5ufnbe7x6tTnVlrpHtTnX3zKAvS25+dxQXycrLa7pwUGUCSzeMK+hH7NHrrnLOcAiqWoruc6RR4CqH6nTLiaoJbI5wfgR1Br6pu6yVc/kDuKyq6D5rRhci71d2hAszLGruZQbjkWroN3CGkFduL3GrSVspe+pfdKEo4u22carSrY0sLs92GOQFrVl1t3RvBQWugPWjMri3muyVcLK0Z2j3dffKfKtnc7EP8a4bdVKUOKnAyA916Wgxq2dyccVoKsLMFXH+w++Nayt1co0VjKrVjErnXQaRqbtzYwPnyzUpy3f9qPvJ6mgrcA7LzcZLcwNzvA0DiVjK+3deq3hvGmv7dE7nJu6HzjN0GqAarn6IByxr4kfK/Pf0ZVrryO0jsiN3vvaNLWhXT+mq0HjJM/f0Y9oro4qCKt10wYRCLM0vBXcZDpHKQi+lcN5xHqAtKan046If7p9uNXPl6iRvE4vNdtGnIi8kahNzpWiO7jt3mWTPL0TMxXUHgDhuxMzV73MQyum8yt93VsiwqMFNL/MS4HgErq0itSt0IQBcyuvqNNOEKdxr0OQf6PbJkW81djWnKM3YRSXujVApK4RToPIBgQ4LdcgYqiN1f2jCwJ/39GNf73dK33M8l0iunKTdrd/vOqcNyTIsP+9E4zdIsi8Fc1DBV62yLUAexCkorCV3yaSgLXl0f+x3IrdMjJV/7RUvd4h3SUtzduFiLAoou3X/6Rfq/XQAHOotHO3Fcm/oD0nMlW/uP4BKKqrzA3OAGu3PInTNd00gh+5t5QpN4B5RTxgO34meD+DPT0yVdqMQKS0BFPsNn+krT6MqBg+ddwgpYyufcc/vL0rO1RVz2i856K+sYBxySbxz7XFXdLDP6i41deTwP0jvT2N2v+6HaNt1DEuYqFt03yfUTlMtRXRxIZ+PUyi7dTDi0yqydNXs5zdobCPq7ACTYIft0q9ldi/qda/bcuwHL+7g6ngKr+lpEXgrQXUB5lNtvUi3daOR0qn4L5d3t+hG7H7yX3Z36ZDpBCnXc3ftw+7Xcl93JYWITiga8c8tTwoyB+1S1f9phirr7R8TyqqpLldyzQoSqH2UFXC37iprj+iKBbBPSqr1cO1qIOyVzBVwsgCwq6pr73JVsZgY9WsedCgd6U1wYx11KB/e7jdR5XN/Z2NuCmHlcV+tWUwFQx1y57CPzeYvT3VoGbvvb3Pwk7OuYnJFAegbdm85KPfoGBr2aepzVuUqp0zIH4nXcJgbLG2w900MB0t5Ly90h8zHTG1Pl3XxgtvtUdP6dw/stklTa55xaB4QLD/LdXfg1cQd/IyOAjoX024bdxngqc0C9/RgieHOrvAY061/yx52RQaQyVDuL3fBsBvLK2i3ctDjP2yOLWNmvU8D7SV2+YMaEE4r73G4AgAbaB9Q9lKACmq/dgTif24pqYTxDBX9S0krivbRE+piqarUH4gf5BiQ9xynJy2bzWNkACZlyykoE2PfZOmvYPb8zmcqH3EEBFQcTWokCUDwUqg4Hy93VcrASekvpXMy5Bt1pC6nc/HMqSy8cMt3GBvkHA5vl3QUGQxrnfIYYq2Usc4/dJQYtm8Q9SzFUkVZKF5PpXBUGAfPTegTYVQefu4/d1QcbkgU6JDxCfL+7lz31BgOylYuvPFP9sQu2+5/czQc1ir5dinG7o8BL1DzfzTKziQcFIZFldVMe/L55FAfQB4/cd/1pBimMMDwg0K1Ty7IFBmHCUUtxnEMGanK2W6TdeQYCuvj8kUBjB1ZrjiuL3UUGiUqTBvdDcLuYPWUGfFKpS/Q8BwfPe7g9b3tAW2q7z8D9RVRrAT21BlfT2P0rBleyOruf3eIHNLpGPf/Uc2MPs4/crQa12ttjbQYLQ6xrcZ19SJEqHGtY2O8KprugHD0GdDOWu8LBmsrWui3dBpgKu0OcQwfrYoByUT1rB6GLCPpmPfo19ou65EY9ZPFhcm4LATxTQYob5l0BPdSV+DvcnTN4qAfg+xP5kLo68xI9jj1yhSQ7VLxwmf96393uPQSBDQbSPBpMmVqyvebAYjopyt49uyW0OxmDE/gXatuLfPWEPT3aAhPd9bw9n9naG5pLvDxOoFYGvQZGPT85ukpFgkY8DqrA0sP0JD2GGDoywwfQ/DCG0Qe8PJJTMdL9UmsGCIcTB7w8SId1q2xzhDwohvJbdT152Rfrr4v2PI+5x5J5OpI9oNx8cre9yoDya8sGjT0OsYtTzpo7PeKz6wYKWrf6Q5oBfco8RvuVO95SPIf3sGTbW1Okh0LrRlvavVyGhzKpBkY87rVVU38jujxKdfTbMoaVdOuyrTvfB/erC5vpWns8TIdz+syHIHDOumE9rIZcUuH8TTgBgsPbyIffyCrKXIYUhwIKs9zohpXaRdrKvF4hiWol26482IZd+/Y8Qofd+8KGePL4/dkplTmRaqYTYjyUweeyg/vEhl0KdSsBPGSHZgsyh3qGryp1fJ+EQ6KkusP9CoboshFrhDx0h/xqawe2BT8qjUtmh9f6wHIHPNUFm/r1vDoluqpDWo08G9uCOnv6mTx+uITSB/pBESMG3QfavGdKwZtTW5+jWQDh1Fdrlpsovak8LjN9vE88u0WX+oCKLzwHB71aBL3xzNmSCdQFPHzUXPtjvJk8XYW8Oz6grRqVPYmBxHNTvAU9+AnZs/o6jT2RQe47gvtvgbuYoRpf+ls8dYq1OakbrjxWubmSfNNUvIEHO0qJfPBRCZq1G56GXYutkit9WLlUE5x6vocMBc17W8JteIBFdfMS0/09UQcBMoM8czw2AjkzMtKVPZgcMauq+0U8Y2mie3U9N1Jph49Loz3Rhtr7oz2ii9J7UuKVPSpAuNvvSwi8QKVNG0GHfCGm02T7jYephiPzzn1oUZDA70sqwpmGBZtdGhb7FL09mjPZ2z3ZKByaj+oF6wWHeId8B0Sc8Og0wCc6tAbNeBMGutrzRWI9PYLcklKKBT0MBCwqzAZKgoGH2bP4Bwi8/kAUCuwGdYb/wLPTqMujPX9BQJMqi+M8hiz2evSjRTxPBn8SfdJ3Pa2G7zvlhq9tiON0mme1gz2jOUwzIgaZPWkbAgtiBis9VYfPepBQd5CfOoyTYjzfeKSSzJP2PWyx7euyBqaH2QYQu/IGDPxZfXjKEgYufHOVFGtL/PVRE0ETKoq8hX0ugOcqHYM54kRtGLs+fQNyasvmh4ZAEcv6uzV9UWgCGyt8zQq2fajoOstiu1ZcwuksgW0LQId3hs4tY/qRfckl3GvgHIGoMwHSUx7LHr2XMg+yNBT9vJ4sedvMfK7y6oZuvIPENnME8yl8VSEqk0v79nyPsFy7TLorfSpk/5qHBQR9xzUtu+u85bmqq2a9IpJ+85ydjbwXithAWqv+UQmLybvFAra8vloNy+29TsAIITW7BqqKfSDKLcu/9Up88bvw47tMqbzHZB3K1nztipmTpcr9vdOhFxNVMit9czUkqzaqdXxtwbV6MriFvaGAiMlnS0Bc6HwvIBGrhv1gVRtbb4kRhlJMYLKHW76aer1ZdLTS/QMrvYAap1oOdHeH1qW9e8fKaEdp01dbdT2MMR0HKXC3Wxh9dlq180B9U1vuW7GbuEZMRp6bhv0IQdOcUao/gi1Zob384sma/byt0B9akyIwfF80CaoEXOm8KKV+OsMDFGmUR9rjxFxuvWIq7LIrQsh8SsE7u9IIt7zo4aAt18phHKJG03ozRCt9BaA+2bOSoZ19UCJbYYDHAvVhFzQz84xcZnw6ATNSb8s6g9+8tvps4KiHXZVoR31TVWMSfXJJiuP8wNBdjb0ChrlSJXWxvTCar4vVKLe9GmRaRuqcHbxykRuTPfA9fJJHzwcqWltxPr1elCyG6/CuR2S7buNjU2p90EcL87l06b2KRr2rLXT2vPG5izKzIPG86VjC6700XHyOOP+ToYJtvaJHwUq7veRMAIqS6mp9ukczGlOqST0TJALysur8Rk91FYq9imZ8easDmmu8VAtYi7xHuFsQvZelZDl1c1C9kbxL6VzaeHyJUPMyJFtUfcFHEfsOR7z6AtscwpJHB3MsFLhyFn27GYgH5734NHRa27yaoZ5GOFvnvd5Hp6tJRlLLnTOXm5c9nRtX6j8gZ3STveAwgJqzhYxGE1t0C8295E28OqCa5526Rm+aWzrxoya8M+QMUo91S73cm67q6QyfvXFH81nGRjxGl3syg/pH/YDa24oi4b1UqBQLvINWRzibJJz1YS5Q3HqG2ru9++GVR1xb2n0PhnXrYbxZR9QapJrSR4+7tBoFXLJHzwyUmtBGCgLr4tRGv1D1a2+iXbxVrD3qSvzxvEs5m9Nrwqh8z3pO8Gj1aUbmioBbZHy/UQyaWPWxvRix7etVBN89+kZ2pNTLaN1GvE90r2PXJSF8rUZt6hhp0P35R8GGsIaJ+IbTcIeDRh7c4BEhcpG9BCRcm0yq4Xwys4IzkXK2fUUgfJq3vLDh4kbEO7/ccjCn7FiHXnxkHFlTdQa7fN0kIfpMobXchX1qK+Cq+Xxfh5KbEQNlfABJWmp4fMdlqXKt0KlcAEb8snprdTzQ5bXKR/tXyCBGypr1vdO4csu4+k4HCSi8okjTMvOQR3Is5mtxIg9GKlqsm158hYdsm4UH8P3rlXxL4PwGycKayIbI/RehoPteC4N8sUbUEsT9rvthu5N95/KKavQT430MCTpat0eTfbfyKNJ8qm99pTOxurICE2OoZcGKLQefWPihoYppyqN94JIiE29GK3334JXL6ku3fL9EJhr4RsW5g5ptW9d9IxSyqrSGwgl5gWITZ4u3R9jw5moy3MDGBhJ6u1oQ44aoSjcH53zgxlqHXDwWHCmaJPMVPXsRUMe6hrt9+Mc8G7DGjnrqC9998Maoulj9+3kmhqjGhdHrY58GQaB4Rt8HDP3ox1+Hk313835qmfy9AdjGKwv/hiWQXQumuuT9AsqVS8D930cyurt8xMfghl18pMeuh2THNyrQhjr9qMaPRr0BKymia5N8nsjce0HKiQL5/LTbAkrc/VLsp0fQxpH8OiWyaq78NHtwxpH8RlJziwjGKf3uNH6K4r2NmHVzRgeG/Xmw94ZNBsL9CjkgOs9HJBO2vUSGeHxgUPdTsprvR75ho5oNyzYGlKDKxnYHQZBTTfYGk/3iMIyBfQYkxtLHXHqmaoT83LHFEpeKiXz9yaJHXMbSxioTOrPUx6H8HtW3B5N9rCRHsu67CsZow4fjKPymx/JHTMcx/Om6aruPhjYEbfmsxqL8GsfZSp/8sOHau0V8wvxj8OaGXvq6xhLYPMfp/frGxUq/h4tQMmv8x3z8yXDOIjYTAv2mxsS6WvzmxhP7k330YU8q7dqjffr0bEszEyX9FLpKuh4Ts/0Bx6hH0/01LOhGf/2ANeqrJp0AAoRbAfMOgkmhEVwBhuZDAOHAxkGHt/zXjOHyhEYIA6iRZNJTFE8DoxAEYG3LykKd/a+7ZqoH/KhHxPslxja6PcoQQy2o6Uj72toc/fwRUA9a+aBkfSWES6HOO+K0GAMPRmJGiwNCOe9C+HIX+wcpF+Rp8/ny+AOE3WTTx1vv/JxxXEcGnAHGOseuUQpHsMApxwvKAarL/CvAPZORm5gCck13Wk8Cn4QbODjiBGPD/WjgwqqN80mDabBsEmLSIpyt/Qe6JzFSRnhhVof+W3pCVRt7ynVRckYwAqXGSaoIgh+L0Aoz2UpGq/x9uGnzhksjx3DiBYvkXTXGtDunkuwMl/zDx2ZS6p01/WGDOkb5qi/931t6R2KGiWEsBFWyhkYp/RSxG5LGR9D92sanc45zpkdL2KsGC6IoAlZ6KauWRooDtM2ZMv+INkaX/UETp5J2Rg/89ccW4xvGo8Z2q02rZfAH/c6BKBt4uQXHC133u25HJcfGuIsbHkfd/SZH6gxQA2XGPkYBfBXHpDsfk35GVcckq7WhAUb9/TY5soZG5OvGN8cR+pvHiCpR+pf8blAnB1OqFfyuOFFLpvyFBTHSMUfz/J3HInJRPYfGd/MMW8nG40o4i+aDLkE0xj06Stzpx/3KmdJwgpnGc/MbqlAG5YXZxrub1/y6+Nn7i+t5x+EFB5vZRyf8NloTOsXSq/z0YRD7LIQn/a/HCftlXHhh78ZFR5SCowHYrdRT4Q05xk8glHtdOpf8EOFXSwXBF3V1x9nGVUeYAvNwhAZB2dgCFwUgknl4qr12MTlgDUZlkKL9kVpiK01HHcc7mi1Gh8duABwa1JoV/N3HGJodRgCEvcdYmg3GNkSwy1FjcKha2I3TgoNDx//G1fqX/OihB3qiguPGMerHeosCymyLu8dwKWMYJjedV+M0M6UCFwQLChNGZcfVk857fPoVxu3E8GtMndf95iA967qQaANvWceHlirkJyX0nisUJm3jgLsfx49RswH+eiKAi/31RkqSG0fv/QnGlJxPO+AnzCfDDNICM0Qv3Qon5gMBUK9i8JqiAgW5HiqImlv8QYVhw2PrpWLoMXTGGiZZc7YChdEUmiwmwgJzOvp7PsIuWeoR7CaD/MSJiiZyK5wmmWFTQPty5kLaJlXrdrwkAhMFG3r8J5oZGxrWegVdTgPYiyNGkII+2Y9yoienA0jxrUc3XHQDPrPOe6dbMVGfIfplW2A6FEwDu12zRrzVMVEVQFwK7DNBvY8TT2CPRuYn9zNU82G8liYC80HKUYLWJmnzXJuUgoRpMEqRc26LqgNDbeD7DierUhiHLf1OJ/pLKKvpAq4mGhunA5nHWsYfAhlV8nPVWgwC7rBnilKaPibjeBbzpQNT4ZOrVvNjg1zpWRuZy6P89iZmxlewEumFcskCmtXfan9HUSLCA/qpwYsAxg4Dcm1UqtICVkXBJ+NKPX0hJ1I7pjIDWigwWePVy+1LlgIb2p1LRca2Jz6ixptzx3kneEeVQpUBKarmm5+iXWjrtUaqAp0uJy555/t9vU4Cy6gdy1GG+gPwSR6GlSZYIGtbK1pPAgw9pUZ2ZT0nU+DAS4fb4GIMA53IxYbbW1YmlQHTxiwJI8eN4B8grqulAmZQa0uHWwICt7mtxv0DpSdQZd8T3ibBJk3651vnA9ICFSZzx6P8d6RVJ6HhWGNhJ8zSfcc6J3ch3uvRmmQDesDRJw9bIkcxUaMm0RsgXHEn6hqJm1Ym1dJy0xPG6cnuO8M6ySbH+43w0yK6A9vJpfK8RpoDn6vTktmbGSZdGpUywyVWJw2E43oBWsMm9iG9hyDaDAPbJ3FaKAM3OSe6HM1LJj5r55JQ2tMn3uMVm+XGVYlvnTWyxwLzJ/zTfGM4Q+Un8yb++wYnNhWFU6iCghmWJmk71wPi+9YnjOqXIpIDtiZ5itciRAKxJopaZAL0hab7vIatJs4msxpPA0cVzlMu4+kDySaRBmxCqSdJOo78XibceqsaUSc+J6FKwfokAv4mmxoRJoEmD/Oi6tsnT6GZ+gwCuiYbU38j1gNWmt7ihxrfJrGosfqiA8SRelIIetZCiyZfJ+LaogPfJ1hS+vouWID6PTo1x8eco1AXM/EmWc2Tq5h6oyaopwcH5gPUUXvLsAf3JhWLu6q0Iy4n4L0Eey0nMeuv0tnjBfq6g90mi6qKAyQgvUaDbEynnyF/2+R6VycffP8aWSdYnPDLfzMop8CmvCZopjImj5vP/dYD1jIq2/im542MewID5g0Z08x6SIOfJ7q7tAMf1buzdLsGJ8Nsowrj3Few6ye/mh8DUSbDKvSiwKfaJ4tGuydjKvPdYKf7YyBaJyZ3Czy6UKcGqRi7o/wwptcrMVDpJoVKLAOfIZRKsFomA+IKClIsAoEmgEY8Q40m0Ss6JgUmToaTJgW5bhVyuzwCJSbT+gKmZSc6U/YLuKbKp6gG2wJ1yglHS/w3AsjqcCeUgy/4fTqoJtsDyNJNis1zngKuiSbqcoZmgwAtjxrRAgZyuftjOssDNLmYJto6NoPbgThTUzrTghIwJeNQJviCVmqS2sZcjoNMwRbreaItAo6qY3IogluDHKemoyqDkpR3q9CnJqXzhkrbTIL6NUCT4JupA9GgfIqCI/0DA5Wu687cJyceJpQG5YJup0yHRYP6sOuzLIe1AsW5LauDU7UDsKCvihyG9MWk+ZyGg/02eF8ncwZCUclh7vuufKmDhC2e+7NTLYMX+VBL81IoAiKBfZrCh12CXKe2+qmD04qbBsmn3YVxBlU7cYMtw+QyhlstgyQEotpBSy2C4RTEir88IYLFZI07UILlC+38sEu1AqeEZwaEgnE5bTrSAllAXKb2WooCKwk7Gisnjlpb/T5B3fIpMzVtDf2ORBuKbOITBIsCxbk7Y2vKjW2tpvpl/Hs7Jyt9F9ps42PHeLOnGhPH1aLTUfI6r+v7ywOm7/mBWlKchkNUke7rpyaGQwhhx5K94igCPgzH6m2jradB4H2yi52j/FyFkkcq4rFaq/3uefJzKaazfeFapZrNphalG5LJWsmnDzUvJtmm5bg1culbQSa4Qt+CISY1AStUFVvZWoRCi1Mq8lGCedXKG8dGhkJM+E/jhVsuQmwqsMZuQkwEr9oxgiBB7pzQ+gBD7MWKGxVaakL4lCkn6kOLJiDHikMQq5Ka/iIHgcI5qcoRg75gqtwxCjknWXhGSnly5ENRpk0npQNB5MqMhmrGQoU5NIbFJjUAMKOdWy+m64fcO5qbI6abpxUnlIITBBOwrUvEPdlSiQv6mwgmL9WDW36HP4KTmAGHc8YaPWIalIbHp1dKIYa+QnsN+cdhhwVCKVTWmx0ntYpuMlf6V6ZfJ0taJUI3po6aRL23p1l4fcuRBgNSPbHFk0MnEEKWRTpa4KHumoZD98AgG2MmiwNB5IfTjcYwZv9V4rItx2+DhoRURzMmuELBKHmGJfJYQqOmD2ohmzhCNCejpsMCYJlbpgrTKydJipQQkZqCRoZDapiJshsn+6c12NEaQ8ZyQkemI8aLAx2bO8svWiBDwNKb6gcn9OTb6x9aKkKXpqLjxyb7Q1emP1vsnCBACGdZm369t6divTmblybBQzLAKkZDpkdTFfivisxiz6ZHpwumr6e06qgbtUM0sZeSrDlpxx+mkDOtMpWbA6cRDbDaTwMkZ+jqCNu4p1Jm0aaGQwmSFVIPu2+CGdUO+38me6cPivZ9wGfP+kCmiGbzwc+mKns0QyWm7LJgp/WBp6ahB2sDnkL0YJCn9z2eQ6xmJVOW7GpCUkqyZ+5DnGfzM5SC5CANi2TbamaZo6B6IEKnQ7KGKKZ0Zuh7tqaOQwhB8odHB+tQMafOU5insmYZDUcbgGbrh+cGi5sDpz+mJHoYQ2Rm7NpYQs5TuIqc2lJD6UENctCj61BGR+rrGfrmZ+rr2/1bYM8baFHZ+kBDAwZC23RCuDVHm3RDS7FEenBmSFOfG1BDQAfF+zBCCCFW66X7EEJ+oZsn5fqmZv3JkJKcpp5m5npYQ+IYPzK1+1ZnBtIMehhD+bP8pkRnBGfhp0QKP6eSlat7AkJOZ6wnFiYUZ7J6eDNfg8Axs4dWvMpnxUemehhnqmbAmr5C6maDRixCTGaz0sNHWmaNaywKwic6Zn8rspIokipC+mZMG54m/7VgUbbaIWcRw0SSDtvGZlwa+os5YqFCjidMmz0noGZXCrPdFma1/EonL6bWZiommoNiZuaKQXoJZk+SUgohejJnRGfKpmRnf6fXBmJnVcavYghGUkPpZxKnb4IHpyy6gmc6ijKnW2GAXC8GZqcaZ439XLp+Zo1rCqcXpkVmSqaBZ21npWYUhLcq2kKXmMVKcPJhZg+n4SqBgkdSEwUVS0pTf4PPp9qnEUJq/dHHH4Lvp5P7AkKfpp3bZ/wDbZMSs/pX2dEBlNlU2dTZNNksAbTY/LNibLj6T0TKFRrYW2diOgvE3ZJTyFzYW2fpKYKs3ZPMDftnpvBe7XwEy5O6+GzYB2dTe6cgT0XTuHBEB2ZDBZKAT0UK+adnFvHkqPsBLMTHKiHYW2YfRFFFflLyBfrY92b8xTIgPCnqEbzYT2bbfNgAeVIdfUdmw3EADG9n61DvZ0rYl2cfZ7ABz2fTiXdmx2cRQGoUPCjKw+9mb6QVJ35Th00A5hPYXqY/Z7fgN50D+GdmXrqfZ8joCYYHZwc558W3Zq/YMdgHZiAt4OZSsXA4B2eS/MMBFsTr4ZQ4u2ZPeFaBFsVIIV7Yu2YTeZKECOaqVV9npvDV9ZvBdpOT8b9nwQBJS/DnehA90Cjn6OYMm6CBt2eUcwDnzaaHZqDnKTAE50s9SOYgoICD12Y0CGD94ObGnATn5pjfCY7TWkvk5qlyb2bnSYA1ROaRIFQBwKUIKltnPhOOkWvT06E7Z6bxSsSYsWvTLOGPZ+jn6zlROHolh7JY5o209ots51s8wOf9uOdnvihM0vTmFOe059znZTk85mTmP2f9pGzNAObBkD9SMjKC5ujmus1PIgLnCxncoKTmR7pATNYo74WM5+ubfUm8568nF/mC52BhJdjWKeRhHuRbZ1hnF9DWKSmqYOem8KCct2bTGFZhAOaSsTk41igdcIjnSuaYYX25auY859bxAzD6u6LnReUvZ1rmruRwFJzmmXCq5nK41Ob9kZzmIuZKy6/TbOYzAOLmCCE0uIbnqu2M2fLmTWk3gcCk7cWS5/i05fB6JbNiuOcBzagUhueoFQT1RuYaFHbnIOZOiOlZVufn2UIR/2eQzYLmkUK3Z7fgc5QLrfLmoqjPZqDmXU2C5ysg/Nj45imN8ucggAb5dpJQU4LnzE3g5u/4uufFMdeEgedv4Vz49OcROPBA3ZJGo0bmdh2o56CwU8EVZI7YW2ZOHIHnc0LR5wMcsObUQRdnpvDSQKshFsX9/QDn2QHNJ47mb8gQkltnqMV5E8nml8vq57FZq0l45o2CE+lG5z1omDOhUtxR0Ofx5yjEPuemUuR8SeZ559jn4ITi5rByzObDqeMESef/wP9mGLA80EnmV5nw5gIlDAVW5/OkT/GO0spM0eatg2bnf/0A5vH0aufEaK2pLOcjDBTnZudpoenm9c0D2WbmruUrBFywNJNNXaLmVcks4UdnSuop7WvT+AnXZh7gXEft5/7zjOcu4IhMi4A250xRLOcu4e1hg7mXJDSx6ueHCNthSOfA4Nnqnef4tHI4QYGXUgFS4+drp3jn3kCeBLnmk5GXEJnnmvn6cFPnQpHE56Ub6hBT5298sOeLgrjmk5DW+W7mXfQQwOPmLDia5vTFvpzr5xfBCASJ5wmg6+beFIXn7XHb5ujmE43ayjHmVdht5rNcxedqQOPnh+cL57vm8eaBsHEx0gDb5qfnJXxZPWnnVKTj5wRoyuuvk8SQV+ZkRdOBdpKQ9FfmM+TnZ3oROeb35neQu+bFIfpEbeYsCLPjoufPY63mHdEV+Lr5duchNCPm/YHIgaPm1XD6mFfmhcFIhDbn5ApX5nhR12HM5/QYV+dRaFdmQNKfHXvmwWBVI+3n7MDbYm3m+DpQiHolBOCD5txyvHua5gswU+bYMBXmbGF8ILrnfeZKSobmuRH7HCAXZAwipNYpkHi556aMVgNm5vihFmzR5vmRhQX50jZwSedjrNLmwPoCFKnnYFDZ0FMlxrmfRDgXUF125mrytucsFHcLuBbfxAXnF/iwFpVpH9j3Z3dNt+dpwmtdAOZ5NXDFZWS8kQDnf9meBFQWw4DUFrxCsBfTSNyQ1BdLAP/5ZWRiFOLmQ9r15s8zvcDUFuPwOEEppEuK1Bdp2UgXtqQ+kltmgU1IFvnm8+dG5uaIXoPJ58YbVuf/jbfnehFqOIQXeIG4C3aSwgQMFwosceab5zwX4dhz5yfmKBZm8BoUAhdkQYnnRuaUF5IW24GA+G3nA9lxJjWkXnkz5u+kEPlJMmq4feY8cmzmxkAp5XAXCxlSuJbnkknryOPm6fTAoKoyJ9m/Z72Yqs1qFjQw8NWyFskg3+ZtXErnNHTr1IbnMam0zBoXt/MT59IZPaGHebIWUNqG5tIAnDgaF1qK3OZUg1OqbeeNK3MEVmT8so5NVheGODz5urKjUZ/mnDl5xJal6xC1uVYXSbBAODIycjGQFnZlHUHlMzlQDhZPYtPnoftdoOPnwujAnP0z2RVeFiEhCuYByTcnXhfMdcrmVeEw5VHnvLDVuZ7nR+YgFwJQILLn5goXOJAS5vTFUhc3Kbx0G8kT5vrFSiAaFrqrURdkQNW5B+Yd0ZItFOeZ53EWQnQW2MvnCOoaF9GgmuEsxFvZRiWyFikW3+c65uPm6kAC5ZrnfOYd0JkW7AT65gVCbecakGWr7ebs5xkWSSCMF7uBpDnd5huwEwUBFubmqhYxQW4CveZW514XnJHKFuyENEO2FmCylOf25pEXBqFVF6ZTpMO2FmBgJ+fxOA4XjkXLAaFTBXVeF5pSsOYOq14W4PD7sAjnWhUZFyMVkhfiFsfnPaBYKGEXnRfxdAfmshbUgNW4MAnbZowZjOfKtZ45e2cQ570WLQyB5pUAaRdoQJSSB+ZTsCHwDrB72HPnSVgFxNWhJXzv8Vdmb3tHZ+fRGLDiFou0uufyERFRX5CBUnMVMxZ5AQIED+cFBBto6ObDNLyNZOaQ6ebmL9ERuLEX93nAQEsXg3BO2WTnpnW/Z/MWWNGO531AX3FbF0ghkhYTBYVRWxcbPcsWSv1AglMWcjEgTXsXPYIDFv2Awafg5qG0uxcMkQAxkhZFUksX5Noi4btS6OHq5i21dy2O5vQIAixTF6jcmhbDqYvmIBbHYI7mUySPsaQWHdAT66/ncrFFF2eAgxa80YoM4+ZdF40WAiXvECvnjiEV+JYWlkXvejUWSSFQZe4kAeQ/F28W5BeaJOI6qxb+KrulbOZ++TcX2/m3Fp9Tfqc3KaHK6+CwFj55kxe9Fy/QfhZpiQQx12YktGgJZucyklcWNv0Z2WznfGCIlnu4SJsM5gfiUxfueLxV7iQo2EsXiJhcsAQX10j3F7hsdDRTJMmxcRfzQbB4c+a3aDMABxegXJcWD8FZF/MXxJY65yKQ2JaElggW5JdglzyFiLVr0ng0Vxci+QolwKTbgbiWWqRdG/nTLcI0lwdAsJeXxGiXjRKwFpLqhsRTFmqEvrg65x3IcOe9F8ba0uc/ObZK4xYXsmbmOuZ+oQTETxcIawEXCBbqOE8XK1Xwl+h0rRpPFgpVxhfaaCEgPxb8swsXvilSkD8XFyWoFtVGPxbVRp4WCVCNMCHx+uDYwQ8F+dNmgVoXlXBgCS3mO8rj5oXGe2fEaQc5RRf5gc+CUyURDZAXZPjoQZdSAwOf56nmIpdiaycXvLED2GwQnan9yTHnvLBmMQvnHZqphG3nyXUpFu5m/kAKFxuBRzng58kTwUzCl7Yhq+cTuOvLYJZI5S/RppdzeZHZrJcCJIcXswCkl2Nhv+frUKRb5xdeQBAiPCgLMVMVGJdMLWTmbRC6F2hARzmUFiCgnhIElis1U32O5zYVvhUYl53IauYgoE7Zo3g+lwhBHRa/5LnmDrBGYLEWIia45/NB9mQn5sbS2Jc7OcsWOzQWuRiWdzQn5qYtyJe5OavmSksW2ayXSOkTFy5Qphe9FhD8geabVcGXmCXC6QvnUbFSGTcWBMg0eVdnwi03FuvgGBb6xcTiTxe9IAAXY5ICDaKXHjKw5//AQxfZK50asOYtvX8WShdV5qDmKyVKFwwFARN+Uk6AiReFJBvnBQTOp4aXKUCbFxDUQ1QVlwKGrlLRYaWXDhnzODwpqCWllk+MheabgOAwSpYCkz0XLxYcYbWXZpI/F82XQZYHGj8XKUG05l/gYARSl6M44hd2hQWWRohJeE9FJL2f5mQchOcBC3qlNxfyuGHnFYO7XSmWA23DFu/4vRd10LMAlhY3Y2/nf+CiU6LnGbk12EsWowFFSjWlKhdTlr/IOhaSODFI3JckXZQWsqRaF1OWsgw6FtOQbpakwRf5XRYqZXA0Sxb8SXoXcsCGltSBoUDGKlZlJhaelrn4j02i5uYWNDhTFyrwdqQ2FiDhLOcmsPDhVJZJwvo0VxeowvkE9hdkOEsXX0luFuswThcnlpNkhhcTbYeXr3FRSIYXjKArl69wgFCeFn0AXhdglxCJLUqTlgmpYBb0sRKw/TlJMv4XYJf07Rim8hbWxL0W4YviudGXepefluDa3Rdgl+1oTJtp5xEX85eKO0GXrFpol8Xi/2fOkmUEs5agui0XKia/lv1JhZZiAMkWYFfROCfnqRZXFpVQ7NBZFvMWFOBEFnznMFawMj7nhRZG59CWDCy9TTkXJ5ca4ZiXhRcm5ueXcqglFhLB6xdWsBybluau5OeW6QBQ58Ro9bpTFmlMOhb25vFVOFd5AJbntRdFstyX+qjLCLmXb0RYVwJgBFdpEEYWj5cggi0X0gjnlrMAR+aJDLYW9LDyFX7mERZ75ohW1NUSMT+XtFeB+MmW5cxBFksBXkDJljtnR2cQ0C7FwxaMmCxW85NuFhrFrJVsVyOhjRdmk2MX7pDxTQkV52ZgCWxWi1O3F6Cw/vCblqeVYGBzFrUyfFeCaDkWyYOLFujn3AsS3V6XhMBZ+e6RFyV656zolMB8VwMwEBYeliWK0ld4eQvniySoVRJWaQIdlx7wGDx8ViW41papUHxXeIGhBHlSoqnali4K6GemlucWnFehQC4WB4H6Ub9m1QuaodcW5YvukdRRV0x3F6gVbFZocYQtupc0MoZWUgXXFjFFjOZI1O5br+dvF9dn2+jRQlMknxdsVnEx+sxTJJlV2BdXQdMU2zhqln8XVlZVTACW3JDy57ZWkkB/uMCXtmPukFz4h2cM0+sWnchaIN/nsskAlWxWd5EGqfnS0JYh8eDhIilIlzp6XlaPoK+XUJbCGzcpyVUFrUiWcoQ6VwARckiolsvpgVe3IN3H6JZull9Jn9iglzYWtnkSVvwlWpdfsermUWFHxN/n9+VxFs+VHcmElySWuuZRYXbcpFZEl1kWyVbDgDoWGReiVpdAiVcUllrnCVeqbNSWjjh8Vxf5qlYSJHSWnFfS2CUWNcFUVquoHGBMlrr4Fle3IaTzZJcZuCFWmRaFFghgHyC55zMATti6ltygtc0s5zMAJ/QslryWIVfGuWsc1iiJyAKXV0FSuUq49VeN4NVWS4C4+OyX6xDFV0xRr1tq5+KX6VceajoX/mHOl7ZWTphRV0mw7la7Cm+bcpf7Fh1WaJFilgwJipYdV5QylheCaW8ZbFcPhkE4apY0Fe6Q0c0cF44gmpYjVuFInhbaliFX88D8V8oSjZYdVyFmlxdR81ZWysFZlyzBaIthVk4UXFbCALvJplcbfODw1pfNnIZX2tML58lhPzheVwFZtpbsF+lWDhULFg6WblErVvozVJaQoPzEzVaPRVhFz2YdObFW0zA+wZIWzdg7edxX3GMnVnLie1f07DJXiYWWMZpWUviw5wGXmldJsUGWkZCcV/ZhC1YDcGft3FceROGWYeAVV2pACCl2k3dEnFc+MHWBV2fv6T5XaRH4C47mLyGlY3pXoJxxliDUXleauG0XypIpl+lX/iS0l/xXaZf/Voxg4ZdqRAx4rle7mS9xYlPZl/9Xl4FvVl/gkAoOVoeH+ZaFtVZWfpaKV37HvXnukTCLklfWcXTntlcaZWTmrhDHV4AbCeYw6EZhSNYctWTnpUgJV5lAWa1k53WWI1f85nWWt2jo137AilcyFh1W10KxFrjWS1Z41svnlhvzVmlsuZadlh1XCDtdl41ouOYki/RVCZZVcMdXWpqkVk8gA5f/V4bj0ZehAhTWnqjJlogcPsXukBwGf1flYZ0bbFaIrRITHCh+ibyXV0GsOEnEzNdJSM1WZ3VaV1zpRzmM1oVhzlfMgdWh4OXukSaXW+fMgPytSVeOIfa94OZsDSnnLNfay1qWK9jo1+1pwTA25xuIIVavgUx9ZRaFYYzWWrhtF8qxvlmk1sVASCDSlkUXjNZzlXYWCFf65+lX9NceV/kXCtaXgFLXA3lZFoYB4yT8lpSXNyiq11/gJRe6x9dmLBhaa+4lSI1HZilAOgEVFhAbVFYpQclCnVf0+ermznINgLCXVGWrJTRJ0VvpFpZFd400SfT4oJZkeesW5JnIgebXEIloFj4gX3C5Vh2KiBbq16UaZWctVuW4OtdkQTA07VZTpnbXJ8qfxRAXAgWM5vZkomQA0sOAuOfkFm06+Rbqeb9mJhd4DE3mGzC65xeW6GFm5yLWhtcGoJKRduZuurnmsUkRUACWBMlPOaUoxIgM588XKFEO1jkpQaCXF4KFLOe2pYihppbocKyWmUEYsBSoeVNQxr7WZvH9cLEW3sIs19IYPqBs51ZmJ1Fe11xrFLp5U+KE0VeN0YCmnajfnB7WgrNDbDZXeHhR1+nkDWHuJMQFDtZ2OBnb7eYjJLfYbLHLW2bmE9ge5pqwaW1YF+zFtfk0SWpEDRH50rHZmtf3ZBddK9L+8Q7WyYFM4xXXU8A1197YYefu00KW91EM0RTnhReayw7WhzQu5hIl0Rbo5pvJhjgilvnwZFZ21s6WcGnuJNLlzdbjcX7mAiR4Jc3XqP1G0iorzdcnxVqXRj3x1zp6heYuUZW6IfBa1wrmxpbzRMwprEumll2ESdcswNftz2aRNH3X2wNk5lmgL0TMKc05q+b5zPJ0zCmh4x0WrhE51twDdlcb51x5NEgqMBDXZCBX4jXWeWV41ti1cRbdAefZCZc+wTnXhBBww9MXt0D51oYFAFZaq9SxvxAu5xGCOLj51ziRdFcQ18OUbdfp5buiqRfZAZXXxHBK4SzEzdgX15FAeLQ8KNxqWdY4uAJkdlKZ8w7X3HiKVv65m9ep18nWOPwZZaUop+Fc1s/Wk9cgRRHmuEM4wZXWT5Vll9xTe5ax1wFZD9YOakHWG7BQE8nmpqXx1xASMhYn5ffWYAgu1xWCY7j51ghAGDjdkyGpe9a7ycsXWBBDFiojxZaB58xXp9eTVF3WFoJyMDXXPkCU1yRWqdYqMVPoy5LnAL/XpdnDu59Xy3H+13qlW0WfV0dg7xaYcsG0cedIBAPW5hrEVxVBzdaqDE9XTUHYN8xxyxaC10vWt7CF5yHkgMTMKGyXkhdAUAvW91HlhTxW5ilzpnPXmWMC1iTXzdfSCDRXDNeMoDXXq0d4Ns/l8DY0N+DmYDFMOvTWytcL5vQ2fthBF/IkW+aG5uOWv9deJWK5ihZTl6fWXLGy5ioXhMHx1zmgobKXM+oXp9eofZoX85U8NnEwbDclw+4XDtZV5tLm+heP10k1LdZ8IR3XI9dYaV+025Z9AMI3DAnWF+AjX9bMNyPjB5ZWFplAHqRsF8eXJOUO19Al8FeS2WeXp9ahdSkXF5cwTUVBUO0ol3HCiTjyN4Q4ABYCN9DI8jfVoKo3nhch1zI2Mi1jls+X/tc/OSmZr5cD2PI3sMxzl2AoiChBF55DbKefV3qWxjejyvRXojZZoalCZjYOGcPmwNaYyoI2wZBh17EXwFc8NxAk4ZZz5II3fUbiFnZHrtcvgaAhQZZQVw7XL/2l5irX8dcpqjiXZJZa55JJLUHt1krWdtfljM9n8ta5FzI3XSVYF7LXijYSvLgXUteoKYo3SchN5uUXijeE+eNX/+w2lzI2WhawFnhXOdaXfUPnBFcjF6uDKcLEV/6Emjaq2MvnTRaBN+Tb5Fbx5tyhXmMAVkCU8jcJocEWnRen10BBZkYWNkUgYAiXVzIXRjdkIR8qJjdxF/xWmTepNl/gM3XZN+/ZkERx5lY26OZFl/SWwFenVwXQ71h35xR5xLEHQTDXDjdHZu7nXXiw5s43+TYDUOU3DxcfOSzm6aaGom8W2ghlNgsbPdbOFZjEJTcB4E3XBXnZVxU3YaGI0+4k5GG/ZiGD8sy15la5jObjgx5qPtekwbU2GdQhNwJhfpb+SAMZdlfKsdDCXTfr9UNXSaDW1wGT2udd50HhtTZUhlCXwoBJu8Swa4MJ58RpTFBZN6HgRfi15v2NwzYMRXbn2jK5504CS8l258pHwzdl+qCWb+azNkfVAzHlN/nnFTbnk2WWbOAvFzcpLIODy8nny+fDNwZS4hbj8CXWeQJXcKIXIOHDNgJgwNb/l8Sxv8C6uLk2BzfgNyY2/ZArG02XazbHNxXQuTe0aWZQZzcOSPtWo6uC1lSQkSGnloU36uZUkT5Qdjd35xU2LrIJF+BX0Bd3Ns/6pFanOc/mcrGPN3bmM+e1NziQ81Wv51+tizemy7WXwOB1Fa82eUFn5w9J1aKCsGg9BddpSddn4qbINn1WTlfKAhhpQ1bEhP82MhSYB2rnUWi45jagWQE1Vv3nuzfWqggX9VeLNlkazOYq5hfQXTYfKNKW8gS65kfXE5f50h3ntTfCsahkteYYlCU3FbkBF5t5+hGItlOzCzZeIUc3lJ0Y5wtSJ1G1Npi2nhbpVyc3cd13kDBXtTe4tp43CFYh8O5m8KGK1wS3xLHD8YdXKFZQaoS2wgFgUe3W6FbwtkGg6ARBN5hXFTcwi0o2lRahNmCZr11251RleFeKmOPB1jarQq02W6c7YNE3s9eKmCMlinhNFqI3xLdYnTDXLRbUt0GzXZeJNtS2zfwn53Hnizf4tnHm+zZMkaBleNaMV0k4XCkNxoXnU0FxFniAnW3DFpyJ12d44PoRDFeKpGpAt/APZxWDiUEs5xDj07nRl4Q4vyUStgNxwRd4OenXphgl5HHmh4FHZ59ZysFBlltquuZMKfXqqRcskLjm0sfzgrDn3W2M56H9tYBz5+WE9IVKtheyPqBo1ysUurdgJRjXoOa6t3ch+W17F3kARBRqQevn9pbW5sRGIfCzY0jZDxc3yXgWLYGNaADL+ukcyermvQHMqrEXinCAlGpAdUMf5tIl+rbQ1FFXNLkp2RK3Btml1k5XW3zpw6gWVSDSt5RqihYq5vfG6OdvAMUxQBZsYJaJXreX4DaQIpf8lrnmyXxOAPVX2ZC6t6ao1+ZVV4czQbf5qKMgyBdBoLq3ENQ6bWrmyQABt6xHutbvhB638ngTJ+3nSsU2tnmkNqUF1vqQurcnexw3WGmDAIm3nSVhNwmEibcB7bhW43Acl77B7yVzNpN4urZGWMjqnamw4XG3kDH9Zp2paOCqtgQw2eqXF4TALLahh14Z0daqdFm2w+XHFynDv2ahh5DmE9ZmaeG2YoiF52zhUle+tr7hnVMWtpRxFbfQV9RpwwzVth8gkjfUwV314bfzAbI2APAVYeG2KuQlF50lcbbswYgqJuchklEgl1RRVyU1bbdgUC4Wn1KtNUG3jlft1uPQWrYlVeOd3lcFoLq35E3qO2zmdhZDt/1WnVe9NHbZNij94E3mZ8hRtjEEE7WXJcbaurdvGBAWz1JnzRK3orYAltsl/bfv52VXTTlml3YZaUnI1/8IuKUStmO1yxa6+L4C5rb9gE6z5bdVtzco6hERoKRXljFThHO2FXnXVohD07Z7gbLmqaeJ+EO3SDbz1nKFThfHUToyTzeZ+GK3W2bytpkiZ7fQyC8svZYABcK2fraeOQmXP1e+ttS4vpY1qVkXW4AkYfc2uHCMGKG2coQ8trChcbcthP2WDnj2IeG3RWsw12WV4bfTuBXWoOZauFG3LcKnzX5SRbTVtghAV2chGQghtbc6O06XkYUVt/mplbeGFvm26bh4t1ZmFbe+to0oDNbBk5a3RT2pvK6WEtj5t0sBy9eGQZZCibf9cRc2blRntpNpOMtXZjuIL7b2E3jX3MXal/e3QwUTFyIUUbeWqC2XhPHcob23frZQN/0WvRbTBsUwMhd6l9h3ENR8trRWIfG42JyIu+c8t0dnSzAkFqe2+Tc3KMSZKkCntnEWurfv0/3nCRbkdz5Su+elN762fOAalpE2ZbevSJDyebbUuER3sMBS2Xbn04kluM4gobiNa0bSp430drsENBfD0k03JHaOABK9HlZk479n6DzGLe3m+xWM5oYYIPydNizXVwdcxE3nECH0djoA0O1r03026OYXUXiFLecfxIJ21dA9tgpawzfCdsFh5GDSl73n9HbBKO25Zuate3EXh9y+LFM2EA3sduAwbPJTJTM20nYZQOM3jiDX40p2zTOv5q83EneZHE82z+a65koGsyAqtqxBPHb+E9mdoVKCFtJ3rClHt8IW6nZhWTs3sNZ8kAL0VDfJN+x3R2Aio6k2y1H/ZUK2uHYbsdygAreydhZ3V3umdtMw3KN4dvHmaHJo9Xk3gtemM0e7aee6VfR2Y91P1zZ49DjOIG84NBcP5w837HeLXZBXyzdudsAq8Vdqdx53MzQ2V4fIueYp3LG3inZfNxJ2zTbHlzZ1PzYNWfERzBfslz3YziHzATldALa45zjpCpHdV5Kp9Hf2c3RW84NNp/h239pV0zyWELbqdhQZgpZQtoJ2H0WclgZRmW00KdzEJRdwtqx2ZSn5Voi3EncL8LCXswC0drJ68tZTcmi21HZYRXM3E9bkdsKgqLYYt1e2QwRx1nBWWbZMoQc2BXdgdoV3Q1eeN+u3E7Htt942tHYPtyM26/Gkt3xIPVYDN75Y+bdhGKXqEtZDFpmGEIUydjhXUkBl9A9nH7GU5763naXtYeU2dRdSQWGhHRYNFrq2PMxQ5gkRbLdSQE9SWzYUVk13gOLz1ndGtHaldoG3NFbx5ruYfCk2dlG2ijMHNy2WQRdp4ymQ/RfZZfR3yGnJuZ9XZjs+dnt0ZxbLk+6ro3fswDIWfgMs5ghdaOE41yDgFZRM6NswyZel2BGXxsFRNZY3sIX0dlohzHd6EGA3EndkyMtXDVi81M4hMxDvfcnmOaATd2lJUBYk5kyh23eWEK+WHpcggdt3BmhDdw0w6Vn0d9cEo1e0thIwx3d0R8cX6zhhdi9A22c3aGo553cPEqA3t6ZRaMd2F9Gft8oSA3DHdq+RWpbGxMd2uiZRVqrZ53aUvF3XhRbYtCt2A2nt1oOFo3dJocwWQ6Bet+x2n/oDVkKXlnYPBSM3/rf0d1yBKCjsl6Nb9Hc9wi938CjfNRJ35QseV3TAtneWBJAHK9OjeQlIzEBax8znUrhc2eD2XZcydnk4Mdng9pEh6jZywPNxlDng91yS8VYXnFD2TvBsrJm2MLBI9vpDY/nZtkUzKPa5ZRG2IEHYlwD35ImqVxj3kDGY9ivAa7d+Vdp2uickt10FJqUA9neRgPb2xc+XK3HHpQznJ9PsdtLlb1dN10SXEnbYJihX7JQXqqT2z7E8Vz232EB/d5dB5Xb9tn92FiseV4igSueBGUt8wVYAcNF3PfEYsS3nkeejdyym0pYuU+rm7arSN2UkM0cSdk6AmSeKd8w512YIXNe40uaz1zN3Cxn9opcWUHBcd02aKVcB2Cy3W3J4NpcWwvfs9pnHvopVNpj3Stng91IGilbBodj3EvYKE4Niebc9rSj3p8HXtxa3Xdm82QlJcvZ3to40ZtfGwQgX0deKFCt2Kvd7F+okYvcB4ZkWLVO7mPz2/IlLOX5Se2LOIMTs3BZHpJaWX3YExFs2MaejdpNoYbb6xErGzPZNAoHn57d090k3CZZXtn93O2F41omWf3aPC+A3jLWWdvo1vtFXZgujAPbRDZGXed0A91iYpTY5UwD3lKXvtx2d0vYMdjYlLMVOiV7Z4PdV4ddWTdDo9yL527d2UxrZUPeHMxjXiUAh2JL2SkM+9iRg6PcMBamWIKGD+b73WFhEUSdXOAzo92CFt3Z+Yz3ZUPfPsHY24dYu9/kkaZZPdQD3tgUTFwMlPPa7jZK3bMFywed3rDl7+CY26+D89lkt7FfWd2/nieNrp6xWLIB/dlIiWHfQRI7ZCUhpRdfWGsWbefD3+202OCOXVLb68BAh5jf1SMuJefdepWO552aaRwlJP8k74mqTyzlu91UxBISU171TKPcoRbzWvRHLRoX2DRbz10Uh+kXF9nvEsOYDcEQVCUkrVW43rvcxqfrYDfcYU1+WVdkJSEHpo9YhFoX3rfd6Frn5n0St9yEJdBeyqwr34rtVM1eXA9lB946xqneMF86BKPdk4Jdxoub0FrZ4rfe7CoYWoSkt99uIEsMj91QWLveusUPnHtcf2bX2o7VmF/nAU/eLaNP33HeKExX3IYNYFjuUffbvC3rnypeSEi72vyHQR3KW8KEV9+27WBf74L8lmfcv7ebXV8BDVZn2GUByllVXemMo9z3rNte/di737Jb+t9KXTfdRoLn5/jafAChpKPfzeHeQ7raW6vzwZW33sVgWbVbe9uk5NYee1q3RJ/YZ+FJ2MykS97QhS81+1k91Tfb51VuaapYpAlD2IQg4ebl3ySBs2UwZLvXWF88Wb8jP9h9yFgx5thoRH/duKopWxxC34N/3naRUNoW1qyUJSRlIuBfZUkP7J/a4GqRXjWitGgAOrohrtpjFh/bVcCkiNlfCwyj3b60a12VtkA+7XLCXhveQDpFDitaoYZAPbOGnl+7SZAiF9mD8DOfU9qhU2/et9H5X1dYu9i6ybHZpicqjFfc9oXU34e3d9vR14DnApMGhr/buGLgP0Peso8X3EOCT9igo0WEV9uJkqLcZpDn3LfnQtjIrl/f9Ol/MbxcPkxX3fUlGlxpnwMW196v7Zxam5JQONA5qVkAPy/biHJsXu0zQxcX3WiOr5tQw4fdl9hMdLMQT4yQPdkTJNolWi/Z5KzDWZBy81Zn2b4VW96K3u/fxKQt2lJO79z+4lNaW92gO3Gp8D2lJsA4GyQBXyuH79qtF91ZyhVwPk21em1Dm5wGQDryq89ea/ZAOPNC75rpXJ/dxrdu3GyjYD3ny8NYoPGX3X/iHF7RFwUygD+3Lexc5Uf/3Xmy4cIcXqg8t92oPQhfZUqRM3/djrMwPgqBT9v5tUvUz1r4pCve0ICslQZY6On33gFLpNue5ZA89RLqWwDfX1IX2QTTXd8dXQPdmDj/1QrdLAVz5mfZ8sJTXzFaZ9vlZ/3L9F4oivljdemn3HuS+WMdh7XfWdlDgd/cUNUzXXFeYxUwYSmUA1kx59REf91nQl7f8Vyrxr/eESOFINfaYxR/3KERhgHu2MFkuD3mFKJeB9pLM21nuyhaWX2b68Q0sO4lndlXJng/xYIH22awpjO4Pd6KbFgDnLg8MpNc2lTaREZ4Ps8BBDwFAfMkaDylwe4Chllq43vZS29TiuZbQ554O7yItFleFMPcp0PNAhHcI5x/21PFvPMjnUXa+WeYh54Bo5hWUvlgqGi0XmObZD1DEVHc45x/2QKSudnkB+OcuDot4zg9je4kPtpRH5+oRGjtlDusXD9bF99ullbLVFvFVTBiRQoQOvzv3OPUPvGnt1qWWJQ5QS1gWIyVPOPUOYhQBVw159GBFD8lsxdcEt1EPYQ+dDgrXoQ5REN0O7jdlOY0PpL2cl2rXAhim2VXnAudjF/IZ+lBaNqQUGTnyGb9bRjNi5x/2xbj5MRLm2nYTDsrBgPYBOvJ18hnuVay2fOnKnBMPS1XpF4rniQ5gCZi2m21u9vqE8hT+turnH/a7yVOAmVd9Dv5s0kV4ty4PRx0a/UhWaw9kG90OBULzWHPqxdaoVy4P8cyy6NSXATc9DngFuDiYVgmH8hjkIXV2NEPyGefc8Vb0tw/3K3xDoWTmB+opDh/hWUUu51Nq5w5S5ddX6OITDrga89dZOKmEsw7x9LmWxWgTD700jBcRg/7nLg+ORbEPgeYlDjNtONYh5pcO5XhsFhrE4ec9DhQ5eQ6R5tjZAGXK8CzmJ2ZFdvrx/2H0YYCPhuY9Dvzx/2AbBKNWZXZQ9/9hrDiaFqS21g6XaRE5HlYuxS33wQHOF00PQpAQjhgMzlMyd9ez8I/uVMGhftfdub73WOcTpXS3e/Xwj79jq3g8KR743vbAj9rzGI7MwfCOxFo5FkCPoI8aZxGbmw89Djb3mJYtU9iPLg50Uge2TohEjz0OaDifNg2MncVMGHig2w7nSUnZH/bwdUF2HtlwOeSOnuceVwD1iQ9k+Pj3qMQvbeSO7DudD3ZN5I+yyAF2NKW7DrVN7pj5Fl0PrI7gIfiPAhnxdN93Aw7bWNb4sJYld8EPE0S7D773YoNkyibmSHE9DuIg3ldS1/J2nI7ZITAPPIV+DnuBzlfEaIXBiQ8mlfw2S3m90QIYMFJUNvjXAhiY9IAPbfZ4j4kUpg/ewPWn8I/mJDB3hVYCFcQY3dMnZuiOB2yWdkiOUmiSj8BBFHgeWcv9Q1fjW/D2URrf2E3mk5nwj0GycPaJV0CDyvHTuYqTbOcX5TD2MhpjwnyPuo7r2cV2XQ8WTGzglhYZFpn25wnt/RyPKPCC/NhXII+7D2EqGBfgjxL2NtBB0vsOgMVWjiN3Utbt9Sjxqcy0lhIk4OpQ9k9h6UHHD+M26jjOj5ASsJdx5773octTgMLX+cRQ92dQYAnLFhvIgmyE8PDhORtel7SVTfdcsM7BdLc+jxL3XLCtNX7XHeS+jgwJenvt5xCIdtiE8dI8NLbAUI5NUY/b92hXTpEK90DJuhKollNB4Y5p1eV3PI6NKrhwJRbJjogmWjc4tvzwhHXG57iOhPGrmJ1WqY5uN8rXLI++972ZyIHFdsB74Y+G82hW5hb5j12bwKSqGvmOXIvt1/Fh//aU9CUMdQ9Bj6WxVD2ZN4mPETgndnKOzo60WHz3Fw+ujrhDNLjSl0dW3va2ykxIPtZRj/NBscqwlh/1Xo8kUEOja9M92rWP93nmG2yOoI8o8EZh/2Qmj3aOgGHxD+sOja1iAMUAigAIAZsBUNiIAOAAoYHSAZwAAADcoADsAUQBYwBAAAABZbWhDjiW3bUlpNEkPAAAZcXRuZbT4JOOpVbKIOOOVre7TUiwk46D2P5A04/d0MOEWACTj7dqGAFzj6H9mOfLjsWpoxAYAEuOa48TjnQogSaAgXOOVJDMCZuAqRgTiLHYm44TjguOxagmBsgAO457zLS0K44bj+gAS45VV4Vhu49bj4ePq47gzFuPjfHyO/uOLyBepiePV4/jjymqW4/KPcrBNAFHj45EdWx7jjmg+4/Tjq57FIAdOTbU9GGnj/SMN49Y+HfRqAFzj8OjpOyTj/TtlQBLj9VXziTfjqG4R49eKQyQw1brjk7wt44+ILuPy4+J4DH4yiFvjo+PAJiTj5cRVJFvj15BC0Svj7OP+AEQT/OPhACTj0+Oc46UwKcgc0x7jyuOp49wT43KHeBQTyBO0E9wTyYPQMSvjvCSQwE/ju+PqE4SeYeP6E4zjy+OEnknj+hOGGgR2K+P347/jtSAd44LjphPE3DIAEuPIqkJscBPNokkPXOPgTXCpcBOJIGYTq3QGE49AJOPnzL4TmRP4WCAT55BhE9ETjAVj47UKR+Pc48ETG4LNE+wTihPpvFHOcr4f4+f2EuORwzHHJOOuXsbjxRORBNIT9a5f48MT6xN8bDfjk5HNABsT3QJLE+x4FKifE8ROPxPlE902DhPgk64TlEEVE9/j3xP2sRN2CuOFE+m8ARO2E9uYaxPgk6oT40Ar44cT+gBc47DHeJPzPlUqb0AS48jxbDUJE+vjquPRFgyTuROtE6D2NOODInzj1UAyE6kT0RYLE9SBexOFE4MiK56547AE5/Y444e8VpPKQAITjpPrzCbe6pPaE6fjiDQsCYKCE+PyE7qT4tRV6DYT0FS0k6+YJBPWAHsT8JOvmEiT0JOek+VAPpPbCemTgJPvE7qT50CH0a8T/ePjk7wTg5h1k63j2FgBE8aT1xPlk87j4B5qk4YxICALk6oT1ogeE5iT7RoAE8iALJPJ476T9oBx3DWTy8FOcLqT1QJnk6vj15ORE5SaQAQ8aSvj+BO6E9hTuJPME804o5PYU5ITlJPyk6ITqWw7k7KTjh6ik9hTvFO4E8fj8FPLk8WT7FOyU5RT6pPeE6pTw0dPk+x4AlOpADJTo+O2k6h4UxOyU9WTzRPEU4mTxlh1459wGZPU45UaZxPL46Hj4RO+k6m1LM72k+0TlRoi2OH2JOPxk7qTrKWTKAZT+ROZU6eQD5OXk42T7HpTk4fjojJqADqTmjh6U7KT7JO+k8UDdOdok+WT7xaFk+qT1RO+k9cqcaOFU9JTpuhuZdMgQuPCk+ZTl1P84+6Tvbx8jr6TylR7NhpT9FP67BIT+5OMJnOT8hpYzUSIBJP1U9f2R1PW442T9mhvU5eTheOm6GcTsNOA1DST/cgqE5BTnZO/4/3IItjGk/ZT2ZP8RF0TxC4hk/FTz85lGtao6VPak9LTtmga0/0T/VO04/v4HeOM07bjmFPW05NfLVOt4/v4VpPMk71ThBOq08LTk1OAU/odBhPUU4dBMFPx04bTiPgoU4UT0QRXU9CTl7ih08XTk19Bk7RTiNPRBBITueOVAV7TknD3jXxTj1OW04PTmcUSU+bT8dOd0+qT7JOT04TjwnYrE4/j8dOl0+qTplPb09nTtZPi06FT0QQqE8wTiIoDE+3jjBPwE4elzlRPU71gVhOgM4rNfRhF47lTydP3sB7BkuPjIW/j2RlbLOgzwDOFRlLwQMx+45gz8BPdZgEAUeOLE9gTmCSQM/7jgRPYM+G9/gBR4+cThlOwGVss2+OCM7nj3DOKM/jj7DOFRlYQoyg148NHDdOaM8wzgDPa47XuS2AjICYz+SwwE4VGZtlCQAQzjxPM4/25bF9aAFvjqhOuM8wLddJn46UTiDOaqSEgThOy44VGNTOck//jpBOpM/KA2jP/45gTuePgM/0YaBORM56JfBJH06N1wBP+M+/V8TPdM7QznLmQM+UzkhOQU4MznjPV0DcznDPIM4czyzXDR1CT/hRWdBhT/zPu3Z8z8jOWE4vj8LOZM40zpDOS0iSk6ROB49RTrKk/ch0T2dOFM/szqQBEs7iThlPN2lSzxROqE8Cz5N0NeGyzpT5cs7HwfLOHdHoz1TOrM74ToxPPE6IzszPgk9aT1TP/ZyIT6bwqk9YzmLOnE9bBFxO50gSz4JOM4/uT/VJBM98T1lOIM6bfU6Axs5+YUJPIkMMz+jmw4QUzu+ANeFiTsrPws8DUMxPRZGT8NhP4s5Wz9JPDRwHTgQIUM5PmHLOfM5uPP0Bik9+Tp55+M7Yz2gA+k98nMm51s/yz+pOpU64mNMOss5aTmbON07yzgQA6k9t3UpP+M+WzoSB7s7LT77OKs9+z0RZnE9gzx4ndk8mTxfkDk83N4jOfk5FT1rOkpLmT35P3M4EZnjPNk7DhIrOgc50zrsolPkxzybOKE9hYTFOJs8YsKbPJk/JzrrPDM9uThpOfM/xzi5OBk6eziHOuymNT/jPtM/RzrlObs5kzwFOMc/ATi4L4M9hT1lON0+zmNnOvfBVTwXPaFGCzqlOlPlRTn6jRs4xT3rOds6xz9jOiU4Zz/jPzs/kAMlPiU8sz2XPlc5tT2nPsc+tCwQPUc72zqWx+U/Kz7XOWU6+ziDOxM89TqWwec/hE4LOJU7hTgVPGs4czxlgUc/QzjbO3c71zn7PSc5atV7OyYINzjVOOc55UjbOlU4YT6jOmWDpznVOrk/w5WrPDU/dz2PPbs7NTgXPAc7azupPrU91T/rOSs6boWdPys5hzmFPF0FdTsHOOaQuzr1Pk/AYzuPPAzH9Ty5Phs4Ez0vA6k4DT8b1+M4J6qnP67GpT/jOIs8jTyJO08+6z+uw5U9rz8jP7U7HjhU4s87RzqtOc08ZztrO444LT7tPRM/ezltOnk4mJX3O/cgXzxHj408Dz1fO/ZB3zxTPH067TngDWM6jz0tO20+izwzO+05mzw7PD887T5uP7k6Oz+vPx05/T6XObc5nTsOEQU/FzihPF0+BT0JP1lANztdOo6elzzvOf89B1jeDec6vz09P2MC1z+wadc/HTuJPH85lz9dJb06vT43P1c6ALyjFzc/Uzp9O/84gz9/PRBHfT+3OV85fzw0dYM+RA2HPi1iczhrgarngLsDOos8xRZ51CEFQzvjPutX/MpgAJM9nT8BODrFhwCZO849YLp3JeC6wzpzOQnXn8/DOLM/6VWguSM6cziSKxC/F0KjPuC7+E6WY6M4sz0QuGHRYLluPVrCEL+OP+U43TngvlC94zzQvlcA0UQ+OJC4YDKQvz49szyF1ZwQNT/+P5M/AT/rhyKGUzwrPFC7OVg0BYs+4TsdwudgNAXOP3uSsLwQuDC9AT2ePFC+1JQhBzM+CLxgvsVCCTmzPkE8idUrE6C6j5VguTMtoL1zPes6/zpQvrYHoT7zPPzFCLssB6E5cLz8wadXyLgLPFC4bY0uBIs6sL/QvMi9wTyJOHC/bDfODEs9Iz0ovnEvazsROWiRyL+IvSs9kTxguGZvKLgrOSi8iL7wu7s4ewU7OFuELCvouqs4sz5uKzQHcTobPpc43nMIvms5mz1wuhi98TzrP09RsLnRPnE5BTmjghi9mLq577k7hi5YRQM5gjv58xi+9wDRRps7OLjYvtC4Wz8RPBi/zg1bPui5StFovfE+STuou3C9kz/bPHs8/MVcxpZlyTqNOGU5ujlLFLs70zueOanV4LkHP1i5PYV4vRFjlT+5O/3RSLz7PIU+61WEvOk4Bz2U09i+RL4/Exi7KLnFORk44lxguadT2TqZO42DGLhYu8i+RzlXOVi8eLn5Pnc60Lgwucc8UBh4v7lRJL+HOyS+DCn+wCIAuTmnPOS+OLnkvqS8YLv4vqi/pz17Pdi9pLsho7c8YLvEv3k4jz/rhVi7pL4FO6i+FL3lOgU4tTmQgEMG98W3OUS/KDefy6U6lz/CpyKDlzs3PPzE+ZbkvDc91TiEvGS/W8sUu6UBBLjXPbS6iLslPeS4ZLkUvTc9n+IkuFS8tziPP2gHYL7UucS+EmeIvOU6VLsYuoi7dzq3P5i6DL4VPBS9/VFov/c81z1Eu9S9lThMvpi6CT8PODS8TLhh1o881TxguQYJFLhPO2E8cLs0AU84jL34ubC4zz+kvTsAlL3PPE8/FL1kvC87DhIEuxXrTLljtiU0ULvAyOC+rzhIxFC7zL3lO288nzvkvLi8jT0NPFC7NLx3O8k9RTmEuky/rsAfPlS82LyNOR8+aLuQuSMF6z+5O6y/cLmfPDRx2Lqsv6y8Xzk/PAy4sL6/OzEAHT2Qv1C6rT2cuei9hLhERGy9cLo0vz86XzzMu+i+Pz1G5cy/nLo8v185kIIovh04fLq0vrYAXz8DghXbqLzUvAIDfTz/OgK6vLsZA8C8NL4sun0/XTuouxy9QL3rPwS4CQbQvRBEQL0ou/S4QLpT41y9kIGCvt06QrxQuVS9vTttO9C/qL+5ViK6gr39VMK8ILsCvyS6jL79OyC+lzsMvDC8ETgAJ5iE7L+gurC7YrwkQNC9YrswYF+E4LzTPT8xPITrBeK9RT7FZq0BCz5uPBE+FrE6BxC4iLoaN2K+kL1gu4epsHSjPes4ZT7f5JK5ULhSvZK+fAMSvwE9eWbSudC84z8BOtK5t+ZSuW46OeTlh5AFMLhSuSbCUrywvYi8M3Cyu7C9MrilQlZLHYZwuBi8/6/nBbC9XQWovKKiQmPgu/C9iLiSvXK6CLvRPuK6tgcIu9E9y0TTB2s9CrqTP3vkcryQ3WC61TdivUi9IJQyuxzYirlFg0i7Mr5fhUq5fjxhPmsTHYYouws48rl8IToAqL5yvcq86wDwu548pUPyvGi6czyzYbBzSzxbPCq/bgHiuRi7Wz1yJB5WfAHROCi+rTYKuui40T1yJqq6GrxRPqs9cie44vK8Gzg4ucq9w4mKuli+uLkga/K7WLg7Ocq40PBques+yr1yJ4J1hQfYvjE9ciU595ICuL/xPKWour4JPxs9ciXauQs9eWe4vRq82r4JPRi8FTSQFpq6ST/OO2E+ar9zEtq5+L3utJK4BL96veXEFSUEuuk8Krh6uoS+2rqqvPq6+Ll7Oqjo8rnqurYBBzlnOBq/hrv7Ors7nj7xaWq+xLtpP0pkxryHPes/ErzyugYDZLonPlq4RUVaugWBjLjav/q8VL9UujK9crpkuIk0Orsau4c8prs6v6oXgLsnO6a7SOGyuBS6Nz9UbjK9FLpGuXq4ZryUuUS/armqu4c4jzv6vYUG5zkMuga5t+fnPnc9qWASuRc6lLwPsOq+RTiPPdTgSr40uPS4skHmvnS5jLlyu9q9xThMuwa81rq2vXs/ir8quLS8Tz5mvLa/dL6NPfK8lryXP4U/SmfZAiQH9LgmuHK8JEYMuma8uQBKvwy4jzwOuaa4LLnKupq+GLxlg9c5gj3WuR2ATLxZNDa4BoHMuGOCJr9Mvva/Mry2vo6+RrxMIcU6NTjMuLa7/jp5Bnc9xryWuay7YTyuvjq4bL+NPU68drsvPgU43TjdNwa67L9c4PK89ZUSvhy9XLnKvzq95r/sv7k/5m52lW86jT1FOZa+mrmcuby48rh6ux68XLuGu1K7TTvuv2a9er7NOty5yro6uJk73Ll8vFK6Dr0tP+05jr+Gut8+rT45IMa91r68uG67JrohPny+Hr/dlZa9vrwqvu687TtfPy04MkeaugYBbTh/Ooa5Er/NOAK4cYcBONa79rj/PQeBBTyfsH68grgzzAG9Drx2vMC/vTk2vBa8vTgivZ69/r29P0K6qr32ugk7Qr7CvCq+lnT+ukG7bcnavUG9gr4Augq7XryBuiaEmrzBvQK9AbqmvHK4YrwCvXIjwb+gAQAFrZlTY1Ng02LTZtNhTgB4leOcF8iQmhkEOMV0WChWDADHZg4GCsLgWj+HyuFXZxG9RNbfnjBXX0lzZxG7PfJbnguixTJRvXAPdhUjm+lAPt5Q5xG44p/DmfqK9KjRuCGBe2QEW1+X3OF9gr0KG51ggefcEbhlobG8GvV7YeG+VZGxvi5n62YOBQjm9NgSMGnupodlQbBdX5XTAlG+LUf7Sb2Z+o9zEIdj8bkZZxw/DolTXz4HOE9/KP2Z0b8+3gm57zGUWlXFTgbbW3YCpYV5kwm5ViCRoTG/oxwnmL6No5kxAMte0JpJvIsiD2YD5qaCOOQO238pF+SJu6TxqOUjmiSBcy1JuU8G6OT8uVRpkbuRYIExvZ9krjStSbymqx60/Lx98PG71YcyFt+f64ckgShWpoNyxCxfZK/TtUm8498cPOwlSklZuyzRvZokhkzka2COhdqY/Zri1PYRWb7CEuBYab4O3StgjoBfR19fzQaI69m/3t/Eptm/djjcH5m7HDp5ukAwCFeZvlDd45/IRMAfubqucJDUOboNx67npaPW4bRcElwcWOm/GjLdmIZb2NDpuv+rnZk2OyQG82WpuM/u35t616nBqb1kBuN3w54E1mHPhblpunm+6+Bk5am5VxbTn8hFv4DQ56Wi34W9Xfm8jmYZuF+EHNy0pU+DEbyZu83HRb0bz/m65xbWWTMqN4ZxvF4GuZp5uOXlPOCOgPqCMFmjgJvz0boGoSCET5y4IWfn2bo+2iW8IoQTErm+f2H5uaeFO17Jub6X2QJ5u/g632eZum4Gnl+7VqkdSbtu3Wm9N4IwH5m6mb3Vv6SQmbplg/Yd1bq7X+W5ViS3knm8gTrY5am9l8RjmxulSGXpuMBWQLYnUObCxb46A/LPVbwih0Is9boXB1W76EZCIOm7G5cluXmPJJYZvvtgTb9bM9DnpaG73dW79B01vrW6Bb2BiFZVebzTHutRPdEVvF4HsYoFvvC7xVUVuqBYrblbUTm6aZiiYfLng5BVupHyBb8NuEWVVbk2qx3EVwv1vmKwnZqTBsARs2A1veqVlb4/kzCsub/pHxrm0brNQ6jitb9lu8m5vSRZtQW6RpoFvt0CTHLVvzPf95pOK12BRb5pvyidXbsxAQW//QD7Unm4fHcFNam7miVSWGuE4ZYNu6m8LF9oAejedbvoQSeAXbmDgEJNJb+zEF27qm4Zv5pgalxMKRmF3bw44U9azC/LMc2/nb1dvtMztbvDQJ2cTC/yKVm/9gUgXeKB4czZuu5d/VbHK7W+/a0Pm6oqccZ1uLqckbrhCUaFw765u+G46dyW4I6DV0P9uGA3uuU1ulpxI7iW99W/6Rny46O6FYRi4528Bb4SZajlnb77AHtlUbur53XNqb/9btOaRVDFE/W9XMXVWnchPIJ9vWbenbkWqdtlRbiuE8m48xfBQjtlFb7uYluZ6dVR0mm4pZZMNIXXLwKmEp2ivD7TnvZgtXVludMHodaZvdTO/EVJvgDjbBP8rYLonbhfMwZSW9VJvyWCQ6+R0Sw+db41pDX3kdSCABiqibxtMLO8PkrZ4/G5b59Tvr3BOgO1v2EGpPSF035K07pmtv+d9K1U14m+ZQF4zPy7p+Idu/hn1UOdmZm5e2KVvK3x+Mj9mjSunW6mg68XX1o0rwINSbtdCuBZmbk1pKu6MgBXX8Y8/yFZvb1l656GOD3uS7ltwtKcidI41AGX2b8cpEW4Il8EkHO5Y5cVuAkG5nSrveRphbxNvKwSnadOrzW/WzZtudGilfKHUvskA70rv1W/zb0zvyWCzuvNuT3SXbra2lleK1GUEMu++YRpba25CJSLvuWFxb5uhiTQc7qLvwW8G74Z4/G9Xwb/nm4qpGQDvJL3OVgdu4PBc7yQFPZdHingFrO59FrdmswtCGO1v1u4XbiJ5nW9yVFpEx3HLOIbEp2glopbnt28WDrVv2ReR7nLARSVw7kUlqZd/4TR8Tm/6709vycylbVTuUaDybwL5R3eG7uZJDG8tgD3YJu9crPJu56c+b28BnFByltSY67ZK7oi4Qe5HpUz2Su9Vd5juYUhc7wWlE+ZLASiYXO/uzXjvi3MW2fzuh6sqbyOhCEFSb4TdbhczcYyg4u6fOG0Whc5rNrVv4u5p7+udHuWpoUHk3lY2Y6XvMu9sXJPzEFSB7uMM8m8OSeys+e/cu63vxmWh79Ybue8Edk7u5OHX1zJjnJGa7qYs8m7sQgtvCSnu58nuMPYw7iikLtaFz6PYVO4Sb68WNO4GURXv6zCHZpT1gTmdb885vFPkdFm6PG8HKADBCed4dKKXLm48hGfIjO5O9LikXG4It71ATG6Eb0jneHQ4cExuJG7C7k2U/O7CAx2MBm8Ds4LvXAK+yMLuKRZEFZRutG+b7ohNY+7z768nbysK77N0ku6GQKMNeQ524R6Ty++PabLvXQTOplOAHG+H79OJ9O6DAXhvm+46Wha5PG93e9fv24H17pSgChC3ZxrvN+5CbkRHInW7XP1ucv3HDikwQ3mDbtXTfud10JBM4+/G2p5u4rdThPxvihg5bpyIk0y37jaRP+6+yYzZPG7lZAbuX5K771fvXG7zb2p0xG+qhVSpU25LbvZuVzdWtl/vFMr0bxvu91I2LpxCa+6sFDHv/MAXOgfvpaN0Vh/uI26zJrduDY1cecRup+Cvb3qcCVGn77oonm7KDodvjIFWlypu7rFTFEvvVJf9ithyym5JDZiXDXHZAOLvfaroH3zi8u4rJGrnm4tPYZPvS8GHVvHvv8EV7sSJ7++yJG9uVO7CAjwLh+777qhVxG/mi3jnE+/QcExuXiGJQZvv+FdAH4MkF4Pc73Puym4/ZRPmhHQ0FYOBbcNn7lFuGsR0lgwePO5Mbo+2LO/r7jPuKjKa3VQeY9JQHnkBMJUhdDIYPB7nyD7mY+/UHxGC+eOH7oBRR+5k4A81SBcn7szIXB8pbQvu4xrw1Gwfy0CaForuV+9cI7Fqxm4q7gfukjmYlmruRDCGQHsBKJaP7qAeP4AdOWfucoVFIGvuEGEr72hQb+6UH2E5q8YomYnua+80Hl/vMchkbwlRP9zzbzYXnG/MgUx5gB4a9jweNZde7yFbUuJsHsXDgB8gHlwfE3AV1rlg4B5cHwTgpB9hOLVLg4F4eXI70B5chExuXlVuFzXpcir2HszIPucIHjtvwh4Aa7tuolzKbnSstJe+76geB+80ZzxXR4vYYIZAs4Gnblgexh5mHyHvEv10HlyEzm8uQPgfdB5YEKbu3oyOTDQfMUWu7/39Bh4EMXQDT280wXw5mh/HNYRvH3TzRDQeSLBI7zJvZ296H/QfKm79mGXVx2i3V6du/u4Lbjag/+BF7qpvv+8Mob4e8R/LwEluHB9p3PEeBFF3jGThkWXkbjAVKfk2Hz3rMR492eAe/B+NFtRvOYoH74Ieae6+91vvv8MuHoxvAdhcH2IfzG4o2GEe/pTS52xuCYbSHgggoJe7C/XvqR9hoJYWY9IMecdpGrei56WZfG+3Gd59Km7UQIJu8B+zTOdnwm5ikOoebfrNHtfX51q5H/tCS7WfePkfQQUpFokhQO+FHkDkLO5uUQSCB+/XJOL3Py5eIIDEEkBocW9WjSvlhExuBbmW7mZvx3AqHoUFcxxDH1OAYR+UDl3X1m4jp4OAG3qZbtJvSR60Ths4w8qa7gfv9VGiK10eFBhMbqkVnh7WEXTlsx4ILAbvKNbk7u5m3SQTboBE9AhjH/ywE29qmLIfYx/kHvWmYR6FXQnmIW7Y2PYff0Sm7xfwAB5CUDIIGx5RveweYgDNLJ5uEwUxb4UffGA5F85v4YWaHmry1x+FZDXg9h4BUc1viW5hHgSye2YpblBwTG88XBqW6W8X5c8fycwG7w5NcDnfGD7Y+x4gPGMem1S7HtVu0x+E+O4eYgA7RksefMh4HyRq9kUrHsHFR2/Y84CeIeaVb/FuSx4X0aseaassbtpX3HV1bxrh9W+fZ/MGRMpNbgfuXkGy50HVsMsfHuoObW6uF88fblOu7i06QW6g535K3W6c2BgeD4h97oFv6zG3JrkeBGFHbxVB7BE3H1cfRR90bvcevuGnbjk5Kdk2HlAlrR/yb2CFzx6Kq7nu/u9GJcMfkW+t7rAqPB97H9kecknpHulAliCE7wBQqCqGQC5Qf1z1FT7A0x//H9ke+g++FbMeQJ7ybvARax4HgbCEOReSbtEfnkMD5vJuA2nzHgqtytc7Oucf5Ggu1s6is8RjHn7AdR6u5RMenx/VH9xuiJ7+NmxumVTydTYfRAJUn80eeh5onqcM9+QuxSJvehCYn2yfeQYLNYEBxMQsnlpYSW/SGI4n5J+ZHsRuKkBuPMSevsgyniXRpzYUbibVgQEoxetyMm66ZZxugs6CBDJvOJ8ubgcjy0FsnzSwC25LSQC0bG9cOJRvSdabgJUf+hI8bmeY7kgil7sLcp7s2d4LjXONmAaevQ8UZsFzgp9Gn2GB0m8CbmRuxkFqOAUemcYO1xqe48/i1vfkkp+6njbwCmXqnlJvNp9muA9njBWfWvafK3bZ7oSeAB7rMQ+liR5jwyJvF5ejEMSeZJ5qb+IjVQUL78hpEQPKnlmpZ+85a1IfM4EFdAwf0Tj2n2addlZz7ptXNp6KG5QWhHQrCR6fSYtT7svvNp4UjBPuTUGr75Ge+KFV5zR0pFqUbjdJhxd77nwfcZ4TV+QO7HQi7omfCjjbZ0IfIm9YFfGDInSTJZaf3sEYsZIfv2Phngs72dk/LtEMap9FHKFWjSugSPZu+tbnk9fukA82ngEitJZmb1y3z4AAmDMALO7S5EKf+FHd65vvHchVb+Ij5YRlnqHrkp/ensqMb7Uabvae5H2stokhTFCHbwGfAHm6b/OLQZ8jZfDn2SpBhBmfSbFadMZuuo6hnjJqwu4qKo2ejgGGiP0el6r2nsijVebtK04pz4Dxn67xNrTLCPRuXPB9tJ5vdyC51OSg/eHVbtfXwR5pn3MfuMamnmWRe1rdcGBhqyWBAPgF3m8DMC9FgQFzYsznLSjNhXOenZ6FbqDNRp+PNAznBJYSMLmfUrgQDiGWdwV1n41p1W4TMcKxdZ+0umOeJNnn+FTvNZ+3F3YuGQN1n36eiW9C66ufKyArnwzNSOxvGTc11W70hMJ9c57eoAAXLSlJWeGeEkIBHq1Q5Z7dn34D9TUjZJOet2g0Fhjx3LnJnwC4OW7Pl9OeXPCxeIlvIRupnruM22d7nmBgD54asuifxNVZnnCNP+9RaR/YM5/HNUdulL3TbzrWNcE/7qtEc54Fn1PumjTI7/UBGiSm7t+5QIJvGUNu3W9J5hueJHjdb9cTRp9RpOieAvUCtmx5yp7txbcXLJ+C7gmzVzEEn3ifh57RYMSeheJRb6KQkkBp78Sel54g0RDuqm6pbwBf8O4UnrmeUZ+yn0RuvZ8xnlSfRzk5HgOf/edKn89vQ5/kDwUfA/ijn/T1Dp7RH+OfBJ46W2U4M58SwBXWhgHlHr2fTNbcnuxvc56SNN/mNR65n5eeOhd1Hqafy576npBPQZ+Wz9keIp7gX06f1p/UHlWe29IdHsaEam9xox/qie5vby5ufqOjq9PVtJTEbzmimZ91bk94UW76UUmUbW7eFImeHThTUkTKzriJn9VwLteNb1F2tyEkBWfXQdX+Romf4PSHHsQRfCBkbqtAi+C6Hs+Z4l9dJH2enwC4cFJeutkwOtoeHF/9nhTh49W7bn1L4l6VddVuAu6dxKJf3hwg7m34Q54GFHCcp4oLtUJfmwN47xdvnG+cmaE46B/h7y+fEby+7mKFKvHJnzjuBu+hH8mf1pIG7xMJER9JOOSg8F8xHhqfil8DMU6qMm9oQtxeOyhJfSCZji+8XxnrfdqZH+ucAl9SuM9nqSHCsHZewl947xhfQl7JUkjuubZZH2zpDk2t771o8l7NJprneF72byWAsl5Unkyfnl5jwhZejp+KXpXZSl6lHqRfJYBjxNRf5F8cXyNFPZaUXlUfNRVb2sFynG7aX+bAtF/8nyFew1fKdo0eQp5ooVk5dFcCbvUeXPFUZXjvx0wFQuZfPJx2nnBkbF45s9geCO6y4eJf7TQ6XmDh+kS3IY3LeQ70ocgciZ5Jh0xe3r092Y8h2/mqVkDvFDLdgUrALVDoHyDuiZ8/INAG8wrg7yFeTKD/05ge3BQ8brhpRbkU73C1FV4FcMsfsO+QwImf17P5XmleyO63VS9Bz1TZoIdv4OHyeGnuZTk37xVWj4MZ7srAvNQD8bBReO8biIvlF7G3YjjuQBQ5X19hdV7JytVfbdNb54TvjpqFX6H7G4PPVEIt4l8fVdkfhhz879bz4osqb0mwSLEpXru7jJ8WXwNe7PTD74FQsm+ZX1sEsF/ybgkecVfy0/ZfSm8DXxqQxjQdlU5eiZ7vBDhe6R66XpX1kYeOFVheZV5oFikfOF+1+LcgL2ZXZt5ftV7miYpvO1iEXpIRajnwX5NfW15CbcKfpGR2Xhm4UfbkXqgLil/ROCDnZp5uG8tfUUiwF9Rfy15FXw0fUV+KXw6xYo58brFeZvF1TWyeIBzVXn7AEBZtHklf1vKOXxKeKV5U71QJDAkEninuQW6dyBsESO5P7dNv2+h6Sxnu2CfeXke6a9sqbsagOe/aABqcKR6NNXnveKG/l81fBInWXv5Au9dF76oolG8RIEw1/5UF7y5uk4qszvJv5e49byuWXLHZHpd5OVFg3qD42w817gXE7yFiYbzveig6W3DfPXLWnkuiT5//CZ+9fe4zIiDe+tRenvW41V5XhB8XjhRElomfnFAlmqIL9BchXyzhbkVAC5b9O1+FYEju7EPvXoBgBLSD73JVtV/ReW9esdk7n2Zfr18/fURfgu4fX6j2zp/oCQNeHwwuXkhfON+p7e6f1DM43o1XpJ8AxImfWN4+5/huSW8TCnZC617Unoje2jUeX7SfyN5hz4yf4UD2bjDf4pSqnpockN7w3rSXsF70bpOKLqZan7+XyN9dtTqeKwjM3z4xIzdsbqlukO9vEYafvJ7M30De3G8mnzjeX6B1HuaftV9yQ7nvjF7432o5dlZtH9QfVAkaVIxfdp5U7toW+SQd7jjfLm56dT+SeN7I7sROdHc97kFu8vFbl3oorhrdgal1ZUq9C3k8lG+pdWnYVJ7vX5xu8vHihQSfAgS+Ezrfv2xL6T1VQbBq3mxgsOHNXxNwpF9jiGUFqV6m2GbuKt8j/YSY3NmG39da8rQ47vyIUW62IDNFUN93XYGAnjpWCRELYIQ8bgSqYylQ3z2g5O+9QCDgXdbPlOLW+t6EraDXSN5UxObem3p7Z3oIaSne38piYO60pQSBAd5J4BgWU+mCoGpv+t4TImLvNO/e3qoTBzcT7hXu5t8yAEFg0+/ljd7ejjn+c0werO7m37bPqOasHqvLz4E23q/uFUEB3uDqtB7Rn1RxJt/NzQ/v5WHe34n5TK107zjvGd6/RVSXSZ4uDkneG7FJ2T6fYu8Z35YQGh6iHhreZvGsOWfvgrmUXjh0BQx374luwd7MyBof/rX1b0nfnZ6tDsRvat5/ljmfau9R3wSEqd+10qr5zt6hVS2eEY/a7ybe+fEZRbruVJOh3h+LYd/XHyJuRt+v8za12m9R3tGEz2eZKou8sd9rFcXe5eqHblbf/chV3u4tAd5fcMnenPjmbjh1bASFn5Zuft6+4HufnkA2bn7egN/Nbsa0DJ9u3gbJw581sFreed7FdbWeLm+53pmjzW8vAwjfvUD2xBsel3z0bqXfqlcEl+Um5d+FxoFudyBdp7nfIIC2335vMWXO3luV/u8BoEcftd+vga7uJx6O38KAD8Heb2ceEd9wYjHulx+bOcrfrd4zHnceVW/t33MfDx4R3xIcpu4PNZnTW94Xu67uKp5qX33e6CaqyllvA98q32veXx7m30+rW+d5brrBGd+/EM9mGPF/H3PeVXAOHwCe0MXO38kLKB7Ann7fnt4Tbpehdx/j3mv9idV363bem3uYSWHVs8B93p35TwXQn1/GG95mEAgeLW6e75XeCJ5qN/Hf41tTbp1uEd513yifXlYR3oziEF99b4fefUrdboNuJ99cgG3e7ZzHYDA/Rt66H0/iF94nRTxfJ0g93/jkbW/KgGRuVt9INrNvjgDt39GUm9/teIBEKd+sqXVu9u5u3qcgV2aO7nlABd+5+LoeLEDYP2Q4jHvT1GGAcEUf3t/fT25kMCQ/Bd7oHtGEC60f3tWhwl9wHRuBAd7txGznR4sfuOXfwEEh7zBNzt8b3mJuDyCQ6D3fxXlBHpVRUh8iqE+Sx3Exx3bevKvNb8+qC2663pfXf+F7hAg/P5xUnuNfn0QN3n7BBzZA3/NDKD/R3vShEtA93vpWF2/cuYLut9+o5rMLr4D73sw+Me7mgJPdTD8p3mI+u1/P3jueF294LP/fb9947tUf9O9u32S7f1SzISxunt953xTuUmgCP+r1Pt7XiDqr1D9C5/pVFWdMPuY5AN4n9NXft8uqlzMBjcu6PlI/Ge9rlXbfyWwh3+/ZRxzL3o0SB91WiolWMD5uVPJuepeAPs3fmJZI1fryrd8IPl7fUR7iPxUAyD8qbghewj9vVloUNyqiPnHeSm4kn+I+Xp9M3o/eg94uXqtfuD94opkf619z3i/eCp6c3+Pel3l47/Se9m9KP6leTJ7/3+Q+9j8HX+o/p27sn7o//951Hrqej98DJYaf+p7l33scEV5wmPfett6GAddfJt5clo03MV+6Pvme/V+PUOwrTd8wPs0fYp5wP83fYm7KcCffd9SgN3XRdyAkP7CgBu7FMCPXzt5CMqfe5oigYd7emoXTSl1KGD/e3/ewqDSLS9Qey/XAGrNuz/ve3o8x855bMjLART8cSOk+rokYPz9UKUtrb2LZ3t4DbEge3urYP0dhHOTbbxQ+lT6HVBNvJwzsPk6IOlroHmAxmMXO3kZh9O1FX/CjuT5sHEjvSHyAlc7fcHgK3iw+7V73q0bu1EEaNubez7GkWxw+jIH+PgdsVD+u1Nnenzim714kKznJPmtAoDf83xnfaT9c386ePT4pTeSfdN49PmU+KF4en7k+DwXkn16e5t4dP24+3j+53hTUbl5ynyU+2NEc3zkfyg34VVzfFG7m3qO0/2cEX2U/1T89lyM+qz51P4LfpR7m3+s5qPLBciFe8z5jboKf516zPr6w1F8RXrM/CdZRX1Lekz5ZAGE/9F49PzMCSO9y33Pf50Ran1GwJD5apUxf9mzJP2Zek5EROAA+qT5IPqs/YCl2V1ax12SVPohCMe5ZP7o/hhhdjvNuyQAz3rChzTY/SkVvoOE9Hzg+C25JsI6HeD8VuJRuU4k0saU/oFeV4Wc5vW5Qr503Lm8p6iIfpD7u6P8/NzSmXrU/gL6+JMRFu2+khT8/G0lltVdvjT6HblPxoJ1cPwH20L67jA2sp4s6iRC+HIA+Hg0Tzz/b+V0/bD8mPmUbR5/jbZbey8X9Ppo/Nz9DH09uj6CdHzc+DZyTX/5fJt5LyR0+sR+6P08hTMS2Xgpu5t6IyJ9XjhQOXoS+OKYzPsteYL8Iv6Sfcz7dgV8/cL5EbuzeU4jxhEs+W17QTPEcKz88Zv8+/JIpH75fEL+EwatJ2L7RHwHq4L+BXlFvz3HwTJdeuz/kvwU44BDnX5RfDw3gMBE/XkAIvjkOUT7HP7ne4PHtJ2aepz+539G5Xl9xPi0f/L/pORc/bR6rPxzJzldibvWz0F8p6gbgoL+pPgy/mp9rbo8+YL/2YYDmMtV8bkVqV+voP7KN3yDHsIn2i0ofPwOdKB827xC/1bfZnpYePz5gv1y8E29mimRvFk2mqaNvSCUibzFM4aYrbmQ/Wr/yKTSjNT8SvmC+5hdEHhCMB+PfIKtEdmq8LvK5yr8ECKEesL8QvuFMn9Twv3whZr89PyHu8FDEbkVqC4A5bt0/Uh6CmLWgY9+oviy/aFGql5uKa54Mv8e0w2+Yvmpu4r8tjQE+OL/fIIOHVl+sJNa+AkAFK63vtl8Qv7wuGz7EEMS/leGJsOVfS1+qbmC/FVGpXy5ear5+5wSfbl6evyyoGj+bXhq+lZLWnvoPz27avoMXaz8Qv3mkxj7FHvRv/Ru/XmKfjG5qvxeghA4sb5xvpzHzWcxug9hVHtMI9MCXXoc+fr+WvtdfPL9svkYpv0d8vrK+nwBc+fdf6b7uvo0Qct6XgElfveqA+8leA5ZU7zFNMwJqPnBJUb/COG0+KQKJvyRqKFuYHm5UDr6O43FfnkBErxC/L9GhFxI/I58Qj925pr+JTRC/N/hs56zfMtPfIan4YeaQ73W+YL7wHdme5wp4NbC+22GvB8o+xr0Qv+gXFOYfbsW+Lb+OL3jvrqxCnvHxeLkZ7/TYDr47tgzn1VZSBPW+ZhBQ5vo/mYL1vl9wbDb6P6nnVb5iFHE/l97tPjIaxRwWPlIh+pUaoQYBsuadyR7N+r+JdbnvLwKM5WZfhb68RBxU3t/6viW/UN6XeVz5GqAI7QDfEwgVv+HrGe6W3hW+M6OY7mnEo7+1vm1f9lZgv2acl9ZLAQ7enb405aduMra6v87Zkzbl74kgM76mmJ1T7t6vyp2++icG3j6gQW/2zDRReO84IGpefb572X3vmN72b8UxU2fN70Hfe75J4AA/Id4H2d8gSqxjvwwR2IlsvqDWKR9d76W/SVj83woXTFHFv8oUxgo63xqgBqcqbj2WRaRU74RJgaiq3m++BqBh4bteH76UbnNxWTmnb+XeQW8euAkqP77I71bZ9t6nlXrfLm98LH1Sy78p78+A2slV14VeQwQ8bnrA3JE+vxs9WO+Z8FZ8OO/CpCB+FODwtYSZ4WTEbgB+L0e23nu/sH8UNRHCDt8wYKh/PlGstr3wNxPxqdPvUN6nvgh/IgjNNYHoHt+cbrsgUSmOXpdBy75Yf75Yl/rGCgbfOH8mDne+Ad7QflsnVeZ58+ZEqH66wCheDIadH9B/Xd5sYeHe1H5O2SMeWln07wh/xyWH7/hXZD+Z8d7HrH6oNmRvdNqGjoneWR4YfxTmkZ5YfjFABsvc79GfZH6qQSkXNHU4fxrnPp4UJPRuJH9CGDvvgtSHbiR/sZzh3/vvZH8XoHi3Eu8Qfo20bRcn75RfafmVNjmfZd7Uf8HYyu7cJfVv3H+SH1XeqH8B4bm2ih/17nNx148VnnuB9d8euVUFFZ76mdOfVtl5QC3f36X/v7gEMH9t3qh/TH6m7ipEa78sfoEdum/d3tR/EhAalwZuIjjGf3b4Sn4D3sZ+wHmSH2Zv6H8UNXVWlm7tP+VplTn6f97ZSH+3IRm/w5/0TPZuIn98goFuhOVgf2vQ4n56ftR+5H54t25urM6Uf2Humson2cJ+WyYu5yvepDTyfmHgux7+bsp+Fn5LnlvfPXjpSDHuydbcf69wtOPebsUgAB8euW0RU56H3kx+K/ITbsfeSe4MfqbuP95VbnB/aW8ZNkluhn+g108eV97sfivf2FGvH6Z/eDiFb18Nln+LmRTnLSmv3t2Bafgg4DHviO/EfgTOaMP1NB7ZDn+3IL/vB55kJzh+yYE0Pl/fZH8kflF/lW8ibvlZ5H6coX/f7n4e7vVuYn8PW/26wD4fH0P5T8htb3Cfin7gPqtuAX+5t+7U7MEZflgCDz6rndc8BqGHyRp+H5+wPuF+2kAx7lifE3VmX5F+FD76vlh++n/IPhk/LH6i1zK/WT7Gf2xhTz+wbJx+10HROWYfWD5+fwB+IB+FPvJ+Ylw27vg/OH45KRJfZorDH2NR4PTEPoRX8ahj8BiOR5ZdF7l+Ln+IPrW4+H5y6FQ/ednufvbWvC8IibR/Wkumvgw+Pn5SIGnupTozflV/mB+Ivsp+SNdFXlXFen8Q4RYf5wXd2u1/GbhufnLAAz9Nfw7c9Jm8Pq1+un6kf/w/nn/tf5gepb96fo/EGj7yBGfMQH+CsXVf9VDRH5x+zOY1vnZ+KX91PluvC37pfrI+jb42f5l+zb/SPmN/7betvpzWrn55foo+Kj8ZfqRNB39qP55/rn4pHr2/ln/5vGs+GAzaPrJ/P25/Xro/tH+4RR1f+j/9fxh/Y75coWt/s7/GPjh5G37YTSpvUrkrIXp/hohk7uChpX8/OQqXwP4QwIu/0F+tfm6+F37EOQ4/m6E03g1+J3+JHxM+WH8SEex/RL75qkB+uE+JHzM+CP9+f2ke5L+OoG1MLl8LPq5+An+JHwqeL35CfrS+DJ4iftg6vN96AhN+4n8bPxJ+s38JPkLern6Xy8Les4Vo/7J+lF6pbhV/7b+IsRE/5n4Dfiafgr5pf/z3ubbOovy+VP51foler7Cg/+swKR/HTdQfWn7Wntc/kp9jUJzBe+/53q5/w/AJn5EEqH6mRprnjO8x3tR/U8Af5hx+pqSof6m5Q+dcf5Z+FLH4vzx+VP5FJHx+q+5p3/wojkbcH3zuhH9oeoG2lPWrmKh/qiqMFzneu+8wJFRr4n8M/vbxPaHp3qIe5m9oDKHr1+/S7qh+i3Ya7ufvUh8d2JJT1+4n2aV/fP5d18ruocIGoNVcUOcqfxl/F6GuMSJ06n7Zf5Ya/2ba7lp/a9BvexWeeu5qbsz/pj53Pyt+4bG/H+k+sX+lG2deXX44/giPmT89fjz+RwV9fjaeWH6q/1Nu5h7UfqpsD2aqviU+Nv7Z+JAffz5U/g3nQ+a0LoC+WH61x7Cf8Ck5WM7+D/ewH6C+zv/7t0Ef3bwK/5YbUj9Qvgr/8RBub49RLT7Uf0xQfH6zC/C+fv7s6FSfAjztXyZDRnfrf90+WH8Xocv5vT9bflT+pBJxfzt+WxZPf1WimL77flD//ZYNvrY+b3+s/vY/BOD4n7qtV/1ev44/nP9x4DR+vr5I/xfYDahM3vF+S4H4vyzfGX8C/x0+Ib4K/sL+1L69fqL+vl95HuL/GX2MnrpkOf5u/4y/gu9ebDL+Wz6kXnL+RSc7PqdeAv7kYWReIwsyfyRQf9Zcvqp+6f+A97Re7P8OTdUfMt+c/12hjP50/qz+SVUJPpc/uX96/qxewzc6fv7wABapnuL/WDGq/6RIdB7UftWxDH8MHjxue9s+oOvvDIiUblk4ONzs74vv3qj9LZvuUW5dMHEwPf78fr3gUK+Wj7GeDl3D/yfYNXZZ3jWZLm8gkAh5e+8CHr3/hDQaHtQfIm6E7Tqcz++kJNP+YP1a7wV4Eh8T/yFKqiyX7qKpUh6syZ2lxd4q/tP/bxagNmr/N+91OTEad+613s7/SVgAP8oebf4v3pp+0OR5/nhs+v6aH/t/Lf/NbqkZdz7O/23+6r89klFvtCB0Iag+Qp572lNARh7j8ZxuWTmjONb//Brr/93rP5/W/8+Bg//uOd8+dv73/jRFqOaEPmRv+2yEIhU/Tv5j/7BRZ+eTfq7+b/+NV4b+s/6vbHP/m4oQvkv/px92FgduJr5L/2EZgx/0PjfbP/+c0Q1p62nz0bv7/BdMU8VVr51/zI4CQPLa+zz9sOCUSyTikAZG3+qRkD24nX0d/lK7bAeF18Lf5PeB4noOvAj4ESJXN6PXzi/mJKYhegl9j/6mnHE9iU3Atu3v8neT/X2/7hAAiM+6U9V/7ZEhD/g73J4+Mf9kOzyTyeXvn/E2sWl9z25J/0i6tx/IRekEhjVb8fxj/tVZbm+uN9j/4F/whPtL/KHgZ+Y7Q7Kjz2blX/dDkyv9WAH1/2GnqifR6oL6wtf4afwGoKwQSZqZo8D17d/wk2GFfElemBIB/5m/xivtw3ftsizcjH4JPxj/sgoSwe9v8l253DC7yG4PdPuaf81NSz90TQGQPHHQC7MDB4NvVd/iikdbm/n8oeCa7E8VsF/OTuTl0PZwGDwi/mn/WZU2fcW+7gAOuYJybRL+oQCXLiuAMz/kkAixAGQ8R+5zN3iusKocXe+X8S/48GlS7jl3efuBEQ2eblf2K7hWQKPm5X88h7H/3pJJ7LRr+PgDPcLVDzDoGI3FQQiNAhd7n93z/pbiNWeQ/90F72AOu7mP/DN+Kgg4Z7kH2GiD4AjDUqbdjfo+AP3eJS/cA0eV8cdBDgBYPvXvcP+YJZ557Pnx6AfwjPgsxbdqr7H/3O/DlLM/+eQCX5JxvxVbnmAT4YdV9Or5JAKGNBRMO7+4f9tR5NC3f/sNfYoBNgsf/6tFXKASFLMZeM18S/7ayRtPhI8O0+DQD1uZZhWgASX/JUAJDIx3DkXw6AYaZQQeKADP/43wlHbufVBf+zPZq/i9v3usCp3MYBQv80gFkTGYATxfOYBngDif4Ej12OuzzGgB+wCXzhprxTwADfY/+OwDyP40f3MuiLRWzeLI84gG9Hw5Hi2vPMApPM9L7c/xL/gc+KNWKN9+QGPAIkAVDwV4BRi9R15p/0XnjmHEdyyntw/4VAIDVioAtP+JrwAD5yf1cvoCAnZkai8dAHInWTME8LTE+8IDzuImAI5vr0A1rWJ68X/5GHSHZtFfJ0e3ICVBwWf2Mfsf/caMuwtkd76dzzAKluBoeNj99gEjMC7bjn3PHex/8QhqBPyL7myA2jMMyFnO4l/yqOBG7GIBrADQzhW/wZ3iX/AjUPbMYv4wHDT/v3wHcgKf9aI5xgOSJPTvXIBcYDWSiF92F3lGAoOczs9ljAqjxl2i9sGXekS87hLDojqAVM/P0BJAsmgG1fwUgChKenenuF9e5nVGaNrU/Qo4qgDpQ4W80iHs0/c/+MQAhniD/w6frMvG0BirAVN5pAMdAZ8ffH+rADiKDJSgEvsJPEv+XoCPe4U/wknu4OJlU5H8rj61gNYZrJfARu7Kdm7hDhyUvkGA6MBzH8mQHvYE2mux/LsBKYD8O5/H2TAZmAvEByYDcwHBbxaqmLUQsBYn8g/5wZjLAYaPWE+YYDEvzqj0S3ouAusBdN9lP4RFCbAUFPAwBbYCQFpUCjxPmKAko4I69jf7CgMHAWb/dc+e/x14AzNSAfj8cY3wwVB774g7C61C4uYb2vvcOHg/KVWOMAwe++w85HTiGm2CPnycNlUv717R6HyimVpEcRW0iIUCOwzbBzmu+vdGgwpw6LjN31Z3m3sNUcpi8gN60vFQgR/LPo+iG9ULhfYhUnkorWGyZK5Fhxy91fiPU8D2Ax4due5ob0nOHpLFSe2G8YlIewBchJSLAjeY1xihLsjx9ABGSYc4hgIjBZJMQlOGsVNKepqsJnhZABTwC7fAwsPmQzPg0QIDAdmAn/YkikcgF6dymOAw6OiWjn8+Ha6bE4gW5/X0BZWwpkZU71qOMTvMrY4Qp6d5mnDEgU4PMP+61xAmCMcyCfhRcBSBBM9uIHznBUgWmArneB5xNIEZ/0s/vOcXSBTT9zDiOnBa2NkjNLuoJtRIFukiN3nGNdSBp2AcpLVgL4eKQQD+Wjf9rThF7Ac/upgNv+TWwWHR5gLa/vTsDh2vf8Td4N7Bp/EOAlHm0DxXqS0QJatG6PBiBf7MvR5I2Ca2MgoP0e/HlHTgdxAePiGPUOWPECOjzlf2jHjxAsKBO/cEx51nH3sFTvEkgwrBhzj5bwG7jQENPU8kDjLr7PyK9FTcUBAx0DusZjXEygYuPcpUOkC3vyD720RFuccUEYp9ehLXnACDP23QGgR/9XNhW1VHbjvIK6ImWxNoG171LnuycFc+Wc8q55jbHageC/euewRxxn4ct2bnvncAhc/UCgW7U0wBFA5A81usc98eJYwKJblufCU4MwhGIESt23aixA+CW8+gyOBunE9Yl8/MkAEpwiYYctwQ4BeQEGBaECD974JFzONkCel+W89hzgIjwZgdu9Xk4RiEp95nyxRgQwGb0K588paRU3A3nAePAmBq5xnoHGv1cjIZAiCKebcKjDZqn2dt1ve7UKtsDThkuAu/uoVBbEgkCYebAL3mgZSGDbumOMkzgjbAAnpWjSw46PUOW79CAy5nEcKd+eB8KyQjGTxgW23doeCMCSIYv9yCeORA5FA7e9p5zUFjI+mkbUHUnVxMtiBQMdbiIeZmBH8sIl6VQNk4BU3F1KcS8KLixQOjbqewSqBYR4zgFNYVN+BpA2r6L/cnx4FQPugS7Aopei1xlo7NxXaQgrAu3mY7hXPYRQOI3qKvTwBmsCDqSQ9xl1uHA02+XeNKoGy+DAIqu3PpeMMD8IGrt3GBF1A0V+Yr1rTgUQKmXlgWCJ0zsDf1TXv3GgRSPXcgCNNpoEHg2DCqmbHiB7WwJ4H0DimONWtKK+Bjs/UgNwJsPsvzYs4wl5BJ4bZ2ogTyASsOeR8ItQOXCI4IJPSJUKDoM4FkYkU7kHsKGEGkDJYGi33jXuxcWWBRq904GxuG98oGXaBcdZx7WDsj3I/NecLUc3PcnV6NQNBgW6vD5WYSd0nY2rz+uDDA1sECx8IBxJnHU4iR3ITGkEIdtLMFALvmZcHhAohwgkJaQOx/uPAmM+mm9ieDewJuXvh/dbYaRszj68nF4gTcvCj+oUCWYEOyjkvthcPJUHAC1J4xQOkgVpPARu61xEoF4/zvYldAn94fP9vN4pQPvgWh/XCByjVlo5GNxaqutcWWGw09IT6lQLG4l+A9ye35xqoGGj3/AZ1sOqB+ut6qLKfzAQdIdZm+d/o8IEHuigga1mYiBPDsjf7Lfya2DCocKeZW8hoGfCiHDte3Cj2FFxuHCjtwN2KlKEoGcj5PF5p5UCuDbTcBegHptHgQemAHrK2VO4JgNP+6poFNuG/iVNuTNlrTjIsmOykUaZJeT7wzQZTd1hZnBCNfIaNppD65LyfeKy/BNuYmYxeQvg0L6mUvTeqrtxOBa6n2p7BKcZ7YUasAe5apUL4CALYH+pmAf1QLqDtij8PTgetjxU8C7ALXbgRaLsA9rR9Z5DL3ieNvxY/yB7duiTyQORZIPAiuq9kCsSIJBwkAetcWxBuCCMIEsBGIQvOAgSBWChCp4O90M3vzcLxBNP98vhVIN5NNR/VhBaYN6EGPH0YQaI7Yec7P8okEKNg4QdpfED4UKVRR78/2SQYKlARBcHxmwxLvxJoDIA2zYzygvxaygLwBGmDe9UvZ87G6lII5lFovam+Utw/EEpbzUQcPuEHkYECGnrpXHKcuFPfX+blxSfJhX33gQtvIG2pJ8InRuHkoxKBPLHSNnw2VCX71wrnaLP94ViA7/6AoHyOse8BsEpw8dMCzHWPeAerdfe3uBj0RumD0PoO0O/0UMNW5a/NySQFICfyw5rcXLjq0hQMErPQeeXOwFvh4/AefrZgR42qAJqCJIoL7nggCbEqWB9UVqQfD8iBKrWHUjDMn/ikWzzbi9/Sd4rA01v72uDg+BIwJwiERpaV6KfAF3Lq3E2BT7wd/jmt0rRoNGGkAgPBKUE2wIM1G4ePqcDsDQg5/vE45gKg2+eEfxrUH2L2sQdp8VFBMSDXF59fB88v0PdzEnPwXwieHxx4HwJJmGcKZvEEhL3E+IwzfxBnTcn/jz4VjgbbAsVBB0pru4AHAFBJJqL4BTWE4IR4/DlOokgvE+P/x+UEOoPSQZ6WemkB7dyl5gAh+lKiA/JB0qCjr7H8hKQdi3GwydcD8OoUoPZHp0vW94/YJel5Ajz/eNZsNZuQy9r+L1qii5t23H7uVqCYDij/wRHkSdED49qDLkFPvGdQcQArJuWPx3UECX239OUeEtucyDC150vCqGuDfaacnPwQ0E7gPMBOOaGG2h4CcgQxoL2QRkCDQ+AgDRXgpoMCvvpfZIEl9x7wFCoNzQTjfVs+YqC3SR6gJsvqx8J44htslQHH/Ad3mqA8I0NaC/kFECUbSICgr8BGn8Ck6mgKCvl+gx3ixkD1p5S8TNQbarK0BhQIAGSUn34tGNAsAEjCgOW7J1gmeJO3fbezJUFiKaAiPjs7PXAwsNl97YRkj9Hohqd9BxoUWKQcz22gYMCfEeyQ9DTadcStWuHPUxWG3FlTgEvwrJFEJVt8XCk096A7Bi4isiGDBG0gKx5igk0fC9AmGACwJICRIwO3dOBxdHYDY9NMi5BiBqNJgJlBORNS/hnKRP3k7WRAq3gIrVZQwMq5lECQ4sqc8sjqoAhHCE3PYE4aeoUDB+43RgY5WHIEQuhOMHWSnx4igYayUWaC4Pinw0pQQbsU1BfJxIIGA6lr5lECYiYrz9fUGlAjaZDHvEI4o/E5MEbdwCQQsCNEONrc44HSgnMnBj3ONBwPE/xAct1iQdOxUx+YWCnx6kgg4waO3NJBcHxwz6VX3nmrJxZr4vEtkEr/hgCwWLvKuB5aDa9AtoWrfq0vFoEJ1AcT51oKiBD3lVw+7cC1MGSK0EHhUlLTBYphXD6HklEBMU4PtB9qIoMEmYL0vsmvH/4CGCx0HIYIcwQeAnNeZQlWZIXc0pAQK8TzBla8pL4XAjKwRQg2hBb1t0MhNrwY/iFg5Oeu6CCQTjlF+5h2vbEEsWCeEFCjwJBIlg89BznFeMFCf2vQRJxZM04W85QFopyv2BlvPs+FwJX56ONxmUHsCWbBn6CovjppG2Hup/YFBkzdzD7mjy/QQm8Wq0MU8Im6tYPoAZBgjfihZIsoH2gMI4oqoWfmzoCNuKUoCCgSZ3V/igyknB7ufw/eCnuOKBgYCkBLwr38/p2CX5UfgDnB6RgkCYK3zeKBaYkV2aJgPmEvn3OhwaUDdMQGpmQXql/YWETlVMv5zyT5hGVA5meJUC5BIORnLATEpc4SEB4aoGl/AaPPWA0oEyEQmb7tAOxBNNUQv+eu9p2KJCDiHsbvPTB6kBC/ADQNf1K0IGGOsa9H248gmw3q+3D4Q6II+HQdL2/bqjgxM0MR8AO6v8Wq8OUg70euAl4V6jxS3gZhCGMoHw8/cgNVkz7gUvJDumEwKIRT4BVXjKCN6EFgQn37LwFr2IAiNW+NR9CO5BQnu9uB/KpAEYkvv6ZYQ/gdBOPsEEA4bV7VOTjBFLLIY+a7Ax2LwrxLAO6vVHBq+B+758dxQdNLkUrk4H9YEE8gi8bCGvSsW62CpIAiRUcCEbxZXBo8Cxb6g4PLwdpAtXBqHcYFTMQOxBHDgtiBi5k/hiQmQO3kmA1HBNnBGOZ9H3kTC28fnBP69wN59ggq/M3fMXuBOC2NhPr1kgZtCA70kvcC5AtCRf9KpAzWwMSkPIS+4J/vvJvPaEDODfe6sbzehG6SFY+9rdQeSR4NP1JU3CyBEAlaQFLoOY3q/xJPB198A3jIRFdXmf5XjeBIJsOSib0IgTFxQj+pECOLjsgnx8CR3EaI9vwW4SiyyvviDfUkkYncxJ7LYNzJHLcU++nIDVSTPvA17i66I5BP/NEPZCgJeJD9QRuBGN9qKSQcFnPpKAwYkg3AYbaTr0uwenzYVQWi8yb7KEhiHA9g9UBkallqRLr1RPrjrZKCmiDNoSvIAVjrogg5SAtxp5aFb0dUjdTHLeu0828QBuF65sMgpCgyNsxkFL4mWyMT/BcBE+IFRYGbz5qk7UL72SyCB0EY1EvljHPMzBCaI+ICjd08etTgtywwe9oorYYmQlq4AuRaC2I44IrUXK/g7PLNE+wsFd6pKTH4kEvdkqUYJbcRgnhOfsugDWEib8Hu4SPGT8LbieoQvIcuLQsgCcIYJAAbuOMCICRQo3ebp09CyELNwUOZNZUifs2iddAYmCiF4DKTp+KS/FxkJaIjCElzyw4tViL5IKmCaxIkhym/h7ieGBgaJR0Q972BOC+JWXwBXdKHRv7F4xLIQ/GBgqCMiE61kHnqTAorExW4hW772HuksgqSX2vzdaYElogOeIMvRmBUvF/FZZzlJfmzA5tEgZIvn70oMsIdOSIVufMCICRR9nZQSUNYH2lYwBu7UMGR/s8pQockxDpYGnKR8IXLAv+UwvR/2qSoJKQcJzT7+Sl4ypLwK23Pva8QgqRDt1uYGwISIaOgbrU2qC4sT6SXNfrAvOLE7Wpru42wObkgoyQsWWfhHYGFEIqsFZghQhZRCK26ewNTRGD6ZxBDNo60SaEL8Xg//E9EE6tTz4+IJiIR0Q2VBYaCO0SbnncQcFg53EVhCIkGouyuUryRdJeWhRncTOEJiQdnA9wh119Cl6OoN9xIsQspeo/cN9ZwUChHuXAkIhuP9YQHVwI7RL+gRuB55wjbrtEPBAU3AqjEqlRNr41YMDRAOrerBQlAFCEjYhUPtsQn4SwZ8h4EvEIMsKPA/3B1xCPiHBhTfblrJUMANkCsCqFKT8xBarPMKhuC60T5Xm57hvAWiSdSBDiHHqEtwcBiRrg4BC94GN4ke4BPA5DupylJ4Gu4OyQTMQ4GU18CcO7YkLGPtLsdVBzyknHBX3yGDMkQ5e+4kDmqB4cmE5nkQ4O+AIpehDHSyGPsR1cEhjJDysAAfzrRBLALH+Sd8MsQckPA/unfLWSxvBw75v7TIUmUcBI+lb5nlZxYiKISrgyvBW6J0yGYPxtkkijEDB429uFIOU3EgQ3fEtEGQRu16WBGihPcLVleh75+lJ1oliIe+/Zh+OpDvfiCTxeVBg6SEY+7wKR6j32GIUDHK7eJxpQQ40ODnvp9gG0ht69l77+EMdIbr3NT4BykVgJ6QN3vuSQ0U2mj8j769ogi7BmfDMQPqJ6yHsbxvvo7JH+wuvcQdjJEPkiIVfZreHGI/IiUbzeegmiU8YvHdf76v6gtUmGSP6e66Rj6y8ENslrp3CLA08IyVL+80c/i+Q4QQDgDE0CQz0jUhktYIBcM8ECTkEMD/tMSIAhUUCad7FOxbHAkAnGeqRIoCEZ/0JnqkSN6g2XNMgElEiQIVmA7KBSWk0CGKz3pntMSSsopQDS7DTEi5UArvTmeCBJl0DGEL5noBQz6g5UDhZ5n4moYHtA5M0s6kZByuANlnptCYP4bQCDAiccgtUm2VSIe6s9PqRlvwa/twCBEKTpIOQ5Kek1LiUSEX4MPNHP6Y/BVVr/VZHBTgC1ihz03/IURkKIkQdUhw7Y4OSSHSANwe+OCfKS1fT8AYkAsKkVNEkoEJ/x8pOBhP6eqf8nKRi3H4oU5A5GkOlZdd7YUKcpFfADx+4pxT3iyUj2NOVA4ihMJks8hjN3Ioa4SFShVFCbnZjEkTsAhKDmeEs8aySEZEcoWlyNakFKo2KFKz0Sst+g4jBFJgb4G8UK1EnpPHrBQlCsEFEgNSJKdkQhBFACAqGkX2AId9fAKhCndaR7TYICoRcoIbBABCSqQgwRYXowg26eP7xwb68AP0odeLLbBxlDYRj4LzOQeZQ2BUh2DrKFxuHQIXcgpakT8JM7ZPIKLpO+4Aght2Dn6RSNBIIeEaNygZVCKCH03zIFtQQj7Bd/pKFaDbl0QVJQxnqJU9QMHukm7YhevQW+OJkXgI2c0GdO5NVKko7BVKFBSA5kisyYBK9O9eQBrUMQBETg3UyclCS0jZgCuodlSdGyH5Ywu7tcnxYDDPaneNTI/bqOUPcHvnyQPu3g9Yv4XchkeJ9PMyha3JYWaBd3QoftyWJgCYCkUq3z2i5EFUZme+FDouTewjcodAyHLkHSpyv7eUNHZG9QoWe/lCVmT6fDooSFQtuW2tA8wHMAm6pJPPJp+CWAgmSSAWqHsvAJAgxTJ/lQpUI4vt1ZQqQoo81l6psnDJqSA5zkADkLhbjYPbZHU0S4+dIDH2R40LWQTupd2OTuotkGRpmikDKfNbBT3ITNYc0MrPhDQzFEXy92qEQ0P01F1QmGhuY0xf7tcgZ1BIg6X+XExAlBLr0IITlyW+cGgDX2Ri0KU/jdQx5Yei9gUFva2A7oBgsJkP4NDEGnmT0FtTLEHBVbl5VhyEJ1nrdyJyI/T8MUAY8gzbKTgwEe8n9EBSi8i0IaXgNakpmAWv7kxz4EkMAKNQ0GsjSqaKhS5HtAz2esIo5+wY9zMdsuKZ2k5uUg56OENhFKUqfp+R+QfBSPvR9oTnvAaU//NfCFQ2h8FCzQfWBXopw1b0Cj1pmEQyTy9RcerYH72iIePyROhTKDwYHv8hbQUkQ70kXWsm54CyEm5MjwfPe2RCBHIBnkXHh3PV/UZzkTfbk91HIenyJreqKYJt6ACjkcu+vWbe4dDOBTN30ofuPyTZ4ACC6H7X8m7od3fH8hHrk9iDEPzIZCXKaLax695rJ6BWNXtwQ89WjwVR1b5kLEfqXQxDUX+DF6FseSroUfgychtdD0UpH4NnIU3Q0UUdG8tH70CiNKCuQqHeXdDLcgbkJ+OPq5KKoO5DNdBPckIOLr3Dh4EGlR2DSIIQfoPQtpAPC8+Tg+XA8lNqcHE+7lBNyHkqmokIJPcB+lcpsN4qTxgfgeKTXY+NtMGGoKjrwbgwkEs1oVf7AXkM/ocYqMt+Vd98H4rKmHTBvQ99oCSobowUP0XMuqrfvg07d1t68igIYXR3Hbe1SpvTpcQI4fiWqHV4WG8RZJ1RTefAI/a7etMUYDiS91foSWqBw+r28sH5OxTqGpvgxR+JaoQwQWbzrziTFVoiy4D4yZ2SixguVQvR+gSoRPAd92hoVXUThh3g9bP5hKh+YK4Aj0BCSpdyCaUJRwTkqXM8hfdgoGRpkzAAWdKne8mpC1xgUO01OSwSABxOCnYr0nUMofMJMcK+qgM/7RPyA1A4fa3+MGpDGG9gPygUBqZdm5UDiwFlKn1Cpzgg8Ueosyh6FP2XFJIwgXBEjCYEat/2KHsD0BtAQu9OoGVyj27tUPPsB7coOCBC736/ocqRxhi495CFShVcYY7vfrcpypfW7r9x6bgIw9jwS0CawH4qifdGM3OZ+OSowmFbQKNuoiYM1+Ee9j6ztADP5DRguPefYVIaj7P12bhowrAuJz9096tqgcPpc/PsK2TDU553NzyYSPUHvepe9qlRYcF2IR83MpUbHo7x7fP2eVIswsGBCroSGGXb2HHiEw1FMAj0NMFwtxaYQ6SQfeyLdUFTlnGnoSfOBxhrDDIJ6f7w4YTTzWU0zHkeGHAvFr3pS3fMUDvQGYGukhkVOMfeQOzLdECqhMJwmFPPQ/egKp5YRPnwZfkBqGRsgMDWX7gagSYUC3GX0QE82wopMKJbo84TtUpzDp96NqnrlAN3OCerap8mFITyAPvcw9sKcr9lNSN3HcQdhlYSYHzCXUqET2eVLUw2VBWr8Y5SNMLQPmLFA4BuY96J7D9VNzmvzLPw6XgemEwsN6vuP/c0KCLDDz4R61OVMeQ+f+DdpyVRa43oPiIHZ5UlSAk37A0iMQeKwwlhQp8uD7XqmJIuAvMN+CjCfX77f2EPjBqes45rdVzBCK1/VHVcLOBKb8dGEEoImARywi5h7wCZ6xAp2Y3kafAt+16pfqANIKV5g+qbLMxh9+kwEsOIwRCAyw+0rC4yEQ/2ViqpUHbusP8lyQvpA+KHRfOR0pucy6xYgNDPnuqNIAxeDXb6PwPhYTgw+lmG7wvfCeMK/bpEfaVhvjCYj4q32eVIEwyHuSR9olQSsIoSq3QtKKWCCVxA/qg2YRrWeVe5t8+wq0sLQ7jbfDRh4gDSYojFHSYWYwod+VmoQwEPrw6qr+qJJAQH9JAINVjo2HTKd9+Id9aNRNQjEYT+/d5hjrCB8Fx3xzYQdZbbeEx95WHaIjvfjGQmOUteYae6LHw6Yc/7VY+zyttWF1sOwQQMwhFhGm9UArftTGwddPGVUXKhsp7zIICYaUIf6+x4UlTaZsJYATIwyJh0tCvwqUsJLPgCFGUanitSp5msIpmEuwm8BobCOJ6s0Pdipuw25BoiCY2Eamil/nv5Iyig1CYt4psPfwSQQiRhErCPL5qIJIYdBrRahEIUFWFGgNazCWw1SyAOD7WHqsJuQSZ/TaKATA7QFyUN9LrjpGz+KO9+hREnCeRBjvbyBelAC1rI4P8gXD3De61j8VpZm6ja5gwLbHBWcVkOG+P3AoTzAdy47oC9KE7JQtQoZQrrUZTQo0oBDzJnknqI44MYCrKHSHxNDDkwokhPMBujrNgLKAaIlSrw24sqgG5Bi0StiyOoBM+UK8yGgNyHnwJPSgBnMRcHScKGVE0wzsB6TDzJ49QNd8ob3Lz+jQ9hwEjSmIDGG3Z4BVFcJOEpXyNYUh3MSIp59plzYJW1OCRPeb+QcUAnx/zz9fkHFK7kDAsUtRBv1ESkccVOB0aZMfgGcLMaF6wptKjD07EEtXwF1B8IaNu9wCbOHbZxtfnqwhzhBgN4L73JRZKq4fN7+L8U69g2H2+/h3FAokRF8Af4dxUq4bvAmt+qYV/1qogLhAWzFVLmiIC4f6BsJLDmWwr8KPCgY94hnwpisygag244DGYqZcNWXrGfaThwvIm15EINngYpwgteh2pLkCqcNg4aHFRbha6CH9T3iEwRKyA5ZKhnD5aHSH1M4YcgkEsFnDdV4noKiSrZw/ABrNCR5aOcKvQX5aQgS1HMcCFJ5S9QKrtGRB7yDfOGq6zfQQ/qTThOo9KCGhcLtoXf6EI+c5slp4xcLTFiwQ2mK3Xwae5CcIL1L75Gw2mTCokpzRHRwTgcGJSuWpYubAz3t5LXqAL07oDPf706hm9mpw17KyhtC/6cJQRtqdQyk2tRoUgiq6yj/jUdZLKDr4zOHD6n2JKkw6zh6ZohVxG73s4cllcuSeUDnOEKORv9MVA4v+DupPhSLP1y7rtqPkAFwtMh6ppTtNjX/ZoBMRoaNp1MIZyjOlfih2ukabRUXiQocbvJ80oQk8wFmXA04mU0SRk/XCA7gSpVwvoefWYBiRofmAbd0WAarqKgQn/drz4P6iplkUgu1h8lx5tS4xydYRCVRDU5G4jgF/QNlNONbMLBMp8ITSV5D9YR1w/E0KNxuuHgXw21J2wNm2z/9s+Hq8IPbh//dM0oRw1h67sJASoNQcrAm18AQEO6jpwnNwxa+yBoE+HVv0hAZwaBtuo8UG37vJVl3LD/Py0L4R5r7HX23YTUlLLBlkJsQFdpWzAFffFAhSeoGeE8jxIAUHwlr+Rx9t/QZak54XOgiEq1mQFdYnLxFod1qc3hH3DvjT0OhTPpwA9PhfnC8R4NUPSyjLwoHhhWUsdg8T3VocXw5XhWtC1eFHC3MvhCaJJAhcshqG7an14W8ggmGdxp5XIKIMeweTqQ/hQEDGuEz9UksDQQgXU5EB4yE/YLRNE7wiRePN8wDRu8J2obYA4vh6EIVeHQ0KNTqV9Gz+Dv8TTSL4HhwezwtU0ciojd7+AL6ymLGd0BIQCqzQsd0L7nNldgEpAitKG6WkOuFdQ4zh8FppIR/T3goYdaEiWqg9waHwWlAdE4wiHBmDpP/S5/014U8WAoBwVxdeG6WkIoEV/FIew+ogsp7QNr/meaGgR1TD3MobOBt4YiaeVcHYC+BI0cE55nmAgYB+fDKgFJcM94bs/BIOZfD8TSukl65gHwwaM1YsblDz/x9NA68DbukfCqzT92w27ojQOPha8QdEHVcOdYWOaBe6h/9wBFm/h+gfVfcy09zwrgHuWmWRnSfHrhS1p+BE+8PctJpkVI+T39wLS5uDgAeNwwc0Edom+HTcJ7NCiLct+IIC5BHKCK74dmwk00RbxML798PTNBYaLbhflp38FT7zRAWbqOS2uwDXiTzrVlNBgIl/h81l5r7GCmX4fgIvVmU6C/LRC6BhAQLQs7KFAiaf7UFn7iDoghn+K5psd4MIPWKkpPISBEBDghFQu2aofBaVOAmH8weF8CNeOJ8fHrBXFphBHv8MSER08C7BSeVBHJy/2fQWdlVnseoDvkGpzzyEdbQ/zKxeZSb5/oJJgaELPFe4WVdBEWAKTNH3VVARDQiNtAp4AEEXJQ2Eq9GDJOEBcLMQOlwOThNYZLkDGtD8YcpwmZu5+AgmHqcLNKnwCcJhkroQ6BeMMYEZC6VN4QTDI3R8gD2XvH/eYSK29SMBU4KedG86cGejgCjQzXuAmZk5wpMqfpQYwES73/4dMYS/QdFDcn5bul7Mkv3Go4SBxHC4wGAUEZbw7puJRx1BEU2n2QExQ5phUQj7MBtMNNtozaGX0TFDumFfWloetxfdYRRwAfhF4/yu4fBaM98HC87uHMlRBEXOgql06mAIRFSEOhESyIo/hWTozyQ30JZ/sU6ZER6HCH3RoiM2wTAQzJqnEg1ZaCL2NES8pNYRrNC7HTEiJxvqIg+10Fyk3wFJOmpEW8g6oMjZQzbYjT01EQ92C4RZpV6cgEEJuEd2DIoWxPDKLQH+0QEfBAw60woidqHIQLU6r6mZn+jvc8AxYdjo3sqYNaqVcsCIFCbz19H2qKhhZEDmarZ4HZHt/ggf0/XdBt5r4NV9FrAsbe74I8ATT80v/M3grtqNohxp4D3w7wb0GMGQB9De8Hv+gUGI6fANw4B9NAxAIm7wQnUGDeaYZWJhYb0nwRxGVUUAj9QFBPOkYZusLFXuOG97wxT+3J7mWIpTq0D8t8H5hgzjAAwllAIAY6+Day00fpTVBoMIisKEHn4PX9CWI0ThhIjgHAVTl07u4wtwMtYjrH4I4J4DJ+QpThFXVsFDYul9/pGmSTYyj9h+4PNT7EUFAxERD3BaaDhfzHEToDIGhzYjKYzkhhxESJGBcRqg9oaGzxn6AbkwtMMALVSgFs4I1Lrm7LQhT3MH3Q1QjVlkV3aZheQYPxHBcKZKtw2eR+4XD7fSfUHRwRLg8sRqz8ZcFqNXOgAeza/uyXC1OqsnHvyuWPZOM848LxGTQJ+ODWI2nh+ekAx7nBk+EkLPZaBLYjWMhzMIM1O+I284JGCjbpZ83cxkv3SjB+YYYoCIYPt2KHGFIIAdDLoFhRlfiOq3RAkBVUK7YT3yYkYmGXIslzDcQ7wSOenu83MUwsnpQeSS/0r3u2PH/0pPkGYHgGEVKgmIzmBXNVuGwis1TnmSSUxqCKge94Qvx9qsshccesL99qqDUkhYcuPfaq+QC+mE6z2PEaWg1F+A/oIu6Dzx8OGQGQIhdXxE0B4Bgk2HePLs0CIZlJ6koJZER2I3CRVL95LgSSL0KPqaD8eMkj/xGDEOpfjHGccRdLDJW7bRjAkXSwllh90ZIJGymiFfvFGPVBjFg+niV82o3EhPA3mDQZUeSgkMeMPuIgyOWbcC0YyBkykaNqJMq9UI0UE/oVMahZNGBe271yxEU4gQXh+MZmqWPIUF4ikiokWFI5FB9AYGJEw2ysQdCGc8RF397EG+BldJBcLQHUfxCeJHjT0DgUCQ4FqrYjQ4Fr5AykaJIyOB6EjvxFBYKjQTlGYcRL/ck4HFhkDKqiQjSR04juuEUxwgkVpIzaRdzoVmqEkOEkcwSUfhCasR6gdSLjkvlgoERGEjysH6civ9J2IjpeUPdkxEZOzbgU2gs30/yNNr7dwOzEchgXU+3kCgbBAKFG7omEGtgx4igpEZkIbYfb6CsRGuCp4F2uCajOW/OeB5wYqiQG4ID9of6NdES3DOUzXSN1fracCEMtPJa0G24MFjJzVXeBf8RKRHC80tAVUzA54FUjpt7YdxmDjVIrSR9bCRAycoRg/nH4NcRZbI/b6fwJ/9GCOaPBq9VnFDcPzZuj7GESRXYjOO5X+hQ+FIwyBBVvo3JEwIOaxuRIqrqQeDPYDFiL8kYh/UvBJMjGJHDIMDquCIfghqvp9pEJnxJ/sdItKelC9UQwXSOKoczpHCRokjRhE/+nukShwgqRqqCpG6sIOzDKVI1ZenCCVJEWHF2wd06TSRhICesEwSKfAXI6YPmxfFDR6SIM0DChIj0REIYRFaDnzDoWf6BGRL2DkZE8W3Y4emIxS+QV81Gr9iUMQWeI6iRs58zEGwVQqQTfQu0hSZU9Ah7TlHfprgkiMckYv259GWwjKNdA3BCXE8yhhbDZkVNAvBMiOsIO7akMJrrhKZgetuCTWqNqxtPgqvURMeLZp24NHm6TL9fLBBXuCnBq/t3AIZ3IlvqmthYUF/CUVXCq1OzAgV8LV6yxildsDvcj8Xi13tIZHlofgf7GBMM8iQEETPEKoA7tCBBt3cXww2wE9vrng+8MR/oFj5Vohq6ozPQSRMysLbZhRk2Fg/A/a4WOYQAFVcIUHniQ5wI4dUwsGuoKUTDiYDaRX1JnMH1Jn+wo4I/xe8SYW3AAT28wSINARgfmCoSHFJkVhiMPOEhLExd+ovSMiQSWNUy4YWDAJTTTTwlh2/CW47Y1zC44kP+kRCNPrAuMj80GtDTpcmMvYtBuKYSfY2HwaXvkmH6WS3CSsH1JlIUTUgmJSA6wisKNoPXbiP1RhknJCchr2t0FGF2g6fqUIwp97TL2kIeCAQQkcxCATi9DVamoPPfaRQ2Zfr5MoMXoL51ERoxKMwYHakn1jFiw9veRtN3xrS0DRQXujZSarxRWkHksPLTDygXYBwrd6lrLAmUFhK3KTB5qYKVCI/3Y8rS8FXMIt86WH1SONTKEcRJerYIyQB5pm5jht3BBg6iiLJqDX1yBCvNB18JE8qGRbZlBoKNIwykekZ3Io2Gy5YPthEEa3ci9UGgCG/GnU8b/+pLRkRIGKLV2A7AztMnhZ/9R2/3s4SrmCM4vwjJFpZLyuoXeI9Ja2pIQh6WdwwrM2uQneGOCPUysvHeoQ4WIBEX1DReEVFgPRCwIuQsNt9EmGYll1iFTvCkWZS00jgDb1PEUkWX78GvDUpT1anmLMVA95B7LxyQolMOJWqbzXnBkyi0fgMiLZERvmPBQiz9WoHPuE+oF9QsiRxqZWX5xcLiLJ65UiRoojCNrtKIRfo9A81MZLgY+HAQx8LCP4fmoYzD+IIepgD+M2A0Me2BY2aDMiyjHnlWF3awe8ln4zKMOemswjd4aXhJLRbMIjpi1tNTwSkjLoBSFhupohg26B9m0dlHowKBUd2WHD6ekjd+T1ahOpkZIwSAnRZdvhIwO0zI7WQgWlKDux7dLSmUX8/bFRjaQyOBNzxckfLmDoA7kigWHh5gtskC3PYYcntw8yBHGu7oi/MJRkcxgpHB2zaUc42OqRUE9w8yy90RYdFIvRa3ncKW7/ixhUVwEIVuyUiPUwgkDSkXsMG5RoYoqsrFSKVMEtbY1RfLcpCyLKKKkaiWBYed+96WEbWlSLHypKqRszZX+BEH3CkROtB7uSSiOVEJHRInq1NS0sk+xhOoiZW6kTYWcqAsw9+pHpLV5URAPBr2MKiybDgLwqUfLmOtik0iEVDAqNpVLNItpAYSjwxJ4HyWkWEon6BPBo4jqqqKVUXnApBRXSj+6KfEKJyFYtPpRvxDqCwb5kVhoCQ2ZsYyjwF5gkOdTImo9CeSJDbVFS0MjQcNtbfK0IsWeF9qLvpCso2tuK6MSVHDDizgT9IqkslKjcSFoNldWg93KfAKKifuagjzJIXfmOvggy9RjzdEks2IVI4rBRt0jLC3KKnir8PZ1M9Lwxl5skNnzO7/UEeWMiJVH+3l5IdsWT1yAE8iZGzFkBHj2QuWRSS0QVGS33cPHMtfmEg8iP4Qb5iJgkzIizE2/xL3rVv3Zkd2ok9RFuDYbLsvC+ijEfckKjqjUHZHwIP+niWfVaruDxZGIbXNoVLI7tavqjNj7rsJpUdAQySWTO0OAItkLAJDbCM5Re7DHzjErUIbgPg0uRp+Ye1HJ4NAQQ8ouiWwd8f5HXqNFURbI5yhHyj4CEN20LwbPmOVRCx80EGfbXfUZsfJ8sAIoa1GCgNp7pxgOZaRTw6xHv5mhQGxvJsR8wkwNH0EJ7wSOHcvMaO9zD7diNA2rtOZQW0G9YNHDqKkfsW5UDarqiZ8GTiOnUV6o0R+28sKVGw7xrwYRolcRZG9tCxg5iV8puIhws26jsIFC4G2LPQ6KORtkDL8xaaPo/tVvQZRTytUxH34I40URWTMRAKUVcwPqJ/oe/gsJRSZIpN4/4OUbACorWhkmieR6yiOfcI2ovEed3CW1FKaJXAbrmDtRGoioNFWqNDkbctO1REcjBCxOqMv4bQg0osE6j45FU6k9Ub8faqetmjNj7z8JM2tAQ0E+jRZjlGTr0CUcVOGjh34DqlpKqxLkT7GY9RVqjmOGs1kWhhifbX+4eZXlFGL3BQbPmT5RjcjM8wx4hbkdYvTwsR+IRhGIcOz2lYKCYRyXYSSCQQOjkWvdI22gjJ6tG1nSTSswQntejbYd/xY/za0c3tM+wzADOtHdNlbbpRw9/M/4dkI7y/3yWlhCAF2PojKmx+YCVHpQQyPEFxcgUFDqMQQdp/dNBFdxiJRQoN1zAEGZnecKDpawE9lS0RJvcAh+x9d6yqHyEIVEoz9UOQ9SEF1NgJVBqInfad/wWaHF2i/+EiJd2RcnYyXD/4Lu4ajQHqhHC9Uz5dtnduFbfWheQ/ZPJ5NrzuPpN2HbRFWj6OxHRR4AdI3dI61DJyf4I33BOg2nPSej/Dajp4AK1oeigF9wV09JF7jtnbAnegw2hTYx9zp/8NsOjaIEm2y68c+wBem0AXNQ1yovC1gdF7aP05GDogCcgpwlmJLaIH2qt5WMREToJdGfCJNHOtSHOCl4i8BF5XUlLGzw9jRdl0p+Bk7zIEVq2MrAnblff6FXR+tkULbHBeYBjkJRMK4HMTYNih/1DwhwoJVl4czdAWQaUCUHTuDgcAfZw9e6HFIRBF17WFyHqiHXhM50cUHQv284V4ObuYxgCxm7TrTsuuWgBAWDUCPdGc0DYoS2A6E6VaItOFIXz4Eq+dMrWPUC+BzIr1Rnk94UamvJ1BD6jiArobUdA3aCbcKkTBticAjYLN3eJZUjLqbVT4kWoFeK6axU1oGhXA90UXo1CRpGCv2wKii+oftAm0cfHhE95wdXrHLQw46B7dB6xy7VzT3p8MZm6jxCO9E+1kT0Ymg3yQ0lssMAWUgQUWiiDa0AejZkFSqMNxk92V4EYp8694ijklQggLZveG7wjLoPoGckZC3B86uUJAWE0B3aOkDmLIhR4YyzoNbH8kQUoBrsb8i8W5wsN5Ot3oweeNrD0jrPkC5UfsCEtsBsB1MF0oIxRB7otLWpKDeQBPdlf0YDA4lhl7Zq/T2qLP3v4OEPRU88eO7C3UQVO/vLr44t0TojR6O9URpopyQaOtYlEaqPWHJ5wN1ufwcH9GN4FaQYB6EtsjjtCubGtwRCjcAglQIw8jKGXtnwMaq/PAxZei/MFysN/0WHbI7U5JEmjr16ONfvPkdo6W8ZrYGE2GkIZbomIRTR1o1QzAPbupKce22Lr9kuwSxksEasAj/RLrIm9JJqK2AYXo0nqifDkuw3ERPHuKfdA6LaNU4FBCPD0XDGG4u1/9mDFoKmDYUCQuPR4wD0uHH6Me/lXwogx1j5xr4/APn0SQvC0+QAD59EJ30RkfNwiQxM+iVr4FCIkMWW2aa+JQjeTojjFvUUiAwAxCjI6L53+k1OiDdNtuOACk+xvyM/UXoY23RIR9YNZaXUd0XLfL1uHujXdEdLxKdlZdbAx/bDGaZ2GKKFsOwsy6EugNBaG3x2OpPwP0Re79phzWBljzPOwpSqa4C6bQO31zcoEYmBRNo5/XABNzXiPZULy6jeA/b7awS8ukgrMRhRpJJOy56J/getVPAxKRjr2EhkK/bO4oKR+EZD0jp9CzTvtV2ZQxOENz1SN6K+9qggy7kwQ4KjHSP30YV3o/Qxcvcl3h96OfIDcgsA4hhj7jg17wofkN3U4xpXZaH62z2n0fYYhshp9Dz9Hn4jo7pfQtgcPl8eH5fHVE6L+mNRhVo1mDEcXDG3g9vQ+6LBicyFcDkWMS73NGEWE4LKQe0PtbvxYDFsfxtoH7NvAf0dRWJjeIzBITGhiKvwY22XcWSt9yGHtHUBLHpAjh48w5UWDQogQfoWdVyAX+C3VYvGPbXv+wwAxnxiHr7joJJQPUYroRqBjmjFb8NMMe0YwORYN1fdF6iNZ0dEYgT8P3DETGNCRYQdmOc+w4xj5hGYmOmMQgQoYceJjhkEhGN1oasYscQ8gDLsE36OhfjCvXYxlS4vJ7ACKsukcY/0RVl0ZDG66MuMYvQCRepgDVToqGL44VLxTU68C8bAENCNE6EnI4dB0Q4bRC8gPaEdoOChyXsjt/SKjg7Pn0IvJ6681bj4lUKbIAfLRkBAjcHqAKkK3QQc9GAIhDCr+E5vWoZKvAgXRgr13YSYj0f4cAOW0BkZi/+wvuFNEdLog564ZMbTH7nAeoMgYE2hY1CmyD1CCX1pjwkZ6brMwBHd3RKSnqA6bRPo5h8FccNcMY7TEE+SAjmboL8VDMRW9KAh3PdbtFFTkK7JdwzTeCM5y+To6J6nN67cG+tOiE3qPN0DkV19U6QQoJtRHDLg0Jrto4JcFBYjRGJzlvolz/BORsc5SbSfH2a0cfOYigUj9lzETlE4wPp/VqeXS41bCuiPXnL/lQuRcC4JvZACIBJnbsZASFcidpzx9muEQt9AFYBkYGCG8vW9NF+YqMROb1ERBErzK3t7HG0AdbMOG6Ns2CAM2zJYwl3J+8CsfCOJkRzaIARvATqDSEAzPJT8clweeBBOCEWKhhqeMftm0QBCurcHBoTutlY9mEZB/R5IcH/QA9zCMgzx1YLCVMEf8sFoDKu0VEk8BIKBz6oxY3S4XcMeE7OrGnZkcQISgMA0eE4tZgksWwAo1qV8d61IkWKMsKVNUSxOF9O2akuDSJLvgUR2YT1lLHBz344F88YjGxli2VDVvCwTkakV9mpLh5phj6GBuPl5YyxNKZpCCRwDWNspYjXwsVwVE4j7nQ5nJY5w4Q3BgKjQTkH5hGQJO4AVj+EYSwEYsUA4My2SeAbOJg20isXt4R1KMVieTJ+z2C0IhHftoxPBTLi/S3uAFr8VyxejoJrbRADqQONhBVO2FBfLEp33t/AqnVjgl7MCrG3nQVTqOcU4WBVi5jZhWJq0LJY6cw0vxLlh0SFIrNRY2Q4qJw346O5FoFtEAPBUXVwk46DaVl1gNY7tMyUJhrE1fF3ZmNYxDgBlj2wztrnisbD2U4g8tQXnTxWMBMawiAhOjlZprErUCFQo64C1oCEV4rH97FLoKA9X6g8VjxzrBVhmTkG2M6xOjIpLDmDiREFVYsCOjKIT46NSHruNRYoeWA3wT46L0CGlqRY0hQE1j2U5s0gesTxYKSCPmAJnrxtCEsVqQnq+w1ijDrBWI5zNJON+OSRweLEqaAzkrlYk90BQJbLEb5lnBLlYxO22VtSXBw0EvqA3sQg+xli8bHHWKUslD4DyxXPxhQQ9x0CJFscPBQPvFKbEvgOWMLJYrVMAmRNlBi1EkBGhiWmxvcpJdgnx2HFhpYrUhqaRi07iFnisTYZLyx7Kc17izSyYsfj4HFIrLAZB62WKmmEiQPmAERRBtjbWK4Qj7MEGxjsQn6TUWNqIqzY8MxLQxDrEM3A2sX+nKi8h1j1Dg62LZrNuTaixEXEzbFuKFngGtYojghIoT46aZHysc0mDoKt1iuEISni6sUQmQ8Ez1jGlS6WPLCB00dlOp5AZtbRAETcPJSN2x4KxeFYh2J1rIN0RmYKaD4rEgAIkkIynLEhctiqm4TWMZTgObUqxRUpKyzDWOFYBRzaIAXtx8bF0SDRIdRYsiYfhAfuKBAhasVixFGx3PwVbEYZw+sRAnQIS8di3FD7DDAQVqlLqxu4skODyJzfOGtY/nkuVi24CGaDWsTddWCw2Pl7lRnWLtvu1Yur4EeCU7F5Cg7gnAnNmc7FjMKCaLkvwMPuBOiylj/2SjoCwTs1qGGx7YZs2q5WMzZlZLD4IEMo97HfViZsSTQa8CuVi4xK9yw+COpLCixwIjkWRr2M1sMwkNSxSndhbGY1C8VDwnCOy8Vi22AdKR4TuuSLOEb1iqZaXLDEsWFCFOxQL5cMRfJzqsWdYu3Wl+BbmBHUjOsbTsRnYXydxQR+2PGPnplHhOdpCVbFWYjt8Augxuwg9i3QS32Kn4KFJS2x4sshuCJ/Fu4ItYlNAhAI1LHQ62CsdOYCiOndj6qI2KxTsZQiGL4WCdoeaV2LzuAw4mMoSaZqLEM7D82Conamuldi/AKw8BGQfMQIRxMmo6LEqxHjsZE/fixUjjmHEyOIIcQJDQGx/4jg7g8JwyCFfY4m+DPdtLEe6GnKItY7WUfhAFYaHqwKseukUhxVvVD5ZpaB2sVN6W+xvWA4aD62I76NY4mIc861abGjsAMBjQnaaxv3BaC4EOLuSOc7I4gLNZd8BmvHfaKfYrIMKKIeE7jViCcZiSWRxHcpkxa+OMbTJNkbI8gfC0tAjOC1gQQ4+WMvliklCK3EkcflAxt2lxgMnG5WJi1vkrXxxA04+7EqEV0sTVWYBgDDjmKz7nFpsc9SRMwNnEiCTKWNw1KRCexOM+RhDZHEFaeC3Y53Go/dnHG3iBzwEhEH5gyljrlwMOJOmJjzAEgLNjh7E4GBCgbTY4ecE9ilFQc2IBIO3rMuxaJZIGFpaB72uJIZexpCIXwiMWJlbJpccZxBCAV1a2WK/+IytexOHwJfLHvVFIBLlYxamsliR/bO5AqccH5EixI/sNDx92PVoKc4xtIjzjtLFZOJecd/cPkEiliNLBbOPg+AwcD+xEwM/nHbAmItNJY144LziNvZ+nFCcT+CYFxibgYHHPOnlyok4qhocDVf7GBOIGcYM0OhAbji/nGc4SfxFi4g5xQA0NGyouMRccFoHHQiqhTHFD0h8cYcdH8aBDiwnF/OJZbhFSaSxoqi6XFhkiECPE4gfYiVhTeAAZTUcaQBOlxUuDK8DcvACVry4ns+SVjcfgvOMXwAAOJKxObA5nEztnToBPYkaI02QVnEvMRr/FnHfvifzi+RDgOIyseqLElxKsR2dFZx0CoVVY/rsc0QwrHetGnVhIoJWEhdiKtSioO1cbXNRZxjdwYOa6mE1sN843XYPBpgXEfJXWcT+cUpx8EJkpQKpyFIOxYpNOWJwkrHjmi2FM44i0suzjr1zKWNByh045oYZWBlLEsgnWccDhTGWfTgNE6SuJokGk4j00kXV7E6puNjcbk4t2x1NjT7Hs0JjsaTYmmxRxAC3Hq2IaFI7zdGx/p0cjBluJeUnnY/isShMa3GSd2UsfomEA4PNjrsLNuJ4NPqYf6xIFtm3HNEOPoDz4dOgvbiQuTq2JhSLALI4gT5YRHECuIeHki47fyzwIfnE8OPHcV+jAhxWCFt7GEiDIjto42+UabjzLAMuIXQTC4ytx+58SXhEuJ8cfVqaG8R7j83GzwH5cVI41HmEigyKIauMeUh9QftmAZhFjEMOKDMHlzABQK8whrHInGBKLuzd9xYJpbXHzBkvZu+4rCgrbi1Ch06yI5v+0DH49UQCFwJjEfcfLORBxECcuwSweOqFmsYpKxtBZhngQKA5yE64sj64bYkPHEsEPcbpsQLYkPM9zDLLzmsd0dY9me5hqpRhWNHvuR4tII58o8nHnqUH5nuYShCc1jIDj5KyY8cSJXKxDq8phZMeIePElYgDgKssmPH/9j3sQz+dDmFHiIvQX2Mcep2zABQnk9E7HdHlcerh4o1B5LjR/ZIeOP4PmAAhx9e5GPG6vSYMjQndm8NHjQaLMahoTrQDcDxnE5ljBAOOFJuNrG9xFgRZPFfXyH5By47xIU7oaE7ipmCsT09aEEhnigTJ/OKbwGwdNxxxGI/nG7+kTMHSeLLuvniU0AOWOxbu/DXzxssNL3ETEOLcQHo7+hoTiQQocuPQhKo4ul4J0AJbFOXVWge84tbEVzitFToYDUsdmLdixvZhllxJWIUBHm7CRQU8IoXEJPCV2O9LUrxSqh67Grg0+wM54srg8SM2HG1IgNcUANAzx6Vx3YRTCxZ0FeDRZxrEYINbdeOmnJx41Gc01jiCAapj48cN43zxE7RxnEgHmDsUSOf7iF9idCx52NNHN0cNSxq05dLGssEkwPC4o+w8ssJFDiiyacXS8F0CrXjPUaueJwcRHTDlxyFAbrCbvC1On84kTk+NiJzwenBu8VZ4gxxLroL2wQKEJctbUW5ghFApPFlAB/Us94hbg+EAkPEgDgBcXS8Xi8P7iOFr+OMshALcQHxdKw//g8JyPsOdLd9x6jVMnFrVkB8YncXFx5nxVcyaeLAYLD4hJ4ECo9PF5oAiolgnL04KniiOB2Ak3sWDTEnxfRMhvEmGRJ8Vf7PJxa9wwfHvM1slvYnba8onivhBzqklcdDxLHxRrghAgLTGw1gGYCR4GxQMrHkLyQ8UjsX24WcdXhjGePbDCpCLGxIxQTHaWeOokIs4/iCJQo7PEGVnWcXHgAex+Li/HJY2OgnGirXbxCQ11fHayny8cX0fDx1yhlTy+eN6Igw4zbw7LiTFDB6St8TZhfFx6+4LrEhbCM4vc4teIOH0VE4moUm8WN4uBOE3j8XEwCNaWGytSwW+LjAWw4+Kv+ohqP5xBaIWPHn7CqcaV4zruFzjgBjreL2JJy6Y5xJOo/nFWml8BBL476aHLiQdIUVDUKGFscU2u3jKMRQeLlPLHbG9xMvjA3HWUiW8RsCZBeCqcRFCAMggUHAbb2xRFjoP5IeP1TtZ4htUVksAFAkckKGIZ4voQonjKwB7DAh8cgkAYqdfhG0iZmiQcYWvMfxC3AIzGKWPj9ogoNh0N1ZVvEXXkfcce3DAIalj6/Sr+IROIiNDfx+jCx/GrOlTSA/HLfxrzIC8R4uIX8Sf4szxFLjp2Y0KAeQlxYhFx5zsaFB1QM/cUzDYA4W/jYP6OoEZcS6419mj/jof6SOJqHv1KMfxU98c8DlHmFpqwoX1QV3UMvE5jDf8dxPQixoHQKKTgeNCPD6faux8ASt/Hxtmb8RouBus0/j0HAaPCzjluEa/xZrwHLEuLgcoVv47GEk2QXFxUCB/cau8AEyWccYdKMeMqYJNPLGx4YDAPGheLGNPYnFyY+ATF/E9WPSuNLQAfxNjB8fB72M3+JQEyYsp7iEniOZGytgEoZbyleBSzBPPXI8YpeRIS1Dj0VokBK5+C7UFl4FKgOAkihmdSHS8MN0zASMoofmGS8UQ9VAJ+lg/vFg+ix8X4SP/x9wtTAle6kvcc2uDzW3fjMm7wuLDIeC7ABQgH453EHeI1jEh48L8OATkvFGoI8CQ/6P7x4sJAPHveCBFLfY9vI5/NnAlXwBBOBXHffA06twgknUAYcTT+cU2sQSREYVWJQCd/4/2BuJhkTipBP/kOkEn/AGAT9TYAKDPsCs+XAJi/gkPGKSLYIML4kExrCgaHKESyxsU0jCBQYPd2dg0BOi2qUEvg6uziUxyM+PfXLAE3h8SxAWglMsgvsfoQb7xshBIR4hBPg/mz4lIW79jzPgxLix8TryLyxdLxBlKDBJCEF4EpmGzIckPFI5g+8S66bc6ECh5gwheLaYABBbIJHnFnsysWP6+B4EiMOz3iYDAyD1R5pgoPQaZwTiLGPuMCRAbdRzxgFk7gnN0DJ8Q+g/Ts1/i5AhdcWscT1XZ4JTDUVAnPX1dfv/IcoCyfD1PFMG2/8RIBRrmKTiwXrPBJhwsAErQ+51tMFDe/FeCa47LU0QISGUhUGhJTmb2GEJejAo3F1PAr6kJQGLmwbEJ44RYEA8f+bKhxTCdJlIwhOZVPVEQ1B429fgkbaMvcQGBCfQrChxSaz/G0cTVcAvWmChqkbc2LmCfIJX4JuWEIfFEq1H8VcE+sId/jPWgTbwJCbd8fjg2rtYcDPBMFMfB4wOGiHNMFAeexf0CD44/gUnjJYR9mGXcTYJZ4JoekxQm3o1E8abjZXBalibdB0BOeQAdeKIJl0ot/ER4QnsccNWwJYX4SsByuPYCdaE6vMXQT/LAUc2Y2MHgrGxCZh+fFGhL6LFnHFVwwhtlQk1NSzjm5UD4JMUIi/jFBMwCZgoMewuzi8AnYhMNqHAEkGe3/iHQl8FhSCcmEhfxNoSy3F5CgQCXBmJ2mJ8ccwlb+Jzoha4oV6tAsaFCnsGtqF/2POWY/imMQsFDfjmeSATx0wwtdhSBLAYMp/MfxX6IcBQKp1hGLNLGhQTUlcgml+J0CROoCkiKQS/0pj+M/IDdpdMJvAsb/EWIBCcZkEjMJYASMLwOeIgTiUElMJ6biLXFeUg4CQEGX8aqHjzcRSeOy4kCOUMJFASt/EcgkKJE0E2oeq4SY/Bg6HwQd2xY8JIEonQlWIE3CXeEi+xcVIPQkvcV58crfe3R7YTYSiyOOHoLwrXsJOLtMnHXwE7tuWEw5WKTjGbgcBPIWid4vDou6UiwmqVBx8UgoOW4uYTJxzA+P/QCygV8JruNg/ZuOORQB6Ejv8aVpHPHRASyFmwoXHmvTjHQwPuO/8d4SUs4PrjmVQehLnSC7CCexWPoElZsKDr2E1wJ1OnxhAPHucynksVYji+ZNhwu53gSzjq1Qxjx01DH8Q6+MQ8eRExUYWFBGAn380fcRULCdoFzjUhhVOLYUBO0CYJpmxRY5iRNl8MJ1QuOcItpIl8nFPBIXHHR45Hj/aQcGKSsThGTGWrZgCajJQEtTr+ZHiJ7VlOThwJ068YJEgHW7FY4E74/3A8cKZT6aWCcRPHaRLqOhFwCeOzgYvImmnBqFKt4+TxYkThogIfEUsU+cbSJIMJCwzoONcJtpEp7w9dj/0D9OAMifAHWYJUMM6OraRPtaFOGR4JRDjMFDNY3K8aKeVvx4ISzwEGg20sQAcWXWuUS9uYOOPc8UVEmyQWUlvPEZRwJCWsrfhxrHwWXGkhPmIq5KUqJxp8NQly4IwnDQnH1s4YSEjBl/zi8cLrTBQjcQNCjJePnxs8E7Z8htRuXgzmWeCUyqAJkuXi0FpohLTDha44rxhoTx1YJ2grjpV47qJ6kt58RYJ0ZdIx4qpS6EFmvEpNHmiXfAFiJHXjl8TnRLitkN40945HjIsQ6W3G8TT4oqJDeR/HK++JeiWiEt6JZUB+ngU+NeiRpgEiJEXoGTgEhIqkg7YjHxOwFngk9Uzv8dt4roWmCgePzGBOv3JDElqkrLjhBbjawqibFA9Tx13iiondhRmid+2B7x2MTT3j5RJe8YxEhgkjBICHG8kSk8eBwf0MXjiqwBxRPlWOS40HxcUTL6LaOKKRA5EuFI9rM4fFZMTiibv6ZHxBDw4olUWgh8SGCbYgkUSLIm4+LupjxE8ho8poifFQ4QliZagKNxM3jRPEQ23zKOlcP3x/8gKuZGRDEuBYEEWJypw3Qms+O5iV6mdZOtgImYm60ixsc6uSmJy8EJGC1BJF8WJE7/s5Xic6YCeMLUiGYvVxt4wcInmhP/anq4gyK2MTEgyy+KFgpDE0mwHnxcAkvhHA8dpbdfINAT3LqQxOBKPG45n4bUTdEb7RN02Aygdlx2ShtpQXOId8V9E7RM6ziayBoqxIUNQwYHxYlwXkDPBO+ieM4qeM3ks8zA4hKLiarElkJc40OYnrXDtuAFLQCwejBo/ETtXmiTWgOaxrkYO2hohMqBInY65QafjXomMyRbCal6NGJ/atciwKpwL8UdE34cTXirCiJqgJCZd6FGxVfjngl5RNtcfX4wiJFgwgzDWONuCWJEmPSRMTO/E/uNJomImBxx/fjH3HYryIrMP4tKk5HjhaI8Wkn8Xm7DGA8UTZwmqvHn8awoLhA8OcRgkr+O/8VwgJd4pjiqXIehKA8i27Xfxr1iHUCWcE0CV3MQ+JA4DiEJn+IfiSAkp+xZvw0XGvxPWdtKE+/x1/jM3BbtEv8Rv6YBJ/sAa96f+JV8RjAQ4WVliDvGjuVQSZ+QBUJIjBQAnvwDoVpO42mwUASYEmkJK6CTaCKcJANEvuDuuPvWuB4uhJWeQown5BLS8ntFVhJCCTfYa1OMDnBNqYbAyMpdnEvbEYiUfwcG83oTyAbAJItQCbVLOOTASJElYFjdCc6EmBJQZhlImvqkWvMNgVFBDDiUxzCJIdismGCuOYgSpPFMFFO5hfYmQJwCTKvAYhPM+Km9fRJdkIK+zvOJa7lwknL4efjVXjDZmASXnDKCJ940THYYwEmltZ4xKw/RsYEkZEHo4Hh0dDIDkSPLRJeLw6K/PbSJphw/vFOo2v8RYMYB82jivEIORL0tMU8D+xPgSxIlQ9QcSeP4iLeqSSs6QfxJz2uxEx7warcL7HRBISSQMoOOJojsgZw8RKOiqUk0YY84TrIlEDgYSVkEvhQJtNTLEdkmjCR7hIRyqHj4wliRJxWP2ExyE0STs5Stt0PCYrE+lkVhCzwm/SzYUM7FHkJSEQot7aRLw9rV47oJCLIeImzJK6Ccl+HsJGyAnDjPeNSBo27KjoKvw1LFTBJmSQCdawJ8wSZkn9CCSSbu48xxjSTkMDhxS+TuV5GZJBPZZHHUVgTlDxE19ggUMjgmRxQqSTPkQBJsI8LglBWxHULlYNeJhUTe1DPOiKsURYp4J3/iveG84kM8e8Ex9xDCtY6JHBJ4cW9gRyYrSw6Tw0HzBSTjwPL26DiwQmApP/EZd4uKGgytUUnCQUIScuzBEJ+OprEkTxw9oFJ4klJgUT0rga4EXZm9gE42+3icnb4hLpSdvLFsJf3hEoasKCWHrGworxmdxr/EZaiRCSEEi06oniftTxRJCCZ8QaFJYghLVgEOI5CUKk68mcXs1HF8hNRSQGMb0ycSSusDkeM16KTQMUJmD41UkMB1VCTKE4NxI6hOaoOBPsxBSksZIKzYN3HqhPFSd/2Zvx2rwdQmopL1KpEEuYJ7twZUkwcFKuCaE9IewCTQ7jjONIfOh4jGApu1yQlfPG6mh6k7DgVviFEn/yESPvNpSVxJdC7UlovV2cT6Ek1JMHB7SYBhK5HJaksE4tQSg0SWpJCGl0EjcJ4qSvIz9xM6SVikp0yyASakm+pODSUWk2hJWagEJQFhLLCMAkmAmgUT/rHVpJgScE7TsJASco0hfxJBoLHmN+OyKww0nu2JowvWElJoTCTilbCFh/jilgYBJz5A5kkh0H6cTAk2WczSTZxiAeK/jt10TIJo4TP1DoOFPCXOE8tJr9YHUlJhPXSe9xIZx+aTwEmuqETCS0kthJXooJaihhOICVOkyQ+SvihEk/uLo2DG7MRJ54Tu0nPUlOSVMk4i478Aot4XxJ8gQ+E0dJw2Z4gkvhNHSfdrC+x1eY20m+piRSX+LaBK78BLJA+qWfsRXSGtJMQpXAnlHnAiTWkkiwKMSsOymRLHCunVdTxiESPUkJwmscZ7yD0JLw8YiRYRMxZNlkCgoT6t8Inn1kuCbw6JGipUT14kzqETJAqTbKJ/PiBKrb6wccVCk7/xbXobQTfBOzUexk2pA4viWokopLoyd3zMUJXndyPF6ZEAeGo46EJPGSsOA5VlW8e04D0J6wYDuwSePJSY+4hTJmBpMQlMpLsIBO/LoJeITaUmaZLswhJ4kkJKmSiq59/QSTpSEnjJTUJCTTUOLpCeZkxy4yPjKkisKBuqvY/OHxjUhRPG8eFAdik4hVJdGTl4QoZLTnKJktyIvY5oXEShKPUPQk05JeqTGPGwz0FGKE4phxdGSeTg/xLVCVw4IzJjNw/0jJeNtSTFkilQh/i4oYP+x4yZ9XQlJpoSjMnn2RO8fweRh22WTupyLOLtCeB4ux0DS85IlfpOyyXbrMKx7oT8sk+ZDbODQE0WW+WSxISmxOTSdlksJBMziwwmJZKTaLZE5cJ0YSIXAU9x18SuErzJUahV0lbpIqyRvLEvok4TpskZ+woqPWkqcJrlgQFpVpOWyRbCIdJLaTE0RGZOvUoVk7N01YSyNDLeXWcWWCATxO3AtmhdBLldn5kromp/i1CjdhJNSfGCQgJA4TxUk35RdqHAEpdJXFpcgaBuMYSeKkyR+h/ipsk/ZMBdEr4vdJJGSY6GixLyCbyk55A/fIrYl8JLI0OVOdXx16SjMmOuMuiRnscRJPGT06AHWWkSTeEtHJCuZFnF+6RpsWRoHHJz4SAATyZKZxmXWBJOg3AScnNvBMcu84o+gf4TrdCeTmgydv7OjJ+bwholzBMQyTxk4PUXiSBMThZMBgLcbdBxWGSOcnDDHuSXhkxrJ2mZh/H9j0SyVwQm4JBETLglBTAVtOM4qFE83N4cC5vltcZpgN9xZeAxnwVWO/cY+4kga0a5WImyEy3UA3YGLcKNiwPE65Kqgf85fiJMHjv/E7WPPOHGE0SJhuSIEbKJLQ8df4gEaNygQ0k4eOtyeXsfMJBHjVIkO5KZIl0EsjxZuSAgx8ZIYoOZiIPJHHpxnEmRMY8RoEfBxxkTRGE/uI0CE4EKaS10TPcktUmIKs5E8vkQeTNpothLIMpgk/9gidZWUmSeLNybruD+JbkJwPEIgA8luFEyHWv3QI3zaOI08Wbkl2EDkodPFJRLNyRGLHBJaUToUCt5N82DcElz8ZuS/Zg4pJs8QJ4v+MDjBpckQjgHaDMYUBJD6DqomG5Mm5rmCeqJmPMLMDpbBA8QF47jJhuTPaBeeNY+F1EozJ5eAuWTWOP6idvks3iRqT4vFHqD+8HAmFmJk0SeMliuV1SeQk49+dGT3LgT+PM+Hl4ozJWuxo3RRBKI4K5kmoM1UUivE7RKMyce0H+4B0T6vG/5JRKjnky+GgHijAyn8U48fZE3/JMUhygkA5XuidAUuv61Pjg/Fr5JHqAHElWJn0TWFCRhj9yHNYhWJZuTSzFrRMW8XgUngkGyS1vF4FKFwWZ4mGJ5eSRGCvWTiSYjEz3Jv/4iYnWoOjybQoMdggoSNlAxBMfjDi7cmJvO8+8nZAPJiXA4z3JMbRrUkhwC+8a3kxLAcIT/vH/2PhwNHjDdxvtDDck6qETlh/Y4P4DeSRm7kuPh8eR4rCwxQlRUl8xM9yazJeCJuA5hYm6FLOlraEvHxDeT5opdBOuZqJ41QaaKI97FPsKsKUUCGUWH0TkCmYFKzwHwtT3xWsTdCkvy3qyXrE3Qp74JIEnG+CNiboUpVQZAS6zrikk9yXCmTuIwvi9qouFK4CJkQCXxFxwu8njwll8S7E3gpQxoPYmbtQHaMAmSmxxPBUOyAeOxWJhFHXxQcSzclpci8CRnscOJnuTrD7PpPRCX+rNfJO8h/8nxxMoUHkUuWMYxV2k4ovTwKd40cZxmcSqCncWkjyV74iopqBS5rHFxJ/cUYGRApz0TnCniXCSdmkUmuJXapn8kHNQYcZcNBSJSchH3xyuMT8dvk8dMUcSe4l0ZKcnlmkz2szBT89gvuNHicUU+F4LYTZxgehJ2vnzIeiJc8TBCl8FMr8a7Ca9xAUEZjBDcEcAsyE5+oFihZgkhjEn2NNY3Qh1TZ0M5hTS+KbG4Q7c6GdLIgkWKpphNWJPAEgEEzyMWIk5j74jGo/1IoSkzIMwRAqMciAEUTbLEHS2kONIQPmChhS0tAnjDMyEhwRDWX6h4SlHnE6OlpnMdJ7FiTxh2+QVGNdLaQW8TB/oTmIEYjrkUeEpAuwc8AHS0LCaiUgdipYZWM6+0jJKR7iSe4GJS88BBzkZKegSS5YAalpxbwlJ3kLebBUYbz1g7HTKVf4HiU55AdDgqrGIwT8ph3nDaiIJStFTYOIYJGcdeEpfmJO3Id53LoNyUwCUccSvNBHHGCsZZBBzG0hAvND3HF0sQBCezAsFhLSlzgTZKXhwaGUnOcOyL/FP0xPjYvKekGjsSnrEjtKViRG5awWguhKbQSTwPERJ4s8JStaAe+KTzq/4x0pO+SkOAE2WgSd6U7WgQEjOc7J3lksbJJJMpXExdLG3gA+EBaUh/gjFisykRDWDKd4MYlx/OQowxDcDjKcWUx7IvbtYylmd1fiHmUrBQUGYcykTkXYsYVbCTEnOdBo7BWOmGIrjRspvIACnG+Y3Ujo2U10pdZSwZAzISRKbGTN0pMxgHLH6QU9zGGUicpsFhOmZ5oHhKbs3bIp85SuvECgRe2JXgUxCp2DXingIBbsdvTZG22pTU9h8lIXEtE4xqSFPZT8766W1KQBEcEpXjksDZslM68SxYnlSN45/ikPSnqKUhQN7CYpSGzF+EAw6OkEPOxCItjdFaZyAUCM4oDW1cT9UhosG5KbGyDaxdSleY53lOCsLuU12UI0U2SlyqFXSZZBQMc8JS+piuBNOAo0YxCp0SU5Sne+07tvEwJcpwpSDlgVuO9KWLGfDxXrQSKkBlJagdetJEp6opUykV5iQMkiUleYppSE1biXD5KaiwbGyVFSWvFCBAFAneAX8pwIjnSkdyWnKbZYvspI5ShKn0M35yEDwE7xPIFfCC+WKk/DbgOcpbJkVzpS5DZrFBkjGoecQSLGt23AMLhUslBdZSTMz5nF9zuOaOsp2AkdKlGVJEqQhpcipe7YybGIVOjJJfgFewd0kshbKxBTQO8FOzOuliJhYpoErwOWUnxxKtJWMjJlPjKcFoNKgxZJGykr5kYsa9ETDKjZTOea+WNzDp+AznOw8p2LHVwTAnJznQosVViNRhpUgHKRQkvXIjoYrOCA521CvFU3eW/Q1Ac5OlOCsQSbMUwZZS/xbkUFCqZFkBs4kpTGFB52LAZH1w68pChIEZYfZHJIO8UkmWRRtMqlm0kNqM+zDnWlVSDizNZN0Dl0LZWIkIRRYmrMz3Vn1UsrqrGc4NKyWNpwuPTPkpi0tGLgq5FRTO1Ka8poYI9gkBVNswIRQL8pINBMuSVVMtWInYgBmxWTMqkvWJEcXczazKx1SlkSXRLaVjUcFKpZXBuqk95icNLZYt7WsvdJSmzGBmqXZscb0jVTvfDy+Jdwvj5DvOOXRprHpDCakZfgDdSJu8lqkCyB3cUHocIhT1SD4gSlO4Fk24mGplySuAleaD5sJVU51c+3jOSTP7EqqSkCTypO9i9sEbVNaSiDUsomFVSYakRjwdSeo0au+2NTkzj7eMmIAx2KmpXHZGqlXDDcqYbyPVmp+cp27Y1OWQoRYxZmyziCalx+DgqSXkPa2ysQBLK74BPGGKQd6pdfB2xbXlLYiZTzJypQL4nilpEKMkuDU/I0RFSnsjROIJwm6GPkpZMA9WFLVJkIjgki1SgJjKqkpoJA8RBQPa4gNSZ+qJpJ5UhYOM2pxU4eKkxWgtscrEHU0mfj2bZ/VEqqYlVdHx6fMSQyu1K+KIbUD2pVtNMqko0AoKpSU5HEapS7CQblMx5DUkmkp4ut5qnMOXoqUG2SypOIt9TbxMDyBBCk29m56TvSmTTz0CahPf72MNTCL5p2M3aKjkzKpzKo8bqSlLnzLdUvDg4mT+ug1ZMLqbtuImprzJwXbKxH5fNWUgbizNTjqxN1JauGqUlLYrwSYKKvWKTqd2xX0pfSti3Hb01vGE3UlMphJSo6mFlJkMD449lSyJpXKmOVJaFGMsSkprptGLH6MT2XpSUvNweXNQgB4/FYCSOrfjRjuQURBQ7ilqSmOKqxFwU0fHzVJq8SRYlhh8d0pqlW5PDyDyg1/JuOt7cnBaC98AWGI8pg2lZLGKqzFMGHUw6csfj1VaQYiPKQn6dix/Sow8Y5lKfhDLU0JhcIAcymDJn68cJ3fzAkDSWriJuK4aHf2HMpMjwCnGqBFhocg0yCgwVjForO+PypJnk2yxXDQtRGFlP/ESr4j4w9+lqymk0DW2HvU2vYGrt+M7/JBVlqEAJNGdJSpbKQ61CAIaZT9xFRFYon4NOSsUl4/UADlpAGklXypSdGRdKJXDT5YwTBPe5L3kkRp8kQPSmGSABSU/U7AWyJAYaHbbGXqWyjHhpxfROKl71OhQLCkDMpPniuGm0UFnonZnV1Qx9ShOpXvDsznHJZmpZjtgfFugHIcTDUvooA2T+FDxeOViISeD0I+HIPj7M1OWbK4Et+yt+SNqkC1JzKSBnSOxc9DyhS0NJdDFFUyYpPtTXCLuYmxqYv8fjgsuEQHGZVLAJIE04oWZ0TSamQHDKqRF2LrxoC8xYzINNg9HlUmWwbHV+M4YUW8lqEAc9i5ISNRgYFL3qcU06spv7dg7Fb8j56oWUyrhwMSimm9HCNKYaELXu5TT+da74BLSM+Q5RpsWxLGnl7EySbfU9KSOPj7GlneLBiA8AU5JFREsYm31I/xh409SAPBTJGmom0LKU5KBJWoQBkyY+RKNoaIUrhpTdp6ogE2VpiZs0gAEJ3iQykV0L3qf2vDGpDK4uvFkqxwnJznJgI/DSF0q+NLPcr5YlFgKpA8/FA1Ns4Fg0tdKTAMtc6bYhuaZmguppjvtlGk3mEP8d0ZCik/zTX4iAtKaXoU0s+U4fNIGlx2K4ae6cMqpqjpVEmhAFVSQNU4hm+MTb6mu+ng8cJbMIp6LSdhxEVN/7sS7TepyxZ5amd/noac55YGxq1SKpZ52LficrZVjOzMEHmlLQTqiZbU32JXDSgFAnyVYzpg+C+pwdE0Ck5IUrtkU0nOsX9TJlJGNNfUPxwCBAjRTlGnp0EEyFISNopujSg4kgNLruJy0o8KegTLo5VfHKaZFg6spBTSzam5NNnCaU08YpysQFSJE1PCUQFLPVpUmtcamuQHIaktUyHMLdj0+bVekqqbmxfUwaBJNikbVN4Wof49lS2fiimnYe0UqY8YZbgLLT3TZylJiHFS0kQpn8lF6lvPmUaYkKfGxD0s7ilBW1GIEt4IQI0UhGLH46iFBCPU/yp1GIMBT6NPw5KPU2yxI8sDRqc5xCqZm07Ik7WMIqnbYXjaTTEfsKjZS4qnFtLKzn4QT0p7KSU2kj8VOaXXU2SxnSVXkBf1Ls6I20xj0lMxJSmRigradVheapKWxdLENcH6UHZUpSe2h882maFUgSc+zdNJebTRzhptOVUpgE6NprzI5SkJ1Lbaa+iSypKhJeBajEDraWHUtdpJFim2m6lLLkiXZbtpSyIiKmbVRVaRu0hn8cpTxeA91IHaQI9DfOWJTgtAGcPbxHyUmGy9DSR5bzmWvKcnLakpewQ8hQi1KZYJpkHdpX18vmSiZ0F8exYiJe9HBNG5auJTaecNH9pp0gkaQptOULB/41sSHMoQOnchV78WZrTjA5/N52mKfXfaXqYZDp5dByvHlAQl5nm0yBEYMSZgKVBMg6T5ce1pEgFmMbFtPGGg+Ul1ouVsaOnNzx/aVNSc6WoxAE3ibZP0gnajGjpK8J5akrAnYFtG0x2MQ7TgWiFNPZNGx4PkpS8ll2n+3jlKe48Hxx0BjP3EQwXTiHnYy4Isq9xOmkKFGsToIkpM4nTTojIdOxUMkE0X2djt72kVGXgOAqMQci2GtQTCAei5qY5Zc0hhnTuxEitKNydioYtp2uIJgkbUFEoXm0v2Ms4SXWjUW0c6ezIJ9pmJ5+2lK+htcr8U3o4/7Tj5I3ZNhJtNY6LKntY+SnvW346bjYZHk0XS9QBKdJYIDTzBUYEjBqpGQdNOXttU7GE2TiftR8VL5KanAci2PRhZoA4NFEzpIeJLpPyg2qnPtRxsS5w9fxrYkk2h6+L7UEkza8pEaji2k7/mb8UckPnwvljkEpU5SfaWWEeupo8VUTLvtPCELpYxMKSAT32mCrQDaSgSMDpHV5cB631N0wdbUS6CxQ896n+izz8Q1iS8CyjS8bDgGWvKa8yeqxjuCtulaZ0KTtNY1dgW9g+SnTi2pKbxQddIV1SgGDNew26YCoOzpxupTJx71NzYpd4i1StSJlGk8oDQceezCnm73TF6Ka1ODqco0h5ketTw6nrtNCYaqBVapMdT3umwMDDqUu097pz+xgfHPszTqXI0myRmLT+LRHhK4aWxaPjJ+dSH0lI9OSAj+01Q+83NQgCbdLgqXGJYtxe3SrWnYiySDuj0/6K3ZSdjgjdNO7tnYlxpORxbumZswiqVHTd7pVAgQPH8KAcqVw0ptJjZSM2m31PWGpoEryp79SjKIRlLjade4mZuW4RNamYaLS0K5YI0WmtT7ubTWIpMAkoeapYiV2LE9OkP2PNU4qKjFiVt4Lgks6W07GWp0scWyKNVNneiRY4kWGFSQxHy+K5jvCI/+pyrIdelroBzkXqU+Xk9vTKETbEEgaejk3SxvDpDt6QNMg4InU6R0lzSiuajHhd6dhCB1JgVSWtjFtM9Xpd4sPpB9iIZZT0KIaaZtf9pZuwnanOMmv/im0hnSosS9mSNpiqsVtlXIhjZT8RC6chTaY5iMRp5hdpqjFtNK9lW0p2se/jBtAETQ6acMgPj6xbT9hZMNNmaWi0wzpZx0c8AATAEKbL04UkbIS7M6lvnt6TZXDVxBNkfub99M1ARFUyeq/fTHeSEWJI6F9wXyx9roK7F59Jv7rZYmD0HCSwrK7XXt6cAwDF2tDT87rr9OZHOQ0qX8edjvHQqkhzKc9kHDmZpAj6Cz+P6oZQoWfpSxxjBpa5xhUtf0tlQYiIt+ltixd6T1iJup2PScoRJL1uRJznDkEB/Se3TeuPjslP3JfpbTAhfFscmEIcFoCkw2jQianfsV85gcYcYovpSaJDKfU/6QXAACGdmccxTBWPZKjcAXGpUv422mzx1aWO9yWRpKbT0wyQ1LnYuFfNLQRzdp/aLNJC5P+04J2MzTJH5X2K2ylO8HMpiIZTXGwtyOMKbydc8afTZbrQDJUFCm01PA27FkynjTT4Gf4A3Gpu3wJbH5CHDXE3UmoebbSsTEOWKSsjx04tpRccvAkk4VDOIoMmuilywKmR+Yi66Y/SFNSWudEGLaDIsUGK6XvOJTJgrHAmgf1sg0qGJigyUiDSNI3KiJ04VkF5ZAc4w5UT6ZlY01pTgz++lv5lcGXfhdwZsbw4GnPZW8GWmE7SWRpp++n83gr6VS5Zqp1LpiclHlJ9Smb09/mLrTRRw1HHt6QnZZxpRyE8bAxDOH+PdUt789rjZ1CIAy16V2/cgZ/loKpy0tM9ifkMt56O7jVmbPu0M6UXop1xADNFqmjEFIdB5034cp9DC+lDKMUqYgSR7poxBOejTdPusVe0yRQjhTupb45Qj6R7QJvpvrV5fEQy0xBB3ndKESXTnkl8ZO7gG4MvNpKJwEOmzDK8GfMMzFCFfS2hCjDIOAeT07YaSXT8/qQJIYJERWfzpQwI6Okw7D78m501kgC3SwgCctQj6bjghXpXGCy+nbkSlqQ22JLpHIYeQkRtIU3jY8T/ptwAjX43ZzSmjEMkugy3Ifhm8XHt6WNrOxp181rebRADHYIV2OzOYo4UHGAcHvAMwMpQmedjz3BS4176aOOFWxCUlnmls3TJyBY4ghgLyFfGmo8nisTLsHBpc41lxCEjPcoOQ0wMkKDjBlJC9PbvLUMuHq4A87+kOuEJGZiicnp42w9fE7X1pSL6U+vx9riSeryU17zmLGFBxK/8lWmjDCOaRCMyQCuNTAqHZ6zNIPE6F2oA8EIw729K9LA+U8eCAZZP+nrkhXxIDnIhM9dT1gwHqxAaUHcT3p9+x8bwgNM2prJY5BoieY5WkPont6TkrRMw/6EgBbADOwEpj0+UpLVJLRneoMs6SriBppyDRgmjy1LYYP14nSoXL1e2lPNPt6beMN3p4PSKrSBjLAhFr08KSCoyM+Q/tN6pBkUs0g1aUP0kU6yn1l30riQR3NOSmKcD+GY1IGMZvDJgRkjt22qYB+GWprdRkzBEVKi7gu4kmwaXSQGmB40rsbFsKPp6y0tKzUWId1hqU8KA7fCcRkclnw8QkSeWkhIzefJ+tP+6SnY+8Q0hkg6kNJIbGdOuRSptwBS+l9jL8suSEs6pKhMU7HigntHkUMkX48Vji7bk1IE+MMcXMZZK1Nal6+P8iFZsLdpQCIjWmV818kFu0zDK6vTnMZ24ylqWcpDAZXCFNL7njNdhMAMupR9UQHpbCCBiGR8ZV8p9BigJJd9IPNNHlIOp2j1LRmu6Ms6a/PSHmZpB71rx1MCUAT0m6qR3ktek1HBNGUrJHDCrGc62z29OE2k7UkdSaGAEJk5Yi9GTkLS8ZNq4SOkjuWQ9sAMym0XdSSaApvgQmU2/X0pGolE3HbTB5OGsMuPANIsEtBBy19KX6UAvWQEyV0kaDJViKHwj8Z8FYp+njzkYmc6GaRpJ08/+nD1PwGZCtKyJ8YysTE5lKKRAfY33mHHoxJmEryV6RsCZiSWud9OzrtOg4EhxY/p+W8F7EF8SYHrAXSTAldjmwIlNO/1oSIJcZA5sK+m5c0AmYo4an6vjT8oqGTIuEr409IeJFjpownbwnqcrHQGxjaYZSoT1ID9EuM1yAeky1b70NKamAMDZMpKj0FRlxDhYmfota/pHQlQRlLNNkmVD4etydmcHDaXjOsYr30lt6gYz4cb91IQwGBMpDc119YqljqktGWWLFiZRpoo5gfjMrErX0moh/ViIXBnvhsmSHKe3p3U058krMnA5ieMhjcSozHLJTxKYmWbROpp12pLxlYEJ/wAayCSpQEy+OpcjMblghMpDo2zSDlgleK2IHGsZgZ+oyOkzatNzKcAMyaZbdT9KCVTMptI2UhC4MQzs3b12KCzq+wS0ZZbJqymlKgL6WaQEhstfSw+STiz2mchEPYZ9BjUsB3jJuphX0wN8SFJr3GnFyv0DDQwgZWxhx8A5lKQitSUrrMU7JmBl5CnBGfzNauJoC9oXzC2JsrggMxEZwtiofDF9OckK946+x49IkqkKojXsbZZImpftZYZkNvV8afp2ROpzNib5pa50pGWvY8emtfTmFG1DK1TJScY/px9I03HmDKIaQTsPmxrtBXUmkmWphmvYyrUXIyBRnC2P+Gak0sykwtj3tqFlMlGXZM+/WW0TLM7yjJTsQzcTiZjuQVRkFWO9gb6Usps9dSVqB0+k4mZzQd5+OIyz7CCRULKcstYtxqg0GzHmjNH1inY5lRRNTjdbZOOnMGLII8phkIOZmyHHvQpKUlUhi1jgVLbVO9GepMmTE9djN2gBjJTsT4+KlJRyFQxm8zKzGfr0pRSh1jYTIUtOKGalYgVwJ0SmWnJjK9mYiGV4JLQc+Kgp2JP5KdU0cQhTT65q5qNWqZB7dSZ5hRWljru1XyV7M/mk8LSqxnC2PjgkaMi0EwtjTPG19NEboLU3nM0SVoWmdjMrcdYcGhUf3ShxlMWPPlNtU7dpWcyp27zVMZpCg413YHTVo5nAfmoseCsJLx5QzFxkhzL2GHSUg6WwqgVbF/qk0CUhQDmZFRhcR5B1M/4WdYstRP7TAcamTLr6R4aRepJ1BaHEewTsgvPM6JxodBLIDy1K1qXM4naxPZTpemAeBVsfNXTFx57MfxlqzP2cn60qkU6kzo97xzMe8JcoZRxWFAUelUG0r1iHYq00+vT4JnMOIQuK/UlCZzDjZnySlIwmfHY8yOrQzz5RIjPb2DVxPUpREzmHE1ePhaTWmReZY9gHxaA52ombXYvEcFfSGJmZ2OzwDt3fJpZpsUFkNiJYmUCmTOxGmA1Kmq5GyjJbYr3iZVS8DwFOPzyV7YsSZzdwD7HimB1zNJMl4UX9ijSgV9LpAJEjN6x6dxY2lFBCQGaRY9MUuNSY7btDLXwOljOpp1NdF5nl8kWGdQcJ4Ewtiqti19KbfpnYv1IkNiVmS2TK/sZP1RyZdsEv7F94Ar6UaaBpp+2Y5o5ltOPNF/Yh04azSCbIBTNAcS7CWUZ20lg7EwR1gYswMryqmDiV7YIDNimYdYz4pnEygETlnDWsQmCAypSecarQ92PmwP3Ukyg1Cz9EbpWLynvEMPRxoPJa6mhvSAWfJEd2J8iyKplqzKNcb6U2ihhYyZvD0JORmXC4xaxppxMRnnglGsXQ49oCx/Ss1y12O0eiQs/qZ4CzDWRENMKWTiMlwI4UyUHHDGxuyXG05hxm8Jcpli1PUmZfhdvpEHQWFkDWJwOE3U3bG4SyXlR2LLC2OEs2eO0AyA4JrWIEyLWMyZ6W8zzbKnVTQGR3PRypGDxd0Sa1KXqZW4wiWg8yDT6WNHBsQgyB0ZVzZlmklJx3xpSUo+pDTjBzjw9MMkNxEtpx4LAYxmU1RGcQR8YEoo4yXZhVWOBbC9Up2ob9TgXGhEzlKd/U6vxsTirumV8UAmTK2cQsIDT4nLAuMGmO70sPJ+LitSphNOHXg14u3cH6SKubCTLOcdUsq0wk2EgVlmIFBGYDwIkqHLiiKzHZV7zqd6CFxQ/icZktDBxsXScNYSvjTMaJ82OPLrXUuDSAzjMmmLNIojtvY+7W2RTeGkt5IWWat3JxZ+7VY3HB/Ar6UhFCzx9Dxp5QvTN+GbG4soOrKzrFrb2IKZsFMi1kfrj1UBfqG2mawzVdxKkMnFmGNObcc2GA6ZZjTlLG+GScWeq4fNx2EtgqkONKVMFhQTiZhR9PXGjuiKmdISU+x8IifolJWWWieDYvoODUyoekleIC2ElNLXOnAtPXEuMncWTE0p3EtNj3DwNTPwCnjMgwIqZYMGkp5KRceX+eDxzcFXSYurJgEbX0jVpiqzd8QhrNYMIU000sC+le87KxzTceMUOQZ3QSGmn8VmFcVv0iGJlbj6zAh0U5ziRrZtxVBttVkmUH/sYjoUJ06qyRmkbP0wlL30yZp4NimVRk90WaWmhbex63o07Ed9Ihma/sOpYViyNmlIuNmTJ1MwvYAPiFlk32InqaMBdxxWCgth6NlI4uF14hJIrQY8+lcxMrcSLWWsZ6tlwRm/cGnBoWUzj2wbi2nHoVJYmYCsQCZtAZ6UrH9L+adOs3g4nEyqmlpuJcysX00NZe6ycTrQtI8KUi4l5ArcCVSkfGQacZHMEsZgTBnVm+ONSqvmMteMnri69CLtL3GR+s6Uk+vTmLh82PGrC7UVZmKRTK3ENrKHabGMkhpKVcKhK0tOZaUi4wjIB/9welFFIzWUK7UcZHMoAAnjuMGmSWMwVpzbiUvFejM49jcs5mk90ypWmWSFlWQROOVp1ZtFVmbYmhafnE/dx4aysmllNLkscGs+jZurStK449Du1hH4ytxHugv1CQNJqWnW48f2csyVSk2tMrcV+8IHpH1R2hlpeGCwvNUg2A7Kz96lqVJNqWTRZSxMmIkJn0GLL8bGoQ2YcyyQ2mgbKbiEO01WpDfiGOjHy3GmUF4gzZE9T+enauK5LjM0yepWXiUghQ2RzaVGUxVxFigA/w/9KLaf740gEPiy8En++OOVrlM5Kp2LiBFDGrIp6fXUmoBT/TC9Ljt0Vca1E/mZRVTI/H6dndqeVU+XxBXiOOkaSRJqfZs7OA7XT6qKNnQ5cYRAsOZPTYx3E3AOiLHXM3qp+Lie1JA9KFtG749dAttTQwRj0F88TmdPFp01SLfGqsnmqZDyVrxjxhgES0tJvHL54tke4GyusC1DNZYGKWKTZVoTHfGuFFHGTB5R3xcj8jykq5FgGQLdfcykpSFbEvOLcogcsogk6HiGOhYdJqqbnQoLxGf5KxnMml88TFIcZpDFSLPEulW08dwLaGpiri3JDUoQ7zhoeavxVtQggQd51k4AFshx2tY49SmGARu8efcasp5nJ7XFKTmIypWM/zA52zLJADZIpqSGCG7xG/5XRkT7HXae3DR9ZUQ9/tno0HzGcSKN3xW7Q3qDR1IV0Dd42GgVszO8jWEhu8ZOYRdp4sIsvGoLxR6dLU43xq/xjhm3/ylGdGJUrsK8yk/Er8WqGR7iIae6fjT8kbzLptll4u3iP0STal3gBG8SrTZTZb2FlmlGXQpuqNstuJ2LiVmDVTPPFti07VxcKVmmkSxX46XPIBK8tfSRdlJ+MFoHDGQcZEdSznHoI1l2cDssV6CuzcdZjZOtcVQbfMZEPT8XENbD52bBgvhJZriRNTQ9LlqWq4iCIqGyC6nauM9hK+M/HprXj1I6Z1Nt9NF4jSYwYyXSkZVIt2QWAMqpzdS1XH1RTbqUz07XZsvghmkFER7qXe2TXYogyse5ZeIv4tbUYXpwLj0/J89OTaRIoKMAKuzxek/JJUBFYrRZpe4TEln9Zn5GS7CXgJ80xK0ka0ifhDhzGhQOey9JmU3xLier4J7I5DS27LZ7PzeM0s2Q48IdVwnetH92ZCNM0JPHpQBlyhRJIFv45tkcRSwrKE2Pr2T8wdRZBKgu/FMw2EONqsqQSvATpCRoFK56UYDCBQ7vVGgnptOTac4EnZG/dTTNmN+MoyiHsuzZVQT6ynJ9OffnhDCBQH6FHVl+lIRlgAoAXIMwyD4i3zDSCQ3bX9Y+HJboZIeOZYs40t8W5eA2/E53Fxqbr/fVJ15gQhYgNMuCmME3tBz2zH0Fp7I7jKuk8DgbGDDAnNe3d6bEwWQJroJIByA52afmPswmcSCzgSgwcxoULRQUlJJqtdh6rhKQOYI0jJKwMDVwnKUk4mXiItPZOBy5lm3jIX8egcjeZhsA/9l9HGJabK43MJsTBI/y0tPdnqgE5i44GyqFngHJ3KshUkmWPQS0DmqSFVCSKUrLJ+wTc7Eo9Kj7LYE1x2OEMjZmWkkf2fX4o8pJ1lAgkX7OSGXBnR3IN+yW3TbVOT5LALI/ZA2QSukbdD8DDfsmr4YdTeTH5BJqBoBwHQ5PcBs9ZH7PW5Be0qRaHoTTAhuKEUqfi6MsJojt5OrjdLMqcQcyyo21TvfZ/xMT+MQ7dipxjt8DmKoF12UXsZ1Z8ShpxbsVMf6R3s9dIKPTjDBsFHr2XNeSzp3qF4UlIOwUsWXJGISW/iPkntzJCyuwLQvZeaApxkSbxymmP4ovZfrSwZIcBNrlHEM0xQxAcFwmFHJcOdqDa/xGOQofC4VIqObh4vCMplTKKkQKA7dspsmw5FhzFDR1VXG6QjU/YJYZIdW7XlMAtJTzAoJnykh2nB4Ie5gUEx9eF7T4ZRY+MU4CJY0cpqPRSgmBvXUWdfs8/ZJ4p6OA9sgYaJUcucaqfQ2yl+KNKCY7idRZEVwF8nrwG5OMFUtH25+zmjlFTOX2dJ4+o5MeziylXHOqOYZsy4Jq/dbgBlVOJdlcE8V4GBzLNnWhIMRKIMy45W1t5LHBVPX2TWEqdk7uzIqmwRNccc7ZdzZC/jC1Rb7KQ2joEovgTdSPPYQROTONWUhbgIWyFwkIqF6OYVUmYwZoTC7gHNJi2ehE3L2K4yn7DoROXskBs1LZh+zJBJ1hlfqXpsJCJYaU8WkUUgR8QBCbwuUmzIf6VxK/Zm1U8rZxhzLajn0Pq2adNOUJ9lj6tlQazlCT98PFpCuY2olKfDJOXy3RapVwThYrEtJuGuGE4cyg2zzqmVxLvgDJkiQhN1S5QnEZTx6dNszU5xXSjylvVM1OTamXWZK2yiomcsChGTeLDbZppziSADVNBqYPEsmEti5TtmHbMriVLtU5pNBy/4kHAVqaVds1GpRUTh0yt7OsqKMckMY78cQGmSYAQOR5nDPpxNT3EkiAQgspKU/d4SoTCVB1+DNmUDs4OJg31ilQ/zLB2UVE8J0+vSodkwhK/jOBs3Fp2ITYEr1bKL0b8Eny42DjRamsoGdOXRwSbIwPtfUgPRLXhP8hRep0l5kzksgFsETeM5MWyoTLtwabO1qcqEpNAOmzadnWhOGppSU02pXxzvHFa9IY6auEtfWmWzErAL5PT8OzJf+pLtSJzks5lCGeAgNI5fww0THyzJXOWnsmqET+pFdm5hLoVuss3sZC/j9znQ9K12Qv4p2e+vTTzkLhLQ2oHMvXZ70sb/FkxjrmWj08/x9lQYxmHXTNCZlJFLZ1uzj/FUMCPKa20785bYJndmU9PP8ZkALtZHuzVwkF2maiSR0H3ZZ5ygvz7HLZ6auEvMqEKyzO7WVLPOXPJbVZvxzXCLeCz8qbccvQE5JJcanzQkeOWPxAkqJnT5rgFxMRSeJ0n0W4YSKpJrNJDlmkck2pVGhxOkwLO6icUGGi5FGATNCVxKPOCv0rUe5UBIYn8Xk8Oc+3AuJ5OZrDlKDILie/En9pTp06Lnuxx1JO+01o4yZypXo/bO+XD2IgkJr0pXhlbEzQUM3E960Q3Tp8mVxLoBGUMySs7Zz9UiPr08OVHseaJwUcdDm7nXmiQrYn9pu4tgIkPSUSsSZ0pxwRHj/FaRKlU6eSQbqJYzS86k/W3fHIRc6cBTizuom+XJuOQ/4h2ZBiyiylBXLccuUzWzZE1s4Yn2S1EGaCcmqJ6op81mQnMriUgY5vx1bTpTlIUGP4NqsxE5BcSaVb/jMPOZXEvH4QZTdzkwhJXtni0y85BISLbxlbPKuaXEu5ZCPSYckNYnXoatU43ZRUSWSHlBKx6TEExWCYvUS6lY5JWiW5VIdpJPTwwmwhWiaf5swa5WoJ3+m09PmifP0iep7dTLLnJOP7WfBclaJD2xpGkD1PDCZVcpNptxy3NZNjM+ORmcl4ys9TLgnAkRhWbdhIZJN6omFliAmSidsYOJZiJxpTlugDJ1viMwCo2kSt/CLHK/jDMk/HM6iyu/h9JLK2iOs4sZ+ySqDr9rPyuNpEi00oizGnCrJLGIDuUDhp0RTrImE0ExGQEGIR6asTNRb4LPUgJ30xpJaLBc0ExTNJ2DvEqtxABy6+n8+LOwiIcyMpqITGkmLml6aTcRIMJQ2FoCzZrJyiT50WBQnEzBWSRRIk2DjMkOgCPirRiO7VjWX9EuG5ZeSI1llNOmUFo8FE50PtIoneTx/2Xr7SKJgQJVGkwcCkRmJEg3aq3S/iriBOJEOu4n+ZzRttIkfJNOSSOpJK5PESw/gXDNSmZyEpw2yrjVdnIrNbMDLsXIZXOprIlq+g62Z7MniJplxqcm0tNssgDcvKZ4GzD8kzJJcDmVc8txMyT+pjEtKw4kMkxxgzixN2g3MOOSTQqL+p4bgHIl5Kko6SCAAL0ANzpnGSHLBtADcgsw7Cy5oA1tPGSav8YM5B1Io7mlsTlaePgsO5rC4QGlLcn2SSIoHOZ5IzzYk9COtGc4KBLJYkTz16FlLZ5m+4zOAHzo4GnAnHNiY4KHOZhOsaIm0SxBWeXabSJXYRE1maXE9RK3c3hMGszpZjtnKbyCZk7gWk8DW7mW4TWmTvYjjZcNzx6ZzbKZVDSLNhQx7RwNmdMFruW25aHpw7oHIlEhzK2cjwjG58iYO2k6yxS5DMkoyA4bTngxOBKSss+8Ps5vbgvIkm3MIOX3c3deU8z14aE3MMxo8MgthkUSRziJmHk2YfxHiJxvEEOmutKCbO/c2d6XoyGSIY3Laho2s0Ourrs4bnMqlzbBqMp2x88TA1B1hLu1iRFaeJHBEsmlMxSgeXhAXA5mDSoHnDeTEme/QjKJk6QianeLKvueyXHGZsyi+klGPCGmdWkCI5oDyaPRlVJ8fCNE8DgvNpGynYnL6SWacu/ZyjUlZFiRKn4JPkofpENymInU5mCmd0KPpJnrFE7GZwBgdnDc6iZSFzzXgza1bMOe8LlZftTkbkX3MLKXw+B2Jc41hPhcrJWAgDci1CjKzFhJ73JLhMwM8jRjdz5EwaRLezmLcD25egQ6Blh/FciZhACCZFKzAHxPJOvtkVMod4C+TopAIg27KaM/Ce5obdqylaNwUiQIED/4BKyvbzD3PvAL6UnZkf8S+tbEoACeSJNIZJabsgHlHXMIiToI04OT7TajkwJMmOJ/cqyp+OTEwpbvCfaYAhfDJCEYn6hmawyeeKkju5OPiXWj2gRIydRI+WpgFos4kucJRuexU6Y6eTz/qzRHO5YDKk/RZttSI8Y/uIHaQk0lcpjHjFVZsCUaqR5lDp58CtRDyjlOEqd2kphgH0okSl9TA2lp+oTyezHTenRnxILGtXjJipW+JgEmX6FySLRU6sSo6T7WD3VNaOTWk39mQ7TNnmNpO2eXE87np3aSg4mZHNc9ik8qw6WUScnmOHPASfDKbg5xFSywnl0Si3uk8op53SA/PGeHL6AcAklogJTgzSnKVJISTMSUp59TzUEnp3yUOWOUwF5EtF0qlShl+eYp0GnpmtjukAUdPd2e2Uj55g8EQTn6GxeeeErE45tZSYEk3PIuOfPso/gK+ZArlcJOOeeKsrZ55+xoBmWJM+XrXUy45SKoyaL4vMWea6Sd3ZubShnkOWn2OaGUmBJFY1iRkr/QL2WpMXqJ+HJyIBd+M6ef08q/ZY4gb0l9PJgefaU/nxrTyY7lPNJNSY08hE5QryanlmXH7qT2Ulp59koZUHbHJmMHk8s2C2qyj3J5PO7jLXUnI4+qT3/7ZPMj2Qk8pzA2LzbjmpPIcGRmU8VJ2LJ6ik1LMBSTa893Zlxy97ANuhpefik/J4trydMCAnLewFWAdhZkgEpwme6hKcJaRMagMqT1YTVTOraV34mY0QJlwXmnCzpSZZldipILzUUn6QLauclY8Z5SOoxtRIlOmeeKk8QSxtTRd5neO9ec0dJQ5dFSs3ns0x2ebk81FJDrz0nlGVMoyVZMeLZ+SN8skwfh02Yr0/LJ0ZwpbkCKG1IRMU3zuMDysWap9KPUL7uTI5BvS/Ml53Dt2Yr9Dmxvby7TaA7LnACTknVQbLT2bZ29J4yQ5mUEZLNBL1kOZJRSLV02UktwIjMkJYGiiQZLS10ExS3XH0TJ+5tNk/d5FgzFlyApMxQOT077YEby1sqIAVjWY1NcVJVgphrlpF2Vef+ZLvZmfSUrEkZKj5k3U/PpmTzw+GnTIWLiq0t7ANdzotlVEj/iXaVPG5EzT5hZo5K1zFdMutZiOTw5ExTKRuRMUoSghPj47J80B2yZzw3KZOYIpPE9OmrxGP03d2JWSfRrTXJn6Y1knUmjkzF+kxZNAaTTc8mEg7ycBC41KzxA/4rmOj9Fj+n79MlyeYSPQZV/TN3k84gCeZK8D/JH5ZDrn39M3eXRcYyZ1a0P8kMiTCaX3/HjJtwILNm/9MSyZ8Ug6ZAYFHulHqAXNjgksAZSuS7HROOG2mVr4fLJnqYrpkKkR2yZfoURZKzBYmkrvJdTCxMnAZiOTldiXRIIGbZ4sjQx5DqylgyDIGRykkdyYJS0Blf20BSf04SLJ2jSo3aopOrSmDEjJpi5CnPlTTKIehDkkPY7YzCAYL9hIyX7vGkZESJlXk1CyKmTyyE1JHtB08n4cmkGeKkoVCs6y9jTKvJcuFnAZGZqgzUUmQpkmyJoM4lR5bz0wzkNP0Gda8q60FfSyioIHKNTmNeCwZluAKvkhnmQabHKZV5MvpzlyODOWGWe8qTMkDS5hl0ZKMuWXc3r5K7z+vmA5z+GsMU46AMjoy7mJSLG+VTKaLZYQyP8lrqksqVdwIMJVIiv1AxjIv5H5kgKG5OykjTrZJsrhrc/x4POSiODFEytudMQld5uyUDlkQbI/yaWY+OprYJwPEW2hoKZyU0MmIOS+fCTlMaGam8/kpn1kS6mQH3veSZmfq5TplMnmq41UuaoyLkhPnzp3mhDM1Gf983e4z2zJhn3vO6+QN8zr5Tny2vn+rJEKc4LN7AMvovxmWZwJ7Gl8mQcOczfO5pfLCuPC09v47ZyqX4Fd07aS6eH7JMPcYxn/hQhyS3Nas5tGYve6opLHQj/gfWpAjcJilnfNIOZG0j4ZFmAFXY8hLteS4U7n5mHz59lNTEIEq68rYp+NYipkMvJXeTnKVOiTmyv/F35O7kaIM8tpl+SUxzqLO82Ur8t8+E9Tsrlq/PIsWXc3Kpz+SMXIArJzJBMU9FaKnz8Tnb5IjMP1c2qp2+SZDDPLJVrB/k884yWSR1I0nLwKX1gDVxPVTXihEFOmkiyc2GJbUYHxntpIq2fQU7PAGtyatn0FIsocvcoU59BTlvwuzNa2RH8v0hFLTdqkx/Izyg98o6pfPz7srQ9KG2TPkp5pzyyxtlNFPr9HEMkQe1vMufnwQTx6Qac+gpU3oSxnfVLOKfvnTTS/1TLTkz5LbYFZ8nbZzBSLUAffIO2UnuTIpVWB4WlnbK7yfGtOVp3pzDckzCAymaNpB7Z4RSKckE/P+gmIUvIEoQy326V/MWhF0M2M5Uni0wgCHl/OXTU8IpvVJFvlM1NbyZgeXtp7NTwikRj2zGfDs8IpeHtqtnFnPCKdNIYlpGOy+8nHDRVqdU8DQpN/AYLKNnMVqVz8j3BOmyyDnFFPjJv+Mm15eBT6PpTzP7ORUU/zAKRzEvSTixPyd18MOZbOyxvnekG8UpKU6c5POTXHzDvN5jNh81XK6by+Jae1MvyYpVDWZm5zn8loArLmcWk+PAV1psAXrZLDJNkjdlpauyJilEtSSeTD0qTJf4h3Fl1XLvOcg0fI0j5zs6mCZPbnJDs83ZExTFKo3nK/OVJku9QiZyq6krvN+oBnswV5QFy+AV26yKmVYcBAFI5wAG7TXOguXwCpmE/dT105GZOOLkj8la5RmSyAVmvIY+UANIgFc+zbjm4As0BYnszn53i1LlBEvM9yfN+MN5oVyXcl2l3xgthch/xMKBF0TqLIl+QO0CYGzTS/Xn2FJn2B68jl5t/y+xaJrNhOWbkwiIoIyG2k+AvjJGVUorCKhz65rPt0zuYRmHwF3YjgzmGUh8BTAoTLZ0FsqCkXnwdGfBOBHx39gLnltKw9wWbk2hCL9y88C1nkfcSrmM6281SDuSieJJWIOcN9ZXdl8gU9vB7fKxnEsO4HiVNDu/yKBc5QSoFst17Znb4E2cd/4iC48F0S6nsn2aBTiYW55lYc/wkcpmRYqIc/65HQKHYox3Ko5pUCurh6hyziQF/Ms2NuZDX5grixgXmd2YeabbQDxvKYvEIjrKBccsC004qVzB6wIVP/kGKmS4aJxyMbRjAup5uV4415hwKR/CIIisBdf4rVMcFtDNljAvJJK3tWepTwKQiTRfMuOdy2AhstwLKgUhnmJuUkLO4FpPpkr4y/PbOY44YUZHLz1gWktFkyklUnlxYwK6jrggoOGSUCri6woyQdhzAqKCOTcviWFLEXUgttS9GbpUKTx/FYWbijbKwsleoFIar4zDIT6pKOeA+GMc5KUcSQUotDxaQ7tRjxvLgFnSbjJEHFMCzbMcyy+rZnAr9UG2c/EFMqMECJr1PkYMwUuviG8zmMaV/IKrNhMggO+QSbAVTEKPKc+1FwFkUhSJm6ONTySkw+FpgTApQWVvmXGh3nNUF5gKw5TKbOrmboUqhg1/yhxkWYGYbMuU+jW0YSw3C5Kk12SQCjzARVov1mI9IHaAn+FFpqPTGAUuFKNJKxc91sHBT0AhDUW6ua+kjzAVRwe5n27PMBTecJvp/gLPcnFHQb+WBcw3J960sblOdLNyQDE6T5C1y3QWJonF+Yc8t0Fd311FmXHOJvl/IkzZ8+zswVvEAeOT8k9NsXbyKzT8wEfcTPABwGf3SSlbf+IQIPXOM+p0+5ywU4GFemrS0qd+jYLa5TE9M5oJyEgHgFJVGqnnZMY8RWQYQ4XoyePxtguoYIu82kBonjbjpp3CNGV0QmsFlLgpwUT1JNAuR4ueQco5prkjWzbBT+8NwFh5pr/ElEECUAgM2pEUniOdnX6V76bm4D0J5l0MglwkTw4I2CtEM9rSCbJ1IG3BeiaQf5/ChZvLO0l2fpQMtsp8zDWFBaKGEOEhc1+wf4SvwUaYEqabPDCcF9+wC2FiTKAhY2C05ePPyUpJH2AghdZs93ZSJApCntxA7LBFU7IhEEK9B5OLIsQErkm0BfelFmmU1R7CU5dIiKizTiW7geK0UPY0F455/l+wWGhDPGWgMs/MV4LQPj2fJJeT+4yU6oYofhmEDK6gPQkifZACcUbT/yFl9mxgfC52V1APHUdkiKTrEctajYKj4qc9JLgJcrLqAquYwWm4QhGifYA0C5GFR7wUlYDukC40inJjYKX6BeTOVOHtbaSFkTN+6naQpIhTfwSmZPbIF8lU6P+hNAM5c4lELwEBbHLeznI/RsFu7DTpmSP3cSdoQdESn0zpTKVAs0HoysnJQlQLaVT77IF2AgchJIErNoRmR3zGBcuZaAZAhwf3GE1k2VlYsl6xlQKO3xKArMJpCCzIigkyNLAec36JEG0lL5vqY4oWUshpuSufJKFzlIabk/UETiRg8SVRQTTXKw+Qs55sZMkcEgIL++yivO3vBrgCqFGu5fGkgDx8hY3PBE50ZIPIXyYGJubFaOoFg1pIKkDkSVBVcC1L2MJzlYy8gqy7jeCkZqhkL7US1jNnAVsLAzQGs5xfkSfJ4hZ+8Ax5IZT3fmzgqidOy8xuIh+zUFBIdSSqR92RsFqJy/AVfcOAheo49x5BtjBIXb+MTWXRwNQ2s4LPqGJrIY7Coc1GgShwuRnBzymhdRIQfp5Jis4kdyAmHJg86M4vULfsBhfNN5lfEhvA3WNOJm3YV5BcviERxt08rrmtQsvlsf0hUWkMLKoXIzPKhU8C6SSLEzgsQjRNf2I2UY/pLwFGQUf3Du2SqZOZpVwKKp6VNLO6uR4wmsIplMHl39kqBeuSWYJYDIVllXqBchKpZfJpBGoPQmR4jwoCxMpKSXfjaAybcLZmYvCSEFhXwwWmvpESCdoQXM8WTTijr2QuWEMSM6vEQAL+uzTriyaTb3DSF76sRZlFzkMhTE8Z7ZooolwXzb2kuZKU5y694KflDk7IrTPJC/fO8Izo5mI4hfBYM0i85psjloXTLkTGbJbW6Fy0LYmC67P68tILAzQ1ggYxl0tI8hUzMYlpvpx8YVo2UDBcDUfw5SacnPhFAuLcj5CwL46Pi/GZogozfFHClHwpIyxgXR3JzeTM0CmFN7Rpfn9dDZCKwoTAkyNpdZmUaQ8hbgYaRpNygywlfNhs8nqUvmgY0LZLQS7P9yMXC/emhoDCqlyIE6hRRHHjZJr8rgW/8mYef4EJEFp7x49QjfLqCVLQFBSBrTTnC8go+AkEC+BpQ8K1XhBAuSXklCka2msK/ClxQs7keRsjqpWcKPYJ7qQ7ziIrJKFBFijylpRXZhX+pZAsU2ykmlXAqRHDTU5gkMsQl4Uv+mm6YPBWO2UaEX8xW3PF3EvCsGQV8zpLyM03UqCQQRt5nhRWoU2TylqUgY/GFNwoknmTPSDCbeUU+2l9yG/Eo8UZHq8Ct8g46lQEVaAvOdk65PyEIvzq2jNEgXSfwoQE519VzNyFtNl+fAi6gU/uz3AX9sxbOjboJaZxCTFsCvxHd2Zr88BFoNEMDnBAqI5mzxXeSz+y2MDjazZ4pWqQuFG4Rp2Zs8TFbmbMhIFOCKfuKWTl/OS+AY9mOBUm5lQAsyBa+zIbi3yxF2nGzC6FiPJQ4sNQL9TEcIsVGNFYmoFFQKhEXGmX16jUC/qWMiLeqLydIsBey4qLibIB57lb8E7ZiFpdIFzBIegWKItcIlIktAkk+xeEVd2NqOJIctUeMiK0MBhNP3DMwi+9AiJSapbFq3gRRGORY5SwLSEWFFmhhYOAHhxTagemyiDKJaoPzDjiCfNWekHAvgReg4Q18ObS93HeIsg0Ohc5NpxXE/NTrXOgRS4uG0QRgLSEV8Qs+hcS7J1w7SE4EXZYAA4PTCswFMiLOHjNLOrQF40gpFA2QYVmSAWTFvGMP1gbmyEnHwIq3uOT08mqKvjABLdwqv2V4ippFEHZpwXW80AEsiUkBp4oSSkVOpP6uXiCmRF0RYCnkJWIplNlgVPASOzyQUhIthdqgyGDZNILoNLRTVYzgyCuxFwjYt2nmQoWRUbkkQJD0tOQXeIraEJ601/5JiKbkQ3nI1BM6sobi4oJG3nybxkRVlwOGxltSxVL3ItGerKCpai2WAdCyrHNxPpezQhFac4QGnagpkRcwwbbZBRR9TbqKTpWEaC4tJeYAobijVOB6YZC58yMKKKAXLQq09q7880F+QThBylnLrmQ6CoGyohiGAWMRJLHCiiz0FlELFbjJvM4BctCuGELbTeAUvgvJRelUoQFVKKgRTarLEBY2Cs6WMJyZrmzguObFtc+QFbKKoUS5TND2Y2C5FFCSLbjlQovavj8C2cF8KKDpnAIrXOcqkl0pXSKhcjXwDQ7DCCwVesqLxBK5TLy7DgitLGSJo0EW1ItTYi0igEFaqKSZZEbOKRUIisL82VJ8kV+N3ihMjU6aZb5A3rYF1EeBVai82yRryUhZjVSNRSr7EhkLpSbxJ6otBsr4iuvg2tSI6Cqe2gGUa4dDm8zdAEbSrL58PoilQEKzAhVlidz1RbV9URZbgE83bUt1uRlyswgZoLczNJJorsbkLkDMQpnFARlonIzRWKYZh5vOzsNbQqG0uuRCvipeqLEumQXIXzAkM51FUBCikVHmHOlkN0HUpFLyg7h6opGjltC//5MiL/hG+vMrGJ3bC+AQPBqIUrMkEaBtLXtFynzkZn0oF3Zr2iuRAZVTmJkyIoIIJCouppQe8fkXhYBl2XkLbS55zRxEJcwoABMLrXJFSyKcubTlF2RdEdf3Z9J90PHQqGfbkTUo9FzCLyjx/IqIaZ61MtFRrjsVlu8zLRfmYOj5ZF4KObQqEtJPpC+JpeqKDxaZTJAkRmi7Z8erzFLCUIs8kNCgfC5Mg4phbLtz2hUbQya60aKeqHbTOsWXqiqy2hdyh3gG5JgoN4CCykwVSFagIYsK6nICsWMHqKyaFN1JjtGGi4aoEkLMpJ5cyubmNMXxp1IIL0W30NBGSi0DmxEdAY9LrrKrntRim/Ilsle86QwhCRavkYaqYkyb0XOoua/soM5MqZHSGMXh8J42TL6QNFhJRFKqDIoYWh6i3Ih6Ey5wCcYtFWSVEqRFEXz5m5XCwvOZTCBDFnBB8xnc7l4RV9guIZGb4FkkZtwsUIu0r2FzqLJB7MlI4/Os9O1FEaillnuNK/RbyCRdp4s5X0WVMHPYqNs2nY4mLfYYb1Cm2fuU51FtlTXRkfFGoxYlYZxsWoLPtm3os/lJncwNQzmKRGCQwLLucGQoDFrDReajVwWB+DOi1aouBySSFOIsswIRkxAWzQSTEU2SO22fx5KyWvaKIikE/OcNh2izpg/Vz57Etot4eOQC+UhCmLTFJbtNnjrpim/gsSsBQWNgTtRSWsQ+ZbwyiMVwpk74ovU3HcCGLU6w6bPMDD8itDFm4zHukR0B3KuBs1UOdqKliBC0lWqfVKeLFHKkXvlLXFBRa3AKG4VuzsGEjYqO1lP2ARFFZI9UV4XPJ2coc+LFQsFWLmMiJg5gxiweKVTye3HOoto4Ja8zCpg4iZsWZDXlqa4cqLFv35PLm7PLtRfZ9B0ZH2LUMUpJldRWh0tMFsqKTthJPNOeQWaT1oHDUevRr1Imts6PLweQ5yfJg4Iqg5jOLdZFBAiEcXDIBZhZbUkI6qOLcqnEtK8Arwi0EOn1SS6mi3CxxWXDVoZkkBX0WRIWCaP1cjmUvct3xjTygl2eO7VHFtpSt9lh0Eh1u+MBFSOczfenMIsWZrAswPp4rxGcW37wlGVYaIRFcgQdCwnvPD6cLi8YIkB5b3kNpLfIPkEFNUWuc8+Gy4t4iXic9jU83NlG4ZUUcmSK5VHF4z8I9kl9JVaeO0S4s2qzgK7a4vwusFM99oNOKNqAL6AOmbB8iXFJagPXkRTNRxWbxZpZLNwucUUsn5JMmU4fpEuL2YLsvMk5NAi6ZSRvB1FmR0HjRaHnHgcVzTyPkwUAk5jIOOJZ1HyscU6/S36ePaLHFIPkeFksfIlxVnTY/pPHzGcUcCB4WRniiXFCu4LgUoiEsQozisrCBKyX+mp4s3mt2U6dWCSBYjognMxqOTiyfgHJTABmSCPBxVCUJvpdDhwBnN4qgfi8crT5XuKLQrQjKPUo7i3u0GjzjPng4qU2QxC/moqOKV0mcTIUeZQinkCZuj5Hkhgi5FoSPVWhn0y3PkR4sVGBsSVyp1IjUcXIGGBRos0lm4ISL8ggcTUWaVJBV3Farxwpm8DJTgBSwPnpQgyU4CYolMBWIM/RFpv5SViiDNS+RLiwDgAzh5BlCK3BxRTPL5FhGQ0HJv4ofCjksrQZqOK0j4TQrHoGpPIXIpJtOIXVfIUxbQhZtJzSgwo6QEs3MfzCzTI46KqWBfqjh+c4LcRuddYUTmDfObxYb7XAl8Pz8CW07F5uX4Mr3FD3IcfkaYHHRfFPc8Fodd/KHN4sOJOhM2BKA+Lssj69PW+Y7ixVAccSUhkbgxHxSnCFk5WhU18VyOSZ+c5jE754OL5Vas7NMxUrihdKB9zYxkz4rrOnqiB75i1SoxgxLiKBY2Q8HFKeAYUVtDNdxb+gDN0aZy9/H6N0bTGwigYZEuL3rYS7PB+dvi2GAfpzofkmEpwJT18ogl7/cMCUdfKwJTk3KWhgOdkKB14qfYaYC7YZIBKqypmEoOGaji0j0bByhcmvWJfYPNMP9ZVwyTCVPNKnmaG5V3F2GCwukqbOBiTYPPISN9yOfnNszrHhw9fAFchL88BOuI7GS2MmCgUhJ9BhBAv4VpQigolmWFXqnRqhwRenzBbgWGzVGT6Iv2GVFzX0FmPNCOCqhl7aWDYsNo4n48WlvzkqJVHjdrmcEy2vndEqjiOoc59m/RKJcUKDAjSTm0yYFoxKD7x+XO6JVcLE/ZOSKh+nSHTv6TxcoRFdbJygmS4RWJW+QNYltdSY/G8IrrZJUuBfp4LsUp5kqSKmYQCvYlPX9BGSxVO29N0S43SNeKTqA3EsAqUbihKS3RLotpPEo2ULMSsiimuzcLQfEuYxpkSwiJOZ55xpCl0nNOhE6mpQvjUnDVgqPOY8NaQgSw8GwUIXJJ1ENwcpRrYKELnekD0CeyaT7AvAT+TinJL3sGp4d85FnYkODYaHp+ef4yBo+JLae7DHjHCfU4CYJErcZwVEkoNmYUEB8cf4SIra39LiLmuC8C5+UUkOCDOnvABwE9SUGricPntnJZ7k2qQoIsv8ywlCvkQnqVwEKWfJK5cFsYEFJdX/TcJL8LL8D2umfBb2E6ooTri/3QfgvbCYwKUrg9JLwDkDzWlLhFgTBJ6fhDCzQksswBkU8sJAGBygmteBghYucwCSdJKdjhSFLXOaLE0FwqEKJzl3wAGqTB6D86C/jezT0cAS9JOkj0lyapLlixxHYRReEkaCYpKzEDlRNaEF9MwoINgUwyW8CSG4HQ6HLox/iramRksNfrmE51Uk2Q6HT8wA4CSkEJ3Z8jobdo6BIgmlSkw/pbWLSjk5HFVCUwfKSF3gII7SCkoUKAUc2lISXjBnTIrzf8U6ZQixf7p1IWrhI7iC3YvLwxKA9zmYoWbJbzknSFkzdgGD+ko9FEkcvTYzUTCyq6cxoUBF2IQIAZK7IX17PWKZGS8Aa6ESKO6G1BCdO5C7A53tTd8AhOm8hWgckAF7JLvlwzCDb8fo5WMlQQx8niP7PiBr8XG84jPjN4SfuJg9LFC8/ZnqMOyWs33YuY34ljue5KZ/G+cwX2cU4Y8l/VFxAmmBHvEJuS+eaoxz3vBa7AApfZUBqF95KDfGFBFvDCNEhFYMmIoKU1+XUCUeiIclYFLE4mwUqzRRzPK2cqATJ6p0kreoKuctVwBFkci7qKHtCQKo96J3Xc6OA6BKGOd+S574+By7eJ7ktvRsYc25gVjixSXTayECV3ZNMlS0EP+mTkoibti4ArpCPjRTwAUvXSOyjHI5bb4/CBUiIOhauEslxN5LsBD4iCSOVtFKCl5MEdAlLeC4CfKXaoqb/jdhCEWIAtBcpDvZ5IYSSWhghokCEc1iYRpL+vJZxPZKFbzIyl1N5qDn98FgsNDlEjkY+zeiK74BgIA9Ccg5s8QHKWcoRk0TuS73wJJLBOB4MJ3JXBS0rg0FKNjnVHPNJSR4aZhjfixVyXLAttPkoXwJ+2ijSVu3Bb6Y34xeEfhBocoVGD08Y3YSkl9Gttkh8HPFeC3YgC0jMLu/H1mGb8TCXDewbfiTPiX4BNjmkKVAJvSMSSUqElGOSy8BuaRpLsqyJBOWCWJUiGWksL69mceAapf9LIQJSlKNKU8lKUoW2S9SlRpKHaJThPDRcF5RguQIoINaP+Obcr1SyRiHATNfaXRKZNJTOJI5/jsk8BHagthYXs8w4CJLuCLsaP38V4iHouchJWKU9UiSpd6/CyRC/i0aDlePKUWbcgJQluEvAnlKKsOagEhvIs4SZjQjI1QCc8uSvAnuoMXnEHI2tsdSjEeY+zvqVGkr6AfkE7o8bKSAaWAWgepUm0Mqlmot05ALhJ7gI3BSIupTVcwmbPzjiTRwbl8SgSCHZGko0wNGos6lobctqUakOFJaLMfjgDHgG4VoHKLYhFSrEZM5ye3ijdXGpVsPMfZK8peqXHdy/2emmd6lnrzwMTT7JSukNS5dA1eShhgd5SGpY0yaQ5gLoSSXSOyviRCDMSUGNK6lFS+OBUms0y4If2CPAksPABpR5aNo55binqUmWX5pfSzaylvD43FZ2BIxpkaS2KBl8K39kZuNOIZ3rQ8luWBjqX4BX1SWag7l5GWo34VoHI1wMdSzlq5tKO0it3SFLnDRXMJJeJIEk56gb8YiE7dA6hzvZjPBIvwD7SrF0G1yceBCuV+Lgs6cMJuXD5SWs3yiua4BajJORd9VCYJLCAtRISvAFJhVblchMXzKJSu2ccdzNza56JwpS7sgkJzKl9vF0tzNCvnS15p6tKLOJ2nOJsHlhSIuac5w6WNfDJpTAI2GJPmtNQXE6iF4nWc1rczvixX6CIrRCQVSraluylG6Vs+XcWejqbfEBITZZkkkr/wvkEpHmANKnSnJnOA8oVShlITQKWrnloCS8a7qdoFHcTnEoA0rCmq7E0CgOeAfW6fkCmibw8bIpWfhbEVFRPEkKWbValJjwhpajRK6VsdSz+iG0TdYgwPOpdDKiq+lTKoBKXsrxPpcTZb8lUuspokn9jfJZwSO+l90UM6WXQFOBStEhM4rpLA6VhXI6THRSsOlplzoQXyOgyibDBAClyUT15poFMGdPPsimpKPDQ6VoMp3eGYk+108sJwwmavBzwKC4Jlx2MTf3a9ksCUI0i6eJ0XAeKXJbI2iRroy6Jj9Lp3EcXOBOAtSlRwBfz86kcUkiLuNbP2JNVjA254+khiYzA1ylNIlTIlf3L4yfNqG+WaIT1T5CBHKUferRqJJpxLvE4TwaiYh0LpMOtLtET+HPInjWaIElhyKdLmsEAdSR7Sm6JB7pnaWCgr9pXj8V4J46VMDEZnJz2urS14YE9Lx5ytlOJ1LWNDaJ3G4LqVVQLaiVj6VUJyWVzZa/BJmhJDSp7mNjK8F6HzNScMaCjASgtAjSW+EGLScEy+opkbzowl9Y3kCWwXG0FYX5fqBbUv0gXec03GyoUei7KUB/cZr+PoIANLyzgdXJwvrME9k0PVy2TkpGgBpeugcMJki8M6VgPScCZn3EGCdJKAYndRLfdEL4v900gKCQlb4nqiKC4JMFrTLzDmCkvieZmEs+WAFLINAP+IiZceSwZlEESsIHHkoHQe/AIZUl3iGGVbJIX5OBowilsILu0nvhTTsSnSihlHiSqqR0kpLaJYkqnJ1tRcGUVIo8SRsoG7JqDLzXkMB2qdpgy05l/csVSXRQAeuYTQERxvtKS7l3MrIZadCVe55k4eKUvMoeuebTASlG84Y3k3XNwamKSj8qHtzxJAIdO8dKGisO5HWBI6WlgCqQADc1gQMzLf2m8HMaSVq/F2odDo2IUTC1poNi4XiA6aKzIlH2CHJe2sP8JdZh32jZFJCdDOExW50cI6KV7XEbuUxaOFlxLZ8WWypLWaXY6JzR7NyxOzJ0raYE44fmJ6PiKTDtorYecS3OklskVkoleqkgSY4XH0+cUTjtTwUrHRRlEy5QYMS5whK5O/FuikunoVugPyVB6HkiUZSyvISDL7XBz0r8+DQ8vkFUjLzbEOPJlRgLrXMusyK+kk3ENcpYplH1JkDdIAWUOnoxorc7/sx1KN8SV60UiT0ObFw2t9L4UVCwc2XSSo+gQAL0yh/tLpJbl7cx5l7SBmV04GMOVQRVdMvxciEzceLRZQbWX4ufkQtklA1OI0tGyxD54yTHjD42LdJShixZJ8dwRmV7WkDufUIUFxkTp5hCB3NvPjaSk/mD1zOJICUvUKo3cxrg6aFCi4x0L6ScJeB1J5MdMqWNJPhsGaaRguxLx8cmgLyIJLFSqFUrzL61FGUrhdhWymM8kNKzWW1sqvKeNS8LoV8TeGlb8FcpfmYNjxAEwqDYA0pz6tmy3kWjBcMDQF7LynpxlHous6497mDdP2pWD3KO5NVxTaXQcwxuW+BVylv+xMElospoqacQmBqcNyFqJk0ubyMlE23SU9KZmqK3LBFurS7b0WtycDDxzhXZUorIZJ3WwBqmgaDDIYrcy3ZGNLCMjuJPypIfJIalOLLKWUb9yGpfhdcx5JrKGqVGsvgZQNwU1lSHKbYmAYiHZbkyvJJyy0AmUGjI69kxE3/8JJKyDkysuedOwMsbo0+Q6blCLn2pTB+RW5p+RTaX9KAGOQSyhO+oTKEkIORK9fM1EvRlXSSqziuUpgMNLIxZJuyVmaUKoikKXlPRbRPRdJPYXJNdJKIyjxyD1yyhq9UrLUioczOAM/MdaW3bBHZXGKFdltNBE4nRSGtOQDSjTleSTKDgDZP+/r+gT5lH95zi6KcAQORyRTdMSeA4t66LThuXISQ/xq7B23El3KciCd4i7pXRym2VpTUrwBd0q55iyTyGWwWC85Y0c7ZJVWBpCAPt0BxR4kjzQQ3AQuVk2NumarlQXII/VAcX52L6KJcsBnAqOEhHGJcoWWHh6IBZsAV2yhPP36scTfFGSlFQGdiLWL02PVEEga7zy1ZkvbAfKVhYcKwKDj9NTleO1mbJUvRxP8MyLCGDIWSWNYprlSeB6cyU4WBGW6ZJDgnXKFynADMSeGDE8ca3UyHuA8EgWWPmIP/p9PQvAnNJg1AsCMtLWhFisLALPIG5SMwSbIuuTxOXUWP9HofM6cwGXL4rHqhmtqNty7zl0QA9uX9BBS5ZVM3o4swTkuXxcsKqlfA5rgOXK/+ltixO8Qdyxo5e0zsSKbOEK5XaMiSI6gRrQhbjOFyF1pSiotKh9RnlKhEcfVyrJuqozYnYLcscsiNyq64/rNZ67riVkmYfCy5YDxg2AaBjIkhNIQafY6ry7Rkl0Gd8dxiH0ZDAY5OBo8vC+Sus00ZcqTZ6yx7Ou5bMEouIZPKOGo3co8rlrMi2Ek1SLJCZ2OO5QTy9yIPjjh0iSDxZ5dE4aCZpY96ojsNnysU1MSnOLPKZjDrtP8iLUSlnl12Dr+nJmG7hLPXafAEkyjgBOhw65Ye+CF50oyeuUE8s7BWZ07WZ7XKPK7q8pq5ZM9SvA7dJleXazIh/LPXeAJKtiLByQVPR5YX4rCwdNwheX6GwGseo8PwgFdxzgnx2JkSIry1nlqXLroGc8tj2UFMNLlivK6eW3AFi5f4hL+xdsdL8CU8orKeKYCklXvLw+UN227xh5XPXy6kyVuUt2MX2Cy8nEZCosvAmE1mDeYdY+MEu+B0nFelK9mXrPfXlSvL6rFoRyhNM1wFrlmDidRRdRAm5fA4nP6lFQlQ5nWNYONly8kgFnjpObf8SCrqs80Bx+zSuog7cq7mfZxdLlVbyo2nf1BZ8AJwfSSHbj7jncRHwDIOskW5+3KdqkvEFjcW3ZKpwS9LT+kPGD16WRYVLmjEzc+VOEUOrmm7bexqJo1eWmEojcVvGNXle6M03G+2NgsBvmaklqyzHlEE8pAtpHY5Pl7M5Z66rDz5scMrHPARcROSURuJy+W7yjkoH6y0Im9csbfNZRapxN8zEeVOFEvBQsshI6ofLDeTLgSvWTOEwvl2Ko85kgbG+GX9Wba8IqzpdgjJN7rEbwFAVPmjHeUMpFJ2gM4r7hhfLNUSQbN9Tu141/Y5o88BUF+hl5TmdMlZkBM3eX4QBk2e62YHxU1R3SXg2L+conYnJsR8cGnGczxZ5XSQvmxQiVCLHs0FrmrvygsptPKFiK78tCqgTy8ta9ViK7g1xT95Q5mADZHQk/+X4XWLcT/qAwKtPLIr4EbPv1K4EjmFRZLabHbkPqKVvmS5WvLQywQs8ps4MLrTMgtgzOeUNksrcYKCobgIzhWyVwbLhoOV47GFke8Z3EeWhz5bM8+AVmHQuAkPGHOWV6HXTUcfLiSCjWNKLBf01JYOHlabE5dleCf4hBdGxljEaBxxN+4GuS31ZPXiJBVcKW3saYpRQVQAJt7E/AwdSQIKkKFOIyr0I3ZJybK2cNOZJWAIBXNXHIaK/YylRcfKrNiFrIAzOWspAV1hQJFnnOMV5ZbsHGxWmZ2QDYCtsajxYtfAf6oCeVUEpt8WvgEEBvQql7Cn2Md9l3srsgwwqPLGc/V6FcjaAjZXPxa+Xv110Pmm4nKErDj36wdQs42fdcG/lhRK+bE8hREcVFCwaF4NiTBb4eMX2DLYXVZtVYWeWodj5sVZsOGljVYfpCDrNgemDE6QVH/SS3GeT34FYKCdaFSLjWDAb0jj5YGYZqpPTwPyjn8vYUC8U8dxElUIBV3SyIFXUNNZpSSg3owEbJ6OQNU+VoqlKM1nIsjhFWugLSl+7izG4E8p7KWO43lwjWIMRUwoOcscEKDyuDDoZcVmrODqQTy5hZVqyVXn6CvNIJV4jyxrMlsBUEYNj8TFMFikBddBCaTCpPBUMK1GFOIzp8BrIvfrhMK6exvPkIBXfHCt5ad3HsBHldrTnPrI2mtwOMkVp4x1JnU4qdcfaSGmF09jUtwAisk1Hxs3YFs+zSFhl5k5sdR0SIVX1JxcW+rLSJATysJliNiFB6dTiqrk3gQvxZgo4NpVV1x2Kqs29YtgqMkr9UtcFeaio0V/tlm3FIivcFQlJddp/Cx2oKK8piJv148ewsTL3SBqdw7cZozNflNaAzBX8VjqgWvy5ICBGyfsBKjGrTO0BEVZvq1E7H8LMdheDYoqqn7iTXBK62Msa/CJLldpc4xmWbFGBLk4fvsqQqzc7NcCBiakKoYmsFhh5qfUrNWY3AbIp3i0IkUurIbFfmK4qOIwqlsD1FKIoLy07f4+IUKxWd/kHWfwEOsOivLQjitLKMsOv5EcVm9tEhU0xjV5dgU+1Zanw/+UcQn6sWKmE94BPLfpL2uIguJEMv0V9kJUhXv0NeFQPs5fl1BTwTlGWDqCSFYzeGVVdQrintNy0PJitcVXkgG5lzuwgFVSMch5SczRTqF8uw1CV4jaaBBA/+UYLjHcRtNaM6I4qcIyA2L/zC7UXLQUhthbEBa37FfvCpOZjz4IeUaT00Wa7jFbx1aY7JrFzJO2M5kDaQC7iSVjcw1ycBTzTIV+yAfon1zWtpb6swkQefjGMwP7M42Zd6RflgKhWnG8uEfhZMEVkgemzLA7YOJXoI9M0465L1aeVCnCl2fbIkQVbGTQtkF+NeFSWHVrxgoLLvE54kBCWZs6kRDoqBvyfLOxFodyGXlkmTFXFXCIgFasyc62EihMlTuCvmwris2eqTtTmfD4hLj8S8BDEVPnZI/FYEIIFfvwQSV+JY/+VZkAqRaV4yFQAIrb+Ce5Xs2WsTQvln5AgRXD6MG4Dfy8jSLzikKnACskru0MklAcJpxeWqpOxccPkaqZTvKJQkSKE6ls34iHRsoT8XG4GLTsRXcaLJ2rinLL0cG4xMXcxVxfkQK6kjOFSyRbsruqf/KPaAIso5cRI3Q/x9Dx3Una7JEmkMKvrZirizxTZFP4WIGkkqV/iM1+V3wiy8XpcWCVcnA1XGp7BrFfVRFl2FUrFUDA+OHmiO0iqV26i1+V4KBu2XGQnBJWmYSAWleKSfmvy8xKkfjJpUT8vLmXe2OqVc0q5dnjAsbFZS4YkVHLiUiBjUv8IOtKuPZPAJ2pWJsP6sYc4luxWt9qwlx7IOxJMEWssbvjJF5fcvueP143U4J5jmuCpuIlsR3IFluuThiMoNOPwWhDym/BNvik07olKWld6KnkpGp9XIhc6Of5eQ+KaV40q8hzbvLGlXO0v5sYZJYJUwCvRcZ/TQ6ujexB1lDzzbFZwyMFZcDk1+XeP1a8RwBR7lveBG6GKuLxlcAK/2AbRK49lfnUUlZNSQ6V16QHpXI10TxMb4wtM3grYmxM5O1cSacT6iMvL2clEytKVMAKi9mibj3qizwxZ5XajN3xHcoqUmBQpHFtrshNBEgrUPLV+KOREcK9tJFGSfklNXRzlBIKuQVKnjWWmF8vLWm7CxGIyrxkhXmd1w8TVcS6JAgr/pnn7MaxPxK2O5bRyAn7uLJqrGiMpDxpR0tBVmd2xGRvs++UAIqv1BRXJi2EKxRXl4Uk9DnUHE3PL0K3gMgwT47xCBE+NI98wY5FfCxRWQpjGCQUmSBJBIKwtFNHOBYK8Kyk2CBzTNjHipL2DgJDfZcr14PG8uAsobh4rmSAIrJMBn2BU8XsJV4V8H92zkKYDVGWuKjmgRHjUnpHfNPzCpchHZiGM1xWlAyT8ecM+UVrziULnauJZqHLKvdFBLSrirp8opCLaMxVxYxLP3Eq5niuNDs8s4SfKyia4TMHlYD2WCV/eL8XFm3kuiRtNG2Z+wSyg7weLDmoRQUXx5MFRohiuR0hXWAFGZ7UrojqYJIv7NBOL7lz3TGfH3GlnCfws4OZ+wTrVIu1C0zPvPc/ZnhkQajL2QGOTtpJ3kh1cclDSHOzqACKsClI0T4iDqRLXFbqmLHx3iyTvHxIjyJXHK7cRa4qKKS7ysUxWgUvHwxoLjfD5vGcyB0SKXx9mwd3HBrHeNLh4wmgosSAMwtzOk8foQRflNElGfHItydcZ9wPuZKnjgfhfSqnCcCMCySuTghnRjBPIZfjK3oiVcrwoD5uQGrjXc7nxGYASuUmqUGCYCoRzZAnAnxk3eJgOMDy+pq74yO5V4RgPlXgA5uV/Kx2yhD/SklTqhOBV5asNNHneK8FgfKjAVmOy+XYUuAu2czs2ac3CrgBisdOW8SIq3KMDXjzfhJSrmBFPK7Vx75NgBVHtNm8U4UXwIMUxuhRGbO+BafmPCCOiq3zbFyqEfB547DBGIrqIkvOIS6s1EpQsj0i7PHIsmElcGSQhZAZhedgQCpOIGx42Cx6FL+KxuATVlZlqMkVeELz5XYCVeFaTLahVxCs+Mm0/FhZLh4uvwQcqFHJRVFw8RoS9wV2iNDjlAiwKVZ7iFhVWjwHhVfmCPlcnHOU6s9d3KCjvNWOIcYNyVKiyTZW7gtBFe4GfWVJpx3BXJ2wE8aB0fducfK5r6DBON4q/ynkp1ftz9kYKSZla1aRiJOCAMQws8qPelj4rLaEkqv+p6eM07hFK/dkMEtB5VItXF5VlM+eVBbwZeVBLPnlSD9F2V7sJqZUxSDMvM0Knj0SfiQlmqhOgOA2YXHZV/SbJUpBDL8XcJSTFnsqzQYNeLcWRbyhRy3Uyl8CEd0FFWESybxLMCxRUgqsd8aMdCAV2TjAVVlszUFR54+h0yIqC1ky1JdKmQbGXlJfCPPFkrVgFcZI6vx4zIEOlTVF6WTd4vuiAIrPrhHTLe2VsqqbkLSrW4QWez95WHfB4SY/iAokTKrIsY2E/1A0RV2JUURyUCah9WlVB8TsDkxZj95UfkcA5vCif8BMCqn8YXsnAeXkqmtlmhMpqvEclKu8VLC9khvmwFUdgNw53BFuYTI12SFG/4nT4GsreAkC5GjlVwhY8J9KUeZVc8uP8TUSUoVRqrwLnBZxJVUMTb852pA4+XC8oxJci+P/lVLwAAn3nIrwK8K+gw0pygaieUpv5ZmWLfxpLsQaggyo72YcSZBVQTKloLPVETFfEyyoeHTZDq7TSokpTMYNeV6X8YcmSJzY2cGsJ85C4S/blDcqlEZxSlAw/hlsZVFMpyObbafsVlKL5VWwdkV5V91WlJKBgnjgkyuJYEIEqb5akrE7jiBLkWK8rXoVrXtBVUMYlKVSAdNPZ/OBIlnYwu4vAv4zK4iZgHjBOJN5VdjlG/lW7R3ElMwzG5PsqnxJZ1Lq/mNVhoOGaEixA/zLbVVhJJtpWocoXlkkBKqX8wB5lR9sCmljMl1DkjOBSSXwcpnkN/LF/DSHOY8qLK5wSqLA2/GpKI5FaQoa9VQvlPZU+HFMCeEHRflKCrSgke0FGlfkk4tJWQAP1WwSpjVfsE5TEdJToZXeyqGGSB44NYV8ANjlAIhwVXt4WlJbK0yYoVis4ZNIcowOegSmxWotBv2QW1Kpw92YFklH7Iw1X7KmPS6GqskSeytJsFskyOAwU8b+XSAix8QYZJiVyFyewk1AyIAW7yohMXNL+9x/Kv1Mfjk0wILbUWeWPGEeSc4E3/6GsrRDGDBNNqdgK0BuGwxCLkKsA6Rn7yjaJYmqtJXezLCuf3414V7vLfgk58h5lVaq0053iR9vHJ8vQRZKEpac8mrrsF1nNaUrFKpDcWdKqXqL81h5XnSq4JogFi5WJ5WbOWykz0VkgI7TlUygGybzmGIFPpzV4aF8pg4Kyckul4UZ6pU8IuxCcI2NflChwx4lvHFXSZ+KjzVMYTWLyHVzeuBtExFQnK4ItUKIu7pRyaNsVhYJkzlZ7LWaQdNHmpFVy3nqwStOOHGc5Ai6cLvFrGIpWid+fdqVhMI/wkOm2Wqtry8w4h+yIYLFzDV5TYQ+aJhnDHxXB+Xq1ZcCb1VT9KIYJvXBPVb84lq5O5pR1XbAt6uWLo2gV4LjLLkU5POFbEinS5T8JalUKaqKidh7UBVMmrVrmrsqllfPE1PA5ISg+XYxOW1Y6qs1VEjKeXiixLD5WFc5eAbhSbhV4Mshiag7ElVHDhmLmwJgklddgtqJioz3BX0GATpQAnZZ579Y2tUPavKCRfythl5c09AkkrCxBSQodpsrwqzri+hKHWcjDQ6uXllRLn6wkGleIy5K5gHoKXABCLHiTDoxflLHIx4kquBIlZzMtRl/SSbpW5FUGud34ClwD4Zuol0gGiRVfgGd0gWqAVBfStYMApEsICs2KSxXPIp9OeX+LRVINNTTkJiAgFdDbYU5lkhvxWotBsZT5YfdVoNEsQYqnOQRJIqkNVpih0FVfqpGpZIoQXVGbEgaXMoDQ9hWK/9V6JyIISDSqxRVNjaVIg0rU1Vj+PjlfJwFG8MQSUIR6d1zVX6C4tQ7Et6pVFqt11d/09+sZmr5k6w4r+rGEaNPZ7CAqRVQlCQiURcfpVbTMSTka8ktVaFy+IwkuqRlXz7MYEju43bVm4SuwiLav2uWIsuGpFU0orkbIBoVAfK1YOm9zaUiC6oieclEvpWzfiTXCY4pLuZiifbxwaxBVEPXNb+NjKonFJdzmrh3yshyYlsptl0DzvxX1SmSiS4JWcVzvTUkkgirXFcoWc2JoPBhVUfsF3eWwofWEO2qUux84tSSfQJdwVeHou/FxSzsZVT4U95jSSMgjd6pRFetK6ZQejB8bHj2EVPhLcxoWvQqUSp5JL6wPLiv6sLstoOVZcFgFVZfIDl7etzhX/mUVuZjjElVM0IH2Xr5NKFYC2NjlhCA8/G7VFe8eMkywCjqq9Nh9JMoebAKk2U+dzlziOqol5B9cmeho6riPliRNr2NaaWeu7LIC/lIIs39LPXfPE51z7bGvCtRsIq7We5X2QHlXIEU03k8k+CggoquhrhPJEUK3K+Cga7L5kI3vL/WoXi1JJI2JFJVVYGOubbS27Vd6qnOUoI1oFbXih65UBCL9VADLhuRnRRzVA7F28VUdCwQtgKrjVirKHtwIyVp5YKSZKJBbCVtXzIWHxa2YM9ywAqarR9JOkJdCq1WVakTnEpCap65hjc06a1tRfuCr4rVuciqdwVTmpe5bxdB6FX7yoV6DkT8jo8hMd2JwMpiJFlI6DU+vyGSXwPMYVS1YAHk13K8lciCc2J4sdbtXQgWIeShaUEVi9EAHl6DSGFXl8tEJpAFzJUGyo2ib/HQ2V5pALAiuGvi3lEqqHqY8TrZYqirzQLZc/GYHDLBUwrwhLieo0f9GVVccbBThLilhOEmgsRBLtkmGtyNFdEa8x5i9s1DXAqCCGW/q1fAnoqnVKb3MdxN+KzIyUdy2xThiuYJV0k0mVmGrM0WsGskwB+krTMqQyvImTT2cyOPgtjlOLxCFV5DORuSk0fMVh8qhkk6qBaasDK/BI8HLe8wHyuumhLcql8X3L30yN3PBcVtywUgX3yJbmce2K1b7YiY1amo3NV2/iGSU2KQ+Z+cyiKyRRLEStgKh8cCITYjW6qtgEFOEiI1S/j4jUo/IiNfyCj6umPyCYkYoGAFc9pRu5a+Q/lX06PweaC04rVMoIgnmMellSsDK4Fg/DyrPC5ODVdMayvCKB8rBcDAxP1uaIDR6V9ErCImg9L+QItq1l5AjBZwne6uASZWYljVm2rwEmk5Fe1UjomZ55KEhfEaaswSS+kSJ+4vLU6Xul2o1e6qudJRtp0ynt0lpRbNgWd6X3Kkn7YaorYRS4Wk1wrz0JXpGrmZTu8DHJjPKc0l6lXbKIyanNJ2YA+MntRzJtom8vk1jkqfVVCmrDcibyia5ibzQCYdCtIwOKkvkQoSqEPygfMwORMEp3l7cqSMlsgFmVSia4p5UstDVXz7ITlpQmCTVP2S2qyKCplSfVCeE1c2qsfmzXSj5Q/4o1Om3jzhVevOiyiIOIXlzmz7Xm7kn6Vbpq615SipHJWe7UA8bsXGaRzQrRTX2vKg8l9ypFkIJqUaXlNFu5ZJeGVJk5RbuXI2mteTV+U8ozPxrXkPMnalVcEdxJEgyrTW3cp75YCks01VTg7uVGmobTmRYPXi+OTS9RpjLi5Wqa31JCpSE5X7+hmebAhMxVQR9hQlfxwlmmdXU7liiTrZ7tlGLNQS89s1/fKAuXLBEnyU9y+55c5kEOnbcueeet5Td6CyxKyB3nN6KL1gCHlsihbAmL+QgOgssI0WwrzRyj12PHGprSxfyFHTvVVmasX8pWqzrVlaoPnlBvFBFbKazF5+BDbeXEZO6QPfwiSVL4QznlbKV1VVNqo553Zq3eVamodQE+a+FV1byI/z42PuTD+8HbJmnx8xVHcRGiVSIluKzXKa7nofN1hmXylUOCAK11RZitqQM+SpT5gyY8zUoEg/yZ9sgapG1dIP4c5PpvPmK2AKAxzXLDVoyLNZw8BAFHdzVpXDuizidboXvsRZrYNSXfMI5UWa22hz2S8YLycBVrH+Er0e+Mqb15E/IcdrCkz/qJlyGfl63GcaaoNCdKz2S2rbtlAnEsBEua0k54y+XCq21SQAufaVi/AEAUwcHR8QiAUSF1bzE0CwTI5NZJ82MZpqrBfnVJNblQ+aob5rntHVUqar6+QfeOg1dqqdskJ4HRNU6qjb5A4MZeXEJKPUAMoGKpxurKTV/ulJtHQq40F+aA98KvqtctY7EGXiUuqbQUtWlgQuDK6MJXFpzAxy6phyY5SpMeSurXQUg5In2MVqjGVz2SOkxq6pxlXRapDy2/Ki1UW2mStQ5apwJ7eU6l4SmoPNQz8r4st2qTzXufNt/svqzplgHyCfHKatC5X5a8jc7urbjkQy16MNaakL5Kxy/dU/JIe4PWILVV2+TKEQTyp0tRMUhV5ZirurVHqFvfLMqoYmJOTtME8yuF5QgCkP+DliM+XYask2PLg5oV0+BgImSbBKFa1qsGpnGxlrWlqq52F34yvmHGqNrW96vHyROBHKVv7Ac/kF9xPVfoBcfJVGg3VUXn1v+SyAfG23wq6jbFFKYeGNasNUX/yo8XnCt9SPYU7/szjSETX9FIzUg1a535v1rDTXhgqQ/kJq+wpnqDNAnfWujBS0MECVFprwwXjuEm1anWZgp8TkfonJ8rSMQO0Hk0HQrWGbmAtgKH3KuNwbdjF8nEkQdFVdc7jVBfVHkWiLXG7uEUn4VauqLrpY2vZ3GrqgTI6uSGUgKNODWLO/BvJPLI2xXS6sdBSngVLVF+l1QWpoG5tQGqiopF/svpVvqsFtRiiP9VNoLLL5zCwCteqCvUAM9SkJW2vGKKYoNcHVURiU/mXQFglUiQLZJaCYsHJr8vTlAnk6aEq70P5V2YUVtSPPNflxw0/MkGI1H1SG3FH5S1rDYDJGoSNTbawXVnZrN3kxSy+5U7a+d5LtqezVlhPjwPpVT21JOSbb5JeJHNVO7czJy1J8xWKYSI8XYQcyJo0RZFCKfO30GS8Jc1PpKV3mycC7FY5ZCs1KVVdYwBmpuFCoClqk2PK8eU8dVIBYGEgq1adMVAWa7AvVcHk6vJvHh5j4MaoeWvO873AOPiIbUrvIWTuAa/q1Re9dyHNWs5+bzmIRMKsq2IVI2OeOOyq/UVS8K6/ARaO5VeuTK9Qk+o0CklJ2SUcsCkDkSyrn3hIgsTcNeDE3l98SXUjdRhslULafGF3hlCpW9o23hSfKypV6qq4QW1BBBtbTCunWPBqkQWWU2bSfXapmFtyQ/rVPAqG5Mpqr15Rz4RGy2qpdNUvCxvhKpq7sqBRxftZlybpVNlqOVmcRIytYCCkFMn6qBbVXAo+wsGq4tJZgoP1LRqptBVT4SSu0trAQU0KkgSeBqmHJRzxggkVipRlZUC/SBEwTEFqcUr+FdxsisViVq4QUXd1glQ1K34FRDqMRUIQqRBbZKdg143RIoUHLB3CmKK+tVvILKaporPfri2qjB17b921WKBKnteDsG/lhpxAQXmOncNYFTSEF4xyXZVjqu3hQT4iQ1wyApeXNAoanELywJJzQKCxHL6pXVVcChg8terGlSUmt5zHQfN3lO6r8YXdlFm1S6aJwJKuZL24nquYuFkC28+DorsvlhBNEWiIi29VXoLxoXmSqfVVkC1MsHlri0kojT5xi5a1x1siB3HU+WotBZX05tJwGqdQXGrzV1TOEnUFzF8xjVPB1TyTyLdso6uqmilaClaWKhqxiJYEcYUj66o4OYbk5cQwwL365s7AX+TMgjW2yNdiNX2FIF1RY6ijVQeShsbemrzWi4U5mms2rSWHV5PrmpHyt3lhKjzAW1RORtVgoY2YTRSqBACAqNlW8kizAPlwB7nx+AuCRhYqoAWFiG2ZcN1mIL6oK+6n7FJc7zlhEUKimCKimHAAgkubGmdducDtS8HA3GSLOu6VJFxLhouY0FnWPZCt0ApxREwUqDStjTOrphbw5CtURJTtnWtvjgCiBvd8Er2wjnX8XEe4mbfUcc5zrhcg3cThihdiJ51JeSJnVwS2R2Is6urZZnFEwpJXMWdWuweAS/392NHTOqPtoNxLMKSLUnnV7Ihz8n9FVelozqMLxEmT0oDuQCHY0zr+9F4cVXYBZkp51IRoGCohHz9yNi6m6mGzqlnJQ4TRdfY0DF1GoAEvaHEGFvKp7T515rxPdhgusriJBxOjYHcQVdhgurpxbS6ws8GOwwXVT3yJdfU7Ll1EYB5q6pHTNVPpIql1PO9S5l/Ou8GF5qNF1VlsHOKtHyCNIc6kBQ3l97nV9NIFQtM6szCsrqsSLvEoVdaKeIWGnzrxrgq2umdVLtZmKVqpm7YIurkZO2JUJhESLpnWYogxdkOvbCJTzrquzy+Qk7mIq611nrQ5IokalooDc63CAFhwcJIhcr6lQi62GhJ0l/17TVFZdUN4SHRErqjBhJICedfpiBQShrh1tTTOvHcPjVIjeh5J+tgJuvpQXBxEeWHAqFXViTEnHJ+xJYeMvpU3W4QCJepBxJYeLJLRXVXfIzdV9ffyhCbqHtSPcUCqE/Cfl13LxbnhmcQs4dLI6110PtIuK66DbTE86ph4W3Ff+DduyedZbyEaqWcUL2xqup4RXW60uo9LqQFBXQRA4lnFFAk2Lqgu55uqRSpvkbF1PoSl3UJai2OGC6h7YCnEGuCEZC9dYSUQC4S7rkUS6ckWdcoEnd1ljIv/bauoNGcrZO8getxU6prOrulku6kABgfxbnXbQqfdaqyfd1fwkO1JHamTODZsI516WI8OKgaFtpU86yR+50U9RCJaSOdb32HjiYZoj4IgesskGB6pU2GmijnVx6BLdf/y0ycRzrTLjscRNjuH80V1SrZUPV5jNDdQfDMGysJV7jTQutufJBxWdQ/3loXWFpgo9a3CLVKaLquqo8cSyloQYw11vCpIuLTGDUQCGqa111hIjlJCsvPkaK6j/kqnEduAe8OjdQAZODi1uhb0HRuqrAOx6v8WeKTDiBiTCC5WZxb6OPYjGbjUOBJ+k6VFn4qnqhtAACVhKpK1bZ14WAnUjQeqfcgrKVT1MAsKQoSWjxCfp6tbKNbV80CotBEFKZ6k5xS7qp4wdvFU9TS2Yd1qMEqRKzEBqBjAwWd1Lvp/PgJuqB2Uu62I6U7qEVimeQOsGgcaN1t4xVOIAWkX+N5sa11HRxK3UUBOfRNa6m8hqHrz7b9SmtdfxjRL1uIpCPWBvDkUi26gx2gtkzXWeyVo9WimTT1hOQyuafsWZKtrkq91LfMFOLfR3FuaK6iGlFVlOwgRnAXdbf/Jd1DVFFHhousJUee62s55Xr1eA5Yk69VR5XL1A2RAHh3kFoRZWCBl1IpMJvXLZFRdQK6/G8qHq2IkMnDZdUudO8grzF0PUCurG3IB6vz1IXqIcXRepbkkZAaF1Zb8dvX/iIRZKS6hE0T7qOlWiuvB2B55QKoxair3URklzQbe6zSwm7rp3WO5E7dWw6U45TXqiDKVutsyit6ir1Bfpb3WIqM/dfnK02SZTQs6YOuvnRA5xMLIZGJlDjtupKrEe6/00jbrAYDKLVF1LkwB11l4rfPXs0KzhAm60UURnr0CgJygTdf5cAn14fhC3UIrA7ZEu6tswgmIAvVZgCM9TwaOUBAXr5T53kGC9X+6y6IIOlfPWs+qs9cuIESmOgjCpCFuuH3HPaAr1e44qYSuepfpah6pmEzGJXPUwxR29adIR512bqU5QDkIK9c9PDL1J2Q1PRMuv/CN/gOL1J2QGjzkuu2wqnCLT1aCoNXWzqhc9b74UrsmHA8Qnw+vEYLBMODiiqtMUI9usKkNeZL3w49Me3XNhI19YQoqX1IChYMrHkHkXkdsT7IrEy9tYG7049Vb6mOl3CClPWY92v/v76skA3n1mPUqeoIqeaccT1JiJq3UEVO/YjJ68/Y++CFXVDD0MCBO6ggkNPqU/VvuoK9WKOc71BFTB0BBeqavts6nzWntUWODQoH3OFH61s4n3rNvD9In99aSkYeSxrdIkbN+rpAGnJZJKAoYK/VG5JMNPNwOGe83qMOhA6IldZ8KICU/vqFBwm8UQ0PtAp51ubFjXUpCygitM6uf1Gvq9ripimmdWvyVTioXD3hUIur0CKrFC7pM/MnnVsj0xsr6XVaGvfrDpYauuwhBlcM/1wmAAeIVqjXvmf6qnkevqiEwnuviYIQfRHKEkVsBK9+sfOEi6x7wn/rM/WvgqY4g+3ffSvfqYcLmeqsmK8PKP1nDIYfUYrEW2P76rnYZPM7yC/7G19XIEO+ARnrDrBvetMQO37Jd1mHdC3U0wg4eOe6j9VizZ/fXSklSOrZ6rhSvfqYEZEyRPYJx7fl1xkAShades1GF66ugNGts7yC5+qH9QnyEWKdpU6xXEBtZ0LjJNDBQoIKA08h0e4rzPB3SxAah7FVeo/ILkZCgNWxQHOJZSxSILgGuVWUGlmREfvRseJYoNIh15kkdTkNTUDfF+CX1dTR5vVN5CYBrBQVbu+gbYMEG1lgoLm4XeMagblRI1WSz8NJgRrYVgaS270+s7ll66s6iAEMWOD+uAJhlYGxRmLHB0VqFutJoifsIL1PJwt9hWBv1TgQGqt8fgaK0m0CX4yOCGbZ1pNFEsATupslqMSKwNP9htxIbaBQQbEG4+FbHVWA04mFlOGoGzzxJvF2SofUgVdaAvFckEgafpTgpm0DZlyNP1RjyXA1O1mC8udvEt0GQa99i0CWt0FwHDINTUJjAENBuChFb6oGpMSiGg2dS1qDR4G02SzJV6ZYZBsPEjn676mYwaDZk7ep0ZbgcNQNHFSDvWn5O+dcNUgw50AbKhzRvDUDeveeXyElp85UZBqwQpglW5u4Etig2W/GyRut6wY8EQaIinIcUElnGJdoN2iNoA3OSFQ6LMQdKyttrC/UPSluDWT6Jd1j5pTfXHWV59SqhHBEagaZfTOyQttMqcCINDDVMbJzWhhyk0GrzYRnrDyRE+qFqfMQMpqs6hpzlNBt5UqV6zTIj3I1A076GvMrOoSlkGQbCnZ9epEHtr6nWIIALOvXnYX5ddFIZzlnXqdRVEhrMGNSZWEqHdJjg0WCKoDXrlL4oGQamzkJBqRCbUGjCRCTkIZYgSLyDacRXz1Dwatnj8hpfoGX69v2bIalVCcBt99tWSbQNnMKJ3VavwH2NoGy86sFB9Wp4huK3GgGgUs5IagGDxHCp9eJIAx4mIbUQ26hoQhCiG6VVRob7A1C1JZPjt6kkhBvqhamYQsrdXnOUN161luvKgaCAXO0GiWCvnqk2SDBttodgG+RM+oanKllYCY4gx4IeMtwb1rXreqq2D0GrrYiCIww03BuODT9gYO6BXqXkyi+uGqXwlAr1Ff8ZQ3DVMRQee67WYcwanKlHxQl9RJsBa4mIaG3W+esFdEcmTEN+gpPvV0rUVDULUw0NBXrmtgbj1JOFYGvyyTHVeKDNuzZ9ZMQPOITnr6/bsBrHECfJM4NkIQ2Q08i2VdRcUtegfvrlYjFaWQ4ohoaXYNIbugzuuoqMmhiNQNJECUNImKy1DW8tWji8HAe6h7Bv//hq60S0JQpNg25GVpdW6tGkN1EgJIkSurGnPXcTYNGu4iXUn/QjDagswYyFapfBLzBrnHMOG5QyJgbbdLnRVbDbxAN8N+mJfPUgSyndQ8bcOI83AoRbHho0UIjlAzh8xIMg3USxwkqtYN6g5oaB4LvwyPdW5RWoNfH0RpK5alLwI6Gkt4m/pb3VLcgiDRTPdsSaRotXH++tgIDYGjSY3woiI2QEl89W5ZasNAakZRa3uuAYJ4GmkpI3AKfKa9DAlf/6yD2ZTVddDmWF79X+qELiWcVLcTcRor8pW6unAVmLZiC9zKtMoiQHvZhxATakK1E+dWByBcN8TA8rgACU/De4uKSNZgwl/rIOGeJf/68+2Ncl9/WMXCIja+ZW3172AqHa9+t+mkSZAdumayTI0ikiekjzAPU4uaE1A1B732klSfXI2xwbI5K+eviicO8eyNsIdoA1rqjw1PZGm2c3kaFnQRhsXVbCpMpog2oMg1/iAc8qFGgH192lecS3usbTPJGgeCb1A3I1bFAwjWjQdbSDXBPFSQRorBOu69mQbPqVVZOvXXdWdbEwNGFFOVKIkF4gouGwP5PHE9KDGRuODfswGVBGkatXWHEADWRa6p36YT5Fw0Z+z2de01AXEi4a0lkgcU2dRUYcKNJQCqo3PmlPOGoGiXkfUaPTSRHWODSv/ZV1uSpoWXTRrziJ1G9lkuVqmo1ivWrVqP6le2uEb04LDRpq0kNieyNKyJN/UV5FMuBkGzj1mCUCGkxuK0jZf1YaNnVwNg1J1Oe5BNG480vkbe6lV3IldQ6pTb1zyEAwayRs0japG3qeUGldI3IBtXFkdzLcg1eYpXU0lPpOA9GmCe5oa7mYYRj1dTlJdgNQHylo0AqAwjS4HU2S5Kpdkz2RoTFktGpfR4UbFo16uphgIjgMcNelB9HISBs9+Fx6trQLAE8OKOFxWYPy6yuWmz1w/U0M0luGs4DMAym0duB/1iZjRgKkDiMzdJAReur2CFTJemNDaoaY3Xk0bMjAQGHZbPrhUmNAzu+S+6tjp2WqZg1ZejFjYULQ18E3qm4Ce+pmNIlST4NaUrzQ1HanvEBO65HEKsaCdb3OXW9X7yTWNvD5xI2Mm2lYms4CaSfnEJW6XDW2ddOlDnxLPq+laFus5SYZ5fjI3hdbY0vMVbget62R2CrrctSx3Fm9chk92N5joqpotWniBIHG3oUiXqSCXyxtfdjCGnk4ehwmY2c9GgDchOUCCTMbBcAaBqJYH7Mt5oDB9ZA3PcLmgNs63igvRFSvXjlHK9cd09F630cAwJ5xt+HChpEWNsD4K40i/FvPNkGsUktcaOQI5+odovN6kjUwelOvWpagrjQyc8H13ek9w0fGBs/GsG+ckobrQemChv+ilb6yQu6dqWOAbzlVdQw0rhOVPr7UT8uvg4DSFI7uM4zDiDwcDMJjlGtm5sxB+lTn2E+9aEcc5Jw0R0pkfhse2ozG0hpkITXo2UazZ9deve8NnMzVfUSdx1ioiYLTE3cbrJS8uoSwI/sI+NjvJ3/WSkpf9XVFfdBo/rl4CbetXYKRJPV1s4DC3VExsbuvBwYvx7sa4HJLRs3vDAmpGherrRgKCxt2hBSFUJhHzp3Y0DTl5dSvMbX1DXArjC0uvX/lb63mNLzr20l9GkDjZ8YCaNTEo22IWxowzhO6xKwmm81nDf8o4jQYEWURjCbKlwTRu/sm96pvU24TMOD4xvljU5ZXF1gNAtKwWxoEeNdG0gO5Cb1nl6uuObFHGsKgs0apvShuofaeYA0f1m3iFE0GBDxjZQoeb17/8FgzHkEQJDzGkKlh0amVQkbIVdRAmzlSaoVpf5HxpG4N59NUKoDLa42LMGGjYADNf1Hxhael6urUHhXGq2CO4a7yJeuufqR1E1tej5xtfXWhV5XJ86r3B98a5wWro3zjaR4CuNuRDmE2daX+DUi0uLW67q8bAmes3qWLygr11s8thRHxpyFibxHCeucbjE0VZ07HML6jU1bcaq5zJeRdDQk7deNPMoog3egqXjRwsg71EgKPI1ItIISTt6pjU18aLAQjjS9jaWACuNCewRGwTes8VNUmp7mJAlocraNBaTeI4DDSsJUx0luJvy8onGznmLSbSPDxhoaDUZMbr1HxhAeC8OV5nqC6j4wuGoyg0Hqy8TfMhHbuDQbWe7mht9LlDasoNGFQK43UsGEDbuhYJowHwXiAXhjmppP3UN1OIa5qadhDqePLG51Cryknk34fKZCFbUPLC2QbENTyxpftGZGkdyoAqmQiVDig0nd8uJuCLRKLmJeuT5ILG05uAPEuLTTE3djbCm6ANVaInAFrOEA/Cb9ePhKUqEWhrswJ9QrePRN2RDHI1FShWMT7G5tCuM1VrA1xoVdcyVPi5qSaE778uqK7pZyuKNSNJrk1uNQW4g+0jKO1yazQYuxpYKT/YbZ1eXg+FrzcEDfFb6oC1wsa14Qz5muTZWMUXKmvQtaDmhsLKqbGOKNuWFeU1ynnJaXRG99odKbH9R2qQFSmh8ylNDIgsk2Ga2kBeKm4kxqHquFJqptZtsHGsqi6ihFU1HtgxTaZaYzY4qbqY19eozNPcm9ICBlhWA1AIim9WaQF8AQOoCvVZMRzDfa6eRB2Qbnk2KpocBhMGwNN2qbg01lBrwNUgMQes35k7k2KpslVLG6+UpHybZiCaZLlod6mwnCbPq36pSho2zkmGx6qRmk5rR5uBlTdveeqNYKbqw1tek1ADn66FNiqbCdZFcXhTRam7VN1aajU23/yrTa2yJ91XlwhU1Z4GTcbe6iDU2vqnt4xtiPdZOGRVN6FT4BJUn1c+Ncm+Pufbrl3VJpjHTW82OhNZyrFU2wFF5ZMm63HQ86aNMDMRvFOAeS7VNQxd943jbxNTdrQcENQHQAhQcpti5qh6pCOeKpmU3VIiM9aOpdJNg2gXTx0JrcEe7GvqQVwbJiyR+rqGTYU1JNpYrEU1lLlSTflcGFNFMdvI0/psRTX+mvGNM/qSU3ePyxjSBmpkIYGbYY018PdjduQjDioPTrKJrOEBDQoJUJhY9g9E32YkBbq2vaLgTsafx4wVCHXmLqd2NawKNfUsWCljfmLXuCtLqbRDUJtBMNdhRONZUDBY3lYFbOawGpLJhGa+6KdesdTYRmvdNaXq3U30ZsmlqSGox4sGaYYq+epFsHHG6NpRpy002hpsgzWJmhoNd6qxw0vxE4ykRvJIRXrqgpgM3GZishvf1w2zrCWoUNHXdc2Geb1xN82MCoevJcJsS2Yg2sy5kj9pqTEhpmooE6XAXvWOTAszbeNMANv+Vgg3VWOpCU+60NE/LrMUyLljrDYm/NzNBlxGM0baCDVocQGCaoONvU06Vit9W3QZYVpIay4a2Zv5RkJm8845obchrzyDKDWcrJTNFLIrOqzqEHUHFm7EWi6MRY2hRIszclDNONu1tx/X3AGqFWxmisiuWb4yaJxo9nIW6+5MhI0gvWZEW8zbPEIAG8+hqbwWZoazeMpIK1WKb6nCCgjwzUSQav+LWbx5VTJr3RrlmukeiWadVy5ZvVPtnGuGgWNLjM04oOUWjM3VK4oWbBwAlaR24BMVXLNApVKY1R4zkYLZm7tM8AlHC727FszfU4NOSHHr+YQWZu2IBvSBoN32E2fXE3yievTGnR42vqy8CEIFK9QeaepN/iZBuJGlRZ8hZm9fSGGl5S7z6w+zWe6RL1fj1Ls3+e3aSawG/zBCrqeWpEsVYDZMHBbNpqtWU3Hws83J1m1m2ckUSPUWZurxK8pWdQvWBQ3VoJiDGWUG/ZkmObtWw1WSylqy1CzNLhr6vXwB1GjRCMjb2E2bvEiLJv8iJ8TY5N1MztU21niK4jtwLLgaqa2dVCes8PLPG96g/xJzk3juC17tcmgxW2XryKWKpoX4KN1EHNOVCBc3OGzS9fJ5QtNDwa7vXh2nBkdqmp44LBUT2CfnFLTdSRWHNAigQQrXJoSIKqkCb1trIM03TGr1zarmjo1iqbeuIGcQktFx6M3NWeIjPWe7UPTdKMjBRMwaBQztpvkxaCmwAk7FzOs3Jey4zXeSgLNpbYVPKdhCBvsTm5sJEwa3OydZs5YG4GgPNtwALM2GZvQknNaI0k0eaJYKJxsCSd5mrI2iXrPnmA5oZIgCmqmi/caRWr8K0+DQ58O7NLzEIcITerzhrpmovNPIaKjJGcrBzQRLOL2LPqyRHR5vvXNAG6WFwoaIRlCNB29bU8l3Nf8im83aXTVTVqswUNN4lC022N1o4k1ldMMZubE2JNJqQ9IPmm4CCQaDc0i5pQ5b56rXNjmbnQwenB1jd8LJ1N2YlkYqCSzTuCLmxOklbqM6IaHAFzXHoTn1Pi12015XAnTQv7L11SchEhC6pvsIBiG+MZbwp6fUL8D2jdKMte+O3rldhJZh1zRcmeUNtY08c1yMusjRw1aS2Yea4qTYBoUmmXm/2hFeaG3jJxpDsQO9EsNK7hoc3NvEJTfdFP0NPvL/MRHurjqSjm1LaR7rPq4Z5rZAPumj50tqajuWqMmHTSW0oJsYea19TQBrvwnn65EZwFwco2X6qDzfYc+bgnl5vM00ervTW8qs3NbYsdvWVeCJflGmu5wCabg/LXpsu4HU0T714tBe81CFqPdcpSQ3NORNKI0mdnYLazMl71lvIzc1W1F1TT+CZL10ozYCDY+s2fsTmpa2RqaT5WD5toQo2mupuZuarVoE+uHhE6mqylAKab152RulGbNYrMNsAVe81BIRLDfCwNVNWSkG/WljkLTVj3TfNy9IHGoC5v6NRO696UU6azSDXcQYKqrGlqqAubRgRGptzNKfmgFQ57qs+5N+sCLaQQWX1j71L80SR1kqmFkPIEIubelnnuqt0BHra5NYMgyU3vaUHUIqm7vejIlOkr+IyKLfwMz71NfqBC19IVsXMm66tg1ubf+JLurtgtem6DgOCQmi2dxIbzSeJAr1OXRAGS3EHJGXJFWNNCrrCH5W6tJDRJm2YglmwVSBpevTTds617I3eMfk0H5rkscLsHP19Zx+40QXEb2FSG/wBMxa/ZDpZM7jUP1LYt9ktPC2UfCndeSmNdxVPq0flW+oC2Msmp91tUTQ3XMpn9MksPBjlWxbH14Apt/QJ3koYt6XMjlKrWCGVE8W3f10has4C3FtkRakGnJyT0bSZxldXm4P3jfl1wiRqcbK+oqMJ76np42sj13WCpq2LTM8DVNoqbqw23FiJ9vNwEyM5obH1AQ5pHlpIPLYthBx3PV99zPTZmQD4+E7qOMGFhszIMpibH1uQJCS2LbkrDU2m94t+f0Lc3mptBjbGobrNNqbtfXjCu/ymxm+kohJausAlFortrWQtUITOFr1rZBv4ze8WolQicbpi1SlsLXDKWsYttxAQZITZsjTeMW230THrBXgAlrjEjCG2UtopbIPa8RsTTSJm9ZUpIbfk1bFo2UN/xV1NBaazS1o7iEzXNHbktYxhzcqsBsrTe8WwIka6ai2TsltJsWum41NWxbZpxtZpn6nUcW4gApZFTKBVAXOaKW3E8xBbq3SwBt8cUELSt1sbxr03J8v79Z0lJskWxa1MUGZtaUgCWu1slSaQdjaYTVLSqQG1yCma2yTIlpeQC16g9NOJa6chsVO6LVuPLYtJxsmi1NUi9dZA/JgejBaC1n7FrY2EKWqhgHpap+BqKVy6Wz6mKYXWlEA0tDDhLUQk4w6dYaBy09lqHLUCG8U4C4IWs3tORPTa+wVQtYEcLHLK+tweIDm3bGvca9TgflAszX85Vv1BEtG8Cblv3wCRGkpJ5XqU9W4j3BLW5IPHNlMIKS3XZIszUaRCdNc6E3vUAZj/kZ168NwgObqirQRrdntxg33NXEh13Eg5rNCp1m8vkIUaK7b9KE3LfpmoTNdVsVy2HiQVLUmmzrN8ASDS3CZsBzTBW0r1MmbGw0mKF98vcGm8S/LrGwFZrEL9b6KbZ1CkAjwrnusLMXpGlSVq6M38pwXlwrR/cIEt4BgmqDkVtReLw5WEqL7waK2VqJBzc6ucitHFxlUmupu8EbMQFcw3ZdvU18AnNDVooeJBE2bh6D8VrciGopWdQtfRyK3EOwB4tV6/jRVoRLg1oht3XHJWxPWOfqQlXkVrB1GBG5W+kCiGXCGCCGoqwGhK8QGIrQgBjATTQZNUN1xnYocHqxtPJQq6gmg4rrDY0RvHIrYKozn1idYMK1kwggLXgeeb1jLhERqwUHVxuRWk1sGHEptTeMx8rU9Qyt1CxEoC13tk/+re6l2YPlbvH7CFq7+CJWjk09mbIyCFur59vyScEtdfhnK1IrL+kpxGwDwalbIMm0FsajVxWlEQpz4co1DIqsrTZ4C8sjBahbGlVoqAUCWjSkRAa4/FgcnXdRZS1itIYVz3Vu837jUFdaiRCSaflg0Vs9csIW8rEplbs5Tu0VvdVnfbX18V1NAhHuqR1QNW/5IJZacDhEVt7MHOixANOwEpq3LuwJ9aEMez1cfj91h1hoiBVVWzd69obPfBVfCtCIrfBv10xyRK2/Yz8Lar5L11UKLwhRnFqnZORWjgSN3ExuicXLurfiWWwtNsC7q23jAArQIeWeN2Yhp55PuqJON1GkxQYtroA08nGM+VaEe+Fnxa9HRZNytCLzsg4N17gIvWlVpvVK1W2h6p1bekGVFvQKANWh2ig3E+1CFfEYrVUcE9Nm8JLq09f2kuURvdR1rFanvDD5rVEYmqK0IUlboA09FrUrX0PBTN5ck1K2CUtprRauUatn1suy1WKl9QPZW6ZEsZaKBJJVo/ICEWLAtWU5yK3uoQJ9ZpcWJNwLY/qr46k52FsWi4uUoaS1A2hohCE9FEAtTjgtS2xWkfzR0eOWtFSYm816bELdY2HTH61wagU1qltx/JW6lyExyI5a25YH/zZFGdmti/ITbK4OmmYVaESm10uaXkKi1qmCGl6x84IlbQnTpRr26mCUeyt0/8yg3IXDZ9cAdGvKDQbanTs1p/BAtxLKWjlY1K1IiGGDRcmkStNNaSY3B+skrb28Y5NJVxWK28Jk5jeQkgAxBValVXMxTOya/fUqtFPJkYqS9M73tpWiW8fnElm6dvmLrfXzRLNE2Y7q1q2sS9UTBAatljwuU30llN9XHolGRE3ry3GE1tk7vh672wwdbDJBOlKc9aVS8itfhtUI1eigHlQVW/tK7nqNvUfYkVUATrL1NCmaKg0FBKI4PvG1f8qLqCgkIrVarQtZVN1BQSFXmtVqbJFvW4eKZgaqT4PYoOAHJ0RyY/aaw8YLOqcUN7So91sH8bnVH7KqzMIWs21d9bN/rkvUQDfoKE+tLNTyVJaxsPjaoc0qIL9gMKIf1ov2U11cUuqNgwG3MsQgbUVXFywYDbVTmslvbgPA2w5177jOgCslo+wO36tBtjSonPUEIBp9e+4wWkawaCHUZ4ER8deM1gNgPZn60/cWTid6m4+I9gb/2hJZM+9aWPC8N/7Q1fSdetoQvvWk7izEkGg3+3FZdfgq8JyZQai42/1pozWn6pM1qDaVImd7RFjXIysBtdHBzfVzWkRUH+67etKz02M16mGkbeLszr1sFSuXUFBPD4WsGr4ZHDaVfYMUh6TW5YMBtGQFAw2Y8lykJfWyrcI1snPVr5DmDThqtfW1jaPnbQNrbFGPG4igmjaAcqJ5U+DW4Itxt5ewM8pMZt4bZVuNKVnXq0USUNpd9B1jHEN5bsxG2FYK/yf0G/PE0jbLpQalodVXF6tet91UI02Phr3MNhyNP1DQh/G2M2tmalTG+l1VxzXjik5tJjfD66TxXHoNS2IoFhuRY2l1uBiDzs0azjAbQ1sdjihObUuKL1vnDCNVenJia4SG17yrwZWUG2tSi9bQrjQTkDrbsCsBt/Kx5ZKteufze0gINabGaYDAiVvCFCWW7dqrjwrQgiBDdzYTEpIN5fipZKfBsregNWreROsb2nLOVtpVHPWiIJezarVYEBq+4FLG7ISWHrzn5WjTBrWeSACtiKw8/XZCVlvmH4KZsCDayjL2htPIMl6sY5TZMqfXvNpKbVZAr5twvqYAS/1p4NH69MV+5I9pG0MckrDbgabxtiC8jPUNgn9dYvW87JrJa7yFnpr3MAzVSot0xNfm0frT/dvNwKNu2TaPoWlRvYoQiyxet0BAc/KdJRKrZ02/z2EiMyW3wckXrZ6mtyNtjMWm1hWE4LV0rEJtBLJY80ge3Q9b+416adEapNYINqK9LL6k/lCDaYOkxFvkCqy2sC4JhamRYvNp47t8255tpVao+bIpp+bePWihNDfrDe6E1t7QMGW9akO2xFm0x9gndWPYIg5BVbIsWwtuw3CE2jh6GraHwoKNqqupuI2stfmZaW23IUrLcBrCltJLafa101r99b2EwIS5TaU62oNt7EBtrY5N7Tg6G19lPd8sx6rVNJDaTCh6omkzUh68sJs8RkOJzZuIoHfW84SgzQRG3+MzjbUZGzwi3qbZ0YlNvQJdg9AC0d4I762m43olLg264lqDa823u+WwEXw7UBQF7kDvULs3+DSRsKfgn3qpgh6RprbW9QHWNojwFG3OfgYuQV6wSkJnrywlfJs+DZYm1tt/FoPGTqNvBvMm2wzh2wae8zy+pDbXCwDr6wIaBFDJtoL8WqZCENYWw521UFlArajOOdt8NkhM2DbGTbXI+fdNJHJLSWTtpAlFbG5XADocvW2z1SyzSCAE755bb/0WVuoLGbw2z1VU8l9c1qBOTbcUdACt+piaW03+M0fFkW9qy/bbbtyy+qgYM/WtbF8iYDM3X7n9bdiLcAqBnCIdnbtqO8kZ6qYs+TaLny6VEarUe9ZNtVtb3PXrlql9SRsdv47nqJSofNqBqGGSc912HaM230shRYVhmvkNj/jHaa8uv3Wsm2rTmVU1V2CGFtPbTo/XGScMVPPFUduN4oZGpEVXHqpqVnZsNcDSJZNt2KTL034vFA7YkIROWRG8dFintqawTp6wU4e2KxO3z2vw7XOWwjtLqYuU0EduTbQp2uhNy5bk20wdLNTWh2/ttHJVOC1XGEE7Wcs2MtknJNPWF7N9pK1Wk7cd7aCyRy+DijQ28Xjt4pSv20hitPbbb/dltkRRKdjltsIOsEWudiqLs3O11W3w9bRQ/etcyxTjgzBo2Av520Xe2ZMiSDPvH7bUDst3N/fA1DGX1r0BBFyemNzx5CO2MKJQ0pL02GAz7bCbJlBuhfAB2gNQ2sbk607lSuTXmYF081QaXPVFdsGjqMWqCtpcT3gkVdrjjYiEzzxOpbTS1FtqErDg271Nc7s6G0CgQhZBsW8FNubwkzaYloNnlPYkhtPIE/cBPloRTU1240qvcaUU1UKh67ZjVSsNJdBV62XQRx6tOlca4ubafZUa2Vy1MnsFbtZYsDS3BWCUAJt2o84Naa+AmXusG7YmtP71xusVu0k+xqrV8M3htZMF4poGcJGxCt2nzI+7cBU3HDQe7YuSMztVMoHu1Sri6rWX7Y7tw2Y2y1yLSSbSeMfCNjgDbG2rM1C2LC2xNhCjajkKwrifdU+cD5tRyF+pZPuqZLcd26F8qma2S2aNvZUsvgBgNOyrL63sqTXyDn69jNTXbiy26ptspVN6uGJPR4+vV8Pgx7UGJA7S7ybau1du1hrXBWh7tlIYI02ldurgsMs1ntvDb2e03coDTZV24UWXeQQ0189vQ8FXG23movqmInx9iCbVaW1Btj9h7jgwhrtLXfWmPmXcsnS2IzgV7YK8B+StaapXVERJokF36pY4mvbCST/1sLGMoE1XtNBzMXKBVFhgEk240pbIS4o0G0ml7agOCFSI6b963p8yfOGjWgMEK3bSAT/5uWzqV255CnHray3Lpqa7ULkzwtWbgX3VwxIxQKzxKTAO6aHu05yh29XTWprtghhbjYidqhpud2+KJtNbLBjXduNCsQhRgt3rTju3/FsJTbObfBtAoFY/jYRvupWN24SCf3qAM1jdt6Yv+m9BF03bK+3AZsX9T2cr8tdfbN3UN9tmaghmogNVwSLIB+cTb7c/WmmERL1YY1oZpW7UOK1GNdfSjwY9drvluxxLhoBGamu3Kx3n9SRmtPtUrtlnVYKBN8Ct2hfttGbRu3HdvU0Mwmr2AtqauQk53ES9YT247trObJ62k9up7bG8UCtkpbD+2d9tArYqWlvtbybDS1Q9sxbGjmzUthXa52WPJuaKa52hvV5TF8O3fVi3rUMASls2map/aq9rVIa1W/ZZmjaCHB6lTMzQ09GhUTQIg8YwRq0Fqg2w2waDwj3XS7GCDR4k7dqp3rXM131vcXiTiRANXmasB0bLy37ZVm/Ad1Ap03Lt5VxtfgO1U5QpaQlULNuviYLqNhtFJiSG19KAxQMPJdHNlFToB2zvBEbelmigdf1wZg2X9QUbesoa1yfGb9kAUDubmPv20rNCA7k8gcUnIbf5my+tTBQ9ThN5rqzfgOslwAj0HY3NZokHcoOyitKHK6G0FCk+wE7m3rN6g7nFDfupHcq7sJQdSL1uG2jZvUHauvfoN5cKlB2QH15zaEMXyNDqBdyHrZsDctr8dgd/t8su15Cl4bUwOoqt9MaToEUDuV6rR64ptxA7a9gsDsx7uueL8gruMJ757JoY5EAO36gIXFrdD0sKAHQjrHpt72bbe1W1qekt9mx2tbCgC1oatvIoDCrS+tFgx5bLBZvIUYUOuZshta4c3j+ob1T+8LGtlQ6Sm1MOV3BQwGzRtJ5FqcncNoxzar2/xmr2ajbaI3UiHeOvXj1UHx7SFlDo7ZPL5ZkRqi0yh1sVpcHdTmrntVcSKrJCsvJYKr2ifYF0kWc39uUiHYr46NtnObf+0pnMabe64fnNikSFvmkhuFzbb2k6AxNV28oS5umUJXaaXNGTVVe0zKDs0rg6RXNJDaCTbSTgm9Wrmi3tN+ogS2L5oUbSThbjU+ubtYCfDqVktDKZ4dpubbe2+ojorfMhK/1wI7J6RrBvyHXQ29Ky9R0nS01SoeHa41LrEela4SnAjsu9N7m8oVtvaoNYnSQDzQXKrEdzisZg3ZgSxHTuCKYtw4UOh3pSz69VrUx3tJcATvrAhsbOpEOwQJjDb082q9r6UUF2jy0LI69a2fepT3A22qPkI4RPg2l5pZHUi1Tn19ebbe3+MyPbdVi6hNVHR0fJBepjbvUOrx1SckyM1YNr2ZGedBMNPebVe0toKaTQPm9Ud27qnPVfZFr9eMku/FgobJ83qjuNVBs234d1w73SG25tnzbb2tdg19MDrAEO2uHSgaM2tPDbVe0oHTD7QRHSD5iI7GbgPHxZ9Sfm10d5KS981h/0iHVaHDztt+bn62g60i6ixwJ/Nmw6LSC1DvfzQXWSIddDtv800cqxHeGy+UNqDs/h1WqHTHa0JQUdfI7Uw2gFtzHWCU2CgcBbBR3tcsQDR0AfUNDerVvKURvQLbb2zNmtw6rDrZDujIlqE5X125zXh23sgoLRpYez1s9zkzgU1soLZsOhxM7o77JYfxqo6C+rSotTBbVe2rfMxMp0lNgtwI7Qx5uRv9fNMOxYxD1baFDrZgWHTYOVD1Ihb1x35eFSTRIW9cdhoDgfUWqLnHRuxR+tChbgR2C71hbfrCOUdiAIJy0z5BW9UmyzmqT7rdC3qjqKVAYWxDN4yT4cQmFup+OqO5qKVoalMB2RvGSUtcvwtdhb1R3Ls0cLf6U4Mdu4F7Q1uFtdHaSbY6t1ipVh3UMGnHetSErAro7uNzA1phnM0OwsYzB86w2RFtdHUOoGItCd9Xh2/twpLUkW10dWfdZfXXGVdHQ2tLItmDB7x10mQNLaicrVtrZh58ZuRpmeK8OtwRDY6qi3TDr5oAtW5uK9RaIR24EiaLc8mpcdPnqT00dFqxHceaCd1LrbGw3kbFS9Otm4IdEg6wShFRj8HX62/Ad0l50CZBtpHHSowsYq4bad+1zhWEjTjmq6I2g7BSCLk1nUEm2iQdw+MGA0x+BKbdx27ut2bbzG2JuHmsSstaINWlbL60Dt29qtgGqHw1bacuFUtvmsmW231JiD4jPX1tqSbWbfeuNJsdCV74Dq+mdamzttYA70v57Lwm9X229SdfRREvWrTjinWOMrNNnIz+B0IzwrzTHQgYq0A7hykG9t+BKOm8jYCDJCR1rtqUnSjSGYNW7alJ3LZ03bWQKiQdfRx2604d33rfBwLm1DAb0xT4DplRARWyD23g6jtY6CRhLk+2xqd+4YlvW3gRKbYhoc5qqSbv21dTvFlhSW/9tXU6EtSxlpA7V1OrnYMHbMUDjTtnqhJiAVNTcQup3SkNU7Uh2yydL5UFx0HTsYHalso9tSnbhp2TTpJrdT9GadV07hO6SjpRYF7ATqNzkgHp2BI2SRrR298djzT0GkRuoExBtOj2Wt/rIcl18HwHawrXGS3HbBgD4DohpaY2ybNq9bbOjKDvaLSlY6AdOYjZO3+GSUHUFSWctN06JB03WqzLXJ2igdmowDM1qdokHTGy5kNWnaIZ2fZGR4g/3XcthM6VlIUFqM7VvW9byV9rWx1nlohnc9vPqtNnbCZ1wG03HdNO9mdvZonPVdDWfrV9vCTtPjp2+29FC3rB22vztwM7oxAIeqHjAb6rBJKeAde3fIlQHY809Q4QTbbJXAzupBKTmyXR77aq6jJeTS7cLO5PxIsVlU5AVtqnT628P1pFJhvB++vLyEohCkK26gMZ0Z4EtnSzWPDi2EcTp0HAHLyDciODiTs6Ny2HOtdnQc8U2S2EdpVELOtdnSBSx2df6lBkouzqypPWIEDiiEcThQBzoJZYrAi++wOKY50MpD0pmBHSNZic7IE4hcXFMMbxROdyBgSfrsvCoEtnOrLGIHE8505loS2MKSYP2td9bZ0uzrMnjHQz9iNs6py1ezoOlmgkz9ixc6ncSnHFozF49A1+CV5W51hQDfgpFxfe+mvi7Z1UwX+CBffAga8Pqe52Z3B44jBHaolAc67uahXD7ne/a0aNYUA4ZnBzt0YovOjDoGiba50emhW9UvO8waj3EPZ1S+qXnVsUeedP/a/3WHzpnCZvO8kcyXqwoDrZl9nQ9ueudg87qAiE6XfICfOmedTvxFLrPzo3/KfO04CuzrN519iDHnRtQUgge86/1IJwofnUDTI5SMEdbq0Nzob4Wa7Mzi/7BKvpfzodlR55aA4LnqwoCrKgp8sgu1l1YUAQOzBzryBPDmrBdEgtI52MzzwXZ7bd3yGC7s51/xTIXV7O1fCEoYL75kKEwXRMLbWgCnENAgMVqoXcKydCS+eSMiCJztYEJIDJdoNzauF3SHEg4thHRX6XC6arQrzs/nYnOzBq7s7wmoHzuraUTJOudsCjGw3l5GaxiLFAdYoNa8CgdLX2knQ4vM6Ac7DbC4Qk3nTcbewNeBRr1LIxWS5RWmHRdmzpuW0ctTrrOYuoyYrd13yCFNrmDUYu1qhk862mDuukB2OrGKzqlPVhzrmLpLmR2pWlY0syXZ0ueBUHndfM1eY864g1ynTuvoCyxOdMnDaBIpxEvnInOrbZTXVKerf4FTdeXkGO4zslQeo33ASXQiGoBdYyJCw1pLpcoIIuzhMji6+tYYUnyvtbPVJdnWsmMT6LoPwKOmpRd2ul5521I26jUouneOhC6SdSVEAtnTz5YKweHFKF12zq6XeLZR9QipajF1kwBqsoMuqCtRi6yKbNzrs2AfmoxdfSkHOL8LGsqjYuhuOPS7amRG8BsXZKQqZdb2C9I3qLt0wSsu1UE/nqdl1RxAvneiSsJdHppgMbyLtOXU1OopdL87WF0VGDINh/O52dpc7TZzjKT9nZTOu2dezk+/rPzutlgkuzHGwc6nXooLqj5L1I2BdXooEZ1pLsG2H8urudp87eR0laUNLOTVBJdLM9Nl3WbC/JE8unVWPHFafi/lrSXU6jeZdNpwjZ3vLs7yO6dR9QEGaw53F9HuXWMuuONdeQffRorplAuMu9siQhMyF2dLoaysotXpdgS7GV0YaTJXafO9vo0gipl1QVXJXcy6oHs+NQ66HmLuTVJBxBZdK7qvZ2qBGoydAETYt4q7e+KYuRS2nsWmVdQ7xt75mcVhXQcurhoih5gV2CmM3dXgUNwUJvFkRlErvcXbqulxdUtIiA14FGiTOSpR+MMGaZV0aV2NXXBbcxdVW5eHJw9QMRPausAkjIk/4wY/DHnTirHrVwK6NyqaerNXSzxYOdrA1t52PTs9kpsuz3w9Lr/V3tK0RXVLUa1d18BcZLoruoTWauh4N2K7rnUXhrNXfaKSLihK7F/VmruDAOSpdld5i6jV3cruaLQWun6QVK6OHiv/hmEJS4acoKy7y10BzsWpWAlfNdXs7pGXUmUbXXbO0HUKD0BV2ejpdnWYyoudoqyxV1trr3bCviKVday6m10GFhiSvKu0Mmla6m0YYcVVXRGu3LUtN87r5eKI5XXrlOyCi66DV14FEQJLfOk1dNzqN12f+1yXSucnddhrh4bybzsjFIYu5BKSCYT13kNDIjeQUfi8CTl3V2GAjrXfOCFZaOrUySSPrqonoQuoNdh66mgQtu2OoOGu0+dScUNFLRro/Ld2ukxELBUE11jzsRIMcZfhYMXY3128JhFXZbEbVdqTySXwCrqGXSBvSy4Ra7UN0rrtNkvSuxRdmjp/Hjcro6bS7OvDdzyNW11EbuZ7DCu6ld5K6anQ3fKLXV2u3o42AtJvwqrr7XXuGuqon85YVK/FhHXXbOohlxNaJ13bLtBcLtfMNdcK6vZ38bvuXYvY8yqAc7BnQCdk3nQl1GUNrG7CMhFLqsztqu0Fl0ViL75/KQk3d8uNRSYEdvi3CbshWoZ5DQI/xb1N0FDwM4vnkqB+6m7W6YVWUQjt/gLl1dVQbvlpySXaJ2dMzd/djj51gcjHnfHgU3+F99N8iKhrqqK/WC1dszSfu1kbv7CihpCxZK7CdN0nkGA6v+wfywqS6IXDD7M3nc3OfJd+MixtTG3xhdepuzHGapl+FlSurqqKlux7isK6601cbpSko2ZRxwOPb6N0xbgAEuiunMk9G73YTQIKY3X4Uqb13m6lJI1rphgI4uz6qbgbSN30briCazxVrdNm7jkKZrtr1pgu2rqKVbmV30bvPwANuyjdp87BC1Egww3eMu9cItrrH1CNdry3SbiG7ioq7ml1LFPI3MOurzdV+adji9rrewSxuzc+3pBst0oiHX7WRu8Qe7HF0t3Wbs3Plt5TedaaIzt35JLsXTQsgXZ9G6dSpFLu4mLAGuqobihiO1LtGE+H1uk7mEHNn51oci+3ZuTVI635rNMgpbv3AcHOuoO3c6IXALkQvnVoKMbd+RQM509f0PTTZu5PkhC7ktYQ7oFrkY9Z+dEtEd11tCy4RcCuz4UB86anShho0CNLMa7dsFxzorvTNh3Qw8phdYQBLHY6btHzFtxGwFtO68t307qkXZfOiDdAnwo0oVzvvnSBuyxGbq7pF3/ru3wLzlfedAu64hxMdVeXdeuokgnLVf53fLtHXSg4DDSUc6o82y7uoqtTunz1tqahZgKWEGMmBHBztA66t2hjLF/XUJunXdt4wiuKOOBjXTruu8ATHFwN2Prs+wGYG6DduK6QN1PTprklmu7Vd0OUHkyTbvJXVtlX1kTG6eV0C7t53TWu1pRii7VBqcNUaoKSwuL1vcB0+3I8VyGnO7AOd26hd/QXzopxKi6sPddfB2IrtRxqKS7OpdoUk88d07ATHnRoEaYBeO7yKiYLpoWfazD+d4Z9o92PeEulLFu2vupe6u1S0cS13eYyu2dU0wv4TG31bNqkurTMZgb9szoWvr3TBquZNwax4Clezo2mglo4FdojCXt2V117XRK0qbtYe6hsbG7tw9kWSkngY8cFuIxTHD5qXuq7g7YlSUTrQM73SXQLCNObhX0RV7vRuD1unICXHqw90iklxmo44NbYs+72BxpyW5bKFJWfd3CoO1ISPyiyH3uyIIBgM6v7rcM73SD5QYyc3wT+Sl7tKOiLFeh4x2aH93v20xMr/uq1hne7qihNpjq/q7olvdk5lHXJQiqhWqXu9DM6C64bAbHQf3T9QC1WfD8zlJwHpcmXBxLsgSHFT52A9T0po+oIpVD+70G3wbvTSFNm2fd2wJ0JKGlk7YLgeiMJdql1ixaOU73eU5VeKVPgbByl7rAxXZpJUwQUs2D1PjxWXYzctHd1BJmD1GiR6mkNul/kUy6MFweRrqqHdYAziX2rxOIiHvVsmIe9iuCe6/4xPcwUPZMqOA9odiFOJMir9mOoejy0Uy6fqA962QPXbcNUyxlJ9wVwHuQElSu+O4vkaw92taUVMuPYIMZpe7BATraQIPVqvB/dklph5KU6CtWl/uv2YlB7wrHdzuaTPGCbldIAClD1sXI63VVAg/0r+6h3jIcUp0O93UvddQcqprVSocYKXu14EJAl0V1fW073RrgF9ilKhEyxJHvlpFtu3mA1m7WObcBVI/rq1JI96soqV1eCzqXYhHKoSeh6dayl7r62JoenY+2h6H931HtUPQyyM/d/o9pN17CSSPQ/My7d2GCCj1fKhGqnAuy3K6R7lW5/Lr3+oYu7dQ1Kbi91+1of3XI/BndY/Eh+Sz7oLRHapAxRMdov93ZwBUXYZmClis+7CVkuLpUzWruuRMx668d0lXGz3XqK68y+eSDPpwHqEtLFu1aeoe6RWrZfNi3diqO49Ju1PZqMZkKkHAep1ImLkppgYanUPbEfTo9ETTkD0aHtaPTT6yQ9o445IqlAraPWHu5goOf0C/ATH36PYSykgSn4r3KWMHqzIADxUIF/7JS92IZQUEhFu4VsmJ7T46/zpTNXAekD5v86T3gF7rRLJ7GgAIZeYdj1+8gc4rkNCD86x6Aj3Artrsr0WqtgsCVe12vSgP3aD8LuG4B61J1ezoPfvf5KEVZZgA53QHALaV7utDZwp6lfStDokfsZOiU9rjaTfqg/AsnXbOiu4u1tEV02TolPfc8Cqyum1HJ1RQGpHH5xLfdbk7P8hGURgXQNQEAc/waooBTWlv3RQUMtt5p6SMLYruMoJOum09W/AGj3LJtF9eaeumse+6FNSynpB8imu6wZp87uqyrfM2XZ4qvk9Eo95ZIpbTxHBKejGWFh6QDapLvpVKu9Y6gD2SIz3/eN7Xc3y9JNqswwgSbLt5sIYuk3d787oN37tpdnYaWUzxmy7qCIxnsx6nYuxxwnU7gz2ylJ63TTGVM9ShZebC9rqIMsM8Q096hV4j1TogLoUqevYhVU0td3bnWbPfFiIBdivw012lFlaIrFu97uWZ6yJw1yUQjpB2ys9jFBCF30VgjXQWe1wywu7ZT3SXkG4kue4M9SlNVz13zqvnbFBDAIXO7tz2dnqKXaOcRNdcLweK32Lom4hKexhd8O6e6U7rpFRF6oka+lBwx50BbDR+mG4Sf5Ep7fBSY2XFmTx24M9e8svj0EETIPVFAHQsJ0lKT1q7vpzN/Y45dKM6H90oGiK4hcuqvdexBYVIwXof3QGDeC9/O6JT3dklU4muejs9dsE+d0diGvXcvmD89f6loaWGnuWzuwu4ZATM7vz3VVye3RSLUPdMUxYnnArud7n6e3ZeK+6VYihXiIvfDKBs9AsYbz0FLWfxlEaQiNUUAA0CAHoqTQb6vi9PZiGj0gKOCDXxe1IZol6wT2YLt8LHhm0H4R3ELz04DO5XW5xTi9emAOsZQioJFBKe/ch7G6KjJTmgtnQHo2kpBG6UF0GXv26ihu8ZdQV12yVu7tPnaRCllA8G7YIQzLvH0VFEeM9iy6vZ3zVq/rRxujL1A4BeaSanrXSg6e8y6/6N9d0HLv8va+lWp144y7Z0cpBTVKpuvuiAc7SIXqtli3QEQCQ9QV1eQY3HsoyjFeqKe8vlEI4ae1cvQwGQrc0u7m55pXr7EfMe8ki2868K3OEOl3Xx4Aq9BVLZz1obLHnQaVH9daVieakWQH73B55fPJxrtwr2/+r1ZhffeA11l6A0jgLqDEna+Jq9ZGYgF034isPR8oXq8l26Nd0J7rGvUkifXduW6XZ3XDhO+oVutXd5g5IthFnv5LdleyHMTh6bTgilvmvb7TZGKWa7HF2wGA0hlZegq9iKIet3e7tOvfT0Iy9obrQVIQBOZqKb6269pl7Wt3HRAIBCFxZ69xPF9pKzbotrQr60mNW26OZQA1oezj1fNbd2vqfvH/Vk2Xctq/l1BvFVbo5btBjVDe726tTrFj3HRDdHn4uwe4USofr2eshcXZZwa3W8nqmEiibsN5AleKz1o6sVj3qQHhrTjevdN2J7MHbt7IV9Rqak36H261xnU3so1NTul00SYaa2gbo2l3bDBKz1Ie17/INXurDcaZYLSrV6BCWqetwMQAJfTdOlohb0+5nnnYHKOIt8RA5F1hAFN5pze/igaW6B22dzJxveEmYw9B265r1C3ryBBC5Ja9IN7uCItdto/ute1W9C5EU12exkhvYULHr6B17zb0FX14cu9eokROk0zL0iZoXUg7ewbdl0R1WXYrtrXQr6+s40B7Rt1Weu7djOu329Cvr+DQW7umXSzekektRalt3mhrJXNUjTZd16y2fXDxWB3MdQU5wN169iSW3o1vbDe1O9THFTt1+3uenlIuqwUZEbjoisYtxkuKYTY1CvqLlUTnuu6YckKz1YPc7N1BuCmgap6uYam57vwXMtgbvUd5a5dMrco72irIelZju5go83qbOIclCAXfYQN71SEQ8M10ntILdTkAgRLi7mT1WesdCUkukCa2+JVPWDtKC3RsZFaNXnrx/GYloMUcGQqz1Yu95d31OXApTje+CSmu6o7qDDtU9TyVEaScC65LXb3r8Ak9urKc5t7KMpPSUKPfoBJq9wiqKfIAjVm2GleobGxd6BwGHXr28IiIX+dkujMF0y7W2MgAEWK0aV7xEJT3oFyDuumW6xOVchrZOgKvQkoIpd097sr3i5jnvfA0vaNcARJm147ucStZu0iFKJC8d0iTCgffwjZ710nMXBW7XsnKhZu4+9jMavL3vQikXc2LKh9AlbQwSs7pOXWlerdVZTUEL3tXtYfbOe8Rd2V66uG13puXe1e9GgeDri91vLt2vVZsB29S7RFtxpXqzrf2ewCWgD7pEiSAvjnWzO9q9QqIH72i9O1XSx2G2mgm6gr1hhisIcdQJFdhi6ECBNUC23cJeKR99bQLD27kDTXf22FuJRa71113tmvtide7K9nD6HH0cPqLnMme/3dqgbCcjQf1Z3XhBT914WlWeIABA3/Ni6pnytJ6jOmrNv3tnTGAk9JW9oXUG2MoveZmq91FpoMr2EqXgHaK6z+iR968i2OZrfRoumz7gnyAUfWCEkB3dhOPJ0izrtvF7LtxKeT6l30RuNafjkDqvdZUCd/d+iMyk0IuscYBrgbldB9t3nWm23OvYmaT91FU8iZKg/C4HdU+7xIRJlKdA5ZqvdTYSBJyhK7hB3DPqx3UWe8QduHrMSQWHtKfSB62Z9Uy6HBz9xt8xtKOpjdyz6UfW0lIDvchkioNDNgShaiXq28tr6psJiM1nL0mDuGfZB7D29MBgCC0vcXWjfjURFY5oatKl7Oi93bk0q31zGCUeHM1BWzX0+leUUy7PYCbZuqfaDZKldFPItbiAut8FD8+zDtrz7/J0cHoLSBEOgV1aaF4N1OZDhDR6jKk83K7sIT1Jvi7SlUPh+aQ6bvXUSCYvU2+DJ9PMpFt1iLIKHQx63vBRZ7Sh1qurasBYe0uxg7qcwl7LupfbV6o9Sol6qS3q+EXTTFiSn4hrqQQLKXoZ4Q666vW7J7buCfuqqEm9elX2Yw6E3UZfmxXTF5RZNhqDT1Q/Pp1jinekwF516qBCFPp19StSu592QCrPWOCR0vbfRAG9cLBNX19Kr1vTAEe1aWT8ZdQOeoZCtVuw5Knd7EvS0cU+DvcOte9fnwrX2TmXkOV7epqkDZ6EJhs+sNQfzOKZd/np8X1vLOdPQjrI59CatFdAgP1C2LEm8ngb79jqAa+AefT28Ys6KW0ER0Busg9iQemlW/r7gSjSuWqlZiOgT1p/V9t3f4DxHQJ6oaeDR6NvhlhsJyFHi869uyVcvWckvcPeqgePNV7qTkajLpbkvSOir1X7lqt0EVEHdY3cUS9slSUfUQ60JfXCmfKtFL7m1Cevum8jS+3t96z7bJQQvpKFcjxZVMVeaBPWQwWxXTFciF9W8YBn1UvXb9bhAfOOVK7FJlJJtgpbxVVbYZsIAvW35CY3azkWv1uEBTjhbXtxjrs+919/K6cVHa5suiM6+z19rr71X2xOIaPZgxRZN73g7ZLtVydRTje5sJhL6HdoLFohBkFWJZ9eiErfXhYE33TsfLVtx0QOelyro7SKQQte9aGzBuJFciNcdG6oHOYh7nkn+vvbyExezxauXqJRoNHqolSJmgSxKs0mN2VTSgLXMsQd9A1A8P3zeoI/b4273MIkaKX2IRCkXZ7BP0N32B6PLBzt82W966AE1DJaH0+HLdfYWMNI+sW7WOz+vpHqEXup2d496czzjW1/nWzZEj9uIzx6S/broLVe6hbg2eDft3ktoRdV2SuSKBijZx3lutSnr/OyVluXqlraS3pY/XK+4l4tD63LJWep8uAdpHPdnEho3WKdJCfeYyMp9aF7CF29clE/dmW389YllVC3cvAePcCuuNdn7r8oHw7vC/Ce+9WMo01hJqIZqXfVaRaTdJoENP0gpmp3WOhKwtAsAhXIF+GgKnB+1zU0m6h0IGfsafdJu2zgB1aQP3a2sH3dNdUz1JIIgF1RqFQnQr6pKE5x7fnqhFrV9ecNCa9yUC171xruHkp9wfjy6r6ldi3zt7NMsGhdQlVx4r3pFry/UKhSi9+8d1X3PkOc3fdchX1lv9jjKrHpFoVp6tEMUi6lADcBpA/RcoPY93iSIX0PbxeXYybO9pePqVHpx7skBLO+ue41O7p71jhp81vY+sU9pvrNv2S1Mdve2GmLmdNlnr2uAUiFl7uuuhTAaXW7F5tFXQxGhAeZdZh13sBv0dKVu3y9NoaUA0nSVhXRn61SNuBaVl0aH2fzRVAfpQ+26fv3sBoi4ibxQ0s797//Vi1IQPdV6BQNChwkF3SP239f76xAETXUv1oPrvB/RXCP69fNzwf0jLB8vUe9WJNkWJbZHOPtEjQDrBWaZ37FS3xMAnggJez29q0bP+G4vsI3ftG7tMeb7i11aRpsnZm+xn9qkaREhlrrmNqG6jNmOskEj2gxvZUov4cG9kTMBI0G3sNLP04EP1Yiy9c1k2tOsf/6pyUsS7CVJ7iJl/dyCrq9Ugpe/XxXD+khce4oe/vqsJ43cSEXeIYrX93yIuH2PLqTqdZKIBd/D7Cf1YUF2Tew+wn9LLi0T1bnvF/Tb+kJ9Zv6Ef1fXkN/Z7O1SNkJg+H04gS5/YAIWtRXy7EJb/+vtcD16eOdITZe/Xf2U3PTiCX79LY1MEpwLsz5eD+l/J1n7kMUKBsBXj5etRAUbr//VffrEPbPa8X9Gf7NV1Lrtn9dsQZe9Wq72P2vNOXvduuw/1X3UQn1l/qvdSriYzdh4p81HV/vrVR+uq9dZT6fLgau3sXcnLA79aKZa70blShjVgTNfKPvKcYb/+pWevteg7dH37Cf3Ap0tPZNSVh5qkaPNChHulMnt6/IdY77tr3k5ri/MC2mx9KJTRXWX9XgEs9ehNiJYYCf1L+oL/Qq+yjYY4aJhbG5Wh3bs+utkVqh/71FCuODVUNRHK1Wajx2rRrtijhJV5Y36s8Q2XLOuXcvgCINGclab0N0ISjSdEU0hdF6XP61BpvuHqu3iyzOk8g34JjzvWVtEwN2sj553iTHJzU3kQiqoi1QG2MhsSkVge4kEUDa0AMaYAwA4D+yCN5uKV32DqGfzd8UPaSSz6kyQRhtvRrU+24BxUaprCevry+jOGzAKmy7Yiq1BtHolC+z6WKX76qkupoIPQdA2MNe8zM31kcAWLeHOy09UQDW53DVLVHHZeoI97Qbf8plrrMyatGuS2Qr7zTjIrqcqdGtP698jaoQ0JdSLPSo22/9KpAnpIBpzcRQaG7oSx1B4r7f/sJZdiuxlqImb/SKmVgNfv3wVzterT/xF2noomlqGqO03T7sBYQTt9yE1gnrdKB7QY3RkVI+aR/aihTwaKdnnI0ccBhGvystAl+Fj4sBAA934GQDRKgmg1VEjzfX0GGkNdrZQz3+rRlUQEBzrxOElHTSmHQBDQrmPl9Q9zjg1fj0ZEnN8CANw1SwdTivvBfWMGya68L7OJImBtzeENWn/Uaf7Vo0M1VsPZKUZptDtSZMR5vq7yN8GpaCWU1Y1Dc6rGjZ+QKfdBqqtQ2U4u3/fojYgD5CScB1ZPzIPQ3UlINGAHoGQLNobqTviz19rDMTA2GaBB/afMAa9d0b8/p6HtYQrQGqhoz2YDX47dr2A39sX99jvqTI2Smn23fD4l7972AMQaaOucKfpGoxCmf7ZW2rRrJoRSFenMzwGAgMkrje/bifBoDnwH5A04LpIwiYG48OhC6krCrNo2QILgFxdL+SqS09TwIKLQuzrJcgGOSgYcTSsfAfOQDlMCuH2TnXyAybSx398+Cxg0XXj2PYmGsYNeCgir0QFi1DUFLVeKBiiN5Wxhu7kqb+wZoM4akP4jftyKiwB7GqdF6YPx5RsVnOUzEedvLbao29MUlvXOpVcNL3cQn2gNzPjd8UdlkoX7q/4sAfuqisu1P9qhbnkKPAdw/Vn+84DqSFM/2k2hMjef5HBdzKiTo2SpV6PXc/FyNSkl+z3VemQjQulWc9y982QNbamuXf71NkDvyVrZ3L8AdbQEBgsW8x71v3IVpfSHeQzedGeMR42RBG/Mlouqd8R8aW3noXrCOgcm2GpSIGS9gGnoYaYbAHX9MDF9hU+gdAoIeeqYI1Sbn7kZLtcXSEmjnW8x7uwkISSPjeWur+9orp7c1qhTtminEIyYE8bkFSro1l6vVJSJN5VF553lQDxPkfGiN+J268ZxonKrA/PjYOd7wSAa0fLzRGZeumUoFca2rYo3ocXdUm/V43N6484kRSrA/eAaC9HNlR01ItKvDlIuppdAYHlZZAXvw2h0up0DFLrmIau3o2YcQQkn9UFaPjBUAuTPaz+neNhKDgMZfXvATVselI9zG64wO/Jv23T6gJMDA5a9l0mRH8TfOPVdMgV6p3WKqyFxEye5h9uSaxJLq/rt/RXG18Dx87uH3lJqSxPLJDC924GBMjE1XF3QGB6jUb4GhXbFxokssGMjzdZF7yk0Y/GRHTBHJR924HsdYR7rUfS0m5CDp4G/12RJu10iQe/R9kSa18ijPuIiAWBn0Ai/N4z0wbtyTSgyBA9aGA3vUc+TRQvt+j8D681NwOk/qYKPb3bb9Fa62OnSfHZPeUBklNBDsoj0FpCZTdG0sK4gL61ETuxoNmedFaA4SHqQtCgNOUvTKeklNcltmgO3ylHAxIM0hMqp6QP4kpoyAqkdLU9tgGyM2tg31PUoB7SDAd7TT2Cxv+gpjZFTQaNBYM0pBBMg6C/SddcxBAWzOnsUmfLGw2A3LajngDu1gzcywH09v0lYM3SzzmA0GeyDNG+ISD3diPljYoNKM90woRIP4iB0va/zRSDY+Ael5nfoqnUyEBaehQGNAXGxtmOgKem04eZ6RE1/Sto/jF6QONotwmX0VnqZCE1gkg9fJJVE1lhGJqml4Iad+UGmDjwbvBcTS2nowlUHYt2QrsDjdeufs9sBQ9E1wtrs0iZu+7dPRgEba0PpODEQml1u14Mvl07Tu4gy+c03934GEWhRVGxLA8ut3940GCFXHLsrnWs4Ciatd62d2NQcsUIee889JKa+l5SLqPPX1B3chb4Hrz0wJqQDG0uh89CCbVt0vnqBnSSml0Wt874WDgzoug8g8FHd9z7Tk0PACzvTaBggtvpcQ/rgXqk7eUmm34aHY9z0FgfX3L5u5aDuSb/oNM3rGgxYm8NdX4Gjf1wxQYdKNBus0uSbRGHs3sIvYT0uMMKu7ZH0wJuYKMOB1XduCaf9zWJIvvg1Bi6DAep733JKD0TdSEspqtRY6q2GuDluB6ey4sMCbfr50vrAOTAmvccBz6Iu0HQZ3Rhme1WdF0GuA6ZvvYRH1Bsp8ju6ifjpdpJTcPkFDxz+7NL3cQZDMA0erYe5s7kK37ehc/DceiyDg6b8gFPbr9YIW6ovek5oK90h/u1TWM8hbiBijHE2Y+mdyCN+nyYyRb3b0hPpauP56vaZdNJEH3BUEKzdPzPtF0O6PdAi5r6JvPO1+21RaeXgU3u6+J1bRnNfWwST06NJ4LWIlJm9gpaXc0otCZvRyCFWDe3V3vIXHqtdRCM4l0Ku7K32+5qG2sNevf6hebdoOXbvxnBlmg/cYAGR2wpfssvjQqAED1lJo82eprEPYSePHNoaLvgMtnM99az1Tq9YRYgVbTZrKgRkBgskY4hic2lS2jXXj1HgtYrQuYM4O3KLRA0559axkMi30OUFPbG2pXNgj74X0UFh7TfsChKDHJ720308GHg36kQ3Nz64ZX2esirTbMYP3dY4gnU2GnEog8KkZItcjloP1FKSQPVGmws8ugGDgFJJrK9CE8tmDF76W7U4wfLPcSmqNNsAV5fIEgpb6dcm6ZEFh7SiROpt9btvByn9yaaZc4Xo3uvU6mkxxbK7JA332M1g6OKqld4bgmz0JaCAQ0s+9Uoywb9vRq6T0PWD6TeDDXsMAOxQjPjdtMB5hTAG08xVpsl6qJev5yocG2FJ2XvduEvmwat5b74Nn1JvNcOg4Oy9HZi1U0dlgDvfsycr1NYiDY2g/BccTvm5isGG7SS3c5q7orHe6muIua/kA+Hroie4Wq9dcz74RFFFsGpIgh0NS83qk5D4zgbPTdU0eDCXZe10lt11g78OAWqBr89BrOFuObL2utQmUCHnhzQmtw/VwQw3NhkJsv3NuzEQwozNJ9WjxdEMU3VofUqq0/NzLEtP3gcx3zdnqtT93CoRc1r3FvnX4GfKdx0yXEQEnq2aIYhqhDs56SQNxpqyFR4hgbtH8GLVAkXqJgskWhzZfYHrbmawbYwJypROuKyJB02Ec0xvahjNVNhIhFbSqbp49YOmnekkIGdDwKwZ8WtJumcCg6bkXzUfqlDGOm8BD2iGejlBpoWKpcBnRDFSGF5knrqZrO2m5B48AkX1341I5TeNcExdjoZ83hBpuk+Lku8hoaYG4BkOuBPXXBbZItMUdhwNV/qjTTg8j9dB67FU0TIc3nUX+gpDssHc/0z+tkzabwXZNiLBtR4fZsMiPBum9IqvrNHFJyW0INFqk7NWr4mN2/TQB9aoNAg1hgDnKmF5pWUj5eznhcRbQ6CBHKY3c0pMmNBij3Io/PuqKoXmkyIfMGJyJHltUDrFurCeZeaz6TPQc9XoXmsuGESGC6gAlphgEPa6CDRpad7F67qXaJ6grYthgGnZ0uLPeLeK8Jy9/4HbiDS+yVvU7+uSxcWMnwPzQaWMC+AYm9gMHfc2zJmJvTihjdMh9I1P1G/q6zAnYR39AvaMs1Vvl83SqnAItNgL4hhcfvYKZuWx5YmN6MKLJZpjuE9uo00U7r9sxoxjovanqIbNBxKmN0magBrdhHf7x177uNwnZqx2n8hyBEJ2aFirmfonEmXmy2Est7Eyx1VtUGqzmkc9Mxrfc1Zvrq/YdLWzN3vxEn1oRJtDSnfRE9KF7q83bnExMhih+4AYN85oPc7s9zf0+p2Dz4G44NuoepQ9NBoAtr9ZvUPlwfslFfzD+dz29o80BK2c3RwJFHNumkRz1tQxRzVIUFXdP0g8c02YvM/XcuwvNaCTvgNBBpEzYsmJVsgZ60DWGofCyMmewDMpqHdvg/PrOBlVmtMwA5spl3uRFnjcLfZK+A1BfrFCobK4HyDTp1maGF3Y/7suGQZWgaxGtNHkMWCO8zYjyDADhJ4dUMm+WDRIYA/02H2aCXZTLvtNM/mwRMxRrjkMbbETQ5scBo9+eBFk20JghYd2hgL0Kea7x29rqj5vbmnVqIm8pl0QSXnLWIIDH4+2701BloeenFSuyHMCY6Q7FQdi3Q4jeQvNtZYa30MnNAQzy1TmFlaGX5L3oc2Fr2upVdZaGcJgGjTq/kJjBbNpxE/pL90g7QztfLgaPz7ykPV5uEwBkeOr+421C80BoDbQ5fcLODqPqvkOa6wWzfRgzBKdgq5+XV5vt0vPut4V0qHyEk48RqrNHAoPN78bK0Oukm9eJ7mjtiDR7hPxJwbPciehkbYxcHvD1UrvmEFN2o7lix8J0OtpRRzbwGxdDPgRAc1x4DtMoYA5DcvRa49kQsv23RPB0Wti3YeT38QasyDGBH59wkHSq1DKJ1vWbGiOt/Ulu4MDwe0rZ8MWH9CkGBa2+d3tfVRUQrNM7ZZHWSodOXoTWrkkhnldIMiVvMwwD+t9uzlaioV6nqtPbEm/rsmFDd32VfQjrRfvPfd9kGfK0qvucg8wUHyt7Ww8j0eQdKrQqyxHKzVdajEFVv/bXzBiwcm3qqdGxD1jvSFBxTDvPxqz0JntKreK8VCKuJb7KxO1oslaeBzM9otbTiJ7LrjDGWW1v94UHiz1y1rKFdWeuU0kJbDmQaOR6ePEGuWtl8N9t2NnrHLRGcFDSSpgFbxy1rr2JLevGDopaOenw7oHPfWW1tgTSGrridQYhCDF2Lj9U56esOwKFUfXOe5rDSCTP/1G/r52sPkUaDC2Ge3Q7jF+gx1hqZGzqHVC2vNk2wz6u9aDepaRkWXrr5DS+s/CAUi79oMulr4qUAum418kbrZU1NrOg2TGt/lxD1Pz03QbDLYXkQe9D0H3i2ZdLW/eqfQktCRFEH2HTntLSyWph9BKGA05X1St/UqW97mEMGfUOXGBiEv6hsctooEoNLAQZTLZuIvY9Mu7RS16Qm+4NBBxXd6OGkRDzHsxgz6WhakXWHtd1qlrquKpxM5REp5Ay29PEawxxen0tmjTPX15yn1re7HUldgl7GcPXVmAwwDrZkJgZbIXbJYfZg2GWtyQrZ6SkI1QdoDKL/Z598rj6sND+Pkw6LB7StkclPr26Xqlgx4+4JSOH7v4PkVpMjNhuwO92laMBUpQYuvXK252kW177L1JhtZYI+y6rd/16RK1ndVlw2eB9mtPPqAeITrvarfL+kO9GcrnK35I2egzQENjD2YhojqBfotSTrhmZoKcG0NTj1oB5Jdu2X67NbeVLmfsufCrh0nmsW7Kc7OVvVBtrBoBgMmH/wjoSq4/ZHcyJtfOba711XEsDQGYfqYqOGXu3J4fqEL/+2ZRiob33EbXWs/ZOMuhtxPFmqCUXoVTZE2kfi4f7m1DeNrstetpBpwwbaqm1ZcGi8C5+jv+mLbxsrU7oERnXhmeJ1W7nyYINosOJP+8HICDbMDzVnpyUNk297uYkHtr1k9q+EDFEdf9tja95V9933/eGYRaWy+HW3Kr4dYg9I25sWHt7af0FBO3w2vhnFd7OHtcMUtu9NHQTTtd316T8Og0AIg6QQY2tCLb1I57LuvWUk22rYuc7fL17huI8TpmPvDh26EW1EVgY/STusBtwEJib3XwHOmY62nMejx7ze1gNrvCv4+3QIF6JiW0MNBFvUhuEqdGORTv3PzvpYU/hoHNYEGIlzZNtYGn+B+nkToqqm384B4XQ9uDdNFLauPQo3tY4G/hj69A0HYH2Hpozw+w8pb9nFTFm1uXJXnenCLZt6txrl1d4PHrY0JLq94+rtK2M2LvXbIScrdJigGs2QgfksXdWn2dDH7RCMI1vEI7MhvP9pVbkQwMFX1XYv6sKVAtwFCNYuj8/XPIEN1gyGrV3aVrfsbb+09dhNbdmKBrt6QwLWzXYQaH711XoeSuqKrE9dwXjlq2ggjqQ8v2qqtdEStt394ccI5swxt9RW7SvHt+wsPePhzOt4a6Mz0WhlYrSXMzcDF/aCq0w9T/g8fhgqt8hGOf2k/sOOnCM669hXbVXgndKZPWQeycl6oYRv2Ini3rTmeRZ2v87orYhduk7kze7N2mRG1LmqEZzmmmBkzt0sKK9231sc7a53eqDBgT6O0ORgU3coEkLtaLA4R37Zi6TVR2pmc2X7kLigdtHJeTun9ALBpy23EkDg8rh+6UyhHahiNvAYA8Cg2ilt31Ty314AcibTMR+DdLulMW3+h3vffSUX+tJeQzAP0AbAbbyDLbiofxBUhgNrhNds+vmQB1bu/HlMWLfXOoilt2VJzr0CAZC7ShyCzDvh6LO306O3Etgemr1k7acEgX7sfpGL2pBQCY9mn1SNrE7cKajM9agGxO3fiG2fSqHTRt/rtYf3IQXBI1ixSf9xgHeO1k1mdPVUoXjt9ZJeD02AZy7bm8YIUhwHHG30do5KD5e/PptjbGO6VwdYSNPWwYjZ7q6AP+Abc7StyvZdsAbC9kvAXMfREB+EjdyRyEMxAbE7eIhD29CQH1O27kjLXRZzJJtEvx6XKZAcrHaEk7i9tL5uC1xduONp6aJjdaRrk20TavBPRUZKNQ0pGbPyAvuqAwcRnoR4r6CASYtphyt8Bm1hB+bnAkj7g9vZ0B7Jt4V0MAPJmgtbZjyQiS+NRmyHeNq1jFBpT40e0aX63HOTJfSkRjSBbF8zX0mC2MbaqCdW90MGkg1qKB2Fde+mH0i9aB2wCXrYhl22/HQ6wGuRBTKopbR0G9jiEFwzgORNrV+MAhsFwejbaODjYSI/YNEoFtjpt5QMfAcXrQWHDAD0oHCO26UlzIwqBsTt/1JqP2AgfU7Wg8bL9SPp1O2X6wU3SglaEjLeHBj0VmnhbTB0HlGdF7HNLKdo10l+BjEDbxHiN7BwZMZdKRp567BGq0TQkcg7vk+9XMI5H7wAo3svuBqR7Dkwn7M8ZVNq5ZPbGpdoCXZtiNVy37PayB7YjM69WP1cgemI5NSX89llNCw3OBN0fF3hgYN2xHxwYhPoKrB/2oIJUp6fgMfNtDyc7Jd4DvwHF61foyhfRsBRmNWjbVhHSbo1A5E2ot4em7O8j6toDI18MiPDchiKW0eHCgIxETJs9zgTrnSm/otAwcRy9urO6wcQ5dtHI2DuhNthXam6V/kZbcO12hlW2BUURo3/uO7TwSWW9jXMyiMpW28+q/+i6N+FHJ8SjQd1AUn2w1YlRHG2U9dpIbNZ+4AD53b1GqXbqaI+d2/kR887QmZb1ru5l53aTd3RGHu0B6ngA3PiB/t9jzmYqY0Ez8sz2n1l6z6iAM8UZwLD1uuYjx3awaYKUfIAyt29etTHUc3Be4LUo+RQbeDSdKd+08MDVuHM+/YjTXah6RMXvYA1hRxdWdcGU0A8AY37XqO5M9NxGV+1SG3afdvmprtIe0D4M0Ibko0LrAtDXjTpu2vev4A38R7PthoZTb1Akfwoy+LUS9YJHNu1aji23bkUantyuw9kMj6nymbj2/1aQEjSP5GNqa7agwj4jk8Ke+0q+3YrZZsbEjv3a18jJAfxI9T29xaOl6vAMlUa1jIghrvBJVGo6E4QbT7YVAra9IvrsqNNQi9WqD8Fkj+FGMIw1ro5I+lRt0k877o4G5BsRCcnFY0jZt5960oVLgas/uvIDx3ajOIpQalI65Rvf6GAGJMPT9swPOJh5Uj0/adgIrLpi8vD2vGcu4GWgM6kbFxkv+mtcXvbabDTlDLXZ8KNSjoCB1b1DAeQ7ciyQl9dNEiiMvtm8I9M25DtLJ8SD1Z937bYuR2XDXpGiiNN+L33ZP/EdtsMEqoO7AZHbYLQJf94ZH08MmFE+qSaegJgFnbG1YPkYj9TLO2c5cya7gP4NoTYukeJ4DT5HlQmLTWAQ0WR7PtnMLsaNZkbq7X0NOL9mUkVu0PKCgI6CBzyj59gTyP4oNJo69Cfs99o1SaNUjHv/R3vFFtVpMz8PYR27I0lRgBkRV6cQOuUbEiEzegkDS1Hz7YEnrk/T12uzVM4HpyMr9tjUcaB+cjY/ayUTXLsZA4P2jPGkt6NyMmUao/ZjeozU2VHfHgq7r5A9pRyx5xt9TyNNdoG3kfey8j2VHBI740Yxo6jRjUlRH6caNikdaDPa+t8jOXbBKR9XqBek7R1HsXFHvyKgds8evwR7+qzDabSk4Q2fnSaBwftMfjj52wUZMo4ddKe9iFGV+1geLtg00uVQN0yhzsrxEZtHYnR1cDtXa0xiihtTo38OjhwowH7L3UjoILGZRpONqvbyryvKQ8vXnRtDx4N6FV2IjtAEIS+/Zd+TaEiS/STi/eJu23t8mAl2wF+BqPNMO3HQ/X6A0jtysiHaZtRT9xfQ3i2IjoZRBEh+1wa/rzh1/wjovWxoaYdldKCv0CWkcHQDkNtMXH6rN2ujtZ7o7+7kRfw6r8qzfv0oAuGyR55TjxsNiptbMOVbaND/m7gx1zCR5QwSW4EdkwcNaNu5PVHWcsnWjQ4T1R3AtoY/clu4EdLDo871/4dfo676QTdmt7xkmwMFGA5NSHftQNSjz1rXvK3WfqpUuxuGAiPAjoSyMW+kIjwY7LoQe3q3A8GO2e10RGhe0HFhrfe/ByIdVurtMO74ZRPi1qzOjLI6vMB4IZv7QIENbDX16xe1+FwkmpHejodh3MH8PKWo6HQyCCujgSGGR1K6zmAy4RxEd/oYKb3d4Y6HSZgwhdV26Oh1sVsePaGWsodnQca92YQDwbR0OlZECtHPt0dDv10qb+v7dk46LZ45EdVwpOOp7wELlJNCtzrP1RhI6HdhZbbe2UThQo/bBo4dY4h4d2o7unox97LB9emxwx0BIEPKfg+5stzdGZzTNQY/o1XR6uol26TP3N0f7ySnBpndZQ6N7m8MdrslnRzzhKO6PUNJUfN+O1B98DsfbAF1Q4fQ7TIzCVxU0HImNeOQukkjhontQ/1qr2SPqJ7V+SnqDMEGkqOK/UqIwjO3KJrBLaH3dYcyY3kxrR9+Ta2lZv4iA3ciu9GJKk7Db2SjvzqQ/JW3dftHVcptTSd3Q/24ixCDGb+3D+tbmnRBsJjPODN8OutuDdQSu9O96U6hEoHPpV7RIOrd4DmGLcNRTqalqbeqXtp06FYryntDvdlOoO4t8H1cPuTvQsC8GrpjJDaJI0bMcG3Z+oE3Qfu7Su39KgfIHsu5+DXU6ptgkHtOY41O2p0Ka7bHp0zqjqrKR9oM+A7uyBq4bYrScRzXudB7aXxcSGBnct+nrdBIou20fLwcmXV/LiDp07f3Xlvrp6iZOhOiW17AkkotuAgL7iiWDuHETJ3TtIOo5YhfmdMucu6QJvxhwhQOjipdl7eJ2tTuONuER7UkZYaPEkpERTXdU8O5jPyxniM08DCjtAO8/YkIl7STz7iAHdeREB+qfBzvU5DowzftunZGrw6a7ns4ZLxANRlE+9YQln3sampHV6cOGjEXbUB24MZehrzmXqk0w7XuTYrpAQ9lO96GYh7qkOYztU+hAhs0EFA7xB6eAdyYDQOpgowsVPX1EtVRY1vzEp96kslB3tGTmAw0vDadGfJi31KoIhnTP0uy9sOAPI0vPLGmV7uihDEs7etz41EkAxIOyR8yQHxtq4+tmwFAwD4jssz0k2zYDrpRwh+b9s2BZ4iUsboid1G2bARgCU10AYAxDZ+oNXUZgH/RbZTslAkv+3WkO9G+j7q0FkQwruNNjWeJ730ghr6nQdwhzD6iHUWMlsdH3cqx06djlwUb265v+Y5eq2+dS48pu2xsfGrXRetX4fU75OiY3oC0nFO4tezNHbL2FPqwSaQovsjMQpgZ3c7hG/dtKO5jVSApXyyfu2PU6x6bDv89LWOj+BBg4lRxGd3sCu2NIQiUHR9gZmKidcOk3qDq7ffVBmkO6g72RyqbpXhNlO7Wgl59jb62xlRY5Fhi8jAYEP+19KFO9EUu4Vg50HTp2KsbKQwAhxEdsrGlWOQYc/Y6DQUmDx/JUe6YMdPZiCB3l5mw7Vh673pr1fpOpnG1oG69D5TuviXH4TY90mTuvXXxJQjAbBxNspg6W0ZLfrhWSCxlIEsdGTJ3fiBIvddssntZ8p7R6NUFrpqFOn2VRYGvHUUcYDDdcu6oi0A7xNxjkfF4RtOn2d9qH1nADEeXSSJ3OWDf6VoB0Hmh7mjHknjjn6gp2bzzrJcPpSxqdvMVA102Ea6nYiB41dhMkKONbGJE48YRmadJIafV1DIaeY83OLQjn06amCjIamQ16xyxCRS65kNjMez1eWBvP9G37hubu0UZThEFAGNV1ybDZlyt89HAGjK2+HMcEAh9JADdKm7fmxXVU91R+uHsqRzAFYObKQA3bXiW5lp4rNWqkaiaSE8x+4iXu//1zlB19aRxH1g1/6s+Mc7M7dh3IvB/W56G9mIBU2MBf+tTJalxkZRX/qkIpbszSCL3u939QilE+brwGzdqH+kkMvHNtnZkJoD/WysPLjEqoZ915KHTiFAbTjoi+7wf3PfEC41dcNfdhP7B2ZZcfT6b3+rokMPNwsCYMHt/ToQWrjGKIlANmlJXZqXEK/dBFS+PDacxZePfuz79DOxeOYgBNZOcQG6waN7NtXif7v/9SnkGHm7JQ/92qRocNkOHPbjwB7x/3cLrm4/W8OsD8TAUEHVK0vRcDu6v9fQZluPLwV3gzv6j8oS3NuXjoHqvdeTBVSWCKwgXyz+q4nNvzbo8hB7cPU2SFb5nYc6YDYORHgHXmGoPSB6iUmxXHcgUMHoafe1cLLjpqA1306YHl1j1x51Ckb7WhQq/HSuA1rXL1h+wnONUd2EPY6wOTBWXGtTJovpAhXjdOhBsh6SeN6RWwuGoez7jxWwsuMK6Dz9VtbVvD0xSmj2iuunwFSbYfcTmRD/VxqsJ40yyAGtxagqK1Zce9wBUM9f1VBMAeM/7h7WTP+//++HNAeMuHpn/c5QDbjdxBaf1XcbhhKrxuLWogG6A1WcAKTq8Rwn9BE4bOYBHnCPYT+nRFzEtDUExHvT/VIJLdmMx5Ej3p/o5PNpzMSYvNJXOPhHLF4+yyRxN5QFqiYVeJ8xapG70d1StwsAlHv/9RiRoG2MzsAyxR+o9ONFxj2kSSaiKZH4o545YGkv1xuxmeN16HYDeb2gPj95BZ42EqBT2RlY2vGhP7i6RdSwlUq++s3jy4hKRYVjArGr36olDPnHWb4zHs+/dDzdzjlZVEb1BgE+uFXxkxxZ8bdeMDcdoUKLRq7jKEYneOrjvAGf76xfBDAtQVJg0UP9c+I3vj/jzVfWSCTcEVlx4/gKGL1/Ussar49Kqf19l+0q+MTSUcTc5+R55H7NqhhhaKX9YyBrLj0plI32uOF74yzx0T9z9xauMn8dafZJgKvjEuwAy0CxHIfhOUcyFCz6YY1b8ddWhie4Z9PZj6+Orj029QmxCN+WXG2hDphu5wbebAJOzvbvf0BRONFjggKk9V3HfWG98b3RXVW9vjtXG1EoiYcgruf01Xj0KAMI1aLF2Ft0eUn9tET/g4fsywE2uBgCuB14MfF0bobqbm7W3jcwJ+10BAcqmqrzZ/c0q6qf22SgS4/KU6yDbBJRmEv8ejw2yBlj9MNtEuM9nobqer3CrjG8sLw0N1MmVHDxkqNcEa6PVmcwrGBNhqgTGSZauMQaFs3GNGgmR/AmCfGe+oByIxutQoJpwVBPSaDUE3vKglDLAm5sUBJzSrRGGzgTj3Ea7pdgRcjUGfBzigKrv8BiCaoohT5A0qqbV7I13HUi4sQQIPjVP6XlIKcTwrbI0+yN6K0TBPPv0hqgEBzaVckUzqgoRXCjW/BEDiYMAA/iQRv/Eb4J/6FpJa0qAmvE/YjcAyKSewb7jQxCfV0HsG0/DzgnZ6rLCAyE+zBRITIEK8IabBqYeOEJwkOGKA9g0yDhrkq6An9jAQHUClMdVKvaQ+xcNUq4PBNiMfPOJBGrUUvgnfv6OJteiMAcXwT7mo2MMEm2jhPkJtOm9uahsJs2HZTpYEGoDtBdehNHwUtA/IwSDinWUoBV2gdYKfkJ29YIrq7QMlrDw4vmjQgq8wbv7KbCbKogZA/IDpfMzOIWtCiie0GpfyWQmAwaUYacqSK5C4TcIAIg2lolZ4oCqmcoxwb/kh/SXcHBRJbIDBeUIigfahpDbCykLiUKLqWEvCfSlnsJqFGNUHV8LEinyE+bu4F9YgGlRT5CeJtGIJo7EqR14roOCYdqX+qXwTJ15yvU+dDroXCJtwUwwGo+1ZCfF4ZiJxUAOh44RMPkH3fYAcuAKxQCQwPcEmsRccJ6KSxJxLo3E1SCujARpOpQuBOVI3AKONCZGiVNIImKeYHfqDsR55KFFOvJuI3+3nmEyzUwQTFOsjX5K2LfNtxGz2sewnTZx35opxXKvPcBtSVuI2Esb2E+qDaETJ4w9zV0iahuZnx3iyUpKX+NnTg/jTSU7rG/AmHIyuIZNqUocLLjfi0Dv0y2DbZmXK/d930sYVB/8cd9gd+/Zy5ysdBMuofiYNm7ccOnomZQOP7t9EzkvaHDkIw4Woz8Y0E7aJ+iYSgmpFS9/s55rZx3EZiMHpI2VJhf44lVHb9hyzKcHJia2aAQWrUT4V5QPHE4a1/WqJsXjFg4+RNbqrh44C/cbjoiqo+N0k1V/akM6Xj1ETxRNDrOzwhj4g1dCkb6bWJ83wEyJm6ZSqVstePEtjdE9ooR7jaAmrk2b1LkQArx/bJZMby6LQDVQE84+ciDK0tSOYgBKbw1WB+fyqAmuoWlgYO+OZ8NfkAYHO3GeK0H8ZFeXJNTwlsubSBLVPbuJ1Q+gvGGaHbJtHo6HzGoGhbbyk3nicJ42p3WJN1oVwGPrXA2Wn0m436vfHYuLXgdlmbyHMtQkU7ck0suI0FkMMFyDv4m0cFi8auGGhBo/0/AnWy1KvqVnfItJhO4Z7fxMRd1nE2UTWdt5EHDxla8ffjvuB4RQ7M9ujyxQYAgwGeEcTo8sAwM7twAFm4eBqd5Sbd6Ifcykdie2siT/TYxeO/f2qTctgQc2GyDp1XbgZNQlfLCEG5UGWJN661q493MmqD6yh8Y0z8Y2LC0mm9608tQOgNwdyTRr4RjmwIwMl4vgf3DIwJy0UBYGvbESCYIYENBsiTiOz2uPKCeGTT/7Rfj4YnOk1aSZdEwShviTUUQDBMGSZYKU5egW6VGbsV4BuzpE/T9AsD6OTxlKMzDo7eUmkkMdml2kDMdtyTc4tGATKeAyY0J0PTuHDxmkxfoa5F6LDutE37vMQTir6LtYQCYILRbkIVyBgmIL2rRvQYV+J8fxXomKiIjzP0k0lJjD81sj1BNG/s61tDrMMTWUmE1UTs3C4yI+qwNU7K5JPvBxMDbpg6jmFYwMmPJBvUUJ/xzMTNIbtb02C24E296oYApgFuJNqTSsDT8ywXjLmtag0WsijVtzSwiNjjTaEXtcavZDaGhfkNXwxeN+GxaTdT+8gTi/JYu1HxuYSm9xs+x7Z6WJM/nq143MkbZNLeHfuZ7xzt3UfGt5aiEnAKny4e02PHGlwqWgTTfU0FzjShj40n9jXSHJRXSbXA1olFXE3Ym5t0ItGW2G2JigTANbESBOnS145GQLGDjsYh+NMCf7jQO3d2DhYmv8PkxuBky/x4rpbGHw+3dLv34yS242NFspoNYF42W7RtBtpm/AmMM7VhpnHd5a0DxFKamQglJOYltrKo7tCLRINBhceevlcJmCNgc9aZzspuGMJl7CsY93bBYPCsFD420wYAjCLQFLr4yewFmKmtjpH9KZ+NCoiSgzDlGfjTz8sYOVaia41e2IzNjCbvfjf81OnNuIkSDUxDV+O3/z6gzTQowWY5NQY1MmjXFiDJzW90bSUsqMCa3aAQWsboUQCxeNWzFUTcu7Gw2JEmdr2MJveDrWJpLqgsauFI9s3bE/wmyXq53GzlYiZrLSnH/RxJqiaXkAhgNdk4imr0j3YnrpPWBl65rbJ92NeEENBbdHmek2s4VXCCAsEUG34ducKPLb6TdDG1IMgHkmk6MxpkIlGlfubXmFBkyZlSBD+/GNYPJyZ6cb3x4RQ8kb59Aw/WTExjpLGD9MtKJaRxBt7cnJ31uIgmcviEZqDnIwJ0HsARajU65CzokKqWpDNTzS/+Nu6k0TY/SJMTxkniCMItEzWQezBTA9Ep3Y1Eiou5gpgAxj+UH6vH18bJIKSW0KNassqrqpzo2g8wsv/jCmyLoOPmiUE+acbuTs8B2eNvysEI910o9hVexAZM72MkBUfJlBNqnjmhObbuog7PVDpsYoCrLYzJtkGh0JlwI2ybjkQPi2xGNoR7cDSfS9hMImkEE4iYQRy+Qnal19Ifb6DANCIoGTVrwORsm3ErAYH4GTcaOAJDCZr9QWBrJe48nTJ3qyaBTgm22iTHhHFlaFsOd44IR9uNaRsTZPupro2KKepsTbgGIU5sbwDk7km3+eLutyFPXicfk0uJ4/90sHgySEOzKuoWm5lRQ7MqfZprWuTQOWQMTFA8+kMR2vs+n/xojihiHBaYu6y+ShfW65NZjRCuaRxCqI1GmpPdqks7dh1EZkU0Aol/jCWwIAPHTPW5Flx8LCxfqogwHi102KQSWXNyb7r+PxIMNzWZpGrmP6rJKNK5ttZHDxsZpz+aduDNLwwmLAwQxD7wL+BOfjNULYTmvha6VwrDmGIdI9JJJ0UcxFwOU1hEvr4xMfF/1f7pVL54CbHbil++10mz9uxMXEY/g7LC2sTR69Q4Mx2VD5pWAFyj18H81hzswRWAbxkpDmXsIv2G5rMatuLd197cSP4NOpBQ5m4eEKjQSGtaA8WzEmFoBqNNOJ0mhbcbBNZIvBxueYvGxH04IZAFu1xzUuImbzXBgfWR45iiWwD+MjngU9cdhDmzm9/FcPGhgy+pswdm8rXnjJJG9plgEnCk88OZP1yDRUHW4+KdTRgsh2TwTQNEObKzek3j6Tb1N1UqtqTBNibfWmmPa60nYjrxIZubUuJx8NxWgjD5hKdn4aIB4zuNndJxPFAbaFrv61ATOZ1200yQoyU9m6Spt4qbTVafKc7lq4ptgBl29L0WtAYtJVpLRP4FRgnU00PtmkxruaZDBYtPlNOpImU+jBidmwNLn82RUoE3qFMaYDunqnn0JPB5Fi8mlyKhPHZFmrNpujrqiZHjYpBRANv5Umnf08XacgGb1RRDKazgDCmwo5ZPGTqFuyYIQChzPOJVza6hns3kJ4zWuPP1AFpaSUQyYocu2mkIkq5irIFZkYS0AQQGzmoqmnyPiqZ10S/x8jmqzant7x6zlUyvxQxDHsVauO1AapLZBVScqM/GXcTtpuIxkoJ9QoocGghakCyobfqms/psyjCePufCljZo6FxQASc640mptkBi3x/btJqbk5ANycEcpam0fMM8mW4pBprAojPx3dMwyGtlz8yeEjUGm8z2n/G697DIbdHnDx/mjmqmua0XicKFh1vZlN6ahGBNHLX6U6DREVTVUDpVN8qesYiFsQVTiKauBNM4QTU3UMuu49fH00jAfuhytUiDRT2hyH03yMFTkxpMFET32bLOUBJxXhKAhjj1HosX+OiNwIQ8J5ZQWEUmAfUxfznNhPJuOjx0mCrGNkWl479JZ5D9LIvDGbcf8E51m0QC6+sQAmRwdY5uc2LQJ6po+s0xJjXE/tWFrN1qpEJNZ6x+QzVaXrmojsWkGblpUIqWJxmSwFb26CkqfGscBW+7BL/HF/hrxumzUfiNsOtu4TrLAVvsvsnkhmK1ebB4KMycDHC3m4VDqosNIFEnDxzRaKxgTdfAl4AtZr0tufx31IBb6IF1uexocgzVXLNJQr6+MsjQIw3oLBAW8icG04fZv74vvx2/gDaGoLquizSCFccD7NEtb2uOP9XvLV+THtm8RAjlwo5u5uBopnwcKeaZ2J5ydb4SjmmAIXAsa2hxDhRzd6pT/j6+4Ps2wCEJ4/eAfhh1ebex0d8ZTbAtmpnyNosTZxMWgVQySQOHj7Ssc833oia5ibOD8sW2a/pVNqeTJrlm1AN2kn+7UzqYI43JJhkiZaGrVBCaeoDIXmg/AieAIE5z2WnLQjbffj+608c1mgln5gyZAaNH6noOb78fMZAtmn0W/Anw82HocD5pKpxKTHmn6wif8dJ5hlm/0MIgmlUkBafaWavJ97iY2aG5MB+jLzXTWNhTrDQ8c14e33E8vBD5WnWaysCTILLlTuJw1DvVGzRNYQjxzSxPbWWA6mMs3EO3Lkx2UBlhvuazSbrCxwQGEywjTAf921Oq0QyzTvSXZWVV0reaxoZXxAEnGYeKOb4c7SaZgCAsB73qnaCKZxUFo+NflphE4stjfc2CZ0Vk5GiQdxUGHeeAaKcOCMlmxaGBfGeaTl1umzfIGs9m2HjBCPIjK5SQR4kG0o2mKj6IafFkynmjo4EGnVxJUafK4utcT5kH2apCZWKbnuR9m9vEtXGlKZsYdmjpdvAHKItzbM0nTO4k/i8aLT0BBYtMjLsPQ38bCiTmPIsgP3ABtgBVp4et4nLoK2BpWR48qeazT05QtJZrqH63NBW/mAjEn+Sm38fzyf+SlpTE6gFs3KTlV5p8kVf4Y2bG5aTSYFg77m4myyKmglHjqdz0fCp8ksUWbw81a8YzsbZmnOdj3GiAM/IcDoQzpiRVJ2au17bqafWWeh3sNFsmRiVlabQSbNJ7GkYBaoh6jcZqtD+h8empYmqCXJZuN4RcLNMGYVCWtPp8fLQKP2/OxAgG4ePBO2A/WBh6zWtu5o7kdacG4FXx7Z+xfrQepMERf4zbTbzNJeH6+Mm6YbzcRMUdT19Yw83KGSWkwOJqDDdun9ZNl2w606j0AnTxIqEc16D3wk5p8KXT+CawlOW4Bf9YImR28WvH9u1gFv30uQJhqO8kbNHEO721eGmhQcTPoqDTWWcd2fe98X4Ef/Gj2zzeu6rF2J9tTK85GcPJWTkU9kSN/9Lpa3nLqSerwKzh3AwJqm5Tz0Ud8cTyfXjT6RoBsOjAXT4yophYtkeJO0jKKbsJBnp3/1BZTdFNq0DLLeVFNlTCjkBiNtOJy7Ofxt41Fxb3bHz3Bf49YpjvT+EBymZPiYcUy2Wq7kwGmOHjbYeBUMarGoGWlH3i3zvFL474pggtbVRimFsCcIgQNh06Qw6sXwa22PeLdpcApTJ8nBBNKFmEvFrxhJT1Zb6PYs6dSU2qWtoIxotMlOyVvMFZTQLXjJ8rCS1GYjv0wFR3MtuWt1lPlKduILnoqvjIB0kk3t0g5Dg0p/QDlxhYyYEqdaUymW2fijAnOlNjlupuBXp5CIjk7oy0BgX4E+MpqrDvXVb1b0gzcAwIKgXW1KTXG0+lst/vwJviFVJamBUfy2kCQCWyjWmAn3XAaIVAM0lYB2TFZZ4cMh/Xwk44qe0tVbJJuO4e1SA7cQQaO33H171+huwPeotVATCqIAS2ncwu5tq8YoDMIcsZN7cflI+fpyvi9unehQd6bjOFwLTD40qnsRUb1DmCSx1PotxHV7dPCqYBLZk3KA2Tn7By3iXGgLOZ8GJUVWHOtJbid6nM/m/GZvRsMVPJ6f9BC+Iz5IbpHUUOi8kCU7DQgFDO896+Od/lEA4vY0MAgRmkkBJJqIoMT8drjkRQE+NAOFXQyMg2Mjn5bCVFV8ZLrWWh9OKIOmeVMAobqQHhpjNTK+m2SCoadyM2Pp6qywsnkfVFGcDMMLJ+VTHenJTSxaacOFnaIQztz485O/CiqwxRG9STuqnCS3r6XH44apwktuOlx+OVAaLLTc4v/jQMlpDN9ntXk8OR5EtfRovNMyaaqwwlXbhT7qnz9NzShb496pzfTEgtZBP+qaeLWXUJQTZF4xy3+sN0VojEHcjapafNGMCejU1VhqlEaMnsNMDYYMOiJJk2mtgGjLCBm2Z47mp6vNo45txo5qbFU9/YQbxAqmVQOPGci+HDx0tTA2HOPXdqZzQQDW1PMQ0cBjgoiYX3eS9JtTEGqni1xqpnk7yARzN9WpQ1J/8ZcmQNh/fSXmnEBODieLaJ1suhTA1bu5K8h2oU5ER5IQFsmYiMTvXQgsQJhYtKghWh6Rydtw/KTG7jx6g6BMFVo73JWJjti7mG/8wgybNg/12VkzyimLINxVosofXx5G2L/qWOwVlh1UwHUbStGukcpagdFSvXIRpmYOmmsr2imahuCIpptsqzbXzq9hr9UyHtSStfHVVTPgCx0IzrmPzTHN6qq2SSU/4/SfdmtDyEV2Zr7EGkyuYP9TRIjiXFWhHUWgVJ9GUmwHcH0xEiAOAyJVitokZCeM+zCVM4VguzAasnQY02XrtM9rJ40zC+gkFPtXCjLePo4ct5nwdynOVq+vLorbo8sDHuvFjLDukyJm246+BwfZNrgeTM7Tgz2TpVaOel4me/QQNW7Mzs0mexNKtoFVqmZpMzINA/wJkmYNwwIzU0eEZnZmMz1oXBJ7LWgT3XbdvGjitLEzb8W3DqkjCxZpyfVkzLY6G8GVivBP6+LZtgQuFSGfuG35oCSZWouPWlF14/HMbh7NtZbJ/x4RO7laYdg0yfkaQKZgSMJg95pzoOAXMyY8xLTDotTSOASVKk3qZiltfKFDTML0sPM68xOSTRYdhm1iuU3kwIeF5t9UoNFOEuTQI8SmIcOLjMqh3FdR4HMTwcPWv9bhzLp8d0wZr2ygjf7NpAlFbrQbYHsQJTBsmEG0rMrQk5Axw8zTaoGdOWyeGbSdobZThZmszM/Bm3U0hZ7StX5LiJO5mf/w4xQe3TNum9zA4WZLM6aRoKxDEd8TPEtu8SKUp9sMocnpPHLmXwky3R0vDnpYmuaNmdq7VUc4/2dhz/IHEtuiTIEp7fy3jairT96ZfODxZrBC7pnMDj0WceROPxq41jrbyBSL8ZfLN425JeBRnqLhXkfWHrFp4aSLd7/2jcLmk07BCGgjFYwoWWdyd7vQPh3uULomYmIvNoXxdaJxjBejbaSxV8fRM8hZpQMSJn2GIq4dCuArrJrTq96wa1g60tU/OiS3Dx2y5JNYEPcs3hwOST5gY+63anF8s5fehGtfNruZOE4LurU5EamWw/Gn70mKEbgJ2ZywUU8DDq0/Glq46w+mitnVrLVPpIymrYJwf6TM4TQq14+287sPJ/hk2lbwe1DabLbCyJoy6rrdDRP54XVM6zoNzT3fgFzPT6TYkwnyX0zIO9TFOrjv0YYZWgpmM/GsxlW+v67MnyHVTQVnNMPAJUX435Z7zDdDzatMg4fo1iONYyTXom+oRfPWTEzpJ94t+VwuIbzWaN/dmEaB5YYnYYPS4chGYvxsqTotb5MD56ZTEwNWw3GsOm5TwIzrj2eroJQTgknRa0XWbZM1O6lf2We9pAmm7oKrbUiZWVbAntKqi1pIHbNJ6ZcA2HFb2ui1jM0oRv5sxkjCLNmloTwsDZ94tYIsKLMDiddbcDS3jhzCnlO2fkmk0+np5TtwbgQdM8KbyI92rNzTgin1O31ShL09RRsTtTkMMxPSKbFI3hWJSTO7d3yPq+Cv/copgf5IXaw7796c0U0URx/p42m0i6CdrYrYhpoxTtnbQVYQydH0xzZ2W+c+mpiNVNuQ1cBprH0v9bBbNk8eX05i20XNYmnN9n4NqwqsOrcLARTLF63KTuDM4fps8j33BzPgovXosw1+IG2gPGbKNVNorVoVzQ1B6SHIm1eDouFikpovji9aRO78GcZ00URzD98Kmf9OntsnDAzp43gFTGEMmaKLKU9aZmDopfKEnho5nrIz5293jjSmxO07qoQM+Xs8sjMgrC+A0SX7bcFYbvGhfA+lM5dtj/lHxvAzvHbzHAJScTs452sAQZBmSSPpHJqs8jxsmi0JHPq4V6d3wzmeax9/umNlNx2dWnewZ9qjYpGSDjcGcOU28RslTS0nbD4DUdVeNnZm5ThAlbiNXGHO47cpx4jGZK3pP9UVNI97gES+ShmOO1fPFOw68pl8W2xHGbEjif+U8sRyEdkhmDDNH7J59cYZiFTTjb0G0h6b6A04oNf5WvHbDPukYjJf7pkZYv9bfl2lib4rdI2htio3HcVPSNtVYr4Z4j2cZGcBaBGbJU9k2kpMlUmUxIhkdFWWak9K4H5ZoW12YXr4xjh4PtXdjdJHsqZlnfInBFSzPGBe1CNvKutfxh4zoFH5SZw8dKMx2RlzqLxnLaPhQGsSbpsFAkRRHu2UlqZVU/DZ5VcXJmaaOnto0uFcZqzYzZHQjyaPuTE10Zh2zBVd5rOc0fLbao6Ft2Tan+yPG2c5Vm6psYzxtns8CEGc747Oxr54atj21NzGemIxOoRqzGvg0CMCKE/AbdklcjkTab7gy6eevhE20Cjm6KRBPhqegbSNs5RTdu4rSNW8zOM6eQsRzsYTiNNmZAUs/T+pBTsDnIm3b3QgcwTR9eAEjBj+M8dxCbSkuioz1FU4m1OIcrUzqByMjhfhF+MquGYbfJAgL0vfHMgCVBMVs8vCWEzNraoKNcbKRM7aBi2zrDmEBNVWehs4/dA6eQ9nCO1NhynUyOO3XVEst51Nk9pn4ENw1V4K6mjaMflVmk52dLWjIqp8JOPvjko+JcfJNTCdD1Ph0dE/mwJ09T0/bYmoXqdcYxv2xuAz5magx3qbFo8PQXvjdL8G22JSDLKsbpgTEp/beFRjKcl4iU2pvjsgMyeOvwjT7Xg6BKTIGnRo1XBO2GohpyDTclHWhIeifRNNoiZDt82Ah5NzjTHsHO2nByVfH9wIhdv45BXpj5KcHaCxr9DXjiQRp09tbAMGpbG+Gc1Qe2jQ+ecmTaWgdtslQBZycyqrMxSMakKQU0I0Ayt95yMXYu7DY04c5gR4SgmuNOHOZXcOpJ4XkvJHC9haqJ+4jvgudtR7lXLMSadPbRBwSb4dqnRaPlhJTQE1JmXOWcAR22DNjccytcGAjGHbDzyUObtIzEyxmTJ/DiKOh13cU26UBS6alH8Dh8mdxIw/20+BnstrlDCKu0o5ZTJzT8t6TKOBf1q4+skqod5ol0d5+iZ6c0j/fqT3mnOXPn1W5czEKM/TSlGoeqyCeC02pRsTDYWnsMOTtpFgMc5hGOG4ly21/wQbkwGMZDtmKIZnN+WWS05G2ooyJlnFT120cOMyZZwsEc7buREWWaqs6e2zcm9SmStM70ZZ7mPQBuT7KiiiOoGDls6846Ip5baSWQNyb14iF2vBGbDmrDM79v3tl08mFz9T7BiNill40zwRsUjzUUpbOCBDHo2M62fWEqlJtOTtpGiB4Z75cinUY3NRRKjUyH06Ej9CT/xMF4tAY/0jXbGTmnttPBuYaRMzx/bTz7bCfkTOeO06e2878vfHKdbQkb2BtvpvTtOXb97j96fu099R6iZhPGO0LYuZvaDTrEoGccl5nNAEZ6490G5Dtb27ojPxNNGo2UTWJWv0SwdPKhI9nLVxmcyAE74/w3VkL4LuBYdzYuSDOZDDC1oGpRnIzmrwd6M2lKdpjip3HTRtGk/gQSbR8ch23kGAumyHnPUa+xHfpwxN/1GHXg06enYNCRwyI1lt39PGdumGMRB7/TUPgLO0402NkxU7KiTYpGV+pzqZPk165qbiy0cnDz82avbZfOQJToumMu0GUIP0xos59tT+aIJNHeSuc8xWKdzG0Y3XPDJT107nrItz7lAUDMU0KLc6Gi5HjUi0iiPyFnN0960KjtyMdcDMkefo7WR57Ezz7bcJGZmcnbfzeEaTyOo3XMTEIJUzOaZLt1gmG7M+6efbTygGwWaFKT3U0KGShmZzbl4ylJt23u21HUyGCC1za8R0xPJeLj066211pHZ8InMrdsevpDZqcTx3alm292fkiQ/2hM4JxDknOAMdxPoiNddTGmGyh2YMC8Ho/k7VzkQ7g9SVid+sXKOtXpJ4mc23N0f5ElXx5YwBp6mImOebJ48+J43txo4K3Meedt7TVcfxyHimt72+eav4sjxpMkfw6pLi1qdKeF220Qk0MoKvFBYcRHXDa/PTkEnqe2FRg74w5YTlt6jQtmbq2YSw2p5uWJaEmwIRKefYQNBrbCTmWG4YmBkbQk1UcJTzyPNtlOe/Cwo5Bk+TT2GAsoOx9rbebRJvKDQTHifjWWyYk8Gx76WSqDSVMcSZ67U5RjHj7WHY+3wfwEk3mJkhQojAurNiSd+7QhMOcz0knfu2kywNU1IJ/rzIKYdrMqSaSowA8QMTGknPPO+bNykz6hoiJX6MW+OGCYe7SN58azLqHxvPxqhyKKR2m8OItFLvM1MeikgPvHUTQ8NmqOqMxWEzT+Tlz59wkdPaZhfY0lR0jo24t0+IvYZ+8wRhYKTNg6xu1z00tU1n0lbtp8NTTP08oLwz5rKXG01mtqPCUBnk0d56ftszddvOxMemkLFprbzY3bgWi8aejE6TR/ZjfqmUmO40ZDNlVJ7HDSVGejkyud6dPpR6GA/LmrrM9Ue5czEuD/tFoE8H3zufJfaXEuctyPGg5bDud5pBLJu/kMs6pYLgCdj3pzhvMw+9w0JO84Z+851RBuziFjOXO7SgZ0xtJh7tQhZR1PoTsq84RJA7xBXbXW3Njo4DnDZusdbZnFXN4UbKHeO8v/jOem4h0/MoEU4Xp06dUi1djMVazKI6PUTp2Uin6KMeJI1jOPxuvTxA7tzl8mepswEOva0Gin29MUDqddPvxvRTFA6dTTtceK3Oh25yYZGJuVPc2cxnX1gOKzU+mFh2Kvu/s8LZ+PzeqHJ9Pi2fj8y7ZDxTG+nER0dumXczvp14dFDIQdNBKcsY8CgGMz4SmYR0u+mxLBj4mJTvQ6pGkU6aNs4iOiNy7Bnn9MMjsbRNsprLmmw6JBy1ifts4iO4FSRXmE1ZFKciHRtoowW7tm06Mwao1tt7ZmpThvmEsCRWcZnvoBnIdCH5e+NC5Iy9TkOtlJyHm0qOW+YzAHGpzAz97Gq1KraayarY2nRuDnyhlP5UdkHeve+1zrRFNe2G2DU1TnZikjHiSgSYEqcOY0J1bG+bh4GSPpDo11F35yuzQHGxKL+6Z4M0AO/Pp26nTMB8sdR6Z3ZtuzLI7o2SSGcmo8Ixxl0/YnBfbCMdi6jcpt5Tk46xta92fUM5OO1HCvdmocHXjr23fbp1cwOpGgGOPAPBUzgx0VZBgUJ0Hodv9pHP2LezQzbdGPUYlIFiipzYdvY7uXOVrnL88Alf3mnhnmZFejseKWLxvwzjo7rKOkqf9IwnRlPCVKnOK290cwfGMpj+z1w62RNMqcSM2UO7Dc5Gm+IMyzuiqfwJzIzEgXO9b3GYJo9Qu3ATCDmPm1Vaxb0WoFjGjOgWrNGoQLqMzkO04OxGnMHN1jvmEHyZpozLI6pXoiCbaM3WOhOix5mUQNlDowUQCZpl42gWlLIIuatU9MOyx4kxn7VMyMe4XavJ2FzBNk1tncOcpAw35vvZDcmljPZ+Y/4H6p0Rz2fn1m0ZieDU3OOzs8M/G5HMQjuDAO6ZpRzoE7Yd7kBITU1wa6MxsMnJW26MdywBkZyBzMgXEf16BY8CzEUWtTYv5LGP5NG5c78Z10dsv12uPnu2YCwFlOSTTjnLGM3AW5c+45yCjJOFXpSdyZ8cxsgfuy7ankTMBBY0bJZx+2DfTH8knwrzo86f5j8YNotSLOfqByuJx5m/t0/qlfVkmbxYw6uUvzV4s38OyKiGI7HJzjdp/mb4HgGeZM08xinuo3GixMXBaRkMzxmj42wXXeKE8euwjSRr3wmhHlFObsxmnZ7unIp9aiup23AmGs1vcM5jk0p+ZOLqy6nXN28fjCWQ8WNnkh4mnQ5rWdkyr5lNmv3Rc0CnXVWur0qAXqTsxtjPJhOm6k7xCluOfg9RRxz8ckimWCnrQQKndwCwYzfXmMYBkqT381yINgd5IXaErJidehHiFqiKY5mF73khcOCJ/xqgQkFGJIpMkZm0+JZhYL6hQyXO1inUnTcNDRTXGq+p2e7QRc1gWZidcMUmMqWaYH7ZZO90h6qnPsD5NotwaIefBB+4dUG0Dt1xHsTwaGjd9bkEqyv1WOL6kZ+tkG7twkN7FfTDqF0tsDh95ZwfNvD7Tp9NILp5A6G1lRssXi8MREDZoXmA61qdeKAfRgdusyKBFOJYFsnT8BoXzqaj8m16UHNxS6J+aZYzHxJh+SfBeBtOtt2AB8CtP4DpHmVUpkrTwL7yNjf0hnkx8CNNjrDNYTPAoRWnev/VeTl+F1OOSck3k6+kC4LmWINFM5wZMnW+BW4WGi4sDmnTvyigtpiklNBHm5SEGw5cxQO5TE7XH3NMbTuvNCxpoMTYfnr3DMqijE48u/+J/SF5rObWdP88OdE6zuFLjO2grwa1jPx1ySfU6FQISOep8xRx4bylIX6fMgsaVubdZ7KdQsirPNPWegHaA/Rjzv5bukCIMVos2RB06d4dUl9b/Web7akKPsLYNnX2OthZvC6f5zsLuFnj/0DOpsAL7Hf2OgcdYABQwBwaGHHCOOUccUQCxx0AYG9GQCYo+EAnxTxwIyH45VUAHxEiSS2V0Ai0W8ZuAOgQEHENVwnSHBFlgACEXaTYiJ2QizcmVCLSBs8hQpxxHEOOURyMKdQ7A0YRfyKQO8UfCmysOC4jiCxTBHwECLYFK8Itl4CHCdhFxcJmxB6IutJvgi3syE/krEWW0GOQCIi30yLiLEEWmIuES0QoPxF7U4qEXa/Cq10wi/oPH2C8MpWItARfgi6szc/prEWCIvsYCBQiNbJSLRLVFICIIXuiWBF+rO1oxw0LoRdYi1JBLmY3dQkgrMpz3EHhBD0AJkXazmsRapFJBF8DggFw8Iu5aCkIOGhMmdlEXecxYRdUi6o6RyLQy9gIvWdENgN5Fp+J0kXCpA2RaDM6hF4mmpHhWIuk0ssi2AbWJgrEXUDBp8GBAhRFriLoB75Iu6vgiiyOIIyLqUXoZJawEMi9h7SkAiMhLYQ+Jwyi3lFsKL9VEvIsZRcb7S5FjWWyUWYEP6RYciyOIeKLmkX9ea5MFxAFhsAAAZgBAcfoZSBqMgwLpi7jpYLzI0kqb2ZJCeFoLQALqL70hzXAHs2Gi9BQQBgiVjz9GKbDxQKNF84Y3UWoRU0SJv4ApkCaLGyj5ov6oEWi9YMdTIK0XeOZTRcGMDNF3qLhZURos+xz9jgHHIOOVoAjL7bAHDjpHHaOOMcd+chKFVYAJcMGFaKccgFB+Jwj4K9FxpU70XLoictRei+9UeJWv0X19NOxkMAdLsqeOH0WA+XsYGSKPj/YGL+wGWAD+FBGjsynZ4wRVxWiB1of69LJnLZQ4h9FIDoxewbL9Fqh8nKzEYu8/Hxi+ME8OAMMWV4QkxcgOEQEMGLIEoSYtwGDjeI9UNHMOucnovuwgBi8OonCAj0W/othIIRi1GKp1IcMXMMEvRYqcLRQkmLnWkvIQmnr+LiLF97uxoAC/A6rjQTijF1ViCMWTXDeoJJiyU6B3gBtH9IEkxYitGXYC+++2rkYsCuqnhB6AHWLwsW8TDCbTRi7U6imLeJh++DUxaViye6OmLz0XFYvNoRZoHbF1mLPMWVYhEnD1i3qoV9gL0XjKSQpkpi6bF12LYOtVcCcxbZBgzFwQt0uz+Yv/RYdi3ymZmL7PqwkX2LoZ+JjFk7IfaocYs6tS7+HDFqZWDsWQjiDwBFi6jFzOLG2cIYv6xeBxXnFxFmfsWe235X1mgNnFy2LXsXM4s0OZETizFhmLHIz8rjOxYbi4CPK7klMWrYsvRbDi60KUuL12xzt6nvFti3DwWih4Xw+4ug9jriyAobGLCMXygw6rhViwlkTuLEuqB4uYxAVi+dvNi0wMBJYsPlAdi4/FevAa8WssTxxe2IInFpmGS8WjE4/RZZyLPFzOLFcWOC5YxYGocXFp1IrUWwAAdRa0AGNFz7QNCqb22nf3eyM/FlYTjsKoiA7RaI2EagImIGjY2bH1wneyG5rRUyrCxAEugoG/i/dkUNoFXqNW0+Hnq0MBil+LYCWFouPxYR0PAlsnjyBTQciVDzg4qAl0yg4CXkEviKGASwgl0yg3Mg/4satuHFGdFpaLv8WCEsSBsf8m/FkNuifqaEu4JYoS59oKhLOonP4vEJZYSyXmxBL20Xzovvhaui3BAF+Ad0W/wtOABjjgikp4ETEWNfCrxYRSQJiJiLuDFUgApxzpSRRHdiLxg92M4KJZa2Eol9cEBqcpEtyhBTqJdAXuA8iWu9D18gaIhLAZQA+iWe3jo8XDInXWeRL/696fpMRck5eJnOSdxFF1qIDvSsS2MQODyFiXpyguJcv+MNQIxL8yIXEsV+zUkDolpQ4fiXFEtMRY0S8EltRLTEXcCQqJfLopGIGRLyhsOC5YJJuUAcwbuohXwck4OJZ9wDDBXRLaCdP1C/93yixJzXxLEzy9cSlRf6yvSAFxLPIcMksnjGcS4Ox1FSaag/LL2JcX8u0K4pLrlYRE7dICfRcUl4xLCSWefIRJcyS0Elw8L3SWNqAJnB8Tq0l2JLbZN9BSeJaSS5pF1wCexpPEsFe1YAJwEI0iZSWs16tEHmS7bFwpLsmIKDAX6hcS2E0VIEoyWE9guJdlnMslgZLlnB9ksMW1Ki9VivRL5Gwi3apRfFQCYlmkLmZ6mkuWJd9SbYwYQAtSWqks2RtqVqVFuxLzKdREtmu2yMI8l+71NhBEZAdJdMS7vcYyLvQheku5dJgws8BMJlQyWAUtzJYqgGMln5LagINkvTJZHUMK2aKLapBVkuYustSisluRLdyWiDwopYpi5cl6wQpUXAdh7JfSS4clgvFlnBb4v3xYyAHglwZADeq4+OQVVRQIylzxWtx1yEu7RZzMG9gDoAB0XKXAspeoDdEAvlLBGAIEuS5HJC3Hx3IacjBtfAExZp5qMoJPIXpR1wAluOFSweEMVLnise9VTRq1wNKlouADZBFUt9EDlS0qlnSAb4XLoufheui8wkH8L90X/wsZ5wZ0l9FyCQb0WVGjfsWtS1OiH6LdqX145sxf20b6AFPO/0JXxz+FFPeKvF4VOs8BoYvqGopi+nXXL8daGZSiO5zGdFi2Or+91iEa6aOmEvq7Fl006ucnkC30RRBKGl4mLANBgHDvtTrQ7Ly0vO2EwChCuxZikN3FgGgVqXXUswLN5rtzmhzeUPBXjiNKjdzvalwWLh9zaQAp51rS67FzelOaXhtNqxfq1L7F2poQik0Ys5uHbUtHnXgMYsXOgVNxdqaJjVB2LEaw2c4Rpd4sMbfMKDnZdTaAtEbrS2r+htLANBEHzaxYQg3slgGgGVth4trpdJANHnbYJZsX60utpaPctbFgjutsWi0vd6jHS+450nO5aWbwhQ0YdcNHnI9L3sXRhhOpaeQHul12Lu9xB4A1pZdS5PF1cWp6XGWBNpfsXXGGWdLhO7UsT5X2mRDinSdL+6Wsf3ZxZHS/mlO6+7sXw0uBqyFksvF2XtthcnkDQkCnS+Ih8OLYtB50vfpaWnHIl5dLsgEcYvAtWnixul5pShsXiMtBpZfSxQmtGLigZmUH3pdWdHPF6vMvqWnkDFpe/S7oOreLZ6WK0ta9QS2PRlvNLAGWLXC7peoy5nFsDLNKXOotMJYPoFoXBfNr8W/5iSZY/i1wl65AIqX4SjMNFky6wlwBLf8w5EzOyWwSxyln+LJtA2hYTltgSyroJ5AHmbOEs4JaQS+Jl6GgemXnFPoJb/mJZluTLpmXuEvmZZVoBplqTLamWxdCMsGQSPyO+TLh8BFMvDTEVwMdMaTq20xXMv/UHcyzSqx/eunYv4v0pdToM5luzL5NBossdttfi4wlhsAhqWPwtfhZui2aloRLqwA445vYjKmZWloNsMKcTQWTKTZi3dSHCAaccCsucLwRi9s4nEwpWXtZl3fVdi0WyX1LHmBB4X5pdRGtVlqbihsXI9hppccwBZkntLiNzyoClZfpzEy4HGLi+w8YtK4ALEpSAOtDVmJPU6EnArpM1l2GLSuAh8DUxdBhbTFpXAC6UHUvpZvdSytlqjmRWW8stZZby5WrkEB+nQciE5lZf2y7wuvrLm2WcssOKtCGFll0P4OWXuc0kZeyyydlnNBQcXzsuPZc9dfAXY7LX0XCqBQ+Fay7GyaGLGl9h0uG5CvwvYu/K8+WXyFmrTXLi4izUTLD8XHMvY4EELfumshLYZg4cuWCe+YF5lq0APmWtKjuYCRyzFlsMwdJxMbJaZf1S5ylpPw3TqKh0GZdLCMTl+HLCWWzMuE5eg6IvYjvjn0TKOi05eRywiK7Ag6OW01hxYFxy2sG6TLYugT8l0hvqavZlhTLkWXGxhdxmzjTQl5GgPOXMbKBZf5y95lwXLnuAOcvY5bJy3Ll+LLqOW4IAipeSy3wlvyAaWXYACCJYei1pnWlUbMWoA11xc04ngy/XLAlZDcuxW32y4c4qrLCKc27LCAEMAbWKCGL5/E2rX5pdo5GblmK07WXFf47pdS6d/2HrLCJp2M7L50Gy67F33LmMWNDktEizS8TFkzpYKRpYv+IVhi1pnaeUj6WM/yrxd1yzlly3L7qWk8sW5f9LRzFq+OYTjH0vzklVwO9Fo3L5WXcYPGxcvBAGcV2LkZRmYsl5Y81FF+8vk+eXV+4SwQdi+F+ORLqXSxcJ1pfrCA2l/3LJQYi8t7JaRKY30h2LMQ5Pcvpiw0Tk3ujWLseXTJAN5cwfBfFoFSOWW3jNOxbTy19FgaoPGXR8sZwhAfiAoyfLbwch8tWLCdSI9F7qE3uWo4uvNODyw6CUvL9i6XBKG5YAhGgrYTLAmWoU596Xyvs/sPPLV8cIJKATBvyyXFhFOgBhRTigZcvy2hxG3LDsXkDDHxYLy49lu8hBgB88vm5a+i7GGAKGQBXY8NLbj7i7pgh3LL3E2EJ9xaq3JPl+IwQQDTT5oSVdyyNwcjLJvj28sLCXPy/AVujLCoxbiZixcr5uHFr3L9eXl4voFYNTiQVoRynN894u15bHNjmmY/LVQ9aCv/juL4O/lzmgtBW5i5P5b5iz3l2klnBW78uD5ZN2KwVyuL27Mx8sMFd/y2TBafLaLHACtz5bni4EeLeLS+XqYtEFe7iyRcnWEuGWECu0FYRWsPFyTY08X0M5LVxQK9oV1sSePpbcsrboHi9DCTtEuGXoCu0FbVcxhliw+9eAoct0pZhy4RMBCJnOWgstCTCcK/LliLLDhW0phuFdUy0Ql5iYkFdEcr45ZZyzLloSYCA9aa0SbDuUKEVzzLUuW0cvBFbOUJEVyfT1mXmJjxFYAS9EVlXLsRX0wB57I0rQjl6ywm7wsiuU5Ycy9Tlo1AmRWRcvhZe5kLkVkoryuW/ICs5fGaEUV/wrTOW2Et+Fa4mVEV7TL1QA1cvGpf4S6alrXLv4WdcuGMAq/iblt6LV9Qn5UVZYzy3XFsaAQxXHqgqh2Zi2NADXgpFg7cu0xa1mCty1UA/hQXcvvRaigGfzQPL3vhPcs6nvNnD7lryMmMXsGC8yiGy2IxvrLBpheCgppdK/t3lryoQX4o8vW/XbyzzwA0L8eX7curFZNOunlzjAVuXeiu9uUkKKblx6LVbAYnhHFfUKpXF6Yr/KNm0vPfFGKz3q/bLzKY70uDFc0fdXl2fLQJXICur3wHi78V8Z0DeWD8ZgleQIjq2LvLWxWigPg5ZYjpcVyPYIMJ90tt5dGKy8V+fLUUGuCsfFcey/3lrLOWsw/iuZxdvyxDF+ErsxXOeCX5bGKzCVv+MacXoSv7ZdAK23Fq+oMxWjCv5LCUK8iVuArxhWm8trFc/nM3APQrFsXzT2Qj3Gy1oV6UrBJWqCuilYvi5SVz7Lo/7SoDPFeBpNyVzArZAA7CsGtGcsIfurhtW2UXCsugBsBehJQIrHhXCitfoENK+aVlHLvhWOWBcKDy9ikVlorW/RPUDYMHj7QfJwVA7pX2W3ZFctKzplt0rIv8rFOJFYdK4GV9wriWX/StyzDe2QRWrnLDpWzSvRlcqK8TxdIroUAoyvUJdKK+LMOMrqZWEysiMCTKwaYFaW7hWVZgplaVy6kVqorPCWjUupZc6K9rli1L/VR2mhLuErS1/zGFOYe7z2MOpYh2SVlk7YyeRayvQtiqy22VoHMsxW+oTLZesPUD6JYr+VYg0th7uHNHWh/HKnqdE921fp6yzM1dXOYe7TFCrS3/QyNlifdCDJxstxSvXSwBe8c6NxW+bBLpb4vaVs/NLIEoiE6GVAcUa6lju58BdjyvgzOGKy2Vv+OjZWy7hHFdrzNBlxsrO9bm0uTJgbKztfS5ZZeXSUhfF0bK0XU1vLLkS045PlajULbloPVp6XbyuwPFoXRrFtsr6hlH8uWbo3K7qh13EHm7hYttldNtlOluBdkFWLyu1lbS8Ki2ACrvKZLyuIVYT2HHHDCrapXGCStlaIq3Wlio5OFXLBR/HGXi9g2WwufF7+3g0ZeeHE7FtsrVsWU0tGBjoy22Vhcr2sXUmokZesPUn3SUrPFWRys+8vAq+xV0CrQUxnyt9xeASkeV98rtZWHuBgFe7K7+VqOLrORvyviVaAq9/l+d4b5XRKgVbHsXYRLTsufFXLHCZxa4ltJVvxFqFXsJ18xc4q0liYCrzerHysVOA8zOpVxgrbZXJnbewEXXTQVxyr+eIlityVbbi5xVo843FWW6aFpfnK5ZV79LKJQxKsmVcYq+YyWkAepWkyuOZEHrAkGmMrbWBMt0wMDDK1TliMrxWAEquGeQtK8jQHU9GD0LSvhlcgS5IkAKrinbwisq6AKq7FVrMrEQAoqslVbQSyaVq/I0nNfBPM5b9K3lV/PICSQuU2+lcyq3o1UqrxZXEyueFfiq81V85NouWxdBpVb6q+Fl3KrrpXXqBZVfSq3aVzyovVXmisE5dfCxdFlLL10WfACVleES3cHB5kkpX59D6bBTjuGsRksHlWyibaABjjqtVmeD36XZEscF1rWGtV46r8SWtqv+HpgwhN6nNjzKcBo7RkiWK25a/5cV1W4VbCGUNjXvM16ry+8bCAOxs2q+IMU04Frxfqs2wFeq6T1NGLkGBPqvhrB8WutV+YibBXtqtHtgRi9QG3MSr1XgLjD7Fb3vElg6rKW0jqtDrwhq5jVm6rfBoV4QY1foulzMIjeKHJXquinWJqxQlbQAX1WUPi25ebik6vV6rGII4PJYls84QzV/sK0sX8au0gAOq9dV4mrHy9aj5k1fOqzeMVJsINXZWzjZc5ovTV8QYItWEYtnUVTeCDVhM4aMW+tZI1chq+OI3OedSWRE6srEiZjjF4EisNWlTCtmUFqy9VttY/jMpauPeDReltVs1aP1WFas8ZcOqzdV6WroQxTatE1clK16QW2LqIc1pxbkDJSzulg2r6q5Xav+H0iq91V4IAzPsj8VzL36i37Vvnazsl5S4MbAFy77VkgOAdWw6s7eE7E9nWgM0DVXRqsNDDjq586hOrMgwQ6sTRoTqyNVpTLplgU6v8xqDq5ObHqhqdWtosR1aSy/NV9XLdEhpyDpZZ1y6IIYoYDqWDcvvRfv4OJMeurpuXG6sBqQ/KxMVoGLkkhr9y9lZlBkoV79O+lahyu3Fbri4QXSJwYeXu8uLp2pubsVvGLfPgyuCLlaLiDPV0QQQShzise5eRi6IIIF8ZMXo8sWxdEECduRbLfdXE8u11YyLK6lyYrjdWUT54VabGDCtR6Lh9W8Kt4lc9y9fVzCrexCP0uz1brq4+ltlYqeWm6tz2Vfq0/fZmLA9WQUxl5ZRaD4nWer/dEDX7asbXq2mMFf+b6XV8tX1bqpM/cvfLNBXZ6uuC2li3Lkxgrs9XZ+OgYkEKxfF0erSDXMKxcFcILmPbSUroshn8vfpyfjCnF9fFlcWm6sXHCsqz/lkrL3dXP6twNabi7Q1jurPJW5CsUNbUq1AV4grxDWRKscfgHi3g1gyrUpX28tYNaCq6gV0+rLx70GvKlZEa4g18wrHDWYGtGXzIK2AVhBrU9X6GtSFe3TuJ+OtL1DWR6vkBesxBg1kRrgQIn6C8FYhi+vVkEjhsXCGu4NYtyF6VC/LbBXZ6u71bUayflkRrL9WlGuYxfvqyAVmwrFBWd6t/Zika/3VsxrbTxcCs8NczgEYwIRr2hW0K6zQGcq/KVgRrmjWWCviNdnq5EzNWLihWD6syNesK7IV6gAPtWrSssYDh8x1VpXohxw6qufxezq75l13oaTX8yuQMGv4JqsHwrLpWc6uu9BhhdJOoqr4vQKmszVaCK5HVqWQNTWEivVVYaa9DwCar9VWcmsY5bzkI9OlqrcVXlZD5NaLK6U13JrXTWngqZlftK6zIfprYWWyqvVFbRUGpYIpr2VXJqu69G6a+k12arrRXy6vtFY1yxWV7orFqXDxB0MzJK6QmARrD/Gb0uL7Bjy9lAMrWZJXurEXZyl0BryW3LaXg9u6N1fzgPuxg1+k70R6vNIPGOCaeo2wa9WvHaRpd7LaccRurhqC40smnoz6n81q3q8IJ3msFkWBa+tmTerAwoPEs7NYYy2+lhrhwLXdmuPpYuaz/V9XgFaXjmsE1eegGc11vLx1YDGuHNbVK6OrcTO8GBR0uNUFHUPc1pS2SGXDj0nbHJayyuUyrfL0TEvPQBSBWo17kTwLWXRarpeyJAH8YFrFqUt0sctcEaBC1oTLZ57OPWItbha8Dl3bGiLXz0v5XzK2nLF/cgSLWHYtzazXq5XePjLcC7lYuHiHP6QIViqaO6NkmspVc+YO0gCctrVXIGAkYDR+jlV5KrjVWWyi6tZKE/VV7mQCIhV0POlZWa0nVu2QmSnfw1VNb4CNmnAOrxpXOqvZlfqa4eIPQMVVWxmvKyEda0lVgor2rWh5DvCD1a701n5A5rXamuJ1bKa3nIUNr2db+qscsENa6HVqGlgzXOmupNYFURa1horHLBrWthtama6WVhar/CWlqtbNeES5hwaUKlXhXOi3jBTjqW1wTSepwK2v7VbijdPkOuOXMcHwlVtb/k/NpWtrT0qY44NtdsEbW1wTQOudq2sVKFra/j7PDOLPqy2vPDvfBP21i20nT0646q5ona1210DIaeCm2t1tcna6WLQdrph9W2lVtbDNDW17+tLbWDd41+o/TilqB8J87WBXDr5yVja+mKtr+zVT2vNtdvGMe1/te3ccd2uVtdNPlmpTJOZ7XNdhVtfm6mxU3trrbSu2vYrCl5Uu19aqGpWC/CS/X/a9SFCjOdaHn2tLtfYgQanOr+WuwtITltfCLFW1+Vok2al2t9tcQ640cCAu67Xd2v1all/ih17dAaHXETjhSnLa8yHELAaHXCFwfp3xjgc8UjrNfrf06OUvNxVR1wUkM7WAdP9te3+H+12trBtQSssGvxuRZ8nFUN0CQp44gPxk4sonRANf2xoOsSHAw64e1x9rSHWcspftaw64SglCkvbXhOtodccCOWnLytdiEu2u0giLTuJ1qmrkQCLTw0deXa2p1vdslDdMOuPtY12oZ1zTrtlcUHMgwiLTte1qmrbWnWOuvtfrwPp17y+KHWN2ts2JxZNJ1ytrPOwcOvudZs6/EQTwi8nWCEkpx10U1lzRjrAHW0E4Wdf/VGx1130HBdwuvubFra0pTQArQXWxOtMdcC675167O47WBGApdYM695gWtrDQo32uudZfa8HnTXYMccf/hjquc6y210QJbnWjOs+de+YJV1szrxXXNzboVLK6x51lnuOeymuv7Vc7BHHoe9r1nWdc4ddedcIx11DrXRRs4iDJx467JwQLrq7F52VsdewiSInTTisHWD2vShxqOFq101rNZgBrWtnPLa0P4llL5qc+YB37neuNG1oZrDyAVusO2O26310BsGW3WxJg7dY6a2zlh5AWXnFbGSbB26zMQA7rN3We7jeuGma0V0Gsw13XgLCFRgq6Cd1nzAt3Xnuv5tYrq4vIKurXRXzUvCJYgyR8I/XLjcAaGsN6pYI8MVrRYUPWznKRrOGK35CVPLVY7lY51Zc84RDFnIdgAMh6veTvby075izkdaGcn3IxYdQPqtH3LbkJMYuwvOICoHl8nr70XZsBv8UDy0T12nrVqoSmT5pd4nkz1yRQlqQR0PzFbuSzel8t4VuWeev11ch6yPHHiJKUb/iuTvQvi6j1r1LhD8+0sVJJh6yae8FgFPWEes3pe8WjXlipJOSsrKvbYSbyzkOxWDDeXJhZ1xbC5VCFvvLT2z2ev920J2HCB7vLJPWo+269ZHywL1nPLHBVMesPtxBuEb12ihj0XoeuI9ZGvjnyOWLbvWb0vgFIti04Oy8VSlWJqrs9Y22IQV55A8jXLeuRpeHCMQV4AgdsdcMuFnAl670UKnrpp9Ltzs9chdpoVlOUfvWkhBfxUkq3gVy5LPdRcMuNNwd6wfNH3rYfXeSu29e/y9dLfXrJGp8+uStefy3JO7PrA6w4mSLdfta0xoUgyXI7w2uE3NOqra1uprKTWplBt9YKaxywb152CljWtBtaW644oD5eIvbSct8BG6QH2jEzLqbXLutTKAn67eJ4MrBIAZ+soaRH66XV4NrhkAh+si9v1a4P1/vrAzW7WsxtdI0I9WmT1CbXV+sH9cmax618qrXrWd+tZCcta4eoU/rUbWRqttFdSy0W1kHrmWX+Ah2Ql5eOW16A1zMWTIuXJJC6yck2yuX/WenGiOF/68AN96LZcEglDcdZDjVyAR6LKdRinDgDa8rXhGKAb7Csf+vzJsF3ggN8PzGA3HKWe/CgG480iiAQ7XLUC+gGwG1HVStMEA3UBtXpDYJqKcSgb32XqBvJxaAG1QNnQIrGLM44oDah8AgNvYIsCZGOtYUBcuFANrgbcbw6Bv7VavSMgJahO7A2qaszGD4CYINvStO4J+Bt+OFi6+INkAbYwQkdVl2HLa6vDDUr7aQx9IsQDUG7JFCjOaGQhYlWdZO9JjFhtIgZJSE6P70gG+2kbYGQg3/+sp+AC9vB11RkUA3kRmADfg6wX+xwb72knYxEdcjoH7l/CLduJB46RVC2KG4NmgboqdrdCwejcGyESTZA5bX71y/Z0sG/5NIdrLKA5CsmDYRcrANmrraiAoBtA2CQG7p1j3h//WBT700hy65vStIb5A3vYAdtdNVsjFnqLNzDGOtti0ri9RkDSzoqdLggx+IKG2AN3Tre44RgAFDdfhLxYWtrf/WwhsojHva2N0ZgblPUyTIhdaSiU/HJ7whQ3DBudDZGG6wNjTrU5B6BsjiCsG4oNqAb1qY7BsqhtAjQsN7/rtA2WOC6DdWG5iSQeOW7WvshbDd8G7p1gFEUhXAGBBDcY61kN1Yb4Q2YC6sBpIGzYNrROUw3eBsJDZRGuUNuIbO4IEBs8lqmluW13Oh7eX0GDcWlgTgbvF7YnNXrGC95iiTuYN5gbCSRAu1MDZmG8m2ZwboI2OBvdAF+G111kvYmRcyOB3DZQ6w4NlEb0tAvITWDagG0SORAEIHXmBtBXWeG6YfdEb6DAoKrDdb0y6ZgHEbgSNVDxEddKaqUNnHQRcXIhts8zli+gwLQbgnW4Bv/9duOpO8iob4g864ukjbcaox1pc+d+XGGAGDcGGysNlEbpg25uvjDfQYJiNgrr0w2JBvoMDmG7jYcUb3kBuhuCjd0G49Fs4AwI3hut4DdSG90ANobyQ3xJikDe6ABjpe9OsI2JBtajZz6uSN+UbzMXLRvcjY6GxYNs4Apo2dRs2jc1G02xHpc2I2suDVC2u2NYNt0bow38Rv0DfwYJMNyEbFo2qHy6oUm6y5CCGL+DA2Rs8jdYGu9FqiQAfxkhskZqkAM314/rcGAb7T7DCgK3coClTakQWXjz9ZqKyyoHMbJHA8xtQrAN4vsMYQ8f3WvWveQCJCVmNuFQRY2pLCV83zGzM1vUoZY3cxs5YCEYK2Nn7reeAXSuv9ZNS0D15armWX1aj9ayKy99uGFOOanMbGVpdHG2nHccbPvBHqiSxPgLthcTjJ/hQWaxEJzYQXHawnrc2WyDNrlaWrDulvW4f9plGQwdZGy3S8KNIRxXp57q51Y+P8I7cbGSZdxsldeC8Qz1zcbwt5/v35pZXG9ONxeA4G4kevzjdfG4+BWcbF/9q0t7jYeQmqVlnES6WZxtklfE7WON0/T7aWqqnQZZxU1ocZtLteyxxv0HmCaDcV9h5gBW9xvekAmrG3RmvLaE2SkpElex1J2XdWzSEU+8viFPAmyW8AWEF99WCWepx/+LzaYxrJN710utx0nMPuloCbJE2pIJ9ESb3crFocbmmA1SuDNghzgt0d8bJp6ZG1fF1bjlDaR9LYE2vxv7mAEK7y4SFMccdeJuzjdoTE6lmSbapXupALjcfG6xN/yI8lX6JvdbHMK8kIL8bM2c2KuQC1PS8eNitTpp9eJ0ITaVEH2aYybJGWnxOIMCEaxxVxcbCQJ4CtYZZAmzIV0Qa042rIETjdl6q5VuybzJWQ27yTbbimRHY/LAmW9xuUZpgqy2ZcyrME2DxsctRLi+rUSxELBW5cmBTcMm2RNuSbrZWQfGFpMiXZ5NxS8vIll4suTfVqKWEojL1bFC0sFJ2TijZNgybnyRYJsWTZXhKmNvbrr1BGU7OFb9a//oe9g3fXdutpteqmw1NjKrlhRjICBtc362P14woYqAmi3OteRoJME5/rJrWW+tPuEzeL61ggwY02SmtH9aqm1B4Dqbh/XtCgNTfda02N17rodRFQCjNYIMA1NyXLy03fXBzTcamwNN3abS027Wu9jY6K/2N4trn/WzUXn1YnesfF3tFVToIesDFZumx3VvnrqeWhujCeRuawlYpQr0Kg0iQ49bZ6xminFkhPXw8tzt1ka6F2E4rvqK7KvjlZnqyV3FygK9WyQSe5YN7rOCG4ruPW64shd2abOj1+YrF02OytPruemwDjDGbcPXhesPTdrKzYClVr+M2ySvjpixm9ekSskJp6r5CANaG6PuwsvLCvX3ou1Nz+m9L166bbLcgZunzEsayV3Y4a7uXzuWVxYN7tsbZtLRtgkZsoQhRm08192LDM3sZtklYYPjuAcWb8pSCZvdg1ny8jN6irhM2B4t8zfMa8bfPXrMs3BU00TY28rDNi1YYM24F3GxfmbnBEnFrI+XAZumVc16xfF+lo6dwxYsq9YVm9ACAwcn5W0REyzePQ1OltrIYs2hciSPkgm30EGhroM356vszafq8TNxjL8fWGZvSBI7qxy1S/LRs33wR1pYjFnfls2b+6X21i8zftm2KaM89nJWrZsOzeXixsoOQrcc2C+vEFcjmw/zHPrKs29ZuLld96+3lzmb/jXk+vaFdVm941jbdhc2QQDUVaj6x9NiWbMhXM5sUFfRm8RV+8AroAZZvWJWPSwnNy2bW1s1ZtyJkhy9AgO+LYmXe+tAUFM2D015prflhEqtTTZ761v121oE82smtTzdZHm017Jrw020xtAUDMSIVV5ebW83lmtzze6m5uQXeb402CKAR0D9ehv16XLXrWV5t7zb4CMHja+bF3WCxu3kH8VoZ5LabJ83F5vrTemm81NjdoshBV5vLzafm3fN4abx02Ncvv9Yyy+wAGOOemA6n1zp3AiHeOnXO4C26OCCDZ7wJ1sqmrT5xrgXlpygW9pClOOyC2SCWoLYVfsSgMBb/OwYYDaDbQW8SgDBbyWA9AyZJ28IFghEhb4wq1YPZgD1TQanZBbcC3IFv9diR2FQtiBbaydpZAskPoW6NmGhbPeAQ+kwLdIW8Zi8uOvC2Jaw+J2QW2oYQhbW1Z5IisLfQLLF1rOImSpZM7ILbkiM44IyYtTnpZuKLZTTOwt3mFwkASFu45Z6tiot6lkW8WzMhdxj0WxQkSDxCi2vcAaLaEW3cMf6uii3E0DKLYoW+SwaRbQOzGk5ELaQW/gtyHrVi2+8q4LaMW5QhAuOri3+Fs3nQ8G3ItwkQd2cfFv/QswThwt4j8Oi22FtCLa0WwEtopSB/8VFu3qbUW11AJHM2XXgltSLaMW37vbuOGS2DAB4LbqiKoN3JbCi2lkYmbhUW3iEvJbAmQUFufJwQW9AtjBbLZ1+PKeLdOkL4wOpbVPsssS0LcoW5UtsZE96d/FstLf89i6uWhbiC3bK6VLbSW+Qt73gxC3hlvmOHDgCotwZbYC2huhtvOqW2MtpBbcy2Glv6LYDAu6l2GAxi3SE7CLauub0tpRbl8cilu9LaIRYMnA5blS3xFvKJ22W5xgXpbIy3YltdhWEgLMt038Ky2elsbLcYWxEtxZbQy3OZs9ZQGW7UtjZbRy2bluDLbqW0K+XjNKi3bAVTxw2W7Sa6pbkyEb8oArYgWxEtxfYxyFKpufzdiIDcaJpx1/BIYRUbEpUE042lAxlBA0D3zebGwvgZFbCFBxZny3Dn4ASt0ig9rpiVu4rZWm/it2AwKK2iVuBoA42Bitwlb46scVvrzZmm7EQaFQupSsVtH/xJW4yt0/gOrUKVusrcRW+PwDlbKK24t70rc3wKStrKAYq3tpvU2BFWwhQaVbokQ5Vt8rdBfiyt0frxQA1mtv9dui2dN0BbOHgUIu0RctwltV12CpOooIvn9IOq0+pDyL4kWGq7CMCm7PBFy1batWaYQeRZwi8JFjiQobc7ItpRY/jhxIDSLTEWn75AoENW3fSHPI3q3QIt+rYSLd5gfVbLEXhGABWiUSz6t06rL/BaosbID4iwswASLDRFCXKyZ0TW6JFtCLgFwDqsOraki+FFj1b2a3gIv2RYsrvp4ONbRCTcmB+rcjW0xFxCL9q3JmgsQC0iyPuctbJUWCosK7nLW5VFmUpwUXi1sHwhhgsRFv1bpVzJksmPFii8IwMbW2WxEoucRbQ8ErzSCLua21avqc3hSy5ydtb5q2c1sSWGpAFtV+dbvkW3YkyAGXW+P4uZLha2rVvBoQCS81F4YACK2F+t5DCFfKtFv59gxhhmC9RcOi01No9bKngT1u8pcE2Nh4Coik0XrmAyre10Gh4GtAm0WC6t+eDvWxZ/cOrF82x5sqeCfW/et9jYJgwgNu/rZ7GxqtxarWq2P+ugLcjUNAtsSLkL68It6AgZCjoEW4qWWc4NvaQtQiy5w7AUeEWR7NSRew28mcXDbUoipIsCRVVBERtsGiKkXd41QMCQ2wXxMiLD4GxSA0bbt/DRFnh+2cW7YYhLYQ2wuzSiL0AIVmwsDeMTDrnf5Qay3bVtUd2o23DeFDbpG3G46ibeNWwRt0lAMccMNtSRYqQHxtmjbF7JgItMFB9uLJtlCEmG346hobfI2/BtrTbqgIzIuZvHy3ghtpXURUWJ1W2Dj5omzjfjblTBA9FsMVx5hRnMCGmm2PamNSB025pthCekgJyNvDDgnW/frTTING2ElGinERkGiiMCL5R56krFJeSAmgnTwwIi2zksnCoNTsdeWJ5mMF7Gg0bca4FfhRGQYW2aNugaS82xLBCTbfP442CB00M0Fxt4jbq63tNtybYLW89w5zbs2MctsCaRj8Glt53t4iWzYExbdbtkjsGRLdm2aNvw3mccPRhPuZNG3DBa1rergh1tlaGIW2y4LNbYhPKwEWrbOG3WNiebfES5Ztlzb8m3Stv3wEPWw/NrBANQQRL6nRemiypE4Dbf62Yiv1NcW21GrK9bMxANqbbbZfWx/Nm9bCUhTwKfrYUyKtt8Dbh235tu4yFugmtthTIN22Ltv7zfVW7wl9ZrXwhgFsPRaFmUQNmpb6C3SLHZCnYW28tlOO6WghbQ3LYTbZ3N3GxddavlvfbayPbWhaZb0C2Y45muOfeFbgdpbji3dTB92c8W/8tgEgQ4HRlteLapq0Pp2+If22utgcF18cfi+V5b60hmltE7afhLCtqj27qXcdsdNSSWyItgHbC+06mRlLfkWwDtkf2WUhmdshLdZ24G8FpQdO2dltmuLVrZTt0vq1O2+drIYBJ22juX7O5O2QmW0LfB2kwAOHbYMBrOaeLcoWyYoCnY+y3/ts3uMx22jt2pbAZhHinHLcOOn2geRLBvFLgK0LaaWyR1gMwoQ7GltmLYN2wJUnXAtC2aAsNpfV2y88TxbMu2udvdsXsW+9UdJ2XO3IaiyLcoOpV4T3boMocluwypWuH7thXbqy2PBA652IrQz6m5byS2fE4mKGJ28DtlnbDu2mdsHLe120Dt3nbnGAREugfXgW5ItwArOGrUCnx7ZCWxntrPAPsIYdvoLb3MEC9c5bnHZmlvb1tQlYrtxxbaih/dua7dL2yUDPPbEO3cFsfts+2/9txA5jxSK9vY7dsrhtSgYbre2qav97aCWzgtofbq7wIhs94BBW/Il1V4MBce8APMJKy13t56BZS3/tIpjeHm7Sl/UrOZhSXCrZNRWy9hwngW+39hhcrYFW2qtjebIUB99tMrZrIKigM/bZK2OKWvrcmMCpK/bpzBAL9vQUCv21lAOlbt+2gtD5UoP2/yt8VbOoAX9vGoGxW+/trlLb+z5VvsWsv24Q/fYYO+2j9tdTZGmybAYA7pFAFVtCbDgO8VQb/bEG3ntvlldOmzBt2OOqcAlLYMxZY7AMV8QYkcXJChC9fjGzhNXA7mM3bRtTTDjizthpQr4awXcTfTZjy6ysZYm/03u8spDFzi+DNk4rdwcJ4vsHb9y3qHcrEV43GevYHZLhFC1xGb8Y2EkjVxa56zQdlegLsXHqgU8ltG1Idsg7uM3NRugFh6XElulVrsax7YuqHZPdJqN2yrrkoiP02JFEOzKBKaWzLHfYvYHdlmSBADzdJW9tDsHzRbi3IlQBrBB3uYvAUCYCBQd+PmoMW/xGz5fDWIwNvuLhfWDDs2NsfyzXNpvLKQwpYtBVZT69gdnm+ITWM+vt5b1DgbFuPreBWYw5lxYbm4nlqcO4h23DvRDfUO9IdyMMu1sDDsWioJayJsgw7EKnj0saEU7m4Id/2LOlWUGtRHaLi+Uuy/LdwdPUFLFcHm1wVwI768Xa+v1HaMdS6uSo7ljWPDuADdKO8fF8QYpFCqGsdzeRi/Ydmw7Imy5tt4ra/QB4MHVs802IShphBASws1x7bJ+35mDTHawS7MdiEoAlaZjvtNcFW0dtwyAdwdE72elahWBitwhLgB21LDbHfmU/TltEo+x3Opv/rfnm8yAK326xNDpvWWHGO6Ql/Ir0B35jtbHdWO/QltMrHLAHjvvHbza1WNt47A/Xnih/HcmOy/1yDbJ023tvbNaE8Cayeur9ZX4xt72BhK5YHbo7sJ308t6DVTy5R4aTZvdWmJSJHb1EKBGg8rDB3rg3u5bpsJ7lo6OhJWGesz1YBjmbBI4rL8seDsQl1Dy/4hcPLTMcxyoIzezgJEd0Cqy+WO5DzFYhOyBStmLyJ3bRtPb0+K/CdzPLqJ2Ojz/FZNxBfF1E7yPI3psk8ARO2ulCErz18GGuUeHTSI9lucA7h2ZE4Ild+egPFwU7KJWkt0j5chKMhmAhr9TUWDtjDNxK/qdwk7RzcqCs2Au1O7ydmU7cgqoxuWnbVKz1TUkAmo3ETvONaenZid6U7OR3Axsqne8m4QLKQrGp24Cu55sXy07HAPqN+WqjumndMq8FnO/LvpRrCQ8tfDOzad68IQ+XRZBVHZZOz3NjSr8Y3bTvMtfgaxydz4rrdR5GsQncssTIVqSrqZ24zsCFeHCLEd7x0IAo4+vaFbJO05eSSrlZ328rjlEYyzuCUU7oZ3GKsunajG9QGycwG8XaKswndJilXluHqGZ3mzuZxZTO7DgbZA9BWEzvtHajHp3lgdYQ83qoAjzehywBt+Zgo8UfSsd9eHO6pwxqblK3L1CUeFXO21Nz47+q7mhPrHeP22yt+ZgEnr8O39TbwYMedoabB52hVtbHfPO001uqbVJQbztrnY2O1dtoZgu52o2tolEXO/GV6/rL3WNzuvnfD9ef1647H5335tzHcPO1sd387e028GBgXbuO4nVwBbldWwTvCJb/iDigjGbk+wfouj4BeTM2VqcbqF3V8sfjaBi6hdpqkb03KOygreYINTGgNLLTqKYuj4CG0uB14mLCF2Bt6uzcJQX1lhC72EltYvpOLxiwhdlCq0M3ojXMpwQuyicKFr56IRE4IXdsanvVgi7GC259uvSldS5+N/i7ol2ryujjbAW8wQNC7reW8JvCXZzGg/V9P16y3ZLt4XbLyyfI0RbRF3KuFHFZQmwot5ggFF22qh9peou5sVnrLJSqOC6sXbiZO7l8y7wl3Y1AjbDMu/BN2y7LvpqKuaWJ4yxJd4+kGl2nZvuXblm9xNtBO/F3pUKoleVi1xd6GSjE3iJtOXYXmTy1jtCO6WGLu1ilIa1Fdzi7PeARPBqxZTnWRdnvANF3cJtBXbSu15GbBrvl2nLubpUHS2MkW2rJl3dDh0zbFmwhdpK7Ik3HLsxXdYo9YBqSbo+AVuZv5cim3zF3C7qLZv8vvbGzi5hdyFMe+W04udXdkq/VMNuLLV2KZtLFPDi/VdnS7xU25EvkXafWQJVt/aqV2/xUIVdEDNPF4q7sjXJNh0Ze8u2qVhGxGpW1rtzxb93hFVtfbo82rjteEDQTG+dzfAFcQ9ztrzcvO5sd0/AR13Z5vACBUEBcdjbb852r+CWbD6m801mK7F53njsgXYgSDYwY+bmcRnrs3XfXO9TYChI7fXXrunXfeu5cdg+b3eA7rt/nY+O1ddmmIQF3r1vPnfH4EDd/47H+Aobtz9aOmyCdjZrGB2QFuxxwn4LK1yQoeWXhLv4tf1y4Td8mY2LXhit1+Cqy+TMCCasxWlzi0xfJmF+ofyahgCWsvkzER9f4USbLRN38ljfNd4svRd7NOhGXWessXZgEKXgFerS3Jorv7kEhazcV+YQDaW8bsitbpu93FvG7ErWLWxU3Zla4rd5oY1aWFbtcZaUtnsljW7RzWDt2c0Bku2i13W7o/tVLvE3bLy8sWGBbj9BHmttZC8u9lANm7VPgyru23c1owHFtj0su2ybtfpcaoEgcvy7pzX3bu7bu1uyrdzW74a6DAAjHapW9AIAPSLmW7zvkzAtLPddtIr9TXI7u+/u3O6fgRgembWfjuPXdPwJm8VEtU/XmbDZpyfVujd4C7V5207sGpisyyDd9O7yd2vztJleYEF4PXO7wAgw7tg3YeuwdduvASd34btZ3Zru9DdlO79d2K7t2qQTux/gRu7QJ2AFuY3dgu9BtnG70k27hLnBKvK9Cd9Uov/qaNh1ldtS6U2QaJSPWzyvTjb6hP2SA8ry2XzlCdnCHqzuVscbMrY1qDjlbTS4IdD7+8aWV+KCTeLaFZ4w+7R42nLr5QOp63vd10Bkz1A8tMna3u6+qNRC7N3V7sj3anu52VjbL8KhhbtFZfrK8Pdx+mU93YKs3jdfu6BNkU7v92tdj/3azUF2V2e74D32rgf3Y7kN7U12LEaFpZv8GFdoLpd26OlE3noU1oG3Gw+V2Xb/BgnlZiNb8q76lz+7o93JKvS7Okm5HsY6C0fgg+v8GB0POYdl9DYU2SiCutW/S4/RUkAwd3fXBKFlgbXv1ndw7D31RPnXY+u/nd11w3D2UbtBYBqCE0+/67T53RjuGGAl0bA2zO7lhQpHs7et9KwDdxVwcj2frvuFGUe2I9i67iN2+cAiPY4ex31ie7GC1e7saPYke6Ukfu962b/zvMGEhWqY94ar4j2Q7ueJBMe0I9zOodj2DHvQHZgu4D1uC7g43mCDz/qKy06dTtOkFUHDtttltS2zII+28eWmYstpyi4FQd3SKvqXP8DWKJIu6TwJdLn+BfxyB5aRi6E9r/AStxYMMjZeYIDe7U8bGMWW04cldUPHWhpJ7ZYRFRjUeFDS3Nljx7VwrH0uF9ZvrtrM6Q7iLAgYuFPc8e1eV7x7C+dJNjPQJ1i+xNjx7Dq8F0vTkhwe2zIcPNr9WJYuFPYwsEYdvOdbBXBnvSqr1O6ON4Yun+BMbiNXfDaHnlo44ZJqvTvnxeSe74SutLFYJO5sLPdWe2xllIgHGXpnuKggFK+aWyJ7EdrOjvvUD+Np2XKJ7ZNJprsq6Lie8C1MbDpp9R4vJPa/FdYV9Ya+GWOnvpHfteMDV+p7nT2gqujxdYe7WEMgdBx2VdBn4Htjo+dwx7Nj3XqDAvdeUl3doLAaV2kAagvb4e5dd4YQw6Q7+0yPf+oBk92ZqUF3FHuSJHRe41pivId53CnvLCfUewi9zR7PNBrUx39s4e8MIAF7td2Y7up3eGEGS9747+L3IXsMvcOO1MIel79j2/wgTGepeyWVg1L/d3XHuD3Yei74QecevPX2YswpzxKHL1u4YtqWxXvu9cBi12VvEo6vW6svgxbTjkJ4AwyJF3GFBLpaE8F7g5rLaaX+vCk9cDy9k9wV7M+mmLvWBjOy+MdnY8Wr310u1rF3SgjN3l5or2AAg19YhCMtlh5Y4PWkeshPcFe8A4YV7CWw/xtSvd1u4HFohO3r3AJu6xaVe4+fJDLulw6QBBvb1zJS1x2LEOcdXtW9eNvt098N7PtpkrvfWiDSxGUWficV3A3uCvflcZFdjN7A0cCBFElZigLa9+aynPWbYv4Zade071mWLWE2y3u63bhFhs9gaOAig96tBBugy7m97PrvMXnsv+vbrSyPcjUrKeAXfQl9Y/GOq94N7Ns2xza21cFe4RfQd7m8XbC4xvcj66MVX1L/Xh6/aMZbOe+G9w17eU2+3uFvazexgVld74b3vqTFnfni6W9u17nPWu4szvYRAOW94dI8lWq3vrXdri5u9+t70c384ubvbzew7Fzt7/AA/ntqJAVJcDd/F7vpRpXLnzbruxDd16g773HhPLHfkSFT4P97+53iXtGPeKwOV4B0j3RbTzv/UHA+8j9TF71j3LdAwfZqc6cd3NYymagPu8PfBuzAd1TAE6x3R0UvfqSC+9rl7XVXaXv1JEA+2f1mG7WH38Put3bLu/U1n5gMDF7+tZtbawNh9197qB2yyt9jbce6At3iA9GskLut1awEME7Zsr3H37+C8ffjyyfVnj788V8LtPFawEOn5De7KxWOPvAuRg61Rd6WIsDW6v57FeEu7dPMGb3VZBbsKbb3dfGlzYrCV252Qn8HHK7DFjj7tJtBLvifZ3qykRIT7OF2zPuXTZKdBzFnj7WXMRJt4XeEu660uWbOMixbvNwWTm/TmMN7HH2JSaDvdRfb9nbz7V9NQruZXZWnlHNvvLaJWVPt95UXK0p+v278RFy5vRfbc+2zWbxrFx7UrtnORFmwuW22LRn3zPsN5ba+V7d+g2D9XvEmdzaM+6oxyq7vsWOPsqqQkmyeSoOLdn2mGsN2wy+wJ9+z73+X21wWXcXTmyoJN7IcE88sBfcU+3/GATL3n3roHYNdCZLp9gF0yc3K+ZgFc6+8td1G9q8WOPsa6Ria7V9ia726cKkp5TaV1tLdper6jkMCtLfb4u+vV0t2QVW1CtFfZFm5JsEa7Vn2+rskhMMW4d9glrXfxBvvGfbUa019iL75X3IMsMlafezDYVtOpLa+cvPECe++tpT97NL327tvfaXmxHd6/goWwfvssvaYIP7SZ1tUH3T8DA/f/m2C9upw26dd5N4vde++D96O73L2iPu6CB9ldfNrO7LrQfa0KPfg+4DdgJNQ1WQbvo/dx+1R9pH7iQgUfv2PeJ+/99gj7nrWy6toHdY+/y9qsrTbliHsX1fkm3czOe7XxWZ7vM/bfu/6gSB767tO2JzFYKm2wSeB7yxXNxviNB3uxcVm8b9VTBIrgdaPG1QRD2ykv2zsvO2Uvu+PVsX7FOyJ4SC/aDS/tyIQNdWWniuvHF+ehz9t4rH92qtYM/ZGK9JN9n7ZJXc8urjZN+wulqoegk2DftT3flTFdlkGENSdZnuGAXmezgSZe72jWHftXKuIq+d96cbFv22MvkFZ9++QCHn7sTXzfuO/eXe2oV7X7KL0/Ds6lenG/kSTB7ATW1fvi/esKym+fDL9P3wHvVoy7e6n95xrhTZdrsznfX21FVnJ5ubX8XsF/dLu4D921wLrRNMv/vcsKNaFCv7wH2MPsvHZ3cP7SfTLoP3XXCN/fDu6X9wwwrf2VHsDTc7+0S9uv7n12M3BiLLb++jUcv7Q/287uIvf/0NX9+NrZH2kai34Sn+23d797UHhJ/vsveB6Da1uD7aq2XHslXdp+8Il4KwrbB08vIXdbK5LYwvLv42D/vM2teK5+NsUwvKFICtJp2WyxGQQLEG93+PFpxzksZExSi766WS3HTBu0+yNl8dxVUlTxtJHy+Ljk44diL/3dxtE7ZmyxuNoNLbTikTAVPZfGzv9tmeYl26nsY7eTyy63P8b8AOqSsUTcf+8l/GU75l2447IA5Jm0v5eAuh/2ZTsqXbwB0otEi7PQsgk5P/ey2PL1sWbO/3eeBm9ckm/rdnf7qf6nfuoFKITkxYwqBVDX2rudl3wBwS13MSnqcuAfOTfkq6wD2rLDk3C0scWKoJuNdzgHKmhkCsLXbAB8ymT2E232SMtv/dIKytd09L2APo5synwoTqoD+QHFU29rtznfruxf9lqDx13/qAh2PgOPC9vv7/D2LjBphACK5X9owHDD76ivz/cw+xcYIVQYRXmms7/ZOSRT9m/rSP3XAfnLlcTi4DjDZVgPa/tfvYcB0MYWwHhgO2sDGA7yK/YD+v7SsQQgeUff2MJYDiorhP29AfVeP8B/R96IHDnN3Aeq5d5e5v96urVZXtkl8nYLFK2VvMwhK9tsu2paKB3CdoDoXZXRonvxrem/Vlo7LGHRsTuIxbmy3DEiJME2XOsssCaoK8Nls7LTESClQUndAEF8XRSJq/Mrxsc3bQsCdQAFIjQOg0sfjqkgvHlz12pWWS0j5A/Wy+9luYHe/2dsupmAnVDRN/WE+GW8gePZY2Bzg9vMwZ3xX6tJQlmBxBlcw7MDrRnsJ0ZfLHK1jFERlAssvru2k7H3FiyhR2WlgfONb9LMDAG4HRKRl8uWXyoe+cDyyMEOXzKvfA/MO9hMIOWD33YzAynKXOy4D0EHZ13Igf9/dewMZCW0rD/WWzCwsbhB+h9wIHUQPXsBpjHZbai983A6IPPzvt/deoMPq1qzyH2WzDYg4R+4R9vQH/8SwQf4vYhBxkDqKr5IPSc1mPdzMLCDukHVj3IftYGFpB+y9tkHTj2MPsb/c1ywON0BbwYBabRkladRncVoPKDMX4RXSlZFB6b93nyUxW7vmgxYguHc1/kH+CGSLu9UdKS/yDz1kCD2Xu7IxfjmFZu/dLfFBfmv8g8EiOy13UH8oBVivT8092uqD8Fr/IP9NhQteVB6MV9cIuh25QfuXBNBwKDnPLUoOnQcVpkFBza9n4rpM8VDuZmDFa/yD90H5FWNs6y7a5+BLq3Q7yXLZ4BOg5E8Xqd1+2YpWIXCTKTYyzidWgAwIO20iOzBaxlXdlWYe9gkRPLHaxewaVzMHPD2p5th7sq3SSDyn79d3+QdH6peu3edssH6Wk1/sgffBe2bMTH0iWnCQdygAbB/mDxIHC/340CFg/+QumD8WYeYPqQdetc7B6kdF+b+sxewexA8u26B9jsHAAQswfwg7lAJOD+R7Tx2uQdZA4ES9qt2OOFkhzg1vpZVWYF13EtkQBL2O6+OK6+y8A3UM79buCbg8u/VIQSo7Yb336w2pzPBzZ1ouIXsBo5u0NuPB1iUH3AHvW8VDHg8zZmoCUlrlWrXwdrg5QI5r7B8HxqdOQMXZ1nrLeDvvLDjB3UsXg4fRjuDl8Ix4OGMut5YKpU/HaA686ZBztHg+cHFLnK8HPXXbjqhXw83QJWQLraXiy0RYQ5aGDhD3Lt4d0AIfoQ/OIKuMVTdW9zCIePg6JK394X7OKEO8aTixdIfFRD5UlIk3gGAGp3P0QkJN6blnXCIfVYTUkIeD88HTYwJd7rg+Qh8Z2M3OBr9iJiEQ8IoNFRQ4DplxkwdvdYfY3apJOQ0/3kJQ53aXu22DoIHGTdVIcpdzvOw8ND5j+YVcQek9HizdnW/SHzXRsiSKQ+0hwZDkKAukOt0PKQ+shxIGkyHj23uQebNcwO5wN2pzgvWBis6BHaU3dN4+LnkPPkGupdkOwQN6tiFM3qDuJ5dQ22Ppeg7FsWxgibIGYO57lhzI0Rqyesz1bGCHP2I17NndvBsxPKgUjFD0obTWb9PsCCpjy6Jkb7c8eWMetyDdvU2tlgKHkg2SofeQ8zy75Drq7ID97euBQ68h8717vLYwQhxUFXfoBv/1gzhiVoC/AA8hZGxKlWRrys2m8sOZEY4Nb1yKHU2oarsGzaah3I0My25vXYofg1aS+zI0kaH8xElZuXDIHi2MECqHY6XuofFQ4QGiJNmHCWUPFocNvfF63INwMcFX3lLVBxfKh1tDivrKDXVofnQ+j8DMN56r9c3S+sJDdmh9u9mTh0Q2xgjYsj0m4tLAaHo0Pi5sRHb5G4mFae1Fc3IodzhTb4jEdlaHFapWrteHeIK9VDvq7hfgEhvt9Bqh/0NhhrOgRcDpencr64FDgUUTAPL8uobf39HqdmObEMW4oclXaaO8KNqq+WjXw5uWNaShyzWUhrRh0aGtjBBaI85VxGHxw32TRsVQzm/I1imHNV2Ejv4w5JhxE18K5X0OrbXPPcu3HJDx1QBQpUft/KGFh8WDjwHpYO0WIA/YYYPt6aWHY/2SXvgqBS1JU1qebSUPBjI1g7MB+P97QISsOu/t/KG1h739lEH0IO4MiY9VCB8+kCVJfYOkfuaDaJMkODntIYsPRwfyw/HB0kEWWH9j3LYcQ/ece4uDtj7sccXij+DWli2SuJeAG62PuxPg46QamthiwknKEYshxapq4Ot/a8kpXw4c652EYH0ow2LQcOe1u6aTRi6NQSkbCzA2kMvReMc8AcP1bW7HEiCVLTDVjnD7GEtuWvhCg8BzhxnDlgAtfEq57VrbJuursH4qeeW44fWojDEm1av1b+Vw2jjLQC7jhutuLWBzB24ezx39h0xPVogTcPEaAbrfrCmoCI1onqaKM6seFS9sIAHuH32W0PBeYlYADPDiOHZzlOP2Dw5aG++t9b0xoAx4drnA3W25VKQglcOI0U7w6Lh2HDqv5scOS0jyQmPhxqO4OHhIdSsgn0EGPButmuHKcOzO5Xw/jh8fD4zOW1WF+QOUNfhx3DyeHC3tj4e1SffhwYEMlLf8O74dAlH7hxfD5Ulqa3jBQYLmPh6wnABH2fzM4dLQVSGz/D4iHJcOuQAAI7OuHxDveVgtYN1svw+vqtgj99bycPj4ezpx3h+XDwHi3fND4fnw/zh2KYQWH3iBhGD+WDI2JFUCjwdpMxTgCogRuw7DssQDSWqISsI5kGJwjhhHfshlptLUDQ8PQjrNAIrVJUtBIE1S2GAWVLdQgDcA6pbYRyhIAllrDoRkC6wjuEBIjzNAsiO6iB6pcch+7Drf7mWXVwfghhYAB8g77L79clS66bFvc/BD/cHpWRDEfXg5PB2zFitW1iO+zgHMD3Ab3DoCH5EPPnpDw8arP+DpSc28O9EdawkZTm2PaLr8QrfEfzTmiNX+DqXOPOxS4cuI5sIBlY8hH4EODmCmI8LONBDgoQrAB4kcuXGK61ToxCHTiOjEd3CX0R5kjmzrEuj525WI/kADQjzroZkOShPAHvCkApDx7j5SOcwfFdEqR6rx8pHMxA7IdhKeqR1j97XQTSOoeANI9rwJpDzu79ohLIdY8CMh/UjkDbOoB2kevnXW25991Zr1P3C2s6I75B9igNcHA1qLRXvRZGdlLnE/JW/BFkeVbhtTifkoNMzMXfYDLHC5mJsj3uHTbtrW4rI+EiyZ0NVzA8ONt2Ujc69kkjiuHogYpixrI9MbrP8I9QeZbohsKIHlzjcjpOdaCOrkcG6ngtQfD05HQkPbLW2cIhixmsI5H8pdm4cXO1LeM3AQD5WyP7kcOI8UgFCjg5HSyO8aRkaEzRRQV2ZH+iOyNB2xz0G9EUN5HGKPt4fmoGuR8ijsFHxaww4Sbw4hDfQN4EgeQI1JDwo/JR3qoSe87yOUDItDZztsBD3FHgHBFkdSfmWR4iXPYbiVtjU5KfL9jMjF3YYLEP3kcUpm2Ry/46Ki+yOaUcbhyRR3p1KHwxSPRJCAThnlIvYr9b8HsA6v0Gb6R9lYSQS//UOm18BAtgGvqkRHmvqBEc/eE+SC5dPbmZyYVEfXqBlSwFwTRHFohZEeUrasYFKkFy6TxZlEerYFUR1kQdRHK5ArUfAncmR1jdj2HV9XJN0evehO50ATKQ/qOBitbgE96g6l7k7jdXAqho9cMAYeVyNHrnQmbsVh23q7rJsT74eXghD6vB9y0fduNHyKsUoeZo8DR72gkW7E5XG6tnZMzS4mjgRrIZVOetsnf7q36j8NHC92eZAo0GDR9WlutHu/kcWvGxdDiM2jt9LID2m0flvd1lFbl0NH07ASZtGjx/q4e1hNHnmxbauBo5JVDh/d2bW4AwfS0A+vCPrdrtHyvWmWAoNbbR8e9qyYEg3P8CwqPIq12dnmQ/5Lnofqn2la3NaM17Xh28CvMQCZQxWdpNHRg2o/vCoAEaz9qH1lx6OeGtRo69Sw9wDhr+JbF0fcWhYa6+j9ub8DXQ0dj4Ssq6JPEert6PadzBncsa1uAJMkIU2Yztxo+fQmGdoyrWaPne1/o90q1mjs9H5S7l0c7BtqVGee79HqGP6YcVeF5K6ejpPrz6P+6v8ZAibgX1k9HYZpY3tX5p1XLKjr2QJ4UcPvLnev4HvG8WH353KAh0Y4OsuBd7NrWfM0PtQg/MB1LIKcu+8bm/sWyB4x+bD0sHW4Atc06w+zawJj/WH4yOggc8yFErCbDi2Q1GOmPtjg7rB3bIdjHpH2p5vMY9Z4tbDmpHszWVMfOw/wIBqRKu7nqOWPtTI5yB8Ilxhg4lCfYdo8cyLttkUc5M4w6AB4RYYe/BeeMYLp5+NtZ+1vek5jhdm9mPQX67HFsx7JnXRgZGIp0vR3spG7owfe5CCPnVg7pZ+G9Vy4uHHZIxTCeY7/nCwVn7iEJBPMflnAncMedEbgSWP/McDw5O8GCLTzHrIpQMRjw6kKJ5jlIagEwSlLfZdZG9GAiuHBpVSsfy7fClPljoeHZmPGusOKXUOAdVi/stGVX4fOY62q8d9NrHHmOtRthEa/h3ZjrUb5WPbuiZFzOAJWYr6L3mlnqQdY+tstaMAPyMWOzgA78GtGJXDjNLk2PRscLw/ObayjkbHXspp4eAqoKxz1jprlJWOI4egdGvFPtj2OHLWPJmq1Y7Xh3vK1rrjWP1scG8UXnhVjgqOew3qxt3Y8B4oljs4AyWO1Yusab4G29jjLHMCPlZZoJzOALljhOHUUHT3iTY4eOksV/+VIOONscMdZmx79nEbHy+AEEdQii3i3NjhrWj8PlsBFI50B/YVpH7gDAeUt8I+4R+lIWgMLl1WEdaY7KQHmII/FXUA8cc6gFJxzPKRhHimPrxAfKAVRxklXL9GqXzUdapctR9IjrZgNqPrHt047CAIoj88cDMQXUfapZYMEJgD1Hfd2vUcD3ZMx5llzPAizsHUtSVo2+7VqYV7suPhLvy4/DRwa+i27nKSvUtn/Hlu9OjgNjQ9WTEjLfZVO/mlzUjSuOpHXc3b5buxnaAgy7CjXtm4/0u1GPUFryBJ5Pu4WpLR/VRVK71J3qYua48m+6HEc1FXJ3VcfCXbLOwrj1CVI8cLcf2YilZDLFzK7fuOuJuY1ldu6GjnAQIk2MyXG4+t3ScDzC5HV3gXvgID1OzkccqAMl3rg2RpZ95TQVoPHkoc84uMFaDx3z4dBra3Lk8cG45GvpaSQi7iJ3wMeV4+Nx9/K0hraZrmvvq4+8m/02ErLFuPCm3EVdS5vpd5XHaz3VU30LdAx73tDeLFO2q8fbKKAx9mGVa706Psw7TXaIQvrjm+kApWZ8dy45V9iHj8fHdX3C5ORvbWAx7jrPHplWFnQnfa3x5BlrvHxuPwxJJvdbx4vjx2DVlXG8fx44+BLUdsUWzV3P8DkXxom+GTDr7G6PSiDqtY6vGwVqXHaVJr3uF489x6ujpIKgBWpcde46ji33j33HKFdi3sXhi1xx0y7aEyGWJ8eOFyMOGxl8Ibi+PtXLhHYXx8bjs/HCYOJ8eGnaTexvjkfHUrpt8d948ox6s4OjHTvJuwcj4CIJ+v17MHrSPHvt/ybo+yDdyvm5BOAgeSY9RB33EZHZFYPXvthFQUx/bDpTHSN32CeiY9PwDwTiTHiP2vvt0E44J8AIagngmP2wdI3eEJ03dk67YhO7YdyI6h+1ITm67Wd3FCcGY9Fx0Zj71H0yPY46c13Le4z91srXzA/En9FefS7QJ4V7ev3ea4IrGjR9nCwtLXzByryqvZWKz8nL02GxW00uCsHTR4Hl5T7PycjMQpQ7cJ3Y0PhcV42dPvc50LegjNuwnQLBBGh71YTyzinACEOhPOfsbZcJzpETg3LfScyHFAY53PdBl/Qnv6OQSt9pZ+TgYT5tLFrgEa7GE64mzl99HOBsrvJuN5dnSwkT2Z7xJX0c6KTJCm9SV9HOQXdxsu31cdzox3bPHvFlKMsRE91u2b995O7aOsSsfZ30J/2jjt7HHpSc65E+2u3vFx3OrRPuAd7xYIJ6nQUzYu/XdHsy+GIJx99wQnEhO+cCzE/oJ6kD9xozlyaCfqQ6YJ+4T5JGux3SwhfMDFweIToIH2xPY/Mr9Y0WGYkFYnnGPNYeTJ3CqZMdv+YUxORCfE4+doOsT6QnwWX7ifw3ceJybQZ4nShO3MtfE9UJ+v9xcHzkOh7tEp0ku5WlhOmdScAcg1Q5tS8+liEnGM23Uu81yLlsFDheyVhPV8J4eazS3NllhoeRlU0vrpZYaAmbWi7CaWEa5/9pquweqs7LUthf3bQzbDS2SnRChPF3s0u65wCu96l5bLuKcQSd0nDqe4yTjy7oJPL6sxCkwLLyaadL7E3WSdyzczuKkAPpO01CyQQIPY+JGSnGxtieP30uzpdxopcAwOjlh3gSdsk4oy0ulvkn612wMv85zhM4pN1AbnJOASvkVa1Jyw0fVaf2X2KHDpYxJ3xD8SrDlWWGjVeDN65zwac7I4BZzuY470B2SwHEHhmWjkIMY6iq46T9l7NtgNidqo/4aH/21gnhmXfSecg4Nh1xjzknXmmmwcaLADJ6YDoMnVxPPSeyY+DoO6TwMnjBPDYewpz+ktbDv+YLpO5CcfE4PoImFD0n2ZOEycLE6e2+oT8XHwPWgScVlCPq/GlzLAS6X1vCQjTJK4lgINLVZO6GsgPxUPHQXNTZiJPX0w4F3W8JkREgHKykQs6R7GQm4LWUDOfzZFPuYSt+a+38Cgofs3bibGg9HJ4VPFerarm/M7FtC4OvxNyl0JccCIgizZzcHc10cnQuAH6urTyrzqWTvCr3VZ8f65x2SujfVx/du43dydyzZiYjuTlcnS0O0UZ6JdHJwrY1/HMFJ2yeGPoyhynEIVro5OP3GkNbLbH5nZ/CCWJgKDufkuzjRkWZ7BMjSksnZ0oa3vlsVrJ2cGydy5KnhJdnasnHb2/brRFxbJ95N7N2p5OigPaVYRAJBV9bwDU4QpvjVnwy+t4Z5QplXcKccVxlbK2eOVrvSQQs7PQv1myeT0DOrlRjdb3vYQp8uTxj0ejXoKfUtffJ6cHUhrUDBBICMU74VbFN7N0HiWT5gEU/3S1+T1fbuf39ruLE6N0EVyDH7uj3WuY5+XmJ6SD8SnbuhJKdyw6QMP0nV9KclOSwcKU5QWK5UEH7LgPdvAYKUOJ1sTvSnMP2wydaU81cq6T6j7qlOpKe6U6UpwZTpMnllOCfuXzBspxmTygnsZh7Kcek/mnFZT9SHTkPsbs65cRCSeV+NLKxXAAmKVaBYzHlqalHdWFRVzgFp676oNhrZgpHQdj+NLYiQDkBR+vWyeIIPee+MT19PwQ5O8NLGg5V1T5Vo4rjmkKetN8a0+3odi0HXIStyuflaXJwSEpSCe9XKxLqZwquf5T2qHQrxaesoVIfqxauQEbYVO5ZvbDRVB+1TtUrYBw8et8/lC+79ulVrppKuvtr1T6p5W+ZObWaGTiu9hOtMdg1jp4eiWawnTlaji7fliXr/VP85uy9SFazlTqin94oiWtchNUnBvFlwSxPXygIDzcZ6jC1mMJ+5W7r7LU6ap2UcOWbc1OvevNU7VK3imP3LZ1O0vujU/160dTuaH1N5UgATE6Y0NeYTyn1ChfqfKU8zJ1MoAGnzsOiIlHsMjJ4mTrjHXTKdKeVg+VCUATdWHUZOFYdohLpcrwT4hQpuN3vsUE5ZB6G0MGnf1Ol1Ag07zJ/JTqTHONOHKd40/jMCTTzgnl6hiaeg0+DQq7DhcHYuO+XsS49AWw2CMvdwr3issNlcWVqzTwm7w+RgwFrZYtueeVuzUUvXzU2+pY3XbyNHHrLWXmadArVaBxuVsLImNtA8t9A4Aq1NqAFrnQO5ys6CLFXHfdtNL5BRpMnCHfFp3JUA2x0wP+yswlwrS5VljbL5BRzS3NlZWB6bTgO0feWtfiTlcNp20Tl27hFW7ackzfNuwBVjmnztOX6Wu0+mNSOjlgQSD2b1017UOA1QDm9diuntxsa+I/S8zTs2n212b1YNladp9HN2uJOmdLaea3bey57TrjVik3z8Se06m5dfjnigw6W/advNeUzQ5VoOnUmsz4s2k/ai2JTo4neBR4caxk+5pxXTgQnhNOtifl06Na9YD+KrRe8a/vIg8hp1cT8goX81IPsuA47p261l77imPLdA9088VmAJbun92oW6eXE6Rp9lUXdeo/2DKjUkEL+96T1TANm6bWupk4Gq7PTuf7mxOkyeL07Hp/i9zen09PDMcFtY0J4zTrQnE6ROJv65fHuw2kEVUUJ3bUvn0+FLhTdhe7JdQGQLondjRyXUKkY1v52btzZYbSP2JZYraaWG0junFou5Sdr4uPUWjJs5NhGy4kN8QezuXv6eV8zvG2/ToNLDaQQDqhE6fp8fTvibI/s6nuIM5/G/6tv8b19P3Jtqnfwy5gz2cbPaONsvn071Fm9NqjySD386jWTZAa3elkuon9PPlpOpZ/pzhNjtHnaWG0iNN2Hi/aSRhn/kRNJvMsfSJ7Az4SbAs2qAeoM8lm1rjIJO/DO60tKnYhztwzp8bbdH2JuwM4Ym9l9yCrTDPqJu69aQq4AzxKbxp3PU4NpDttkm9p+CS6W6GdlTc+zKeln+nd8BB3uiM4oTgYzpCbdM2nZsl1F/p2ZdtB7acd1GeHfJzy6+V2xnpCGyJusM/oB7gzglryMIhGfylywZ1IqAhnO3AlxuXcH3R04zh+K/k38Me+pY/py93aa7Zv4cGfN04wm+RjmBnZfpUpvxM+0Zytu29U96OYmdG5uehwWdkuocDPm5vaTbyWC0gxSbybL4C7CM6Wp1Q98RnrE3/TsbPekZxwzjlqDlX5GcGfPpK4FN6obqU2pzvmVdMZxhNtpn8z2Imd2iaaZ6M9shn/k26me0M/8Z/ZNqpnajPvGeyTbMh6EMb6nWj2j6W1TeTqHMz8ynngPaYcmA+he5nUXCjdgP16fBk/UZ+cuIjefGPM6iOZPmZ/3T8gwhzPUafCPdOZzXTjSnRxOGovRqSgu7QYRZnBNOrmdbE5uZ4jlZen/1AVmevM5Ta8cznhIGzP2XsvM6OZ1oj+mn34XiycPRc8hxFGwNbdEXPIcVKHIi5xF5GHvO4lEtCRd8x0iF6bb0FswIsnhVEcFpt4iD4W34OAJ0WM265FvCLSoVeKIZrYsrsXRUhQCUXnJjWRZ6YgN6T2ilLOfqIpDuJZ0hFlNIirwEIv4s4+IlG3N1b95hEYB4Rfe5DivQSLpmAwIs8s5RZymt7lnct7CIscRdii1pt6U1ELPLcKybZ8XhPyM5LtUYzIvIs9XW9lF9DbvDSMWdY9NDgASzl5+W63S1vDAG1Z4hqTiEdYEwKUzM7TEHVSQVLnSOdQBOYTj46Mj+encYhR6e8pctZ2mIB1ngf8S6saw50EC/RTxWbdAYGBSpZZx5IjtnHpPgFUtC484J9eIQlivHNsOvqpbNR4QQVnHbrA3Ud7UBFx/8ToFnPIPlweLxzgFM2VihpIWdI4hH/asY06lhRAO9qkeuAxzoLqzeq/7GYVC0t6DCdy+jFubLGawKMJ1oc5YKeTjSBpBWKsJnZexQGPa+NLMcsvi4WwAtLNDNutnoGcZ9tjA6mqFWz1d4rJ3S2e+pZCGAgD1p6G2Wx2d7/YzZ7nHLNnVJWISCVk7nZ6BN14tmbPrun0FaVMJ2lg1YqbizLsrs5LjhhMI/LNF7h0vAuyPyzs0ZirW7PSCv5zTwp/6MMwrI87MKemBADy37+9dLnbOEkOXA6Qq5a7FQrt7O6ydDs+PS6d6PCnOZ4JCsC8TMTv+zmU78+tUJvRFBp1KxD9In77ON8uwnHoBzsjnEw+D31Wyjs+A588D7uIOmc5VjSBHIq5ck6Iu9B44vQ1xaim9CkFSE013BoksPYxxxvto477g4KctTzcJSKPqCGn+ZOmCf+YHmIpszy+Y2W3mOffM8kSC2z/dNmIO3dDsaoBZ/ITrAwnHO7tOnE5QWLxzpZnegOVraKsBIJwCdpjntlPgycSc4ly18z+47lHOEgd2s7l0Kxz9l78nO+Od704B69kDkFn2zXjb7CbkfS5cjUubWfMYSsSPxjy/cDsznOPBIqflteqKr3VvsUtVPHDsNA6K5BVTu6+RBoiP217ORi/lfPXpOoPfrMMzawsNWdzCgfnPCKAFjRpO8SCPlrIXPkhTWg8+QUjNz7gUwPzGdxU4M558Vz5aNnOkucyneM53jN0zn/+XahMMzay5+tdjZazMXl4sd7nPx094EjrtnOkZb3vf19JjFtznVuxGqBhXZC5xnyQinCl2QucbHp5azLrJvLFEP4zvsvwtizuDj4HsZpYZtr4CzO4kLY5LIXP6UCPZdl/vNT3rnx6X6OIMtc656/jw75KoOvl3lneAoIwhLznAXPJzsVeAi55K1+s7+1ONqfec+JO4uuv0HwOWOztnnpgpyFz/atg72eTRlc/252ad/rna3OCySjne656XN9bn7LX2udMAFNZ1m0b1AICm7meQMEf3iAp9SnEsPNKcwUC+50EJxunWbR5Wig84YJ/Rzw2HIXOLbx+k+ssBXjpHNfdOKaeUBER50GV5ebrVjIeet0+h51DTi0jSPPcPvA840MLJzzWHHuhakBMg+XmyDz8nnWzOSed488hB5WD2nnhxPuQc+o7lYLB160YRHXBJPvRd9YB/jRjrby1hBv6k7SmoJ17x0andOee6238hB21yuIj0X+efuzx55xzzlnnINJkhuT4jwzuWcR+mhHX1vVHymZi6ST8KMtQ3CVKg0El5zz5XrqkHXZecsNFZ59x1oXnKNBOedIAdV53wac3nKRBx5xydewjWp3PXnWk5suv65uiDJzz1dgW9xDeeO89t5+VEHobPJ4bec22GtnuyN42rIYJOefJJRQIrW13nnIA3464d/1N52jPDrAnPOGXQRdYyPrwGSXnbQt/Q5LtfVFO3lljLhkRyOt65lghGnz5STWDF2efC869QMaFOUbUfPE+eo9Lq2CXzlGgkvOhF3wXlr5xINrFb9Ltghv+8+b54/GEMwMvPvecdTE0Mt3zgPnJ+7djiR88Ek5LziC4V+Km+ca87H5w2IYfnPfOWOwZ84n55zz/+IF8gJ+eS8572r2yhfn36BPN0gjet583zvIcBYgOhus2whi8PnEGkc3XGeY0NfrsE947XnkT9XQAfc9hVh6RrsbdesLvBE+VO61KI1IgQNOGhjP84+6wuqPgIM5cTtkObbf5y5Tlso9DxIglPtc2WI4MT/nDY3J+AAC6xp2JYX/nkQT/+eCoDgF491x/ngLPCycM0705/BdkOwCAOUGRt46lsPUSeurYJPYbD4C65O6WljBblucv4w1A59S6CtqWwPr9VXs0k9hsDYU5IoVF2bbCFcR9y9GlsgXKPcUofsC5ZsNitkW7FJOWbAbOGEO/QL92wPiK6stUC44F2148NHpAuWbBwyoIF5fVogXM5lkWvzEA6+3gLxQXfeX21IKLawFxgDxsoB8cFBeF5eD5qtd1QXheWNcnv45tsNQ0jt7YGWyBcXdIvZ88LDq7Tud/LizU/gy1YL0hyY72UMvOC6ZrAk1qBU1AvkXX0FYMFxl9xlg1hxO8viIcWu/HXJd5672W3DS3fdsPvyFs7gQuLLsiC5EK9mGEa7WgvFJtuC5kF52i7/LTguZBeiC/yvoBliQXIplX8eI0Bvi2Rz8u7Uthr7y3E6FsNivPHLmNPawd1OFKFwHRtZnW0xVx1sc5R5/XERlgfPhnAcR3baFwH+P4nNQvqbBdC7py8Jzg4A/Qvmhf8c9aFxGVPjnzNg6hdUc+p5xPTxoXQ4qXifW2EqFypz9jn2Ng0MuSc4aF2sL6YXzH396evbc0J49Fkzm03oOkc5scxiyZzZjykpWmxi+Jb05mcLpHruTVFkcRbtEcIYA/w+dwvn4Z8Q8lBN3l+jm+ul8TubJYHZphCnrLubF28uLeBd8jUDsaY/KO5ExZYzEF3zVlwWaNAlivE6MZR+YnYA4jkBJxsRQWeF7tpc4XEziVQf48z6/ONlnHQziW6Bb8BGli5OCvUHv3hDe5sxfBDNlTh3Q7rY38s4i4i5xSLjVJMIv0Rd1xbv5tcLpEXcVOmRe8s7nG4MlxZHSxSuUH5pYv1PsLla7+g87n16YGeF9BbR/LnrxLhcdZ2608hNmdK2yP6FqCi42mmMli/mzIuJH1Xcn5F+RYAd4krXLEtwCzpF4ZViUXAouQpuKSbli2yLwUXgTPIRe0i55F8eji2LFIurahv5avzQslm3msgYs/upJeeFwg4yM4KBWWasts1RF3H1+0Xpwv2RcDrFxF76Lk0XhphWhS384fViAc8P1mxtrLDNyyXp4dfVTnvStPK2kQq/W/GL5NrkYvRhdTeDt9SUJnXGUYubI1D04/IGMjnHnJPPLvA3ec91Dt4WzLwvr9bhpi/LKOSaKgztn5tUdli/nc/mL2unMPOHvDxtgkDamLxwYpELk2sY8paF7ALrXSmYuiDjao87F2aJ/GElYuWyh9i7hEwOL7mQLYuAssER22Fzpz5NnLkPjKDLAjIO/v9/LL/0OVxdTjZKwJDksg7+4KNstvYBGnfhdqAHBqTrBP3jYmBxKlDe7HF3SstMw9Se8xdroHMTz6aSHjbvF/MRPJ7pNZ10vcpcGFNuVh/7JmB6qSQA+Wy8xoaQ7Pe06nv/i43FxyT31JG0YF0thXa3FyEq0Cbjl32sBp5Ic+52l/N5S8WjLtOpbpSa4cZCbAk2rxdpHEaO7Ua5irSEvUnt4+HYm968+CXRE3IKuo/J1zHFd1AHamA+hPazaol4B8oisr+OmJtYS+K2MelquWmwPZ1DvPdyu0uL9P1ks3MJffi/EOyhLwoHH2Te4t0A7Dp/hL7fHbKhUJtoS5wlz5NoSXLhiaJszKDOB+eLwc7UU2R1Dii1xh8wDrCXnqJeXgBTaUl3cQUGLSU21xfbi7O+65VsCXDh21JteVf3F/EaA57hksjsuVyxOe/pNzYHHUPWjvSA6XSwik58E5U23Jfbf3we3Z6pyX2Eud4vDXcLS+JLls72U3gpdRxckl/0DpygJEv2/0OVdR+c+1dgHgU23sAVwiwxyrtuyXNQZzSblLtUl8JLh8nHAPmJc/i8a+7FLjiXNh2IpelZaKl86d0KXWVrdDuBS4ay9lLsKrb2isJc0S60B15LgtIB9hPJf5Zd2LhkEAUrvkvOy7ES9k+qoVrDLYUuspsBQ1DF1uLwIL5QuEQfCeCWO1DzpsXwZPZsD/xbWZ0uLoVCYnOgedqYCESfDzyjoErdHjvj0/YR+bgTaX7XGTKe5mD2l8tLo4nR6glpfjS/NwC4wwF7PYuQQdl+kVMm8zi6Xk0v3ieAC6Jy7dLqaXqxPczCvS8Z5wCTnyn2zXJ9suUtPpyGjjIakJP0Gc0Ncf26eFW+nXdXZLspkRqB7GjhcEdfT+sTQM4Ea/NmcBnE9WgueEw+AZycVxK7rfUKTu5o57wMLyAtHqaPYV05Q4pmNvV7lsLl2Co791YkfmyT5BnvaOqZc4zZ/u3DL5TEb+XXGfkNZRGhDDmhnoMugZcP1eWwso1rmXXE3/yuMy+hl2OlrqqmDXXlggw61O9vViLdAMOT5qoy44/AhVmWXd9W0Zd9Q7lvaTL2vQbJPQ/jYVeBW/9LxRnBFW4Zee6I8Z0H1vWX4Mvo/CZHcFlxDDwJn2k3GZcl2rym62dxurUsvfyclnZ4a94tTqHyTOR6tipmZh67Lxur6xYpoeOy6bywgtoEyLZ2CzvArdQlXkz2fLf0u2Se2Ddpl2rLjqnnjOvZcGXGvJ8MrNerqR7X8f/o7jl72OnlrJ0xyGvuy+Yp4kLXBrzsuJqe5y7vy9pd6WX2yiQMdiy/Qp0uj4+LUMuIYdjM7tly6yGOXE1VQxdwy+Q3T9z7NrsvVAafPS+rkPW8XTHfO0O5cwC+csIld//N3HOLZAniuJ5xPTlRbtndh6eVg8Hl33L3oXobQKEjkzuR5y619uXY8udpfKyF7lwsL5WQK8vnKf9y9l6BvL74n2bX95c9C7pp2gL3TnvIOtCeUeGT8EhdnlArZXiPAMRKKyzfL0V7qQpHpvoWFle4L5REnkSoZ3u9FD/q3Wh0RnSr3Hp3bld2zP/LoNwbM3Hu3q52I8CVMFKH76OlXtAyYyh1NUbV7WcUFyeifHVe2U0VcnYsiZ3vJJUum5aBDbLl8usvuVpcfl3HHXBXx5O28W7jaIV1uTr28OD2yFckzf5wDgr5+Xyl2aFfwF2I8ITgkgHW2ogk7EeEc5EohqgHxHgm3yzo62mPQDu+XDX2R4scVYEV2HN9GUoz3iPDj2mPx4KBP17VqoRqdajibeyYrAuX/bxa3uKK9D60haid7sivxvvPZS/l/U5fOb5QZhFcbMLBm6c9kjLm53VvtBVebIqK9mgu1c2Or2lvdQV/dD7RXfr3MFcww4nShO9pxXxFXTRMwK+4BEtD+RXnZdKPDakjmhwnE1XAI0u0PBFu0rpyErnuRdHOZpdXE/CVz/Nt97ku7Z5fus7Xl/UkE/1ysO33spK9Xl1wTmNY6SvbzsWJGyV5Erp5nSZPVo7G5qXl/IkAQIk82ZhdJK66SPErzeX9SQylfk09HF8EsapXB8uGPtNK+Pl4EDpnnewvyQsEo8BVb3DrpX3yPo8vfZZHUEqXDT4vSvVrAbI6TTs3DulJgqOnqTMcxBSzyj/oEaWPvXlzI752qXDpZX6KOJdEFw9jecsjuIB2cOplfMo9dAQJZUxL6xRu4cHCVkzkMr9OcY8PeldjhW+Rz0rjgb3KWcUeYEm3h++L/pXa3Mh4eAfJJRxXDgZXQ+3QXDXWE+V9Yd75XlQ9w7o47EmV7Gl1cYX2wnldmeiRRz3tKrM8iXIVc+4HJx0p8b5LoKubCDSQrDhKYllyEYqPblcAq6ZnPCrrFX6OPRKe6A6B50Jx//qZ63CeDEq5A4pp91Tn5KvP2KUq+goKdLgOrtKvrpdcpdulwfJIZHJsBf6msq8bFwUrrjH9KvnZKMq7JVyyrtsyXKvAeclICGdRpsXEAymwtNh0QDKAL0ARrAIgAxVc4WJseBYAalXZnEeGAq7BVV++MAQlrSXnZKRIUD+NqrkDiaquV9gvhelQAqriVXKAApVfP4BlVyIAOVX7AAFVcjOuABTqrqxJLmwHVcGq7Wys6rwVXqqu3VelbF5V66rsoyRqv/usvbfQF+fL7fL27ccZvePfzyz9RYGXnr2aGsxT2BlwcM1PLe/J1Ls0xaUK6svVEnK9AY8tpSnNewPlnFW6MvjXt+5eEmLFdvV7M9XR4FyWqzV8jFq6KUhN80s2vfzy3G68mX0BWHcuhq7WyyE9okuTJORXvb5cjV/yTgt7Eauz7HkK5l68D0WjkOeWt7mT5ZzV2zN36+Maup5SdQ8s2FCVr0KnUOxN2z5ZllKZdhvL8b3Qy4Dq4by12r8kuhaujYvd5d/VFZdvvLgb3zi4hXbXVyPluHu+vwl1cqtccPhHLqN7csWL1fcy6JmTWr/PS5Mux1eG5bZXt41n2L86OMm5jXZyF8/lxNXNcvA5yWNdjVzdTnE65auO1eKTZ2exQVn9XQ13p3sO5aYHeLLpSHeBX4JgAw6nixbFv7ykW4R4v6FZHV0n9hd7LavL1cPvfvV1BNZ4Hvz3ihdetcJoZ8Gu5QSVkP4txi5I16wl7MbOmAKNcrC7bSAWrvqbdyhFVaka/o188MFjXCRXmNcxADo10yr54YvzdWNc5FfI1x22yjX/Gvobtka+3IKmVkTXtGvqNd1jek1xN6ucXgavgWfBq8AYOTCVQbre9JWX8bdBhVfFmfnMHBZNskoG4GyXzmDgsWOFWRJjelJHprhlW0g2+DRGa5U12sB7Xnrmo8M6Kjds14x1rQU7qWAcfW/g7a2+8WyuZwA5+zrDaF59Zrs9i2mv1NdKE08x6pr7XnteYDsfYS9wGzyeXTXTo3wXhzdb6BUjj53jSghDNf7Vbmx9fbYPn4WuTscztzMGwbHEUkW1XuO5LDas16lryu8bun4OuVOr9W4Eod58ZWvGyhZreoCAomHTXEcO44JIji950Zr6ko0cDBRvpIvuq/OUatEKWvT4e+w192g1rrzXSVlmte9a43W09eZIbmWuDqs/UQhG6Nr1jwJmvu+eta/JVOilWbXS2vi9sO85i13qIZbXQWvWtefSaVuL1rg6rpbqIhvba4jh4drq4bRWvY4dhZDO17w+OW4W1XpB5iDd2Lh0dW7XbhJ2htRjuBlKGLgrcmY3UmpvAhEyHxpAzIUojRAidy/ekL9rr/n32ueEf6iZB1wDr3eXNZgIFf7dNAFxdQXbbwOvIBeCClU5zDr8sbI9n4dcmDFkLoN0L7XkOu3YdJs8BJzrlk4bqt3lv00w/yKazTx+XgQ33bsAIqty1RF65rhuP5isjiHZoTE9v+XIw3Tdx6vfDywRkbtLiT3EofE7qsQvk9nnX8vK7cfdZVih10op3HQrxvhu6XD4y8gSBnX1qyTCes6FTy0Tro2nX19G0f4RfduxU4EfLquuVemdzpl6w1FnDLID8KFduDaZFrRd7bOpOveMkFXZPK8YNtugsGWAMyq9c517LTg2jKrXddcFwZ1ixrr3nX7LWSFelDdEWnThrq9xsXAIsCtfV15FDyXXYBOZzQDQ9l11xNyvMLI2w9ePpYt11sNkVr7LwddfWpj8+G+lihXCA2ydfrXYOpCyNtPX212LFeG65Ja3mUQ2XBGQSWtC/N5K3brqd7Diu3BvbQpm+/t2gaHbuu8psYq++G17r0x8pp8c9fWMH/eNu96vXF8WThsitaUh1DDqPXbGWXFf7DYDu49T2PXSrXXOhcFb910nrnIXTfWiNcWw+oyBm6KTn4KgdKg9I+ml9yrknnc+vl9fvS+sYMkSY6XDHORxBHuXWl/WkCBdu9PAdeVpCP12cz7QIZ+vLmciq9311a2aen9aQl9fH66h146oW/XNSujYcr/Sel0/r1NQL+vmlfgqG/120ryTHHSvD6ciJbFTA1jvFX8iWbAU4skTaGaokRL1yYJ3CXK8GV7Abh3gIyuEDcIStFOMgbofb1kcLebAq7eV8WCBbHjyvWUeOtHMx/djjdG2cXCDegG+M1Tnt3A3mWON5ZoI4twPDj+7Hu9x3UvdOvKx1AbhJHhuQQscMG+gNzu0SLHfyuRQrZJbQfHAbiZXOBvSL3DmnQNzrnBq4e2OvlfiG4ARZAmbA3LQ2DND0G/BVwQbqzIo5z3YUwq/Jxyjj+7H9LxO5sKG7/a6ir1ZXlOh7sHwG6H2yobmrHeKvQxfw4BVR2tFulXhLU+VcHbd418RsWw3FKv7Ddkq9l9nYbh9b7/OmNhuG85Vyylpw3QquqVfeG5pVy4b+7rgRumKbCq8yB0mzn1H8WRlhpA49I8FZj/GOExI6kXCRbGCIwzZxwTmPe4erQ718uDjlp1pWOR83+QiSN75jsM0jXXb4eHK7eh/PsR+HFYWzIso0r/a0kiguHb0O8bgI45feHhFo1ONmP5YAHw+UG/OO+7HlYc88uiZD72ZSAMeHzcPMjeWdfux7NOKmrKRvTTRbY5yN2MbhI3iFwBjd1Y7ETvNpBxSa5xZNuWX31zOkb0rHlVULebrG/2q0wzhiJbWOMjebn2C62GJA43ficWICh9VyVHhF5BoxRu2jdpY/UZw0b4+Hf85XQArG9ON/0b2AwGRuusxHG7eN6VjgDMyHW5jctDdmGxMb+7HAfKNSuARcJ/Ktj4UtrG33IsoUhgRTLYAKLd4AtIQ9cQLSwFFsE3F8P7Py+Y6IoGzqv+HCyPZhtJdRxi83t9E3a2UN4LbG/426cXfI3NQN3jfShzq2AUb/iLrRvMCxWY/FmTUbhigXsACTcvXVmKzLekHHFUXocctY9hNxA0PQ35KrWNsABFUN9rdVlHDUXOjd/G5i26Sbs43XxvtADva62ytTj/hH00W5TdcI/CN0mVvcQrZzycdfrbVN/KbonHXOPFsibdbI2KIjpnHUbPuLT+s8t4Faj/UgnOOwXvXiH1N/qiPnH4iO/WdqI+DZy8wBNneOvT5cLi6HuwqwaH6K4vSbvfV0+3VeVn03Ncgdxd804wW4t4YKYNQOZgdORAgNaq9lm79HMHsRS0+iu5D4S/8PuX5aeRm9sbilDlM363ghpXQzY5u56bpVJ2tPDPsCRChdHVliM3l3hdAKupeDN56bzgg5tP5Belm8q1dbT4WLlZuyzfrg7qu7Wb0UH/msqbu+m7bN0ZzdZbY7NuxhD1Z9p6It2M3qNwA6duXfo5h7rEOnDtPIzc6K0Yyw8DkM3gZvU6ffZcjN/zWbybWdP/8cbsz1OFTD0Jkc5uJVTX468Fh1dxM3jvEi6fNXczN3SkDOXcdOQze8uEzWIZVnr7hZuwwesTJQu62bglr3YiFFuPm5kKyVvehbt5uFCsDtvlu+t4EmzjFWeXgZfZPNy1SDArfC5pbulczQOHXrqOn25vyRJV6/7yRZdg83qT2s+YjXZM5o98aWLCcZRvsoW7ZIFHF5830Fukzff5ZBy9Bb1Gwx+PPfjwW+/sLrpo83QSuZ9ft3d+8J/tVuX5kRBC1Tg+x51Er2YXNFvGLevXa3KL6lfJX1+vDYepm64oXsz9i3Ym65wfbS8yVxFEZtCwGnBhe8W7YtxUrkS3tUQKnZCW4ju6xb+S3qnOxIhyW9f135EMfzH+u55cw2A4t1Jb54gOlulLcY3ciN3sLsvnFnFaudfrWRG0ml1NaNxX8opV8/5IW9NzCjzfO6HRZnQTfgcjtDLTWztxs2W7L5yzk98HofxDldeW9YME+DpQsdyPOWCQ5PIh9v8AuHIVvkWRhW+P5J8jjVOAVvcJu/I/DzjkjmCOsyuy+dtIGPxM/OlFHVfOnT2o1dyGq5b1WD1Fpg935W7lCn/pTK3YKOX0svvBomz3lUqA9fOSrcDghct/QN35A9n4jOdbI9qt4Q5i/YDVuO+f82w6RkVbxq3lPVnk7xztSt/HYC0V2DWPxjn88CZ8BD42+fKPR+esOUZ+J1bjXn3i06UfzW5mt+1sHrLDlvJ+dsOi2iL1b3fn0lLAaspW4uN5pcEjwDEP4FVpY+NQBpmYagU1vEOAiU9tJ3n9r1r+pOc7uB1STF/dbnpHHhuT9fEYCily9btlXNKAPrfZ1tet1ablCokLTrP1EhV9Z9Gz003GMhzTd5EEtN7WD4dggNui11VPXtN6Dbx03pwQXTcny52F0GrlNnnEgktPps9tS3odnpFlaWM2dpx1xt7r9wtnhNvlUw8/doDMtlp5rK6M9XtzZeZY1bgWtnaaX8aip1hnK+2z0m3g9YZftNs/VzuzdwWmctPGbdH+x4u6r5GFOj1R2Rb5pfooYTbjB7xNu6nuKAOT8leVmdnqkgxFhGAVU3exN6W3WmIQIfeoLjjh5z/GsCD2c7ls2/2rInjza10GWJsu0PTla6AOjW3RXI8bfc5o4q0Tb4ir3fNOy4JvxG2flfcl0RCcmbe92nwt4FN2j+CGB+vsSr09Th7b7NCRXP5Ksu24l+5ufLDL9tv/nimn1U+nbb+BsMv3sJgkZZHQ+9KIKrVz6hbfQtiGvOHbq23MrYqbJ9xbQ5+LbrG3MhXaj62FxVt+A92J2Gz3hbcZ2+Uze7b5O3KcunbcjS8yt9MTlwHNduvSdsa4eqApahu3pYQcigXE+kt5boGDrk/X9mfy29nARkrzu36TiTid128Hty3bhpXD1QiRy12/xe/Xb/u3WBg27eqY6nt83bzS3iSuZLdQBAnt6Pb5Ggc9uvpf465+l6D1rqAhVj66sB49p67E/D17h9ur1BSJjWyz7jnVwU5lgRfc9dC7COjtOmePX/EJvNYSSOHlmc49uuaqwz1Y1N0rTpwoU1PZfZq09/l6/bisgKtbkRihU97MFLr27ZieW97diqVdS5fbqB3SuuqlaZ5cZJFrrrrMNvXj7eSg5l635cZ3XUFZLGtv2+5u85yqHrHchYMsNLQYa08ya3XcGdZ8u4O/Nm5Hj2nrLJxndcoO7969rovnX4phjYvsQvsFNrNsoVxPWSiCT6/od3j1sB3wevqHcvgv3tyIzvY0XvWnLrotaxdCQ7vh3Db3Baz69a4d1AT7B3T9W4He9vYQJzQ7ilki6OwgSnQ6Ud4pNg5HSDu30c6O7vt4aT07DUhWNPi508BVwQ70cQm6Z8r6V46bl0VsOenD6hfagl/cbt/4oc23jjuEefzTi3p3GLjU3Tf2p5teO8f11pb5ywvjvz9eWwoDqwDzxjHobRvqCr/ZKV4eoFx3M9vwnfuO7Xp9QoGJ3O8v/HdtpAidx471+bwgSt7dum4J19s1iBOAEuRXsMzbl2god8NXPcdF8A7i+bV5IUXo7Cr20ZskoBPF+TF0ubnYuxacAzbXATeLvNX1XOTvBXxdxiycVltJhMWSk7bq+Bc8U99NXyGvhlL2g+QU4nlvJ35Tuu6sTO/rq009nuOcr1mZfevw5m7sdcJ7T6vCnfUBDbN5qMqQrkhRCDtzq+iG5U7uOLJb3LZuvnU6O+bFhp3VKoqif7q7FAciiOonD/BDZstO/Nm+ur6Z3yLWJaIO5YxyO89qw5Dp2e47qSnweyvF153WgnQ4tQa8ei/gr/JVUcW8VCANaTsd02r9XXBWIXdGHdOe0CDqi3QPPSeebv3Ol+Dz1cWb0vhLeXqERi1C9sHnGRWNkHou47t6jzxUcKL39mefWPJe/ODxGnlSvSXf7S8GF1S7nfXMPPRAlku+Xm5HiRl3BLvQ2gMu+ZeyfN5l3HLuHDdFFbxd87D9l3WTu0bdny5TZ5/0/K1+uWSneiZr9N99FmhrkrvJndW5bmIGGb6p3ShXQTB9m6rVzHljoZcZu+nee5cG0Hhbrp3fuWzSDEZRSh9k9z/pwVgXxcPau1d1zHKI49Tux4tbECLN8mrxPLtEy6zeMxa7q4674p3l9W4OnA/Fby8ur2V3JM3nxExxd2Lnh6MvLeotAGtzEB+NPeVu9XXAzhzeevBl6zq7w83pH8TDseptPN9zNodXv0WhHRXm/11zG7213ozua3t6xbm9G2bs/M0s3RXdNm4re7PlnkIdrvDnepu6ig73F053NrvRKgZS6Fi93lg13EFu91fGxcG0ERb1vL66vY3cES7mbAvF0itO8XdndyxbqGahboN3Ts2iBm6u7g0Yvltt3CeGM3fHxabd+Rb+N386O6hlc/B+d+CrAuLebvnTuru85i+yaONwaz2wXeVu/ksbQ98HOd+WDjCduKue404a63JdPCVdSY6Rgzo9qebN7vWwdxi/vd87Do7lYJquLdhO+OyJL06PtJLum3e3u9Zdx+75l2QTuf3cPu6cd59oSy+v7v6tD/fwMtzy70D3FsJLHt3u8g90vbil3K9uvZnp32fd2B7qD30F3vpfM86KaekL1n7s7vwODZs4bq0tUg1Zx9WXXcJEiEB5YTh13+Uabiiq/fbyx9kW4Civ29Ysk4UbZ8cV/V3lpEH2cL1ZOK77kDLA0M2/CdLVLYM4ET9V3P1ERCuUe4Li5zRcdnJ9Xymm4e90J8L1hupagvh8sWxbk94XlrOV+HvtyA3s6SJxfFpyprAu0ieqe/icgVdiVNUhWMw0ns7/tKW75j3t3Piie/ReOso9z8onS1S/jbu692+Ex7/VFkV2HPe/RbIFF1zmz37rSRCuIlabyzh7iQrrYdohu+e4wB9kT1z3/oJh2cTcRld25746HUDXiPfye9l6obLpT3r2X+skxxfI95AV9hnpnv82kilcFK1R7/m2mJXImtGe6ry6E1seLUs98bD8NaK90579d7ahXymnRC48aw674T3y+W0vcBe/E94l702XgXuzvvxe7q9wUd737VXuP2fINdU9+XyDOX132lqk1zxSlwyVyz3yN5ezs4NePdwMJzErLJXLGvjhsquFTD2xrS1S+B5ena69wl7tr30zOEXfXu8RglsLgigeShqTKhO5zK/t7qoX04OqtB9rxGF54bgbQsX2Ohf1aGu97E747Id3ucld7e8e92+7o7353vYyfP1Hx5Y8z7i3UNOlk0Kc/pB5976kymmO3rfiKHe9z/rgXpR50EacAG+0R0AbkbHeq3x5YGre8gEmti3Ipq24fcWrZH8CSzr8F6Puq1ueY8IcAiz4VnjDBXVtMRfxvh/HRhgXq2YWcSs9RMfoIMNbYEWenpZrBp9yFryqL4rPfVuqjZLWyT7tWrD2djVtOrdTW5z79zYDLOR45o++m20Y8TzAy2O9VsKRc+MMtj0rITa3/ItajdCi4jIYVn3mvSfLGgC7WwmtprTwxIR1uU++sDNT7mKLvq2yfcxMLOS92twn32LMgos5RdJG2L7xdbRUWsfcLrc5Z+Ft7kBxvvC1KSYE8x1wnfzb262MItU+5oi/utsyLurXjIue+8mx1fRt1bOPu3sfl6aai6gOR33b2Ot1YvJeIZl5F8P3uFLikuFRcmx6GMBKLba2cotI+/TW5Otxn3MUYNfdAoHe189C09bX1u4xC5+9u2yB7iCQKsoi/fnrcT+M+tv63KTvodcV+9O29NFwv3D22x7e0I9r90NF4I3JgwW/dQSJVNzy97e3PqOVkSNvjQZ+MUVsr63qtYEk3ZxtyPmtBnlN2NsvreqCygWzym3LVpMBLFm9pt3NaBqA7N3GbdUiImZv4UeWnffumLRW46394yfFj9243Rbs+28XcLDWZm7tNv0hsPWln94Wl4yb8GyKbvBm779xDSeurKwPh/ftOoDi4dlwm34/u7Ts208Jt6BkY4uZeXDgd9+4reK1DzB1P/uW/gRTZ4sKel1ve2w0/yuQVdMPvbpUhru6VdxuMnw/3usD7/3ffvklCv4+XwEul+0+t58RGe6+Ltt6IGW/3RH6QA8P+6hmznlyycx/u/1KsTdhXaM9+0+lCgKvvOUGeyzf72cbpnOg0vMB7VKzGVJgPhAfJmecc3gLi/7ngPadOHtgDttfp8pm1yrrqaV/caZadS/Mm+0497246fV28PPiLD/6gL3qMacr65+91cT5QPylON7dgi4SV0h7zu3bQsYadR+H0D7TT3QPs9ujA/n6+390ATQ731H3JWu409btwoH+73sZgbA/1K43t/YH5J3y9vO7faB/Ze04HwV384ufUdK1Z0BhchxWr+WqAg+YdlaFITV8mraIuQVGrxbOq1jV0IP0QfuauSlYEFXvMrmrzIQAg+mQYjh0Fz+GrUX7FauY0FHugX4VWrdtWmiOt5aFqykMN7d6wOSg/OQffB+Bqn6LztWfqve5ktq7jV4mrJKwZatW1aaD67KPZLMQebqsay46DwkHjS7xC2Hqs8oxto2XUV6rAELHEf1B87mw8sBHVF6WTauARzZq9MHmoPZpWjiTZB8tq2vgDbkQwem4v+B46t+kH2OHwQetg/tB4dO60H6fHBQfDg/3vf8PuEHgWroPVxau9B7gy1cH3AjF1uB/3dxcAjp+Y+ObmyXZg+h9tOD7UfUMXN/sA6uRhiVR382Cv7pKvLvdliH+DyUJ0lXjgwIEAAh7dZyYH0NoJkgfg872Io8CCHzedWdWQffJ1e2QKCH/P3MltdUeOHa791T97J3O9vP+vWs+pl8rrmmHIgFr5ceQ9JD2tl+XX//Ws/Ufy4xO1ANvRSCMvkFd8jYekhvdoBXBKgl+2gK+gV+yH1JLFJ2uQ/d1BAHFeNtkPA23K1e/y7yh8gJ8mXn8v8Yd1UiJD9gr//r0oeyQ8q65kqdpVkKk5MOaQ+91ZN18yH/2b0evwZnGDYpDyIziPX9IfLO5FE70RZ3rpUPsz328TfDb/Dr+TmPJTUPq3byy8N5LaHjkPplWLQ98jflD6b922lUofX+OATYWHjSVyimR32OdSmh61DzXFrGHJ4wsrOZxekV4aHmGb8c3+ECBh9Sh7NTjxX7Ie4w/969Zh6CHLRXQG98Yehh70VzYrwMPPIfzFfaFe7qMCgEC3LeuqsL2XdwywGHtAbV02vzfl66/67m8ZxXrMO3Q9qNYTD05hSHr0c2Yw8Vh5DOSnL6RXTcvQZA3tsFQD2HnjXTfvK0hbWwHD/WkDdIA4egQ8YqAgQExr2QI+sABNeDh7QYFOHzjXM4enpKsLDjFwhFtYNfYfhw/Ca+L994wMcPYmuGGBbh7Cy2uHvcPbNi+w8nh5PYApr9A7vfumrBzySKywTb8XQOnlsbe5s4JEDuLkm3D4fDQz4XbFt+LoIxEMT3BbcSZ0BdLzbp9nQeg43ec247Z98Ued3oEfb44pDW7Z2mlrHWxWxAFdVs/2JaM79y4ZbO8p5Ou6XOHU9m8P6Eec2ccxYfD6a7hdL6isOK4vh64mzZISdndNNZQefvGHe8JnDc3Zt3KGfFTDG4ocBqDnwEfWncG244rvoZDKXG7PRnvy6CSUTuzpiP383Rncmdg2e1hHrs3otxoi5oR5bi4Bz2+O+M4f2eER6kjzxH62nmFP2I9tc+DSXRnPUqpDXGYGnk6c9koIT9nlZPmI/Oh9kj3YXLeMo1vf+RmJyqJTvFrVMFjOM9AgR/zaTxl/+OoTovZu7s//jvfmI17rEffC4yo27d+qGMDnZkfB3t0dVbKyZILlyCkvbbf/h4Yj4ImAjnJ4wkoT4c/Mq9RHnSXZduuI/kR69O5lqELOxEe1nuXyw7Z8lHtjLeduJM5+BlmK8HbstnTomdJeW29PS8VMZECVz3E7fBR+HNzHbusnzyFHKxBVYjt3JnIyPuGWs7d2F1dlS2dzKPzUe43dge6PZ1pHtr7iUfb46iFV4p6h2aDLmRtakq7m6dt7fHPWtGcuxo//xx5Dg+ToKP00eZnBqNd6j//HWnpBLXUo+3xxWj7nb+Sr8ugFo+NR6wy9xH9N3hUe8KdKR5At2VHpyPI0eE7ckZYSsIwBVO3RUfuo+MZaaj1ZHxC3NXWruQjS/d0FjbBfXKCwKFBNdSsD54Dt6P30ecXdy6BaFP9H1QP77vYzCZG2N6fxb/F74MfwPc7h/P0N8UOQLB0unI8Qx5+j+JzoGPGHu95hfR4w9xOHt3QaMfX9fi6Hsloh7tunE9PcE7mew057jH773ERu8Q8+o5/gBdE5srFOvf7C4ewVD7fL/mVsJOqQ9KvdQUOzL9BXfr3+uxpq+Z2Oq9jwB7OuLXvJXVzV2Arr4uhKQeNa8h5Gy0V7PyzgsfSFeMzBFD0yHkM3ZY2JQ90h5pj9dD6nXPZvF8NMx7/jgb7M1E6wOTQ9Kx+TdJ2r9W3DMel3l71ZS5Iwr2AwspOVQ9Nvatj0AGYvdGePTY9+Q7zi3EydmPjMes/urmUNj7TH3d34xOtvdbE6+WKMmqJ30H2Uq50u+DJwHHzQPm+AfJBEmRRjytL8WPasP/NZvvfbiMYHomPlSuGY9qgh8B4nHiDoocfNYc/wG8DXRbrD7IceKY/l3ajj84H3NYhcer+vKW5Lj6T9quPRcfu/dUx72FyPUVGCHP3B/cwpxTqCHo0f3tDOe2R426VuwQz/hQmncr/fhM9AXtTbs/3MDOo+T0276hN/T7FertvN/cgM7YlBzbnm76ucdAjceRFu8MDqtIObpJbvi06rSPlmV1LMwPG4+Ec3DR/f7lgb3ViO4+4R602zqZ9aHUjO+j6q266hybH0fC4oto9cAB+LoiZrRIPet3oMtPx+Nt6pu+UnbceLbc7u0HjwnUQu3ggeU6imKyoazhbyQE+7Iqizec7Ti2Ansy4DeOSLe2M6njxL9rCwUU2l4+7adkD8gn4VeX+mPevNM9KwNvHzOLBFu94/Hx/wt65Vo+P18eU/DyVa3jxnbhOMWGWq0jBK1ajxxVlBP8dvLOcwM7nj75VlMc2jOdG4O2995vQnhBPCTXZzeNx8nSGO99838CfgRF+29ED8OlhCLejY8E/1M44T2Hb/0X/TOWE8N47kD37HpMnMaEWXfJ1GApPi71TnYCeHDZ/M72CNi7kGPUVW+aLdJt2J0gYIxPaifYY8NGGhiLi9xGPZifNE8WJ+CMHonq6XpieNE8OB498A5kGa990v7EguJ7cD9CHyRI7if9E/vS5PdPNvJxP2nPFNdLg5ch8i0a5H83AO4eRJ4PBxSz77LdrR05xbkAEmlp1gkujiOH2PNw6G6IKj2pesyu5luoQ6rQAfD6FQ34PhV6lw6KTzkjpFUBcO8k8MQ7nCncjrJPk1v/nWUjd7RdSXIje0uwq2v/Z23B3O6hJPP6qDwedJ/ra6b+VCHvSf+2vhPtn+NEn2eOXbXfMZJJ8GT1W1iZP24P4k9adc54hIaHJPFxvEe5CQ9dq1XD6ZP49cEYtkqyutxYbxmYFw1bhAhG6MjQ5xHtk5eJ5w9YIErh4jlE5PX62vDuYJSuT6pzm5PCnE7k/QUGQy5jZJ5P0HuHkAvJ8x0vi5Qng2iK67LfJ+xj15fDeo5U9p1U/J8u6l8nisXlK3mwAEAGQgP+AeJAw8mBYoDi4HIF3CHqAlMehXfum4ei3NEB/g+QOG6sqW/zgi3Vt6LuKfSI6ke47Ny6MYErvP3JvuyRCQmzj16T7LYugzui/c4u/0nT/h09X6LsPeEsAp4Tli7D3gm3y8e+YF2SuL1VtHu+LsPeHHtKET8T7gqfOTs3C5wu6Kn7FP3xXCU9Wc/aJzKnqkrLnvMU8BoHN10eDpVPXg2crv5E8xT36Uc2bE+WyBdDKus9+F9zFPbKe4ruKp85T1Gd7Wbpqft+JeaoU95ELztzfXOLPeYp/VuHkTmvLjqexU8gNbKu4KnvM7kDXSvsPeE3EcdDvC7YC2HvDB6kQ5xYV11PnxXg/tgLd28F4BabngK9RFsdRAuB/o1vVPU5AfgeiBnhdwSr+0nQPOVLeN71jJ1mnsNyr3vY7u7eGzT+D7oYXld4kQcYu76FwOgDEH+zOjU+0DSh9wWL2YXrKf4H5Ty56mJWnunnylvBWASHXzj8pEFjsFIP20+lp6p53pbntPA6f7E+S2H7T6T9jtPvafDLdum+vD5mYbvmFcO2CT4QbWLhzKRyAo0S+KDuJzMaMVjkOW6cRfE4bp8hRwun+8AOidd0/zp7BkUJH/GRwRc8zDg5A+zrGb89PeqhtFvpJ2XT5Cj29PdBdg3tnG9btlDNrYulGoPQCmktEYR+n6I1FcPM+6Lp/SToPtfo3aqvBzjuJ2ChBXDp9PO6fUx6Pp4amnH4aDP56eAM8Hp7eroWKK4JDKJoi6a8peplcEsPbbxcTpmbw6b42JEXxON45RHBoZ+ANERn/c+08OkM9CR8YTLNNf8J1bpfE5H9rhR0+n8DPqGeu5jNhIQzzq2AJQOGeIk4wZ4rh6I7LzYsSdUM/y2aSOL4nTLEOuAjyM/p+CTm77L9P34myYBvFxEUFpCHjVeksiM/j3wXh/xnnvYKmfgbABKHQz+RngtLkGejH7OSAYzz1+VUAk5K9IQcZY6zg+n/TP6YNzM8vp/6N9i3OcZv6epKTaZ7Iz04nT9PfGef0AaZ6Az6CrJTPSRxc45gp+8wAUE8HIHbP/M8yZ4UHqQNxROR6e9zB6DQ4rphn8TPxvgdnGCZ5ruNJ4rly7Wc15mcZ72M3/EDjPxWPdXpiRHXT7xnsKV1f9Ns4IaR1bLt4mBPOD3r08lZ46rbXsQ9P+Weqs8kdcUTuhxYQAKkqS9I6Jy7za0QQGtJToti4B6ZYAKVn5GJTcv5TtRkCL8QU0d87jRwyNhI8wKaACnuXQcUcogBEu7HKANnu4As2etE8JWHSAENn5+Y02es0DjZ8rG79H9bPeZhKnMQlF1k2NnpnCW2fxOdBELI2CiYZ+Yp2eNs9HZ6Wz5dn3bPw2exdACaCk2Jtny8PNP2gDcadGw3NWb1CXjylvTelA++z7zToCXduxA3fM3b/F0hEDzQs2WJgcqRI3u8MDtRQ02JkzcjZecCaK6XoH8OeXwZmu/ciruNgJQbOMEZvi08nJZrYUInu8euKXYR4WB6VljWGP2e/xv0Nqld6ZKP4Hf2eF0toB7UUN95BB7AAe6c9YW4L8CQHmHPHUf20mnpaP2ctmAiPZEun30Pi4i3UhVxA5Q+ptZu057w6Om7ylDEwObXjlu45z5sDknPXE3Wc9y59Yh1QDnHPdrvTgfQZc9syJLt+dz2Xyc82HY3N0EnHXPoGvMjtxmCSjDlH2xCeEvWlUFR+/Nw1lsj6EUfM7ccVaZzwFLzHkEOeTuGtS7uy5LnkxEGUvzt2c57Fz73FpC3QUupc9VS7NzxDnAnPLcWXUl7i8Vz1HFvXPxOexwgFHa3Nxp0IdQs0fYpc/cfrdxx+s4HS+5pAQUW6OyxhMZnPmmaqc+8PlaOzy1RKXFufZnu70UKB4DngyXh4pbI8G55Sj43L5RPwZPbfGkBqDj2ED9wculuR0/N54AA8B7snLeWNO89nJ+KwJ+Sr934IOZdxYx5RD9jgIfP5gf+8/Zx+Jj+WErsHXafggcd59cT0Tl7vPeMeG89we7/dyCDpfPxaeNOjNIX/1/mTwA3GAvdEeBI/fB7CVINax4PZm4vRb3sK57PcHNiOEav1UXN54KmKJPSHcT8+xI5xi4/nu/PN4PyIf/OpeQKEjhiHyCVKWRfg5yR3O6hDg/+etYS3upgYAl1q1sP+eMhRIwAfB9knklJoNBjwewo5vz5yY9iHFiPTwcX55DBGkjoiHF1ubkrUMEIh0DA7Avt+f2usYQ/6NMDGriQhEPAqF5w4kGe5iaLr2SOQC9UF6FBKGL7pHE0axWmmQ9YuNQluJuveerId1I7/OxwXxpHAyOeC+G7E4L/0j/1azBfeC9dI+4L8yvDgvk2f2kdPb0EL3wXkQvnzqWC+oC7RTzk73e3nfOcZvEHaQ+c7Hog7AxXbLXaF6em8zFpT5ZImagdFQ47eeFD1nroVOyvT3/dftx6M0BXNPWJilfoj9m6lDinrCcZS1eZQ9p64VQBWPIGw/etoJlPVxIdyB36hfSodd1YswBBoDQv7ru9C81Q/tJJrLiIvcs2dZvE9c0yZOrjZehheEi8Fy+UDtEN06X8UPsvtDU8iamtT+aHePXLbdRfdxUp7lxfJ/UttZvG9f2taWH9WbNvXfC9LQ4tmx4X5STPl2NoeZFOuh27NxfLXPyCofwtZMO1z8isEPWWToc5Jy0LwjDtkywNWBi99Xc3JsUXwIvaz2FBxJg7rzyTzt7A8uaCeeRfIu9yPnpjQTuBWMer9frmpPnyl31GwT00ku+2LwvnxxQ3Oagnd7F6v16DHttIjmA79eP9awIDvn5i3WxeNi9yE4wUKsX4H3n+uylB3F7WL8QoV4vdafCad75+DV4K99bF96d87HhZEYVyEZrAuJrvAS+EK/GFUXU8uOAJfgtc0fbt/DAXF7l4XRwS+opggLh6mwEv4b2/i+DJ3jGf02pjON/s0YKYl+dDJqMt2Phgs2eeBFtFmYQr246dnQoS9/xhhL7iX7CJVJfoWtU1Zo+xiXqEvMHoaS8Ul7F56iXpQmkaefvFf0dVGXUHD83PJfb3ol2LBLwzHnc0xfBQS/Ba6eSINMbuOgRb+S+Gx9dSNl1zkvumuf4ArAiiTlHYxsoIZuu5jUhXpL3dyGq3/+AAKjPWgbGQhgTUvtetvTLCl8lLytbOHtnydoS9Ga/1L0iIIfnR3LjS92l7xL/SX9WVIZum8aZJwhGf4jF83HpeWS/6wCz6SaX5kvnwyRbmgrZ1R0a45ROWJfOg4ml9A0u0N2Uvh7cTS/bSiKG6SXwkv+peknx+l/4BTAt4Egxdt8S8SqgxRCaXpkM4XxP+m4qk4uxbAAsvEZevufdiJNL6qXnMvupe/LterGJwCa71p4H5uwujj86VL0gt+Tnw5oJS+2l71gAkov0v4tGn44nQANL4WXm0v7ZfqR7czj7L2CXwcvZZe/S+aLh7NwwSSJwYPLNRmRp/nL56X6kv3ZeVy8Tl65L8ikasv9JexAntl4YXcDYrsv+1WSCAxc0I68mX9v4IZu5F50l8XL+38Zcv8eGQS8jl8zL1eXh8vrJfuy+PNMpL0eXoZbAVc2aSXxzbL5mX7v1FvNPy+Rp/zjdeXx8vIZuQK8vl4ZL1+X5LKDZez+m8FjrLxK3R9UfZemy8hm8tKF3zz8vqFepREOl9fL+2X+UuC5ePU0oV/Ut0yE2BOcFeNS/qW7hL40nYrQlZfyK/24kor5j6YGUIZvWY1Cl4RLxdXY3gCjlDy9gV5or5LxXcvgJfglersEiCUDp0HXuax+K+K2L5/N9rybPqQwZQaiV8aGYOnuyE0lexxC46/cD/xEaEbg3gZUMY6+g+yJXqkAalfK48qV+JoApX2SvOIStK/sKEUr+0rrD3xluMIBXg0vp1XLpScWuv+Tsj1Zsr8K9iNH7IB6i6C04xO4yV4niVt2SZd3Fdpkymjy4rJznubv/09WKzQ5b+3gVfnK/pYgJl35XsszTuPUUjeV9MnRWjimXieWLK/QO4hl+8V/g8DaPM8sYQHivgs7gXKgJWTPGC08lO6DLhyvMEuoSveEHWxfzL1XrmVfr7fCy5Va5lXsG0CAekV2jFd1ej0bHWXWxW9jOWO4Vl5qD/yv5s2Gq9BV9dxj696D+7le+q92nYhAzSVpKvFaXPZfOV8srx29oyrPxW0q/unfXR0VXtZ7d0leq8lwevx96d/YrPlfBzsoNYwgJQYK0nhcuWG4zF/Hl94QYLEH3vjq/x3eqF0pX+eXRl0N9cFg54gDdXtfPKYPVSZOtYLB09X/YvW8hXq9Pe/1mB9X/NPFsPr8iV3dnz7Qtk6vtcffq93V4Sd7r0a6vYNf3k9yzFBr87Dv6vqJbMfuJs/rj29n46IUQRmytgk4bMOy/Vmn6NevL3jRhLS3U94vwEtZ8LviC4xr069GJ7NJOMa/DikDyxSTjGvk7y8SfsC/2YOxQvnXxJP1c4T3qPRzVWNNLx0RzFrblfJryjXnsAFT3ia8o17yuHjXrsrgtfIidVpdwj1woeJB6wOZ0uP/emMqujgUnOD2vL2pqNfq2KThmv/rDJSf06M4B5HEVPHcrWNBeEVax9+o74GoFCcca/u9aVJw2VwCcAfW/ydUPa4UPdotC32yAvKtcKFC6v+brwXstfMANV69iF67XzGEvlWMQxLpepyEzmoKrEQuYU6c14rCf+bj2vDNekGaMZZdr+HXoWvCYOBAdy18XR7gFg/73mka+vWk/Mq8HXhvr14QbYAjS4HAICoEQnmVWSKej24krznXljHC0vxGD6Y5jj0cTl69W3TIY/7GEuxw8T5YvfOAq69IfcGFwzX8s4hdeG69hA4ICXnXgarBde3q9YmC7r3jH4uvGmPFOdCF8brwPXzfPZdeaMf2A++Lymz0nHexoA4sxS0mx53+BE3KI0NS95iEq7HWlgpMEWuAElpG6QTxz7rEibkYsE+koFBx6n4B/Hi9fvNfmQv3SzGVSbHiNwHqfmQiy19u9byb7LcNSsA49Vxm9Nxu15mvH68lc5B2J5j5evV9eYpbma4cHXqdxu1uPuahYL15/r4wwaniQ9Wa87hY/cHJ5wkd3EUBf68eSLLy0Shg6v6afyOfdRYiPjxxSEY9twRMhYN6CN3T6zaQoKBq0iqm/wb8dzNOWvARdttkN9nedAL65AJDfNtvUN7DqAmKETI4hUbuU0N+FoPQ3rHHrDfVOI4N9LyGmIMhvCSAq+JREE4b/XdphXh8lJlbMN5kGHsECJWDXnaG+HwBEb0Dzy+XVBpBG+4N7B1wQI8ZSvDeOG+KICTK0o3uzSXceMggUeGkb5FxTRvBGAFG9BA90b2HrFr9562jG/wcwobyZXk6b7qAoU8wp8cALQj/yIJOnpTRqoEXFtgQMxve0BTVfyq/NV5YAaVXbwBZVd7wH8b/WzThuTbNSsJq5MFAwd6RnCr7iQn1OnMsInHOV0DiQFV8LJN5c/bE3/1XMGA/G+2q4Cb8EAIJvOgAQm8s8DCb9hYkZ1DdQnUaLiIN3buIVuoFTfwP6rQ0EnGX6X82Cx96m/Pjkab+nZi4KcK6a2bZN/Ybg2zM1XFqu3CBWq4GgKE33Jv4TfFVfabGqb+Whx7iWpegJYTN7eVZ+xEiTMzfVdeDGQWb1SuWlYUzfmL0jFi6b4VgHJvIABJVeBN8tV8E361Xwzfdm89N4ib7hYvzwmfdam+Hyiqb8IwWVxa09Z4j+fCDG2I4z2+LTfEvaI8Sab6vgzpvxqvRVenN6IAH03/ZvAzfDm9DN+KbyM30pvkTeI1sWnQc4tM344ODg8GmorN9u9ozCOFvz3CZm/Wrf7sVC3jZvr4Atm+rIB2b3s3/JvBzfCm9HN5Bbyc30ZvIzqhPDJ1gpve+l6/2ovLrjBFc8bjVDHCvINLe8BbViDpjgy3ilv9Oi9QTfN+8p73712r9ZnxXc42+moSz9iV7UgeBW+6/dde8CAOM46J3FXuT7D+xaq96tX0rf6oplq8Jt3JMA+7eruvi65z3l5BSd/V7clAW4mH+4Ke8kn3JUwh25W9RLz7OPHlqVvPLfDfvxq74D6CvQ370au/47mt/Aex87n231rfbfuLO7Dp/a3313HtPpW8hmA9b12V4EA9n0SAfBu6Vb2mYEX7bsXbI/HErj+wu7t1vIreOA8RXaDb963xjLDz3pW+0wkHexLSJB75U9r1nYNfHe0G3oMeCTXV3fZt6hc/O9q23UfJT7toa7YD8k3eEUpbfsA/ciEGdn3Fhd7nvhmL1P3YPe87b51voGuA7ctt9bDw5V41vrYJr3tRTaiXvJgAoXEV3q7dHIXhr7o9tnF91etE9jt9cd3IUf51U7eJK/vzwzuz3b+dvfjvLq8SFEJJ0Xdqe3a7fNi/Ie/rbwwElF3UARh2/Lt98T44HmdveMfJ2+Ex/rT6nHjvw47fS/Ant+Br3NVoy3sPu2TvNT1OVBKVLarBtdiOIFq55QG+3j8gPfyc1SaLn+x7Q7qTiO6u8pnft8JZY5AWEBiTw7avh8MUgBRMVAldtWYZzhbAomIQcWOH6n2K+yNt139XbV98Eoth0O+PGDtqwO7RC4SHeOux21dWhqI4WDvCWBCg8kDpg733w1ZHrKwEVKqgGA78T8O2rVmt3Nh/t91TBR3+xxn7e9EuaRyG9S+319ghNXmO/0d/iIkfbJjvdHeDEdqNzaQHbVpq+IuxLuG4d7uDjPB5uAXm8JO/bHfNuHvyRg5mHftvQGI9S+yL8TDv8nfNO/EwjIxJJ3gMigneCI7Isjtq6BQCzkcNkv2+xrCSs3p3zuJUHf+DQKd6E76Z3gAO1GJwO/+kQM7wAHUTv4vIkP6gd687wQ4fe4oHfXO8Kd/E79AXm/2DnexO/N0EeMF8H1jmUatmUu5iBi746znEPoje8wAiX3ZS7mIFLvsXehUshs7wkEjy3jmEqWjTfOo4dN8kwCG3LZAobfL28ER7l3m9maqWnUfDoAFx5VQONn4sAUbemV4fb/vn0BbnoxfkvTUJZq5vZbRLK08FkvUWW6SxZZPrL/XeoUs9T3kNx8oHrvseHqWvLQD4qflF4bWXFPUltMzGV90w5R5LJKAbEt6baqS3cMRxL+rkNu/sULcS8t3jxLIwICcAvJbm77cl7oOaOt0KK9JaWyyN3+kTmiWru8++4WdkN3s7ve63TeCrJYwj8IZMuCqSXgDdlUShS5uU40HOkYfu+VD27i8N3sFLk3fe4AWG5QdeEwycXteBanj7bcXIaPXoOAZRTHWdQ9+/YIj3wP+A4vbUdB0ETaCJfGPdBXfau9Fd6kR4GzsrvSHulqBY96jVlztSNnhXfEbeuo6dNxoj9nHmHue/d7C6nL5bhGZ3BKfSy9kTD5bw+b5xGJhOQnv6l5jRJK3+m70ZRPK9qvb4u+Oode2RMXtbsrW0b4T7l7J7g5fCXJGu5YuzlYXdhureqLs5WFN2ta9gs39HT4q/1q/dL8mnptXOF29YAyERZ7+rdtnvWuvW3uhl65796HkreOvfDe/ah7REZGn3sQnhrtnvIW+dAiX13539vepA7Tc73d4OX3okh7vyM6hl7AHkCWZvXaaebrel06YJzesefXs+fw+/Xt6hrw6kbjY0ffy1gAV1nbx3X3KIvpeu6cKW9T79cX1fXLFvU+8Zx70txn3iuvYfeX1DoE0j79CkCPvS8vJs+RpE0nSPXqFIcffIa/w9+TSPpGKdvUKRE+8+B7CTzOntWXyid0GAfXnqzxVn2BOujBlRKPV2Kz333wGzqQ2UM813GsYIZwpB7vZurcQT99RWR2z4m+zJvy443iArBPJn61YS/eOssjbF0z7NNWfvMOUGM9R9svjtjj/A4GGfAEen6msYPlcUfvFme508ojdjUXhT6aM38d0xCespOLhG97Qb6Yh+RHBZ6MRUMiFEb3ffoi7lBiqzEv3u4YnTcdE7m01oG6/3pwth6emssojZ+lqeTs9Px8ddGCosDwpzAP4fvJMs0EcRZ4gH8v3kbYeWeIi4nDYH74lnzvvhD8wB9vV3Twuv3w7ylI2pM8lxTwH5b8aou+PNjM/ED+RDP5XO/v3CcIxCL4B777Zn4gfEYj3+9sGYoH1yoSsnIWfiB9zGwhzh1nYDPS/fv7ASprWLixPYQfyA/n08n99i63uII/vomfyB8SD8n78f3iHKjSdZhvGO1wHxIP8/vk7O0s9ID/4H0Vno9P1jBuB98J14H5YNvL09A+h+/dx24Z/+HPzPjTMpKSs67uklIPsTPgycMosOD40HyMNugfWWfLB/QU8+yJ4PiQfN/eYs8d94kH3oP2JORA/TB/WD9cz3+ntDI4uyQs4mD4/p2/3mwfBg/1GeVQdEz1bhpfvmPpVoNuD5/p8V23wf7aQPB88Z6wH946JwtmA/YB+nDv/ZDVnrAfpQ+rIDFD777wG70mgS6er+9vQ+SH15nihakg3QhjSYEcz9l15Qb0Q+Oh+d94NjnX4NYuQg/JBsFrThQGIP+/vlQ++C46D8sHy+kDIf+Q+Sh/YOiBQNUPqYfhyz+h8RZ94zyIN1FZP/fCVKJx1Q23nEOguwQudMxXpASOlTnX7w3WfJBtVbGz94dXyl382eSOBUkvUr88UA7PssBNKP2N4vb9u35bPuhBbh9CMAeH60PsxAS2f1s/fD76FEgYN4fJHAnh+/D9LqMCPjeWdw+ALujZ8eHxCPm7PXooSOC+8wBH3vMS7P1jA4BRwj5nm6iPlq4l8x2t7gj7RH1OntFPzPO7+Y+YkhR0sU2QbF/NiR8Vw45anhGNUXq5tSLC9vKjs9sjthDweIBrX0qdRR+PIvvS9I/qR8tsynfiRnqkf5KOy8Agw/hwAyP/YXrHN91yUj428PyP7fZZxu6HRUDbHZjwDoVHVoKgUetWLWVu8j4v6NDWkk43lveR52iG/nlw/kPexqyV9R5gPg4g4uRYFx7FyGqqt6v3plh840JORFtjt4FLv1o+p0Rxi4d0NdhMU4Sxo6xf36yohK6PybPcAtLF7sQoCpG6P6S8gLFeIinF7UsBSLn0fr50f9vI+ADHwVpY7PiLuOs4SzQsuDt4dC+tglqhL1983KEmP0wSEY/cfAgTWTH+aPldv5ZQXhr2HkTH4KcQsfbeesx8tXBzH0WP8sf/ipHR/1zRuzAGibVHtY+Xjoxj6kxzAsDjyro/HBi4VY9H36PjHv3FBV0DLfhdH36Pwrvb4RqkgFIEZTrTjn7wdo+ux+LaDSxiqsWyYoSerw+M96TyHqVfFPKF3Mq+dEdh69x9tcftleoicwLcyrx/8GoH4n3sEi4a2dy4Z9navEHBHCfa3YwgJ+wP+nyn3GEgTq3ZT/RdjCAnKtuU+Xj/33MA7rer0t2lx9vRkeK/TdpcfP3xiU/rLb/H/A76VPW4+2ieOfcYSC+LQCbVv2MFtAT6NuwA1sBboE/ngehp8Qn+RVtTkME+sXpepZJ6rnj7BIoeqqYfe/cYSA2qCxrHV2rx85Y3pKyXFxhI7gYM5eje8YSFwHFOX132+IBffzAJ+o1mCfqKxF0cAFYUW7BP507/v2GJ9B7yrD8hPz5Ik+vxGsUT6gfiBb4Rrd4/cdB167EnxhAaqtjGWdvskT/t18H99CfUkg1FfcT6vH2g8fr7++WlJ/Xj8gy7Y1xhIMk+iJ8WXYwgPeP0hrzv20G8h96vd2H346voWXI+9WT/SdzH32Igtk+m++b4GvyNJ1AvvPFujJ++ZoTj88QDyfdjv7J/j8B8n+u37yfFO4k+/PF9jwC5P3yft13m85917Cnxc+ZNr9IOt8BNvnPbzcX5D3DE+YvSk/fCn4e36H3LXfg1e1Q/IN3Yj5jrQHRN4cS6MLOD+13iycBvshK9w+Hy4Ib1HpCSfbjPwXhx2JVP4YtWBu8hxDw84ZzVjwsIrKPcp91bB0BDCrrqfkZxpIU91Fkzm1PhbHc/O0EeTo6wN7L7chH8vXp3n3Y9fQlvFqqfSBvip+pI8uGEKbmqfWnXI9h3Y4cUmMn4W3kBuKp8JJ+2cZvDpNOjU/lcC7HHdhbknvqErWOEVeFJ42nyYjcnHfKPQxeNUCsN2CH2vAj0/3DdQh5Tj8h716fzhuH1vMcA99t9P96fLw+WFCRAKenxiHr6f/hvSx8nAIZV23779gf0/wZ/KF/nF6oXgkPhqC9yfzj0ih9XKmsngVOxJxbk/kaP/1qG9rZPKuH4w4v7D/L8lMFVOY3o3Ff3WkS1moIijWPOcIuSgGxTuccn2rHjBugPCKp5JTiLn3gR2nXITaSp3TPgmV1VOCZ9QDeRn9jPxqnVAR4yQYz4PJ5PgKCnzfTQofoz63RxuxfmfsnqOA+WLSbl3ZdCJXANflZ+xK8o1+ZddWfB4e2bo6B4+n5eoFLc283KwcGz+Tj4DPjgIDFBbNOw/YYYObP3Wfps/Q2iqvnKV3coTWfJs/kp/6z7C6M/N6vvzEwnZ9JT6z75S7+2fEcfx0huz+dn1czrlvDcfUVt/2O/uwE9s6i5QPryu3p1S9mtlu+n1/AQjq91aoFzfXPpQppwYnv33ZbTmdPd3Lg+VPU7X8HxdHiTzNHXIh1nad5YeMOk9pIQEHor7vrpev4B4W7crmc/i5+jOEEu0/TsOf8wOE59Wj73+z/d4ufVOSFnfYPazn8sCEtnP0tWyu11eoPdHrr8rsc+R58N5f/K13PqTBGvWRZd9z+7n3Fdnqvxc/a21VE5Gr33P4yRe1ebCS7jfzn0+iRibS8+W58ynYbmvM9g+fgE2Rq8L52nNbdz7DUqE385/iTfsq06liXo+AsdKuBTev4GjQQyrUU2X59av1xhzBjruf00kqYcIY+nn2Snp1d98+o5/Zc9cq8PPmErnlXdnvjSdS9wQ91OfKblMvfBVdee8F0Jj0QVWDDydp2zn6gvkjLD8+7geiVaQX5CtAr3sC++58Fz8Dl/JVnefB3PkRlgL/yrjtzs89DlWimujOyoa//Pv77nMLdzffz6IJ8tzuh7x8//17Wp/WvqM91Fb9ajmWu0L/bnzkdyhf9BlnTtdnYbn/wvuPrWGWa5+TPTCq42dvufZ3V0+vhVfQXwgIcI7yi++5/gm25h4gv857VC/fBeEL+Ln8QvtjLtFWRpdoVxICrPnhAuJAU3J/Bk9MX1jzlwHNfRbF8PV6jCCWAJHnw8vFhDOL6dJ35PvnA1/AuXLmB+8X0omn6vegP7F8eL6QMDYv4JfElegl94x9CX97PtQPxMeIl+b57iX5n3kVXIc+3s8UGCO8gDL2hnq7wB/dn08yXzWjlBnRdn7JuVo/CZ9ACBf3iMvW496AhX97Sd9dLqr4N/cYy8Xj1J+BM4OMuQGdhfkkpCjL3cb6/5QGylL9sZ03xy/3MaPlsupL6IDzTLghnnccBl8gy7/jkqeY+JyLWBq+2M5yXy2jqpfgHaMJsnFsZL3teLQ4OV2p5/VL/AD/R7HBnJ8MpeoSy+0Z/UvlRn9p21GeZ9y5XerNpRnBlHYlS7L9bj90vypn2DPOy79L8mZ8YzrpfN/A8GeGCFsj5P+TamdvXGGfnL4YDwNXuOOnhgPtizPYgx9gYQ0ALeP/5/jL9f9zpVqBP4K/Jmfvo9sLkqeMPG8+Psmf/L8pbsRj/RnA5LzJuey+wMNzHM3rmK/1l9J/fkXzhMZ5fCs/XY+Er7kYCwHil12gP0G+GJ/9GPjz3R7oq4HF9aJ/pX22nlXQaagQLJWL6uJ2EEGz1Xk+WV/yVLCX8n34R7vK/zA+cr4ZXxDPzOoYPbgl+0GBpX3yv0KfpSRxV94x6ZX9Ev4MfADQ5V+b59ZX7Sv6evZlfka8gISQu+jX2hg4vWryu6r5QhHGr0gX1MR0oTJz4Frw8txkPawgwAdN8Y3u9TXlP1uav8SeP/bx/X7Np1f+LBZmlwK7PkUADg6WXhekDG+15HUn4X9mgFq+3KVrZZNX6yJokP4te/456r8GL4uloOvRq/uZfsnyDr5ZBMMP/HXO0sOr7Zmy2l51fMDEPPuBodQmwRUtyEOV3L0tZr/1+ObNmWv7q+6QC5F9jX1mv1+icV2SeK8A4ORVND7dL9a/ZLZzQ6rX+6vqa2reWy1/hr58u0Wv9tfYnJo9cRyqzXx2v5tLia+s19Q9WOh5rXrAH8a/1rtG18f+9Ov7a7Drhm1/n94Ja5yM6YvVK/qPsCQAXbU3npWI/SMbZ8uz6wMJuv/2fYQO9mR7r59n9u3sn9Q8ue7cXr6DnzEv1OP16/zA/3r5OL1FV/0NigfO68Vk2inzqYE9fy+fd1+Kr+fX1+viev/6/El+op98D8ZbqWwOXZ+p9R9Yst0TAVQ3D3ATkelC5YN9Kj5vnCdC+uvio6Q3xmFU6fsG/MYs4k5+xwNagK3gDWcSccG+o2OpE5GLFpOeDdPI57lhbz/lAt0/9vSlw+V54OipA3gzpErc6xEun9S6Ia3pS6MN/1FyHh8rznp1xWOyUfN8+wHWgbvjfGvPoN81Y9BR1xvsDfRBuWUc1W5Ct30/c5HzaFGrfLxuo3/JvvnncMVIDeIb+E32iHiuHQm/3efob7yx6xvg63AjQcN+Mb9OtzQLsjfK28dk+6j8vUPqTsnHw81EBc9/eHRUl3xF37tgrDcHWh/50yaBnHrm+ex8CsCVnfcWH1nCNuTTe64BK749AInvH0+YbckhwY8vDbm0gdXfY2c09/dR3T3+cfUG3H2+EAxgwiV1lmrKQwLsT0d4udXOAQmrpLCuZgddcsS4BHV8DBiP9+4Fb5StylvoGofNXAI5Tsky30bkimL4gw17hxI8JI3Il8NYnQAokdzLDS3ySsbdZqW/Hg/b/EzPK3HS6r8kcvJAKd49RtMl9LfOJp9ahPC7G30QefLf05RCauX61aIIXwLJLFHfqewGI/oPL4l1lYQewLXgJPGaS8jVmLcC2+Fm/iZxa3wwiCMzziX6t/X+lW32eAjxLVW+75kXb76kCYlwrf1FwLt+Pwq472VvvLf+7PjkvXb7R1i74sZLZ2/hDK6bFeD8zasJE8cSFkvhrD23xdv2oIzW/Ot+yYn+36NvlTQK2/vt8dB963z7gJ8TnIvNI59b9MCEElwbfNKtbt/Apam38PsbbfBW+greWpRO33y1r5Y084PQAk78O38ALtQEBO+rt8+CqiR2tvrin+Qwit+Lb8x307ylLf72+SOt6h1YZAjv92r1O/jQAw77q3y8Rqq4wO+natE7+RkKLvyHfcp5pt9AOaF38CoHQGvO/7qtI74W35zvzQAXweM6szhaVRxrv47mgIf+V9z+13ljnzZ6fulg86utiQBn/uvmEPJu+Kxha74N35rvx0fJu/hl+x1dC57bv/EfCM/8Q9M09j6NhHmOf55d01ARz/vn5a5ncXCc/EOJA577K4WlgtOqEIoc+lPYSblJ9tNLCIh3QszlaLn32nBecp42E9/UjzNB7vd6ufisErXfDlbie9MpVXPEurQ98UyEJzwnPwvfK4vO58e75bi1vPvOfJe/gHtSTdLTkUqfmXnrf9yCzJob312VsPfYOe9DsWM7IoDwBd5rVAOyKDPJKweyA973fUruU/BUPab3z7vtjLxTOv65iMdcO0xViHOHPQmYrLveyZ4vnW3PuC/znseQmZz4JVnPfM/VXc+Z8S3356fJRfBK+lhAE9X/N0vv3Pfgee2MDMVfL386dyffde+lnTkVdjl6WnPRC03PE5d75xtYQ+TlM7pad998KS8YX9uMVqXHC+b67r7/7d2ZV4+f0P5bc88L+gy/PvmiPNC+/d/T75XNy/voffoefPGcmL9uYDDH0sI+5B8IA95/CXygfnvPhwh8qTAx6Yt2evy3Qfac7ZImJ8OEA114fPMq/isDEH4Rjy3X6g/mB+9d9Pp1fd+Yv9A/YCVPi+EH9rCHgf1fP1mAWD9NdSeLxaPh+gnB/2XuLpyYP+X3tQnKhe3d9YHaBKFQCoznLOux1saTxkPwwdsIkbZvcgSXNZw8Dly5tLRkxaqcvFED+f2br28dcW0PAnb1TIxaDyzw1keE0nZU5ZKE9kI17Zh/MYshK/dVaKT4w/rUms9+vOJha6x4MZpseP5QdSH6dd0Oemznnh+2zc59UBGyYf7t3gNK7DsE4Rzz5M3wk7t08ao9kce1OytPYc39yY1DtDYQLz34PdU7SwyYo82gYti2ofoHP4szjYtyH+H30mbEbnuR+W4s7Cjli5kfivPPlgGWs4eEnHBxT+kq8Y3Ej8hTf4vES1gw/6RJT7CctYlKGduEvHu6EXD+hH6AP+Uf0U7M8x2c/FH9qP/kUII/rB8Qj/nP20j9kflg7Cm2GUzRH4yP9pRLDH5u6Ajv6uWAt3K1g2PypQowSv47DhJEd7Fe0ue3lWEnZ0bk677blhdx4xsHH6KP/oKEo/Ox+7ze9H5OP6HXat3nR+VQdzw7XuDy1ho/Ax35j/X45eP0Mf9pyvFPEUBdH/GP0m964/EpQzOV0tfOP/1nxGCjeeFi8LME/2uyv8eXkJ/W8/3HaSEHCf1MfVJRRKID58rBxYf8E/5Lu9Z+UBHRP+Jb6jnKJ+t28bnYRP+jHvBgYJ+KD/8H7GO0Sf1/X+ogENJcH9FX8qUKhyzsOJFecW7YP0kvzVfrXetCfGyC2ywavgJ7/iFs2eRr5bTryf14rJq/eFsJniJr8tllWQFbPA0txPZZOBQD9mv1c++dose7dX+BEEMERr2lT9peLC5wfgeU/6zh+2fWr+lP9avwS7xNfOT/js+FP3cJBAHka+F86Cn8Am48QTtOlp+RJujr9HOMAs9dnwCzeF8Kn46B0+loefM8AD2e5r6+LhQkSKQha+sJsLy5sFwrXltOLHYb2cR8qDS8qfh9nTa+Qz+z1XynIo+rU/mp/GJfWn5jP0gY1iXZa+jT+Knd7XxmfyWbg6+HT+pn7tP+kT7wgiZ/ei+Tr7/CDykyOv0i/bT8bxa1JyKfoQHX59h0vSyAIJlHFpwXDp/Gtv8ZZdP0+l0yrn+RzKveEFtpQN79+fRI4evcfwGfn/LIPrnidfO06mn//y6uvmM/3RRnTtuC7zP2KF3DLUdeiz89GtDrxxV3s/NJyQLeB15jP9c6b2v25+HT9HxXdr+uf10/Sf3lz+en4IX+xl2wuvp/jPdM2mvnyefyDLkCIJz+On7a+7kLh0/u5+TJ8iZcs37WECTZEwumwg/n4JP9+flXgIwvMqsP8aWL5QfpmgWfsbvdAvcgvx+vqg/MF/Pq8hL/gvwEvlaXV4/GKYfR8WEP+fu9vKF/QL+RL8wvxXH0VfiEQ5wXAX4GqzhfrC/BZPxD/Ux5YaIBmJ/3BKeyGiZNxPjwKn2hofj3ti1U3bIaITOW3Lct3Jvu3J0DCbrjlm7ZOdLgKr++1u6Y0Jt+fwuUzdksCc1zPHllPYdRendeOSEv4/YLNwi/uyLtBNFuAG7jr7+8t2qL+nTS5OxWbjS/+TuW4+Bp6Yvy3FhwhE126L8OHZimB7T0sAOriKI/N/LUW7cnSrwPc+molkC4eKUPVo+gKF3hL/IS9fj3EL0GpLDOPL9kC6t1prnly/uAv4I2jO4IEYV9nS/GzvoCA2X41GDU9ip2TsWyQCNDzvN0Zfzy/SKU7j9YB4FT15f1APDZvxL+dO+ciEJfimQfUukudKX+mUofFiAPxl/G+bmR5iv/590xofeIXyteXbcv607kK/DKe8r/aR8pBa5frtWD4uaA8fpbiv9Rfmc3IQuor8txc4DzknLq/ml/sLeLm5MvzYdtOnFl/mdprV5wtxZfqJFUifWr8YXnefCNfJRP66+ifubJwmO+hfmfIgIqAL+tC5Z7msd96XcV+6CE7X5hsLCwWplafeepgYdC2l44vqAgp1/gdy59/0iJdfuxPni/rbB+FycT5MLva/ISe9d+HX/WJp4nwaIH1/f1+x3eN5+sTDYXr1/W++araANyaCx50xW+5/xD7eVHyY5AwTYyed2j03Jg7yHJzIuGpIH/yTBOEi4kcfchlIAtAm9K4GqNCavG/gyukbHG5kxv2cr3LQ6ZtcfGHK+6dTFrBTv4WA7kfdOrsvxdv2eGv2dGb+q7RC2CxPcA3jM9VIQZWIPhxbgTS4akh9E6zK7S2ATLAJOg8L5EsE35p33vK/G/WgmVZoI3+Jv2KLF6CYt/JlfiGb/9Ldk5Y37ELb0Q1b8LGhgb96bySO74l3K5ngFClaG/Ot/pDfABHcJPLfkw3FsThqBC34uNzOcSm/aSLFlfUHeSRzpxEbYi3W7VeRN/paF8y1Xjg5EE5Re37oI2Epg0StY9fVC9OlV40Hf51u8fdGOZ0Y38+PM3D8s5AnurSsdz0BLK0sJTVn5ZD7eAm3eqrxyjN4n9BvUKeaQ3AcJ5Lu/hl/ZOEhxC3OR3bRQqvHc3aWNwwfH77N62Ef5Ku6E8zfRlTe5LuQZn3G+Ra1M7qdEWfmq+Q/2PWd2BKKX5sEN1ndhW3l3+K8qZ3TYUS0mfZ0try0qWtbO6v6maHO4+yhHE1O3ZHYdvcZG+1xJJbtLkT6aBHNDJyQzYyTFibfBqJXcWHH6i2W1f3fl4O/MtH7kOd3bv5hrS4sJ3dE8z7mzK2mQPQkoMSiPCj0X/L7vEZ6EpBBAn7/SGwNGbT7O7ucVL5Tbv8ru7s4GBp271ZFe7D2X5ltfK7XubbkKrbo9VkHkLB+kOeBGom4sGxoNqMCRXukmAaBM5XryJsl3Nb4Q7MAEbDXxQhLXs8u/Y9gSV7zJ0PwZpxXfyQD/nyCISewRPrvXYwNXNO7+LXk8btQyP6zkpRaH9dCRu0ppxEzz1E8TNYRyb89ecPagpJRi0U6EHXL7nTRvB/Wbxp+5UBzCU12OmbumAaSolG5afWTX3eNaj3GERdzjxgpN/zepf67dsCUnAbCU3+qd9ucgR1H/5sSTQMCPZbYYd+hYYwjwZ4ZhZ32/To93Oa4Xxfv1sKaNoz7xGOZzFFMOvXAUBAv9tJzIOP8ujumhMzWrCF+Z71vBa7RjURQhrs8jJgaIP0gv5Q+uALft4Db14XhnkYc6y2s0lXSaEcFqibxrSL4DM9nYVX6w4IESVQjgrLSJ+aZXM/HpkqfmW2z4Yx5BmYadr/fspuVDkxnYX3/PHj4M8nmDaAKh4o3Dsf7E2ZE9QyBJK4YOwGA6x3IedH8swT+fQfqf0buwt2Htg9h6dP/g5hwocEeXatt3b9P7ino/TAP83UIFoHUT1xlsO7eVYfI9ew0723qSku3Tdoku4+n8xcjTHpWJQ3fFiAF7/ru2D9q2JZmGfI9CvM9szmJg/KspuBz/eDZC0L2nkHvTtWhvbYxaEcCv2IWLLa21ObKx45wc+Uwtar8k2Y9nn9h35MgNRPf6tt6t9+4baMrHjS6JaTZx022J1j14vLY3kxxIz+LH1CR2ohOJ/I5CcMrbG9bFhjHol06vmjKQJJ6DP6xFgbORSe+rrXRYeQgHiD0/tV45d+o20jP+W1YObABG2HH6n9gyUe4x2aWF/uXam0zEP5TAeePbsob0nsERUt0hGBN+8u/rd+8n9hyg5f13fkseKrnPlMMNTnHm6M8h/XCrKx4V7AFfzSieGeKp/ePPSjVscZtPBAtb+nuTYJggufyUlwl/UkFSF4qlFlfhc6qaewfVxw71L7/So4/10kS0nq0o4Lx2Pu4/qbGvJkbH8ZMkDv9eaeGepF8o7/jq3vOmU3MtSu3HHX9+37c1qWjHl/TD+KyadoJof7IfakeA56OX+Ah3MHp6vUe/xXkRn+kyvcb4vcaie5HMSLN+Iu4f9/gIATsVs9WEycEbTNeHIjtEj/pkAo8II5sBAgUwKdsCRDNOgH7j6gVj2i2b5W76QQ+2GSHdBFNg8c4PIK0KfyUPERFqQc638G4s9f3ErMJBlK8KbHszzjglWZAJeT6yMhZqdMvnqfkRp/EHYdl79KFQ7i/wERWbS9LET8yzJcKEvBDT/MsKOmhLyavqfzJt/XAVfw4f37IHqu/swOj9/HZ585uI1m2/nd/rQ9c9+f38lnkYitz2R7+yB5/9s8XPKbBfFXs81a0nq3kdcjPSwMWJsNFBezzamYwbDH1yM9PhKAGzmk17PdRqiYtcpVMLyx1YFrLWprs8W0EYGzt+Pq3bo/27swt1Lt0Xlty/mg2Vgo9p6t/AnZhxza/+frfyroa+zn7HtPa7epzsoJlcz2BbSh/hUEgZhsP/rVWXf8e/8pAKUkgJFUiybfyWkfTEe7/X7+bTyNdZOrbd/J7+mP8/3/I/9G0AyGjotSn/HT02pacbCa4F08m3wnqxRvBdPNFEBxtmWIXTxxAl3zGv1o08L8Aqxza+Tyvb1ly3c44IKnaQ/0Yx6vmQKZv+57MlUkYFrY2je096BY1P80/xq/jFxOZnLEafNwqIpjkVXjZn+vH8wusM/3p/zae64ka9ZGf9BngZVeoEcZqRZ4Xwp9v6yTJ0eXDQiWIP3/3f8UvI5eOUtz38mr2SP3ArG+/oX+rXZIhxVcH5hyFeDlpZ+YhKFAfwH4Av027NIH9xf/UdTsbUk25a88pmEy0Qf3F/nL/Kd+MR6hf6VVSfpqTzG7/+0wGeasf3kvDnpuSsWP9uwFfaRPpz7iqwjcN64Uo+5q3bZr/Pm9Wv+hWz9yCS3MpoLHcohYb38zdRD+E0WO9+WI3Qum3ZgffnzeglLy7Z01nE/p0lEyM7H+yB5JxXjUot/oduy3/W5ZVf9w3jiS5X2H1brH8o0tuthU/pt/TJpjHWHf44/2K/b+417/Yv/nwFd1CqFxL/Oc8tY2IWlS/+v7Hzednp6HZpKsibjxlM/JXss8v/Xf55pF9/3jgZYJcN4CHC0M6fs4a+82pDEliP/wfx9/+elh8n8ykmnxlrY+JYh/U+BcN6PGUpFn6/sRu+3+gqHo/62/085rz/7n/fv+wJmo5s4kJ1/ga8EiBe6J81t+OyFephwzxY4Nd7XkG4UzWxP+/b+2dGn3Hj/kn/rtWbqnMv85f5CvDC+FFnJTSyH3yrqGusR/JnmOV6LMCpf0Pfj1ehrPy78WdjyXt1KkQzptsEe6PTpAloS/wH/3P+ELRdP4sVZIXgLMtPM2kMcry+No6LfNYl89RgTiRyrMg+PR5pGVwhg4n343Xomabj/K7/gaTqyWo/xx/5n/9v/Nv8T7xHqLSJjwow4Vkj7qVtk5oTxHQ+o5zXpYwqUZ3m0IA2W/ShIF6QVWvgO3bR1xYJ9XuRNWyZsmyfY/gM3/YYKyn023zi/yk3Gb8UqpRzMWxCNrNk+endQrZh7dlPnbrGvW+1Fk95CvfHDgGwQrq3J9oYNSK0latL3PTI7rzAtbpGkmPteBBiOMwFFihZn15BIFrFywVbdzXCeyxXNmN6Nk+xNkhebk1pZHlFwAFmx3MYEYktyL3j2DWxvARQ2D7xipUNq9xhHuh1C2QmrCRyFgjvM9sb0nfpokr1a8Gw34tQ4obUd7p+sQk3Grb4+4pxorFdFGRg+9vNnG2tmnfoE3rm3u80c8Lj9NZTOTb3RyS8/gKJu2930fyP6nZLKfQUWffns9XMthibS+3CnfkYdCf/uViJg/nX0oXvHmLgLVFPxAQkgjvMRlOQJqt5G/PGJSns5mtiuHCggfCPkj7fnDRFjvDisuQJmQoN3/il2ARZBNvmjiHAHpBoD7fvBOPwfEdSEXfhzrHxPEXvPGqJpxEKdgLvANwCOJuxLCC/qP/hldOfxMfEGyfN+2p8/iWHGyfG5sEC/uotGmfIpkoHfgIAVmfPFEp8pmY/rwAWjpmEphIAR6fHwAXg/kJrB6fJLHMy/kFSMAfGemDDbFmUo2yo/vM0bEtJiX5rKfNWjKY/olgOcfP4ROdxh6iJP/uOosrsF5/oVIHP/nfhCOJuLrLO3LeSotwPrUP4lH3vFcIK3zPvbPPFAjvFeivrUAqZGwfOAgD2QucTg2YJf/nT1D7fmDbH3vDXwtlzH+jLEwLhvIreohJsS3CqPBbaPsomI/hC+M43OF2jPNlPxBKVNEAYT8udxoigtL3FxaFUQinfjaFLhvGOiohJnOWlW3DdHLCGCnfvv6Ci3MCXPbbOn4FnOj5vIB+COJt9Bi2vC7ur1FlNjBVej5vFjdKbZj+gEtpiDmk23LY3t8LPwfOXUkUrHtaCX/mXogSHLwGM23PBkADWNDCPo8FjvPksrobDnBgMfEYAkYbDnKEv/hWTFA7L+0utqJM1k3MmZrB0mGCfAkRGIbMjiKoARcOvBzP1YHdxrnvG4KmcAUbumCfNL8CgbLVEgLvJTAkDzLJAif/i8HLsLL0ICCyIDvLP6PKbN4soDvAW8rr7BhfFjvN0brr7HSJK3vFwnI6LHF8h7vNNlLr7GJKAjvEkfBPzFsPEsfN1YnDLHCAJMfPS8PKHICvGwfB9sPQ7CUlJf/pA8BjzNbEr9/mY7Al/g3whX1OLmqArALXGyyp0ARWWDnzEagnxPPSGnVvAcBHmikUAaViLobILvGt/rBgjT/rt/jI3AyAdiHNyAdEAddAiebNpMgFvAJGGgPHpiNNiNEASDcHELAZhpf/p1aphrL9Yu//tjzOTzA0vmiAYBLLV/toxAvvMUsh7/vnqMXfN/hPCvCF/qjfHjWlDLNQSKjfFa7FDLKrmKjfFD6FArGnKhXjtpMs8AZ6dDVfIgMv+/kE2BdTn85LY3lo5rDfIGyJw/t9WCq3C7YubvIjxO/muVfM+QlS/rFWpaAcc4GI/itRB43OLMk8cHPfhU2pjfPSyFJSEL/ry/srwOpKIxZow/rIfAYop7zG5/mz/sg1lPJNmAX7frmAXG/nz/k9fLlhA4ZsWAbNfJbhMP5rG4IfxOXFoj6hGActhLNfAkYMbxgnUB7Bj9fMcXPAATmxgdfB3PDbJhLoN2LrZfFnrNu7FIqJv3AnGIgMrY3pz0OefIgMuQ/me2H3vDQEGWATfhsAfKG5GAASEIOn/g15jjrHD/iGqMBQA/ABbxilJPP3NNGDv8F6/hmAaw0EP3Kw/smAbZfGGrP7zIz/n3vKEOpRLJeAdyfBXCPAAVz/nmfK61OQ/o+AZNvASBKPfsL/m2fPjmMy/sV5H3vK/CNQ/tZyFyIEqfL7LNLxlpxDyvIoGMY2GI/tOAcBAZBAd9/n9An3Fp5wM4HFCjJKfLdsFibAF8sn1u59BN/hWcqnblI/iEoLIgk+AXyaqt/neAf+2kRAVmfPeAfR/tY/hQvseAZt/jBfOeAWR/mQPHuAdzbAaAdJfJySqkHIA/tJfIxAnd/lS3LWGF3rC/wDnsu9vNGtEvrG0/h63COAetzHzBPBAaJAYWrEOoCS3IxAQ5rNJAdLfB8Ilc/jypiWAdZUB67Ei5oDfAd6MjLIVarZfIVIEb7OO/gj3D7yoSlL/rE8fu9fN6dOffkZJMDliPuKRAcrwOwCEJAeu/thfLZAYfrHV/h/OsY7BRAbDfKfQGX/vZAQN/G95K6/l9eEu3AA/KN1PrUGKQF6/PNhKY/vI0EI/PWVuQ/gJ6BFAYa3PAATquMK/LG4I5zIhxHbFHZ/E9QudxuUcPU/HsSOE5jI0ozTOAen6hho/uQ0AlAbEdMo/nLelEATr/Fz7Bo/gkoAlAdhplGrPdjC83OZzjD/LrqmFHHc+mOimHfiufF6/OI8L3/nrmN9vF4/EF+MkLJvkDM3no+l5JgMAdD5EYBlfzCXlmFomNAdNbHexvK/ADrGJAfpGFpWEzbi78n0/umMBe/ECZIXzHZfir/H2iLzzDfwLZFHV/H/hEUrP/3F6/IgDAZrF38OffBg8M2psB/oeJHZ/E4iDnzFTKmc/JcFEX/plrHZ/GLcmTLJYEDj/JpcGTLK+GNVAXcdFKbBlLEzbicKMffnSGPGeu7AuTzPqFEI/DGVDYbKHnMFxip/EwWphrLFms8/LKUu/fmaRIjAf0oD67EqINL3Oy8JqMm5AXrfNhuMx/gF/rZfLMmCU/k2/hVNB27NZAbZfKDwHaZNYHF7jE7fEszPe/lS3KvfPQAgSIB9JFNbhiiB5bEs8k7fHx2PAbOJQs8/H9rN1/vxIip/NOQtJ/qAEkR+nioDmLCDSFQ/NrxDU/o4wCj+iw/C86PKHJU/lQ/CUUiiAU2/qtsI0/jx/na/DqrNKASRyF6/IE1FzLCksmM/GNbjjzFZbNo/BUJjjLGbANo/LAAplbNBQl4/IF2tQ7ILWNo/BQ0mcAVu0CafI44IgxGcAZA4NK/JmJjb7KvQNZRHo+gqwIXzITJH7fiful8yIh0pBvJ+/BLeLobAJ6Gy/JqiMOrN0vjDAY2TlO/uP/jC6glAbEluP/pjxNK/DGBCN7NQUkntAR/I2UEP/ktjDP/PzbPBLGAPEBASY/BiRliLKOoJ83LkHjCAqv3B5ApLAa1uPzAbt2hbfFzAbl/s3AYbwK3AVBAWU+A3AdQKHPftBAWo/HzAe6Aet6I2/MpBuQ3jFKrW/C55OQ3mAamy/OhhAAfJr+AkomU/GNEiMAeGUuS/E2qCOJrRYjs/IK6NrLPv3DQEJbAfR5GHfpfqoy/JVwlfLBa/uQ1MdQPPao9xmISBJPKH8AkRFZ/gRghDAUhxPHfnHWl7Af8rEtJqMBNfAeqViUAfqrEfAfVAAK/iq9mU/CcKHPfmTfOS/MW5Hg/loHGM/HXWNkAevCEXAahCD+Ab8lL0/EVcNkAYcSF6/BDwlS/q+ASaeiKGAK/uggdamOwhhGAWW2JLAevUmL/q+egPASsCAK/mhmglAf9aFQpqfsp7AD3ATCAgD/j8TMbfJ3AUblt3Ae7fKfNJD/lU3kluvJrFL/nNKEPfEFJhGAVySE7fEtcg+AcG/hTAS+cnPfuggQhBvazCeAbQ/pIgdtJm6/kXAYqhCYAd5/jU3M9Cjoyl5/moYPn/J5uiEAfEgvn/Jf8OIAarIPn/LQMhgAT0ZD4ArgWg+AcNJD4Asg2sy/r/xPsAqm9E0LIjxLTyMqAo1NKBAaofMqAvZevHfsYGsqAgLkPI/qSwlSAnLVudxo/ChnfNdXo6FjXHDpaJEAlCMOdxmzSIwAoaEGBVKsJHbuFKAjmwBi/p1iF2ApMWnPAVZMCRFMDPmHbLavh/zOUAo5WEUrHGQrQAhRgILEDIQnDKsqAuGLieiPJQEO3BLopeOITLKnAF2Av9xAo7LDUiloOH/M7lIibFNxMbULIAslZHnrALUvn/NRFj3bEfQGn/AlJMPrM30m8/lZkAZVnErBt5HX/AzQvjAQx/lD/LgYjjAc5/PMgad/mQPFT/B5tMsgZV/HbbCebJI+EXAWEaFWbKQwj5/HSuDbLFTKh5/EAKGBrDr/j9/Kzzrl/hr/o7sCDSMr/mg/od/C5ksy/uBhIy/IV1NB/j1/i8gT33OTzGjQAlAdEEpsAQMBgj3GtZjjrFxAXF/FpYlSLOxAZQAgfbI2/hx/um2GTfOTAYoAiopnnrAaToMga3Dta7ONlL0gdu5hcPIo8Pjbn2xJN7Gc+p0gTfgs8ATcqIYgXZ6hjzG5Ih0AusckDzG0zKYgVeutcAcwCHMAvZiOWLMHggEAva8CPIHsAW25JYgUeNDrvngyqEAlJ8pXAb8YvUgbj8Bi/ozYu+AmS4mj/tMaqm1JcMMS2FZ/unhDygYOoIq/kltg+PP22DWmOXfgIoK2AsmVC7zNvnL+ZJWlr0kFS/oH8u+AvIFHL/skBP2Ara/rGATxhIMgSDCJ+5gw1NY/jCgcixNIgbIfM3/Icwnagcs/DT+CVARQ/my/GLatPLHD/tK/IAFkT/gnUI58hchjdSuXfmocggAo8gXcgQvfjcga5/gD/vcgYT1sNtuwgdPfit/FNaPAAdL/h5/GTfHAgXZvEXEJZwC+ASIgbWzlQSgeAcs/PTwGggaeAUp9pX7LeASX/D4MGAARIAdY8CAAKHHKIACuAKH3obDqylmUjl+to2gY/zCNFvwAEmVi2gXebARwBOUGp7OpgG2gUmVk2oCE7ll3mSrsE8k2gf2gfU1oOgb2gRWLsxwD2gWOgcKlu2gXXHgSPnsLr6UDVtrx3uEAFtVt46HGwJx3v9jgMLPoPKx3mWEBugeAaHugWOFCB3pGdlugdR3s6tsr0g4cGR3upnADHCYKALvi5wkR3kSdsMSDh3lqzk7HFOzAYjocPLJ3tFlDflJ+gVAWKF3lFLkZtjegVPHJR4A8mOxgBB3jR3k3qMegRLqox3qBgfBtvugVNnKBgeNttugU9rh6RqKcGugQfHHBgZhtpBMJ+wP9jlBgYBMJZ3lx3pBgFdcnp3iriCn7sRgZ8mN53tp3u+gSs2FxyMMsk9rsFhG53iZ3iMPs+gWnwIRgTugdm6FfhOxgYegYBmMZ3sd3CxgZugckju53lZAIegfzHI53tfMtRgbugQRgWnPuR3megckjmdPLJ3reSoLflwgBnJF8HlwvuEwkqjupga37rWLpNnhq9ql3sOgTIMFnzJl3jpgbqbuxIC1aFGrPl3qajpT3gFvsV3nT3habk6bl5vrQjuZgeGznHnBT3nj3lT3oLjsjbvFvmIfq7vr37nWIDa3uGrqdIKC/M3HoFgbIwE1QHr3l2VhGIPxeDUDlK3oAwJxNrK3u/TvwsCG3q8gFUvkk4hL9rtUGdltjjkegkWrplgSv7D8ZOL3m0vsm2Lfdta7rYzgtKk/dg69oWlv5gaK3igzpBIAFgRyTmFgSz9mb3rYzpA/A63jCtAAzrVgS63gW7gfHEFgR3uDG3iSvg1gVPdkhrtozsrWKInkO9qQziNgWO9mBrs1gUqbEHblBrtNgUltlXrnW3llgSW3kNga3Hl/8E+iGWHiRlrowCSlP+bktgWVgV+br87qVgZgcq23l5VlVgee9vUzvtgT23u0zra2CnbiQNNPrqtfnoDnuIGmDuYvk9gYifhJXq9gTgfnnUD+JG9gQwfiprtWDtyvr4sPgSGSfnmPm4nkDgUKvmDgU+vtR9oqNjPntuvsI9vtmBifuWnjwkN9gbSfr4sPDgSjgUiflIkL0gn8zsjgdSDr0AAAAEKEbATI5oC7MwDsn5dtZKSivKiSDbQLhGgCttZEppXJwmDbNKpZZzIOCeMKfJy9G5fio04HAsACpzqM7gqxoJzAxpGHprJzVDZyEg04EdoTypz04Fs4HHkAYyid97YTBi4Ft0S1yBoZDf0gcFxRLx5agH96aZK2yJdtak6wgwjOD5S4FA8BVtbq4F+UiU4EM4Fq4Fqy564Hn07c4E64FlcCT8jlQ7OEJm4H6sCc4FbZT7hhm4FAurjHD64Fi4HjwT4CTO4FA8DjJ7m4FN7Du4HU4ETYo7SxpD77sge4F+4Fa/iW4H9KAbJ424Es4F24EJvAbJ6O4EH95NZRi4GZvAa4FL97x4Ha4HDoqtOrJ4HD1rR4G+YBGHqYJwpG66lj9tYi0rrLDtpBU4FZZyiSTp4HF4EM4FtJ7rLTG4Fl+iC4H0IpqITtpAvqyKABV4GBUIi4HHbwNmAt4HmRyqD7MlS82hV4GNOj84G4OhzwBV4HIqhtJyrQ4eaBnK6sLDl4Gs4Ha4HLQBd4EZ4El4HyJakQpJ4HlQ7j4GL4Fe4GZJyZG5h4G+j5T4E94GX6Br4ER4EB4Hvcy0G6rHYh4HqM4m4hTxx7256+Sa4F1fA24Br4HC4Hd4GB4HU4Fl4E1AgV4FfioiJYYR4W4HT4FP4Gi/ov4Ff4Gl4GO7DaPKSDaDKTf4EpygU4Fc4G94EQPARcQB4GH7DMAAS35G4Gj4Fa4EgEEH4Gv4Ee4EDWp84HQEHy4Gwq60TZt4GP4FIq4Zuac4GIEF4EGx4EYEGC4HwWpQEGN4Gm4FkEFQpiaDb54FYEHEEG5D6r4HBZLM4EB4HAEF4EEmt4sEGV4HUbBK4EB4EYKSwEFoEHU/AB4EnEgq4BYEE2SCy4F54EhCxYEHukJ04FR4F2Y6nS7dt7z4GcEFfc5T4Ep4FP4HIixgEEyEF3ZxPJY74G4EEuJYc4GR4HTGod4H7i4S4EZ4F66yyEGlFpu4F/4GmJbIEGWEHkS7L4Fj4H7hgiJarsDaEEwEEJJZaJR2EGEEFWEHMEEoEFP4Gq0414E34F8EH5izyNoB4G+ojCEFJS6j9QB4EtDBD4G2EF+EGsEGeEHaEG8EGuEHV4EIEGauR8EFOEG/4HKpxKqCOEH4EEb4EqEHfJYK1ZiEG5EFZEGt4EP4EL4EOoBz4GSDZH4HiG5MDpBEGSDbh75nK5kCif4F7BBs4GMpYCEFAEEG4E/aqI+py4GkEEBqQMBLeEF5EEPI44EGlEFnYRiEG14G34H63K9EHgEF74HjEF9xRDD60EGKRLoEEr4H24HD6rkEE2EE9EEzEGrEGgEFO4H2EHR4EkKDlEHiEGGEH5JbUEHn07n4HyJaS4QTEE9OhfiqsNz1Na4lQO2JkFZ3dYvT4gby3EG1hjNj5ME43jCrdZ0vBYrQ/J4T2r8FIvEG+eA3EHlrJCYY+LBmo5ZIAryCT4Cjj428AvdZLUBvEH95ADfJAkGFd4gkFDYAR4DgkFAaBKr5FFZ9QiZjaZmB9h6tSYYkHtjZ0n5/JaReJjlBPYEt2KeSAGo66TDokGs0CPVA5jBdMBUsAW9B6tCXOBjj7Zd4yMAWqTOFCJcwbwD2m4IkFiUBIkFxyAMkFIn57swnbI0VZgC4GtbjZ6Pdb3WJxi5DRAnbIyeapEBTi4Vl5ihLf86OYFvWCaOIAkEXLIb1jAkGC1DT2BckGesA8kHykHEYDcdwWrjQtJvITM44ckEBiAakGy4BakF674p1Cw65yVaQj5xiDDZbY67/a6qc4sZDEkGAwDWkEXN418zLuLiV6mYHdRZzA4UkEXLLEByqkG0kEOjD0hBmkH/W4IyDjjSs0DgUiIiDskFqkE3sAmkGykDBkHkn6N0AdHaqV4yV6/JAbl7hgAmuAekHgX7j8ArWwnbIdnJCV4j4C/eC5kGWr6kkEzJAAZh6kHhgCyjh+kHwkHRkG3VDIkEDhCQkFJRB/DDlkFTMr5HJRkEBkEVTB1kEu75t97mV4vpBNcpLVJ43ASDY3rqf8KUV464RUCCrFYW4IRdYEVLSBAgDZGLqJJrWl4I9LAlCrFZ9awr3jP1Dz7DGjbl5ANiIkl6jkGDkEKNxydYfZDTkGrFa7kFwdZTkGu+hLkFKiBnl5WkxUCA/FaJH7ZbD9kEHkF6gDrSDttYnkFjkEPkFsyqZxzPkGDkF+MzXZxk/o9GoUFaoLraxoRl4OKxfoirFbXkI1855KDy84gUHnkEkl6RIRE5CQUGbkHzkH+Wj1OBwUFGmiRnDLe4d/yag4njBedZtAZpoSQUHEmIyl4Qk6ag5eaDIdZ3kGnkEPkG4xy3kH7kGu+g/FZDDzpEjP1ADkFTFa9iCNdZ0UH3kFhQB7WjKLYKRpVfyrFaSCTBdbP1AAkSFu5J5CnNzaDY0lKECxcUE1BiUNw0lIOJgMUEncxgUGdMxIUEsgDSUGoUEO1IC86iUFrkYRl7TULIoAqUEEPj9kF9TCiUF1LCOQAkUEvkFhQDpXzlpyUUGGUGkh427YfZA6UFGQBdbAvlwO1JgPCzV59ITfkHfSxb3C9V54UFQl7bkEzkHslA1tYEVJWUFJ5A/DQjkEyoztwC9V4vayKUHAR7twDB3Y4t55N77AAFN5FN66oAlN7DOqRN76g73OSDxbNIFJUEO2JXca36ShQCCFrpUFA1AmOw2brJUECuq/kBYt5E4FLoFAG4mDYufzNwD0nbBa7lUGk8AsABwYFcl7xZDU4qUgBVUHWa6B1RZ7J1UFuWqIl6NUHvoz1UGtUFeWo5gBHRydByybZuWq1UFnRyizLNG6uyiUFBjUFLl4OZAXbKVUGaOjVUEjUH/8AtUFjG5LUEDUGg6iLUGVDwHwi9UE7G79Kh1NwdUFdhR5a4sDYdWzNUELUG6a5RQ5xjStEA7UH8bZ7UEOHBnRxyl7F0QruCqgDXUGys5WMZczC5nYal4O4RPxh1UHHwZ8gCybYv37PUFnUFjG6dd7m3ArUEwRZSEjvtg/UHszbA0HLAi10jXUEis5yRjhbDynbKmACs7Y+KKQConan8QYRYg0EKnCQlAQvgXu52k4YN6HSBTyjGJRsAAslB9AoVdDE0Gp0Rxw7k0GmN5JlZehQk0EbQBuZL4RgVI6tNZU0Hc5r7trCN500FlegM0EKJAc0G7bYVQA80GDcbM0HEN6qm5IAZU0FC0F8N61iCqxri0F0oAc0Ei0EMN5zNhU0FIdx80HpSDQeIqADEeB39wcN6qm7S0HMJC80HM0G7bY60HTkD4MBFxqmVDyN7a0FhKq60GtSYq0FWs6G0Gk0FTyhy0F4oALADr+BLejRyRhgDU0E4spBICm4xnXC64CxkGTjC00GUlA7fSv2jgfZ1WzsZCEqCatTJMAV44G4DQ4H+0Hr+DIw404jQQDsK5MWjBeDrMBuMBUiBO0H3t7Tp57C4ycBUXiXxz8JwjNpVtbi8w87Z50GTiIF0GXeyI7YCaAjNpdtZEiQcTRXKzV6xDJ4ZhQi7C10HbXie4HA6yZJzF0GEZCl0GwJhudbt0FadbV0Hd0E8+Ql0Eldyy2pt0ED0GEZCe4G1CaDJw90H10ET0HlxwV0GD0HtHixbj3SCO+qpJ565R9wBL0HJOzQdZa6afLZeZzdrh8dbD7gnUaz0EwKgTXBV4Gt0GH0EWPLupaACSO7Y4awPBQ84H70HwLwpiyw0I7pZ2tCp7bNyxEhg+JwTors7Z6WBRVAbJ4U7YWcgpizL0HT0GdLKz0E/aiTiLv4EGnz30FT0FV4EvPC50EgMFj0EYSSi7bAMETvQd0HwMGL0Fz0HIMEArCwAJn0E3Up55ZIqSDopn0EhdAcdbEQLl0HP1L3gARUG/N7/N54t6At4Et7At5xUGgt4JUHnN7IOD5lBwR6qbx65R6JAj8Yvf6rZLMMGNLwBey4aAazDFUHkX4gb5vZ7WAbU7AhW4C5SMl7CMFEDa4pwaa4a24WLKNgiiMEaa5s26QYi3kFO5xma7J+DEwhyMFSMEwl4SME5gC285g0B6bAyMFBDCSMFjhSEl59+78s7KLb2C5Ll59+7Mab6UHx1wKMFqMFJBQ6MG2MFaME545GMFzo7iMHlBh8yDdxyaMG6a6AB7ciKDJw22BH2AcZYG7x+MHlxxOME+MGMnzBRyfJzeMHuMGRd427YBMHxl5CB7WqixdbRMG2VxCB65NJeMFZ+Aal5CB6EuTgDbu2CVOoa24rMLeiDyMFaMGFMGnUC285iMFWt7Q/TtizlMF2MFRLzAQxeMETq42cCE24qYEwFyqC5ZMHJJ4hME+84iTrNMGxMH+MGLRS5vA9MGx7CNJwqMHhdCDMH1MGhMHGMEXl71t71ziI7bxMF5a71t5atINMFjcwOdZet67wihMEzGhaMFad6T5xhMH7Vbyt6RMHrMFuMF8B4zzCOZQ1MGbMHOCTALg+86uSTO27+kS0DY0C4DxBC25bMHDMH9Khva5fn7+mBMmjEESn8CQjDW0G7S6BIzGALKnD8PDC0GO0E0g7vMF/MF8pw00Fk5YgsFP2IjsBm6wx0Fkg5YWAfMG6wCzjj60FxjB1UgIsHAlAAsGm0HXRZRVa84FosElRDfMGz+DQIZ/MF4sGAsH6oDp0ErS6Q5posEsNC7WyS0FQBCbRDQSCk0QO0GksHYsGEsFP2LEsE0sEb+AssGbKBBp6CEha0HWB6csGn8Ae1LIsFKB78sHFUAE4SMsF0N5xdDwsEW5JAsByDza+Be0GNfijKC+0EirDy0F41CbRBXm7FUDYzy7sZa4Bh0H+syjKCR0FbMDR0HeN6/hAUsHMir6k5NRjJ0GZoCp0E28BksECMHdkFAG7ILaLQzubAQnYMj6sLaOsHPUHsmjUj6wLZXUFfc6oDbgLYZ67NUHUBoWQB4LZt0AHUHwD5uLYPKJuRirRxaHAUZzgLZusEHUHKiTrLbbF4qj5HRye/B4LbE8rsYDOsG+sHdF4BQxQ0FhsH8LaWXw5sHynYusESbCliz9YhFsGesGw5IJYhFK6yDYlsFCJjzUF+CrHl69vLDE6hsHFsGVsGATDVsF8DZOTp9KyinDlsEcDZOTpLnztsGY+j1DYFTpoiLesEQGp6l509bUgi5sGtsFe+BTsG9sGNsGzsGXAQpsGpDY0sbuvDxsHMqikDarsFVsE+sGLm4eJJrsHzsFDLaKRLNsEHsEkLaXuyeCAnsGRDp3P6OQDI0ErDY9dr+sEHUH8owdfa5RJEzIHUG3prmLYBqQDIZ3oGPKIkLYfRqNgiRnbQ8SnsG9xTXsEcOjuFwWeY5fbTsFZsEA5BBywQcG7sGg6y6oRMxxgEiAcFLjQDUGgsqUjaJjqF3CA0G+1BoKBIcEYcGvsFsLLmLYzzAaoCCnaRjaAcHGF4BsGHrRDw6rDrHsEesF9sGIhIhhQwcFuLbI1AZsE0cGMcGadDnsF5eABDbltqiR5XUEscH8LZ/DAcqQMcGHsGbRDQcHLsGJsEIoLtsGuEJqIB4LZ+Oyg4yZsG7sHCcHnihycFuLYKcGIXAXsHOBKJy4tsGesHq7afsE7sFuLbrwBlsG6cGHsFUNq6xhKcH8LbGcHOOBqcGnTjuOYPsGKj4kLa+dZ96Q6nZxjYItr0cFOxz4Jj40G3W5E/biMChGZG0F9x5CsEfOBIKCDTKk0HNjwksESsGx3ZecGBcGM0H5FB+cGmkABcHGALKva23i8sGecEDwQRcF60HssFO1recGk0ES0GJcHt3YH1opcFZcGiRAd9p5cGy0EhcFm0Gx3YCebt+xG0HK0HRcFxwYrQAa0FyDzZcGZp6FcFxcH5cHI2BNcG60GqvDisGlcFE/ZtcE+cG8oTVcFJUbMxq60H20ElcFYsGUlBjRqhGZu0HBcFWZh3CDysGFEiKsENMBp0GORBijI9tobQBxTZasEzcHBgYgHB6sGtWJR0E/iSwsGWhDlcHwsh20FiLCnUqSOAp0EaOCLcGLoGCMGk4HfoAOfKZxxqQAsurro5ulDg7YPcENghPcGwjxF0F4sCgMHfoBtGj90E0WKGZ7foARgRn0HFezR84YsBM7avcEl0E/cFBKBt0HsmiQ8HozBr6qJKxvcEbW6/WYj0GFVpj0GHW6Y0pupwQ8Ed0EY8H0yyT0FfcE48H12ACYZ/0FeZxI8GL86rjpr0FeZwWoQUFb12ATog27aroAafJ35a08E5nTKJwBVxwYh1xbC2AIuSo8FnSwLW5EsDg8EgurRDbM8EH0F9yzOOrk8F08GT0Gl6jVZ6HW78BCU8FTagXVyHW7E8GYJzY8E7W6Y8ES8Fo8F885xe6N0GGqwM+RYb6a8GNJzK8HR841yBZERL0FVbbGoDB44wMEIRgzGBV84o8GIMEn3JfU66j6RUH9N5sACDN4XgDHN4e37nN6SSAmoTkYBSwj9swIiCcMHie5EcxLCBEhJNWBPeC+8HVQhFTCdNK3kict4w+6k4GEr4+aj6UGtmB2MFdrYM9wVXLSMGEr4/LD3pyJ8Ewl7PASoGDKJy5MaIl7p8F3sSDJyE0ZGa5x8FX7AJ8Eo1L6MHYGDx8Hdxy5RKea7TL6OioFxx18GWMFJHgocjlxxZ8Gl8HgIwHwjWRJJ8Fvozd8El8FLL7avBt8Gp8Fcl4zKAB6raDZERKBMFwr4xbB1Jbt8EE4Sj8HeBAG2yfJwD8ElM4z8GfJg8RLmjwcZYIzi5NTt8HYgQL8G+Th/Jzx3JZMGzdgAr5z8HzWR/UF6Pbf4y78FJmwP3ZUMSYJygGodHTSTaLJiz8E98Ewl6ZaIzpRn8EPKC7MHZzScQiv8Gl8E/8HgDYr8HTjbCTS8UTKXJXMHACHylIOHAgxL3MGL3afvD/8AgxKda7V25EjjrkibKBHkb4sGr25v7TS/IZ4adcGjcGeA45FAoCGS0C+cHssGY26usRP2I5DowsFGsHUfafcQECHhgDukDoCEqGAAjQ0CGc2L1cH7cFHE5+BD2JRBhB0CH9cFj8G0bhP2IfBA4CH8JbUr5X5hYCGm/j0CFWbB+Dxw4CiCEjcGCCFQ4E9JzS/L8CHcCFyrhMCGkuA8sGsCHPM5yCFkCEdcGKCEaCGoCGSYLSCEa5a/hDUCGlwrYCGBqCe0F65gKsEBcBKsEOdBqCHPhD6mjcIioCH20HrcGrYA6sFbcEBcD6sEWiCGsGc0HqdBTTiYcZPMB6CHarAAbCWsEXcHWsEBq7g36x8Ei4Az+L1sHncqMl4RCGjUEbUE+MGG5DRBynUHQ0HvZbWpjtUFOxwTqCpMGJCE9UHxCExCG4VbLUFBWpV8EhF6RCEHUFVyx7i5R9ZTUEwlyWMFEb7z6xQ0HRCHvZaPxijUFA0ENCGRSzrUEpCGlS5/CTbUG5CFZCGsb53UHUBoJMEAo77UFg0FZZZaqZw0HdCEdCFfcI64D3UEDCG3Pyk6gvUFqYCHJj1sFdYB8gClZZm3ycQgfUEX8FUmpZ9wHUH1CGrCEj6h5dDw0Fbi4Z8hW4CgYEoV5bi4iWQi7DynbwV57CFPuxtCFJCLq57QxBrGKucHybx7CFM0busERhRukg3CElCGoxzel43CHluCYcF7qy2FzdIALggnCGFkp7CFMwhjABg0F7CFWbo4shQiGjS4uoFQ0G4xx7CEvJjo0E1Og/15bi6HJinUA/CFk3x7CGSSw40Ht5SE6y4iGVozvCHOer656oZqpgKonaB3bIiHRByhsHXCHwiGFqg7CFnCFbCE/pTXUEjS51DI04i9cFgmDECHsiE80FTcENcGV17EqZs0FRcHciGCiG60Hs0H6CFfCDPr5KxYy0GeMHECGz3IciGZcHFcGYsEyCGeA4IpIKiGc4CyiFpYBX5qC0FKiH8iFbE69vLRySVcEYsG4dCOxDq0FVcHKiEGCHUfa4b46iGaiGI5axMztcFIXwSiF+yA0g7aiFU0FW0HcCHWiFK0EncEWiGSiHqdBcLKSJJBcFKiFysHmCFzcGWCELcEhCHqdC9hIcvKk0FrcHfa7OCGbcHpwDbcEN2C7cHPIA2CH2xAGiGL3DHcHGlQBCG8OBuxCg+C1uCXcG4h6lUGx8HCY5525n8E97DfZaeiD+HyNJyjRL1+ipME/o7liF1iEtpy8txyMFERJQTIL5yBVDX8EViGMl6liE5sHv3KcwpMZw1z5liEb8FjNjwFx0L4qj4jiGpsEGL4VhqNiE1n5yyI1iHtTyViFDiF9iG1iFziGy34wFyriEcDbjpz+YS18GXRx8DbbiHUSyziFbiGJz4bGZdiFNiEHiEJYjv3JjybEVyaj7KXJ1iH/lyiVCXiGz3K/sw/5wODw4NpPJIviEL5wcohG7bbJI1n7fiGN0GbiE9iH79yVcJn8GSUhxPY8QADIZ3iE1n4QSHyUg+crUj5EJgYMCwSG/iFLiFS54biGLiG7MHZQCpJb38HoSFjiHCHLKLaASFjiFuHjWcEgxLdTQ31zgqZ96SNRJxIz35zm341iEjqRUSojS5kVBr8SoCEzOzcCGMSFMCEmCE+iHOiEWU7+KzsSFECE0NC16xYCF/9oCCGWiGeA6W5xMSFUgBcCHECGnNbiSG0CHEzycSGAQBRVaUCDKCGSSHcH5A1LKSFySF6iFJk7fpwcCGS0BSCHECEhpx3SAdnLCSG+iGeA5oVw6SGySHyhRSSFqSHyCHsvDGSFcSGmSHWSGaCGOiFWSGWwDsSF6CHySE2sFZJBiSEqSSS0A7XSmCE2kCzcFA9aW8BWCG4DBpiExNBj6qv2gkJK6QGh0EJiG64DuCH6kCeCEqsFaNDaSG+CHxU7msHsFBWsFAaA2sEz16Li6JHDBYhFpzOgSl8EafA3SRiEqWRCpCECMwVXgezZlSHXZbAiL/XCQEqXQB7i7YRxrqr1SHY/K7ZaGhAYgSlSGcTb9Za1SFwdZJEpdSFK4D2oi9SG+qD9SG/dBy/B1xzDSEJCHZwaRMSdSFFSFTSG3kGx34jSFZ8zKC7jSECHwxCGpNQ6AwezYtYYdCFNxgu84Q1A3a5Li5aNyoUFTtAz7D5ZbgTIdSEG9xYwQdCGonps86eNwJagUJxPI48eovtaJSAswjbSEmMqCdagOBwpAdCFqjL3tb0dKnSGq5SnkQzSExCFzSHvSGrSFZCFhmhvCgrSEG2xrSE+8TzSETSHQyFfBw27b+dxTMG2WpzCqCdY1xw3Vyw5LqnwrSExnhIPZzF4hcz3tZ/DBqHJYS5IejaDYXSHH8DEyFvSErSGNyx7i5Gpz9j7f4p3SFYS6HSFPSHhdxZkAUyEQyHg4pUaBAiG/NzNSHjtB5AhYS5WQj6UF9SFFSFKiJ1SFCyHwyGoyF1xy/SETCGz+jDdaEqBVHBZZZZ9YX7BC5Da9pSS6KyE/SGgyEKyEV2wAJBC5DXGRYS7qOIFSFIXyIN6jS6PSGSyGGyH28EPYEmq7kMH+N5O8FVSCxUFHgDxUFnN5Kq59YBWQbu0AgPIb+CHY6s2J3xIY7DOyHW5QsJAyLwubDOyH2nquyFWYD8ME5SFD3ak86zmwT8Hz8FGa4RyEERbF8F78G6a4tc7XGSZJwd8ESDapkZxrzX8HCOggDbPzrJyHX8Ff8GFc68pgv8H7eZDUHnc5xyGZyH18HltafvK0SGAEi3l5rdZF8Gf8EKMGlyFFyHRyFpyGPxhFyEJyFpyGpNTriR5yHSMGfDYNpwpyFSEjxl59yE5sYNyFcl4QDaFfA9yHBa7DyGbIgb8FT8EMza3NyH8EdyHZyG/NzEkRn8FP2waDZM4Hi8JryH5ME8UAj3Qzcwj8ExyHMrxUihrJypyGFc7QxAUYoHyHCDbit7l8G7iFG5KHyHFt4hSh/8FXyH7EqgCGnyEMzYvyHlpxACFhtDlIo27ajRLgCFHtAxni18HfSyPa5htCfvKXxzZKAvMEWyFE07kcpYCEsSHssEkZJ61pkCF+SEeSE5lZD9a8SFo8b9cEIKHmSEi9YUCFeCEWw4mgrYKEKCHwKHit6EKEqSFhSHjy7AxqkKEaSEnzZWDw2SHUKGUCEWw6JTrsSF6SFHkB9NySCHHUZOiEKSGXza0KF8CFkKEI848KGcCFXticKGeSEw87EjZuSHOSFHkACKGS0DuSGaSGXpAEKE+SFPMDIKHBiFJQChiHBSHhiFZSF/lAJoqRSFYJLRSFmCGP9KuCGW8DxSF5ECJSFAsHJlBMKFAERpSF7WgZSHBCEaKFXcF2sGk4Fb4BO7gwFyqvgttYET5djqqD5QviVtZuKFChYD4BQgjHl7gRBRVBwdYrQwTtbCXbJthoiJL96XooCMAyXZrWbviEuKFeKEBKFtfIRKGHvjxKHJma1ri+KEbtYIXa/Ahs85QbhHtZcXa3jSd96eKFILaT7b5KFL96VbiuKF4y4UqgH95lKHxKEBbA28S+KEKdbUXZTF6lKGGmCjdbUXal5gb4FLoobKCKXbNoSxKGGfB5Fyj4BZKEs4H2Z7kuB5XbtKFJKH/7wJXZpCGwSF7Xg1HhaXa1KF996r5C9gBOXbR+qZxxxKFFKHjCo7PZJKF+KFDLYVxCsK7NKHbKHdKErKFVKHJKFFKF0OJLSL7KENKEePaBKEs4GRwB2ITdKF4Iy3kEYHjF+L3KEi2DOD59KEW3Z8aDhjZw3is9z3KElKFUBDkGj3KHgQQb4GLKFaXZnKEmTRUBAHKGj4AB7SWD6FKEfKEiMDhKEQqF4daj4A26idD5JIwqgDdKH0oKoUHfKH4sAYqFjKFUBB99z+fYZPZNKFUBDvipwqHaxov97vKHdKHQqFJKFfeZqLYePYWyj84HA0rjXCAqG1AY0qGPqi/KGbKEkqFE5CqXafKE27ZKngf4wxsFRPYmJCWD7VKFFKGgo6g4zpKHlKFaqZpKFrKH4q7mT4Zp4/N6jN4UMHRUH4t52yGlAAOyFjN7HSbX5A8hLmDgLNraqGbKDa/QILoxarwqBmDwuzorcTscCe/yhyEx8HBq63EC//QwFxqKynkFyVqc5T68GpOCOqEFZ4+KFNJDTkFgLaZkAfbBwdaGqySUEYLaLFoIqH+qFF1LeqFdKLviEOqFjkFCGa+qGfJyRqFILY+qGJKFqlAHkGstC+EBs86eqFUUEzqabxaIMGHyTxqGr14USHpqFRqFPzJANBJqFuqFw9R1KHadCS8SBqEUL6wSFeZyK+KgrYQjK5Nio8Hshxt45RwZXA5n0G92gwLatqERqFjhTf5RVqFF/yoUFqQBsrDRXZHcrKVaIMGD2okdYI5ra0DdxxmWCyAB9qE1+T3cGuqGFqF5qG3kFxqFDLYGu6NqHZqHJqHmwaF3CbqEZqFn9KbsAW8E5qGdqHGdzFqEFqHxqHh/7gqG1qF6hqBqER2qsqFHqwf4w3qHJKH08HWJqfkDeqENcDBqHOeSFqH5iw7qElqFfqHu2T68GImBF1KBqHfqHhjaGqwiUHtyZ3qEBVycUEWxrOqFn0GzIpqLa1QblqGqBCwUHxxofqFs1iLkFMxqjqE4axa87AaGsNA1qF9qDuzy4aFdYFjqFgPC4aF99zTqGrWCzqEwaEeqGLqHxqHJZSQaG0aGdqEgaH08GUaGcXa3OCC+h9yxgPBkMFKqHWyEAt7O8FAt6u8FEt7u8FKq6K2an+JY6zNIGiaGbKA+pCZUHltoCbLiaHvkaRwBSaEE4QGEBWqHZT4iu5TW5jbhCLbM/4vkEr5ZjUTBNDA0g6aFKFh6aGLpyv6ZAu7izKnwJCLYCBBAaEhc76dgADhWNZNlZmaEpuTb3z6aElHCtyH5FDOnAuaGv6b+c7uaFwdYmaGkUGn2BIhSWaEGaFXyGB1TVWRaaHBaGFc6haGlmwINZeaFla48zoxaH+aEdOj6UGLpxHIytzauWDx0pBaHvDyxzYceoaERBaEpYQ+zaS9LOaGbfawUGRDYU5LVLZwMJyUFB+q5aH6aE96awzbpaHO1j6aHnsbXc5JaE5LYnLxec68OjxaE3z6JaE/jzRaFdaFXkFxdY5YjHLa3Tz98TzyE9aG3kEpaGVqGRdYWaEJaE6aHZOCV4gzaFpyEsRp2aETaHTVCjaEnxjpLbDaHQJBraGb5CoUFoVywQLbaHVaFL1Zyzpec7zf4NaHFaGzgCjaHT5QuLbaaGLaFjJDwjKeaFUUG7yHraHnLY3aFnyHahqyLavaFAu5BKx24wPaE6aHfaH2LaVUh/aE+aHlaFG5LAUG7yGVMjjaGZTwPqG7yFXaFBaHuvY6j5QKG+N5WyG5N42yEu8E2q7Et5gt4e8F/pwv6D38AsOg4Ipx6I4UDp8wmOxWFA46F7QSvooE6GrCB46GqaGZ0FvZ6X2DTMqmyFVnA9iEqRJqnAj4piIq4SGngQs6EMYr4ELj5zqNS9SEeQju/x1JwSvZPNTf4oKWDhZ6LoBM6Q3SHOXIfYCC6E21R86EqODS6FN0C86HcdZrYr4EIy6ES6HK6Hy6G7MEX86PfAgyGM6GD1wSRz30Fc6EK6Hd5w0oiipwq6HG6H2khscBC5BIoQtDaRpxt8S7SFfurzPb12ASkxHSEZU7PpbHqKJLZb9yVtaRpzq6GmyHPaRs5xtZANsSmyEQ6y7jbO6GOCQgyHhHL1Z5E8HsAIj4rroGRpzi6xsDZS6GMl7a6Ez6YM6Fs6F9JzQU5ra7m6HJ6FgRyp6FC5B66E55yHLKfLaeNyi6G81y56GG6Ga/je6Ew0CX6BDSHNoTDva0oAK5iCyFxfjphiF6Fd/CkyGV6E56ESpJra786FdlZYrYXUbMyH+6Gk5yMJjQ7Y2DwOCwI1yZ6Eu86eSS26HHTDRq4M6Fx6EN6EPlZp6Gq6Eh0Cy6HcdZJ6Fl6EG6HzSEpWyF6FrKyIyFT6G8pzBC6N0FTtAEEhXpZF6GIyFhdAgpj3pYq5DKdbZ6FlpYc6EKDa36HR5y/DoEyE9ezT6GaOhfSbW6En6HR5z26FoyEG6BAZZd6EO6Ge24bPZGZaz6Hf4py+LR5zl8g6MGsjzL6Gm0Dh6FL6EfYDcaHYWLKqEWAAxUGEt60MEY6H0MFOyFkUB2WCgPBVfBVpyXQFlVDtpQByGtpxF5DxjBokL4GE4GG0SxZN5FiHXcE/F7a9b7UEZgB8nBFSH6uQMGHl5Cxua7MFHsHy2SMGHsGGLA4d55wdZpLqZCFZZYA5BcGFsGFol5oWCk7Q27bqLrYl5vA4SGGDJz1LomMFFdoCijlxzyGG3l6pmCxubaDZmrpiGG5MasGEoPxFSGlMZQCGiGEwl6IhL1ShyGG3Tyj8HlhJDKKZJxKLpyl5b56WGHKGG6GEcGGwg7mAIPkE8GHR57LsTlpzWGEDCEeoy4NQuGEil6F7I6EDKJx4FAIGxdvZ055QtKMGHBGFMZzl+I6GFMGExCGaDAcxDcGFaGFxGFupyGGE+MFnSo1qb2GExGF4A45bKuSoJGGj8FhSrxnwZGGuGFE5DJxxGnC+GEwl4s6B3mYPkEOrjzPaeEZ99oPkEmRAH/bZGFLMAPkG6iII6HyqGE0H916QpTS/JypbgsFIGBl14M0GTV69GFJSErS79GHdGElgBiCGjGFP2J4FBcYIoKEbr75EgDGHSyC9GHI0Bx7LAHBP2KLGF2SFcKGqiG5rTS/LrGEeiFJ4w7GHgtjCKE0g7WordGELp7cCEQjKt4avkEsCEMKFkg77GFrGGHGFyiF3GGbKAUJDTLSyKFXE5oZ4DGGsUGqCFk5ZPGGcgBs+xHGF+iHzGGlwoWV59ArKKFJQBBSEYyAhSGijDDGGS5AX/bSYCRSEd04h0F6KGMz5xSE7cEGsF7cE3GEIRACebmdzA8D/GE5iGkRBBCEFiERiE0GH2KE/F7WE4JiAZMGHMEVE4UmETMGHMEg5yEQL3pw7MFmE4nybZdYjMHyQD0mF0pCMmEfLwwl7kmGeMG0mF6MF4ZyiLDgxA2MGTMGTs53CR7zK0mHhfjhZ67eA76CwJxMmFY1zCmGUmEVMEKmE0mGnMGl8EymGA3BLMEVMGHk4ZawaMEgbwJMFblDqOT+MEbME+MG7eDpzpRMHcmHqmFf/B/Fi6MFzyEnzC6kKtMGWmG7MEdk42EAhW7/IxdvaQ+BU3QHMHumFCZwAjQiMEpME7p6/myUmGEMDq5xjsycmEHMGs2zmD7qobGmEq8CD95A0zlpzymHNZws+SXxyJmHc8x8mGiMGJoAMZ5DJoRmGqHxrFxGmEHMEhmHz966mHaDYpME2D4KfIlmEmmGMl5XWBBmEHMHamGKJwnDy5MGVmF7D6FCzgqEBmGKJzxmGZJyW5zgCGKJzRmG0mHW5h+R51/6uMFTtxtGGXu4KqEMc5trCBMFcsFfMGYKETmGUsEoQgbGEiKFQ06zmGgsFGpz0CHYHZyDxQsGq5oLmFRVbjYCTmE+wBIsHECFVZx7mGIsHGiHkKGpx4mczHmHosGa0H26B87S4sEHmFvGHEx5YU5xHoCsHC+aHmHGCj0sGvmEPmHnmG3mFEsH3mE3mEm7SgsEtY4AmG/R4/mFQsGCsGHmGgWFcsFisHAWFaNC7mGHtyn8DzmH+SHasEhiEQmHQyBQmFuTB4KGwWHGCjqsFl87wyhxiHDoAuCGJiFuCFomEeCEYmGYWEIRBPmHHlwvmHu/z4mGgeCEmEDDCmKEkmFhCHBq7Un5mwEBUF7CQWjYBsDKYjuUFEpDS6HUn6ALqxdbeiZqvh+jZhNDHkFeoRW5ZUSBLEBCUHiWHGjaUMAFsQ8WEcWG2jYs9z92Tg1JqvjxjbKWEXwivFJqWFejYuIjQUG8WHCDZnABqgZqUH6WG2jaJXBNihQl76pCq6ETAAY0i/l6WWF8WFajYYygWWGMmz9VDxjaSyaFJife6L2iuWEbyxqWi8UFq3A0NYA47yWHP1BtcZeWG6WHWl7iNDYPAhWFGHqel75UjMJReWG73CKl4EsrRwJeWGjij4UFlcBeWE8hzvkEvNL2WFmWG3ASqWHc6EYjYAkROWGKWFUjaT0iKUF2WEKjY7K7sUE9EFjo6sjZfjwyl7VWGFu5d95SWGYl7qNCVtZf96iJo8WFUAIK64rK4+WHjhoTEIsjY9WGhUFXMTeDahn7uWHDVIdJhUjYV+zSWFpWEojaX/D6UFOVLaWHoMCyzgmUFZWEVWHWHYWUFvaxUjYuFo8WEagTDDZ/YFikhFWGLWGaUa9WHlWH/9bpOIqWELWH4EKIGG9N68aGUMH8aHUMGCaHoGHCaHjN4SlArWRPRYqtJzw7iZLxMAn8L9szsK6C5CPZCs0qfWE3MB2KrUGEZ0HFiE2qEDT6/DoTZxxazxLbVuj6UH61Aw2F4LYlQqu4gmdIw2HRLZzjLZdZHCRBsHILZjRLwNxUPhZsFmVrB4j4FYtjgxsERCFQ2Hzpz4DbgLYXFKCJwE/hScHgLZ6SyEZzvUy7sG8pjk2EVIFZsEs2FE2EI2FZsEaBBY3plJzm4iNsGWXxij74FZvLRcLaC2FyMFs2G0cFYWDESFc2G7sFi2HaDYOCSdsFcEFR1JXxz82GHsHpDaqZzqih+XZlWoTiFE8yAcB4LY2RpC2ES2FuLbub5pKEK2EOdZdsFUkHQ2FZsG/NwaoAq2Fo2FOTprExSZz42G7sHzybw2EWrC3sEjqC17C7pwpCyso5OTo7OLy2F6qA+GgkLYG2Hi2EQ0b/46e2GXiFY2FoI5OTpw2He2HCsArsEKJabmLC2E1sFJS6W2HJ2GpI7QDoM2FN5yEdzS3YOoAuK725xZcCc1YFToNcJW2G7sGPTrQcF22FZsFWJ6M2F2bC0cGvRB9iFG2H8LZ1sjeRzp2Hm2Gf9p7dyl2FuLZIAbTsiV2GwcEpEJwdYy2Fd2FzmS6xgq2GM8xcLaQVxJ2GsP7DsHTKD52FZ5bIggWXYz2EN2Fh2EEcF/kxO2FuzzR2HzEEgShlJzx2GJsGN/am2Ga/gp2Hd2F/0Fm2EDl5p0oN2FM2GscF40pg5wqn5t2HaWw92GN2E/sGP0z32HO2GscFQzYD2Ev2H8LYev4j2FBQEe2HxUyeCBZ5aa2GP2HQhr3JyB2F7DZi0az2G3sSbFaP2GO2FYpzuxaf2HD2HKLZQQiU2GIhKEZAD2EH2GK2F32HH2HoOFt2Fuz4wFyD2F8cH92EMpwf2EkLbQAhb2Gj2Ee2FdzBL2GowQXG6yaEG5plJw50Th2GVMCs2FN8bfsGyaEQOESAQAcFudr0UL4FydsAkOGEOGd2EEOG42ECOF8OFZ2E8OGgcGmkod2HoZwfYATqHT55w5gQZxVDwTXayOFcQz35ZjlTmLYGkrP2HUOFPsGIcRTsHkOGUcECeY+Dh82GI2HZkaABAgpzEOEBkYGOGo2FZsE9oGm2HTDBUSp2cGsTJuRiWOG7sGRPQSqH4OHeqEj+yG2EX2GdqGugK22GN2HuOHz0rgqEP2HU1qacKGOG+sEDeLnihZ5bVIj1qFiO7hjZNf5pY6HVpp2FocQ3UjucH1oFcY7ceoRcE82L0CHpOF/MGUkHbmFhcGxcHjtLqrxpcHhcF/MHdSx5OFJcEy5w5OGvnz9cHpcEZOHAUBDGGMWE5cEMUB1OHVOFpcE9cE+YCtOFfmEpT6HcGlOFD8E1OENqHLuLlOE5cHGQAtOEcKFtOEjOFVOEcfowWGNcETOH+FKBobjOHEialOFgbjTOGS5DjcETWQ9xyUzjTcHxiEqKGoWHkiDoWFcLADhCLmHYtCFUArcFa5xImEBSGxSER0EkWEJSFkWEwmGzRA9OH+pKISG0WFsWD0WGI9CsCFhyE65buZY8IrsWHaWF/pYJjw/OFWWF/OHY6iHWH5WFO5yK4RhWGUWZW5aW5y8HCYl4yWHR87bJ6JLaXWF8WFguGtKQKWG/OE1J56LZCWGAuEIuF6WGKWGS85xBr30FIuFob75BiAUEmWGUb5B4jvkGnWGUb4vIT1WHOWGMo4Yk7NhqkuEnWRM8EVMgMzROWEfnjn87plAdyZBWF2iaUb4CHhbkEPxSz5b6k5KKzRWEcfrd5YMuEFgQ61KAcBlc4Wk7YgEKWEUgDkuGP45ouGAuEEuEUUGrWHR84Ee6N0FYuHIuEBQRsuFaWGAuGM7JS7ZJ1J6jr4b4ylK6PBBWEmuEi86UKgtWE0bzN86RYiSuGLAYC6FysC7khDWGS9SC8G6uHQ7YtVKZzZWuElJgJWFnmT0uFgGzC6FOVIKuFysAUYjzWHquFWuG6gIrWFkuHK86OCobWEzWEsNB0oYBUG7WGS848MAqHgguHIuH72wOuFUuH/MG9Ui07bGuEt6H/MFJiSCWENWH4b5cYo6MG91JtWH7E4wuGdWG49Kc85ZuHF7Z9WERWH/MG+uHGWFBnx+5bVuE3y47WETWH/ME0uHyuFluHwy6CWERuH/MEkuHKuE6uGfvBauGbWFysB8moVuHkBYjADXWHiq63WEqqFUMFqqFzAAaqEjOrGoCPTTvWGdsyq0AFVLfWE3eRm8Eb4oA2EqtK7uGNBLHuEgXDR8FqaEuQ4GmDHsg6MGaGFTyHwMA26jdxwpGHCDZeVAmGGFGFol4GmB9CqBGFMOSIl6nFbvuFlGExyGPuG1UGMGH6gxK846npPuHKGEsGEXl58lYo0hQeHECrrkFtZC1CG5GFAeGE1ggeH3uGoeEYfjwCEvuFTFZIeHd8E4eE/Fah0CsGGU0R5a4YWDCvqSGEOGEzkH5aq10iAeGDkFEeEGGEkeFyFaNlZO7iNJwEeFkeH8BBczDhGHXCH6g5UnhrJxBGHwV5eg6rjqpgIoeGDkERlTCeE4eHjkHMhA0eESeEhg5bzyXxxsGEoV4hg63uHPuGk6xiSiSeEHmhqSD1GGY0HqeH3iCSGG/uHy8Ga066eFyGHzMp6bDqeHhVKMGHvBJbFaCSzoeHOeSfSGyeH0oLyeET9ajFZ4hDSeGUeFOg4ceFlMEYeGvuEiMKaeFeeHSg4htzm3AieEzkGthqQ0FBeGHkFSeFn1wyeE506lGHl5DVGGMlb9upXJwUrogKFJVDR+qseEUcgjmEE0E5lZ6Y6fGFSfhrmHZeHdGEHqYrOEMc75eFTGHjGGYKEleGbKDTGEJcFnmF6j4in4LGEPGFelYCRQHGGfmE1eGXqCsbqrGHPGENeEEUCH7rmdydeEteGYmFSY7WHq9eGcgBnGHwKFLzqXGHl5CWSFdOFteFdZj1eH9eF8BA9eELGHGdhDOGIu6LeHdGGSwhrmFreFTGH/GGzGHr+BJLarGFzGCFeFbOEEWEoWE+0HqKGHOF/lDjeHDyicgAzGhnTjImHh0FJiFapY3OGpiEDeEO5BDeGZiH9gB4mEWsFZECZSEXeF2KHMWEps6Q5oY4jNKGbVRadYcOhOrwg+EqX79tbg+GOOG1HRQ+FdtbRZTz145EA78Artb+PLy2Gx2LOSAI+FDXzZKHyJwIMibtZqe4yqG4+HIMGI+Gm2EERB4+HJupovTQNyg+G2VyYcBQayd95E+FadZtToUSFw+Hk+GZsD/2Es+HIMEiNyEZzJXRtMg04ET5KY2ExMAiZ7JJ4RFIDpwKQDbywiJxyUAEdgMpykewX0Gc0SU+GT4CVbo84E+Ly5iTNKFA5hP0HrKDOkwD4CNkQkdaK4H6DwD4CQhA04ERmCrKEM+H9tZM+GPKEm+GG4Fo+Ebpxk+HIMGn4Ts+E2+FadYqDKBOE8+HwZ4pTzJWTS+EgTRyZ7lTx0+HQNxpzwcdYVESDJbQNypjL9tYB+FfKHDKSYZze+G1HzNKHpBDzT7tTwROEc/QXZwpTwOc6Q+Hk+Ft9b6UE1BBQ+EO4ED/LOD5pBCJ+EDwSa+EKLhQQ6Gv4SqErTgNvRDT7KtJYqHzACc8Jm4H8+GhJwY+EX0EajA2mH4TiewBm4FuCjw2GKjg9f5m4GEZDO+Ed6LSzblTwXBii+EJWIN+E4oLM+H1+Eh+FSOph+EtQJRqBV0GHXzTKEm+Gl0Ga6yqD4W+E2DxDuy54Hz+Er+HwN564DU+Gl0H5/QD2GC+E4MFQcxR+GHmDi+EL+E+Pi++EtowpOEWT7ngCO8F8aG2yFoGH2yF0MGOyHjN435blBKidAetyiyA5ZAamq0wGv+Ee0jYXyikA6cAIMig2ElUG0GEps4vDDtpQ8WH0UGZdYtxJDuHNDBjkEgoJKGHMUFUUH/WJjoROWFrkH9tZfgrvoyrkGSUH6db81gCuGQBHIBG9LQGUFadYWtAoBGIBFjkEdI6IcgIUH0UFdtaIsDtUFEBEFT5XgwUUGXkHrT4L5jDEhkBEsBEpjS0uHdt4tDb41DrpCKl5AUE4MG0/BcGHgUEPqG/rq1lioBEiUFiBG2DhBWE4aG0fzCBHCizlj5odZKbLGWHC2bv0FoPiceGWUGzqHoxZhGGmUEsBGMBFtuFeqFEfp8UbsBH9tY1ZYzyEfkGmBFOOSUFC8UGcUGyfrd8EcUF2dDvtZqe7r8HCUGwUGktb3EBYBFAaH3nrCBGyUG/ZzeBHmBE9wT1mBOBHKBE8WGeMLQdY7WKYBGaBHMpx2BHhuGwBFadZNiqgCG6BEFT7LLzxuGhjxoda7QgBUFhBHHtYhBH0BFOBEZBEQBGGBGKBhweG5BEIQHFBEWBEXtY0WKEBHeiZ1qEVBH6BFOWHwm4cdYk2BrGKfe6JeiX+FjmHX+HI6EnN6o6ECaHo6HPWHdIgcEygMCC0xswhJ2DfrpDohlQCFUHJELkAyDBFFUGXuE06E3cHYJA1PxPyFTFYlw6ceEr8FX1ZhXSryFLBG9V6L8gzyH58HsmGA15FsR58FLyErV6LBHFyH6MG27anBHPISEl5JLZYpjgKFXBG1yFz7Z+IBbBEXBFtHDPBHeEBJvBAKF3yHro7pOKLyFfBEgDZpXa58Fn8Gb8GuNbuRZZrBLBFX1bCJCSASTyExyEAhEXyGT8FDyFEXbhFifBH5yFX1b3JjdyHm3Lla7SY5LsjYSHn8HSb7xPbhFjVyH5yFFo4xQhghGnyG+o4khHZdZfyH4hHboALiF/BFX1YucKvBFvyGBo7uRAASEtyH/BG9DaEBFMhHTo5L8HQhHro7VG5X4RgCFqeGBo4iTDVyFmnygy78ZA0hHX8F7fgZeEecGlg7HTDYKFoCGYKHyhHsSHIKHTeGUBDKhGCSEYKHwKEahFkCFCSFFeHNi7onTqSFTeG69AB8K8KH0KHkWFSY7xPZUKHGhHi9BZyp0KE2hEWhHFeEbpjMKFjOGayBFwTsKGbOFqhHzy52hFmhEOhFWtY+hGCKFsei7eFCY4BhHSKESKG69ChhF+CHoBD6hGXpBl5z2JTmYBKKFmCE7OFneEbuCFiF7xCoNb2CGS0COCH4WGNICEWGomHJiHomEveGOhFKlBEXZr8QOYD+CHfeENkC/eHvOHWqEps4W46jiqz7avaHG44fHwfaERaHNhHWLQuLaA6H+KGoZqEBE71ZNlbCXZVoCqMpBaHSXjAlAyXbciANhLhaGuaEW3Y9hG+aFNhHE/b+XC+aFdhHThHtNDSBF+aFXkFlfalzyThFeaEbhFYcRBaFThERfZzDSZxxrhFFKEEspwhQINapaERfZQsobaGg6FP46vRCKoDkLZQ6HvtARfYTpJs87naEW3YVcyrhEVaGEqF3hEzyEvz6u0AJfZXhEvaHtlYTqEqNZnhES9BUaFBNbs+xbhGOqHr1abhG/aH+KEwTA1eSZaHlppe3ZvlIChEraEtDZYCALhEg6H7hFYCD3Bw5LZLhFOfYO9Lr8EYRH944fFJghHzfYjaFYCAWGS7aEzzDUhRERE0REPhGl/4JXbkRHXhESwQW3Z3MwzMjwREcRHMXq/hGfaHz8BwRF9aFFKEq6HWBFCREW3ZUPjoZjhaFyzrCXbN3jd8FWCDEjgyRHERGELZpz6KBET8CARFBaFHIyEqHq+CJCh5aH7aFqRFKoJDaHogqbXYytacvbnhGVqET8AthGdhFthET8DYRF7hHbhHz767hFmRGraET8CLSw27aURFbaEuRE5myz1bXQbJ47ZbaaeFvhGKRGuRGGRHdKgnfZSfiORG11Y6whe3Ynwy9hGtSZc2qKRGWREaRHuvaEXaTNxgRFfhFRRFKRHBRHAsr947aREURGgLxE5ALuF/N5LuEoGGqqH3+HqqGP+GaqH7xDVUSU6G0eCVREgJiz1YDWZ14AKKKFCBk6ELOqf4BVRF2iBU6GzBHg2Eiu7eizfCHNCGLI4wlxxCEpCH7C6UaGfJhQiFTiyJhwegAZCF/uEzqFjRHjCHWSzfCGFCFK87bKyLRFiUGp5ZeZytBjCADTUG1yEVqHbUH9RE4ax9RHtCEHRFDRG7CFL0GVoyVUHdCH7C5ugBDCH9CGkeGgJxDCHNCH7C4EOCQ0Hw0GaJDsAjkcGnNxyFY0mxKGEvUEVGyWDC5sHceF/JDE2CiOAbCHSb5gZzEiG0iEal5fmzQgKMiFGcSLI6+IAcxCvRE6o5JoxbRHzRGS97pGGnCFwxH7WyrRHLCEaDa7DDoYqUiGVl45WxPCEMeAMV7YxFDRHZVjbI5DDwtQh1CGfuH4xFPCHNCFfB4WWRuiFahEUeDMxG60F8iGteFEeDsxFG0FM0HssFCI7qiHxcEreHmN5Z+A2iFLGG1lD44BixHCxEMc7FTCCxEtcHao6U0G60HyxF3OEw84+pCGiHHcHXmHnrbInQnAB1cHSxGqxGKxFG0HyxHgC6s0EOiEm0FehHpi4mxG9cGfILwKG1qE80HDcHBhHX+DynY04iTcFBiFJhHgmEphGNBBphGOxHInTXeGrcFNahOCEneH6KFEWGGKHXOHGKG3OGNOFrpBqxEfeGJ0FWKHJdCHlC4zADeEfOHgnbDhDIeF+eGFnaf+z6UFseFMxxZoTGeGZGGFnb/izZdYCGF/uHZxE8GLweGuGEplAZxHPuEmeFK86PRypxHQeEonaXBCwlrweGk7SyWGe6h6+FpxHDnaVxEfuFTyG1xH4eFmGExyHynYzugqeGZGGajbtxrr8GeGGkeESK6eoy5xE8GGOnaPuiEBEyeFTxGYBETxFyFbsK4KQZlxFgl7KlBqXoZGERGFDH62Spzpz8eE1a4SlAyNh3uFueHHxFq/DDxGzxHnxHoeH1xG2jZIUDLxG3xGajb3xHjxFnxHUlDTxEbxFjyHDMDvxFheHUn4nxFVxEjxGsWGlKh8eGvxHr76/8GLxE0whuprweFxeHxjZMgEMeGmEL+WFuaw3xHaho0ODdh640Q5eH9XrwKEIRbDeH9gBHeHmxHOWBYJGfGFleGYJFoJFjGGwYIxhFr67ylxzeHUsFCMDnCRUJENOFMsFVjaS4R0JFrmEa0EdeGkUBdeGveEw87sK5sJH9gCjeF9h6zWQjeHmhEqxFLmH5xrMJEzmGiJE7GHLeHkJEwn4SJHbeEyoziJF/FTreHCiFdOFWMDX04BiE4JGvmFgmHe0HJMD7OEDLDCJF85COa6+xEhg5tWw5hGUwB5hFXOEFhGkWFFhH6JH2BDcJEfeHWUHTHLPOEbBCvOF6rAwmFJxHb/aCUCHRG7CEISHQoAFCHDRFN0AeogsQBwiEkYCTRGvsGCGEBJFJCE7CFiGGeJFDRHEmKCmHi6GrRFlCH66GfXAWcFVCGqGEzlznRG0xE8mEj+xNCHtCGF5yrRHeJEZJG1CHzCG08HvRGlCE2GGlJEPRH+JFE8EJ/g8cF5JGVJF9CGHUEcZYw0BOYDvCH1CEZ6FR/oAxFZMHl1zAxGsACgxFMZxPIBQ/pTRGdUE3VxJpY0iHPCF5l4bpapsYHUFqrioTYvpYQxEY0GPa7ppYLJG7FyVl5TJEwxFXCHdJGeNTo0EzGhwxEA0BDJFRJE8mErbw+HiHJGl8FoZb/CGwxFNMG1NA4xF0iEapwExGrJHbEDZlz3JFE/ApED9parRGzJExpYltIzcwTJFIPam0AoxFhJGjMH7JF2YBI0EjJF36GBJGlCHjUHrJEUiG3RHNJFZZCg0EEiGfCHLJF99rYiGsyFQpFYiFoiHH14bpbjJFgiFApHfwJZJFnJHHJHmALBJFUiIYxE4pFoZaHRGAiFPJEMxGBqyopF3JEkxEfCHMZYMuh+JGfRGoZYkpHfJFpJHRE6EpEWcjTRHyQCvR4VOA80F8SH26D8pFU0GcxGcJFyc7CpFiiHKJFCpFKWRCiEClgOxFHE5Rp5yxG6iGGZa/NxSxHSJGpx6q0BKpG2iF7E5v8oyiH0JGhcGiSHW3ZeiGaxEqU6WkQ6xHmiF4JGkNC6pFKxHKpE6pEWPJU0FaCHypFbE4X87qxEbQDuiH6SHWpFGiHGlROpHPhCKpHqJHu0FIWEbcHJhE6JHneE1eGi0Ckb6+xHB0F3eEXOFBxH5hFPeFhxHWJERxGwmHO6GFaRZiFJ0HWKFEmG2KFMWGJb4liHcdrgGTcRHNiE2nAr+gFpGeiDvgjFpHHhH1iFWqjTaF9hFAaHTiE/qTDhEOaHFz46ESvhFNhHFz7kpKzhFthFtpFr5g4RFeaFNpETao9pFUUHbiHayhARH7hFDpFhaELaFjiGDTwSUwTpE3iHEcRORG26E96A+XDXhFZaE31w+dCHaGPhFDz7wx5FaF5REXaHjpzNpEg6GaRFgFw9uj3aF/hGKBF7pFLpFARFNaFYNxZUhzpHgRF5z5TpFHhGtpGbfbjpFiRFfiGq2Lq+hRNYoRF75xfoi9aFZUiVqGP77dpF2RGnkGlpz1mDzaEVpF75xoeaGRHlpoLpFHJAZaGfpEjaEH1zAtpMRE+RFr77HpG0RHMRF75y/2BnaE7pFjiHPsxScQlpHEH6HaGfaFVpyB7DJaEWLzXz5zLC3pHEZFN758QDgDaLpGzqHflz4ZGJz496bnPZZEYnpEbpCe4QFRHIGGoGE0MEP+EYGFP+HabALPYg0odRE1RFCZG+VLENaS3CFPYpDTVRGSZFtRHiZEtRHU6HdREuQ5BjabbrXaFthHWrZ/4RqZH7hEaZFdVRAZFXkFUSCwPQg6EjhGua5iTBe8QNpGhqGk45IujQRFjkEGZGy/TWZERw5yLB2ZEzpGWZGJLYVpHNY72iD30FiRGg47/UjnLaERHh+635Z6ZERa4vnIERG34SraGKjaNMi+ZE3hG0+6/PTQ7ZoVwjhFu+6kxSuZE4ZFIN5WZHP1aRREha6VjjkLYqRE1Qgha4RZFSRG/ag+JzeQBNN6NaEyyAJ+4Hdj7LZNhFajY+ZH2ZEwRagwpwZI1ZGeY6HCxuRGfaG6MDlZENZGtZEBZEzpGv950+iZaHdKjRZHInKoLYbpEJZFNZGGRHw6HobZmfxr0HgZFqD71ZFdZFpeBOZFiRFcZFFRE8ZGPWF8ZF9BF+eBJWR2+C46E1RGqeAsGL1RGDDpza6bZEtRGJewbZH9pCdRGhCE5pEsWFl/i5JGnRFXZF+JHtJFUBCVgFBJH7RGgyChJE8pFKDa+qA5CFHRG3ZFtCFxJF6DaXQxDRFJJHcz6PEypJFrRFKDZFiTFJHPZFuHjXZGfuH/ZF3ZEw5Hg5FdCHDRE5EBlJHTCGkeFNkAo5GPRED4D5yrHJCvRHo5E3RFNJHga5hXQ/RGXRFb+H/RH9JH55ak1jrCG/UHSb7PuAXJG45HVPxjCFHREtbR4pGYxFNMGEioIiGbJErCFiirTJGLJGvJHI1wrJEnczy8Hv1wLJGuWA4iHc5EbJEYpHga6UqCTDiRnYfxyEirApFTRH7RG1yonJHjRG05GkpGPkEU5GmgjLUGS5H55Yd5hqSAopH5q565HvCG/ZGa5GqOjMpHjUHa8p05GgpGa5H9t7cpGQYAvCHy5Es5H25F5l5iirjJHW5Hi5HQpGg5Ga5F4vrG5HYl5Ny5igKCxGCpEI86ugK8iG2pHFhG484h5FCiEnVq3DBmdyypHVeFipEk84zdZqpHwKFTDTJ5GWpHPDDFgp6pFrmHqbhp5FcxF2z5VXR2xGnmE5FbRZTmpFF5Hh5Fr67R3pZ5GYKE55EOpHhhEJ5Hjy415GW0F9cGYJGV5FDcHeiEqJGysBJ5E2eQBpHHeG5hGneEhpGphHEmHphGNCKRpGxiExSGxpEWJHxpEtkAmKEMJF7eGhTjRxHDcFOJGDkAuJEJxEWhHuJGZZYMvgt7b8Jyz4J4RYK4xF0H66gd0Hh/hICy50HM/5j0E7ngI8ErRHbXjkbYdRwHRHN0HeBDD0GIMGVFhjG78Uo10Hb5El0Hn5Gv5Gn5FjG7veBX0HadCgMHOzhAMH/0E75EAFHMqJn0FP5H8bawWKoMFf5EQFF0maU8G9FBt16EQ4RejPqF7Ip55aE3TC8EM8GcXLTdaGhTlpz+qEXl7wqAP5GxqzTnJhdaKjjoFH1xQdxCIFF04AsaH4FDVZ64cCf0GpOAXVycvQIMFAFHv5Ej3q7cDMFFj0G1HRVKxYMHDhTEFG6mRsFGPZ4IFE67QX5HQFGEQ6HaYAaHA0gd0HnKA35ECFHwZ7nKCUFH48H5H4alYAGDoFFV1CSECvg6Uuis8EPgYHp5yFEv0ECRRgQ4koA9OqP5E75HKFEQMEH5Eym4O8GdBG4t7LuH3WGruGogDruGRN4IRZMMEzzBVXjPUSMoB4zzQMS8QyioD1RSQ0ROFHBt5R8HnZHGY6x8GsqB4eYklJak7BFH9YhZ5bJCipMEn1iQSHL6xhFFU6IV2E75ZBsET3azVjLpxj8SViHhFF4OErmxYDZ6PYhFHQwj4Da/oBXq7yOF/0bRFG1j412GzIqMl4FSB5FFUwRhFGvLR4OEicSVFFlFHe2EVFGlFG+vC3kEoiSyDaFFEaVazZzpFHf8EEjTKOFG5ZhFGNCHM+G+ID7iEalzFlrNFFRFHSTYjFLi2HA+z1DZc7AaTKIOFzFF62HiCE205sJzGQgFFGXMIVbDN5ZTiFbFG0DZxFEZFG3Pz7FENFELjYyZQgOG9FHRFFm3zbxihFEZFFXFH+OCRFFhFGZMREDYHFGVFFPFE6MGDFFbiEfCzPFE1FEZFEonxtFo3FHf8HrsrGHQAlELjZAlFudYfFGVFGZwCdgr0OFEuyrja26xFMH5sRxjba/bRpawOHQ/xtBEdGFy1Cwdw5OH6DhiCEd+B1OHpth6xHBk54lGlOHTmHECHElGFOEi3jp5EPVCBM6jOGehHD/Z2lyTOF0lH15Gpx47eQZcFSWCdOHo1C6eqMlH6pFdcF6A4/7wZOETRLcCGlIKDOHqpHbt5G5TclFiCHilFP2Lec6ElFXE5SlET2Je3jECHylH0eKylGoWAZzbrOG5OGBpHbOHuxED5GexFD5EIRANPCnOHdWTRpHIWET5GPeGSI7PeHs7Dl5HlFBivxHcHGRLppFxxH5iEMWGz5Fg2EgBEuQ4QJxij5Mxw4rA9dZVHJ/sE76gcDZK2Iy8JelGoDaZSY4NpOxwmAg0+ES3RimigYHelGZdZYqBBJGOUpYDbyFCelGW5qpDa6AJR1JqxypsHLjYDUzBlH7T6udB/sHMOioDbJlF+lF30hFlFJpw5lH+lH1tZhFiycEtWiyDYGvxAa51CHelE0BG92Ag5HpqoFT5Q0yRnBnRyIL5OBFW7AxlHUj7TpaGeq5sGzQCAdaFUAgw4QnbDlFgdbB27wcGplEX0FubqRsEzlE0+HNtYFlGllEJJ5TlFTCGFlGrlFXjLTlErlFg+H5lEJlE7lE0+Gd2hLsH6B5DT6ztbwcEblFadbF1wmcEXlErtbqv5OsEnlH4+GTmrAcEm7SZFxCdbbsEt/A+D5vlGDsHfroNpYqdbB4irRxaxh8dZxdLzlEygwxY4scBUC6lCHdlHT+4lbylCF7m74+Er5gkiERlH4+FDaBtCHqOR9+FHlGXCHdiyb956VpzsHYmh7DbkNpEcGLUqdT7B5zMcHohKtT62eowVF9lEJJ7VG7nsGVlErtZTXahsHpz5Pxyu1bT2q+lAQ8yG+HVkp1CFa0A04Gl2AWcE3lE04Hn4haQi5lGM+FblHrlFKuLs4HLIz1sFDJo6+FExrHlGvOLZw5Ebzw9jxsH4jw84FHrrtizhlEWQDs4FTWjvCG3pQcdYXdKEVFFAjLJ5ABrblHNkI8BFWqjWcFUVEiVG8VGoxEHlEcVFQ2GDxErDYsVFVsFEVE1W5+t6cVHCVGm+FYEzqVE3lGG4Em6bGgAeVFm4F+VE7CGxlGzzzeRzynYNL58db6uQGVG6VES+GsCjqVFYVEyhGpOGaw50pLPmFupGsxF0q73agIsE95FUlHeIApVFZVF8xH8pYKxqSpFypE5VFnoCWG5ZVFGxEvT4+dAVVFh5E2JGVK6+Jo1VHapGgp7xfTNcG1VFJpGvEG5a5t5EmpHMcB0nhmiFl5F1VGfT7PKatVFNVHMcBDVGmxGvGF55GTGBwB5ZVHupH3cAtVFt5HepEd5HwkDlVH/OQ95FaJEWCFqKGD5FZpF7xCetzqsFRpEBxF95FmlHEWGWJGWlGSI4DVFQkGdVEJ0GL5GVhGVUDVhGJxG1hHXuE1z4VUH4pHro7oZJw5FjyHgRFjRH7RF0Y5FQrDJGC5H/BEnLxzRFHRFPVGxJHSGFWNbPVHbRHv1Z0RGVCGg5HQNaz/bPlGnRFWfba5HA1H0GzvVEwhF/pGI5H3ZHv8AnUHlJEIhHjEJ3UGY5GEFyXUGnJHro741FTCEwpGuNY8gTE5FI5GtpweyxdJFc5H7kB5lQgxHU5F6DYytZwFok1E/1bveD0pGI1FyBKwiHO5GFu7Zpxh0A2VGkiHktY5iiYVH/VE0tYQ1EcpGc1EgbD65FLRHStZc1H65Gi5GsyHwYAQ1E65GMtaj+AAiHGl7etZC1EvVGotZVVKoiHA1Htb6g0FgiE7Nbs1G+lBj0BJNavMGwC4LQQsxFciGIC621EcxFtVEulFOb6O1G8xFSpHWWBkVCupFCxGilFWb7NyhV5HwKGnNbe1HKxHtVEw85kUDB1Fh5FWtY8xGKiFNVEDVHs9BmTyF5HdVEGtYEgp9VEmpFx1FMY7R1EaiHixHZtaZ1HG0ETVHMlG1eG51GzVG69C51H2xFLVHeb4x+jd5FTcHrVGqKGQmGhpEF1HDsD1uJB0Fj5H3eG6sHHVFT5GPQAz5EGpHphFN1bx0FppGxxFurC3VE2KF/eHZpGBFEsWELJDLxFnxET1HjxH9xHCDal95EwzdxExyHFrCbdKfJxFxH7BHz1F+oi0eEio7jqwvxE/7jnBE7I4AeEqGHrRGcIqORgPkEtxEgDY3JCYZQzxF0xHeaST1F5xEXOyH1Gz1HbI7zAClxFb1EHVYVkAiGGMeEGpwG+wUphWGGUeHv1EVKTWBESeE/1Gf1F/2h5a6EpDNhofxExa66nB1cI7xHXCEpDBZvqOeEMOw1W4bb7NBFGLqJv5q1aUnqceHoNFZ9Jzb54IyseFueEEHbfUFb1Fk1YBGGL1Gpa4ejL4eGENE7XxVpbkNFea6CFqQJFheFkt52GEkNH9eBGeFQJEo0GvVZ+WTYeHvTyvJHgfYOeHweGtGHolGqm45NjoJGByjssFLiA8JGDGGqlGVK6SNGEJGISESNGiNGkJEzGGlVGiSA1AxiJH8xF6NTNeHUJGTVFBaDyRxSNG7GH8xFi+EaNGqNFYIDM+zYJFXGH0CHEeCa9K8JFCJGh1FcY40c4WNGGNEUeDGNGSJESO4+pEONGuNFyJH06JGNGEAxKJHR5FhpF4SDqNHAmFHeE11G7OEIwC6JGAuD6lGS5DWNEafKVeG3eEHVFmJGXOHmlEpiFWlHnVF4SB3tj2JFhQCOJE3VFusB3VFr5EPVFAk5muKqmGJmHFNHpmGlmE7/a0biMmFNmGP/bJtia+FsmGpMF9OB/9S0mHKmHFGFcHIimFqeqCmEqCHlNGimF4A5LyqVki285SmGNNHkTSXiGlNHsvDlNE1NHUA4lNFOmF9NENTSjNEzNFYA7e9R6mHLMG2FzsYY2mFMmGLNG0+ZpKFtmFrNHLNFwmocZbxjJmoZPMF0mE/UCNvjemHla4BjAFjxzpx5ME1a6XNGDSidmEzNGP/aXUr/2E7NGspRE2F4C6G7JPNEKDzLNHB7I1GEjuqwSECNAJDR//b/NGsmHQyZGyEbtL5mEyb7g7BkA5vNE2MHtrpB17PNGZxylNGv8IJmGTNHUZqB+EZmGPpwdDI1mFQtGJfhfNHm/6N0EBC7deicA4mxzcbi0mECTLAtEv8yuMG/NEsA75iwYtEfNF7JE2QZMihqmG7MFgxCQtGlNFO5D+mFNmFYA6EDatmFotG8tG5MGPNF9CAEEQROFdmFqeHCtFgjhxMGKqxLJEfGA4tE0C6ICHW1H55AisFysBh7bECE2bqXmEysEyNHbt7qtGUsGrmHcCE6tErmH36y+1FYGBVsCXmFssFQxDzVFSaF/mEF1GW6B1DJmtHWtF9GGEtR3mH9VH2NFXE4iTKUsEMsHnGFHJAfmE6NE2tEHr5OtG/mFl5HLGEBtFQsFAWEeNFutEhtFQWHPcLnGGRtHUWE8lG4CFaNCmtHwWHFUCIWG95FJNHBpHzcFbVEj1FaNDfWEtyqn8CasGmJHTQDmJEpNGFhFpNGutGoWDutGmsHQWFL5EnLB5NHD1E1hFXuEem6C1HMOEEESLm7NtGc2EWrCesGnNY+Dhg5yRSRFKGrgyxFHNL7wDZk3Y9tF82GxlET8Ddqzw2FO/himAyXb0ZSc2HHL4rsGLoCn0CCJwLtGbsGLoD7UQ12F9tEW3ZztFTtGttH9tH56QdtF7tEwLbrtGP4je2FbtGBp6vNieOHCkidsH12Cn5Ly2Ehyx9sElUCoOFEOFHtFkC6XtGzFHXtGGLbd5yh1JjtGesEhpwmZxEf6bXa0oDETBLuAHdIx+KBp6tWK+OEPtFILYN6GJOGdtGjX46tTS2HwdEwdF5lCT2Gr5C3sHx2B0OFz2EkcGNC6aEje2G6Iy4C6CFqG2FDtHHtFEdEftG8QiVX5HdQ12EVWjRXaYdEttHIrwTqEu0CT2HhQSaC6IdH72GvtE02CZlgAdHntGNC4btHZ2HilICp7W6Dn2FuxYWICBp50Ar32HQdGkdHmPwDpzIdHHtGRUqbtFNlEs2AAHixdbzsy+sHx1xAVbX2GIL6Bp5hmiSOGqdGjX46dEaOFbtESC5HeTv2EcdFtC7cOEAOEYdHY1rs+EO8S+2EBC4QOGt2xB2FKdEOdF1ZhCUASC7Jvpr2HfhhydFjmzf2GrtHedEmdHlZy8yhftEGdFYOGftEDl51C7CdFGdGw2APKw27YldBadGw2DXXChdFRdE0C4l2Gj2FqdHPy42OFmdHBdBkOGsP4YdFpz5odGAdF+XYRdGw+GOdFgOHFdEqdFNsRudGw2AedGwOFIVHVdEWdEldBwVGw2ABdEQZxBdH0LYpdG6dEeQivDZxX5tmDnFHJdG5hyZdH9dE+dGIOHodGUcGJuEudFB8gqC5O9qHtHKiqaC7TdG7tFq5rGX5B6DCdEMdFxp7Ciw5dEsdG+X67yzsdFDdG9dETZzjtEYk4QMTQ2GgcEWk6pdEyEKcOEWk4mOH25xKwhJX7LtGmOGudH/46ndG6dGexY0OGHdE6OG5dFjdFYpARFFBQF/tG2wQDFGydGOX7uDRZFFmdGbmxIdEJxCb94WX7KdFN5zJdFrnKuOGydGBp70HhXtEw9HJbDfFFHtGBp42vAgSEOXJqdEY9GBOEA9FbX45JBv1wvdEqC4EfqxOHTDBOcGCsBwdHg9GJVFX+FpOFF974lGR1GRx60PLYlGuhG6NHc2B09EklFFOF6W5M9EUlHx5HWlGVK5sV461TSlEclHI2APeCB8RC9Es9F+tGtC7YgS0lHZ1GLC6oDgSlHGtGtC50RG9OGM9Q1OH4U5/eLXGF89EpT6lC4VcEdOES9Fz8A69GjOEgALhtENp4ueAClFhtE9TBm9FLOEKNHl1HprCVywalEElFalEneEZtFhiFZtGBNEJCD4U47yACYoQRCFtGkQDFtHt1EWlEJpFltEu1GrOGHdF2lEqJwOlGD1F1tGZpHZtHABGkmEY2538xe0S3yGzGBVmHYTDk2F7A7wSHeWDi6zF8FA1Jak5sixNRKZyHr2Q2D5JYbxyFjECViGJ9Hp9FzpA5FG0IBJ9FAhE3DYlxzzahRpB19FTiFmWC82Hm3KQDZykC19Ht9F59FNZTp9GgVLl9GHnxPiH99HOmFWrytiFB6CdFEBVxt8Q59Fl9Ej9E3AZpKEZ9Hl9Gj9FRyGO6D7iGeqHK2EL9Gz9F58FoR6so7/xzVkonyHb9E1W52R5SkDd9Hl9GzDK22Eb9F0Fy+kJj9Ez9GX9HOCStiHD9GpMHjqBT9FryEd9Hu6DH9HjJLADaLxzkFb79E39H9xzf9HX8Ep9G39HZE4pyFkwQkcH4x6tpJShG8jacFzv9EwTD0SGKtEIlCOSHMSEj3QzmGIDG+SF2NEh9HjmGoDFPMBB5EQlBYDE4KFatEbnaNxH2hGa9F7zC+qBGhGa9Hp1GbzCTEDkDFiCFeZwySHMCEEDECc4J0IuhFMlErHatNYehHxtEqiGox5FAjEDG0DGPTrqSFBhGmNHn6D8DFYCGOpHYj48DFOSEv0om9H8lBEDH8OIcSFhNEexFNLAN1GysC6x57kRRSEmlEbcFHVEhxEnVFB9FnVHltEQFA+pBlhFhhHi+q5NG9sD5NFuJGFNEYp69vIcqTKJzx1xNiElsGpvDKMGgrwVsG3NwCcGiMH2DHwWqY9ECNDtiFOTr6bBs864pweDHMOgwVGDNEDiH62H4WQUSECNCjiHB2HOTodNG87KbsHkhYF9HuDHW2HhDHKMF8pIu2EpDG2DHODFl2HFcGsmFZDELsGsTLbNEbMIp2EtCjESF2DEVsE4J4a0zlMEeDElDGFDGd5CK2F/9pC2EBDEVsHpUQSqHu2AviGAcFovTJMH46jgdE9do8A62DFpDGscF9DEtNEeDH+KyVDFNDG7sHUjwRFGsk56OGIJERDFm/40OExhKLr60mE8sht45n2G1DERzrwOHUSxwdZO5wDiHQOFLDEhW5OITRXYxhI2DEFmG3jAyOGTDGtMGYK7vsEPbjVMFlDETDGMfjhbBJDG0cHHvgXMGRDHIOHC3i22FvDF02EmdrBDF3DHKcEPDH9DG4mT/DFDDFVDFZsHQAi/DF5DFGcFrSqXDFAjFmcHfEwpmEDDFwjG3iHjDHHl6leJBywIjGwjH2OEY9ZrJx/DFrqE4lHHhBPDHxqH4jFupwojHeOEjuRFMF4C6kSH2OGdDEpmHCrxOcGI+KtCg4jHT+pu37wDET9AFOFTmGc9EnNDsjEIWEutEYDE8W4lOGbmHRhHFOHcjHFUBbmGK9Ew2DjhpslFXmEkDGb4C7SoZOHmtGs9FIpC5cGBtFJ1Ej4DtOEnmFp1H6DHdOE8QAZOFUsGy9EIuC9TaisHzeGUDEw2DqjHSjFZOFmjHcsGMDH1xCWjHgWFUbCzOFRtHu/zSDHchDJcHSsGptEKDG6lFKDFa9HkDAnOEreIgGEaDHxiFaDEYyBGKHT5HhxF8jEMJAPOHfkDVtGmDGPMDmDFJpHr5F8g41KyQSHymGclLJjELNGiZyc7BRME1NGUlKUzhMjFl7r7BGtiSZjEtNGNyFJjEAtHPyznBFdFACTaSmEVyFOAFt9EWMG1yEZoKDlHFMExyGVjHJjHZjGtjFljFUmEoJzVwqZDF0mF2RJuDFzMFyFYdeIDjHctHP2JJ2EBmH9jHviGDjHga7+wIo2GlmHOxJimhumGYhGRAJlbTDMGZMF/UFzO7ZwCOMGPNFIu4pMJ9MF9jGKAJrVI4jHZjGHjFeDHpjEec59iEpjHgHqSOEbNGk86SDypDFdjEzvwQjGPjGGlhTDElsI3a6k879kiEtHStF85HXjE92HytGQKHtGE5lb6Uy6jGklFHkBNaagsGptFCDH9UAQTGCjFSDHgTGLOGCjE+gzQTENUAOjH7mFBtG/c7ukDyjEOtEmjHOWDhIHYTEYTEcsBY/AETGajHhjGJ5HNOGgsGetHEKHylwvmG+tFa9GXqDETEqjEyjFETHSvCAWHzOEoTFeFZQfCUTHRtEp5GsTFgWE87yilFWMAL9zrOGatFO9F95Eu9GbVF6lHbVFrpDSB5+jEFtHj5EomGT5GB9GhjGJpFkTH2BAKXDh9FmsED1FncEr5HTLANtFzBEsWGONJeJGfuFGTEnRGbxGaBFfVFHRF6tKvZGgpGcxYwk77lGnRGmTF+JG/ZGcxYZArm5HXBHeiabREQpFLl7P1BJKII1EmTFuTEocFWTGBTEXRHBTEpJiY1HmTGt4KNJEspEkxaZ3BiVH3ZGv+q1JEc1GxTEo5EU1Ekxb6wZOsEk5GKuq4NTk5EfRZ2tjM1F95QbjFcKBW5Hl7ADMG5lZ05GY5FExBFNwHUFIiEfRZ+TGYcG93pilawqoE1FakIRQBNy5J5Dlj5N5H21HdeEVb4ipHO1Hd1GreG9TGSpEBNH6zBDTHu1ElVGKjFEoCxeFapH6jHoQAERC55GS9HHZD8Z4B1H1aBu1Ex1GcDEiSGlg5Xcbe1EWpHdeHNJil5GkTEDTHbe6V1E2pEjVGQMDVBE80FiDGTTGUJYnTFWxHfGFAJa3TH91GCTGysDTTH+pHV1FuxHaJGZtFSTGx9HK5CjlbRiF+xHcci+9EqQDJNEB9GpNF6DFqTG9WDbTEL5EncE1tE/jBmDH1tH3VGNtE11buDi9CgNZHOV7sKithH7hHozGaZGBZH/BEA8DzZFWaGLkHS7anm7BREOaH6LZtwAtpFthFfLbzZFNhHUzEmLaERHkzGpZFuZHBy7ZGZozGT7bVZEzpEqLZHthHhEMzGJXbFZGkRFxy5J/DLpF9ZGCzGZZF5aHxZF1y6DRSvhHJZFwy5SzEHpHpZEqLYoIK7aHZZF31aY0DDuKNaEFZFxy5M2itaGRZBJy5FSgUDZeZEszGeZGfaFwy5KzFZZFUzGP7Z0ODNZERaGohH6zGPpEWzFy5KdZHgZFwy6jKrsLbz8Fg6EdPYv5LizHQ6GWzG5Hyz1ZjZHkhGqijjaG0zGf4AKXT2LYhzFoiEs6F3pHEhG46DJaGWIB0Jw8yDUCjC6GnpE5ZGJzF5ZFpZG9qFpzHqzF7aH0RGJzEkzHIREjaE7o78zF/pGraF1o44zGczFsyCGZG4zHEhFBzGRZHQZGuNYpVR+zHuREaDZRPZgGLeRH7aE8yAwHRWRHsRE1zFWzGZRHkaI1zEczERRGZzGVzEEzH/8gH1aRzGyLaxREOMAxzHFzEXuRyUF3475zHg1EDzFZzHF7ZvhGLZEo6G3+Fo6Fu8G/N4buEuT6HZFhjQUcz7zEIUBE6FHzEMKCnZE1RHyUGtkaSSBnZH/eEXZEiu5JsoM3ABUGomgSDZO+YRag8WEvzGGF4EODvzG8UGbpQgDbTKCMiIQuEQdgo9YjqT7ICwuH5tJ0cCu9acUIdSF6tJ/zG09bs9p1SGwLFOWTwLFWMaILF5X6A8BXU6ALIIUGfzFQLEq8DTSFILEYLGVU6QGykuGfzFXU5mzq2WHDIDILEq6q3YrsuFVnIUFblhIHPD8BEcfgDKBRU5l7oDkJBWHRarJU6OxAwLH10YjD7thI37qhBE9Sxe9bkCTsLEZhrAtqsLEq7h+uGquxlc4kbA0LG2e57IhkLGUZS/l5wkSELExhLELEfzF/zGu9a1ozypwKRpwLGN+J8fSel7oLGvzHmnjuNgxe5jXisLHn7C9/BmLEjFC09Zvj5VdTLe4lrC2LFO/QpfjLe6iRiGF7veBjYiCLGHWBOLHsFJDWFLiRPU79AwuLFC1Lr1pOLGsYbgLES3gWLEGyqpWGkLH7+KlCQaLFULH+GF/0jyLEaDaP+LYCg8WEmDjDDY3uLF4zsuF6LHSeJ9zI2uExLGotrPRSuLFIOROLFppTxuFwWzuLHDn4/lTWLGFu5PuI/zFye7mLF2eJyLHjhqOLF2eLZLElLF0cC/RaKjj4oJeLH+5DdLHOLFSLH0cSJxYLCbTWEZLEDLHFbCpWERLFveLjbTPzG5LGs3o1LEELGvzFIRBJLHwhopLH4aY6LFv2RWQAbzFdBFbzE9BE7zEkt6JUHevIKEoM2B4nwIKEnLEU/6MeLAhpBhAHdxXLEtyQ3LG5ArNHBdRFulFD3YavYlNE1NFvLE9NF0mG+lCcmExmHKmHKvYF1C9jED4j0NF1u5cmFUmGfLHvNHljF4ZxnRzTNFO/QXl6onY0KgFxz1jGkDagYGamG1mEKMEwrETNHgrENNyQrHYrEHLDzNHfLGImDrNH6mHgNFErEaMHctF+K4flDbDGPNESK7stEkrFI475VzA+EstFea62dDHjEtyQrCGqeBemFLjE1a4LMCcoidmHrjEv17A+zrNGgtpNMFxw7vLGxmGdw4b3IFmHKjz+w5UrFZjGGvCYXDDw4teKAjGVxAHB7CizMtHymHaH70tHwtEbrahRKOMGrWB4tEGH6A3BrjHNFLNb5ZUhktG284UtG6rFytHvjH1w7VwT0tGNMFrw7qrGitE0rFjGwvNGurGjiC4rE7Ehrw5CrE/NHgCHUlCArHktFAtE9raBrEHDHEtE9rbstEGrGfSFirFYrHdn4tw7JmHorHBa44eD2ij8rHfLGrsTCrHgrFZ8aSMEUrGH5Z8tGZrFqiKtmEerHpOgPNH8Iw3a4cSDhBz7jH9mHVrZ6rFLMHDmHCNEK0Gb8EcjGqtEKZCBNxQsFQTHXTGfiCtrFcsF6tESNFdrGn8BijHOjEsKDn072tGETE9iDLMFWtG8jFHTFME5CI4jrGqjFtiBwxTOtGHTG8lGKN6EDbcTF0TG7bYWtA+tEbTEmSGiN4LrFMTFWNF7rGhtHsTEdrGiSCHrFRtFF1L8xFnrFxtFatHWm5BXz8OKiTFptFFtH95FfTFejHpNEIyCDzByTGKjCJNFPrFBjHQyAhjGd1FhjFTrG+eBrxFUWFGjE0WExjGWUBxjEh9EJjG43ZI3q4cHm3L2DFwbE6OGlxKesFK15PiFfDqLm5cKCotil9HeRRDLZobGwJwobGLm5IbE/iEAVwztFNXoHDgASFh1CU2E6no3DQnyFUbF02EylYriEYbFILY517wbEGjq+sGsbHIbFVKSYbGAkiOOGEbHHl4T7r0cEb8HXiGz7qE0BoSFKyR9sFjFZg9wADH2DGCbERFFERIibGJ7rgcEj0r3iFLHqmCq3yHpyibXbyzA+cDL8G0f562EVbqmCrVyFWlIsbHb6DdNRq3ISNAcT5teg1EKf8FCFxtbpxMif8HkVz0bpCGSPDHsbGYbGQDI92GubEmbHS2AkbHSnYwT6YDJEDatmC2bESzDybFgMg3AQwT4ixrybHcbECbGRdLtMiyxKccFB07IbEzxyidGVrpPZrNGGebG7j75urAlH8bG7j5/RTibHGbF4bG6Lo+bH5bEwT54sDQlHCbHddF4FCpbE4hHFbHuLpVbEybEcbGwsYYKL1bGYbHzCgebFxwS3sFGLq1AZ3BHQQpabGFbGUbFo4pgOHqLpsbGrMxQOHuLqO+yI7a5RJQTIlbH1nJ/0G5RJRDHuLrqlA97jlbGdsGVbFtfI4hEvizm2GTeFsbHMbG7j6S4RlbEKbEVbEkdA8dJryGybFHbEdagqbEcbEEmxNbEXbGYbGJRptbG7PyUcHl5DjbHdbGabF+XZbbFcbEDbHET5UxI/iEjbFVdFPbFdbGZyFTbGlzoQGizbH0bGAT5XbFLbEHbErbFnbFpbFsEgVbEBQTbFHZbEwT5hATXbFI7Ftzog7H38HtbGPbGm/gfbEHcIdfasUE74CfBHsFwcT724IBbFyjLYcFtzoUbG0hGEHQTqEF5BLSI4hEKnbI7FWmCQ7E7bFM7ERXYnbEcbFxwRmbGH0agcE9zprbGgSFnDGiLZLzo7ow/9FDIGGT4UyCMjHX8HE7FM7F1bHKXJUjFtzp13CT5yi+YdbEI7G0DbZbEIT43wzZMA3bEsbHeAiI7Gs7EMT6LbFn1xwxJN1icXZLj7bbESbEsbELqAV2Hq7Fb4B4XbT9E1bHST6+CjJ9GqbE7V7JCA/9EO7FGezKOFo7HNEBoiIgDF1fA0OFqT77bEPSxOcGO7HWbGyMpwDGI6E8W4IiC69GKKHIDFpcHR7EZOEcSEcTGJ3aITGoCE4DFo/ap7GECGndzijHY2Avz4x7EMDE1OFrj4ZOFEKHJ7FXAAdTH57El7GiRBbbHF7F8KH0THU2DZNFSjFGSE1OFpXb94BN7GDrH17Hc9GCKF+hHOT6d7ESSFCKHt7H1xDV7F/MEBKD51Fz8BD7GSDHbrH2SHUpB57HrOHyDEfTEbVF11Fu9HKDEXxDXioreI6KEBjGBxGKTEltFWJHB9FAbEMJAN7Hh9EftraTG06DncEx9H6TFKZHhyEUGCi06myFAmQKjbfSzRBg37H2OjUh6x4YJ9TKyFP7EIDZTYyVTSmyGcLwK66ElDXSzf7H/9zvZFQ3iS6HWBiELFPfhf7Hg4q37H/9af7EL0hv7FULFxPiGLBwHGA8Af7HQexb6GgHEKjbP7hHYC/6FQHHcz6RjZsDZg5DwHEYTD3kSyorkaAUFZ6ECYDi/6FcgSEz4tyQz0hIEpbqrcz6HxBr6Gd8Z8LEc/SY0TB6H0nwsjZoaa0HEycDyWKlDaiqZwJjN4riHyANZXrjEHEJICso4D4B4HGipz9uxgHGYHEpEyQHHv7F64A+GgO6E4HGT4Dv4rYHFP7Hcz5USp76EcjwK65lABqHF+6EeYj55YdO6wHHCTE2LF64CSqiCyEjOFmHF2XR7fiyyHMHEV5ZngoCHHiNyAHFGHE0HFHSHAhL9LFb+HVHLMyHbkL5q6OHGT6HKNQiYGKHG2HE37HiHHn6LOxzqyEqHH4TgQHEJIAaHGqHFYHGhHEaDZkDjcvimyEMNBVD608q+cQfpwEHGELHENh1KIrSFRHHwNiI6wkHFT4Ca5HsgHYyFyOTXq7SnoH/CQErt0CT5Z70hOHFWHGFu7v1wUHHB6G7ogO5ZVHHt6G7PyhgilHF5oqpHGGJqlHERHGJHGVHGOxBCSjyHFULEAGBQeSP7HjHF/NiRvSQHFhHGLvByHGbDz9HF64BaHF2HG+HHB5bPQpOEgcyFtHGuHE1eZ+6HuyTgu4kU7NIA1HHosquHEx+KwyEg0DLwDDHG93I36HD1o3ACa5E7gjIDbZHHmFGR7GIQA3+F3WF3+G8ZFlRH8ZEVRHUDaf8rZYAVIj9sx80T/HHzNzferaBBWryNqDXmDimzAnE3WBNJ7KdzPLHx9HXuHdOo50GIMFWhyvzHCJAvcE/uo48GJHDH5FYMGV0GOgrTczc8F10H1F4spLA8F10Gu9bZwbg8FYnGvzGTg6v5HUnGGF60nF/cFonEMnFRug4FGL+TfcGnS6AFEPcH50FsApcnHsnHYnFbEBMFFeZw8nG9vJPqBYMEb0G09b2ui6FHl8535a2WoaFFwaGfHT69a7OhsnEq87JF6snGo8FjqrpF5UiKkFEkFrFF5SnHb0Hh85S8GinF0FHjqJqnGGSwk8H0nGSnFck5Y8H0nGu9aBVBG7bCnGQ8FD9ZCnH8nGvzGXBCYMGJKwSnEkZKsxZMnHtYxe9bcyH8FGx3waZ6RfJcFE4axyUi09auxrl0GhRqYZwkZKkeD8FE/aikeFJS4tDCPDH8Jzf0HenEvByxqGWnEkZLbKBa8FZnFSJYOnGavyGF4jywv0EJnFyFae2E6nECuZPU666AqFHlCRRqARnHj+zb0H/rxX5HqmrSFEbMIweEpVGLCTtqEcFSANao/IZnFdnEWMb1nHfbgpnFtnEo9YBnFY8FNnEA8FzF6hnF9j430E7LFWFHFREruGlRFruHlREbuGVLQR8EqOCUIqnThFTCI0SbnFYp56JDM3hqIq+FEHnGKZEvLE65ZtOL8bhaZGxaFmuLd8iXnGkUHXnHGaFLhGcxbj2DVpGEzGp5aMbL1pH2aGhqGc2L9pFozHjuKAZEFpG02KUUKLhFUzEcWKBaETpGcxbxZq9aG0zEFWLDpHVzG8OIacr7LYMzGEFq3pElzGMo4QjIXpG9ZHXqEbcpIZHezFPhEbco/nGz1Y9zH4XFgXHDzFyUEXGFEZFKlTau6i9RnaFyDqk7C/Rag9RUZG6zH0XHWc72zFYzEwXEvpEmzF7TKRXyGRFtBAaDZATKwXHzpEUFbiqYvnEgXGE7pgZFIXFy9LLaGoXFCXFFlzYZFGRGDu5cxonpF0RGB7CVu5+eboZFjZGqXEYXGEXEjMAxxbrBhMZHQXGKXHKzE2zFwdK0ZFuzEgXGBwLTpHOzFdQY8Wp7hEXhG1tJIOQFzFbaG1tLoBq6RG5zFtaBaXHr1azvwhu7TFxyXFxegOu6dJQfnEfz6EaH2XGMXE7dpCXEwRpgZFtaG/RYWXGsXFXnGgtre5QAXEKu5UOxSRGlZEptJB+zBzGKzgJzEqu6xZLhaHGniJxYmZRMZHTzH+XE5XpTzHuxxWIDRXHWcgfpE5zEqXFpXECXHNzGDu5+mqMCiCXEVXHLux0ZFLhFznFRUELnE2FFLnF2FErnFHLFwFI4UBHZH7BJeAQGCANRHT+IDJJbZHuJIDXEyZFWXAInEA+GLi5qQDa3qNhGdpFOj54YK3nFjkHtmFrXG4zGJZz/rTAXHGZF0FyBMpSXH36yjhGq6BlaENZEPYC7XHVLatpENiwiXGjpHNyxnXHgXG4JzbZoZXF3XGqBAvpGERHEJwczrVzG4JwFwohZH1zH0JxE5ByXErpEA3E7aHIZESzG4JyiujSzE5Op0FweCjbpHzzECD5MFAUXG1aGgZxcIBwZFWCCazE/XHEkA6zHSRGfXGdaHXXFvXFQXE2zFGZyDaGOXEemFugDvXGhZG26FNWBiaoDpEbXEikAXnx/XG9pGZGwd9BQZEXhFOR4suKRZG8XGmR7ABBKXH3ogqXFIx7rpEYZHs3Fo3HJZG6Zw9/IlpHgx4UXFThGjxz7iA6MHgZHi6CA3HXhF3XHVaoJXGeXGOBHi6DTbLdzFeXESZy/XFBaE9zEK3Es3HmZGLkEK3Ec3EaRHpZEm3Fo3GZdBBBEG3GBXHxzH+VyEqChXGlZEa3FbXES3HdeaE3HK3HaxythE43H0R7HCCNaHEjgdXHdBEPWG9BG7zGRN7BJzewIzXEByGQ+CpgLgZANREnzArUo3zGiZFR3Gk6GHzFABG2sHzXFAk6T/hCOElpFMwRtcznXE53GOOFuZHYGBHwR7XH9hFYr6iMKkzGhqHYGCIrGUzGjpE5vi/dLZ3Hp+D13Hy3GeGDAGi03G7MGsbDQhp53EbIIUSHN3Hb8SABDfXF6EBQza2XH/pEtfSwSHbpwizFj8FmoboZH5aGtx4uLj7LJ63E6XG2M5z3HviGkXFiM5m+ISqEpzFtL4CpBj3G0XH1Z6D3FG0glZEMZFDrj93HZ3Hd3EvXGmaH8GCnm5uRGbaEZ/asLDRnTNXH8GDF3Ft3ELjZOXSDcwzpHUPbl3HD3GraHUPbkQDLpFfpHUPb4QbIZH7aEAPEdzZw6HHaHTjZAO5j3Gi3FiTjLXGjpG1HSAPE1ZG/3aVIGM3HAZGhligPHv3Grg5N3GvaEB3F7LFB3EHLGY6FOyESJ6DXEp3GlbD8J7NZISZGvbCNx4fNKTXGUPFEPER3EnnGInFD3ZYlrIKDij4aUKXlEZGrHJBbbBtmb4+GD2pjACJHDHOg8PFxuF/K4Dlr4+EM5gi7DBxgn57Axot+xfp78ViSPHIaEL0i1PCf1wW+pqXjCPECPGYcBJuZ/K5BxLsZzqPH0/qsPFvzQ0+FtCI6uSKPF8dbPREdgQSPHm84q1bFgJ/K5sPHj+HywgKPHWVyRVHpFEkZ6AfZas7lTwaPFcPF24hm4EwOTTw6FTCwQhePFB4gLw5/BArIiBVFyMCKZ5Bc5DcZm4HIRApEzdOoz9LQdYL8jEarij6Qsyy+HHGyPCiOYDdWJ8+G+uGJPHXtjv0GGPGcPHIgadzYdMEsPGG5BKqDZxbJJ6ZPEeYBKzxK+EpPEWcgmgpa+hxPHH8h60gmgr6PGBVFJiSbw4DrCSPHTH4rIisPF1PEz+G4ijiZ78LLwF4JIChPEDw7Oy6h86bDwBPHij6cph+BGH8xdPF0G7UF6l0HePGaPE7txDT4/FHOPEwMSuPHfSwblTCPGDNCl0FRPHZbDmPGO+EcPEDw6yPEWPGzDJFPHtPEWPGLMzNIBNPGSPFzFHwYi1PG0wgL+HDPHij4utiAdarPELw7GjRAF7jPEqPEWYBk6wFPGbPEKPEatYOnAL+GtPGJPHpPFs4oQaiJPFRqTj+HvRx5PFf4C686zdw/PEnPG90GsJBpPgHPE0+H79xyuHovEbJ5aISQo4XPEovFsrBW4CNZbKxyd0HlPGv/p/8Cl0GoUJtPEs0b1rGj1FALYNx6ZkDr7gAuEK6FnSpLYxjuGMl6svHFpHauGstFtVDOGy1uEC6EX/ZjErTWFdWHDNH0GLOaFEuFEA4oVweaESvFoA5SvHHkFUuEX/Ybgq4uHCWH6A7Z1DGWHFWGqvEDWT6uEsvG+g7TpHcvF4A7j47zWGsmwuWGnNEaLZMuGeWGmvHpSSGLEbhxOpaBFrP3AIUHBWGnNFKvFALH9WGP/a6lz3aEfZB2ci8A5KQ7MAg7WHSuFkA6GvGpWHkkCP/a6vGZWFkuGavHRaESvFYA5cWg9f6oBFvuaUtFCvHgLF4uGnNHLCpVWFpWGnNF2LbxuH45T4ZYdDL2vGhBGqAg4PYbtL0SprJz6vFfNHFPoULEavFtaAiz5FWHj4KrNFHFxGvGxNifPaE9LkugFLFR8CcA5jhS+vEWuEt6HCtFmvE8WGJKi+pbNvGxvH9kHWzZ//b1vGpWG7WFlvHVvHg1IKuGXNHlvHsvF4A7qpIJXEyvGXNFYebRuHBvGXNEivTGWETvEbvGNNzgLHtuGUtHOLZ9vE8axfNGHvFdvHDvZsdK7vHsuFtvFfNGbvH1BFuCIaA65ahf8g1vGX6GXNHQkDgDb6vE4PEfHHbzFCaEh3HnN5xmBorCgMBtWoByF7mA8sCdxx4GHd+IbsrnuHAfGtHSAfFY0AMPHp3ECvaOsqEeJbKEbtZoWBa5oyD6wqFHA7ofFL+EnKFZCH/oR1SHBKEZdapmApEQUqF4aHhZ67Z6PswQqGofGT8Hq2wofEttZoWC7XRBKGiqHvZZI8yUfE5KE3tapmBixiPKGYfGcfEj3D7KHUfGLYwAyHsfExCE6NBKyFyrgBdYadBDAidD6gPC8dbR55h4yV+EL2RdKEadAiAZDKHGmzvZYwPgdSH8qF0dbKfGa6zAqGi7yUdaSfH+PIFKEUYDCqDR549mIwqGyIBLKFb57p1gH948fHKhJ8fFUfFHtZxmAkfE5+G4fGlZY+/RCfHMfHufHHtrgDbifGf5DR56MfE3KFOFBg0ABfEOfFPKFKfHXUqSbzCz7sqHx57IcxvKFzgo4qEadBcfHGfEAqFJfHd+F6fFOZDefF6jKMqFufFxmDrDTp+F2fHOkb2LFIvhWfF056dpD/KEUsDefHyfF6fFLwCJfF74YBEB6fEEqH3SEYTDlfGEfF7i5FfGkfGfWrefH5fEWfG0qH656fJDqSg0qEhmD656ZKY1LHCHgxfGIHJhfGRKHh56GvDeCT4qECqFZZZZs6CKCSqHe6EqSpGfH8fH0fE3uKOXI5fF9fG1NH6iYYfG9TjMqHFGHmfFsqHHIh7fEufFJKGkqHnfHrfHzfHafFrfGtfF6Ag/KHFGEXfEVfEMoB7fEnfGIqFWfH6+JCsSOfHe6EC+LJOq/fGxGGVlQi4EgqHefGIhw6MEIPgqgCfvHWFGfHErZHfHFrZFqYBhxAWqGmqGI/Hy4qGqHAfFNZSQJK6qE2bCo/FY/E7VIct4BFH0vFAG7DSw6i5jHGELFsizQi5THHk/Fteg0FpIHFz1GQYABtAAHGlLH/0FYi5M/GQLF8KwpDpk/ESDZ0ECM/Fc/HbI4M/GEBF89xULF6WANIH5HEKHGnKx3HRU/Hc/FApyS/F0/HbI6yKjgi5y/GLI6ZsCceEG9ykHHK/HUBBghF8zaLYIa/EdmKu6EWHzqj5EwCc/EpwCGHFqlCi/EcyEcHG6/FSi4M6G8HEa/HiuIBHHajxlc6k8EDehzHF4xEK/FsBGxHHC/Ey/EChGe/HIHGioBH0Dr8GeNyExInC7JJCM1ZS/EX1ElpDMmj5HHiHF7qC3gR2HEVr5N5btGzG/HJr76qD7C4ALqq/HPHFUxGp3rKLZC/Hk/GR4qC/G+YwlHHiWDPiK3HGnZB4xHsqS4s50HGIqDwxEgyKaeEm/FkcA1/GEngGyHrHE1/FpuzaHFpHGoo5olI+/EUyDl/GzNKC/HSHHc/GRYi0/G+/GD/Fehyq/E9/FGi4+axh/HN4rLHFgZy+ty66GWOo1/H2/EgyHjPwvI5T/GB/FPJxdLExmywswGHEN/H9myU/Hg4rSzyFu7yWC/C77HFNLHFTCfC67/F8LHFTBx/Fs/HrRF0SF1/EeHECADQ/FdXGw/HB3GHLEe8GlczQbJwnG4iwGArTWDdBKjsyg/ql0BQnG//FsmonYCAnHwfH3zFInGtSafDHZjFssafDHpjGKRJ7jGJrExyEN6oG7RArFma5q3LIAnMrEoLF8UCuMECmF6DZ18EIAlwrEgLGDgAj2HIrH/zECmDvNFwAnPISwAldjFEAmuMHKmEZark2HzjGRtot2HTjESLHVwp/LG9yG79rXbETjFsAnhjYcAnxU6iDTFjFjyGP+IGVbcrFc5FOKBeDECrF6Da7eJcAkoAnLLHj+xLbHTjGu9ZhyQUjFwAnqAllMH8Am3Y63DE7jE3uJbjFLMHerFCXET8SOmHsrF8XHZCTsAlmJqPJHneIKAmWrHBrF2eIn8KSmHSkgTLGGAnVjHXBFm7ZjDH0rH0LFaAlLMH7NGZLGYEhTDHZjHdeJmbG3jHw7Z8AnBAkzwB8An6Al4HavDG2rEFxZZ+y3ME/jEyu6U1CxbEATEoJGsjFHaDHHigsFgTF7e7ZAltrGTrHLrHXu75AndrFCjFwJaZ7GijFGtED7EPe4VAnmjGYKHnWYkTEUDFajGU07eaSNAlrmEdnJtAk57FnF64dprrGzTFezKw+J6jHWjGGtCm/idAnwKEdAlsTGKlGl7HI05SjGJuGj7EYKAjAncTFOjG29GfaB7wRujEYsEejEvrFrrBvrFHaDDpCnOH+jHfrF+9EgzHaDEd1FowBd1FFAkO5AftqaTHRjEZpHOlFHTEwbF/L6U9Qq+HNjFLL6PAmtDELNEl1BqJakJyJmHlN4DNENNF/L7muCv5aiAmd8GvAmoUE22AK6BMZzxZB8rHuAlTMGrQ6umEUAl/L6V7yLjHfAnNMqtDGTNGQglPAltmGiZAteIlrF1mFRQ5crEcAlBJ72sCgdEbNFBJ5p5DJMFCtF4gkczS2mEJMGeQ7hBy9jG4gnqqyLTKSAldvYfERorHMgkQgkVCxYrFWrFgJ6fAnyrHcglERZI+Fgb65mFgJ6RiAdNGRmF/L5jQQvNFogncEjKOEkgkFRbarFUmGEr70/RStGKgmsr7+mHxAlPL564izMHJAmtx4ygljAC2851rEjS6iPyUsG5AnaFCIJKQTGFAkJtErS7GgmGtHwTHo1DmglITG4KG4TEe+BwWCzrHMTFtYD+gSLrFNAkQzHbt6Ss5egliCG0w6pVF1AnVAn11BXrFGjHrrF51DxEBbrFDAn11CQsETrFzrH2JBxgmn8AW9EnrGlJBJglGjEXrELM6/MH8TFLAnu9FXFBRcDJtEjuGysHz7G11FoWH11HejEeiAKLg4WH7AlAzH3YBHAnBjGhxEqTG77HnAnPhCobZ1BxRjECTGwzFQ6CxjEIzEFNFIzFVlYbroXxF0NHp05Dglv1Hc04C5QaGFueHc07mlq3kFr1GpME6rrfxESeHc056MGnxF71GCmHWGFIJHn1EAVYKbbFBFH1HzgmhH5UNF5xGQFArgn/xFFGEbgk8NFHgkKeF1xEjxEWoBwrF6eFgNEcZaoLpPeZ0NGEVazDKheFLglPgnEeEPgl0VasfGk6hjglhQA7Ej/xG7xEZ5BTtzgDaHxEX8FJ5A7EieeFTgmQQkZoiXxEil5Pj7PglheEZ5CSMiPDFzgmEVb9AxwJFngm1ozieHVxGDiGdZS+eEwQloaaBeF+eEYQmqFSReFEQnkQmr1FP1EAVas3oxeGqeH7SGURCTDhaeFLJFXj6qoFpeHIJHU9HtBHWL6/GH9gC5eHcCGx76fGG4JGpglUH68QmMGGuVhSSFiQlVeExgke+Avz5ONEcJEGVCcTgmNEiQm15AO3jKQmlhCTeEGNEKQnOglJ+DZNFSNGTeHugl0vbYwaCJEOhE6QmyVABEjqQkGVAWQluNFz2Qhgke+CaQmfGEbeH6tHWQlyJEjTEVgl4iByQnqJHSNFiTHptE6lGbAkIDDSTGwmFpXa3oLxNEe94KTEPeGgzGltHgzF77F8GB6QlZNFfeE3AlvOGIzEGTF1hE9oAVhIBUGQBFj2AW3owBGZQk1JGB9wmBEQdGkkryvGwYIYaEt844vCoBHYBE02B3sZ4BHJqEl2A34YQuG5Qlt0BobJOWGNQkZawd3gFQmNC5svIGBGOqHzJFX9ItQm1QkPlS3tAmBFkC4rbwoNi+TG/kEjQnSphMLFSWEqC7Uuh1Pz1BEQUGNC7VQkIUHThpSdHLQlOWFJhiUdEiMDzQloUGqRHnJFX0yhBEOKZxp6jQllMFRBGTQkerphvG5Ql1/4UYT0BHadG4jIjFDsuFB87GdGq0R7vFeqEyC4cqiYJw+UFUaGMsByPjxuECPDGX5aJTwGqdWHNfyu3YCNC10y0uG5QlmijSrjDQko2AupIlvHA+yOBHRdF3/CUV4IwnlXHNdFjFirkHgaFgb4vQkVQlAaHVdEo4YbQk4aH4wkHQlLVJJdTm47YwnlQmkwmkaHowljQlnQlIwn5QlJBHOC5dQkFBE9QlO5AuxzaUHfQkzKyi2BUwnIoAv/HLZHv/EEPHjN6A8CK+rTBGMxo/kASSAZUGMxrZQANVIpUFiwmIjhERBDBGQAlj1Eps54kSJbH7qilY5mpE/bHqwk7G4yFAEbEATCoDbaEQt2GueZBsGXoRD9Hawn8baawmshH+84Oa6I4o+bGF2HupajJbgqFMRKjiH/UEiFJ8bH6wmlY62wlWwkLGr8bZewmihFNiGT/jkFZShH3iF7Xh6LoSxLXiGhwkhbHmwnqbZGIpZbEScwGwmElBRwn6OhbxZkwxJ2G7EHUj7XHiV9Eh84gm5IRDESHQ9bgdFTTj/FFUdDkVwIDh67HmwmEQ4UYb6gnPiEhlGNgKVDHFwnuFywmJqwlbsbsQ7cgLn9G04RhbHn6KSVGf8Hk6JYFGEhw+bH+eirxZOSBKVESxK7DH4FFyOHhwmyDYvjgEjHOwn4DadOBh7HGwloI6cvTc7Ey9o8m6gqRFwlStKb96FwnXFEVRJB2FLwmxbHRXL1DZzwlFMEkKCKApEbYxh6l9E+wlUQ7MoKY7Hlwmdwnn9EWqSgRqYF4IRT3FHVwlZI5uwkvwnxwkcDZ+BDoFbgKFLDKpDZ/Vhdwnv3IuwkAIltwm3wlzfD3wnRwmn5iCrBn8GXwlQInc7Gfwntdac8CY9Ezwn/wkvIZ2wnAIloInewlNiF0TDaVHBwkhlGg9QriEIInmdaXdQXMHpwlGI5V9zz9FEInFdY6VBqwmwIk0Ilawk+wnFdYPa7hjavwk2dawE7HwkewntdYwlzjwmsIk9dbcIle7FEImBdZ5AFxwk07oXG6flwWuA4bFUSGBdbsIllMGT8ER7FATEToHJcqGM5oDFHwTssH5Xy66hIDGmQnNAmy6DqInKInYDHpVGAOCDfQThLkCEyQk1mDyFB6IkF7HssE3FwThKV7GLTFBaD3+gWIm2InhSBMgo2Im17FmQmHSAbpgWIlt7EVdAqqyRBLeIkqQlY8AuIm+hGGQnVLToTaBhH3THuInLSBBIm6CF15HOImVDzGIkyKF5gk18BGIlyDGJhEXOESTGL7HfTFJInLSAqqxeDZZhFiLAHAnAzG/rHkiD/rGnAmAbEtgng+DqzQk4iWKGncEn7G6TFXrCBQn3AlJbrcV76aHQyQsBERLithFtIkFT4dIlWRFdImlT4FogdpH23QX0FYT5i85yQlIOSlT7ZzyUzFdInBBEHirhaHTInuBFydZL1YaHHAUAoVQg6F9In2nxcKpARHzIn4yLS87+zHLIkcOi8lp7InILFo1ZJPCEXHq/GBHye86EXE1/oVBGbUroZEkhIcdZGlTc876aEIOLQ+EV5iEdZWCCW/F7JonAb6aEeUjRBHeZCUNx/fZCHEVBHGJQ6zGoYwVBE+pT2zHbIl+eoZXHrImVyzfIneL7LIkUwIHvCtInv7G4DqHIkIonHIly8FSdZLImYonSPyDtbr1bXInTxpVj5WNao9gS+FIonX3FlRZPG5RLyJCAhZHzIl4sDtTpHIkYLHHkCzIlnIklHHHkDa4hMRFPORVPHUNIUon3ImxVGkXovlyJz6GHFYZrzcg/ImL/G0+FpoThaFP3z1PHdsxbImdT7WhQG84oonHIn/bwRdYYolMok70TXZzeL7yomVOHKRH9rb1PFDPbpLYXBQ/gh8+HMOqXpGfIkAFyjIkUs5dLHUomnIlCokN/Gu1a7MzhaEDPA5PEqQSLIlm9E2LFzOq7Il2okjD4SonIoljInWolUvKCol6Cj+5B8wklRFfHHLnE/HEjOqgKaRBICfbqXKLgI/6wINZgnHMjAX2AjbH9gJm7CrCCnZCp3H3AlCGaGQgeKFufFO1oyLx5omQqFx7KFokbfE3tZ9FpBUiqfFXfF/lqWoCkfGkqHeqHimAZyGA/GdqFb7qEBGyqGBqGtolMfH5olbGBNonCfFrqGmLoChHtomdZqooLm+HdokFsFsBF9omPqG8DYiqHu2SYRH35oXyFbAyyfG5Frk6QdKGKfEtqHc5q9omUqEC5pmgiqfFNfGPqGW7g1fGYbxsaHsY5ghEzKEQ/BToml+qffGiLYvu7GJZ0fFeKEh2IJFrGfHbKFvqEpDYv95efEcpqGhxlonnqFLQS/8F+fFzon2iJtom3KEhfEPwaPonNKEJYTrolGDZ8qFboln9JjazxfG1fHm45n9KgYmvfHoqEPwYbowZfFIqEeppK8w5fHFokjBrd8FDomDaC1onxfGZfFopor2wpfGVfFoporonjKGmwYKLZ1DKUYm3fEjKEkYkLonTfFMaGvonxfFdfHMprVQpDfHEiiPqFt2S+fFMqEIaE47qgCHjfFnfEgYn2wJcqEhKEPwawYlJKFNfEvomOhJBKHQYkpahiYkQnjcYkWxpSYkD4AIrL/44CQZlogD4DgYl8XZaYmaeHN7jtOq4aFJkh8qFAYmbXZsdJIYl/on0LZFdKrmxfoksYl8kgyD7vomE9KXolWYmBqGrsAv8Hj7h3KFHxrwhjSfEU2AdXYpACkYlgYlTdZuYmsYnNKEaYk0YnVRqceHKYnMqFvNClonRfEiYk2YltokKYkl7CDonMYnGYlqYkjnjntZiybaYl2wyOF64aHwUB5onwYk0YliMpQCGQ/HWYmKYmpYmWfHXomBVC2YnNom4aEOYlFokZKHOYmvBElfHXonuYnr8FlYkhYk+YnGfFFYldYmBYn4qF6hr1qHtYl1olb3DWYmRYkWfHVoltaBxYnCYllgChomLnHhom9XGRomRN7OcF0lLY/H/4bg+ha+GBAHG2YYj4mqE0Dr6cEiVCWqFzXFQAlAk6/4BEgwGyFQyELjYz3x/gliyGXYlrczXYlwyGtFHt5C16HUyELjapNQ0uotSGqGENRBq5qmyEXYkQCFPYlMHG/YmFFH/YmQyFlSHTjZxg7SBELSE+MGROhacQR6Gg4kLFFh8QXHGA4nysr9CQg4n9SGXMKqQibSF17DTjYryFa/F7SEu/akY4zyHHSFy/DY4nfzYQ4noyGnFGk4kgHErPQ8TYE4nuHE5LyKrHiCHeSor/HboD1Z7o4nj/GQQYk4n/DKJ6GgyFg4lUvTd/EayGauBM4mo4n/8Fd6A+/EPYkk4lYEjn6GndxTMFPAKvSqyoqXSHiCHA4lA4pEyGauAnUJN6FXjKTJE5qhA3zDdbk4nTjZWqjG6hUyENSELjbJ4KE4m2EymeGC4m5vjMyFYpjnjb64la/FyyGYpFa4nvYm8yEyYB64nxcyWHE84mK4kdvgA4lw4my4n84m6yHiCGS4l2HGcyHSTZsciB/Hi4mauCB4nC4mvFECCZFpznCTY/Ku4mR4ny4nkyGauBdPCl/HfwEx/Z3YkP6Ea4lIPYZlIY4lkyE3VxcTDa4mG4nx4na/ZC4n0yHKC4Z4ll4niNxZkrW/aG8gb/EVta2Fy54ns4n+4lrOQZXDnYk+4k6Nwtog/Ykd4ktLTaHEt4mpChDaQcyHtgRzYndXELYmBkAI/GsqDVVK3w44Ij8GDioIK9AROr/6A/VrAAkHwLeyGT4k+RLT4na7BHYnKwnulE6xCMNHymFcTBn/Q4gnSMGXaz6CDPAk9dY7gnWBF/Akn4nXNGPNEH4l74lQrEUZyMRz34kkAk9dbtmyceHwgmIdJcGH74mcUKgCHf4mOxC/4m34lHJBf4kLNHMIG/8EcAmgEmNmF0mEldAzujHNHKmEQEl5jH+AljdaxmG5DFQEl0njiBHsgmZdZ0rDd8E3NF/UH4ILMQkBmFi2J0BGlmEtpInJFn4mZdYVNp/0GlmGRALuUD3FFtC6QoYS+Eyti0NEhW4VNqc1ZXO5ehJkEm5ZZ4pE4AkXIYgeEbNHWAZcEkUAmkdZ80D6gkcAkYIGkElgglRl6iwFMElEtEcejpBG3ygYjGFmGkdb8OSYJzuZa5mGUzYQqa1mGZmEgNbbCEcEn0PDsEnymFAsb6EmPNH8EmlGEEEknio0eEMtFNMHqEl5dC284+mFKEniEnWAmlPHY3DOGHpAkFPHkpgaEmWrHFfBqBFUQnOAmjMEmEmPDGCEmGEkylSDNGea6lT4UEkqEk1NGB0bhKKKAk0+HlhBXJwGElxEm0jFUmEV451GFitE3a7B7oLzh9mEwCFREmj8gGgkKtGvHGaw6y6QDGGnX4hInYIDwqHS/IPrFTAllEn9jJwTF9AlFEkVEkDrFVEkpwAWNEKjEn2Aq5gDGGtEl17Ha6DUEkdEkOtGNI6J4HS/KdEmRIlXdbbGH8TERgnfsDmTrRgldAlvdYDEmssF9EldI6zElcsEpgl2InFdCLEkvmGZgnmSBrElgbGT7GbGE7VF3GEDCDujElgnhNFCICRNHZRBajFQkHZDKRSE1gnhQlt1HHAnKTEAbGqTExQlXdCjEkdgngbGJQmuJHxjGWDHbNbTGHhmFkEmMGE8eqwEm9yE6rqhrEpjF4FBg2gJmEyaz7BHAkn1NE7jE/Emn1ESEnnBFpLq/EmCElVGEJrEhEk+TFsGHZmF/ElIknwknZjE4klmAlMAmYkl6+HzjGoLrKrH8mFzyHWUGtiIPjHamEPkFzCoiEmwkkHSxH+FCAkAQmwrE0knXzqRrHmAlyxbX5BSrHsgk/FZ0foDvDokkweFLj5moZJElDNEOUEAkkxEmiUEmMoYjGEkn8klJAldjFPj7IknpjGlV5ytF4klanDXFG3jGu7EDvSSknozHgFpAgmDkE7aTkjjLDH/yFqT4S1pZEnJeHqkm0EnPMEZAkFElHV6r9wmgmcjHi9D2kkWglLrFWgmWhHOkm1El5eEekmlAnITEBIlGyD5dH7rGYKGZV5ugmmIlTTG5oyBkljeFeaD+gnTElTTGdXK9Al5eFBc5TEl2QlqWCTeFBgmdEkqzBRkkTAkRInaImhtCpkketE8TFelaZkk5gk7ElHOH2BB/hGFgkPrEbAmu9FZInL7Fdy75Zg4BLXEmt1EGKENgk6DFNgnRQkVIl85DZNHtgnXrG1ImuxCn7G3AlFAn3AnOsF9kGMwlkt7DkEswk2ZHB8zDG4FQl3oEqVSeBGLkE0YEcl4LkEorF6iCjnK5BGzkl7kEeUGHoEbXzFQmQBGQlAUuL9QlUUF+K5MJjdQk2ZEGcK9UikuF7klwxTEUHlBEQK426hOWHcBHf1EENLiUECBEgYGmrwyUF+DxPhHWNEHkmYwmwUHfklrknG/q9qHWNEoUGiuGE/ju1bPkl+uGqBEAI5+FipWFpBEa0Fa+rKLFxBEXa7vMxPkEeUFTa5fXy2UHMBF9a6JMplWFIUkbrbi1BpvF8UGFZF9aw8UEOBHlXHvrZaUGuBEXaEEI5YUHLknYUkgUmEwlAUk52RgUGBBHsZw0UniUHqUF0JwUUkrkFnQkhK6e4iwUkHkFAlCt0yiuFXknQtapBE6UF3y5zcihBH2UEvFBSUm+TEXDrDw45AQ2uGPkn+w7CUmHkk2ZEjqTTkm3kkHSx+dY/kGVqFta48UmAyRbaHUlAAUFFWG585Jw60UkewSfkA9raUUkwUHUUkrTz95DrkkScxYUEeUEj4lv/H4PGYGHjN5trAFUG5UHlhyrALVMBuMixrCroaywl+Ukj+SiwmzXGE/G7C7E/GM640om3yFEhHuD6xUm8hFKDanPbNyF/BGBDajbxHBGIlQIDYpUnr8FfyExUkf8Eb8HggnZUmHeTwCHN8EweEpG75Do3wlTXDGjarQ7DCqjyExyENpCBdo6MFMhGNUmJUmXyHtQ7cpQJ8FLyGuQ7A4q/yGDyGkeFxQ7+YT1UnCDZvQ61AztUlyDa9UnT9HAhGBQ7wgSxdZrBHrD6MhGZTxQxEIRZ6Czu7E7yEo4StWhVUkVyFOYRtUnwhEDUnxCaaeFnBGvQ4ajBDUnv3LhrFf9aTUln8GYDjeDYHUnU7G5mE1h67Um3Txy5GMESjyrDUlyh6rjKyIlshEVh5ACiyInHBFf9aCQDOGF5UkCUiShEj0qfNEPUkFUl5mCYhFlwTSkJdiHdMEXUkw0kICFkxE7UkQ0nDt4u5FOYQ8AjVyFZyEVh4A0mg7E1yEK67vcjh3HTxKhEnsh43MK0hHxUlCIT/rRvUkIDYPSQ7qpvUmGh5WSTL8F/UkwwTggFdiH/yHZGCnJzjeYgKEU0mBeEQKE2kkKIkWw7ChQqhFx7Fca45yRIKHoDFPEmUu6C0mahHdTE5FYiDG6hHZ7HJkkQTDx4A0DHV5Ho/a8DExkmpqAWDAq0mYJEwKHBImhkmpqCthosDF9Ala+GGSEsKF+km7BAeGrq0k60mW0lmhGCDHm0mKw420kxIlmxEMMC60kxIl2gm1klFFbK0nGCFpInIWEZIllglL7HuQmOqC5wnaKHZhE3EnNkl/rGNgkPEnNglukkO5BhQ6pSFH7G9kkMZD1Ilzj6fEn9gnb/Y0c52GTlZwlf6Wx4k3rviH61BTFEMx6Ywjil41SRak5W+zZiTrFF0mbwDaF0mZrKopxkviViEZ0luDHjP45FHhhyN0kOggFFFtrAYSLX2ElFFIl7goTtDYl0n10lU/x50kPSSl0mD0ls8750kj0lqkBGXwq2EF0lOvZN9H4FYpgjhvZbDwrtFb2qpMHhrBgdBntFRFGL0lKYDL0kQDgcZbB0Ey8LT0nwSGpvZM6SqZx1XAUJy5nan0ngdFfZC6XrL0kAtKeK4xZRzpztswblxjUGxFHD0n10nwpqbtGb0ndvYdEoV0nmOBix64WqBOE8gQAcHdvaN7BoOGnzDZw7dva90kDpwUKCC7xKvbxlQROHQEmaVEgMnjpYwlFIlE/CGY9EFcRgDFknYFdEtvK26FHRyR2F10mMl4v0mwSHj0nv0kS6CgdFopwrDbX0lL0m10nmFwrFFwYEt2GkMlEMl0bBd/B82Ez0mIkDMdEr0meK4/0lsMlH0kK1YftHZ0nAK6gMmBdEpgiEK54sBQdFcMmSV5CsDPFGEMmMK7Ce42dGSMlzw7r0llJy4MkTvZVawEMl0MldvZ8UnEdH0GJ7DaqUjlqyh2GZBqoTZzw5Z1itdEUzxKvbS1bztFAdCj95za6cMm70kaK4F4qo9H2MmEK5T0xWMmCMn6MnSMnvFFv0lEMlnEEyMkr0kuMnkMln1xG5bzFELMDb0n3dGqMlKvZI8yVDFMMmMK6uATBDExMmRMkiFKZdERMmHJCM17gDbBMk79G3N4YnZlJwcwK+K6W1A5dHxGB2OGpMlF0mY5wwwAoD4mUnSbEmdJf0lZMkbdEr0kjS4ss709FnTHvM5W9HSlGO9GK0kP1AtMkq1KlEn8J757FlOEa0lINDy9Hi9GsDHyJA4P4K9HtMnGYBCI757H1OFiCEa0FSjHTMn9MmJkE4qwClF9OHECGKjZ/+LegkS0nbt6zMky9EzMlYlHi9HG9FVEmSV5i9EKlH3THyJB7MkT2ISQnLAmeJCDNwW5KalGPrGHAl+0l7OHlgnbAkP1AneBGlFisGFIl1gnFIkIwClImOIBnAkx0nPhDsK6hGbzFKR9E6TE/eG9gkWDFp0mf9YE6o2eH31EwskXglXxEytR31HlxE4Il0BHoQmTVyP1FwskVTSwslgeF6DYalyQeFn1EW5HHlS7gmPxGfmAj+SZxFnxH4smwskosmKBhIJE0smrAKZxFP1Ehq6KwhwJGjjho5HEYEGGH/1GFFyb9RQNESDapzzsNFn1Fyl77UoIBFseFFGg+GHgQkaDb9q7ENESsl4sm0rK+eEE4RYxHq/bpGEkNH8Zzi1D6gkyeEfq5cEkKeGKsmaiiJeEMQl8FYX0TieG8NHjq4MskcQmfjgV5ZaMR1GFSGFRl5jFx2arQQlX5iKrG2smVGH1054tFjFxRDxoQlOeH55bMDE2EkdxGp/aI7a+slyskENH+nSG5YATDRGGyWjga6hsmcslrgnXq42/b+sl4Qnb5YPSxoNGUskOUkkQlcsmjaTvgnJslM4zSeE0QlQHJasn6skO5alNJ6snwJEhsmmsmCNF40H+5GyJGVeH8QnEKGVsmcgDCQkrEkXDC1sn9gBEJFHkBNsn/Em89HDElJUAJxiWQllFbPsyWQmdslmqA2lzaNHG0nysr9sk5kliWB3GifGF8JFAjA07qRQDTskNskQTCOUo9snMTBLsk2Qmj7EDsmoTAPuRKJE+NE0a7RTqVeE7eFXMldsmKJH8OIgmEe0HpIl+QnVkmvrHnEmd5EQgxGJGImEb7GHVFb7GRQk77HtkkAsmXpCTskWKHZNGgsl1Ingsln7HJQkX7GfOGT/QT7a0zHWE6bL5ozGgcm6ZHgXH/lB1hgl3HWaEti7rJIV3GjhFXmHiYJXXFUzGsp6epaoclYzHocljzFYzGyRAocnbXHosFwmjn3GkUFmmExlB1zGxaG7eCtHA8zFUzFblDAQxf3Fwi6IsDZzHuzF35b4U48ixg3HQ6H4U74cnaXElaGcclMzFpRGLI6A2axZEqzH8o6MclrzG73GANa0cnwCHRzHosFUckVZE0cm1O7GzHGXHgW4zZGGzH1k5NzEmzG/m7O/ZozGaclOzEMzEvzA9ZFRNYizF/iBoBSDZEgTR4XFqcmfLZHaF/bAij4nBrAXFEXEbsyszGEXHa3EDsywRyjZEg6QnC6wPqN0FxZEccmeclWREoZHPC6/CgUolc3HPC5Ecl1zF2XFJJwYclwXH48xgcmczEWZ5ScnSXEui4Icmk3FGi6xhhMcl83GVxa/eCB4CRZEz3GJclmZH+zHuckui50clOcmOBFU8wxckBREuCyRcncckXaF7sxkclG3HrRHuZqWcn0GwSQ4DszGbzP1ZJREBcmtclBXFBBEucnqcmZXFsj5lVoZXHSREVck0zE0cmg9SQcmqcmZmBSclRXFo8xJcl+3EaUEOi5Zcm5XGlognC6pclrzFFXFKj7EgjJzFNclfRGTcly3GvnGyi7fthRzE4ZFuUnfvFPWG/vFKq6huFfso0PH9sweNCbZGnzE3cnv2AXzEmOy3clPckRUl3zHb4nhyEL0CYrTDgnPQC37DwQkfVEG8SwNE/xHSSGgNHmslX1aA8mpvgqslfcnisnxsnfoB/cnNxEW5HN1zp0DyeGksni6HReA/xFLtHfckY8lgwDisk5slo8nqslMskY8EnEA/uHfgnk8G1JSFxFcsnD5xAJG8skbW7k8kk8lsslyFbO6FDxE08kzW7TLT3pwysmc87JcpNxFceFHxGq0CjgkLgly5GYdFoslnxEsZZ1UJINHlxEvpaqoH/xFhAhV87w8mMGHhslV84vqyTgkDhJYb4q4G71Gu6LZ85I1TYNHPRGfCEmW5S8kZGG4slV87cDiZxwrxE08FNTCMNF7gmc8k/t5wJHmslW8ls8nweEi1iFu588lIJFCNF28n88kKbZExFMdHysnINFyxbx2BIQnasls5E1TAW8l48la4GxdYyeFJpaLgkKsk2cCS87Viza8n31Gm0AwEkvgmRW74QD8GEi8kbaCkBHh8m74Gzgn5slV8728ksQl85EJ8nKskbkHlsmZAlGoCQ+AWNE9GFrmHl8lCQnGjHjsn5j4EdykJGXMkXeCzeHKNEdsl18ltpC7eCoCr3GHzeFTi6Y/HDsn60lfoBYrbyQk98nJ1EzIL98kLMkMsBKmBTsnmhFTi7JSZzsni0kdknjy4X85aQkj8mJtZKNFrGFSJHjMnEYDr8n7snyJHahE78l/GEe1GB0ll8mwqohNGaJFHEmKDFbAnXsncUA4k4hQk3eFhQlNknBxEtkknAl/MnlIlvsl85DO6GrGG4mFRcFdglU9DwzF/sl9gkpQkuQ7gLYgpgV8EZ8ZuLYYU5E2GIhJTFHgLbMJSZ8FlGyy2ECTGUhEBr7DtGL5LZ9F5yGb0kgCld9FtiFYDYlsGgCmfBHW7qJsFKehz0m5RLd0klsFURR6wngCn8LaB1RZwkkkJuLY0ClQCmcdK7sFy9Jmwl0CmHsF+mr39HYYAp2EcCnL9FsClhDH4EJwdbQCnJDHWy44bEL0l+2FByyEhEwCkjqBryFn0kkLZaMQTiFJso9DFoDqgIlsClyClrRrNUlMClD2FReqZxxCCl92H4CkADHAJjj2EpAafBGvbRa2GzVKcClR7AdXaATpC2HG7GjbGPzEEbEoClN2HWciMCnbIAJ2EATBpwlh1DFDHqCkECmiMk9drRwImCmGCmP2FVc6SClZsHklJOwmaCnwOHEDKZUllqKYRH7eaRbHf4QLDGP2AQIlbhKrDHlWAfbGIEhOCkUCm0hENur+fZERLv9GlNLZw6XsHr9EOUlocGkCnBDH63LiOFhCmACEICmscHaCm/wlUCmP2H+CndwmVCkHALL9HospcLasfHX9E5Cla2HQlL/2E4ClkbH2fEqCmYCmDCkBbERCl8OECCmM0kNCnltp1CkGCkUOHOCldUkJClaOHGCnBwn0jEwPicCkZCl8OEiClAhF57ybClt9Hc3Ib+h8OH6Clq3KW8iiLZutppwmS4TiOGLYzz9E1CnwOEUN5xUlSCksvBDClgjHeCkYClWOGtCnT9GqCnPkbP9EVXIwCmleLfCmtmDDCllXRk7FUCn+OEtzY/9GfCn6+LIIljCmLNr7DG1iE4dERKpGwnOUnxOH/fGjCkGnwsjG2kn89ECjFIDGqIlgkAijFveIbMmL8mYil4ilUdB9AnZOHy0lW1pb8kbECujF60n9OHptg17EL8nv8mzC7KjE0ikLOGDcFd7EEimMin89EPOGoCFm0mtOAp+C6SH69Ebsnj8BmjFOIkcbBoTGySF20kLsn4rbiinT+JzAkSrYyikJ0nOjHkDDUikJhFySFVkmSTFXsk+gk+jHfro4BLr7GfMnFkD1gkR0mtklR0mvslcDEHcE6jHMioJ0m/8l5iHsUAACmQslAClAk6MIHssgZQkHkHy265vB/gmMwluin/SwowlIUkGMFeDbFQloBGE26WrouBF0UkGMGlNQ1QnAZGNUB4+QNQmuilRilJZLqUniMGFUAThEFQnoB7e1SnkkxMHJxRMBF4Ul9+6yRSUuHZimt7zXbIPkkTQmAB69uykuEzQnO26gZD3hELQkPqF9+7hikrQkiUG1inZhwOvE4aGAB5CwygUnoUGgB5s8yQUlHQmgB42giwUk6UE5im0saIUmQBGpimORFJBEa25lNBDhG8UFPQlCB4kDbTWHUBFCB4nJJpvFpBFCB7xDZ/Qkgwkf+49vDSBGkCae4QFMFfEhghGeimtrwFtQTkm7MGZrw+VYnimVMFLimfQlYUk9MH+ikIUHlik9MGZilMuEQUELMHHiktBF/bAncn7LE/vEf/FOyERFAJkQhUkByF/ikldKSwmUPH6JzASm+UmASnZiDgSlBWRvcl0vFRUmk4GNVgQDHhGGxlGISkt2GxeFNlGn5jnfY7xEoSmxqDESFKLoRlFX54DfZQJE4SmA0DhjazLpYDYMcBISnqLpwVHOBDvm4G8l7m7FdaqVxyMFBGEoSkNXoUeGvtGUSloSl7Mj4IlWHTMSncSlfwk9/4ROHqLrdlG7uAV2EsSnUj7CBAEz7ESkhlGCSkeGGI0R8DaQuht9HoSkSSkUmCQSGrbH1DbE6iXpYZGExf41W7CTD7DHprrKFzbbzBDFBGHcVE5qjH9HiSlGI5HvxxskcSnIJTXbEmSkNwnlxQXME5roAcEUTBrKy5xE0dHMpzp6ggw4WeEqVFCIm8Sko8laJxoI6uSllbEbkEhqx+SmhMgk8mTdFTxxlwJ2SlNsjuI5WSkBSlGdFmSm22HKSmWSl1fAUSF15BMVGBdaIaBiSkkdDgdF6ijbFHl04CdGBda8NIRFFFSlbFDFdbVMSxbEWSk2dYJ0LjwmpSm1SnpSmzgnCrwSSlgMhmbE1Snn4m0faT5wNSmv4k8WA92E9SmBdbAbJG7aZSkrDasaxEDZ15ATlGDSk8lIwFwbkFSCjRdbB7EzSlVLpudFjSl3uG7xJBSlDSmN0HUSn4DbrWz9SnySlbxayMjtSl7SnwQ4+az/FH2SmyZym76FSktSlGI5UsD1SlXSk2dZs8bVMFnSlIEmIsybSmEDaZFxJOEpSm5MQ+D4fSnjSktCgBDZdFCJohBsnIaSDwkPSnWSkUdFhdY3SnKOHCSmyDbwiQhSmnzz/wnKDxFMH4SmaVFmaxe0QcQnHDTSzZmawlbwBSnlrSdzZYymnSmZwBB2GoyntSl5Smso6FjFh7EjSnuI7VQghSn8Sn3Sl9Sl/0EDSk/SmrSlR1SI0DFdaNfrDSl3Sk9dYqAjHbHISkSSnavAnjq8ynXSkJ8hoQm0ylcyn+SnweFRSlIEkKgTdSlCNJpY4Jpw8ykFLryImjmEYlFIOAsh58RKV8n9cEWcCvoYaJF0TFCil1wBqymleE29HPJ4GymVeH/rwD8kfJ5qhTayn6LZ9AkEeJWynONH20lW4J2ykKQmNI6zVJ8RL2ylSik5Im4DjqynzslfEGDUD7DAGQnmymdSCuynd8njEn6SDBynPGGb8lVEmuWRWylfGH0CHRynqykHsnZIkWynnPyH4LeQn3MnAzGPMkRNHPMnX8lzcApbRfxT9gAJNG1gkGinfMlCIC/Mm5ID/MlmimS5DLKzhFSfeE/8kQbGHTCr5H2ikAcnbNZHx7K2FQbjMDaIK6OOHtym3Q7bQmw+HtxBcj7F0Q0gRBfHRiB6jZnx5C2FFTipsFf9YxMI4+Gz1QzDagrzESHdykKjbzymk+GzykKjYGBp50n9ylwjYo4SdDH8fHMDanhGj+GrynvUlj/xSZybylrykF8Tc+FKmxcb5AoSxFGIjgHW6fwSsMl64C0qgkh5wsCxKE8l6fI58IRuDErTjMjaGh5iEgKfEerqxQ7b0yQSHecAAcFf9bhAHNKHL6YVh7HynHKEVjRnyn5eSjokwKlAHF3lbW+GHymGh5QKnQNwIKmGh7ZsTpMkAiZXymBnIrynITxJHG4QQHylPymah6eCimYkZazvyljl6T+HPHTeDZEKmjokwDxkHFuawV2F3mDuFwk0lOrz84HrI4zDb59xE2GLynQHHx4ZyMEsKnGDaIWG+YkMKlyz6/ymrok0KlCKnPDgl+HzTiwMlUBBq6S+Ykjym/7H8KlvokUKnP7GDaTp+GcTjsnyYKnsKnNKEnyKNWFMKnx+FvynP7FwKn0+HbQmjylUKnkKmOFhK84zKHfdFEjj1DYPZF7zLIKk7tpkHHcbYIMmnyl8KkrEgqdEeKlyz5gKnmHFDDbcz5IKm++GbDbqYn/Lh1+FwsBco5gQw3yn8PCb97qYl+DF6Knr2Ryz5RJIzokYKmhKlAKmcKkvHH80nYt6WFGdXH8wkeUkCZFGw7/hTscD8jSN4EFVKdXTocwTpAb4rn6IcZilKmz7I+OGb4mRUl+yDM87q4C71HlxEtKkaGGE8mOtA5QhYjYdxHBujoEnosldKkL1EqsntKm5xG4skUnEehgdKkIeEsnHnvCLSlTKnjKnNZTs8lnxGG5CLglLKkc0Yz1H31EhF45xEs8mkAqsvBWGFf1FWnEGuyoUGkQlG/JidyYJwyeFPI67KnNxFCslKfLo8lseFynFA8kc8kIKH8ORINERGGu9YPtwism3xH1nHihL3gnn1F2nFfEhRsltKm66BfgltKmyK7rKlXxHyiGpxFLKnl0RMEnHKnEsYW8lQqk9vCgCHnKnQxBfgnQJHDYDu8nFsns9YzKkBSlCNFNy4EYliNHG0n4qkFeG18k+gnxaCrsmGylN8mXZDkqmmylkJGUikzaC1Crj8ljAllK6MqlVEnZnHD8mhynEKBZ8xjsmkqmUBC9vL6Qk+ykYKCrPrz8laIk8qnY05cqksqlLqDiqkb8nuNGsqkDWr6QlOQljAlSqm78luQkvMkwe7RTqHeHn8nnsmfTGXslX8lailZKC+Yx3smFylh0lP8lGikv8nlylv8mVykXAkcOjxQl1ynvEmNymp0kOikCvalV6UzjyrGtNHOqnRAknNEULat9QREmKglFn5Sta+EnsmEHn7eqn6kljiFnsQeqkEAkWn7HwoqAm9NECn5E/CCAm9NGRqmGUjbDGTNHSyAuqmSkl/hCJDhn1xtmFfba1DF1mEGXaaH4qEneAk5PY1Bj/jHctF/hBj2zaAlCtH5qk3jFFqlfPYV2EVNESEBHjHnNFZMGtzFBAmcknNPa6mTn/RkEkLPbfkLmbDMrEdiGdqmQEluqkEiHAlEkgnBCBuAndqnjqnEAnDqm6MnagmlrHHz7iFSygk6gmFpGsECjqnWklcQkqylOZbysCgTGOkkqU5IIkukkcimWql2U77qmekmsSEnqk+klOgnt8nMNCbd4RkncH4y063qkOylDhD1OQPqloH6EPyjAmHMlEXYzAlUTGqSHfXbhgklkmKSFvqkvqkhL6AalHrGTAmPql/hA3ML8TEbEmvqlHoaLAn/qnqdBl5zt+wHEnrAkX8mejG6qmbMnwiBpjB7AnyTGP8lxpH3EllImPEmEilgRAVOBXAmdgn1ynxxF6TH/smnnEWpa2qHEPgXimBqEXC6OOGMwlOqE+KEWBFhqEUYBpKESUF4wlBqFyMFcamjhEpqFtqG5BHRqGJqHMakJqGcak3ikCanviFsamZqGcqGianLqGXklbqFyJjFqHlBGTqF1KF6UnOREjqF7xZFWE1BGe5obqGfe6LQldqF6WGrQl9qHsqJ6WGbQl+XYNqHDKx9vEdilAFpaamkwk9imqakkV4EUFzqEHqH0akyakUSHjikcprBu6PQkuUFeakIqGeakJaB7YjXiksoGPqFQgjrime4SPqGmakQuH/Qmu3aIaEkV7OUG9YBkaFTqEXikvom1fHvvG9DxsaFUvzwl5hUETXZtaB6ak7inhUEWFE8aGbzFfvFfilnck/ilCwmqHIPLFDBFiOan+IgSnlkbVakSaFVanhUlZolfEkeJHfXQcaGeik7V6zLH0amEX6vpgluG+ilvn6ALG4wnG3HvBEdLF8anhZ4Sn48LHZingRDDam5BFDamtaQJiljiE/QowLFYUmRqkhupquEzanYHperLDQl/hD54h5ikjimJXYtLECgT/pEAhG9LGvFI1BEcvYGLHVilPhGFPbEihGakNinMED3anNim9qFXameLG7Qk5ZEcvaMLEqBE9inlqktLHOal7alKLG9amT7bqLG3QmFPb0TA+imHanDpDvanlBFSZHeoTBalEUnFqkZHINvGI6mDPbjal2UljiGjlFBLF0UnFqnm4q4Unmam46nXamkwnKUEEvbfanSUkaUFo6lgLEQBEDinMEDI6kCUnAZEePZxLHzamP7b5LHU6kMZGyXZpLE8wkhgAdqkbanpiljiHNtamLGeimhxA9akcwl5z5z9JWLF2UEU6kbo7jakKBGfal345k6kyBGvany6nnameTH0RELPY935CUFGUldvYbo7HanWIwLpHOOiVSGw6lsyBzalG6mPVT4LEnanf3HTPas6nyUkIZFRPac6mq6n83F26nFLFUUn86k+/oWUEZAoSQ4LPa86mMUlIUGbPYm6np8xxRELPb9akBUEYyhHPaauS0uEE6nq6no6k/rCe6nK6nY6kEdyzgCfil4PHfimCwmCZHX5AnLEQSmkPHp6lJJL1alZ6m99qNamSZHZ6kF6mwSmulGMPEYp6ep5CbFDolfMCJ2BdymYfH49GwaErfHHl4y+AxqGXfHcqHHtE/eIIqFtfFfl6T4G9KH5onN6mJqFV6k6cSE+H5olXzCCal9omRp6rHYUSFDokVlBZqGN6mZl4X/z/2GTokqW5kk4XKEBdYqW7F2y+YlGfIdfbq9FWak6YnBYmem4jJDZKFbon4U6pqG7okCqEXm40bwl+EqAglzIhm5u/zTKFUPjnonL6nJalXom36kutyL6l16kz6mcqGyqGRp7Wpid6nvom/m6ualz6kX6lw9q+fFgCRr6nreDtLpBfFWqybXZVk6z6nhfFt45Vk52oxsYnsqGem5e4xQYkJfHm46wGlf6loqEfm4m7rx+Gg/GVm7khzYYkZKGZm55fQWfGQqGtczeakv6mem4b6lkYlvfG8W676nYqGYGmL2KMGnDKH+fatcxYaFd6kX6kP07IGkiYmkGlw0zCz7DfHAGlEGlcYkxYkQGlJzB6fHsYlYGlT6lpYmoGlIGnSYkLfGRm4r6lAGlTm5Bal2Ynbm6QGmr6n+fFLm4SGnNKHQGl1l5t0A/qHwGki97bqAcaEzYmZl6mGnOKGPfE4qGRm5oGnxfEAqG2GlwGkEGmLeAt6l1YmRm416kHfEUGn6roLKFVYnbm48GlJKEOGkdZycGnWGnMGmUWb36kg9oGGnrLQCKmyGn48zP6nmGnbm4eGl5om7fFLm6uGnRYlqLZjsxOGlqfHbm52Gmt6kSYlhmFmGlsGmPvZFalIGFLZFholw/ERolrZEWX6iPaPymmqFVGmn+Lo/GHOqxNCXLBrYmNGkhKDNGn4/GtalQslM058tKaaElpGsNIu3FeZHCtHCISlXHS3EOxCOBCwcnG3H7kGBXH7clYA4+dAkXGtpF2AbVpELGlyTC3XG9pFtAYkXGPnHur7barEckbXHCUEU3GjpGeTGdaEfXE/kEoXGU3GrNFh0FA3ET3EEVKg3G4XEH/YNdZw3H63HfWEPXGr3EaA72VLsZGUXHNr4dGaXpEY3EnGlxzFMXHur41rixXHAZF7Gnu3EX3EM2Ak3HwZFbaHUxDbGlhcn/pGPZA03HfXECQAM3GImlzLDTGlnGlzr4l7BA3H/3EgKA3GntzFq6k4mmC3EaXHUxBfGkL3GwUGmr7i3GDGkEmnvGmjGnU5CG3Hv3EnZAQmny3EgfoUmn7cmu14+5gUomPGnr6ZNXFq3HlXHh14DGlugDq3Gc15Y3Gkmm7pG0mlomn7XGu14kmkZzG+6nU5Cm3E1aHLcmSml0mnyREU6lCmmO3EMZEo14DGkLGlcmmoLZamlLORVXFRXEM16UwhqZFhXFJ6m2FHj4nncnjN6XNHyIIJ3GSZGDaDR3F7ZG2mmjTLEPF46GkPF2mnJ3G3zFwSlNKmM97eEC2HxLCHFsE+mmsVG8cHRKHb3i8mimcFOXY6iidlGBsHDtHszGDlEXsEBmnOVENeZkbFpXaBmk92Q8qFJPo9sGScGbsGyXaK5ENsEW3Yuc7flF5sF5XYpmmFmmoXZ/VF5sEyXaPnzyUgdsEnfaVmneYCmcEVmnbqkmTRxmm1ml/VHzfgnfb0IkScG5mkyXYpVQ5lFDsG+2HCY6lhJQ0E6lJ6l6ho6YOrrsGU2FbgC+mnxsGsj7G47blD7lF5eiEqGLnZVmlCsoU7GTmnZE6IiHdbDd46ETLLlHrZj94501bflGesrG47PwmYcElmlbgB9GQnmn+mmq06kVGnmlpFq0VG5mlHmnuVFRS63sGTmkpmnDmle3ZlRollFWYhl47bmn7lEkgiFfYvmkJmkqEZ0qFJlr/lFRmlq45WkBp8CicHgWnnmnjml02F/fZ6Lphmlk/YIWlBmnE/Yxh45mmnmniMmKcFgWljhF65hVmm8cEDhFqy6kVELmmCqFnw4UQAIcGgcHbpwaC6CcHPhFjmmIWmEFzuVEgcH6Xa6wlRCFgGoRfZzmnJCFMHDm47aSGelEccEWIBsWmsVFFdwg44cfZRYjXsEixqwMm9fabmLVmn945nEFYWmpmnvhEhmnk1Fy3rR2GmL5lsHGlawm4cfbYCSoVFucERfaaWmhTFfmnNfbq4GkVFvmkHhGlVLkcHTgbSWkF4qyWmnmlLDIgVHWWk/mlmWmLFYyXZtP5BTGnmnOWmhTGuWkQWk7JH3mnMCCPmkUcGYRH38BTmmUiHDsEBWlRvDkcH6WlERHsWl4cGjbEBWkpmlw0Q8REiWmhTEJsE8RHkU5eWltmlkREWVI/ZGsj4G3YCGZ+mm+sFN764In1mlqRFRTJjsGnmn44AWVH4WkK3aUVEl5E0OGM1HIWk4oLxOH5Wm4VGzNLoilZKmZp5VX4zVEGIkG9F6YhZVGipFdEknX7dWlxcEFVEPX60viDWnm2J0qlx2A5SnDVGkinnkDHmGpcFVElYCCNrHrTFZOFBNaNVHwalE/bfpypVG6xE1OH/tGp1GHqmbTGZp4rWlTWnLWl7MhZVFXTEeynd4AnWlxcHF1GZxCXWkLVF7Wk7rGWhA0C5T8GBiGyiHqimZImaikYamYCD/tF7VEt1ExpFPsl3ElgzFJyl4EBFklXVEwzHkalOlFJQmACnNynwXbHV40mjN/Fs6FKT7dqwKDbr6GI2lx+BZ4l66EyXYTSCiyE96GqXYhwr2LEl6Hu/zBmnsSwgHEF6FIJBn3rwGFFKFY2m16Gk2lZxAWpQa6EY2kMXYOfHQGHS6GM2kA/FG6HrKHzggAyHs2lwqGn5Iv6E26H944oO4uLGQzZURTdKF39j6/FD/Rt45EXZ02mmyHNuRwqHE2lMHGD6Gi2m6fHB6FfWIJXaC2kBHGR6GgqEo+BKyEycDroHUXY2fEU2l5mktLBoHEM2n4EA3fHc2lUqFM2mP6Gj4D1OBzfEE2nK3Y+8ps2kd6FwqHLYDPYkoRRaXZHdRWLF+Nzu2kgE5cYKdHGy2m+2nm2k42kW3bc5oNfF+6EqSwgE5i2nMyGG+xcWkMXxC2n76G+2kvTprHF62ltRHYqSG2lUqHk2ms6Gq6FQqFM2nb6E22lxfEM6GdgLdmlA9FQGHW2nMQDK2n56EI2lS46Z2nM2mZKnKynuoDvHEw/GncmrZEWmlaqEh36s2K4GGGLrt2nE0BEGFezq0JEd2lUGF92nuDQD2lmbCdGmOqlVlZBjZM0q7qEbXHWrbuKHT2lEMl4BqOOFnqGr0nQAiJqEhqHG3H4MAycTaDbr2nhZ55iAjzKZnGB2REMmr2lpKGrqFKvbH2l+qGfqFEMl1eLdqGH2mr0k9oH5qGMaFKvb32krqGX2mMK7BI7/2HL2lP2lioBIaGDfTf3GKjbEqFXqHAUGY4F4qEM8Evikyjb72ntqENingOmCanbKwtilrMm76mDqEdimY4EAOkucI4UEjLDf2mwJwzqGepwBWGnqGP2noOmSygrqGMaF/L55DgSqGn2lSJCEApUFFHqF/L5mVof2l4OnpiCVKFn0FHqFHYFZqTgDaAOndM7FT4ROGgOk1illY4/qEM8GtBHEOkgWA6MGf2l5LBjqrZdbCOlRYHnKG9KycUFBYG2RqxdZQaHq3F+64/2kdqHTYFb2kKFFo2AEM6L2J2amwOmvamzDYoOkpPGLx7tElyMHNyykaFBYE3IoUaGovHTYGyOkuqG32nTYEEOms8F0OnytAcaFYOnTYH6EBCOma9C8wnFGk3WElalN2llakt2kVamCZGqeDc2LyaGUPGBOlKaFyHIByGseCueLBOkROnN2GJdAqaFb4lE/EOKHy6B04Sx4msNCLm6Wax944rSE3BTtl5kCiOOGy6SesEJWAoMkzIobsGZl6Y9pyMGgcSpsGDl5ntg3SGXorpOlLDJpKEnoq+sGFOnESH5OnpOn5JbviGtOnHl45WBWIAXHHZOmlOlFSgUSGdOn9Ok8MnZYB9OmBl6mMmjOmLFbRl6XLKCdaIxA4dH4xEPykydROcG7DCZ0l1xywabR2ErOluDEKHQxY76l5N4gvtZLoqFCkrWwzOlrOlh9ZocE6o4TOlDdCIcGy97dQ5ZOnFsHdOnBDGNOl9sHYoDHOmjOl3OknniDOnE8RNOlyLAt2EVOkrsHRFA9OmzOnomgbOmfeINOn3oDaKk3rDKMnZYBrnDpGki0rlOnrOmZl7veCQSG/Omax7zEQSqHbOnsGkr2JoulmWI+D4/wBGv4O6Gv1qGx6pSCkyF9KGGx5A8BE2GPOntl4gum16FjOn6l4uTAXHHf9gml6A7DhjZDdBgGrkl5lUR/DafOnpOkKYBkOFDOlex5FOksIq3sEQzAROFdjDDsHAFA/OkDoDLOl9OJXDbwumGx7sdJFpzYumYGmrHA/Okw2YCl4DOn0ulXOkYc4tOm1Ontl56HF9iEUuk50kN7Qv6EMukMx5Euk64m9TjVFxFewvOlFYphbEmulWulgGkxY4munAoDDdYU7g2MlnsSXiHItAnXiGx6pSQKDZgunqWmaumgukUYB+unyKYfOlAukIunbqnMukuukoulyuknOnduzP/GeOmLuHeOmv/HN2nw/Gt2nmpDkppAeCj2mHOpmWAC2Ii2z2Bo19EC2Kd2kLOrZukZukkMBKwmJOk/F6gyD8XA5mlB1SD8GFhQgpFBDBbiHBngWVFKehak6AvhyOFOxyckp/L50njlWkNum1ukZKR/VH9xaCmH35EnjpOxzBcSr8GSnBkWm2epTiE+ziUVEtumViHDunALg/LGtuk/5GLumpODLunknTZbCXy5gpi/3aTFZ1JFhpgcZZDwlNbFLumNunzABtFpbunxFEViw45EwlydFGsqAvSk1THbun8GDNKqqcFCOjzFHNHFzsEvukrFGCpjFHyIiFgpiwCFPul/VE1um3YlR9jopG4nx8WmFFET5Y2VGAekQCEQek/unwSHTyKS7HHumNFEIxyq7TnumfFHrBjtulzumVFHoelcQyoelYelivTscG9umvYn4emQWlrumfFEMeAd2G4ekU4kwemoxyNcaCTYadLeVEvBKN4l1lyXCE1Ogblw/7wGcGEekS4l1rBjsFQeniCGru5bRGsel0enEemG1EGHRMelAdCRsEceo2uljuAoZb3ulwekf1LTsgW1FsekkcZkWmYenG4koVy1riIelqen8emIiGIaiu4mojQientXB6ekyek0elSekEOCFsHiVpgemJq6SWkbaChDYp4ngxalCEiiYJ4ncekQpE3umU0EkiFjumu4nSfDi1GtJRqenf0gnCEmZTaKmC4neoI2VEx7gbPYFq4UelZ+BB2GauB+eleWkHywZ/ZIqxLsEpahUMn00GkVG8emrLwgSGUelGemFsFJemsykR/YuRKwem/FHmFw4emqekh4l8FFiVFpelhGTblEVekTultCGBmwu/ak6wa0wIrFIlEZ2TtumrmEtWn12nWB6O4J21F9Ak7t7e1G9Wl6ynD+Bm3DDTHdMnIODe1HiiHjWkEBCwb4rTH0lEv5KnTFrWl8lEc+TTenaFCiiGGxH9TFEam+uC20EbQC7TELTb5JK7WmBylQeArelLWlClGHekbQBnWl9WkOFAnelzw6nMmWFCXell1FA2nFYA0VZvTGuxFaqkL7H+0k1knH8m2uBBBLN1H+xFFyn+9EA2lRQn3elSGA60Gg2nZiHg2m2ikDklukn3AmWDYXnFozGM643nGw+ka5LlpGPnGN4H/nE1pFEzEf04uXGfnFIcnxZAEXGGzFn4FLGlUzH4+keaHOzE4+kbGnGXHKDZ1XG0zEU+n7GmxaG0w4IXFwXGzUGnGn/XGSDY4DzCzFYXHNQ44XHeRESzEs+m4+kyzHNQ68+nw3E9Q6LyDvGnI3FyDas+nfGk4UFAEEOXGH3G7Q7t0BAmkvkHU+mgmmPaGeQ7cXHJcmBQ65Ki/pHomlXpCGJrAXFYzHF0RaAgoPEK+kqYFHXHM+l80QeXE33EsjZqNy83H+cnUDac+lWcnWUnUDbm+nQ3H1Q6uQoAXF80R2+kmzH/ESFXHyXEVh5tHGs3GTaE6JbJXGczFOYTw+nB+nTUJM+l2XH0YRomnBclf9bi+muXE1XEpJYi3EYZEXUmY+nlcnrUS+3F4+ln9E0XERaGmmk9XHmmn+OnaBBGyrOmmXzHY47iZH3cmvsw6JDumkl+lF+n0PEJOnwSnKa4zthtylkfQGwnCDh9iFlzgt+lcQreKldmkqa5FOlNkAlOneRZKNDo+FyWmybZ62ivyn3mk9+kLynN+mlY61PYrymFmmAMCDnhj0l16IcDaARYAukg+EusEr+nxMlL+ljG7cTT2+Hj+mIRyR2EkoArDYNRYvOlRXQkcEEZDe27oKnniIkRY30gbylKWkkm43+mL+mJmm/Zzn+kPynQzgHCnH+npKmAKBBY77+l994Z7DuFx7iA3On6+Hr+lapjBDHt+nL+lo1Ti2Fb+n8bZLFKT2FQBmXG5pNzYKl+WkxbagFYrynGWkTpCr+nmHFX+lKRZmojIKlxWnYBkt2EpvRhbHoBmgBk7aTKFwN1DMKl/+m+Y7+RCY9FgBnTG5+yaaKnj+kQBmqKmHmnUZAvOldzhkBmmbEyKmOhg+D7qM4X+mTcCwMmsBnRKlJWnwBmD+m4BmeukmDaQunwqDLbBFRbUBk9+FAWlFRZFjLuKl3+myRYYBl9+mzwkeTaxOHkSQztF54EYMlwBmwgmwBnj+kQyys2GH+l1Y6VzwXyloBkUtyG2HcgK7wl6iDRKnyBkTUHYIi+YmLRpgRaWBkCKmPKQ8BlmBkzom7mkTUF7xoMBksBkAWhJ2G0Bn8bbY9DgqFBBnwBkPbzlpzjLj/+lZSwkBmPzrIBnEiaT+GcWlUBkFOg4fHOBnwBkfOj3JzCDjaKnxZA4BnoKlCUCsbYxBkHyloBmYDJKBnmWkTUGMYKIBl5sG5+lj4n2FHnN5OjY7ZAdGmJexfPDVIANGl9eAqAhDcAtGl9eDNBnI/Fknx1+lemnI15H8C00lbBHCtGMapG7HdUkOxAHqz4SFfUnCtH7aQTbHXVKBqlC1JGRY3wlEhEjBkS3C6bGo0RdNHSUI0eFlUkbZY0lKr2TlyGWMEKRo8hHDBkO1JrBl00kOxCjBmTCkrBlHBm1YlrBHur6qmSzbH9UkHNFqq6A0lshFYA6p77CeFACH3BlYpjrbF2mGPZCNyx+7EohHUxCyrzVCm4hEaA5mWKHUlLUkX8GF3pGRbgimZmEM16TBngil2MGF3pUijrBnryHghkv8xxsiLJJXMH617ALqghnXBl7GY/pTghE016AKHnBlcKCkhnjUkM16zBkvbHdmEvXpLsh0bHuxyvJFq16bHB+7HShG0vF6A7X5AKhFwKGeVBhdBC0kiqmbMkD068hnS0k9emchnoKEUimHMl15DWhHdMleXpShn7envGDbiYsin7GA8SFW0mHMnd8ZG0liCGFg68+D+InnWk6mDKhmKhmLGB6hnhIlyhk8mCGhlhhHO0kXRCmhlRhHu0kfemLVB5TwKKH4ilnsm+0kXskainoalEami0CahlqDF6im/emGiklImR0kEanR0lHqn2xBqhkWKFWilg+mYjAfEnQbFtamf9ZgxCk/Ej/ExxbmsLXYkD/HxhkWVJZ4lQHF2THG1b9/E6HHJe6KGj14k/7EgDYfZDm/Fxhlje4UYZy6EqHG+5Cn/FK/H9kGFhmZ/GuTFGIr84llhnITJi4noHExxaI4oe/GZ/G/RZI8wu/Fq/FF/Fk/rz/HYyHXIl0UHW/FV/Eyu4IpYQ4nVQh7/EzcbJ/EbeCeHEEVJDhk8HHiLG+TF9hmCHETaodhn1QqRHHiHF5KD75rh/Grhm0GJoHFphmehCs/Hf4rB/HpTGHhlxhmcxatCBR/HKyEbhmUnJQCE2Dys+maxaFhkp/GCk6QxYVhn1/F8LEgfqX/GH/EHHHpxa3/FHhlR7AkxYR5ipOmBHgyu7/7h1/F7/6vxA/hmV/FwzZXHHpxafhndhn3HEvhm8/G5/ESDaF3oH/HIRkxxZuTYZ/F3HFoXGmbDT/HQRkKLF1TFLhl+Ny1HFwxY9JQO6HARljxa4Rn14naS6Ge6YRnqyFH/Ehu65tSJhn2HFwxYlhkK2mm/Efhmy/HOHHM/Egfq/hmyNzoiQARmzOytHGRXyCRkrFgj4qL/EfRYF0Tt/HLHGcRn1hkbhmIumZhllhlMRnI2nNhlwxZp5jrhl8XFURmdHEd/GkRlERntbHdHGERnys7bHEiRl1TGnhncSRGTBqRk7/HqEouHF5TFoRnjhlwoDVBnlGmLYlrZHIDLf/EgAmJDLf/HOIztTI/ywAnFxold9LxQy+RnwnGNKlKa4Y27+rp9kH8JwY6T805/FQRdYRRn/eTp05ZG5gFGRRmEVbnyFydawOlG55pLp9G7A8E9OL7gmevKEdaxRkK6FGLrwm4H2nVFAFRkpRkX2nNDAFRlIIp5Rm9FD/eSvgneWGEOkVRmMl6WzoxG6JRlxRmQFAVCb3cE1RkFRnPsx+dY70GhooAVYZXKUNygOnbqIDRl73oDqGi9xOpbjzprknbKw9GyjRlhNBpqFsrzMVZLzqdG59yzG9a3gkUQr2Om9hbHJa3glZKTmOkvEDbgnthjEUH5RlNRk+dAXkmP5FJRkZ5CyzgDqHzahtRnXzoURxq8ElRm7MGsUG4m7nRm3RnzwFSdaPZ5vRmbrasOlV1AjRm3gkuIgqnF2tikVYr2AtbAKFEJGAJbCEVaqvA1tafRkFRn/WadRmNRnnlay6YQFx9RkmvFPj6M2JYMHICTG14y7hi84YFGkpC0QlKWRDRmImAQsr4xkbRm28FsExHlbYxnb2n4lpnZZoxm9RmpOBf56EX4zOD6UHb5FHlZwxkW8GPRnnlZQxmDtbHRmcxkf5g4FHVcIAVb/s7ttZqKwMxl+UH3RnZqHQK4Z5D+JZkxm1iiCxn+rYvlz+qHExlSxnixnuKxDxByxkDjSaFFiiyfPZJ5AAxmo8HMwS26FJ5D0vA/RkIxmORkCwmeUlp6n7egO2Ly6CvIxX5CWxlYoDYrzfCjRVaf+zkYDXhgByHqtFWxmZTxCAR9BkhRmLi46ywZslHgl+xnZsk3gmm767glTgnUf6PyHoQkO/YUohnKk0QkO/bP3gUQnRsnSTbTDDvgmfKnq1CUIQ/Klkl7q1CA8ALxFhxnJxmueEBxl5xmReGxxn4AgZ8lMslBTbKElXKkJMEgoKkEmkQnRTZwQk08muTbPwzOGGm8mNxnUSBIqllxn5+LSskuMIrCGY25wLZBsmvKmY24UojAJHBsnZ25DxnDgmDxncypwNHtMFNjD1pQ7xEo0Ea26QSDREkPkGO8lBJzaoHsElzgmjxmTxmEskmMFfFazxnLxmZCGbxlLxlpLpPiqrxmLxm5El7glm27kbpgQlTgnJFA6Em1xl3PrUsliGEPxkIslPxmv7Awqk58ny25+7wE8mYqny27oFhudbF8mATEdel4CGSCbdGHVslR+AgJlTGH1snneke+BdjDyNGUqlyFAQJk0qkqNHganOHHLslKB66XDcqkChmz243AJoJk7uBmvCYJnrelYGDrXD8qkz8lxjAceqjQA+ykDeng1BdGEhyk9elm/BLeEyqngan0JnbsnXemgGD4Jn+NH3WlT7EIRCoJln8nUsFvWlvekfWluhnTjAceqGqkP8l/WkRQn/ekvsmA+mNFAaQI2qk5NF2qmUalQ2nUamg9a3N4dFg6kmqJnErF9jHRjaQQSprFMAn4MC3oj+DGQkkgDbaJkpNBH4k9xGa/iaJkRqlejb49olmExqndABrixmAliknWWHNNF/Emb2lqJmuJlyeLLNF6JlFiQuJnzjFrMkYglFqkojYGMy6Jm9yEA451ZIhqlUjbBJnkklDyGkjY34l9jFlY6CDoYElb67py7NqkbjFRYFiUTUgkDUkImZ5rE0kkzRabgSAklTyHpJmFrErNFuDYxdooEm5JmC2HUAldjENRaexgykm9yEZRZO2IhJmFJlaLourHVJmqDQOrHzqn4w7bqDqgn6jSm64OJlJEmGgml8laqAAWFQsGmgl8BCCHRzmGWgmBhmJ5GQWH9rFlAlwqCzJmVAm+kk6hlFqAjJnxgmlEkjDY/+xzElTJn7WlSY4zRZpknzEmfHZfJRAalUJn4ZB4Vr5kkcqn4ZAzjq0THzemIu4A44hkkzmHHJmganZkmiqm4lBPJnnrFyilHJmBvBwak3rE/pAAkprAl39z8JlPMkB0mqqloMDmEENkk4aniJm3EnP8n4amv8mEamcilUZDnJlVtFkakKJkNIk/TH3AkO/biFL2qGPVoK6Gp2ws6EPcFqWHa/Z1s5yOn5Vzc6EO/bO5TlRn9OCQPZxfg17axqy49JJxkHzSJLYEpnL6FodLUiyonGEpmspl6LY70EspmZdxMpmkpkfYAMplAHwNRlx37KTaM2oQMH8pmVFHLBIUDbcpm4plmoJCOmPTovvGiBLLa4M8EWvGlII3XRwaF+WGmTZnvgLRkzWwLjYy7hMpkDtwRWF7jYfNYw8FYuh0TZpgzKpk/ahJWHRTbLIyonEzvG7uLSpk4pmSplipnCpkqvF7gLqpkpiwipmNxkVlhUFEipnSTYX9hb5FOpl6plfEjSpkSpnBpk0K7Gxnxmgu/Z4QL88FBuC+TYopCNnH1OQQxmY27kcziFE3xBdvYdI4CyxYMG1vHZ26skQqnFepmY27EpniFEFpm6AJEDZ0DEvvGGALAHDb2kwKh7OJs25i/piOnJ4K0B6YEjKplJCAach1plVpkKFFG2B8B4FeKy8EopAK6F25aWpl9pl12mZeHdN7Fam7LGlanJ6nlamp6kqGA1pl6JA2VgByGIhTbnE5wELpkeTpzpngYjRek6TSD6yYsBlun1+kiu4AxwonH/0Fh/A8nYLkD75E9HwWjbx4AvcFaMTfcGQlCEnHA8GYIq2jb3agOnFApzN0HDnZwZL8xlnpkPplIbh0nEfpndnaP0R/cEIoGfplvpmo8EAZmjxGvqjxnE/pn0n58nEQZncK4g0ZK8FXpk48F/WGf0EfLwIFFbxHyFFYMGLTRRjYtCg1nG12T+WHiiCxpkMnK2jZ4ZkqnGnsapHZYZmmFFWKjkFGoZklnF4xJlc6IZm9pmo2I3H5QKgWnHQZkkaigFGHpnXpl5TwenGGqyvShDH5e8TDnH7qiDnC8ZlQZmtCgFmBDH4v5In5EI7r+WFi0ESZngcyVxbvrZQZl+6QaDbvrbJnGaxlKoCMo4slB9nFL0FHplDH5Iuha8HwZkWjYwNZ6ZlozzwZ7HxFoZmI8HVpRDH4vMKaxmyZl9H5CKEv2mSZn6H7+FaJpkiZk+naGZniFGc2iFu5CI76STuZk8ZkSlDXgRn1zcZkweHKZl4ME4az3plCZlsZnbKzHFJiZnTnFShZOODRZnVMHNyzq2w2H5acrgZkiKwUFbBZlfXCcKzYQifH6aZn8JzaZltH7eZmP5H5ZkGH7SFHzrq2jZOZmUOmyoSWZnynF9yxJZnVZk1nHSNyJHYVZmdplRZnnxFPplpiYonaN/ZQmiQazt/Cmxn5Km/HF3BxHnFO4LOlA9PBLplB9KvsyxrCcMGzVJEcyDZnrnG0MJj2nQ2mS46J7qhgjFY6dPGTfZjQBtWADw5rZmgrZrFaUQTHp5RBD+fbmnp7OiJ8EIQowT7pOLMNjHp741j/47mnorZl7p6ovG2fY3ZkXZkrBb0/pnZmYFhk9z49YvIAIT7nZnvZm2dCsEowT5NSE/Zm/2nXZldZipVQVw5cIAxyz/ZlbskLY7BdCbCyQ5l4An9T6mPHzuFDJlhT4B6KS7CkuDxoFj7Go5mpbDDhAFIhIn5NXq/YxRAA5uC45kcbDfdzTkDo5m45kV97F+AtYzzI7E5kSrak5l8I64OKir745nU5lGaER3ZU5nd2TWnLKW7s5mNvCc5knNA5uo85kY5mU5nyyBk5lE5ls5nC5kM5lwRh45mS14KDiE5m9hZi5mOUFSbA45nXX4jEBaKm+Ajk5kR3ZI3p2gFZoBK5nKW4vXojRBvhDq5lgkAArABeA05nK5n/EDayq+3CG5l85n3m4ObA65lM5nU5CPGAnABW5mtOBXfQ0pR25nPX6mkDrwB3rDO5nvBBe5njQju5l45moRmuEyy5lEoZG5kSqjBRgB5kV96F3oeXQB5n79BSQKpbDdfZm5nhkCdua7yA+5lx5n1OSSfCR5lfX4nZAVAJ3ACi5lh5n6+o+7BZ5lZkGHODSBJBAhp5myjFl5nH3DF5kJkEbECzRKCxAV5mz9D15l87A15kg4FsjFLQTCgiN5n+cEd5nY5my0FJ5l15kbeDkvRd5kxcGD5nV5l95m65ncba95mM5mtOCT5kGm7jBD95k3OAh37EWjD5k3eoYjwS5kU5nZ5lFIyXoAr5kIurfLBTSit5lHt7XNCx8SonA75mLOq8eKm5kT5nF9BAxyn5n/BkXzQX5n25kK6rzwA35mP5lZ7AH5lYn71xDbTGtdZ8AD55knNCZ9xf5n35ke5kHcZH4o35kbFFx7Bv5m2z4SjEenIi5ly5lgkBQFnr5kL5kkuD5EjTnCx5myjFIFkJ5nDn4IFlTOAxJJT5mS5n79DYFlz5n72a65nPpnQFmh5knNDEFnwFm65mQYDIFnj5knNBUFnoFmEFn25llejUFnT5nvBBMFn0FnrwL25mmLokFkY5n79BcFkUFn25k5uDMFm4FmyjGCFnsFkb5kl5kfOBrWY4Fm05lr9BiW4EFkcFmAFkz1r/IQ35mY3TSFmYFmb8BH7ICKja5k0FmtcGgPDTnAoFrqFkDADThJCFkyFlGFnuAFiFmGFlXACIhLcwin5nWFkmFmWFlejox5k6Fkkra9d4WFnKW5O+b2FlUbAEOD6FkYFnuFn05nf5kwFkFcH+FkAFn097j2mg9aJuFHNHR+E0bQa84DBZdykhmQxyEMuEQ+F64BEwJ884S7Eryn45ip5b05xN+EujAIDSpuHjBBj+kpFka85pFldomFFlWuFPHArymlFlysBwrSP+mFFmS859lJT6nxFnN871FntFHWLYJFmKNBhXDQNyVFkdp56+G3unHOT1uFbEwkMmrd4fjHV6lQgnBHGZcj9FnVFke+GdQga85MAi3+mUfCC8FQwxPAlzwmOsnikEF+GgqRTvD9Flf9Qzok7tz9FkAxLG+GGaxtFlzsQNFkHFl886GkmDFknFka8627hH+GsqDRFmc85W7GaBnFKwweGdJzXFmUc7y8GCp5yrG++G64b4b520yc2G1wku5Gsp6QtHMGJmZB3FkDFkC+GPFmZFlulBPAl9+m20oglnqlBcBlKzwduFnFm+YnFwQ08GszRuBlFSgc8E/Fl+Bm3Fn/lDlFklFk4lnPFnHFk7Fn/lDuTRWKkvlT7C60LTHFmVFkymE8kk+zhX+yLI7XV5xFkYlkMlm8yA8KnAjBQ3AslnSkmufElPGe5aFp6hrHQlmmeHosEktpglnaIwZcm7HTZFliLBc5FmmFYkm9Fls5EVlAM8iZBkXFksll4lke+HUlmUlktFnBkhyll3WIPFkz9J4xEWtCn1HKz4wDwslkSkmHmBz5DGlkVrHQNw2TRfRHqlnhKnzFlGi54VpI+FNkC2WCJ5byllJFlOllwQYsllbFlB+F7/T2lmkIiQBnlqx3RGN+nnFnTFl9Zkp6nmxmPIAR5AHYmtgg3cmRlnAWDQqKvsxfOGG1ApKQUczeDFJlnVsQl6lx9EIfE0alyrDbqLJCGdDY0x65lmhsGf9EMx4d5SdlFbEBNOmpPQaekcjZsumlln+VG9DZcukt/DnlFzAgztGF0mFlmrRz19E0fa//bG5E3DZIl5yshPZE2jZux7N6hiVGdDatllhVH1llEMmD24llF/9ZIl7/CqqcFTtb7iG0d4icHlllbiGDZkRekDlk0fazll1llGRoLlk57qdmnTlluvZflZDmmbDbdvaXbiG1HqDY4l56ZDQlEQnYd9F4lCkpBmWk3llSeiTunrlmoxxtlnKjZDw4gMlW/YPsHHlkAxznu4zJHuim+K6tBqyWlHDb/0nfoIOcEcjZwMmNlmKWlGjaMK6Plk/ZHxDYTvaXlnHhCrRzwVmEK6cRpNlkjlmQlB3lm5sE3lndixIVnjlmr0mGK7bxgDZ6l0mEVn+OBsVE2ulTxHdNRMxyuDaSV4AKhRCEODaSV62kqmQDXlkkVlVrrFenPlnjiYMelJkjAK43BgselIjYOMkdRRBTFSZjgK6pCgGVH7lkhK7YNiG1HcVn6Ml9lnYVml0mGRLsVkYVl1UiNelWDxix6QVzvun8VkWMkm7QqelEiI+D76MmCVn1sFfDaivbqVlyVF3P4zvbKVkMelRDbn0kKVmQiHzll70loR54VkpDY4K5yTDWbFdlFIMnyZlUVmq5qBekSVlnukShGb976Mm//ZeWmVDa+K4UhrtMionbflkuVneiDhVFUMkaZlXln4VlaVnQUY2VFKVnaVm1elDDYBMm8Vknmk3lmoTwdagsVkrllAayLunLlkL2mwpj1ukYVniFYZmlw2AXG6pMkF+L4iEOyq3y7ZVlLMBOxwlDb1MmMeGciE9elababWn9elXqkANAtVmk0FDWm+LA9VmRcETTErJkNGDt5SrWkzMlpYxjVkT8lgfaosFHWncCEa0GzWkh1GvJmxmB/WFZVHbemmJ7mDh7elTVkEpD0rGrelNMkMfY7Vmk0FnemnJldJAHVlpVHWxG5K7jrFPTFKimVgmjVmrVHvTEvemlgnApnvemgpmlJDJlkaPD7VHehklynzUBlykbgAVym7JlZJArVksUgxxGJ0mmjDJ0mdLBUall6nbNYG7IQ0lfUn5Sq7UndUm02LUNK8CmNyG7SpiYl7BH5hmTITtyFpUlw1kw1kbBlyAnW3alUn3BFvnEDCrWBE7Bn5hkx/r98Gw1l2WK41nxUnU1mE1nY1lLGB1UntUkQXGWQhQCF7UlyFZHco7xwfCm9yFjWJDBlfyGc1mnUns1kyXHzQ5zUkI1mBFrKPwYhFQxGDaCrUnbyFHxEbtJc1mgSH3UkbtII0mSPJy5FsdI0kL1Cm01nsmjJLx00lpXEs0m1JJq1lIon1Cn3nDeXEComfUnJlSOskdDJL2DZCnggkVXFm7BK7HzBn+u5m1mfBFihFjxZG1ms0lChFzED61mAWBYxHRtJHnoMhla1muYFzBkM1kGcLaYk+1ls5Hy1mC1kQwRy1kWolk0ko1lJRQ80lvBl71JFqRG7FU1mvbzbBl/UmsNLe1m+kIfjFzxoc0nAKF85EfGDW1lShH5EmtWmDeFSKGx7E4indeEV1kOhlbVmloDxzD0DEkimbeE11kmIl11mGQAbZna0kQe51u76hnDVkDaAmxyd1l7e5c8kqhmPqmfDIKhG8ikPTHX1pPMDj1nHVm8OKyhn1AlD1m20kvJlYJlQJYL1lO0mfJnM6Cr1nGDG3Jm/THCJD2hlz7EPVnHEnzUCnElexHK5DfWGYHgOCEFImfVn/WkwpmA2ke0mfaBLFLx0kVhGopkp0mRhldGlaE7Ps7Q5Ewl4f1lo1HOmGoQKWTHeJHQpC/VEApGBqkZrBNUHJTHxxziyw/ZHSGGVjBVAptCGA5GMc7E5Ig5FJJGajZxAJ7RF5JE3JBq1HoNkG8RmTE9xGoNmiWlI5G4l745ExTHYHbBJLJCH3ZHi+zE1GvRGENnRTFCsl6hxPUEc1FKHaZ0DvUEs1EkHaSKBU5GFTHSb4PLDm1HzRFkt441FUNlZLJGnBg0Hdh6epGk0Hp7F/KAiNkbQCdVlLVltpBLZA80F9Vk9pASNk+1ETelbHbN7ZLekQlB0ApqNkz1nyRwR1F7VnXHaR5FzenGhmvHYFOhdVEbJn/kmbVnKNnSc7lUQGNkzmH6NlG0FHVldVmAlC2NmiNnN5FCMBONlbent5HSJkqNn2pF+bBrVGoan+QmFZA/TEO5Dfkmj5E/enGql4am31k2hlwYAQNF91HuNmg+nP1ng1lKJmQ1nb/bF17dqzp2kY15XnAqRkF6HpNkRqKpOkY2nVlYJtpy6Fzzom072ki22ky2ml6GEVZtVCKHhZ2kFRlwrYeaG12nnla1NnU2kI2nVlbWqQ1Oma6HzgmES7RaH1NkAVadNkXHFZNmFg5UORm6HtNk9Nl95Tq4n82kjNlwaTKHEzQjGVZNLbi2l84yaVatNlMHEB2ndlbk+Th2lGpmNlbS/DMyEh6GTlac8BFhBiEqH5IjNldYDu4kqkAjNmLojc4n9Nm9Nm66Hp6HRVaTNm/6H9NnlBia7SV2nL6HyzDuwZ2HFFNnnlYPNldNnO2kAVbL5p1NnN6HDvY2brukIv6EK1C+05e9J2aFe6FNRl4boNaH22km06H9L3aEvsDrNlwtl04kx2nflZQtkBHEpLp0VZgtmdHEnNnRVYexTHNnNNmvbo6OJMHH3Nm1OYm2lx6EvNmaEiF2mf5CO05euKl2nDNnM063NkrSH9Nnz6Cn5JUyE+2nM04ZNlARnstmOzAgAIy2ngGEMtlkqRvNml6EK056poBHGK2kMtm+rQR6Fj6EitkBoLYtmdgIitlHNnqyE4tnkFCctlpNmW06PNndNnM07Ylpz6FBJxCzBhhJUtlI5kYik/HHcZFlGlmxkFKmGmkfNJkGF4GG8RnfOK1Nyz+zUxDh7AnYCZukXGCfJC2tmFuk7pn9Bk3cHWE4S1lMhHetmMhEI1mcp47xxb9HY1mi9FcJx+7FZyGS87jY6Q8lfyF+tmrBGV8FK85Bp4+tlE1nbI4GlQCklk1kUlkSCG61mJtmLUkhtnOcarBF/UkymFoSDM1nosFwOTBtnTUkltnRjBU0lClky1njUkVtlwhFPBmoo7pOLD8HzUlVk7SkL27GYhHV8mKvCS1kbjH0cwY0lJUkui6Vtm1tm9tkg0lMhEdZyDtlkhE28zhghxUmNyFXWB9tnghHZCyEhq61l4iyLtlDtmKqYChF/yFChH59Fh1kF1nqj7T8wjtn9kIbqk6N6RhGN+KlEkpDCN1mqhGPqlntnoKEy0nYeDHtmt1kWNlyWDDKTD1lRi6guAD1m91nZWC8LrPtnGj6x7A91nQJkhj41VjqhmYKGGTCm0mCikONk3lDJlRftkdi4QdmL1mGNleWD9djiKHmhnftkKhGJIl31lreBPtmpIlqil+Nk6qkBQmBNk7DDqeQh0mX1lhNlKTERNkvVkNDAAdkhhlP1mOlHg+mQ2lNynKJmDjYeP7IfF1Yke/ZtMR3omVFEOzKVSHj6kO/Y0mLyYlkfGipkuUp1olt6kMpmVCKqfEHKFcdlB4oidmofGgpwEfFefFDjbFHJBfHPok5TbgbysdmipmXyzwKmSdmITaefG5fHUpI7ej1KESfHEJmtfEyfGjdZ7jYFgAKfG6YmNxnCdmnfGUlzYXBsfGFGmNxkmdmHok36nGdnUBgpfGzKGNxkynzkGl4dZoTZAvLKdlfjaqdlPonftYkCF8ryufGidn1xxgvJAGl7jbHVigGmzomN4n/eZdon6GmNxl+dlBYnPKF7jZRbLoGldfEpdkNURwYnUYkJdlKdnIYkxdlWnqRBmg/ERdks4I+dmY277doFfG5fHfCbn1RbKGedligLOdkBGmVfGY272dlUYlPfFXO5h2n0YkQ5x1dkPfG8dnZ278dm8GmUlxi2KDBaCGncYnFdmDfHDdlHfEtpItQTxYlWdlgrDTSFcGkZdlRfFafHkuCXxnudlhYn+hxqt7kPZifGwqELxlqX5RdmZfGDxnlbBJKEV0j4ZZAsbtdkRbYhuqhllTpnhlkR4mT5KdBkzpljrpxllbYkT/Y5Oo9Bk4/EOyh4/GHYnBRnhJ4Z3FcJ6n1GeikNJmSRHzakA9keilrakl1CwdABikBqFUM4GREjanhZ7xZAnZK9anqM7b9oxinAZGI9nxim7alw9nJilsalBJ6vmKbakjinKDZwRGw6mBglQRHo9k/ahnhHqam26EOZDhKxlimXanNQ5oELWvENBGtx42RqY9kY6m2M5M9nbim+BEmM6cRoBBHOCifamU9k6RH2aloOlJQ6mRFnQmkglL/zDimuin49ljiloUmNx4XCoFLEzimtMRTinjimNx5hkjWBFfQlqM5JCBIRHEe4bimNx6aNICuExal/L6hVk+in7A4mM4uVlQCHk9lwr6cZmJBE3ilgJ6CugDal49kmVlcBHFinQDaK9la6km9nKSYHil8wT83FlwRU9n1BGtBG2M6vRAu9kJ6klM5N5C//gI9np0YHimuUnxumFRGJul5KlhlnmtlZYHQSk1anCPbEjAjBFuMhSJAnWqEsBJ9mZ1Ap9ktaketk+xnhyHZjyYNmnRGF9k4NmJyHO4n/1mfuGaq7pCG2TEcyFgNmvREl9nOTFg1F+NxS1Fe5HW6GxTA2VHINmY4loNnF9n79yf1mHyG99k/1mFc6PjYRTFjyG+YB8NlpTHnNB8NmY5G1NyUNnzRFj9lENlCslqcTU1H3ZH+cQ5TEsNkvgq9zp9JEs1Gu9Y/QqD9mqO5itBYiHzRHsQoXbLvCHwNnsQr65mhTGUxGqO4JxLMVn81E9nEj+wq5F39mqO5m4zeekHxm3WAt9ln9mvNj0pEm5G3WB1IFQ0EGRxPU679lCVmW1HP9ma1GIiHa1EIq4q5H7RGJtCUKDMVnQDkVkAS5Ea5EvgrCbQ40GS5E2O6t5GtVntAkYDkvWnb1kMc717ZyNlH8kYKDYDmDVlt8nSNlqWCjRI6NnG0lI34LTF/tmBUCEDg0DncyD7Nw0Dkz1lzLaJ1EbJlPI43VhbWkPtkzYozTFrmFMDm15GIdksDljTHONnnVknzbCDmxNmcJm7ElrpAUDlPemvWlYdkuhk4dmeNmr9ZWbHfemAzFEdnb7GnVFKDlZtBNupAETA1nWin9kk0dkOqmLZlM04BC5acn/0Fk8EqNDzVxRnEwMQd0GWDl7ywSZkoJRa6FIqhJ8ZXKz7IDRE7reT7yGGqxuDmpMFgb6m4SP5EWDkCNDiYKmpmODm81zODmf5E2DnJ6G4vKxpkhDlCk78Vw2nERDnwk5xDkKFEhDngk7HWBQFEJDmpDk8mjypkC1zwZ7ak6uclYMEM3BO6EDCbiplpDl6E4qqxezFXKxicipDnVVwqnE8PKk5zFDkNRm4cSh6FtSkGnGEhZR6HplDyNDZqFVback4NBxK8Ewkq2Dk4k6B4APRlI8EklxsoQpnH9DnJ6G6EKoMETDm81wBQTn2KcKzdDlk5wfeDmOnw2SoZZe8atDlNDkjE7FwH2Zl1DnM5y1cnuKwcKCzpbrDnIFE8mhdvb05yeDkeDm5Dn8X7zDkCaABDl88zZ5hL0F3Dk8lKZZkCaDU8EXJyGyzjnHDc5nDnAbLEMGOWTl4AXJx+5C/DkFEizDlJDnA8HxhHvDk8iyaxm7DmTJwaHgBZmthqq9w8lzgMDiFHwTjMZYnSlGZnQjm3Jz5Dk4azgjmTJzVCr2ZnAjmXdl+OnTpkr6FLeAuxmh8GkPEN6FfsqGDFbPAr6F8UbFwCZWIByGUjn9NCs4T+FHvcnlul1hFtOJ0amAyFkjHXZTt4ldSEsal5OkPYnsanWUbPYlG4kdoml/zEunS4mbsERkCn6nd4n8jlialy6G/YnCakNOni4mSaltNkXYkNolVYloHFKjn3ACz6mQ4m5qETOL4HE84mOakv6FGRZzonVqEO6EG1AdfaWalouks9zE4me5qyjlJ4msV6GalLNkMyG6am76niNzw3BsaEWjnM4leoDXollqF/DZSyHDomAGk3Yl9qFOZDajnVSFHpp2an6jnHqFajm/6E6jl6ZA/qFIyHrLZ7TJ6jm64mcKauGkG9zp4nippkGnYyHZjkHGBUGn54mxjlXz6/6EvYmRal6am3SEV4nMpoVjmbmwIOqPqEljnB6HtgT1jmFjlBjkepq5jncjmPqEijne4nyjndKaDOmtjmJjnMun24kDl5zECZjnpjmgmBpjnZ4nVYlPqFmukqyHFYn/qErSGbHAtqFZampOn97D+YnMaFmulfXjmYkSDKcqFBopY4lIZqjjnGjlsdIN6kxjlJal1KG7jlNMGoaHlOlmJBa4xEaFYaFTtChRIWXYbtJ3jl2jmvJGXjmSjmzjmnjl/DaEyF5l7UaGCjkfgIsYldjnYyGXSFrODhjmljlijkgTnyGmQEpbuzlYnzjnf4qhWK4aFk3AGyHW4lzjlhalB4lNjkgTl6jmtjmgaCJqGhjm/jkqRk6jl7BBnjlYTkSjloTlVHC3jnRjm1jmsyGYaEUTkxQifCFvjlmulUiiGLZxanAtngTlHjk+KFFjmEjkpukF+mSaHByHKOaeyGPuh52bSlFSQJ8Tm8TkLZl0dl8g71wBAyQGyEqHHe+HD/FJhnvyHl7D3YnNhlAu7Q9qZhl5hkMzZI8x4Rmb/HGjaEjxThkyTmqTmlhlxHFs4pIRnthkcyErZka6H7hl+NxzYAgyEyTncUFNhm2TkYwFGjkOTlCHAv6HtXaMo4GtxGRna/EsLEezY2cgvtYz8DV/E6yHmTlX/FD9mdqkgHGr/FyxZfNz4i42/ELhkeTl24kpSToOAyzYuTlDHGazZ9KZSHGqRmQErWTnh/FAu5WQJaTn6RgjnAhzZVlz14mWTnD7iXhkldziHFDdClmLx/H3hnZYDfkIgHEJ/HBg5qZRcRnyTkvgqzpi/pzNTkLd5yTlo4qiO5SVTu4k6RmCO5TmRrHG2/HIDkwvAr/GW/HDTmeTngRmVxZ724DTnlHEwRmCO79ITFHEIRkdTlKTkqHFGtDVGZi/EJLGAThcRmF/EIRmLYCVTmzTkERmm8RiRnERmnHEfIp2YAGyERhyFc56HFQRnmRllnFbTl+4ljTlrTlIRlw+Y8nCqO5YcDMRnFcyQO6kQpdhlP/HdTnmOC5hkhvj0LEGFFxTmXTmcTkVGmpum1tZX2DgAl+RkwUBiDz//GVcI4Io6CID9BsmqIzmY9zL4kQAnexnfdmIfFA1J2DbcnEl0Fbi6P2JyOmWnEEzkzmrFpmV0FoWCh0jlRmdAZ7i53My0pnbKzknGpmCbkxpqHEznLEFcpkszlpjBspmJKz50GMzlX5SxqGunFZCEhjA6nHMnGlZaCzklDnCzmcfGc5gSZnizkYdplplKzq5DmmkotpkynFHZZSfgepkBVyKnFmfG8znA8HhnEadBMzl8zm1nHB54qznQ7av0Hc/BuGGKYibRkgsj1Z4yzluOmmnEiznrLSOpkfrS2DkxhKkmibRnMnGLfEpyhGzkszn2zatDmuzlJfGSzl2pn4zmIHJ+zlczkBzlMwx47b4MG70HR54WIqAxnqzkadC+rTIFGiWhPG7FGFkqRiOksznXKAFnEOzkcGHE8QU7b+zmOzlZzlS7aOnG5zmmNxcpkwKhKABZ55TOH2ZnlWxl55VzhGZkJznshmWyFjpnznGx9lXdnmtnevIY5LbR40jmtzljZnNUAY/HrzwuxniGKHYBzZl8MGYzk+o4upRLDYo2kvFyR7bVNk2dYwlyTznc2lMInQeyFNnCtmBly0pkwtnmdYvpC6Drp2mwgKczndNlbzl6LYW2n9q4bzlPNkCpkZNz/Gabzlpz7C8H7zlMOQt7aXzly4J0tnjNlw2Rba6t2wi2kDooepkG9zzNklSlVQKe6HfNmuWSHzkItlOxYvzkj6ESASxWEPznd6FeFokdZG0JEDa62k+Jz7cjZfJpTkF6EnzkXznr6H1dbs26SjlIiBNxbL6wrzlILkSELZzn56HroHWxzF6EHAQl2pTSk+GggHF9KSCk4F5bC6H7zkMKDF6GP6G4iRH6HB2lTSmPKLaHEB2mXghX0He2kt6Hn8Szzn/NmYynhkpQGHfzmxWyULkMLlopxba5N8YRWHCLmgLkotlIEkb+hytn+fEFcSQLnb6GcLmc6HjzkOghsLnKLmerIELmbVKMLk1zoj4qdgJgznORmpukb9SZjaFukqtSbpl2tn1TR6LosJDOtkStRGLlUGF59lYzm/S5FwKn1FFhmBo5i1IqRkqHFnmnJbKpOn7hl0Y7rTnWRnM/FFNYzTl+Lns/FWCBBTl8/GN1Z0bDPTnpTk+LkmTlRLkFCjG/E1hlWNaZTlhLmJLnbTlRLklpCK/HoRkiNa7NbYyHq/EINYjTn9hk6/EINa+TlUyGkokiNY/gggHGXTllLmhLnjtBjTktfZRTkj4pDTlrpyeTnMKQJTlRNYLTliHEtzHpLke/HNTk71ZJLlnhl0xC5Tk0RmONYbUC5TneLkv2zWBFlTktzEBr63hlPhmYNYnfpjhkzeBLpFX1ZUsALlCVhni3bFLlrLnetqKRlP7F6Ln5+nTpk8yBLpHQznimxtRG8sgezZgnFwy5AwgsJCAnGvswnLnIzkYzlfdnUx6cjlCbFeZECjmYzHbhHuqEF3GPnHKjkTGkpjnUphyMFo+nSjnhqE13HvLncAYdpG4REKjnP3HijlRanbXHuak7GkGjmgTnVzHBjnFqHgZEmjn0cnWYk+jmYXHAUHujkb3FDZEmamOjkBREOjmCakvGkmal6amb3Hejl4aGGonARH+jmOALY3GlZFIrn/2EvLm6jmcqGvpHiKYJ+iIrnrqG76kormBamswbFclowltjkCGk8mkCYkkTkimnFjlYaEArmxjkSCLoZGHpHljmcrlW3EIYnUuh2anKml0Jx+an/LlRXE5jkCrlzhFATK6GkFpHiKaQTnRzGsrkcaFKrnDjlMmiSOlcrnlKLIrmERELQbtjkCzELQbP6n1XFEaFUGnVXFrjkUrmRZFegIIaFZxSKrnrckOrkIqFdckIYmETmwJxGrlkaHWrlqrmcybIrmarkmrngqGMrn0aEROH6rnjjnMrl23EITl6rlyrkoTlsrltclxREgTmprmCrlTjmoTnx+nOrkIrmQmlbjnomgxrkJcmMJoiGkTpG7Lm1BkiaHNakiZEKaEv8yjXEn3qTkprGFDXEC2an+LXcl2LmEj4A5SBpkJpnc/HhvCnpkVlg9rlkwifcHdrkX1FXfThDli/rH1Fn2JGZnjrlea5nsS/5GPVo48EluwX5Hzrnc/GjrlMnFfcTft6brp6xlfcQANEhQxq8H9rmxw6+SqBnHDrnft6RXwk8Gkpkd0EABzODDoqw68hQd7zvwKFEVcr1w5/Ng1nFpThq1agwq/5HWJaua5vrlUnHXpB1nHfB4VnGbP5K75cCmtDlxkJc77vVAmnFAHwnrkg1p9DnHrkG+yFDh7rnbrnQrCGFGJKzrrlr0k1nH7rnEd56UprJwzRnhtiFB7RariFGbXqFZGY0DtZn1/I7B5AbnIFHTrnI1bkUqbRlvtyw47f2AVnHT3KprZBc7UZnhaTf1FEbm5nFipm4bmdnGepkobkLnrjDkwbkxYjWDkQbmIblSPj/0HD2QVrl9XGf/FnqRrpnCGzeFBLplm7z76wakRbpn/awu4LFwD/VhiTlJNmDjb6Jk8snIQlabkpxk3gmUMCbnhnKlTgkXrbvxmeISBqkGbkkslHgm6bn5xljKnoOm7pRFxlTKlf2lubAZxmWMHea5G0yr1HGbkLqD+xlFGF5iDablLglubmlxk3glLWFZvoxxmk8lSJAu4gMyn/1HoOkh8yeeGxxnBbk1xn7KnkOksNEEeHp9m8eFTxk9xnz+nmeEyskCOnMnha7FLgnxiB7xl15CB3YPAmVy7XxlHgkOJB3xlRbk3M6PxnZ8EojR0sliGF764CNFVGGcNF5LCFNjfxkNGGtx6Dc5EhkAJl80lAJl8lG1YGgJkYJEEGADbmQJkkqnL1mqFAjbk0qnwJkDTaTbmcgBmylt1keglpRISqmo4E0Jl9eG6ylgdmeJBR260JkzMmIJnsJFjbmEJlI4F+NFTGECql51AucIUJkMinTJnEx4A47sqk9enXbkMJm2QmHMl3bksJk7bmuAauQmSDmlkkQFA6wxeQmnsk+QlPrGZyknEnZyl6qld1AucKiJkmJHqDnPsmaDmodmvVlHbnf8nyJlUdnhhn2qmv1lhFmDjaYcQYMnC9CViGo7m49GA0BbiGWBTbFHEkIY7kTmDCdH8XCpMG47nHFHY7niMHNOGAMmwnAtll725NqmpdJZLzvZZ87Sv0md8ZScEFjAuhiP0no7kxCFhXRo7nk7mM7n0shY7mjkJ87ns7n3dGC7k1SFfjz6ZxWHT7iEakicMmi7lK4CoCrnFGC7ndSHi7kV0mT6gcZbDbCN0lCvjwSEW4CwwSwZxjHAhGE+8pXtF67lMZxc/JpqlMVIBDaLS5IrLW5yF2F/xybKkCyn47nQyGopDvFGa7mViFPI7Bqk5jFa7lNZTxMmc7nvZYKkoXMH27k+7ll/CPDEQ8Qe7njqyq7QIpxo2FQS7+qnh7kh7m8MBupz+7l6yEyNobpzO7kcGH9Kg/pr0OGAOEYiFIrIydGAyq26FzS6S7HR7ku7nUkB47nJ7nvZZMFB27kQ8bvlnXxI6Yrp7nzFHXxKm7nn/5Rel17nXbFxIH+VlV7mVMndQikRi4iEG7Rg5yK7lbi7s7nlZyC7lsiFclGtMkM9FGA7D7lm2KsDHHVlWmm9MljJnLGHj7mbwqwdlKxAKi5jMlpYBN5A7MkLbkzYCxLwr7l2iGalxDMm4DlJk69vJSjGClFyiF/DAilHcDkfS4MlF77liCHzI5G9Hrskbbl4g5R9bW9Fgalk5aP7lzOHwJmkdnvGDL7n8OJ3MlAplZykgpk5ynuYBMYyISofMlX1kSJk31kA+lQ7l95459zMioxQLH7F9klg1kA9AQ1lZlnb/Z/pZkNHIQmoHkeBEpbnuZZDKIeblHgk/QnlyR8eH6eE+DkQ+qoSgkNF2pZoHnWslV8FgwmYHmpxmUjFl37bxnpJHWt6Q8lpxEi5wUHlTgnUHlghFLgkBDEPKllxkWk4r1GVxnzMF8Hn9KlRbmlC7qRwBSlFGFCHnSBEtxnak5X1Es8mck6e+Cb1Ec8nXE70oL9xkCeHI5wseENxnqHkisnIL4kEDvJxiHkZGHDphR6E8MBdxkjxm4jmXjTjxm3JxZbkiHnSBLaHl4HkWrA1xkiHlal4ChEsHnV6nmHlkHlDRBZbkfxmCsD4NESynaeHuE4hbllsmAJkjpnbZ7rLSDbniNGXzAuQmVeFQJlT7kvqD6Qktsn26CRHlzbm0qmHMmDqEr8mXJlxk7SBIEJkIpmW6Bk5xpHk9emiHlZHmXbkapG04TT8nd7H/UCscnnbn8hkHbmSJAFHnLbkqU4kJHSqkPbngam1HneNGsJn8NANHnKqnvbm/hCpHnfbmhNHyDnvWmuhkIpmi0Cscmg7nnOGmlHX1mmqmwpnmqnwplFHmciAYk44mGH8lw7lR9H/8kQ+mVykYpleVBF9liGEbHml9lPRniQYV9kwl4515ANlvZEVNlmxoOTFbHnpI6N9lDUHVlaEUDuTFTMGH7rt9neTGqGGJ7pzUF61GUVY3HlBTHeJF7lY7HnnlZLtDFJGXRFtlbhlKKWkxTEAnlT9n+JGjlaz9l5JFQnrj9kE5E/NkecRzCH/HmZbp01Hk5Hh07hKhb9kcNlMZwqtnU4qvHnM04V1g45H9REMtm61Gy5HR075NwhSgW1HoiE8FCYNl7Wi7jY8FB/9mDUHm4k0nn0pH3CF6VYP9x+JG4xHG141JTspE2UEGxmZXxEpHjCEctkp/h/VGfHnWxoHMCs5HcnmjcSH9nonkitle9E1VlMnlSnkn9nANnnlZkZqe5HAnmYnky5Hy1EitmzQCCNkIpHC048nl25EMpFHlYcnni1Em5HM07vHmhTEqnk2Rr0pGUxEmL6uiFdTE9en4EB9elrenZHm1hA2nnu1FuQmHCAunm9VljWkfqme3BqNmZVZZ9aaNn37mpVYwegMDkDVYSpG7Vn77nBk4bNlsDkahkScwHTFdHnUfbzla8Dn6tFhnmHVmxIlT7mJnkCpEuNnFVYpnkSDm/JkeQk+nk+Nn3VlOhnaqkKDkBNlaDlX5BduyqDljHmaDETHm+hnGin+hmmin/VnPhBRnm6DnXVHxNmIHmJNnIHlLZmtuRf4k1NEQT6/1EhqmY2nt3hfAl9nnGyC/AiFqn5jE7KGSnQy5A4An9nnAEmdNGCqG3lDznlDNFOXaDPTQglZmkclqb1HymFb4D2tAzyHbnk+mkDnmznmT7bI2hmJnKl5PakEHnRJl5a4DKEXnln4nBmnLkIFJm2l7nnkRDiXnk1mnkeH0gnSMGj4BkHDtDY4EnGRHAtT0Hk/nmCqHiIbI8m0mGRmHx478HkhW5s4idX4D45hGH7nnJUo2EkbNFF44MGGwXnkeH7jHKmEW47KeHGklqeEW45yeHmkmvjnCY6/Ah5jGDJlGtm1C5bZwVEmz7lC2CkXkFAmukmzHkkXmHHANEnzJki9GUXkXqmL7mDRCznSDEmHJl8E4ZJTsXk7JkPWlBA6Z4DPUjbJkJgleEDqFjcXnUXlNnlpOEGXYWNGDAnN7E+dBlQDSXnn7kIXbaeiCXmlEmKXlSXnLEm0DmFxB6OgVEl2jHlxAiXnFkl5nk3X5sXn3rGHEkH1mX8mKDmQHkOT4+dBGJGNklQpnh0l1nlmqm/VkWqniXm/xCSXn2JFaTEg1mBCG/smrHm7JnZomTFwYgl9nl+XlvAl0mFsV5TnAjnlUmFEV5v14BqnQV658xfAmPNHqW7VVyggkP4mRp5NEFBXkrnknl6CDbwgknl5soRYjbbnl6WCS0xNJndl4pXmJXnhXna8GmJmDnknl69/hxJmIEkVXnBRxsrHamEnl5RxDkgklXk+LxUgkcAnIpCGyzUJylmHtXlO2LyrF2EmDl6z8RymGyAmRp7SRqCAlUFkDMGDl7VBzmMFjXlrm5TDnmMHUkA/15VOmdMFCgkg7Du97zVxItEBXlP4qygnctG7OlLXkBXmdlLxqklXlbWw9Jk0tGBl61Jm4XkIGmbXn0kmoP6HtnUfaqeBBgklEkzMm3WlcsHtrHvtkMfZPXlzJnWhmlK55WaOgksXlVK7fXnrJlZOGll4HJk8XlcJl8Xmwh7RklpcEM8EPJkKXkZOkXJm3bkVkBJknzWlQ3kQ3l6W4OglLEnHrGvXm5RBo3nrEnr1lY3l1Pr6XnPTF4iConb8l48jGApn9HkCJmDHmzHmi0A/1HVgmQpnjHlgHmTHkkdkAHk3ECw3nIplvEnw7keZCI7l3AlRhnsfYvXqSBlRwTxqGz4aHtEWmgCbFhXQDUwmdL/mSdqHywDM7lu5J4bFi3ko2ETb5hOFC3m7tF5OZ4ZxNXqS8S7tEHeiAT5P24DNFvCSVOk2npt9Hff6YbGuVAttEi3m7j4m3nC3mS3mvZl6hqEZw9AkCbEkrBXtELTj0LYAXpOukTZyS3lfZm34SDdFW3mGnqe4T3tEqygrbEIQbfdF23l4bH3Jg1ZzDsHyzBgmCY5xJfJ6l6ZbqsMLcdHe3mx3m+OHB3l+bGe3mmdFm3kp3ncqFr2F3gCPbGRVCs2Gtvg4dF1VBpoTe2EzmRt451VC+3nX2GfKQp3nl3nFFHiWmF3kTOk2awHCn0boa3kAdH2fS07E1OicMleaIp3mu+hgMnp3nFbpx3lu3mobEmZTvdGwZF8WlTrqZOlAdIVSmVrrkaJJdEJ3livyJFHJ3mVrpF3kD3mSbFyDqw+EC3k5bFyaaxdFPHIZ2FgknZiSwZy93m73nPdH0sgtbGp3kvtEH3knLzf2E8QAdbGo3EKMnR3lvbGr3kVdEDsSDbEP3nnFHCTYcT433kS7my3nTbFc2pLFHzggrsE6rq9+nb3mGLaH3kSdH+3mbbEkAZr3nH3ksbF0RGxOFAPkDl4bkF73nL3nQPkzIKGdEJ3l/pFe3mXbGRZCX3l+DyPbH2rG33mvTIwT4QPmP3lqdJfbEh1SP3lv3mEPkWFjs+EAQiaVGlzo/3mwZxa3m7bGn3nyOFNFjO3l5RGgPlO3kIT7tar1FFQPm7j7l/YYPmYbFHJAFMk4PmYRFGUHj3mf5YF3nGQh53ko+B/bFSPlWMmDkoTXZiPkrdEgzpM7H0PkTZyU1RM7Hd3lZ0kJ3ncPnQ9E6PlUdxG7bDswk7EoPmhdGt3lC7GRITjwkwSSsOGoLphMnb2H/frGPnT3m0MkvKT47FUwTvdFX3nY7HZj59dHu3kMT69dT6gmK3mYbG9TF6PkcbHtb6ZdHoSqFfY6xniPnr3lKT5/bCoUH+PkCbH7s5+Ml33lKT7lj7nFHZ3miPm4+HM+EL3k7V6ABlxPm7j7K3nNFFXeDO3k4IAaMlJPkQT6u3kIpyzqiGT5V+GGMlhPmm7HFPk12Ff3l3j78YxBPmYbHVPl+3lm3mhi4V3aNMnTWkyil3MnzWkJ7Ec9HNrHlxAyil9MkKXkz7Hb7nI2BF7ETPkaXk3EDl7Hr7lpcHj7Gs2LC9EzPlhT5RwSQJIrMmvfYq5hn7nzWmLPl69HDMk97FcTH7Ml37lkDlNEC97FJWLP7lj7FnPkR9EGXlMEA+LwO9FjOG/7kA7n/7lA7lWEByWre9HVnmBjG1nk/Ml+hlwpkBhnOXkRpAH7EwHnLOH6DkIHnQuDn7HiTlYHbQqRPzH0amFVINLFbkmwvmG6lralAdKLanzkkJq59Yz2LETakgDaO5bTamQBHIvmILHwvmIdIovnlBH35aBLxUBFeqEoJxJjx86ngFY8YRZim4vkg+K2UTDQlqWIocpFimTaHsJwq6mvkn55ZL7gw6n6QExq7veAQfwSBElaEx2b8vmK6lyUENPAw6my6kD5b0Hgq6m5hx0XFMvkM7Si6ngFZYOSXQn3kG9YI7anjinSpw6LE3imfWLcvl4Uk/xy/+jsuGcUGTWJicgGvklcli1C5ng2uHGakEJxQtow9mFc6Kjg6vkE6navmiLGsUntO6+pxBLGcUmtza+PQYvnOalGvkS6kEvkY5AaiQwvnxxKrLHevn/b7O6nuvlAu7UthKyHEvmKAJfkrBam4vm5ZZEvkW6nuTnonQBvk26lOXEdI5F2g2uEM9lrO6w9g+imWvkdI5pLzE6nBXEZvnBvlBSAJzGSFCUvls6lec61gr4vm6vnS25wvl1vmRvn9imzqGk872zjTWFhBEMzavNjSvnw8R+5YjobsvmIUF7O6NhwYvk46kbOHMvm/knVcn1vmIvk3OSFu4JvloLHTvnUzaHHRqvks9lzO6Zvk2vk5vmFvmAUn1ODiblLYke8FohTF6n9sx7vkBUmZUFElwcJITBEUcyHvmZ9kzBEPLkNx4hP4WOGDGkpTwMhzrXHiMF1si53GPXEJIAT1p1cl8B4CgQ8vyfvka26OAQr3GtpHvvlYPGdpFAflpKHy3HjtBKnDP3Ea27Q/j33H3vkwfk93EfXH3jkn3HgfnUuoBrkJcm+MDBnRs+lAOlWzboPHecm3an0tCQfkirmE24M2zz3HSmmddnQAi4fnCcnEfmYfkS+l0XEYfnzSy0rkMZFIfkMrmAfnwflwrkk7lpgzCRIFrkUJxj9mwfnofnxjAfvnv3GvsRv3HgfkTmA/vkP3E9cRa6rcfmE24uLi4fnKXGG26yfk4rlC3GSflQPHO+nOyFwWRPvl8B6KflGXGjGnH9kH3Hy3GpLYoR4RLYfXEgGRgfnofljw52Ehq+kFjB8tgUok5cnWfmpopVcl87kaflLcmEaHWfknbDWzFhXGlZZUJQ93EGmmmflgrm9pFQO6vvmDGl6fkBrm+fkVkDifmBrkFjDCuhARF5XFefk0flm3Gvann9kRfmsmkFjAMflEfkFjBtfKlXFurn657LCRmfllXG4yHefmQ6FqfmiSRcfnirlxfnOflkflFGlGtmN2lJum+OlcTnEjmKVHF+mSZGNfn1rnNfm42BNfmUPEtfk1rkZllp3HHYkYp606netB/1Hz0pttFw9S5SnDfn+KFo1SgdFmrr22EZPYQVHLxmkRjF2lpHEHxEEsp5WmjflCSmTrxJmk9OhjflGMaqXYYSywJxpLoM7mZ46gHFHKmL+R5WlbflCSmnflttHnfkeGErflttFGBkSqFsGFGOEgCB68SEHmtsCdsHPfmY9HTfldtGwnbDSm3flFKFopTgqFKLoi2EEWkcA4k8nPZDdhFdTls84mSnBWnEWDk2HQ/n6bHr1YTtR7KkKIaqXYPGyzKk7fk7KEzxwXfnjfnyWlPjL/xmXfknhGQ/nI/ng/nyWnNrzE/lPfldqwEjFfflttGU/nJGF/fnJWmDfmFGEzfmb/E3fk4/nZWn7+ixbk4/mKRHjPz3gkk/nZWnajzqskE/niRHxTnfxl8/nkzCyFY4ykM7mc3ZLfnUQko/k7KExbCVDHU/n7tES/lM/l5WnVKbXFGPflq/kkVj+sn0/mBp5GXSK/lC/lkC7mDiFSkNDEZ2GX2A+pbDxkk/mc3baS55bn0/lG/lE/llxH22FLtHKGplxFj2H2/nbkIMykTCzDsHrtHDwmxeHz2Hu/m+/lyTCjbHrtHXwkO8md7nCwkC/mvfkY/n2/l4/nI/lVSQnfYPZxh7lA/nddHd5yh/ncGFO/ljIFdqlK/lDLbD5xRvCq/mjX4r0Am/lc/lZQn09AyymuSGvdF4rLnbGShnk9GZ/l9ql15DJOGdPn9JxvLRVslDbn6RBVSbqynRHmBnlx2Dt/kUqkqXlN/kxynzbkKXmSlxOymr8nW2C6XAj/nrbknPkL4BLtHN/l7bnpHkT8ABnjbbkb7krTDPvzeymkJkj4DkpH+ymUJld/lI3ZmvAT/nTWl7/luymRymPqkL/nBVa78k7snlxCH/lvbk3Pk3EDD/mpyk/bnpyl1gn/blH1mA7mfWl/TBHOjBojGJEfPmb7EM3n2XlTHmOXkzHn/PlBCAaQI1ykOJHfsnwHleXmGDlI7nGDmQvmKOBdrnUwx8smYpiYnF98aIAUZqa/DkIAVYvnOhjCFHjHwA8HudztZmfjLGjbWFxzrkoAUV5ZYAXfpkYAX55ZkAV/cEUAVllzvrkkAXMsnsFLxDk0AUvFwRZnrKCQ8GymiZihwZkkAX3q4tNzZDk6IqMo4upTSnGGWx8FapOBoblTvCG5YGrGxpkYZoV5aSAUqnHyVDRDbp6j0fSaxmT7rlq7trobDlwQbgu6gtq9pleVT3q5J2rMZnMAWG07gZkYAXtq4lZQibnAdnsAVcIB0AXMAXPMEPDnNyxfWByqF9bn1zklGkx9mmtn9ZkbuGcFHrnEPJgHvndgoEdBYAYZFajWS9kDdzmvsweAV6JBeAXtrnemkYFQRFGn2ms3ZJKzz2nbtELixL2mv2l6/kAsHlRnqOnHtEEQpGOmAaH8am9TCt3FxAX2/lq6R+qGP2nCwkFAV6zlMOnCwmeCg6plUOnCwk18INRllAWLoA1AWaxl1AVb5gf2mv2lvtEQdCYOm/ZnORHd5y/3Gaxnf4IqC6PqDoPFcOlPhFZQkVAV6znKOkjAW5AXYaG9qFZQnFbjXRmugg5ZEzAU9AVjqEOakZJEH3HOOlZQnBEgLqE2OnVAWd3GcKxvQkl2AIPF7AU9Qk4IGgaFEOk02CbAWHqG1QkVOAn3Gf2k02DZSzGxl9AXUC4hGacOnNyjDAW08EM2H4MH8OmdQlD3Hxi6+anzJFrAVnAXl1zB5qMOk6UE02DGXTIjkbim8dGHAV9j4gwnbvmVGkIiDNZLROmHOoIgXPqAwAk3OpLCDfOJIgXP8B2zhxOk9flQ+kg8Azc6onGKSJTFYN6CCbnEgWalZhUC/DlNKivuE5Kpjrluwy4eGyubIjn0gU/Fb05jEAXUgUMgVXxCmpnsgWrFa0gVMnHkgUShBlMn5pnEgWEeFxqnxDncgVkeFHYBHrnigXWHpQbninGQ8Fh7rufDZDnkkAmZlQnp3rn4MHDXCMla6OAlDl1FI0NZQnqOxjc8HquSrFbKTLfrnF2zRDZQnpUbnZqGc5Sag6+g7Abl7YiANYKgVXrncnEGeGc8BCnHHf448EDNkRZlugWvuG7ZqJpnSgWNVRSgX8gWx3kJZlOEEA8F1bqsAVAuRTFYCVTYAWtMZOg54LzojnQfz2gXQxzojmGgUKg5qgV0pnNnFl3kWgUP0E9lZOg56vrmzmbsD7FY+gVUFEgGnueFzX6epkfbCxgV4blEgXygVRgXfpl+gWigV7rkVgX8g4uyzsxnkhxwgUQzn2MDrnFQgh1lLwPZ5JD5gbGVKKbk3h56+KwOJrpnkvDDzmM95g3Bw/mZsDM2EKDxE2GYkkVsFPDYo2FmrqtsFcCGFxF9azY2HFPHi3nzgUzgXIaSMslP+mk2He9RzgU6BYJ2FLFJz0lKLolOlpsGZpyXiHLgXc2GzgUUsneWlP/Jw/mn4TMClXgX7fnPgWNsHCep8Sk7vCK2GfgXK8nlmklsHIrz8GHvgXUCnd9KTKlpWnRDHG6izKn/gVJS7DxnGWkFTqeMGwQXdoqk2HCQK/SkPgUoQXMyklml52FJ2HbgVuLYPsZPgVIBlqClD4TDxFwQUeJLxKn1GH5BkL2GI0RfgVvsGEQWHiHLxmeunuDr4QXCBmIzoiO7NxEzmm8cackBn1FZWkWeZ0QVsGFTOm90bDiE4QVOCkstxgQnAQVIcE7ykuGH8QVUdBMrGxeG2cE1+YpSnse7IikE2Q6OGYrq0PlUdCDJboynRsGAcHk1SrglQixHDFNsgzSkiNylCkTCzGSlnrwr2EiQWW/mtsGvRDYQXTgVD2FEQUZGGHmmXsFkQXAknKFxOQVC2FKLpaQUiBbYQUJ0K4ClVA4KQUPgUhKCfSncBnm46jRIyQW9BCuQUXp5oSlmQWP2EfJRySkBQVuxb/2E3gX3DG7gXS8lXOloZ7XgXhQWZFw9dqZgTK8lJBmP2E5QWmGFdmlXtphQUPgXodFQQWtsHYtx9iFCQV8OH2QWSQVzCkFQVQJFIQV8OHyhRrgVZQFWCnuvqwSEbkH4cHNQXOQXrgUb2E7SbDxHMQWNrlVQUppCK2FlQXoyncQUBmDOQW2QVwjE6QWngnCj6wEaffkzQX2OEWQVlxGtsETlBjfmPsGgraBZ5cSn1WmrDGWNrjSkATBKynBHnt3ZYimcgBgJlcjGVOGjbmT/njbnY2BnQXNslGykz5lXQVIJmkDm3QXXNDUilrbmkilyjF/MHuykrPkl4DMimfQUWjEyim/QXHVlXtr57EByn9OH8im2NFVHlOnk2jHAwXOynyim1AkvGG/Xlj9rgwUKqn2jG1Alfsk3/nhkAqil1smaqnFnmvelPVmCJlDHkitC+jE4BL3sn6il/engHlSJkWXnCikWilUOJYwUeXm5iEGDkRhnc3lv1kg5z0/rZanhvHV6mmMLMvHJ6FS55TvnJvGsp4vQ78vG96Ev1FevmQuHSmEDPTTakavHCwVEvkRuGiLCwhL3imEpmUp7Cvn6vE6mFqXibakavFmmGVvnavFVmFM7kAyGlvFsU7yvneiY5pmjk6JupMLHMuHtZwdyA6vkcuE9k4/rCram2uHNk4OwUCuFuuFmJw2wVOvliuGnk4wNFuvmY9TbRl6U5jvnBuHRFwGwVhvHawUrk74LHquEg1wbvkKvENcw6vnawU0SqC6mluGXZysEoNvGutBT96YSrDvlOwWXZwWwXGWEivG+JyT/KuuGuvHBJwFwUiUkjvHZwXWvk61ITWEnzDYgHTWHrvGZm6jgpBvEqwWUqCpvnLvFVk6rvnTvGIU42gabLH+uETD5V4TFQmOvGLeC6wUFuFUR5ErZzfF7Bns8SxJzRwU2vF+R6Unqavn6JBDR6jwXu6mNvEemHKj7m6l0uHmD5KwUZuFVmE0NGCwUqwXjyJRvnGvFU3GKOBU6mfe73vFrFwVwUtibgsDnwX9vl2wVrFzmvlxvETwXBJzNhoR6mWuHNZy8wUbQm8uGDZwiwU8uHe6GDwVqvlwuGxJztwUN1JoohRmEbvmoSxls6zwUZQllwVvVxAIVzuHmD6awXqvEzvEaj7ywXhvHmJzvwV5WEK6H48yBwWbWHpJz3wWVwX+fHpJwXwVnYTNs7DpDdvn9vGpZ5qiISwUGzg2Z7LwRRvkAIVvwUNLGtWHDpmyhFOAVeOnjpk+OmTplEjnXdmmNA7UjbuGMjlSeBBhBgfGNbCck6LQywfF4GE8IU56mt2zbpnjgVvZ6T2mV6k8fGz2k+KHtonFMlz2lz6mEK7n2lVolt6ln2lCdTRGm8dmEK7X2lH6m5fGSWED6kKIUaIXqGl2bkQOlqIX4Ol/KHKIWWjZf6kydk4OmL6kOIU/eJ1KGuYnIOl2amLolGdnwOlcBlmdlSJCdAaGIXpdnQOm96l7onAOmsGn6fGFYG1nGoqEmfH1Z7eQDBWov6noOmVnG2fFGIXP2n+dlOfE/DZ7KHhdn0OnFqGTonp9kMqFaGkU9my+wD6lmYkmM63HT2IVrolrYEaAppdkxfE8OlfKEhGntYEkhwyGnomjoqHkOlAqE1dlWfFd955IVMdnBY4CGnKIXpIWd6lFdkqa7EqGdYlBYGcEhYqF1IXTYGjIWNfHn6kjIVDIVpYlSJCqOmWdklM45JE8Kn8YlCM5z86hBmrIVHYGq7ySGnVIWlIWNIVXfHkOmvKEKGnm4oCOkLIWZIVJYGT+Gidnz+lqji5GlEfFxYFHIXTdklM6jZn4GmHfHjYG6nFJGlCGmmOlxIXxGmmOkZIXzdm6OkeIW2dkiOmzIUYGkAM6GOmkfGpfGKOk+Gn7dknDaqIW9IXPIWFdm5fH3IVGGkDIWOOlWGlNIVW1HVfk5KmB3FmmmVrmWmmhOmvdkxOkUsiPdmuPCSV5ZYp3dn6Mnocg1Gm9BnXvlCMEEmx81nTBnRtBjUl3Bn8TwTyHDBn1wAa1mZyGqMGsoWk1nHBFet7MoXxtlMZyyNx81nJtnUflsMBs1nJtnQfmD3CchGMoWN9zbBmyoUpdgZ1lpUkYfk+hKCCnjBlFopKwRAhF2mEaoWvBl0hEYfn83i/UnKoU6oWPBl3rH524LqC6JZJUka26RwBQhHdtkhGHHPSQhlghlZZZEjjXNyK1noiGpLaL/qf8HwhnLQB6CzrBkrBnLQD5/KeoWPpzeoUuoVYAluoXOoW5ElkhFK4BWIZIhlGGFNjDnCxU0kFjCO8TNUnTBmTAj01l+oVFYGPyEbtn7SHSQr+1lShEwCFRflD+wl1lBHksIUnS46CEqIndMlqKDntkXblAAXbt6VoXXtk9el1oWahHihngamrp5vtmUdDILpftlT7nu8SQdlxjBChm/tldoWUvAiCH69Fi5aaZLmIDahl/QUPel9oXsim4lFToV97GSikToUHYAGdwIdm43m0sGowSiDEMXmRNl9553cx71k+0lBpHOhkDHnmXmboWw5bzWQEdmnNqgHnQpmM3kQHlHoUEBCDoVUOKhhntnlgvlIHl9flVlZSpBg55Tzl0FyKtZKLn0tls95VPhHzm/1kSqh7zkMLkwNmS0z+2nlNkwNn14Qk2nNNkGrCEUBy6FZNnQYURExMtlQYVf9ie6G36EoNmOSIm2kI2kINkaGKIYVWWGwbnTIg4YX2WHUdh3zmDlbxjZttjf0j5HHTNmkYVM+JzNn6+hUYUQYVLNngGGMc70YVrNnuHZuthB6EcyGq2lUYUTgga2kHNmMc7BRxKtnroGMc67wjnNmYYUZ0l56H1NmMNncYV3NmiYWL7DiYWP6GCHbq2RCtlOuHhhziYXfNnYHY7Cxu2mFuEG1Ym4hstlaYXgHaCLn1FwWjY8sQBHHvNkGHaRYYD6ER2nYHbmYU/YnStnYHZSYUGtnpZn6YXYtmCYXaYXmuHdNnqYUwYXEtkyYXoYW66EuYUDs4aLkYtlWHb2YXvoWsNnmQrw2n5WEDRzdBhtTnDNn6djIKhS7YW2mxYUaYUWTmUYWxYU1CwXHES2n6H7YslH6H9U4JbDtgUF+ni6DmyKWLnkGE3/EQ5C92koLAhfYM9CD2mfR6kxSVYWj2nhAX2sHYo53vlzhFBFBBfnNYVKFCfLk2zG4umCfllfkql4lqCIcmbsHAo6kfkvLnYoDdYXNYVC0G6+nbhGDYUr3GbGnwewkYQjpG9pGzYV8fmdpE0c66SiIXHLYVOXT6fnofkG+zyYqc3ET3EG+yXFjscm3akG+yEfmOflux5hXBQ3HSrkMx76ChGXGi+lXYU7YX5ZFoOnh+z6fkGmkrYXIfmtpGLYU+flE3EABzufk8XH/3G4l5LYX/XGdlndYUfXHGhwifkg4XytDJfnomk0faSQB/3EIZHVHZyfnpcm+K5UVhKflEmlyd5SfkBRGmx4OfmDGnw4Ub3HEZHiDDA4Vqfm0HZLYXZflKvZGOrhjYrfYuUEbllY4W4rlU4X5pFOrlI4XzWLk4UW+nol5zYVornhvaeMETYXAZEPLCPvnfXEDRyKhZs4WCvbzIiELbM4WZvb3YV4mn83G1rBi4V4fm3y7es7/LnkZFix51zohZEk4VuvY84WnYWCvYc4Ug6H63FE4UIfnHXE4K5k4W8olZRGk4X+oCz7Zerm04XLXGxfkblk/YVSREKRG/F6s4Uy+ns4WjYXLYVLtCtYVO4V3zqMfnYOmy4W6omefmi4Xo4XJrnhvYw4WRZF+XF+vae4X9zGe6l84WbYW64VAl7eDAdYXsRF5YXTpnIpCjzLXclZunTwStfk3OrbR4dflFukp4Xdfnqbldnl8g7e5xQN46kn54VJFnzjHqdF1XmNyHQsGaJnArEx8km+QRJmRW4F4W6MFFUm6MH14UokkpdGtXkJqm2EmexgmrFMAlmC7F4XZjE94WOOETjF4C6d4WDnnK87EpB+AkUknG85gN63nm2873GgQkldjGT4XEkmBJlvdHbFEl4VfdGjNGyAlWuH0Wq9Xk7yFe1FbHQ4AlVFm7Xnz4X2knFJl1rH9FnorRwtHz4Us9zy+El4U1Az1NF94WbRC4kl9jH6E7hJl/EnP4Wb+GD4UBJK1DEnXn/MEJRhODG9Jkc8EP4VmAlEXll1kyxFFklNrEbJkvqD3XkvXkLoXxWBgEUfXnG0mQEW6tFVAmsqmIOko3mAsClTYnJk7/kLoDUjxoEWe1F9rEajHxnkWw4Yk4atHfqkXeDn+w3Jm/Xm286LWkEEVrmGlC4atHqXkz1l0EX5knQak/874EXK865gm0wUTWBqiIApnFgmmXloamHoUf7nxWAQhC03lfrHnoV2XnfPn1nm/PmNnm8XlQVATCygbHsEXpSEc3nL5BQAUSsEDOogABtRaiACIAD+AB+xxRxwEADiq44AD4bCE4FBA6wM6amJ4CwKZAHbBU7yeb4ETDDiAWy4uYGub67ba2EXN9xWEWMbDhiAWEVOEUYh6KZAaCyPK6C9CeEV2EUeEWOEUfszeEWF4AuPaxXBlUH1zRiOIGI6gXo8Zac64KlKREXvaTZb57iA5wYKd6Xm5OxYxUkREWhGphXCsRYKXRPPCn5jI8kKBktmEX7DPuARDgEm5zXyo3DPuAPoaGRYxsowd5REWdzYEZD84jCADQeBI1aF64V7BxEX0YzsZwEZAKlILb6db5NxYxEWlzK5EUy1a9EWM/AZEUs0DPG7ZEUKd55W7HJZpEUD6h0TCk8D3+knDyFEX7W7nIBZEXoML0d4Rbr01YZRZiOIwd4bpiZEXNEWU4JLZjIi5767iya437wKqOg57644gQGI7bEWpEV4+BweQMcBuprhbbhEXTEWLEUSm5wsCPEV9PLPEW3ZoXEWFYKTEUVOBvEh+uDFEWsRa6kINQB+uAVEUNRZP/QC77izJ81YdEU5wafEUJ/iAFa7EVboETEUkdYEZCZXLJI4IgCK/BcRYokWfEUnUHPEUTiQIkVs1jUtZQkXbqgCcA7EUV5L90T7EXuXBXEGemmhEU3cGkwA2lDs65kgAARn3XCat68wCMkV0kWwYaDCgARnLeQyH5jc4ixbDnSuxZ75nzU6YxD3wr8kU/CQqxayDT2W7L/CaxagEwvx7Gjj6u50fryVAikUSd6ehDiXBbW58rBft6ehCSBbM1A8kUHhlskWGbgDcAnhm6kUe0hkgDnhnV4Eht6eTxvnGJ4HKiCUzZKkWE5BLhrNpalAEqxZ2kVKIa4d4s5DikVBu73ZgqxZM7LITYCKRSkVINTWkXQF5bKBUWi6XaikWehBZFhl5Y+kUakWFOgmnrHtCae7q8CGkUddhCXFxkVWkW3NbBPGRkXq7AHZbjcDpTFhkW1Q7fIgmkXIqg73bzZhEnCskVWkVTTBpAAexa+1B+pj5B7leSSxb50hjpZOnoFxahzlHpgyxaZkWukVnCpl+DfIiaxZBkVjpYBegWkWuyhcPjNkWwwDpTGakXf2CgCAGkUlkWCuQoRlJkUFkUUuqh85pkWMTZRW7lkWZiD9kXimAekWBkWfjJETbrPK+kWzni4wabkUs5BekXqC6rkWE5BukVpIZFkUs5BOkUESqzkW2kU9dJVkU285HkVtkUjkUUvF7kWGWxjpZNZIhu4M2x+kWiLTfIiUkX13avmqZd6nJ73dY/W5OEXCq4doGkMRVd76wAspagUXD9ynJ5KDDES5/kXNoGAUWBEXgUW8bAIUVSFEQUXzbx2EXAUVsjm+Tg+o5WS5muzlEVpxb7i5YEKtEU2DGmJa87A5EXj/m21b7i5w9LJEVmQ5D7bh9rEUSCpiAymkUXu3ShGowU6+pJwVC434AvxOxZdK7taRxEUvfkX4HAKZ7EVKFh3NafqBjqrVEX+ezcUXCQLTb68uBsUWIaAkpaMUXUghlJbUUVxEWlEhVEHnPzTEUUUXSzafqAycQ0UUTtTRJY9aFlEXukBd/BZEHdWh4kVcAmaJZ0bAgsIj8pTd4SdzE77MTSSUWZpyp7xX4B8z57MZKQSfEVHjECUUGUWrEUgbAOUXWVQLEWTFIXJaWymvEXmUVKUWb2bqjQuWHaUXyUVsy7HJYrBajhhTDR3pauUVLMR/EVW96iUU2JbJUVDd62UUS74ABAJUWWUUt0B0TCtpL7JacEiokUf34WUUNTR7EURbqKUUshY60LWUWBUVP5RDEX2UWs36+lwpUruUUuUXWbz18jOUUiUXZYI074NUXZJb0UXI74bphsUVaJRhUUVUX72CkUXKUXhUXyG59UULb7RUWm7ZdUXgkXRhE57ZtUVAkUp3wZUWijjo8TpUX6UUc0B9EXZUVNxZVUVEkUzUVDJaCUV4kWrjHfkWZllSsD+s5kmFPby2ZT0kVe5xZSzXUXoxYskXp1zEapZPYckW1NAWwX8kVRW6fJGUTDWW4+kW1NDFgJGc6ikVi0AQagSkUi4hP6HPwX8kWSkXLpbIKAykWA0WDJEblRrW6/UWDJExywfUU8kX7JHPUXxpZ+4j/6G2kght4UHjdE53UV4eS3pZft5PUX3UVfbQIZZJuY3FaylJR6GkzzXWhBvqPUWm0DlejOX4+nyspGOhhMnDOkVas5A0VF2jukVCgjf6GcwXhkX2sCn6GXtx7B7mbh36Ek6g9kD+kUi0UUOp80VE0VI0WGLDRkUekVo0Uk0VNtjM0XY0X/FZM0XR5y7ki9F48EgIZYG2xmW7bKKwwAZ5xJuFxXYxkXZlzo0UDkVU0UZJRtCjtkXwF4c0U00WL2KZkVi0AM0V1kXYSTf6GO0UG0aKwzf6HA0UgQ63Rw80VBAQHkXc0XLpbg0U7kUMxmDJE1wUbkXB0XlllBnYrkX+0Uy0XTY6FkXAGFXUUE0UXkWwpEPd7TkWJPCMpF+ymx0UV2yDkX7JGS0VW0W+gCnUW9fn2RAXUUY24WXDaggPUUMkU2YD35A40Va0WtZZV0UvUX6kWV0WJljckV42CtZb9pQ/UX80Wt0WY1Dbg4bPzQF42YBY8rIyBLQGePF90XlRQykWQ0UW4DdTgw0USd4DSEW/oI0Ud0WjZYZ3JakUt0WjZYpZT10UmJbL0U+Ejl0WEgBtSF10Udo4dkWV0Ur0UoN6g0Xr0Vl0WXm4OnA1SG3fDTkW/Ki57nb/Ab0WfkW687H0XTkUqX7o55oVZl0WlkV8+Ct0UghoXpbVkU2YAq2zbg4PkWFA77Zg5HA5XY9kVFI6NKnUkUsWGwlKIDyb0Xlq4H2En0VGkVEtYOCRwMVZWwMtaVdCWSDN0XZU4ldDTBj8kURkW2whBWKKkUBkUGFYzEgQ0Wg0XL5zsDjEMWePHoZxd0ST0UEMUnSk2nSZvzqkXqVICKiL0UYMUudJIMWY0XqFZwbo3UU0laIMVmkUgMW0FZ8uwht7C0WWFbMjzQN4OkX07mZBYaH4ukWEMWIYBy0Xc0WiZx0CrekUd0WkMU0Yji0XsFYnijBkVKkU5PLmHDu5byYAMMWnARMMVPnpyMWQMVwMUJkUcMVQMUpkXjO76MXHJAZkWDkW+5zaMW70W686ldJEMU3kV8snjhnNH7/0Wn5awXw0TY9+Jlc64MV7Th50UV5ar9yGnDdkUdkX4FYzxreMWvkX8MWm7JjpY8EieMUCMWkNYWTSuMW4Div0UzkVDjG4VBoMVe0WnkVvCS4cYX3zG0Ve5bBMVB0UCAU8MB4MWFMXga40wio7C5MWrkXwiQSMUnkVFHbSMUD0VJ0VlMX4FAyMXBrDVkXyMVSbpRfqjkWiZz3RQ3O4+MXgu7KDxn5QBMVqMUwGAJMV8MV2MWkshm0X9MU4CrWMUeMVmMUpMWJMWBMUa0qP0UBLRNMWjlDzkXe0XjMW1c5R0VN5Z7AEjMVh0VFMWwnCDMVabpf57dMXJtCVMVGMVMX4Ggy1MUwMXNMUNMWpMVJNZgMXF0XXuE514GiTMkUMkUShAnWTV0UskUfMWvMUY0UckUShB/mnoMX7FY1Vh9xT0MXzU46nqGUYA0VKkUg8DniIg0UUMXYMDdoqj0UkMXEMDLCDUMUkgWoDjVqRgsVcklf/CcUTMMX7FaAxarcTskX6kUGmA/4ZfMXGkUAsVgGrczaRMUAsX4Jg55Y10U/MVEgbJ65VUg8gW5dqEsW4VZas40sU/Axc0VilbKnqTfiE0XgsWR7D/DyflbQsWR4gtUbCsUBkUwsUgqJS0XgsUEsW8MWhMUvMWMsXi0UsgW6BB8sV30Wp5Y6nq0sUvkUtkXmnq/MUs57O0UMsWEsWNMUssWAsWZMVFHY6nqUsV+0U8sUjHG5W4GnwnMUg8DLbDYNZX0V/kF9QhSsXnMVNTFYcEht7NhgaDYKsWGsW2sXzuGPMW9+4T7rCGpcMWnNnBsXQMWhsXoFB/MUN0WahlxNB4sWnNn33DYMVz0WJ7pNFhQsW90XLZkJCaD0VzlY4noVeSZsUqVbXzL4CQWkZT0WGlYVEZYsUjNnKVhrW6fUUjNkG8wht7IMV6VatMV7VDQMWEVYZDSrXxvpaRMVtlaqsRxsC00UV0WFg5hsWevDMsXtsW9sVK0WnNlXeDah7y0WFg5WlI6MW/UUDg5QpiqMXIVaVtzisU/HmYFhHnDSsXG171sVysXW0VBsWRsVKsUsVZhsWzMU7sVbsVv0XUnmxLCYB4rMVlsWzqjrA7pW5lsUJSR6nazTj4Zbzlazgg3sUWcR0Va0nE2sVOsWnNkTsWWsV1sUx+i1yDXMURsUNsVGsUDsUHsUTkWLsUdsUiM6xMXvsUtsWTMWnNmuODX469IIm05NSHLsVDMWcVZ1WK9MVtsX3sV5BSdMUUvGcVa62pf0Xm87YcUMHhrq7u0WcVYPsWmsU7NmEAwKUBusVfsWzJp3MVOsUF0XTrHyo7MF47eAao6McUZ1DKo4Tloji7p1aab4SupyN5OjBvWDMcWKF5McVccUs+qYUUWw46o6904ccUmDAMcVl+oTCAhEVPMXhyHHs75G5Ro6JWD3I5jPJqxbcdrNvD7C5IEaOY5KcXVcnjYDdt4v57PDm6cWtAlUm64RTKcUXOyFfxbJ4DsSjjgwo4URyGxbt9Br8gwo6ZRmUKEjKSOcUr3gNRpHnA2cXXijIOCW0AXxbwc44dbIOBQTiMi7GcVui7qcVvJz5uwzT6KVFCnD7C7iQzeY46cXP1Huj7OVZxcWacVngIpY5xcX3I6r+ovRamcVGcUXuQmIzAxoTgioo5L7j3YLAxo1CxGi4Y74NiCkF55SzRcWYHLubC+JoYzhso4gTRE0C1cVmcWll4om7IOCqgiwEE1IDcIDTY7wjkPAD1cU88hui7IurfiB9cUtRkBcVpLJ9cUWcV7M7JEjjcX+cUg7nekDDcVnRlxRpbNB9cWdG48tqFwD1cVdcVg1Y9ujNcVqsHacVbcW6cWeSBNcqrcWMi5pRL/qiLcVGgAF0WycXM85L1aDsW40VlLk3cX0sU96CDsW1sVlLkjsUo0Ut0WoNYJsWlsUINYpsX4MU/1a1mRwsV+5b4VwYcUxYgUMXYNzl+C/cU6NZclyz0XqkVoVy65pvcXZU7XcVbsV6kUMtaI8UNsXwK7ksWo8WCMUhkWY8X/FavkVw1H7YQht6sigo8VpjBI8VeY7E8WKoU3FZ4VgC1H+FZwATMsb6sWLpzzsU2MUhYBw1F4GRWVYLMUSNYlsYxMVdMUmaFpM520W2MW/5yMUAhMXwF6oNYwcVC8VQ1G7ywyVhQcUZhGxsWzMWoNa7sXAcV3cVAcUfdIsNZFwQ/sVx0VgNYS8XlfCUcVVLm7IKlMUSNY/cV68UxaG88U5G5+y5uso0Ci/sUINYvvKEcWzkWLpxW8UuMV/cUfrSgsWy8XbpwocVasX88U1ywhpZqsUO8Vf8xi0Ve8U6NbnsVu8Vlc6w8UXL7O8VzA7/sUK8X+zHy8XK8WuNbN2GMS4LkX+8X/SyfsU6Nbudr7MUx8XchSe8V+sVp8UnyoSB4m8WYNYEsrhRQW8W28UZsWNMUXcW8vbgMUiu5C3aK0UCkUK1GP0wE0VqkXzU6sYBVUhHFYtXgy1GriSdsXwlrkd7wYC3RytsUtkWYSEi4h0sXc8XGE4D0UWMUGNahHjMvl08WpkXoH6vDAvx6WbQj1ZIXgtkRM8WANaXCCy0Ud8W1U6V8V18WaizYqBctZN8WJsU8oDg8m18WCMXx8XwYA78WYcWgy5lJKs0VapgmLKi1GOYhD1agIgCNZD8Vs8VjMXZpzYSQ5XbUsXZpyDCh6nbt6ygy6Jww6tyn8Vz8WVlSR0VZ0VB8VMOGZ0VwcX61GIciesWEOb/8UQCUaMUBkXL8XTY6GMV+y4oH50p7prw3860oWk4HfUAWcXsh6odaYCVedaeGAudbvSSDtbh/hLOpV4FwSp5ok4CVQnFZ8TYCXftagtwrkH4CW7tY5NxA6jUCVHtbv9y0UZUBA4CUFa5i86AkwsCXGQCsdbEgR3KHZjwYyiWD4F9pg0CG4FltgFxxxARLKHRtArRncCWPtaLyzTkmyCWHPHhYHKLaSCXv0GR/FECW1jnoqHe+FzkmT/jZdnaCVydbECX54hePEom7yKmDYld+GAm7yKnn6l+t4JRlUBC5dax+Ff9JRIUxnjD+HLZiGIVPSo1+H3G4OBBCGmEcBM1i54E6jE1HBm4HiCW+CWHzGlPFW6yAV5OqAhfH1wDlG5HdkKdbRtBYCX0CVyCW5aqrKGbRC7taWkQ6CVzLAEJKG4G25LooU4CVG/E186KCWeVFELwVdn97AFPHkqg1tb5CU04FrwHxfF9tZk4ENeZnpz8CURCV1zzttb1CWuVFiWl1CX24nsPFZCXkCU0CWtCXooVOCWvInKCVBCV9CXZBEWCXlCWMnwjCXJCU3tZkFZ9kGqCVOBGUTBzpyjCXBDTXZwLCUtkwyD4fSHBBEvRkk0mVfF1c6Ym7sh4hNjaPE7WI7CWGCWGaDrCXEUGRqBmCX3noKCVx4kjKE35Z+dYvZHntac3xrkmgyBaIV/k4MdYOBDsqErIkzT6eCXcYlTCV1CV+CUFPGxhjTCXXjmw4B5BH6cXjKGgdZ5BE+CXRCUBdYPCWEdbxCXxBH2iAQFxwiWWBEDCVQiWf5C4gA1oF1oE09HJVHB8xPEHb4ALCAn5Krdbsz7ndbWEUmwA4iUv87L4AVdD77iHdYASaBLBA84JPCrdZQFb3EE6gAEiW4iUUiUZ1D0iXUiV4iWUiVmEiPdZsiUcMBNInOL6DtY7eQudaCiXpMkL0aTCWZuo9tbCiW7tZttbtFGgLzHIhY+EEdbglHiiUiVGWBBiiWndzLdmjtY1tbSZwhKEyDZUCU6iVRKF7taLtZjFw4CVbtZCiW2dC7tZmiXqiU4CULtakKDhZw0CWXtZv1yJFx5daOiUnlx6dZiKHXZykmS7tauiU+Zx2CXhBGSBqftZeiWTCW/taAV5khQCCUAZiOUlhiWiCXgdb65i2slbCXMXZydZJ+RSCWSdZSZwWiUSdbodbw2FpiXtIkCdbS5wIdacdZrkmQTCudn8Tasdb1Tw36kmnrUdY+ZzDtY84EPKKQJh94p5FzFiWhiWZTzPKH5iWEdYwsiyfH8dZedaVmT+fHHUAuUDw2EqiUFT7CIRSZz9iVodZmZ4D2GamTdiWU8oflxYpCqda6AJ9kFBiXEBHfriIOH9iX6dbHDqY2FZiXoBFZdZFZzVCUxdaHFzLtbkEn6EAgpzOiUOdb5da5iUudasLDKiV7iWedaUNzziU+lEneieiXjiUtDaJdZ9iXUiohfE7iU+Zxv0bRdb6cERdZJ5wZHKYEm9iW15xuCUfmZ+dYGiVgQ6nTidiVHiXQdbniW35x+iXFdaommeiXriWZdZOdYmiUbtYVda35zbiX3GmxPkISUzdatdbISVHta9dZCl7SiXNdZGRoESXDiWDdYHsSfNKyfFBcQTdbyLLPKHYSUTuCc5zDRBoCVYUW02DNKmyKjC0bhsXvwCUhhksU7U6PCFLMREsUMtbXxIm/BAsXB9bpgy78XzU552GarCFsUBkXdIACQwA8UU9bZzBpB6P0gUMVYJIm6BosXs9ZwgCqkVyhTqkWzYD+uAVsXakWzYBTsir0UJ9bZyh8SXo8Vb0X8JKVQg98W2MWCSUKvJvpb0sXXxKGSVMsXkNAm9aOSVs0X0LHrKC2SWyMVa9ZMFCWSX8sVe9ZvxJEHiqMXDYA3wicz5KkUySWIZQrsXqSWuSWmljC8UGSXsSXjLRIwBvKl2zimSXH8gJ86cSWuSXHMWMo7dIC+DSTz6QIhYqk5SVu0WzkXhSWWpQW8WXmpR3ba8XHIBDb6p8Xs9bWFC+8WZ8XqSXk75J8XvwAi3LrMWnkVxSV8SVGsXNSUZSVoh5Q9Z4PxPg5+8XNSWNSU20aeeKl8XswXJFm5GSd979gR8snonTLa4QqBUDbhHFhzm7CUAjZ8jbywBcblzSUzDarSXdZlGQRbykUabC6HrSUYHFqiI87bbSUjUkIrDg7b7SW4z4Aygv95TSVAHFAVT84EqgTiHFnCXs7bAgQajZLSUD7YVUysKnqkwepnHSXP7FJzCrCUDlnsh6bsAqCXo/a6h5+Ca+fFh0HIjYpbaczkUGBeDYgyV6ixBKHGQgBDYAyUufB3SW9xShQ6IaxS7Zl/hyKn6gSTzlnCVkj6AkyzSXnCT4DYk0nzSyqfHnDYk0lUMpJKGi3AGKnTQgeDbzvh2OGvSW0yU8QBB2HkyUGa57XghKlX7GHzl93jijb4yXF7bnSX00lVNhJIXSjbfSxQyXC3iPwmgKkFuqFYkWDYfd5fSXXSXY0mDYgWfHJjYVh55fRgyX/SV6bYEihgiUDyneFkRDbPSUOKnIw6YdqTSUcjTSb5RQ4SyVL96yyVnD4myUPZGf9HmyV2DaRqD19GSDaAyVBCXQVmuQ4OyWmyWqyVhmg4LnnSXFUm+qHOKHAyUFDa3SWuyXSjZMFkQ/FmyV3G44yW+yUo+kt7aAkzKFxoZAyty54ENdY+D4xyUeyUIyV8WkRyUUDaGCUg46N4HrSyqD4AQhYyVByUWfEPDZkHHt3mJLa2yVEyXRG5vSWtWzvykiJk/9ZPCXaKntpDeyV5omKyV1yUWyUzozMyU4+nODZsyW6yWRVDlyU+EBXylFyWGIWByW1rTmuF8yWJyUYyWiyWI0DoiW1oFJVHjy5u5Sfa7YYC7slEhJ37iazAzyV/a5+tCKjYLyViTCazBryWzyXkTBgppdjZWDCSw6x2IryWEkGHyV7yW0iWF0XsjnXuEADY/9ZkhR7ylrDaq5zTlmgDZIDbpFzSjbWQWJLZrORBsGPyWLSWU0i3yWnDZjFxWVlkDa/yVguR2yUoJ7PFF/9qTyksDZCxJsJwC/5zyl3yVv5xSyU4Db7FGg6wwKWsDb3yVWyXuJ4Ga5guTwVkTUm9IbPyVoKW+lxL7bfyU9ynwfyP0mtSZ4yXJZSTzmEKUjUkUtzaa6IhSdyWbajC6G0KV62H6DbPDZjBQfSWEB7Ja43yUzDYWy67iXSja2DYRDasKWW66wKXISXRyU+DYD7aQTAwyWBDYHDbS5xGVmBDaMDZ/yXJxRdJmg0T8KUbpC5yWojaqslYKXF4FJDaViXAKXpDZm0Q3ZyJKly4E0KUCBC1yVlDYH2B2ZwlDYNDaijYMSWtyU5DaqDYrMjsyW6KU9a4wsjcyW3dZ7a6UKW3DYIjZnZxSyX9DYeDbOKWsykTDZWKWcKUKjZPDZmKXuKWlJmxDZhKWt67khhIFzNDZkHGS67XyW9BoPSXWrK+KU9sityXJKWCJx/TJudGGD5yKXvyXvymLDb8KVgKWjymiLR4OGkKV8DYBKUsKWlKUOdbWMDn3AgQBusnLSVUjaeKV1KUVSlAjZWjZwKVgjY93BuKVIKVrWGAKXQKUGWGEDgZkqniUiKU/iR4OG9FAfSXmDjTlBuiXSja4jYcKW9KWcjb+jYmiUkjYCVqxOFSBSXI6sjatKW2sl0jZUjYxjZ/yXfymzWFm7xFZxkyVrKX2jY/iWnW78jaxOGZTwkcEojbBjafNLcyXTKV9ZyqyXjKVtLaRKXQ4ElKU9yXqZn9KX9Lb2KXgdHdADajbaKVEyWGWFaKWqsk9lkmjZKKhi5z/SV2jY0jZBKWmWHUjZRJyRKX1BnqyUK4pcj76JktwT/5zgqVl7I+jZQqUiWGBKWzKXqWHzKVwqVhjaxdEXKUHW7Rjb7KU+ZwpJT+WHoqX5JwrGlu34BsUNx6sfDnTlvMUOZyF8AMqUhsXGpksqX8SX4TZL7gNVpxsVoTYovRiSUUJwJPA2ripsWipk7aHD8VKSXnjaZvDDZTkMUSqVkvRPPBSSUqdnR3jQ8W3k6sfB6trw8WCTYk541sXsMXq1DYbjcSUfZzMqWASyRSVsqUGqVdsVMqXk8BNbiL8VfjaiqUSnY10XRTalmKM0X9sXq2Yl0SSMXs0XgxKXPBeSX4TZmqVj1adApE0WTBJSqWzsVm/BPlgLsU6Tb1maTsVz0UqqV1VTuqU6TbsqXssWN4kaqWq0UOqX/oARqWk0XBqV6GxWSXM8XaqXsqV7sX0qXGqWHsWUTaJqXmbCFSUHuk8dCaDhN7q4d45TZzYA3sXG0XRTYwvCPsWbkVoTZTmTX45vsXGpmK6bsO7y0WGlEGlC/sVGqXWmCFqX5dncOCp0U+nzBpmopCdsVZqWjLB/PhQcX1qVH2JIcWuqV3MVgCWWqU2sKocX20W+qWESh/8WWqVtWBs8UDqWrqUb/jW8VFqWg0TLqXq8VzqXNgRJ8XRTYiuRWVa0cW0qXE/FD0Gk8W3cU6yH3cXfMX0tBPcXsMU6yGvcVxsU6yGfcX18URTmTNyC8XyqXOzZ28Ug8W9vmLwDA8XiqXVc5ZlLg8XfqXW6FQ8X8qUyzYPlB6SXvcWXqVo8XNfDEsVwaW6qVAu7q+Ck8XpW4dc6oaXwaVE8V9zYlUnt8VBDDAvE6yEfsX667MsUezYG8XJqUeza/qV60XXc4svjmnwWqXW6EB8UmqVec4rcTHQ71kUpTmk8VU8XUzatCDsaWXsWf6EXL6ICU4aUygiT8h+SVQaUp8VBSVl0CAaVCMX56EviyKMXqkWvNwZsX8aXOzac8VuSWKaWLwgglZ5SUUaXyaWHeSpkUTYoF8XkaXiaU5sVHPDjcAoaXm1KX0V5MX3qVAcV9MWJTnSaVi8UhTmsTgzqXUsWqYqqaV6sXaaVDPjm8WdSVyaWIcX7qVSaUF8XbMU4aWOQYdW6ZSWtzY0aV1SVvsX0aWJ8UVSXH6Eh8W0ZinkVIaUIB6nsXKyHy8Vp0UQxaRaWv46WaVhaVCaVe8WjSXI7nsfa2fLZ1ChMEtkqK1xOTrGzC07am0ANgjRDEyLbDMEBkroLa+DEAfFl84fRT8LZUF7Q7alaX67b9sHbeI4jHUuij4jRDG+LYqEmFBpr5BdaXLCoYjHN4S5Cn46iLqQHMEo3ANaUEVRIrGgaBQrataXcxZumGmKTbQWNaWggkb8LokU1aVr0HuZaL4gTaUVaURmGbaXRDHFaVDqkt6JcLaFBp6Lbx1wqZqk2HmuCCLZ1aW7aUlsGMLbtaWfWwL2GDlRIrEFaVHaWJLI/9bh5wsLYAQUDaUHMHVPCGLbBZLhLZjaVkUQkLYFgkZXkUtw7LZ4ClkLZjaXNajmLbSA6UmG6VDh2Hci4s6E/Qlj4SnCmV8zFZghW7jaVA6UggBS7Z/pbvWovaVKLY9aXHUaNxCY6V2hZItHPaXE6WnvHNaUPaUzXZeMFVaXjLanS4Q6VXaXaQrBsEZCgRDY/QlQ6UkLZgi6s6W06UC2Es6UwjEY6XgLaIqBvaWg6WXLawLZtaWQ6Wc7YgCmTLaAjFw6XmLYVUX6rEGjIi6W/PG12qUmGusSJsEDUXmuGm0CbaVI2HM9gmrEy6WsLY7AT5aXM9jeLZ+hiEtGWlB8UCsLbZxmDXkK6UpLZRipC6WSlCZLbcLaJLZs6US6VEPA7CLo6XI6WsLbiLYxmGq6X8LboNjC6Ga6VM6W2LbCoK4WFnaXRLZe6WG6U8nB6YCzLatLY5XnFajVaUo8RVa4baXx6WowL9LZ2DGiVi9LZtxkwjGR6WbXZRcSjaVumFbeQWXbmcT64Lu6Vg6VF6UeDYjsDUnygra56VvaVZSwfaUydSk8hpW4GGQZ6XQkA06X3aW9LZdLb+MHc6UwLay6TKViG6X1aW9La9PBfAk9OgtaUFSTw4iG6WQjxcLYFLYpmG16VE6VGLYk6UmrENCCTfZGtBjEq66Ue6VGLZ7LbemEF6XRLb7aU+qnZ6V+XaLYACdS1mGHaW9LZgPSx6VG6XHl7zNxfaWM6XjLa+YBA7Kt6X1aWzLblHi96XX6VLLZP6VtLZJ6U36WGoJ9S7zaX5by7LZ2LYYjE3Qpt4636VTsoHMG2rxPG4/LZorCd6Xn6Xd6VhASm6X26UVLab340jbO6WZLayNyEtFd6X3LY7VIfDYf6VLLZuMy5DbYGXd6VsEjf6Vp6WraWxP4rLanaWsBB1LbC/bv6XsOC38CUGVTM6dXnC6VqLb1wAbgqAjGL6VV6VUGU5Xkz6Xm46kGV7a5uW42LbNEpEGXD6WF6W4GWqDYB6U36UKRZYGVd6V1LYUaxIGVCGXSGVNxmFl58GWFaVLHEdapeW5injFLbE0w+jYV6WnBzyGXgrZjaVr6UqGXUeD56X1JTyGVnLa1mGh6W8gDU6V/LHH6WWGUyLaUmEP6Wp8CbLZsrF66WOGWD6V3aUOGU3jAjEIyb5laWHAAfupsrGhqQTXbJJ4sGUHMEBGXvc4iAAYiVTyVcim4loDCA8tTErbM2BDdCl8oJoA+ITH9BQECvBgorZLFJpXg8rZ3VLKrbcIiC9BGLYSMWv7YnbborbZGVZQAZGW5j68cWx4AJGWYraxGWZj4Z4BVGVMrbwQR5GX1GWkUCa8q1GWX1pWZCqOIdPZQHZ30DZoldjBe2FzIkpYR8XY5oX9GUoom9dTt6XmOg6zF08zbQV2PqXiFCol6hrR6XzbyzGWOESGLYsIohZHF/STfb6Ux04W0f5BUGVLbjcBFfna4i52Hr3QdYUHGVDGVtgJofkpSQ7GWpLaBuSGRHrGXTGV4+yqfmkHq/aXxXTo4WhbFowlXGWQ4UCxiFfapLY6AZBaED7KrDFHGWlXGBiKF6UnXQ64VAmUn6XXny/GUSzGVLY09ioNbgPGdLYTGV7hHa3HwmUjGXbpxZRELGXYSQBrk9/ELAV7266tTnLZYmUOnZZLYdupCLb4mWcXbfGX6fn+4pKYDRLaDCiELbMKSXGXPGVj3GRYjTAU4mXo4VoQTxDH0mXpLZPJx3gDRLYMbjpLYJsTIoD5LaLGWYmX6RikKAD6UOqTHLb9J4imXQmWd1wBWnlppV6Vl8azGV7/5/eDjGUomV8mXc6nImUKmU30j7RlGLYYmU5LbhPovEDomUImXetbdKgL2F4VoiflOfqSmXvGX/LnHHgtEDcmW4mVCLYVoJcmVGLY8mXnLZ0fqmu5UmXXGX2mVrpQRXBUmU/GWHiAGwD6mXqmUBrkPZySmV9GWzGVX/SvFAGmUomUF4zCfDRLY6mVCLbRmUjD5GLaS+IRLbBPTemVhLZDYU/qq0gLcmXPfLkLbhmVawB0cWGw63N6mEUo5ZsxHb5SWEVm75VTAk46m/heEUlmW5iDVmXlmUicWiN4rTwaCxmEW5iDNmV+EWNmWKN7tmVgUX2EUmDD1mU9mUVmVHwCXcXLoHruwaUUxW4TB7boV9EXWrLZb6DrZJEVxEWZQiw448gTpEUpEWLmU+v7kUXikbSzZ0I74zi6UX/EV0I4rEWtEUVEUQt7a8StEU6KRda5R1TE741EVnmVgjhboEx5h9Za8rHQkVFEXDB4LMDiv4qUV5EU5w4vmXDEXQrFLmWvEWwkWprbfmU5EWXEWrmUPeRbRDkkW3oGBQXlUWD3BOxahMn4zhYkVZ7Lf1G9CAwWV0TDtpQ5w7NaQwkWwlqFZF00z7UVmOAbB5OiZkkUQkV3mVYsztUX4WVsUlnVLdUXYWWAFaDrYMchoWWo76jmUAWVvEUtw5zmUMcBwWUtw5UWXEkVQWWkWXzUWonksNyqm7sSYNmV3bYUFB8WUZ1D57iqpa1mVHRa8WXuEWdmXGEWr9yCpa9mVWs7SWUdmU+EXyWUDmWam7iWWIUXOEWcUDDmVlUFCvihRLzmXMWWyPhZkpxEXnREjxx8vg6WWsOqQkUS/BjmWEqLtEUWWXrmXt9lBbZfeqFEUrmXhbY5ngqGiCph3EU0bZhBHiUW/VH1bbbKIXmWsJBtxb/KDzfDzmXuWUQqAJajzmVjoTOWWaixTmWDfTdxb6WXRWVWWV3ZwmWXBUUhWXaWVjmVxjThAAxwlXkh0WVzUEYRY2WXjEU6iQeJaVwzTb7dip8taMBD6qwnmXj0ydbaAlgNEXdEUZWXjL6mWXNJgm1b1WWvEXnRH5bYlQb+UXT6Q9G4uWXlGgj9Qs1ZKnhgPBbEXVCzA1aeGDNeifEULmWRWW1sIDgg+1w7EWr5Az7CfEW9JGRWXVcrzUV2WU0bammjTUUKcB8xZJWV0WWtWWJbZpTT5WVJCG5WVWUnrWXApG1EUBgFkWUJWWrWV0obHEXkWW+Y772xfZjUWWTEUBdp5UWIkWmbZlvlrUB/EXDB7wr6uWXEWW3WUOWX5WUnWUGbY9vn7WUQIy6lboCXBq6vpqczlKGUGpy0YmLSWU6UA7a/NyTzliGU47a0yGOMFSGUCQYeplw2XsQYGa5oZZLqgx7Y/agD7ZxW4Rdzw2Wgvx26VDaVoJxFdLODY/QmA6VsdLpKw+qmAGUiJxY2Ug6XM0gJnDE2UWMbLaXYTrokVzEDPigyb67aXYmCI2Vx6XELYw2UlaUraUtDYQ2UnaXSMpR6U8hAY2Vo2XMOjY2VyGVn9K02Xj6VN6Ueppq1rT6WE6XsZwq2WU2UmxxRLYK2UE2Vm6XaLZn9KMKLOGUe6VS2VNaUSDKc7ZATLc2XIGWAFbHTL82XW6Ux7brSEUDZU2Xm6WBFpx7YhW4/aXQ2VGBg4LnvaVE6WBFoq7ZK2X/Vy22WI6Xy2WaZKSMEy2UeGpNaXoGX52II7a66Xs6XR2V2DZI2W2Vzx2Ws6X62Xh7b8rZ26UeZTSzYh2JG2Xi6VSLYDWLl7a52U22WTg7y6WZ2Ux7bfmoa6XAyyEZ6OoYh7aJ2Vw7Yb5h86Vx2X12WVaXQGV12XgfoA6Uu2VrFqp6WMGUx7YNlq3MHm2V52UYnFO6X92U22X8LDLa5I6V87acDD+6WV2XU7aT2UlmFR2VJIR4GXGdwUGVWSq0plGZZnaVy7YV2zUGXQGVW7Y/SjVNHb2WI+IDKXuDHp6X/tAx2XmGUUGWqWZa2XchS0GXSeKK2Ul6WXLY32V62X8lK+7YX2U16Xq2VnK5fJRc6V4ziK1wH2Wp6VyGVm7YIqWJ2Vc7bbXicGXb2XyAl4jZ1aVlaW7eLZCgE6UT6Uu7b4vhq2WcCga2XUjBmKXaGW+7bK7bPDbj2WXLax7baa7u2Bb6VQOV6KXkGXCi5gOXJa7EGWi2VvbJb2UP6VcUqU2VSGVOKArKIv6V97Zl5nv6U0OWMOVn6X96XqcHgOVtDG/6UmHI4OXTaUpNBW7Ze7aUmFgGWl4G5UGyGX72Vx4yF2WaEEiOVRJzW2VnK7iOX0OUiJZkwR0OX4GXyJZIUA8OViOWq5QkOUi2WaJYBqQza6EOUala5RIPBqprHoODX2V4EIejaYOVaUWmOUMGVP2WSJbqNATKWG6WIOWyOW2IS8GVk6VwxKbzJ96VlaU/ao4OU0OWKOWSGXqOXuwiiOXTrgqOWGhDmkyN6X/Vx0cEA0n2OXqGVBOVs2XyrFsGXROWDnDxJzmOVDJYBsAROXGGXX2WGXIhOV6OXZJbWmxIGVaOVBOUCOU7aVM6XVDocOXD2VnK5FuQkOXoGU0GqjXlt6VIAn1eIhGXjbCdJbW7aAjGhGUTyWYiXcQmaw5v/Zf7avUhtGU8apdOW5GUZ1CdOUIUBlGVgHZ2sI5GXJGVKDAAkDvypdGVtGWDOXX7ZJXCC9C9OUxGXdOUspYAfoNGVjtQpGW5VGrOUtGVFGXP7bZhCbZGtGUycU83mxxwlolnmo/In9hFm7anOUvz4SzFhSr82hMRGmSDyG4G8SXOV+FzWHBc7YR/jnGXrGUUZwBmBtJwCfa/ajv2Ur9FCmXmTg72VoRIhZFTGU72XfOWJRpPhHq7bta6wmV/bBc7azGBkZEYCjWUmitDphiQmUPqEs6DgbiRZGguXouXs8TEmVVMzMpzIuX/LkHSyYbxwuXLUg5Lb9uyVkCe7aoLL7LbkuXclzK7Yl2pBaGfGWl4GpPS4uUGdpAuWXOXcSSJakXOWzGUSmV55ZfOXHLaJOZkOUo5bk4WKmU47bZCSZzaemWAkCiuVKWRgfkCuXQ2UuCaRrk8uVTxx0uUKuWIuWg7Y33Yj2Gtpza3FojGViQsuWL3FWSoNAqSSCsuUEuU0mUSj5Z2UbK4MmWquX4uXmuUcmXCmV55bGuX8uUHkDTVAb2Un04umXKNSUmXYuVj3FQwxb3Ab2VvOW6mWamUS7agJbCuX+uXZJbMuU7NaG4VcuUBrmumUXaERuV+uV1wx5LYxuXxmU8yiLkEJuWMtZHIyfOWPOVhmVo4o5ZEnOWZuWfkI7pZmuJLiqJuWvIB0XFhSqywzVLbxgy/2Bc7YGfS7aHVKZC4BZaVo27l8XXuE2hyGkXXqUpDBbtiMqUDHZ5UbJkUIaUVH68vGVkXQHDakWlB4RDRfcVtrB6mDCqUGHaVuxiqWykU2H4n7rbkV/qUzuVVlznVBgaXQrCrpqQaXqYWNwAwaXmH70PCGkXPcXqYXtuVcMWMNkdzw6MV5MXNuXduXoaXBg4pDAbuX2kVlkUGHbgmxzW6GaW2MV3ByuOY9Za6pjXA52YX7uUGc7qaVtuVskVsoZ9GgGHarmCVkUnW6OYVXtg5MgW8VntkXYxNSUG1bXkWBaW3uVitynqVPsUGHb1yghaUnuWAsjLkXRaVFHa8HZRkVAeUGHb/QqP0V+4hRjbbuXjkUsrieZlQipYeXy8qpkUBx6a0IrqWmHZRGYJMXUsV3BxweU2aUTuUtmiwcVjMXgeVjUhS8WsHa1kXUeXpb7UwxO0UUeVduWP0UaZhq77nqU3cEW1GKsVmSUDHa5UpssXwMVSeUBpAyeW7uUwrFcsUvqVnRwMBIjuWwlQyagQ8UplAYyhTuWSkXaeV1XBIsUUMU/CGosVaeWoxzMqpruW+lBUyhqqWFnZ4LyaqX/MXieUyeW40VzxEMoZUsUtkVKeUFBCMaXdnb4XRmkVq0WdxH2gbOqXpZniFQeeUKaWdxGgtKhqXqkWrRxEuz9m4hkWrRx6/ihSUBkUAxxPULEM4RkUOeXrsUonYQlwyeXC0XOeX+eVgeXSeWP0ViMXueXDqUR8VdlEk7r8eWunbCih/0VACV2HZu7yFW4DSUvlkPZpMeUplD9vBbMVVeU2eVWeU8eUZeX9qVtMWpeVxaXu0VNeXteVeaW/vYtA6+aWFnbXmghaUIeX6eXViTVSXaeWW8iOsUnuU1eU0cVH8VRsEeQLbqWBeUqxRxH7FeULeVs8XgcUzeWwXCB8XVeXf2k9W6ZaWieU2qEILazOwduV5XbneUhsXUXZXeUcqV5XYfCDCSXUXYLRKQaXUXb6cjjuXlXY2dxySVOXZQ6aGeVcWn1ag4AYQ8WKXk01RKqVe3bkmgFqUDuUt0WsXa3eXI8XNfZ/CrdqWSeXBmmARm6XbG0U3eXGqWQPz6kXUXYPeVqaXAvHUXZxhrczZq0WveX2YgD8UMkUfeWesRpqVzKGD5li0UPuUgRHGUipqWeeWKXk/RzwtbO0VQ+Vo+X4aV0qFw+WE8WXsUM+VJqX5tLc0WKXkzrzheV6JaqXmBqWqMUxXZ+qUJSVG2k8hReqVKexC+WJXafeXcsWw+WQRxRu5DsXlXa3gTQN7CeVOXZTFhiqXZaoe47jirmqXJqVi+XLqXU+W6C5ZXbKiJDMWY+XcqV88U0+XdQGp0WsaWo+XdqVGsUW+UdqX7qW4+Vm+UjeWNKGTqUweXlXYJnKOsUIeWk+VuqXu+VneWs+VesWg+WM2oO+WZ8X1uUA9aNuVNtFF2Yb8W3cXkzD7ri6qWc3aJ+VGSXJ+X5IyPeWYSFjbIveWYSHaSjveXP8V9zLSqX6XbvcYM7S5sWKRGMfBqSVkCD/arZ+XcWIICUqOCQ+UwCB0xip+VkCCN+UHuXN+U5spBqVt+Ub8WU0Um+Wx+WE8XsMUJ+Ut+X1lEckXi/lZ+XCME4+U5+WCBBM+XBPHi/lk3QU0V48UD+Xt+XDSUJ84L+WJ0V/CTQF6d+VdeUo0CR+WBq7R+UCvaF6K0MKsqX+tgH+XhsW4PYmfCp+WPun/WjCSWPuk/LilsWPumbmjjuWz4mXAhfeXUPbWCy/eXH3apQZyqU90Uv3HhWKaSXV8UQPFqe60XZH2yTk77+UO2R3eX8GBkKDIaXgBVn+VBqVQBXH+XG+W/3YQBX3lZaqVH+WgBXo+Vr0UF9gLL5s+VBJw67QsphT+WEPa1LCl2SL8W/3aQNDazbx8WwBWgBXq8W/3amJI0Q55SXUPbwbI6g58MV0BVfyIjzptIDb+VQwC7+VVlYVxCCrQXeULPZ3LpJ+W8BXcBVRsVr0X4ED/aRX+X4EAn9iQaULPalPDd0UCZy90Wp2nWiyF+W46nXrhv+XFqlkkCf+WyBWY6mcYG/+W/UUVxDNUCbuU+n6ZLrduXPcWDPaCBWNsVCZGJ2wK+WqBWmBX8aUdqmwlBmXYOkWk6nESrk+W46mZKgvuXL/AdqnpbbeMWMBUiBU1aT7eXJPZ8BUJMWsaUCBWwlCreWPPaiBWkcWPPbO9qtqX+0V6Y4vlTVSViZHQ8zxBXyBWw7La8UmBUhBVL+Xa6mGBWX0VPsVsBXnUW9+61rAj3I8BU6vZF6Qn+XFBUpSXGBX9eA7SHWeUGvbzei3+URlDeMwP+XgfYIyGKBWCvbguJ7B7TuXhvasLjqBUnsqdBVfDIg+X+4VByE8qUFBUlBUw+X+4WFBUHuUjvbjBU5kXW0VlBVY8VT0WpvYxgHXuXv0UGvYrSzQN6XsWtBXNBWRqWtBV4wgyaW3k7gfbfSEwBUeDAkyGHBV0OJPv7CaWZvaDBUKaWZvZTBUxqVjBUjBVaaWHvYaGC9F5tsW1rBJpTczYgMWEK7TRj3BUh+UJvZTBUweUrBWLBWfuXAvEAhXlGg9qXhvZTvCLeXe0XbBUnV6pBX7BUktrxBVHBXGox68WZvZvBVHqW1rCDBX7qXXBUlBUAcXDBUdSU9SWrvYYhWQ5IzBWnBVVXAZBWPvYneUY274cgn8WSeUZ4kwCWH+VFwQb8XGBU5cy4GjVBWskFui7vqUZ4m5YQyBU9BXa/avoS6eVH0U/WQl+XzuUZ4mzYrdBWA0UDopWOK3+UpfIr8V1+XABU9siK0VMhXyhVx+Va0Wlel0hXTBX6/ZW9Qb8WvuW14l8VKE8XCeWqhWKwxeBV70XMhUpZjjqVFcz3UUbTTO0Xa/ZqhUAcUmhVFeWPGBFkXWhWGhVHqWZFbPRTIhWkmQk+zxBX9UKc0WpBVUhWK0U/BWl4kn8WBaW5BVF0W9+6XGCcMUn+WkuARhU0hXUA7RhU9uUSA6KzjirA8qVb7ZKki3+UluKfUIP+XjuI+tjP+WLuJkMWl+U7/ZmwJihVT0WMvHohRphWCnrWMUQ+WTk7hhXmMXxhWyvEuXBwMVOeWVNFxhVCMVNhU1hXd+VYA5FSomMVaqVRhU1hXYaWyvHPnSU8Ua+U7/aJCD+MUj8WyvG60j1W7wBVTNE5MV+8XUA7RMXjqU9hXzMVBBWLhXLMVEcWkuDzhWYhUqCEzhW58XjhX8XiNqUIeXDhVPPy++V1qVZhXOMUjeWthVwMUBhXVhUpMVnqXMSUcBXb/ZIAkSeWyeW2zkg/w8BVzbFPhXGBVERKasU8qVtiGgsUchUMfGQsUQ8VoWDzhj8hVD0XTKCIsUtBXTKBaHBqSVoWBsYLaBVz0UDA64sWVhX9A5/pEKeVaqWPhWOeUqhXARVuWSWBWwRW6sU2BWrA4AdxLBXo56nRkGSQWqUUzlsLJuBUi4hCGFpOmkBVQhUYRWX0ULkUyGFERVAhW4yGkRVzW6zhUKGpkRU4npIwAhhVVSBycU9FY8TKoBVaSXgsUhOhvuhruXxzANRzN8VMPiRgXUBASiBGAaOYhOg6kMJz+XasWyw7SeQmqW2g61vra+WsaVlg48YQz8U6RWZbpYOQz8U7eWZbr9ejPBWqRW5dq0XZi6i1U6EtniRVJ3oMbhOg7Xaght7V8WCeFitBGhXC8W2RUUBVEhXrkFKejc3ZT+xmgVp2oFgqRqVlg7pOo6g71kUFmVcY6BsLE3rWqQVdBGYEfrqB0QbOUlI7e4j+EY6Q5aYE+roJRVKDAalw53biVamFnBABZRUfMZYd6C9D5RV/Xq5RWssIFRUKFkUcCaWUISmktEANwd7648B+SmysRJbp1DTzzmyzLeYB1RUXaGymgMgQ0TZnywdRWWlDkaIOxY9RV8ImNvg5ZSY7pMPh+Sk0cTqR6voTsQ41RW716evK82DjRVs0inqVMizRSluWqYabqzZEhzjRWjzprq4H3gNRUgCjX47V5hvJydRWe85NRUaWDzzlojJui7bqDTZTSIkidGzPaDRXXRWkeg3sX2Mb3RXSl57q67IjXRVurSGk6epb67bWFy8loG0Y7RWQugRIgIB6jASeSlYiKOY5Bc58cDvRVbRUec4WKDvRW0V6ik4BejPRVf0btRU9dbV1roNZFchXRV09BHEzkz7Orh+SnnRXkz7G7B8RXYUXGW6ND7ibghsUs+l+VwXeXkxWkxV3eUs+ll2zCSUs+knUJruXoKVJJ5f+UTUmCpBfeW1EHsVwqBUVEGHbxqSUVEGSVz9BWtD7t5DWeWtD4UxVCBWd667FzUxUI+VUxXw+X9uDC8XNQ5ixVBSWDQ7nmLiQ43uVAEFaexrBUukWzUGMtyWBW1EFh8S7BVC+k5wZC0UhkW0w4ugSwCUdUk7Mi60W6MXzU5vQ7CxXBRUkxWyxWmMWixVSxUPBWcw60+bg+VUaXCHFZ+DvDjqhVKDaSxXh+Vf8V8jb+xX5eVqxW2xUKzRghUVEEpjgXsVaxVivzhuBNSVJQ5cxXTeUOZAyDivsUTeW09lJtDRBW8w5M2j2hVH8UKxXUxWdSV5xUBxUbqW0xXtVDUeXpxVjqVW+VexXABAvQRDMVS+k6xW1xVJQ40Kg58VpaUJxWnFplxX+VoNLj28VyDYmMqmO7R8XdxWJxUW8WNxWZDTxxWBMoB+UR+U6N7A+w23Bl+gUeC40RTxX37CC9DUlBPqxEPBMI5DrJgFnzxWscWzxVrxUScWU46bxXN7ALxW7xWHfArxVHqR7xXBEVl8UCRUWpacrFmuy/PHe/YslD57Lij48vxsUkKbab2aOYBT9E7w5lYR4vENZRLw6SlDwq5NiqjUV3XmmrjMG4wU6qeAw6b9G7XipQWW/4T90QI0B3NYGH4YjyBPGBcK3oFJYqp7z83415aVH73JaAJXUtbJrEkpYxPGKUU4eDvxWJPFY3r+w54JUvxX7rj+w4VAIfxUPxVXw7+JSo3DXxXGUW4JXPxWCJiJoiEJX0JXBnQXZyYJU6AzyKF/xUmkjlGgmgpCJ7aH42JYVPEoJVemRxsCjSGOg6WeAh7QvPF8z6XxWjw5HDTgJXfxUjPEVvoYJVPxUD6gcJVLEUslBEJWEtQuWG3xXEUTw4AFUVSJXUvE5XAUWXHMH18ghF4kUVCI6I6b6JWmJUVCw60IhF4OX4wJWvHAfPFhhgfb75UggsKWG6aJXOJUt0AqJXf1FCJUOJXDE7/Y5WJXbqgCJWyJXRaqROAiJVCQARRWaw5RRUlCZWIlxRVDCZFRVpRUFJwU0FHFSxJXsiUxJV0ibRJVJJX+6aSWVME7FRU06aJJXJRWZJWHOX0073hW6I4zRUNEWcdB1cUsvyROBhJxRcVHRVE0A1xIVJWgaCe85taYNJWZpz/qjNJXKcVnCK8loBJyp+BDRUTRUXb4U3R0JwwvztTpWFAucVDJUANwN7BCvLjRWAxUXb6xxrfRXheo5ZQfmZjcVVZT9RXVJXNvB+SmtRUU74nOYacVQFQnAbtJUdRXSxzjJV0SAdJXCepYFz1JWJWDhJXjy7lew3ZjI95eWASYpzYjo94kiWPtn2twPtRJi5XJX3JVZJWqxF3JXOPCvJVfJVdHSazDRlAB2Rw96ODA7aSApUPJX+UBVRXj1FD8Gjw5UiZFHb6uzaJVi3knFZOuzPxVnVAy1a+JDKUWawDELa+JBEUVhiTcbj1cV+WQWvBjw5BJY1IA7qocgCcWSz5bz1GQJWKjjIi6aFD2JVAm71AT3I7KwI9kBkpUvI4yCREHiEpXUtYwlA6UUjG7+YQFcXPvzKJV4VqYpVbs7IpUuchjo5Rx5YJUIpV+5Y+SAgsgmZ4wpU0lZSpWjhiJtD0pWcpXipWQrTkpUgAX8pWRZC8lZCpUapXIPC8pWzKIX7Dk44wpYMpXSpVaG4Ar4nC41AxuUUKG5mi5/kqtdhWpWIpWrDCU4Lk45mpV4pXopXzk5KFZIpUapV0oZGUCExUsSXGW5n4A13KUxVnmkBpVkxVBpX3BW7uXBCBQdj0xXBCAGERfcXBCCSljjuXMhFhHgcxWliHwhWl+WBo7cipFhVwCVjJrbqixpVx5qBW6yhWONYixphpWPqX+pX3BVOeV5o7BpVBSWlpUpSXthUVpX3BV9hUuLmVpVoBWYNYUtydshj+UC1E22Et0AT8UH1Zb5ro8REBV1pV4hWBxVxo5XgwhxXv0V5o6z3wRxWQvakhXYeXppVlCIVSUppUBB4weXChE++j7hW7kVpo6ZybzpXgeqU4KF8UStzYhX3MVxo6FWKb+V8hHOXZFeVDpXChF61QRMW98XJFyBSUDSXMQBJpWNeXCY5QvALqX88Wq5qppXO8WaUqtdhdxXppULQIa9bxaULpUBaXoeVr1Y59L18ibpVGUQlSXBhWqm52PpbxVKo7nbbaFkji5KDDpiDUoTLxX1+7oUV8I7wZWPJVdBknbZoZUwZVYZWHxWscWwZXIZVHRZQZUnxX8iVnxV+B47XTSJViMaW1bp8Q/xUU7J3mU/eLMJVLSKbmUMZXKJUN7pBZHYpW/xWqJV6HEAJWJkkEkW+PRQKDIJWpEV2vmQJWY0B3NZLWFFUV/K6acLRZFY7BIJVgJXP+ntxBoJW8ZV6JYijZYJWcZUxbaxXqsZWfxUuY7qUVPPDEJW21YqZXsJVDHp9ZaMMAmpU0JUQxmxIXMJW+JV++7opVl4AbwB++4cZWurQXY4JqyUZXRpjSzaKjYcUXij4GJW+Y7CZUhJU6tRW96MMCFyieZUkUUmZUKpVxTY9EWEjaGZWOJVIkUaZW6ZUaJX/G4xZUfxXYbHqZVR1SRZVWZUhZXcJUyJXyZUiwJLMShJXRZGmUUOJW0bHRZFbUWM/CBJVZZXzoi+ZUKJXKZX6DjNUWeJW/16dAbUvG1AbJZXlZUNZUFUUyjZWhzyJVeZWeY75ZVBZUlbw+pXFJXsfZ3466NzXeURpXxSXPhVF46jZXPcVB460FgZ+UmZSQZSlsXoXnyrB5+UmxwRSWl+XYXleCqKBUW44tPiZpXgWlPejwRVft6Z4CqHD6BUgE7uap2eUY+WDZWjZVOeXoXntQiRqUHZVDZXuqVHflwtT2BU3uXYXlVYDmRWDkUvZWL5iH0V24hHfkJEQzqUbqXoXlSriwcXgcVXZVD1RQcULZWSSV+8VB47zEiseUdkVB44dBqXpXvZVpo6eSWzMXjZWDpX/ZUjZV4hV9xVTZXI5WAZXG47/8xa8WB+ULzw3pX1SXg5VdpVe+XMQDXZWE5UzIKghUu+XMQDekB3MVY5V05UrZWtMXm87YXkrzAap6jkXYXmlnjPpUgRFv5QGdjm+Vn4Dh7CjMWw5Vn4DfVII5UgRFpZr9SX4hXHZV3ZUs5ViqHXpCY5WnsUHZUvuCtSX/mlLRwteW3sVN45G5rjeWbkXYXke8bweW65WliFxDhJ8Vs5XlSW05XLZXgZX3MV9ZXnxUoHnhkopSW3cU/JyW8j8BVDRB3ZWjBWO5XTZXVBVDRC3siSBWCsCLZVARWCsD05XP+X7E7rZX5hWbJwlaAwRWbJyLMD9BU/JwlVhHZUx5Wu5W1hXx5UXZVYRUeHm+SXG+Xo5zoFB4aWWbQNE7+ew1pVq0WO5UJ5WmMXu5WeSVXBWp5XRuTnBVDRDQ5UwBXOE6xFTV5WPjYlSXeqW3k52NAJ5XmkXMmFnDFzBWJSUF5WjZUBhUu5XsSU8RVt5Wy5XAcXW5W9+6kk7Q+XPhWck5FKjO5VIGyyxXGBUEb7cqXIRWpDnPiLt0XS0XRkRE+X+5WJFxuqXChUhk6+twqBWwpwhHTbZXik7A+U+5XiRZx5Wj5Ws+Wz5XnzmyxWNhXG87y7C4RVn5WyxXnuWxDn3ZRPZXLBVUsGpVhvZXtDlfFT3uXwqHfZWwpxyRjZBV1qX35Wp0UfBV/5W3eW5qWL5VgFWIArNDlpEIQvBdxUT5VveVc8VYcXG84++U2aXD5UNx6Fp5dvpHFZ/+UCU6YFWSBX4U64FX2RVb8UCU6BYjItYs5LWwUVpIqRXZ0UcW7I3QaRWMU7TLTaRVWhV6U7SZL6RWMFWGuIFsVfbQUU6AKBIRWexWMU7lPw9ZbWRXtZweALwaUt8W8FUEFXvqU6mGWxrmxWiFWkOiik4ORWjk58FUIPZQCW8FW2nDu5ZesWCFVWMYFsWVxV0FXMFWIFV+R7vt42sVDpUCU4wETi5WdwV6MGnpWMBX4FUyFVEfpKFU4FVWFVw75AF7EFUSmCzsXq9HJgTnBVblD+yq4RUBwXPsaeFWRtgUcWN5VmJyxYYGaUFLS90V6U5TP4aXaRrJ0FVhFXWFUGFTaFUjyJIcV6U580DNxVtsVeFWeaX4hVoFXE/EihJ2FUiRXCLGe0zORURkXTU5ZFUiFU1hKXiqkFWKRU1hIs9Z0aXT540FUcFWsLFsskMFWpkUTuZxFVjhWtMr3WLGRVdMUd9q0KqVFU0wjyO5Jzqd8WZFXCFUyRVkLF8QpYFUCKRaLG5FV0eUtkUFFXwaXWxU5FU5JjS+XnuW1FUUxzJeVKMUkbD76T9m56eWrFXLLSKFUxFXULHeFW1xUkbChSCv8WTFU5yU5sWy8VjOYV+S6FVvU6MegZaWteWShL+XCNeX9FWQCU7FWPFW6XYbFXdFUVfYzFVkLEthEK+XpFWx8EqtnUhXj5U8FAAlUO5VAlUKhVaqU8FBlkVX+U8FDd8W3+VJVD98VARUd07jcDP+Ud04f8UtBU8tm6MQIlVRS6ShX/hUqtnR0g8qX/FVglWvUUElXKhW8wA0tmEqId5WKnkx+hd+V48UctkAlV9hUmnl0lXglXgRrshVYBUitnL/AOM5WhVJVAmLKUFXpqXElUAFWixn7f6r+VgCVklVBhVQFW204WNCjpXUnnMlWFr7f0VwlUdciXFVslXclWoFUUhWLi6i4ENhU2qWNUlxhUO5WalU1hXGBWNUnzhUL5Ul1BppTL5W3k4/04ZhVARV2M7OMVb5XqM7Zuy75WANDUvTfqUfAkXszR5UmDZ1YjVBVqlWnZVr0UelUduX/AkeOSCMVVqU6lVdhWvUX6lUZMXtpVeM4s6Va8V9sXOSWWM7mlWeeVg9nZhXOBUfAnqMWJlXUZC6ATczYalVRBgGMWuxXBM6/hT3lZDhXelUBeU5lVulVbBWplX2MXnBXVDZ7MWzsU2lV5hUS+XBM5/4rzFW/UWWlUyMVXBU/04iMWFlWWM5tlVhlV1lUJlXdpVEJxc4EdMXJqVg9m2lXk+W+lVbKRCeW0BWBlV4eVAijBM5GbBFeUfjBwr73Ka/0ydqU/057hVHqWtlU1MX/BXqM7UjgG5UMxkVlUEzCpBWllUTMWYhWulVMMXYeUl1C5lXZfbTlXnlURhWxLDAhUnlUzMXkeXhM7pDZllV7sV7lV1SWWaVg9nblVMeUdlUblXeRUlM6yw4UqB+BVGlXhMUKlVGlUbhWPlV9lV0OhQMW3lU7gAXJWyNHk3GCWVHRbhJqIVWJRWLiAIVXKWUKZDoVVQUWDmWkN4juQoVVUN54VUYVVCWXIVVEVVHRZYVXnKA4VV3hU25Ub5FV1B4UWXmXas5oHBdEX1qjGZVBUXrmVh0BuZWsVU0UWj+A3UEEETI755UajUVrx6mrhuWVBJYgKVQKCfmXYs5olhkkXRu6nEWQ7w3mVDWXqZxm+lpUVOWXas4nxj4779qLKZVpz7yUX8VVLEUIRbjUXhW5jG6I0RjmXsVVFRaaVUK763mXtEXh+Y9WWXmWvUFXbBZUVfEVIkWcVUPWXM8UIRZEUV0TD8AQ8VW26TlfCgWVos67rzRuR+uCnmW/FU/F6ds7MBw8BUGrAhVWsqVhVUb0Vu5XAuyO+rVBUGrB+Hh4FVgCReDpARU+SCq1LP+WzI52gH5hXQpB0GgwRXQpCgujR5XQpAEBxxVW0CZsMWvUXBVVRVWyeWzs5eOpwMWfFUwNlTjr/FY2qU+SCDBw8lU4c4DsTNlVEbR+ZxTSTZLjEaXRlU+SBU1iaxXs0WpVUhdCeFWgPCBoFuFVlqCZVW1lUwNnsihU+XBFVFs7VtRWxW/UWFVVkXRbBXlVUmMXrBVrVU+eX9sXLVUVhUdVWgZzcbDuwiueX60UwNkv+h0RWOhWbVVxXZMRUwNnFHQ0BXAhXYoDK5oMBV70X3VXoNIsBW8RXBRlEWEsWGXsZxAoGI5dv6IaWYxhN6TAkL/MUrInfVVYykORUhc7vHLJI4HAR3qU1F4Lb7QDxjpXt/rIXTjP59eU5C6rlQ75bakUe3YaeE/VUqyiwaVPVxIOhI1WzkU+64xRjwiRqxVN7rryS7P7Q1VlmYA1U+axg1VfVVU1XOBHKACOaHQ2xSECtxwQCXeaFM1X636P7qXNb1OGZghT8RKkWLrpJwzQ3517wdc7D5LDaA+cRA1UCj4y1RdFCnkjUza8Lr14hS1XqaW5MXUTLQ37Ujizc7XEWJEASPkcsW01XM1WI8R81XcTQA1UfDHC8Wk1Xq1WV3gkaWK1VyKS9YIk1Wy1Xq7BUTbI1WWgq8ZQ21UE1XbcqZRLQ373RQDc4Ayj9nAs1Wm1WEtSIgbQ37cxzPTbe1Urhy81UBkUo1WS1X53ma1VO1WjMBi1V/VW0+b21W+YyQIg+pX59k65alcxdRWuyWV87cj4p1X4qGy86/m7ceQoyVZ86Mi4SPypvTSYlZ1UF1VUCUopZ187GcmqRCkfFp1UymH24gH95TJbl1U11WDCyZ1Wl86sckfl5l1Vz1EozFhCVDDy8BgglklITByXx87Sb6Cp5bVJxyUAuhH84QgzfInt1UzFmdvwRdaT1X9FkrURAyWj1UTFk51WuyUfdg08GtwwGCWW1BYHETFn6DDwyX587Z87IpJECXOfgWBpz1WLRWUyVs4i+8ksvD9RW2CVGEioll9ISUNxhBDq84glm3qauCWVxAgll1PBhCUXPjXSxv1XD1UBGnD1Ikb5srS1iX/KBGdoXxaCp7tCZHdkD4i+8nveBPImeGCWxoglkmRhRIVp1XWE5bRXN1UB87r1U8dn+egjAB1FkDgK/CXt85T1Uh9JYqH11V2uGltiIiUHuqnkVkNDL1Uk0lG85BP4gl4Hnjl1WmNBwxXYCUQNWUb4BoKPKHd1UdYD4uHYNU+yW4NXUuEMNW0NV884KbYtIkP1XLYQ6b7z1VBCUtjjGjakk6n1WUNWl86SNUMol8NXwuGcNXZyWL1WeEnal7SNUB84W4JLCWENUa87HXwz1W1iRH84zjpSdaBwlH2Bh85tSgL1WIMAduEbJQANzsh551UmNXwqhJCVGIqpkUBC57RVn1V1KImNXQnoWfFZLyM8kSRTQNW9iDCNX2Al6hpJKFk3Qab4LowgD6f1UEaV3MGCNWkNVFHYRNU4NUlKaVxamb6YabsCVMNX+NWANVyLBdvo6b7P1W7olG87h9qQl4oNXN86WNUqCVpNUvICtOWRGV6j4M8H8kFX5qCkG6WC9kHkiVykEYZUPqxXnDAWADsKAsDyXq1NWbLBKDAY8EVNU7Jo7eA1NVdjbNNXRrCksCtNVNNXf85Ti5DNWQC79NWVRVHOV5Fkm87S5yINXaWytiVpUA98758XttbHCgyNWi87y2H6wmJSXsEUC84+ZxzNUq85j0l9ax1KIcNUzNUGNJ+NWa86HIkH4nLYRO85ZqQD2HeeQB86W85j0l3NVob4nNWJcwyNX686JiWLNV0NUe87XiXLw6zkWB86XImrNVfNUgWCEZyfNX8b7O84HKU31UmNW8KLqiVR87V4W3Ah90nIZlpSXkpFX1WslGp864WEJ2AuJwfw5+PFl85qtyP0lYtWAjam0Ct86zNVG870NS35yINVZ8zfImAtUa8FIbiN85UtW88G++R2KVPNX0tVEtX5NIj85loCJeix5yINWD86MJygtWg8EltLT850tXk8GznBFDavNV0NXrIWYtXcNWHW6X87EtWz85P+awqVMtWc85r86Hl6itU7W5PohTLbymQu7zk8Gs86HiXb3iPkUupEJZq0NJ/1WBVWpQkgMHqlUskWq2DhVXhsUWtUVVWTZWB86xVVxsWq2AJVXzZU22CkATveUBC5pVUbZVtC7QEDtBWSkU8C45VWA+UhZYOMjOtW5agrVUL5UCC6WtWjBXhtUVVWXZUBMEVVWt5XuC4RtU/5XkwmmtV6hWQIiBp5obo3hUo+WxtXzMWRMVKdHNVVMeVKdEetVg5VEtHdVWWhXT+UltXuMX7pWFtXDVW/sV5tVjVXu+VetWZVVe+VfOFndTVSU8C7rHKZxVxC4htUPlUOhWhX4ptW9eWh85RtVLhXM+XuZZFVXFtXJJSHVXKlXMSWJ1XbNaV5W8s4VIHDB7QcnXC4LtUMNbCwXztVqq4gllmNTgYF04yMACbtU2i4o34/oAq5C91Uki7Q363g6KIBv1V9hlHCSU2hP1U7/FQQimJlP1UIi4Kd47tVYb64c6k6i2wggNWvtUsd4WgRl1CRtm6BBZrCTBJ/9T9FlPrIEYGGfCgIC/tX3hzeYAI2GLtXV6m3/FQdWrtXJCUc1Vki4kb7pCV7oEoGAvVb/MHAdXDb5GPwuWEYdXTehzBIgNUM2wrFgAdVgdW4dWkd5lKFQuEodUEYGwaZjo5ztV7oEDoDodVDRB4dVzOnDF4wdW4s5qFC6JZr1U5LxcYG0yY4dXWE6n/H6JybVb/MH4qYu37oi4EdU/t6cQghbDOpVCdVAi7M36k1b/lCX7T0d7kdUQllwZgHwhnaaeMFv1Ws/FiIKYpWCp6XtVgumrtVsgz/tX0dWWNaCp6adXMdWD1WUdVoi7EbiJ5ZrtWCi4y3RhB4YdXMi7InQMdWrgxUfqw9ZC1a4lms/EdI4FB64ll9hmRAJSdU6dXys53ybqdUedVh/E5FCZEUklk7/ERFCfd7/MGITI4xZ1NGbFn7tVvpapNi/tUr5iIi6eIlKFai9GU/HPzqfSyXFlfFRp8DPzpydXP4U7IwDRXi8IDuF5oBA5YZDSopVDRBCRkFdXadUIdUm27BdW0dVVE60j5AdXMi6hvY2c42dVii54aGXNaddU3sXOi7/lBbtXX44qpyM8nGOYai5v3pQuGjUD6CC1dXN87b8RRTnTdW5dVH3QsQDZdWNdWmBADehfLr01YklmPtUgQ4ei4vZwHwjixaSQDgdW+dUX+68lZNdXEc48j6HdWBdXVqE9dWCfoOHAuVYddX1dXR+DokUOdXsi6mi4nFandXei4DxaMdUPC6iBjhdXVdUrFg4B5OrwXdVZrCmHw7b4+dWBdWdhC1Hy/tWYdXHVZLb4/4W3/Gr7xEpVfdVzxaT3hLEXPdVBi4SCKcdXQ9XZBqQ9Vg9XA9XLZXIYAXtXg9WhdrmSW9dU357XWBBHGsdW3dXfqG3xBAdWHC7bjl7/HvdUscAAr4DuFY9XdDGCNBYNVY9VIdz7kK09UPC7fdxM8GEdV8Q5aJTmMgTFmX/HRJ6YHBwNVZdUerk+XA3tVrdVC9W00AadWhdV89Vj1V/tVtRVc9U8GiE9XA9WcroE9UhdWfJiYcBTvyQNVXjI81ZK8oU9WftVLFZ95AM9U2vCS/G8JoS1pAdU1dV9Hxf5A89WZcV/qQkWCtdXsi5a9W+rZo9WP5Zq9WIUBA9Wq9WQpToZCu9WCi4Psa70QpdWRdXB9UB9U69VLdXdLzS9W49V+9U2uYa9VtRU/zwWHAK9W69W7kTa9W7dWIi6AzxPwiB9WP5ZZ9WbEAlNVYiWXJWCFzZ1oI0LZi71TAehqUVWicXF9VwiYYh5XKyhZbYTAfJVQ04PcHZRV4zili6z/YSBr26ioVVwYDN9U9I5fATao4IUUXU6N9WFi4D9WARhuj76ejy1D/JU9ZoV9WvJXs17T9WT9Xl9U9ca19WGqyhZbmXRD9WXJVCOjJtad9Udj5bUEd9XX9Y5la/m4N05+tDLtk1/ZnyUyxGz9XYBpL9UyKDJtal9Vd9VkdmdCGL9WvJVT9UP9X/JUzwDE3pfljao5MgrZ1qd9UdNWUckOLTJLq2j4cUr5CZ99U/9Wv9UlCZ99Xb9XV04T9W6DBX9Ul9WX9UL9V0ib6xAgDXwDXUEkz9X39XG6aV9WrIBON7NgCwp4KkGDfRqIbnjBaAAIOAb/aEj5sVzbjYl0DPC4pjRLdXx+BMuAUDW5rrbjbDdX9cnINrlk5VSQBcnU3JD1YmYjqj7tJndYT41Bxrygi7uDQMe7vfD3tUVcmmQDgHom1YuCxsDXMDU0DUuCznBKnjY8j4oi44MAVPbedXwi4OCwHlaCdXmJzQTiyn5VMxapUk9QiDWPK7PC68t5HFbkDVY8wqDWhfwbdUdZwaDX4nb7sIDtnuOqb+5iDVjtk2DWTIRqDXTRjmWE8DWmJk2clFwpUDXKJYeck9vaeDUnVb6DUyAj7dU2c6xm4ODXIt6cDX56RdAhTW76bDuDWYPb7pZ4Sx4xHODUMe73Jg+i7s8oRDUvDRHtVo8x0DX3vaXVYzckuDVphBCDVxj4mDWEtSopWxGkoRSDna+cU6DU3O7QEAoi4xDVnxbFDUfDRLdUqi47ck+DWVDXMADGtW5SG2eotuU2qVoS6dDWPUXdDVGBXoRXzah8eU/hVokpN7C3+XevJDDIP+W9nFtkVb5VJS7SkWQRVD3lLuWsxVqYAndh7ZW3k5zF6akWGlVzF5MkXixX8yHbDVmBV9DWCMW/UUHDUNVW9DWRdKzmjkRVTDUpBWDlVxS7XkVRlVLEWrS5OkW3BWrS7HkVXBWo/L7kXnBWzDV+kVTVVJS5dkWzsVTnFUeX+FX8yEbDW8+V+S6urqc+VlqVbDWGkXI2z3DXrDVRkXXDXRBr9kVThWXDV/ZXf0U3DVxm57sWo/KqgTjqXjDXCkVIcU79YceWcRXdDGgeVaFVqYCpvSnpXgcWkjV7DVy5XvZaSpxEeWnsWkjVckURBXtYARRqdtVYS6LUyrpUMxk4jVNkX/BWYjWftypBVojUbeW9tVTZaXBD3kX7pXPDWijXs8WrS7vDUYjW2mpkOTYjVE0r+06EjWjeTvlWMBX/DVoeUflWwjXpkUyjUzILjkWSjWQjV0jVEcWajWq5XCjV73oa5VVqU/DXrkXIhVJS5KYCmO5NqWo/I2Sw3O6a5WMyHSjW45XijUpBUl8UqlWfclRGhX5UPcWKo4+jXfMVPakGGSp+WyzG1nJRpVGUWwFUchWKzE1zwJpV8zH1xXChVczHNajcxU94ANqgH5UqLaS/CrDXStbPbRHZVpjVBjU7DU5jUuxXlpVpXbUSJHVVB8VBc6lxXkaWBjUuxXQjWuNZ+jXgjUcsVPamhjW6xVFjUZxWRSWKzFj4TReVKkXJmkTbpVpXuEmb5Uy+WZjW69ppeU/1bejUUlW2zG+ozjlUEaWVjXh+WmzIGNZljXO+WzBYghH56QVxW45VtjVznTzpXj/nd75LpXJjVwto7lWMo7JjWfEpNSV4y7n9JnVVFHZ4y59MiolYukV4y65jWcIF/uX5jXTjUa+VpjXnjXOaUH1Y0M4teVnpX7jW/EpS8XbjVkuIPpUbjUbeWzqWrjU1xVaFWKzHFjUKlUhjWlxVltUH1a1jUIB7CeVtDVAk6bnYEJJFBU4s7waUO5XAUmk8UVBUmuo/sWGlUSK55oAmlXn0nos608VLDUQK5M2TP+UQK7tOq75Ua0HF+IwRWbnZi7zR5WbnZNVRDBV6JTwaUVBVMTWQBUITVoaWA0XsTXwaXthXX0lX7BYaVaqVoTX8TWvUU4TWn+6n0VIPYSK5OyB4BUyK7h1KThWexViMkf3Dh8VOjWMVmITVAVUQK5ksrflXETXF8WteWSV6Pmj/jVBBUw65OaU4hUbMJaTVCjXAK434hj1bnhVkTUYcX/BWzMkZ2wIhVAyY3FVKTX0TVRaWmTW8TUqTVghVuTUWaX6TVMkCpaUvBUOTVvjUgMVwVXIe7sUXOySA8YbdZEbTzN7wh68bCqb6uq7JPpkq4xTWRTXIh4uEWAgCYjX/9Tti7Q94AcogcRhTXIUWNoZBG7v9UAUW5TWeq5xTUwUWZTV5TU3JXBADcpaMZr5Ehr9WVK6VTVpTXlTUawClTVJCQ1TXBTVKm7sCTwUUAJxZTVRTUDNUVTVtTVmcTVTWFVGvICxTUYDVEq6y2VdTVp1bQ95jTWfsSRIQtTUsKDWDGOq5xTX3dYJTVFTUjTWKqHOAXsIUoGHO8G4oUSblKq4hTWuq5Zi7Kq5TTWeq4HTXzTWuq7QEDOq7LTU1LlPLEEYAiABtRYobBrgDQgBDmVl8USH4iJZokr5G6CiTCCBxEH5G69iChFymJbkkDSxY/TWfTVTDWOY6rsROlzREE1cVx1U/2B/TVRCVvznItymJbt/QIxb9za/oDwzW2CIhdxwzX2jU2Y43SnIzXgzVLFY2lKhgB/TWgiWeNzJ8h/TWozUfTXlABfTVLdVkzWy7ZzF6tcW2OHYzV5G5LdWgzVGlzrDXzsoldzoZDkzXcpZOcWAzUczWI1ZjlZMzXFlzcpYJRmczYjICmJbHKzTY7PrCalyizUwzUJsSePGCzXDG6qzb0zV19LSxZUzVSzU2Y5UzVwTU65Y7sKs+WBkgIMWL+TazUQsrAa5h+WaqVw5jdq4Vr54aWllnB5aPNLgXh3Ppnc7ChRr5UesZ8WH/yhk+W8BFW94bq7i+U+yrdO5IqgA+UOzV8sn3KwaVg2zUcpUiRQ8+UWzXdq6rKjGzVcU64lxj5U6zXcMV6zUP5VDxamzVj5WNYi6zVDBL6+VLOK+MVqhTOzU5FgRc4NMJOqX8daKUWhlxq+UaH44dVOzV9jWYkg7MU4J5Qqj/1a2zUPgZG+VRmwWsnuxx/+iAtaOzW3pIlqXb/DVzWWxwvuUNXahzVj5VyCbga5Apys+UZVndq6mKAexVJzWGzXwBK60XqVjM8VjFxt2wE5V3DYJq4XNLzjWT/LpzVGzUJMVPFbTzWQFVdlmmzVY+VRXqL5ZehRu+UVKQmFZnyie+XPSwCAWm5w+JRwgbFzUZzVjxWFMLDq7D1qyxXRBiSsn9zXh+UcO4PMXTtX2LmmY7uLy8yVTJbWa6fzUINUKMFLx6/bauyVDKgNpaeQ7XhR5omZa7as62npKNWTa7NQ5SVpF1WbUF+GyI7YopbnUEGxxHSVIOzWa6dJS0pnILU7G51naCDaYqDla4mDao7aMNU1a6wM632WcBCk+7TRgyyXRa7b+kSpIs6HYLVzEVu2XkLXX+mDXgqyVo0KGRZa1Is4Gb1WsyEZRYcLVALX0EmGRaALXyKkaCY6RaSViFNU07qmeFURaa9aUyVzyETpAF2UOBD18FWD7FyUqYwMFEpRh4LXwdp5l6kLXdyXJIpmRbB8zdyWfHoFBnbIBqLVozwrCGKLWGIV4tTPEX8wh/zXVUGc8CRyXoLU0LUlqDoNWG7LPG6ILXgLX/zUSUbQ7b0LXeRbufkVdnaLXeRYsLUoyUQLUzRahDrxfEwLWA6LayXd1UmLWkQrC8H4LUkLXoorhLXULXaZUuLXwLXnUFxLXooUua5Za66ShiLXpLXuZGZLUj1UQLUX14eyV2LVea7h/TxLU0oiTY4b4jzCXfzUOZH2nLCCUJLX5a60LV/SVlLUGZGRyVSQjH15USCMLVcLVsUn44BJyXm8wNpbNLVpyVH1WfCGUMBSLW2CW21nG0Hc2V4yDxl6xa6cyW+NXwrH77jdyXRqhZa4oR6hNWDILMZWHLLayUHuo0OBL16n2UPZHdMFz17VyVlWkcrHzLWMyXb5SirE5upKLV1LWUMAN7bN1Wta7dLWjyWnLWGtnVoGTyWF9WyNEA5SzyXXwAukGCrj7dLN7iZkG+jALbZvLV/a4fLUzxWI3KArXrcFKDASK6WkHzISfLUArV9NVgrX1NUQrVo65QrXArWporjNVwrXgpVTNU2a40KXeeTWa5aa65DavNUpLUWa54tV1LU/Dbza4xTJdUH6a6CDb4rVjG64rV2KWHNX6MGOa5GKWEqRzLWWMhIFzZLXea6ZihQKXErUBa54rXYrVjG7crW0rWXLVlFIJKUJLXuZEsDw6tUJa7f1FJa4StWTa5pa6MjZUrVZa5irW+iVzyFUSDRNxIFwyrUla7gyAmiXla7WrbZdq5iX5MHCMCPIieFyLNWta5Na4YqW8rWxw6PjKEqU9fxbLWDraUUIK5yXLUDwQ8ny7NXSME7ZEja6rNWta7Da4YqXGrWpa7Ta5uKXmrXoI6krXyrUAI7HyRriWXLWra6Y2HerVea6ba7F7burUna7Pa4MpzmrUHa51a4jKWXLWna5qrUYrGXa4xKX+rF3a5FZwPIQlZb0TUza4Dopva6ejWE65jSoklXvMV1EWL+U0hUjDaqeyelWd64wTSmhUL5U1rXIQpfcU3M6T+VgaUNRZijgcxV765qXrcxV7iBbxh8xWyD6UZRMxUmuBURAvqVqD5VrW1hUjDYEdjIaU1rVvFa6XYRkWVrVd+X0sU1JkFhbOBUTDZdrV2SXfMUNRbq2T2qXOSUTDa7rWFlUbrUF+X2xW8LqW0WAjUjDbqOTGxVKkWJEU+3BBqUjDY86iLVVKMV7iDWmK6xUTrUb8VOxXvrVbVX7rUvrVjrXkaWvYEoCW1pVLrWesUs5KZ64ygSr+WhaU7rVkoK5SUEaVQbWs0UFxWij620UrjWrrWW0UjeWXrW9rVJxX1zR3rWG8UAbVmjWrkW/rWZ0WmTXTrXzrWhBXEbWL+Wy8UEbWPVXyxXw4EoCUh+VBTVzTWX64Ob4spZ/nD58TqWUyVC5VGMbUBqTNoGMbWy6YLOUsbUkcSyWUmwD8bWeq5sbUVGXnJ7CbXZjwYh6/PHE1RcbWFJVoC79ZWxxxIO4D6h0P5I1bY36yuIIxZN8YHdVKbVyqUXLDcUXxLTKbW6bWs376bU6bUbmVDJa2aABB4OgjDB5tbCjhieNwVEWTgV8SWpMo8ZZfHAVJgabXjmXfJa8uC0pW2bV81b3Xg5pWWbW7UVGaGlzI8Nwy1ZqbWBbWGbWfOWS66ghXPrDIi5T+gBB7TDCZEUW4DKUWQzb01YJbWb2ZTtDIWUxbUdW4B9wxUURbXDm4WrBWbWXFp8SVbzaPd6HdpvNZFbUqJYebXbpV5bX+bU6ZWSlao0ZA96xPzKbVlbVJg6qm5OWrQZUKZCaOJtbVCWWtbUkZW6ZClI7YZU+EUdbX9bXTRaDbV4ZU9TVxiAjbWEZW9bVsF6jbWTNVFJXUVWwbaBM5XxWL2JgFaVKnaJVKZX3EUGFK6ZW85i0xYTpBEJUY2K2xarbXwq7uy6lWUsRgEpUWEXGg6kLWOJCaPHBZVlnwiZVNaifYDwBm+DbCJWEPydgoiBmwfxwo69pbGZUQuBoJXnbXJBlImgGpXHbXiZxJD7PxX7bVyJbA7XKJXbbWxWUR2qqZVZqAEkVp2oZZVUNCqi67bWWZXojGyRbqJX9Xp1WVYFKaZXqbEYRaY+jMJU47XwBnYqBspVOzonbWowRIJUaBCyz7UZCCNDjHC/PFuSmybZ47WaZX9SwlZbg7WxZU7HxsFY2lUw7WL0Q9G7w7XUJWeF5Q7WVXFrUCL5I6XaPbU9/AOJU6bHhbbxM4DgglF415awM6WXD9G7ODXDWWLbWUZWeuwiLVrAbyJVc7Wq7Xo7UG5qURZY7Ws7VM7XX+lq7WeZXe/YmEVLbWjDBfbVuzzGJVhZVwkWS7UtZWMJWELUuJUMJWTEU0Ck5ZVW7V/bVEMgmZ5+ZXm7X/bUfxX9HY6LVEPp67X7rig2VUVXUx6kGl2RU0hWRm4rFpJ+UR7WsYpN+UmcwDObWeWRm434J4TWEW5NHCA+WlcyMIRfeWpm7ICQqBU0GlI6oV+WZm7cWj9BWem6BHBHZXF7Ux7U7DVl7Vh7WVVWV7XCRVCMU17VmkXz+Wh7XCRV9hXR7VV7Ut7WJm4hvaslWJ7Xn3AclXT+WQ+CBkgtVWRp5abpeRWmTWt7VeRVP0Ull4rkXyRXUjXbm5etKzzVJaUp7XqRVaFWpm4Z7UFtWtczS0DC5XwF7F7U9GwmFUX6kl7UKlX17UJMX/ZVN7WrhWDtWZm7264u+WZm477Um5Xr7WtbhttWlczZ7X37V0bn8BTa8Ur7X6LIRBWpm4fryhBWf7Xyky4cXtl6ILQvmgrqWpm5QVRHFXvZUP7UzSIBMX0bXqhGjoEyEZPW59qAJgadACazDG85DoGIHWAsAwHW5/qzTXqhHwHWELqoHWe1HYHX5Ca4HW39WfMD4HV0iaEHWz8k844lCaEHWz4AQpUiu40C56vg9iUbdXytEMQ5CBEcpWBDk6WWFsUZdVIqjsHUp6afdWp7n5pVAdpEtYddGA1aE1iVWU+855uFXjYVEW2Ekv2iAK7kjg6b5eyh4aXsDiCYW4pz+SyuE6Qi5gb6+fwb3Y6KRYb5H8BYwRts64i5gb57WX8kUYw46b5kwmT0WcHV/WVv+6I9V0K7K+VJNRVKVsHXKbV20WsHVcHXKbXVPyfYBO85ZWUvx7w9wqg4GHXcHUdpAwtbqHUZ6y3pYRc7KHXlWWcdaiHW4pzVWUjr7kjjuHWGHUjXwRWU6b4eHUHkWWcAxHXsHX3JjTJYz4WxHVpHUWxYBHXE5VxG6e5YhHWp7xdXpqHX3LyfpUrkXUpYlrVVlZv0725U2qVJ3rJ5WPUW1HXlBVaqXQBAl5UFpVs27dejJ7Xy244AbchWA0X7QErZVb5VRpbY775hWE9ZUByOlWb+6OhKSBX+FC6SXVBVVHV1rVs26GjiQBXP7qg5VXBUzHXI+X3ZiXxnWnIv5VIB7/xCBbXp5WfxlZ9RfZXXA7y26GlKmaXy0UNHWp0VtsV1fwxbjAMV70W9HWW5UflVAsbW9TPjXO27buU05VijW3HWQhWOhWXHVm5U7hW925VSXIhW/y6CEL/HUp9l4bX+0WTHWZnidqUrHWhBW/xndSUL7W/xlTHXjqXIjBURiQHUVHW724AD7lrU7U4EfCK0XXqUA7CElXEsVe4CQlUixUWLYz0hfcXuwrylVgaVOpU+hXxjV3T7j8VUnVttgYlXknVJ/wL8WRjWJtB4lVNrWJtAAlW7uXsnVYnUqhW3WAAlWfFW8nWK0XZ5WqO66eHS+Xd+XCnVIlVbrXvMUKG4r3Q9VWo9XSnUX8VDsWWwoSnXBRWGpW+0XCaWWwqolVBSWoq7iwpanUIEB/satjUsnUyhULFUvgqWXB1jVAzmHeRd+W+eWGnW1+VCnUvgqZQgTzV48UmnWilWhaVcnVClUfBVOnUWhVilVH27y8qr+UT7XenULkV/7WGF497RknVnFW3lCehXInXB7XGW6MpyXpJkxV3ybpBXVrVxnX9DVA1UxeL9uWtHVU2JQSRruU5FBx4JgaVi2IKBVppV7gKGpj5nWATjJVBaeUrWJNPpfcWMpw7twixXRnXxnVTrU1nXduXlpUB5HkOzrrVigJa+jE+VEtaJnXfrWo9WdnX3lY8aWtnW+BXBRVNnWgeUXrXfCZxBViaWmjhRKTjnUgbBXDX9jWcvnhc5DjVznVLvKjjVU2I5kQW8X1nWMRW3RwRvnhVS3VUzvnJsSbQS1xX1xxOBWvVWgMWRnXE/Gol5wBXPhWF9LtZSUxWcqYXnW7uVFqZnbgixV1DJJRJruWDaCbnAJpUGu7iIKKBXIDJd4LcxUHGCoLJ8xUFjlHMqvnWDOgHjZNrXnnXCRX3nW3krCRXlpW3nW17V5MVwXV9+X/MUPnXyRViTWm1ke8KRlUz9T7rVvnW4BWeeXIDJfnV0aUnu4GUKEXWvtnuc7kaUepq1AK9lWVu74oKptUEaUQXVmnXUXWUXUheVFOBG7qtjVEXU7cxBSUGu6/nX3rUGu42ggGxWqXEEXXMXXvJrK+VOxWDaCiijq+XqaWfnU6qxSTWqXF8XWSnVEtZcXUEIAz8WOnVumkdH5EbX0XWXVWbnXNDLgB7EeUhu4cerMBUDSUHGDgbiMTY/CQazVQ1nrgVmtXvMXjWHRtX0sXWXWlVXEsXDVJN0VPnUk4QQsJfcULWHJVVgaVC1IlCocxU1hqTVVAaVje6Z+SpjV6tIz0WvnVr7m7VVABWJxYWXWzHUWtIH0WNsX4IU1VURkV2XVmkW2XV5TxjVXp5W2e7eXXyXWOe4+ajK+XVjVje45XUDVVCXGafbtVXGnWLBlpXWznW2e4j0U8XXyiX7lW1lUWtLGryC+WDu5hXWdzWHkVRXW9nUukXce5xtW+eW+5AL0XkXXDawTMXwBXxXUTjWFu5JXX1V7TlU61JOXWlqUcsXDVK/YAnjWOe7BaivsUIXVluCVtWhaWwLHyYC7jVFXWY8j7lVobXlhmTtUW8U9XUrVUzpWdXUpMUzjXFhmxXUwVUhu7NXVleUFxb9XVvjU7eXWTGttVS8VrXVHMV/lX5XUmHgw5XC8W5hqqOiwcXUsUzXUw5hgTWOXX2tWQTU3XUWCzDXUieWbbYERAtmWiWXYeAlAxQ3WibXgTDvSCQ3UKWUoZVVinYVWYHVvraw3X4VUmDCY3WkVVEHUWeA43VqWUeEVI3W43XUHVkZXLoEhmRpWWnmV++4fmXTmV+gA5LWMWXKVUyjYM3VBDBCZUvEVsVVvmUyjbbmXEUWfWU13RWVXMVXtEWzjhJUX0VXeQD1EUVWXUZX+ghCUX83U8+66mEgWW1WXS3VJzFDEVw7621beQA03Us3XQrEU3V0WUvYhcd4a3X5WUVUEZLWsWVokVOZVHtjzUVJoxrLU9HgcgAfWUbB7E8Tm9TAkWQkWC3XvWU/WV1ZUxsowkX/EWc3VzdpOVWW+5s3W63XIWVM3XpEVPEVIN7u3W3EUiVW83VlEWAWW2+78PBJUUnEW3oGtuQtEXeVXU3WxEVsWWw47W3V4WX4kXa3VGk5TWX+3VvY6+Ugm3XIWVvY5gkUe3Xx3XbUU3WV++6oWW23XlQBmXXb/ZyHxZFUO5V7JrV3U1HVZSxZFXGBVB+pOFWGlUG7wVFX/hUG7yLSwP+UFil7FX9HUhOhNFX+XXb+6tFVARWP7xQsrR5VhZY9FURXWgB43OKzHU5inDFUTBW13XcTWMBWL3UUlW9ilrFXERWUB57qwiXXrBU93WIcXLHUBkqAfiGqWmHyozieHU9HU0AG0aVTVVaAHWLRH3V3TAfFVVqVV3VYaU73VPbxZFU6+UVinje4f5Wrxk4VRCaUxSXhZ4P3X8lW26F/3Wb7W/3XP3Xh8V+nW1inz3WMIE3uWAB4VFUz7WAB5d3WgVWt7wNhFTtVI/ZscUo7pL9X8cVMnqrTX0cVCcVWfAuNFCcVLDT/JUYPVf3w/JU4PVeiiEPWkPU39WccVYh64PWnxVzbUdrn3oiwWh6HZjcUmdCmmh5U6BcXJcUnhpGva5vDNcUDoBFcWEzY8PWxuDeY78PWzgDJcUZcWpU7MPWds4rcUY2JrJXEpXLDTITZGej1cXSEhtRXuy5IdCKPUTcWQPxzcWyPWszV4ATU4HEpVSPUtmRrcWmOwwzVc7QCPW7+gkXbcPXZcVmPX7RWQQTxcViPWqHbbcXPcKTNSQPXWcV6PXFG4DCpXRCKPVyPXrQ4ucVaPVjlaJkkvuCKPX6PWtCQdcWds6RYI9ZZukhDcWmOzwm6v1aBcUMpVJhi38XsPUokBePVBvp1cXmoB6+TGRUYzhVcVfVrWqWpPUtcXPY7CPXb1GcPWrzWU3z1cX2WJYY5W0RQJxpPU4WSwnp5SwV3UEh7ke5X5UGzWRh4KsA40VNPWJh4tPVZPYmzWJh7IlIyH6yz6Jh7HEb8kXxzXsh6j4jchVxRnch4PGr2W7QT7ch4axgykVTPUuRbezXYHp8WHhoTZ2prW5DPX8h7BzXuxbGDYNPXhzUMtZz1D6zVg9zU0kiNBjqVgVgjc7ygkdqVZzWUz5fMGyxWDzXtPWs+W9zWRh49PVBu6VcKRh517w6MVrPU6Uk1xUL7p37FKWznzVfPXP7GexhiqUUTYsjbbPXCna/DqQKkdPVm3YCpm3PXPzVdzXQvWp0W5lmGh7eXwWTVzzX/PUTPVjpYIvXDPUQsiwcVrzX3ymbjU7JoJDaaUnXzVOC7ch7kfRzeXPPXTPV+qUGzY4dXhoQ/fCLz7i6wVh7bAhmjXkvXrPUFqWUoaL5Z7PXTjXbo4cvWp0U4vXzwSsvWMzynPWboQlqXFKU4mB1PVM040mwXnUO5VklCSvWNVVmTx3nVaqUvqCX+VxVUbqQFXbYFVF964XVLDVXR7SXVZVUk8U7eg6vXDn6QqKOlUikA5zoFVVWJWABWVsX/xzhYSz3USvUwXVYRXSvXwXXy0X2vVIXUN0WKvWPnVdlV2FxQTD4+XbVUecDqRWDlVavWAHW7HUikARdq48X20UikAVSzplWPUUikAPqJUXWWvXQBXuvU2vUMXWWvXRvVXBVhvWsXVuFUT2EcXVTVWZGyv+UwBUJWDHCKGqX+vWAvVVqUJWBz9iFXV9R6lvXY+VT97rdEBvXZlV2R75vVxlXZvVKXUjlV2R5P+WBnXlvXDnorqV2R6BKC77VuVy4XWzhUZ6DEIjflUvqCevVAVWuvXT7XS5XyFxxvWwPVOvUDtXmZ74fE5xVQhXDvUS+xHqUDvVkxTIhXqvVL7X1SVdvU3YipBUlvUdvWYhWFvW/pVEcWHvVtvV1vWEYigVWFOnaySjvVFwTdiTxFUZvUqjVPVW/Czuc4kjVRvUbL4UjUJvVH7Xf0UfvVQnWvvX6R6LvVPvUgnVHR5/kw65UMxntGz72bxBWXvUS0C7vXVTUv7UHvXVvUM5UrMVivUXy5WCb+jUV0UG+yKxUxhXofUuxUVBWBhDnPWtHVXYWMxV1BXmXSqnJARXh+xxjWD3Xix4DxVb5UrYVxxWOlU0c4CxWSBVFex2xXYTUofWz3VFewYfWVVUllkM/i4RXsfUuxWP5VXYXMfX82zLBXix5c4mJlUifXVGoHHXDFxYfX3zWgbVnYWKxX95Vux7t8hHpUnnVUkXzbVH062dC1nXalXEWCafUalXafVJnUN0VabZtnXulUL8gcK7/hUrUnZnVLDV80RvzTP+V80TTFktBVsMSilkWlXzXnlnVmfXLBDpkWGlX6+m1nV6lUafUNnVYRUZrb9nAllU+fX+lVrHVgJ6MlibHXq9lyqz7nW7HVsMQIlmSfUG9nxmDjkWuTVabYxnWQPXLBWGfUDnWwPVabZWlnXXXCJ48lSVeUflVWfV5nWzhVsMQ4GxAPUlM48+QmorjqXF0RVnWdvWefW6jUbqWNx4Ukqn7Vb8FufXGjXCJ780aAfV3L6wsa64bxBW2fWFnWblXK+HnDXnhWFfXujWujUWbbuSRQnXjfXojUK8U69nWfWgVV80TAoSgHV73GVI4AZVgCUJ1XvzWZZa/IiWcWwpriG6jYa25bLkGDK4ztisEpG1Y7fX74FSQ5G1bEmJjd5PHSI6wZzxzDTZJZGXRAMqWcXLnCkG4PfUJ9QdMEhI7sQonMQO1brSDH4FsmTrnCu1b02pm35mkp+9U/DRbxZbfVe1YlT4ntRvfV1RSVT66vRa64AsapI7gXRvNYw/WHfV38gnfUUxwF4FLo5wJhFzyw/V/fWSlZVayZJ4mPaZ9UfCGAdaqnDQ/Wltj4VFk/U1cUKNxudHmcQIQqWcUv0iY/XOUjffXncoX0E7aTHfUQ/V8DZI/W25YI/XHiUwPBIZYHfXzJ6lkgH/A4/UBlHcvA4io4sEJJ7i/VAY6C/U0+GJ0rEnUo/VC/VXsiWcWg/XMVEXwwgZaK/X10F9iJqxay/Wl0FToRv5a6/UvsBa64E/WtT6dxzI0W3fXbw6yNzTgwQOC9T7y/UDcUuui0/Vm/Wy0VPihjT62r43pbVeRplHVmVAY68/XQdbq/VqxY+/WG4EBnhfRaG/UUyDO64h/VKv4sFYe/UX0Gh/Ua/U/fX9tYm1LOeYM/UYGhqCXtm7QxaPxKwm6OP7QKKK4GlJ75Ejw/XszbD+F+VTdcWFTF+BG+InO/WlTHaPG5/Xu/WC5HQdb10ZepbeNXl+Gp/Vm9WHUEovEpobSxaa/UL+Hd+BO9VVywLPG7I6WcWNUqG4FGDTmHaG/UW5AgkDbfUY/V8+FYlAvRay/U1CXa/VT/XN/WeVGt/Xo/WVT7Aw6WO4m/VmVFo/UW/XaolfRRe9UU/WlPHddJM3bp/XoVGN/WWcXMDqrxYd+DXPCWcVqrjaPGthrI/XV/UVCXAsCi1ZiUFC4EwHBixbt/VYZrO65v/WIaD5xzbfX3iA8VG8Q59/V3qA8VGeTLffVX/VDT71KyfAjMryhSAmPHXfWP/V7qx9+EsMKB97gDr4VHCryUo4XfV3fUCVG7Xya1aOUHr/Wz/VL/UBlF72DQIKi/XsPHRsaX/Uk+r4+GD/XffWNUrkA3//VSPHCRbCcWlvBj/WVT7Ztoh45v/Xhdo8/VP/XZBoX/WtryAA39BrtgK0+HMm43ImxQhLFbT/VhZaEA1uTydT4cZKB95r/XQdbmuDf/VEA2vIkSRDoNaG/X+RBvNbSA21BHz7j4/Uk/U84E1N4H/W7/UK4E6A1p/U0pH/CW94Bk9zZ/VjT5F7xVzyMA0JJ4GA1N/U7fWlT62/zDxaG/XukB8A2a/XNlFGczQxaG/VyJgJCRWA2ZKkRGUvLWfT4HAToSQBGwEcCBA08CTw3UWLDxIDQ9oBySgz6hA0CbVYPWGw7GTnRA3XJ4rOpJA2C9C0+GC5ROs5wcD1VCPJ69I4Z1DpA05A2ZA1lNzFLJ+t6rTUhEUHIA5T72NKNoDojxOxaRCXtXaubXjWU1+F8yCIi6abWRU7RtAnUySlZ1wG21bRtDTMi4zVz9yAFbXyFPjKubVtEUN/V/4RfRaObUFPGLyzFcxDA1U3Vu+H7+hDA0VEX9+GW3ieNz/EXe+EUA6dA19+GVA3NA3xEV5+FO1hVA1hbWG4EJiCIi5NbVePFNA21bX5JLuXAHA2nA2IzVj8StA0DwR1A2IvG3A0m7Q0e43WyjUUDA1wFY4cTUtbit73Ti25ZRbUUkUonWS46cp45eXh7VBp5Ag1jZUgg0fhX9+VWjHBeWtHVKp5qeUchVap4fQputUELiusXChVGp4GeWetVhyRJPDfqWYp70B4ZjVJp5lqKl7WAg0Qg3D+VEg2YRWklVKp6gg3xtUUg1PhV17X9Jw3AAiXUOkVap70g1lvVGp5JeWWBVGp6zeWRSVog1TeWi+Uy+ASApSFWYp4pLpPrX7ZWcp7teUKaWCg2gg2mMUSg1PhWv3X4g1ig08FWCg0UzzvBW5kVap78Nq1tWkg0bnVEnAI9HwqFbW4XXVJp6G+wcRWvXU4g3G0bW06sBVg2V7pm5MRH7CBTq/3E3H6O6hg5keZ64Zm/MG8b6l1CCZnKlBVlTOg2FrgonZkqxJZ7mrlxZlbxGUhj9G4mrntOA3H6MEizG5AeqUZn+eCAJyo/JBZ5iZmIFLRg2LkifH5rCQDw7hg0RH5R1RLbitzkXFJ7xGXiomZ6+g1NZlOg2Qo6ETkA8FeZnnp4juqug3AJVO5ZgS4CZ6An53fX2g2wbgXuWrrHFY5VoClAy2g3jXhYJJKSo3H5QygmZ6ZuBjRIhg0k+r2g2bb48Ha7xKn6g6SUJg0SlBH4gI7BUmo9g1jg3J/X2g083yRHbRkR/p6XmrNg0SlDSqIBZ6DBlFg1mNYULS0DpkZ5jg1xg0A0Sc8xDH5BvDubAbMqLp7KlBwiz7PGhzwHp5bxF3qD2g0HGQ+nbeg1fp7OTA7g0gbGcZ7rg1eg35g32g2aBCvA4rg3VURfp4bICSpS2g0Y/XHp4xbhTzUhK5xg3/g1S8EhK4zg2/0ajg3vra/g3Hp5zg2OZk93BOZ4q0h1nHTg3eZ7SUIbg0OOyNoDdA6EZ5ug1AQ24Q2yWELg1OZ53cz0GCAQ2IZ5UB503W7g3nEirp5kQ3oQ1bg2BQWrxHEQ0BZ5bp6Dg3IQ0sQ27rxW8H0Q1nG4hjAakKHg2A/X/p46uKZZ74Q0UQ3WZ7DDbcK41g3KhIRdwDHbCrxrnBWZ5mZ7iQ3+0jnp6yZ5aH5KQ3pZ4v8ymXBZg0Vg2WNpMQ1mOBsIRqKCnBxjH6FHxqZ4EEQxnFQQ3eZ73oBTg2ROl6Z5r1pWQ1/Snk3A7QVmQ2Wg0mZ70z60ZkPg3uZ56+zpZkNg2Qo6KaGaQ0iQ3qQ03whaH7uQ2nEbcxwdg03g3d+Kj4gyQ2ht77PHuvoWoA3H44QLOOCBzluKBjH5/qivp6CvAdACfH7klr6Z4BdzmH4nr76Q3qZ6NH4mQU3FAhQ3n4A6ZkEQ0qQ39F4vg2ATC6SpOQ0fg3vuIMoigZnug3NwC7eIq1hRjZqQ3VQ13CQpgKfH4tmY9Z4p8ChQ1+ZlJg3uZ45Q3JZmNvhDIj1Q2AeCNQ1AQ1muIEdbpZnMQ0egB9OD0GCajZzQ29Q0GZ5BHFVQ3NQ0jOCLQ0FZnBFxyWIMohlQ07Q10CFxQ2An7Zg09Z4Ki6lQ3Vg1yQ1cLLIxKZQ1/96kWKtQ1iZkzg1LGDeXwXH7CkizTRPQ2dZ5ng19g13Q1dQ3Xg1W4hXQ2ikAtg013BMWK93D6H7eQ09Z6HQ3mH5gw27Q2AeCAw3zQ1Tq41oBhQ1/Q3jNEt5yfQ2L94luLV/yYZmvQ3OOAluJcuS2ZmpQ2UgA4w0Fho3Q1q5Dow2FWJ7xE1g3dNEow3lg03FBRhXIOL7Q0lZ66XATQ0/g1/p4q8r9Q3rQ09Z7Po7n4BLQ2bajzQ3e9TmHA3H7/9iiOADWJ6DSgw1KixCw1LWoYWAF9XtOUwn7YTkzZ4ygwXZ78oByw0GIyfLCyw1XZ5PKT7Z4UYBKw17Z5KDAPYD5ahzDlzZ6qw2DUYTZ71NUXXERcDq7b3Z7lHnz6A+7B1AGn9VJk4X6CFbA2w2XzDIJSHZ7qw2k3VjSX5DCv0T6Z71mYonZ0ikUQDaZ63GBoYVbtg1PE61VtWEew3wN4CeZ4phyHYe0i6xhydAOnC2jZ3thbHSxw0cfE3JCMKCwZ642pVmG+TjU7D+w1EfE3JA8i6IHJ4ppUYWC+L7PGGWI1XBUYV8jjTw4lw0+nZnVAQ+H5w1oahVVX5vB+w2d352HbfYG6oQRw1xw1lw2ew1tw2hw3Vw1uRgCeZ4QBUYUR+Yrp5UPhbbIDw2XVKwZ6cWYDHY9w3Hg22+AEIAdw3hw1QwwTyyFw2k9R2Z74AGjs6Zw2Nw2fWzLdnXVXKBIrw02sJ7s7YizMj4hw0Zw0oBgkZ5Hw3zVWuOazG5Nw37w1Fw1fp7Dw2mfHTVUI6y3w3chSJfFqDBMiiF7Kh2yrs5GfCnw3YTqzw11VVOCb6Z42chXs7HWDFY4Lw2Scj7w0WKCNghcZ5ITrgI07w1ew1XPrzVUvdiwZ6lmJT97Nca9w2Vw0ds56FkmTQRQ2UOL7w0Xw2bw6GoJ1w3xxxBw1wo7oI39xyDw0+Q3K3w1XCLxyv8A4NpJw1VmF0fqU+E3+LTazRFwqAgq+F9w1LrY6FywI1dw30I0Hw1Dw0FjTJw0BQTOkzcI0foX5LBGXzCI2jxw4dImZ5nw2cFxrGwuQ38I1VmFP4ruZ4wvDzPY6o6k9ShZ7B05SVyiI28WCnEYRzpIfVZZYmyb8BU+kZV7UO5VGI2QXXoRX7s6oXX4fVqKCnOCSBUv1qp7WOlUmHLv7X5hVHkYQHUzDVrb6GvVLDUQfF4xhjDXVKbmvWo0Vd7ZV7WfhUGI0+lXOfFSRUOMXtfGUf6r3V5fEcvAMg1QPVH7IxI1lvV5fEuCTEM7mjW27gbeyGqUuI16vXfDVmWKZvVzVVZfFQhaNXVZfGxvavDXBI3tlUBI3CRWyg1xmBO16JlXd+IFI3hI1ZCFiXB2RV6g2hI1NI3ob7zPZ054AaYXjXs0VqKA+oBzXXefHvuCLXXy0XxI2/7VWjUQgzpKLxBUhQ0cXXnhW1I3WTKdqXd+KxvZnlXlI1TlV/uVJfFhI2sRX9fEHkCmVawnUzI3PvUTvWTI3vlVtsXOBIRC6P8V70XDI0hR6vXXOfE6oQ/XX20U9I20DydvUdI3jvXbI2NI3j7WwTV00FpRU4sFSkFdI6pJUfI1xJUZJVB+oJTAs0H5JU/I0pJV/I0w/WfI3DI7fI0ceoAo2ZRWQo0qlDgo36SDvI1Qo08cWDEA0HXulGlJU3571Qi9RU/jzs1ak+iTUgtRUp1WGxphkLrJUEo1lNBEo3LJWncWko2qVCbRW/RVhZApBC9JXTJVdpr54QLRXtTqIBpK8xhdboo24DpbqxTJVrRVMw6OLadJUjRVjdC4Wy7RX9RVBUDl6bEo3HRWAYF4o0xdzcV6co1vUCwxUyo2QYBhkLUIljJByqUPtINVyYxWMSU356zGB2Y66dwso0ijX6DB6I1G/LRqWXnXkb7azX2SUR2rn5WPqVPI7b0aEnUTRYRjXZFVWnEaLLdHVhSXYTCZzX+XUOF41qXfnVoEELPUaBVWnHmFB4g1G/KqqUvqXAAqWo3/MUho2ofXmSWmo3XPVjMVRo2r3UOF52qUb3VWnHTYjb3UukXUbAnqW6xU1CGpzX8nXbF7uzWSaVyqki+V1XU85Z0+UXrUrI48+XGnXho0MXVGo0DzU6RWlo0jzXUsVFo2tzVyxXGjaxo15U6yfWkAqZqVr+VqnHU5rKfXrfX5BU9PCXInSCU0l79o2GdafBKl8ExhwR87ZjwYNFux7EV5ITliGFQByF1VhtB7l6r0nsl6dHFLo1ex611V1xyFsldOnW3VMCXYEpsl5Dl7DdZbo1fl4YFSAV5fA1kV6ds6FQj3tYOUl/UG0uk/1VhtCcU6MundfBHSFHo1Vl7ONWLo1ol76l7RFg5/F3A0i94NbZrtblWALXm7DA71XcdYMWA4iG7OnAY2myGJJBgW5/o3IDYtBx0TlBFAMomPjxRl6pl5vo2xHHxl6894Z1UJIDjUH6l7El5MHEZl4ml77VpzpybDwnxkEY13o3Z0EMV63o0BNViEpUiG0ulgNUcyHXCE4Y2/uxMHH9l75l6YY2jo2UukQdBSdZ7o3dl5hRH286uARGcTDXnbQlnpzcY2jl6FCw186Do3dl6KwS5NXkY1bLVVOkUNUSY2iY1Bl4iY1fl7iNAtIlno0rCHIpDRIbzSHXo16l6GTAMNUKY2Zl7OTBqY3sY1fl5GY3CY3OUkXl4nl5fo3RYWzl6mY04hzfo1QV7gV72Y3RYVLo3JXlCY1XDY/o2YV6EY0fpwvo1sV6ql6bo2OY1+Y2oY2eY0hXnINX1wAgDkhXlSNWEcC/CGRY2IY0QIABl6hY2HInvjAhl6YV4PSgqRl+FjsGmgaCnIloY1Xnn8JxMY037HYY0XyxUY2hTyjMFsV6bNppTnDHA/jnNyz6Y1I8wUY3VY3GY0HbqPJFlY3TJX0Y3no1lNDFY38Y0Xjl5Y1PInKY2pY2tVLqyFro2xY1WNXq4o2cBSw2bqkEpCehbJkHuKQWJCTY3E0DTY2eLCzY1lVDzY0cRCrOLSV7LY143Wb8BblAnbL4WL5kEtK60bZGV7rY1FrCrY1zY1RoLlrDHY3pkG9DJybUwAWfBX3l6Z8Gw+pjo3Al6Z8G6sm7MHchy5NXuS5Do3uY01iGmrzmbkQl4QFwOoBzo2PY3F8GoKZV8G0l4gl7kbCQpHi+z5Y1vpKZxn7YUfl7vY1jo17OVg433Y0Tlm3Y1A42OY1XYVe4xo42uY1Sl68l7JhboY03JAvRXqmoil40c7ceT38HPY1hunEV618EnhT443XKCXIn/Y1bl47I7Zl7t8FN6gaY3RFB0Y1TK41a6895e4x58Hnkm/o2ml61KXw40cY0xl7L8HI42Zl4abZD85qS4fxzOl7Xl4jqARY09l6zmgkZLYZiYGm+l7vwBQY1841Bl5ipaEiF2l7hl7t8HA43sGmI0btDZ4425Y0tl7T87g40pl71l4NQDvwD4Y2pl5M41W40kY1c43jl7NSV40H5l7c42642NY37m4SRGHl7dIAMY0W41Y42EV7jqAEDRfY2BY0dl5Yjb042SY37Y3BSUCY1Tl6u41E40Wl5jl6Gl5h41dOnx42Fl5m42WY3DvULl6p40DYUbl6x43rl4R42J40qY3sV5RJyC41Pl6F41Y42Tl4CaBQ42Z40l40a43PklZ42o43M43B43Pl5PY3B43vl5i87543AV72Y3gKHk41eY3s43k40d40a42i41OY0141QV5uY1pl7HIA+42IV5ml4OoD+41oV7F87542YV72l7UJzz41EV4K43T41wxFEV6E43e43no1zQlnpyyzrUV7eWAMNWzYDO40b42443fY3/l6l40N42DY0H40tInF42Go1T5CD+XVrXNEAP42XnVP42TrW7uXNEDp+UixVXj6j+WRjWoX7trWsxXOV77XigRV+5bST6OCTcxVGT6PfB8xWH5DDrVfcVT5Ce8ovqX341v42PqWIE3onWjV5Rgmcgh0aUf42MLFZXW9V6pvBdnV/kFpIofrU8aVYE2NrUgjUqlboE2YXX8nVXj6evYdjUSsWmbB8fT3rXST7PnTLFXqkUoE0LnVhV7P41ZeUcE3kbX1SXcE1unW5kV8E2SlWdV7hDFCE29V6P9QylU285/41ZsDUeUkT4ME0RnWqfVhhU1tBlpU2qWLzBNpWAlWDzCNHVElU8+DbpWGlU215tpU4lXfYFdpVLDVI3r3pX5hUvXrN/K75UvXpzpXGE1r7A5pX/hVExATpWGlVExBqE3GBXOE3KE2klVUhmH1hbBVuE0pSX8fWLzCOE1CfVAA4X9hzCqJlUvXrgRxURW/5WqE3fBWyfUU16VpX/BVI3qNfD7RVDhUJE2AhUAcUmE3fAGdqVwbEwhXnhXmE1vpVbvVExB3kImp4nhWHY7TpU/HUOE0MvCZE1KE2K5VrhVVE2p0UUjXlE1S5WzqVq15TYaqFWgbW9o3k3VzmS1riqboMV7ea4b15rq5enCTY51Rz5dXZip5l7eQBqJndE1bLX+Jmg4wG0YDE0yjaX15Lq7ybxjY3m0EmazTTVxMYKZBvdxDiz9NIU4COuLLE2vWYP1Lwo1+1ZiDzK2xbE1FIA7E31NabnbCwYI9oSNEbE2rE3Gyov4BnE0oPVHE2kAEAo0yDBePLHE3Qo29IAPE2iN5PE29ixbE1SN6Y9zGN5rE09QBfE3SoBYDU4DWnrEu+jwAE3hRMiBeN7bE0lYDmg3KZG3sldE38Vg/15z15dE2r15HLWHLImTQY1Wta6C+q6xjLX4erbyQIQ+FH16SrVlVptRX+i5tLWg544NoEk3716316b17316DE2RXm1dWYk1f17gN4ybagD4UzYUk1NZXIN4kk2AN5gN4kk2gN6Ci4ok3H16QN7Ek3x66KrFLWHhJnRkWyEmc3Xz17ixaE6x6I31t51Jb8BVvEGTrU13XJSaMhVNHXk3GkE1T3XSt7v1UdHW5zy7Ard3W8jo00X9HW4MZChWD3VyUADrUj3XgDpMnUOo31t4dkRx5XJJ4kbVgBXOk1qk1YRVuk1ahU9HVpz6TrU8TWek3OvVr0Wqk0frVak0ncwslUcaVBt5gyDSE1jhXSt5xryyTV+k0ak0gbWeeLZt4uk3/BU4/XwbVc3Zpt7LkHpk19xUxk2brUQnVa0mobU/HUZzwYbX/HX8LwgfUAPWWSaACVKTVyUCvrUQnU+k2+nX0jX+k0JMUUjU1k1jrWzhVyUCuFCtE0jSVHtmFT5AUV4PUeZoxxgLxUkrAiWX/kUmDDDk2WEXo3WoeCtlwTk39k2tnKoUWscXTk09mV/B69k1qWWSWWoo2vLFbrI075GUUNB7V85MVV6UWprZvrlGVWvxU3+yGHUuKrS6HWd540gKUV/xWe3Bbb4yUUYJWO7CWRB8UVFr56hzSHV8UWSJVFAaS3X8UWSd4qHVVFEoJW0/AZ6ysUX3k0oTqOWXJlTXk0frRGVUEJWzZlHk0kJWohy6HVFEVW97VHauWXbk1PG5QU10WUv0oUWWjZmvEXFWn/Y4YPBhWUdUWiJUfk14kXYU2Sd6jWW3EVgFZfLCkU1iy5rw6EU3FUU67mEbk0TxYWXoU0Hk00tVVJUrUVsUkcwpEWVFKR3mWbk3zUVMU3wd7DZifEV0U1Qd6nk1UU2sbnaTSa3W8JVHT79UU+UWw448U0tUV7dxQHXa6Da0SWEUNTVlElSLROEVgpV/LUMpbo8U9mWqU3KU0aU2Tk0L2C6ukqU3XJ7GU26U2GU05mB7Tkjk16U06U1qWWaU09GVk3UQ37j6Jbk0tQJObW4Pp8VUTuEqJZBXSmWU30WUUXeU1jmWnQhm34HZnBWW4pV725hEp8UVLb6a36Pk2/LTxbWHHTdKLSGDRbVNjCREIJU2Og45oXlWUxU3cUUumAAU1U+C9JZFYFmVUW0VLEUUnUBU2k1ZFU1sVWldVr4F69IgU1epUT4HbFp83Wu0AQxmlU35WUv2iSJbPQoNWVVwg6G7+U0SU3cbh6I2Dl5XXJR7UrWwuk3h7UDU1IE3D+U5kHYE0OtWS95qWjzZXnOn/42+o3S42mk3+XWy94lk2og3u6DWk3Yg2lxwwE3wg3u6C1k1htWK94jU0Y+V7U2oE3u95hYXCnaw5XDU1ahW+tWHU20XU7gDu95mWp9I29U0pk2AZXu95eHA7nWDm7cKmGg2zqWy944ggmXVmg1vzXM85MK43g32Jni7KinbuQ36jZeILkQ3Hxxz16wm7+Q2wJxOjY6lKEZk8w3lxyb2nzfiYw1BIQ27bG0E4D5ng0TpKZJxXLUTY7rH5QsqXxzDLVgD7UQ3cJxE00JyUslCDQ06WGP97dQ18ZwY03UhJaQ03FDWJko030w2w02eGZ6jbFg2Q023snQ03Uw0wFyGWHg00XQ1sIRA00ZpaTQ0RFwq3VY/iww1I03CLQpyUA00z95ua54013y59g3dADsD6Hg2fQ6S00SpLk01VLqk01r7DZw7cQ2DJxvY6Y01wQ2RD5i00ZyWG012D7uZWiD6603/94ZhTc02a02WD7oopZKVzw6q00SjYenAYeX2Q2PKFwN6xKky01H7AYjZz94S00YjZyD4w01201uUrvg1NQ1q03nD6VQ3LQ1f97MD52HZgw1R02dNzcw3jg1B03f94PQ2gqyQD5v968ZnwQ3X94G02R00krWUawp00tD4qa7w038Q0ND6gwqJY6B03ED4FrTGJk502g/r+YAQ01ID4pcpV011ZiMD4102qH6bg0v96W6HIjam02dD74D4a03sQ1cD7wD54w0zg2t65/Y7F02NoDTrVmD5101eD6FepVKUSQ1yQ2XrUu01RQ2WfIgD6pcmpI7bQ2wD4pVSxbAs02WD7MZIwBAM03OKG8Oiu0Dkw1z02tUmAD5+ZlZQ3tpDK02W00X03U03rH5QA0sEE300K02L94X03p02/Q3e00n02XI7sK7jXi5D59EyT02H4HZD7l02N4FmkR+03r66pDCIw1v03OhjOHC9g1P03lUEaUjxQ1303tpBbOguYVt03X4GIM1GQ3n00wM1qeBH02C02ELWQM3HQ1O5ZRD72Qhb03BEFmkQi01zD6X03sw3lQ74HCkM01D5E1qqQ0fg2tD5AM1+Zk9Q32yXdD4DQ0Rorz4Eu00jQ0BE45EHW016DYUM1tglrqgZ02RD4ALXeTrcw2rg2d95ShZlD4AM0iM3+YDcw2h01Tyn4HBEM1f9buRS5Q0ygSM014kSEM0C00gD6dNIygjEw3zCWk6yb01X03aEQZD63016Z5f9a3dgvQ3ng2d94GM3tD6v02qD46M0VH6g00aM2gM3SM06xCwM2uM28M3AM1nUSCM12M1L94J0KtlpQM3k3BXpD8D6Yw0JQ254HuLyg8j500v94RM0e9UslDoM0/UQgyxYM3aM3T00lH5FQ3OKHeM1SM0c01996lLrJIBiM2Z03M0maM38M1Qcz2QhyM1f03UMxt2wCw0WGT84HlWDdLqVM3A2Dsh4WM1LE1Vjaqw32yVYj726BWw03D5uuUqw2aw0wj4FdKfD49M2tM0Aj46w2DqFbdavZAukHDnYyZLYD5DM0mw32w3vD5dM3tM2Kw2ywDbzLPD6iDBJ+CzM0kcDLM1Ow3HEDgj59M20PXZaWSH5iphMrFTEUTuVUfr84EU3wDxG4Sl997nM1GYUjKgyD67Nn6H6UwqL6mOzHH14KYWb+H4RZY8oLuXlw1BD7YLp5HYBtAH97QcC7Oo4eX/w2WDYZEwlH6XM3b01lUSTxGGaWxKHiIZW1r/uVZYy54HlBij1zvuWwPDF4E+hZ2HaHM0RFFz64e8JmYWyI3EM2SS7/uU7IzK4EXoBc5GlB4SmGaDZLcTAeU0I3ZKFe9IXM28I0Qs1zXw3M1fM0Us13P5oYW8QCgdGM65g4jxw1sOjbFHHM1MYV4s0jDZ9BDpZlWZB0QXvM3VIx0YUJ0QQs0LPSrxFuthHM1Is3y8HmNGos3lUFBCxUYXss3zCXL5plTFm+wF+Eas1Vw3AI0Qs0s4ieZlJXo8Knys3cs3fgoyD4GC6TxFTw2qD6G6Yq1Hix5jw0SD5Cs1UYWII0SD4KXRUYVRGadD7XM3cs1qs1nM1dbCmmHuyoCKk6s0YI2NTIv96es31w2+fGBs37w207ZURYJVytVVGQCXiHHM3AYVEs0us1cs37w3Us0s4Ges37w3us2d973M0wI02mGSLVglBVVX9eSkJyELVtiz9xzEI0B4EH8R5LbTVVqI0REEps3Vs2JJnRs1CJj9xzVOb3pwJs2pICSs3Js29+hls1Js3uD5cs2LxyII3OD4Zs06Fw4rzX4GMs2P9HGoq8mi9s1ds3xxy0ITUJxMM7mRIiI1Fw0b4GnPYqs3MZyinT84ERs3xxxitxFDYls0DMHxxwR+bX4EGs0sI16s0oM02VyUZw1s1Ts3qmGWQTFtids2mmHK9A7s1Ds3yWABtAP4Fjs1ZR5llSlKlLnwSZwQI2Fl7UZBQDJJR6JCxtPBRD4e8KKU0WxH9j56o6eejGj5f6pz5kQc0/9VWj7UvBGj5QdlQc24ej/JVwc1liRtGXosFIc1fsTlGUI3VvWCoc1mcSGbYADWYc0Ec2XWB4c2+j7Tj6etmmlBBkHyjAznHa+iuj6Fd4RcAjj7ckHUc2Tj4Dj7kc0Mc1QZDeXmdDAymEGj7hj72m7As4DFAqEUOU1jSW0i5VOizT73rioo4P1kbwQOKSGzxqi5D7B0j4TK7ko6Sc0rp4bK5lKX48zFGgyPFrcxwjatcwpCpAm4AogHcnNRRoG4PNpac1wLqqMa6c2Gzwii6ZWKgJWac3c/FGVzdT7Qq4HW5jsxgHDgm42VxhDUGc1wo5U6KskQ9U1T5Cm0Xh7WURDcnXmtV+c2ak3D+VXj7vUUOtXUE3EnXwg0kT5knWsxV6T6e0WrZVGT6B0Wog1GT7Q0WA+VT5Dw0UveVT5Dm/VhtXec24nUmJaMJBmgjIaWMJC4EgLnVFc0+c1JtUcT5mWEfrX6hWlc2enWj7WBc2iE2MJCjiinpX/ZWB7EYE3A3VaT7/UV+BWxc0+hWQ5WH5A6nW9c2KaGACWWaX5c3m/Uo5U5c1ClUtc2Vc3NfVFPlMc5tfX5c250Xu+V9c2/8Ve+UJc3j8Urc25rSFk1OjXdc1IbV1c2tAnZk1K5XST6u0Uz7Xbc0zqXA5XST680Vg5Wrc0l+XHeWKIlSV5xA3XJ62tisbXxA1cY5AdZ2qSybXPJ5lkFPc0WU1mImPc33c3/cB9bUibXPc2FEm/c2A83XJ6fc2rE3hA2zoDrk0PRaE9apbXjA3RBGSdZzW4tA103Ww80GbVq3XViVWmBo80NA3iQ5w82mbVodariUdA19A1DT6nA7Dm6Z9x81YHZZuUUqbU8ZY9iUubVU81uEk+EDbpVk819Za8BE60LLA3DB4WkbqbVBbVdA2I81oxb7A2o81yqXHA3881nA1cWXNlGCMwC803A2J+E61aNbUS83dImEApLFYvA1LEWNk42JYldzuWW/rp8DzXA1cWWGo387ik8V/+Va+HuTWRjXOzj682b8WXNYAFGxsWr8XUHHZ+otVUMHGSTW0FXsEAkTUyXXsEDkTUO82BbigaU1FUSHG0TXrrXj7h8aW9FW1U7a80DFVg1V+815FX80UIDb0dXTFW5xWh822+X6sWB826Xa9E6Kk01z6RbA8BVFNYJ82sqVJ81Qgg7DXFz7KFjmzUWvVFNaxkySBWAoln5hARVML7EbgtBXeL7bVi75U/VGlJyOlXMY6X9R583t9D+zWGlXx81p81gBWN81kg3GkUZ81KPgljVYNzfaFZ5U2qWp80yeV5XUZ83J83KaUZ81LbyjsUxBXvl58sWAjUZ83CXy0E1jiG0VWlW5TVVF82FW5T80t80LnXFz5ElKjjXFz41rgojV4cV/favmJA5WjkVb83wv7jqX582JVZIcVzNbOW6zhVFNYd81AVVFNaj82gVV983KfUaL5D80AcV383/QRMjXX821fFHqUX81VHTIhWn82VeVNqV/fbH83nhV782x+ydqVL80IfVEcUQC3rqXf0VaomPZydvXeL7Qlg85Vd81TcQcSzn81swnZkDoC31lLDeXaTV0Y5IJIP80f+q+sWSjWr82zvVXn51826g2ujVkE44C1KTV0Y6CuhFE0MxneL4MZobXV9z6VMg58U0C2IaDwC2YhXQC2reWKk1nCVN80xhV+3j8C3j5WCC1oRXBlVA1Dv808qUMvipzXYFXfwwF82OlXzvjF835hVhBDeJA+tVH0UvZGV82WfW1sSYsVmfWxOZx5V8C2iC0GfX79xCC2NhUiC1r82mC1SFXYGBkQqiMVQPWSYxgC1PDUKC3L81kE0N8EpJD8XWWC0qC2n3VT0U9h7sqIwBW2yWKAzllW6C24RX6C2JvVBC1i9ZWhVefj1808FXYGCOzQTzUgFVIvhf81IcV7Xi+GpAVXmC05fXYGBOOC+sU5k2JC0SC3HlWd36qsU/HX2z6/82blVX4WlW5FC2Z8Q0cUBlVGC0yeUBhUhC2p8WKk15KDXjUxhXfWENC3j5VNC3YfXdhUXLB4fW6k0zcatohphVojnOo290U/kHkfUdBUAmmJjUtBWeTG0fXGE2IwTbciSBV5KBPjVOE1UwRtC2vUX1C0FjVYRWtC0P5W/UVrC3JXWPUVk/obHihE3fvl9jVCnXlr5Lqh7rX3DW9hkqxVPDWDC2lzVVqU7C3VeCGqXeiajC2zsWmwWfjVTVXgUE+xVT82zC3hxVXBXLC2OxXrBXfC34E1Zr4aHia0XbC1CCCNo08TWbC2to1Jk3ur47jKX0WA0V/C2fvVb+U5lbG85IZVUHqIC5aJQ3ZhA81L8kCBCApW19VIi3oi3fc0CsBoi1zYg4i2Ei2CcQYi2Uu7utXYi1PW5Yi3SOSlA2OU1etnjGHQpXpXTRNWMgm4q5UlUduGtHwapWm3X4b4ci26ZVnVDadUsi3UG7YkU6b7kkgEpVQKZOHV4+wCZWG4ZCuH1KyUpXnA21U64pwSZUZiRxU5Cgn8JVSi2C8Go3FspVii3zU4GHUqpVCi2287hKK8i0eCoiNWupVeOo0dWI3HsJXJXTFHU6wrUJUMPoQxl5EnCpXDA3Ci0mi29JH9F7ytHCpWRCEab4Gi2Qo5ZU0ddUai3D7BpU2jUUz4ViUX3Y67Tjai25BS2pVJU1/A3nE1ScWT6aCcW6o7rXALxUxi2VjF4PXxi0ewDkPWpi1CABxi1x8ZpYzpi3Zi1hAApi15i1vZBuw3ybVqfXJcXLNjOOCtxw2PUMpW2CL7/BRcXmcU4daVi25PXmz51JVsBaWPUJRk4qZNi0JcUwd70GYuPUodAzT7e2YOcXF5CAm5mebHAD3I7li0NEWJEYecXF5CgiULoKe3Jji0vRkfEESPXqNFtJUCWIyPV+cV1JWri3txxYpUHsSzi2RPVnTDXigHeLn2RqPUNi2Ti2f1y+PVeQiTBJdkqePXzsoji2jADHi0ti0GOwePW+JC2cW3b49JV4pX5mC436ti3b1Gmu5UdVgdT7cVVNzgYE9i3y8HFrALi05upPi3FrAzi3biZ3i01IDDRDwXiXi36dilPULi2ni1Ao4HcUziiHi29cXmoCvygm34+cXvi07i1D7J7i0xcWgYiLi19CD3i2QdWbi3HcUtQLDmgPxzhtzXi1US2kOGaPWds4WcWtxyaZD8o6ES0U77OIyGPX6ux4S1rSoOPU/i1YdU1wT/i20gLgYEcS0US1lPUHtVQrSsS2TDzoYH0S1LKEwS2QS2sTLssiIS3Ida1i1ri2oS3CS2HckUAD1cV8S3YS2e3Jx81LmW2vWPUUymUyvWGS2XN5mI2vUUBWn82hiBWW1CYBXYFXR7EavW+o0H1yCXWD3WJ75NvX5hW01GGaAwRVdpzAXW3+WpyBMXX4fWpyDXnXp80BS3GS1t83BS217WA0VhS0N7VGaUgZGBS1D+UN0VGS3N7VaqUxWmYBXhk31pzvnUyXX1pwhniD7WlpzgQRg3V75y5S1jXUrI0WS1uvVnlUBWncTB9I31pwcQiNqVVqV+8H7vVbvV9pynsC2jUHhWtpwy+jIeXy0Vvfa7I2uTW+S06XXrBWRS2FS3Hz76S15S0gZGUXXtc3n5wYoh3XWH80tS3EXUkjUNS3gfXn83VQh1S1NE05tZrvUzS359xP9QIC1TpyPI1BBUJS1g3WGo22H5V7W681CI7l7UjuUVMhV7VFFVCI7x7UKRWd8WqeDSfrrrV3Xn2I1u80slCr7VUXV+ZmP7UvS3rw6JvTyXVIQ11WyaSVinXTg3c3YCFViZnHS0xvpb8Vjg3Ay3ZFXcw1AxnEM69E6fH5f7VBSWBOkh44XrX3S2+vVOC2An7qVj9m4nuWr4R3I1Iy3fayWI2SaVHS1V7UxRxyZmnS3CRV38VIQ2ZITmFWhMVCI4W/S77Voy2YSxgTXIy35fU7eUIy0dH5paUslBwy11eVdx41vVky2fH7PS32FXEy0Kggv7V1XUslD/4jbjb8nXvrbhDYpI2rkXyZl37XBRUxK5kXUVXVQQ3c3b4y1MOSEy0wy1gy1V7U8y3/S1bI1seVlK67I1sy1acpTI3S5Urg2Sy0My2WkS52J+BVn03pI21xVPS1OI0jyqwQhx82xXqWXUOZzvBFjpKJ83B/z2XXCBUE0ChlUN810nVMzb2k0UJCIzgP+UULbogTP+XKn41lXOS2Q3WeERV83EfV0MX/hXHV5fqg8qXHV5uy1BS1Oy2QBWuy01hW1VUZy1wMWHC0ULZwzxW80Hn6hy04E1Bqk1MV3DVXn53DCly1DsWFy1WlVOC0Hn75y2GqXhy0qMWL80CVqVlXNy2PgQDXWznUOn4MbgtXUxBVpy3tXXs0XJy1thX55UJy1ZlW5y3zVody08TXZy2ag0bPZTy1AxVQPXvBFZMQiM4NfUvGHbhWwnWBy0lMUzS2y+xnhUXI3HV67sJlfUxn7nnK3830mU6g4UjWDy3zMXLy19y1QnUjy09tVkBVWT4vlU/HW7y2VlX/BWNy0AZWAC06gJXMUgC1by0tMWUC0Vy2VtU5k1eqm/lXEC1fy2nc2TS3vy3IvUflUvy2f8WBTX/A3sfawsA5hJR7VkVAfuXAg1I8w7uWQg0jZypnVT3UWX6XIzJ7VVGljuUBtV3czTDWLU2nX4QI057VksBiPoV+WOk6ruXOtUBr7ufUwg1wK1IK21hUWX7wK0+lVYK0MK0LFWsK3xkVoK0CZypnXhk1YK0R+ZevXOSW4K24jUG+WmNCC+ISna5tVksC0eXOBUWX70gYRvUk+VwK1XuVUXVMK0MK28K30K3xkVc+UKK1wjVOC0yK39eSFI0yK1SK28g0PSxfDV5I0WX6DooNlUd0VVGliK3sg2mNAseWFlVVGm2K1dlWWK2EK2yg2mK1xs0U0U10WmK0kK0jlXKK0/uUk5VqK26jUfBU+K1EeWMg2IK2+K1+nVYK0FDBtvVCK3cjXS5VVGk0I3XHWg0Agc16NGBVAyWVKo5RcCpK0LxUpK0YUWGN4275QUX4i2uN6FTWDk25iDpK3ZK2scUlK1Lk05K170ark1XY1R+Wli0Axx6vj4UWW1a2KYeU37k2HoGU0BsVXHk2tqYQU3nk3NK1MVWmWnf1FWzy3k030QYJWdhDRU1cUWw443RzxU3CUWiJWDRGfk2SJWY/FOUXjK14YHpFFqVXDK1EYE7EIgU39K1Pa4wrBsVWQU0SDI+U1WTDK3UMeBwU0c5h3mWtpV1U3nfZJrU7K1NU2xo6QlAiU1cU1sUlItzPWXEwhVZZOxyUU0lUUMYFBWX5UWMJVnRyyZDHWW2JWTK0p3Xc7hsUnfRycU3Aq2prY5dznWW2JW9K2CU26JVdK10WWrjFtK33K2c7Bcd4wq34U23oGQq2cWWHla8C0P9kGS0V0VLiBrI0CC2Z1hmS0GfXKnqWI26k03iCd7UyC2isUoy08hXY47JI32fUEfCuI2D3U/DZGRUWlUkU6iAy3+U/DbFI34fXBY6BI1aqV8q14q1b0VBYFORWnU3W0UEq2Ey2Q0WCq3XU3dYESq2ky0xE1yq3/3Vwr4usXnI26XXTYF4UCqq30jX0q1OI3HlVaa6wfX5C1Mq16vWblV0nCyy3Gq3rLSdS0BlWAxZ/vWOhXSq2kC1HYFmgx1E2H83cq1NE5NE0/DZ1I1khWsNz44FGEVME7dOrvEFnqT4iVtCqK2Jgbm/EE8q6Bq26jJMiVBwCLKFQ/LEiUSFkVTUFCSK2IqZAEcCE1i3EGJq2ir7lTzvEF1UrP2DJq3QxKfEGTZ75PYpq2g1BtElKzUhBK5q2ekG5VEFCQAkFgbk6ZDVkHtkFgkFMc0okEHhDpq0wkETDJwkF495GkGByCRNERdl0n6+xhbDJjlA9q2FuLtBC8kH9q09fJ9h7yQK9q2Ua4vSqDdCg9R9h4pzpTq0hwBrh7kTzWBKEkGzq3kxJrh4rq3slHzq0MMDrq1fJwlkFokFngIUkHAHRAXL+kHWBB1q2akEQkF/lDM0kskEDwRskFRb5rwLlSCnq2mkHnq2nnUOKFL1YEFXbMWEXbNwSKTV/5I0WlWFWHsUbfayXlq8WPlW5fY30RkxZW+VMWmnLX5fV8MUcfY5cRiqU/BXQa06FVkhUHhEpHQFtVxZGdFVga06Wl9BxleXAa13/pzy3BNA6Wlvq0m8WDX496BiFUmK3Ea0v3VQa0paFbFVxS23hHQ/Tm8V3DXyWkwa3WqWc5Uu8WH3VM8Xga1fSh7B5Ug1oVxqdxiq2o/kpCzf3VUaXga2wyxfS34a0v3Xo5U9shZFWZNz/mlnw4fFV++VL1YqFULsUyXafq3cSX/q2uxRB81f57Qa0/SDWW6ikXQa1EIz2W5ya1ZUhUa2VhWDfZk+jK+V5fBaXYEsq93UWPLT+Usa1/hXwMWqa0ca0vx4qqQgRFJWQXFWE9aZkUaWkKa2b0Wqa3Ca3gdbM+Wvq2N3Ua+UaWkka1ABWDfa+a318UWWnqsq60UnspJK0d8mrJHPbIjNW1lDxa3q2LcWiOj7Ja3yzKJa26WDEZUZa3tNV674uckgC7ZnYHE1yoDPJV7Pl1NWxq02+CoZU05JVNWksB0OgOpKW8bIo0QFn3eC1a0Jq3YY6IC7Na0CpK5a0hkGmWANrX80DMk4qkE1q0nq2dq3xkHld4oVDYtzNkHLqQGkHHq33q1Da1Pq1Y45caXP7LrcG7bbza0pa1orW15m4yDLa05a2fLWu6gLa2/LVt5lekEgrWla27Y1+1bVyRzq0aDGTZ4ZRb7dLmJJHa19eAna0da0rM3sH5vra3a0bq0aDEyDBPa3UOK7a3E96LZAd9IHq0VeBVkFtq01kFENCdkGMkHdRYDrBXq2/a3kcADa3Ta30CDDa2H5nBLB4V4OYCk0TXa1dJDw61UgA/iQfa3v5mSJD7pl+ImI60ukGil65kE461aJ6srDbY1e64ukHqW48vDJkHCsD3a23r4pT67DC5kEE/ik62hj5+In062Vx7nboU62nY1QpCs61hhGU627q0TMnRaLlrI3uKtkG3q3tq16KAza0Nq1jcG063NkE5DqC62GkEA63jeD0kGza2l6m54VYHZcKB8eDRLFWUGa5lsCXBXV3nEeU49tZa60vkHU5DaxrgLHTahwxY10SIUnxbxCXG043KPK2e7KUF1TFzzqwUmFcQW60KxqIUkffwYRkxcye2CuLElckFE2NtbLe5PQkfRbrx6IUmVU34sX/a6zuHvaRWIA/FYty3mqhDe4sUER633FEKRrkvk516an6fQkLg2GUGbgiftYO1IBqGnFYh0D6gnze4lck88BD0igUm+60dsDagg+60uUEGmAjjCT5w563lXFfuGf8LO62ECzKsXl63PzEsUEQl5ZHBDe6+UHILod4i2e6kaEfMWFngQuE7K3AsUQdAZOz9kEO60ssXcmJa7GnBklaFrFZa+pJ62h638UHBAbt5x9WGl61jQCG619vGF624Va6635Ei560QXDFjKhBEiUEShDRiB2iVD60rzH0VbGiXBLHBXF7lbb62d63zckYVZudZ6tJt61u61upx662DkFz60V63J62vuGiB4K8it60tvnWHrM3gfzEsUEEjQt62P61TFYAjRKaQfzG+UHp7pt6SX60JzH3sXSEjpLE263QG0EUiH63NcnPHkCnKkwm762J7o9619vGGvnjsWy4wl62JalkeGm60r62L63v62PDGV603U1keEpch/0G+5AKUn8g6lgDu61UG398SCeH763q7Cf62ag52lTRURR62kUFyVCt0zGWFD+KDkH5iwgG0sG2SeGj60lvGGLJQG0wV4AG0h6rdckqtlT63yuFjGUhg7CG07WH0uzxeED619qkfZA4aFKeHcG0QBHD60hg7PwGZBEZ61l3kQHTT60u625gWan4iG0z62JgXbQkjpTEe5+9mqg5Z60OvHmUkKg6mG1xvGFzEGG0UYioBETQk6G18eA+im8G3+eHkkQQvC8UEsUHiG3NGE0lK/kE/FaIK5WG2AG2SeFMG3YLHx614PwSG1PdY7kHx4bsG3j60iPXISk4G1x62cG3hG3MG1qG3f5TXkHrOAQG0ZG2GUHZSbdlwBG2cG1Xl7JG2rMyTaHqLqGG3OG1OXGzLot+ydWEQUEWeGnzI760T62PCHvIjW61n61GY0RG2iG1/kF0JKlZCCG1n1H78CIUk+G1nkGXgSfAgcG1FG35G3+G2361f63rsqD61C1Jd61+/mx7qdG1SG11sgrG05G1yUGShkCG3p63WaH1/koG0pG1TFaOPLQIIe61V61KLrDG2YG25639G1SECoG1tG2WG3ZG30oVEzGFRm6gIQBFa855G3rx5GG1oG2qY09G3mG1nkEv07e4EL614G2WzpD0i5wVNG3Am1JiQbQkOG1PbEtG2rkHUG1PbF2G3uG1VG3zl4elyFG2fkFuORO4Gom1TFYYdAwG2rkEeG09zqJJrWvF/aJckl4QELG1mTy5zE9zoYG3Ee5gm13cwHG3xmxAm3Ym0IG2kG32gWIREYm0qqwT63Im3RpyHG1/G0Im2kwn6G1PqQvG2IG1MeEVcwSGg61JKG1nkF8HrGWF961/G0wm2LG1X63fG0PG0N2yEUEF8Qom2v61Ym3om3T62jG3WUEg8jj96zG0YUHTG2iuHm62QUF8OaqG2SG0gE0km0mm2bagzzHWUF+G0iUnaG07zo4m27G1PG0sm2fG1E5B8kn6m2/62cG0HAS38STG2vuFxfjPkIem2GUF+m0VG0JG1qm0UG3wwkOOxg6EF5Aym0sCZ4XFGUEoUHgLFOKajV7aRF/Jx7BkuG1OHkPgC4m1VG0TqodG2Ym2uUFeG3suEsUFlqBn5SZm2lzHec2xjK1G3esWRwAOm1km01XFT5CaG3WG2wuVhV5MJjgLHGG3yUE10QaBGqm3BUH1m2AG0OUG0G1mG2am3NEB5dqlG0vkGlV4XG3TvFyG0bn47G30XIjm1Jx4LG2qm3rBF2zg5m2dm227Yym3Tm3CDZz7YEm0Bm3fBHum3Dm3bm1MG39m33kGJXZZ63hm0+G22zHGm0QuGam2yXaUm2Ym22zH/G0QuGutQTzEj6jfkHplBc2r0hHB62pWFszjv1aIV5WNWOm3GjbTo78Ulbm1Do7vm2AW3DpWq60Fm2kUH/m2kUlrm1yqF+A3Sw2Uu5+UHJUHYMDVhAqzByLA5UHzwUhq0k84IW1oW0TTDdeGnzyDeCIcS11Bej6HxE3zDIW3izCoW0kW2EW15a3EW2gMC9JB+tBbSn4W3oW1xi7UW2EsC0W1jlDMW0ShD3mBOVDAb6Ka4fVUiu7l073kkfRb+I4qlbO+pPkHNIKYDjheGeoKzglnsSYDh5G3OoQmUGA55owhnkEmRC0DZExCM2B6DboSk8UliW2sEBnkFyW2el5aW0i+5cQWxiWS17iW1VGFaUHGW2sEB5G18Hp6W2TKYGW3gm09tbmW22W0cm3yeHSW3aW3WUGk7TJGFX9XkzWUklKUlQl5tG7ntVam1HiyfQlFmBdYBwUE/60fRbp4QRAChW3F63U5Dd8x/kEJ/U/m2qnB80CQUH1qoWUEMUAa7i4UHL615TG+9JnkH+62+W02W0qlbCm03636W3Bg4AQlzkHKGEuW22W1UsA7CUOW0qlZem0f61VTF7fiQUGu6LvkHhcY2iCQUEUG1BW3S76RW3WUGpkipW0U/wfIC6UGBW15W2A/V/kFVW0JW3/MINVw9W0+W15THMcyjFb86Fp63yQJZwBNW0IUl5W1CW2QUG/upauHFW2QUHl60yl6LW3lFzWUEe2DHkHhpx1PBum19m2Yl5MvTdzBSkmZW2XRBVZglW0SRGR62LzDZW1XzFlW11TGFnCjW0Oslj62DpSnSDtE1lUE+LxQtKsrD/zV/W3DEj9eD/zUEDK2Dj/VYBl674SlxEg23VUEVMjQ21apgNUHgcA/RHQRhjG4bUCwNEA20NUFo22pvgw23Wa5I21zCEI23nUFhARmWp1UEriomLXeuZ9JGk201W6MBCQJGsrCZmE1nhweEY23Wa5pyZjREE23f5GP3SbIi022k+627jiBHbVYQN63qT6CCyDA4iFF/TPnkQ226HneBBtEV1UGWbqfCH57jy2STB5Rl6sbCRJEPLAyLXavD/W07WKEl5kwzfUEPVajME6wwoBFnVYvCHU228UQeDCda6dbahi2S22wnCPJE6229LQRlAELWJqXrCGy9RwxFJHiq236RhM225ApZrA421s20beQR8D1BUCY1lzhDCEo20wFHIgQWcGs22kQ78UDvUH+JhbLVSBk823B208Q5NDRm2104hEF771LY22U21hdaTITAXnyRz5MFxrRDCHR22Z213UH+21X551dRTCFq214FFmlYc21F22kDZX4AnWUk23O202dYl22dlF522/4Ao5HqhCBdYitS623Z23TRjFJHZ23+RA9UFN20alw0/hTRHhPHH14alyV22C22syFD22y20ata6Hm9233EBPB6EiGSSk9UGv/qmeFXtTFJHGjR5a5m9R2227PzF2115yqcGp1wXVy0SnpCHNJgvCEN21+20C1wR217ZaF23m23ZxZ721X4TW20al7IKI023221NMFr20gxH+23XRWh22VUEv21j22l237xiPLWwW3jY1Y8AGxGenlDVks0GCmRG0FSNmjwDvAD1NYpenFVG89GNI5GOqAVUkDl2SEQO1I/Yu0Ehnk20EW0HhnmIO0fbnIe5JQ5JnnXE3oO0axGcJlIO313Y4O3Rnn9cHuzhxnmYO0HhAoO1V1HPekEwWPVl/7nPVmfE1YO3XiDQeIa2zB0FVCR6KHiYir6AjXwgwACEVMO3vVVRG4aAHLUGr4TwuarWXfCF3czwuYxwm25FbREiO2C4AtbYS21jrZIcSJWVMwwq5ESO1yO1bPjfCGyeyhwCybZ8vnCO0GpjaIhEbZXaydlEBEhKoI6O06RKQWmyO0i+735GjUGWO2URa6O0DUFqO1WO2DpTA22OO2y7ZNkALJG0RLgICIFEeO0VvqC4BmO0cliQiGuO3eO3IpGeO1DVzhHHpCGuO2YF6L6xTREGM0BjDHg6JPLPUGxO2o1wFSAJmBCVG2O1fg7/W22O1X57PAqQiHpO1/VgmGZ1UFBO1/VheTFxw6RSAPg7/JHU0GimgZO0uO2ZCQMAA/W0YCWjZm9pljRXxnrIAVEhwcBG3pmMSz50FZpaegWU8ZodbiZmIMH+Y4idao9JmAXAmgKTR9O32UrZqHguJDO39O19yzhnHdO3gZlGWreEl/pmmplseD9A38LDIAWrO3E80frS9pmLO2lT4hcj3FG0IBdO2Ko6iKxXKyV0FRimugWULHIMFt0AXO2njDDIkpZr6gmDqHdnFOBHLO228HFxBOBEzO0jM2Q1A9lGbWrWOmLO09lHfRJjqFyUjHtaAIST5yHO2D0GWdTJmxTizf0HR+DFPQDO0WyizCVAQQH2lvFL7CWbOhBqicKxTO15BE65hYbnFxR3O1dVTNGGPO0DnFFc6/KivO1fO3J9Y9O2bO0VBEvO0P0FPO10B5cZk4u39CXzRTYu1sOiZZ6MnyMu2IMHIu1DT5ZZC2AUSDJ5a72nwdO0X6DQu3GhjgZltO2vIkgu3WOkiu1Y+F8ZmbRnNO07BrWDkiu03IlUXjQbnyu17tacFgDO2Cu0ltKu/BTizwu1QB7Zarsu0Uqicu2V57j955XkqSQVBEbm7+G3NyxzO19NBou0Eu2CZkNBqKu0ku2iZmzeoJZm6haOu38ZAhZk2u03U0bDYXO2O5mAdasZnCu1+nE1CXZGbMG0Cu0XVzMrz6SQW8HKu1EZmbRmRu2ou19qkhu2eVGy/Ra7EX6Dau1oJGQu1qQAcu004F4u3Qbm5EK/lEA0Swu3mDkIjnJJ6Iu1dDkIrQ04FvpnmzkYu3MrxJSDWOm3O0FCVICzQbn73KeVFMZlMu1/O06Jp00hn0FH+rRBE4J7tu04awnnA8VEg0ZYbmLKxe+Hl2H4KiVDkIFFVu200DuZldO3QxDyninO2D0Gpu34u0nhRt14D/XzRQH2nKu3N2HfRRzu1wMGkxJpu2CSyD0FdZlk7CzO23l6EcD2u1bu1KCWru0lu3T+EpwBdyio8HKu0ev4wmWGqxdO3UjyoIpju2u+Hl/6ju1eDkWZmsjw9u19j7qzmbDwvBympmNu0LPEAe16u1jO3fu2bu3Ju28u1w4gSXBQu2hu3Pu1+KidO2D0GBA3VRSIe3IMF4Bqau3xu2d0HFu1au1Qe3f2lZ3QpiwZu0l6H5u16WA30FYe2qu19yzEnHXu2zu0Wu0Xl4GEooe0eu3v0Hwe2Hu0Me07+EDu2Au20e3tEIQe0NcBX5H/u2CqKXu0jtYfDEfu30u0bJ5Bu0H2mtu1ycS7AQP0FvO3HSHokodu1/u0s9yye29u1qFEGdx8e2uDlfu1rYo/u1Lu2u+GCe3RpyPu3z0HFARcAXKu1MOEUpSvu08BEHxYYe1Du2AdaJEbWu1zhTKe3We1xu2thrH0HQqA3u0Ou39A3Ge1Gu329G2u0M2w92E0e0X0E6e0Nu1zO0ae1ce35tKGZ4qe2Se3Gu0su0Ke0tNgFu1xZkye3Re3pu36u0bJ7+ZmmpmDO0ie0Xu2we310G8vK6e17u3IMHee3MZlGe2Gu3Su3Qu3me3mu08u3zT72e1Iu2Je2fTbke38JyWmx8dYle2mpmgOjle2Fe1jqGUe15e0Be3Hu0X9jUe05e0r0F8Zlq8ESu2ToEIe1gu3oMEkhxDe1cHUje3Nu1gjmlzlV4HJe1ye1Oe0lAwhE4du3ppil4HZiDKOGfu1yZ7LQDJnFqOkSnGpLYge1nu1m37KORnsD7e1r4F0+iGe07e1Cdj0e2We33fUte1Ke3/DmQ2Eme19j7Le1r4EvMJq8FAe1A2RP0yoe1W37lu2IMESu03ohre09e27fVgZmDu2XO26366ZkW8E5u0tJYX8o2e0g+2A+0d3Jxu0A+0wG40Tzhe0A+1c36ze37e2I+1mu2mpnyu3tF7Ue3je0Aq5Bu1Mu3Y+3DZLG8F6e1j0EoyE1e0o+3k+3Q+2/e35ix0u16OhxZnkhZCvD+Dmq9xZEGHe3mOm1u0uJaJu0Nu3knHkCEh7bDe1D7bsnG9pnY+2C+3ZDnY+2Xv7muGk+2+A3PLVwW3BTXCDhFTBrqDGDDMiVy+2jgUmzBra1eG4yNIq+0t5Cpv5dgU4dBpq1SEjy+2XHGK+3AIAa+3+ICEdB6+10mZ6JBaiRa+2eSSa+0YW0T063P7rnFW+3P2D6+1dTBm+3wz48W0+o4aDy4zlKlLK7ALPFM+0SmyKnJ++1lpnPrD5yoz+GDxTb2mYBpn2AbJ7IwikJxv9FA3ye4F02yYOk++0i+5ebXC6GC6CB+2p+3b2kh+2++1TtAXEKz0HZ+2eYCe4Gne2T0HJ+0K4Hte2T0EF+1l+2xu1YbmV+0/0FinH7WyLGKkCUG275+0ygwfxxOuCHzk9l6xOLv0HsSbdZmlxxughV4GzbBa8EenK3iAD+3TcyxqFo20hEhN+18+0BsCuwZ1+2f0HD0ksRbVe207bp+35yobJ7F+2z0Gl+1dta+Tgd+2l+1V4FMZm50Gb+1LIyLSUr+05+0ELjH+21+2a2QeDY6o58vRV4EU9zKLad+26QF7+0g0YH+3oWB6MD1O0/F4D+odFmbuFPxmcRovNGtbyl8HAxr+0JRMFAXm6Hn1t45ySMmH/+3iMEiDGMmFxe7hMGd4kD4WQB1HMGktCTs2q0Ail5uVGJJloZZPxnwB3JMGwB2nimQVyAgn/7Z0iEycBwgm0JgX8EG4oarEk2CPpzkDzv4W4B18B5xfjrNG0B3Ufk4gSggmUB1C26N3FTjGUCyYpEldz4gluN6opHcB2tXkgB3YB7sB3+DF/nmIpEXSEYglRBhRl4YfkV7Bz2XjHzzMHXu1f+0vpaQpHV4kZJmWW6ApEQfmCglWbGTJHkB2itFfc4MV5+zCllG6B32tyPJEGB3HkLbDHL9I9xkqB2tmFieEAPU0wiKB2IB1ioUgkkOB0qoU8B1CeGYNX0fkWllpW5PxmVMA0B2sKriMHYSZymF6B1bLXOyG0Gz+DGMB3OyEE1CjNGIB1WoXIB2dXmkB12oWevIr4XxB3G7lAO6CAnhB3n9n0tHRB2pfmeB1KB0KGFJpwSB3CvrkfH5B2tDHpB3FB2gglZB03Gj0tGsB3dSFmB1RMGlB2O6DvNHpB205YaMHVB190UgkmcB1AiGUHatDG8B3q5yOYCjFnl1xTo1tB31NGiB0NZbNB2yB3HsjB55SsbvNFl+gDCGCFnWB2FB3lSGh6oJmHb6CApGa0BMklaB24yEk7SCAlBB0bPaVB3bB3GB3q549PDrB0htw9xl5SEarE2B1AiFzB25MHOB0W4BYkmYB1GGFdB3lB1uB2YoVPLVtOV/22e4DpgkhW7LJkbS7ZgnPXkg3lEO0rS6tzlIEXfB1i5aUHSNKrQsGUO1WiFSsHKXm4lHKtFDEn8O18sE4CpAakb27KtHyXnY0AAh1HE6P7wkEWj/mz+B0sEUEVOiEYh1ZJAmgok3kptEoal8EX+NllDBKeCEh3PhD0tC/mwDCADCwdIGaDFcO1xpG8O1lnn3E3ZSFZA68W2Li7RY3+mGzSRyO3St7BZFeMGOdF+O0GB03nCUEl8h0i+4GB1u3BTjE47E5yh/vlw2D/jHCh2Sh08h2SMGJSDUVjyh2ztiOMFO/gGO3SB39B3ah0fIBSoUqCRItESh1224rmy8h3nqzKh1mh2SMFKh1227xGCKB02h1SoWignDMF2B1eO0YflOh2hMEmh1SoXp0o4jE2h3Ufnuh3TuEMZpqt6J/BMkkOh0Yfn6YismEccxxO3OyFkgnOh0DgIBjAxB3wLj+MEmh0yfk38AEjF2NDbVg9S7niUUjG+h0FjBr/KOMH7sQgVy5h0fFm5uHULyZh0iNBpAlbWxucRxfnGTrbMEAQhlghxfl0vzbDGyh2RW25h1ytH6h33SFZh3aAkuh3TVxdjBGkkBh2+wFOoVffzbNHJh2pfloklkVAZh2Dh3RJQiEkjh3SQqIrE+h2Nvj8h0snXv4UTVlrcVRfn99gqEkoQhVO2jh32h01+J1O0Ik0em48aqSWnR23GOGSWkv23PkbAq1m2166y52EgJmE7Du21wjH59K3h3B22gikiAl3h0ManvaShmlPh1WhDFaSgYivh3OWaFsGfh3nWYn0np21kV6kuDo0HJ23sakFyz+VFN21/lrBqmM23wrnIAlwR2dqFuOqycHQR0FWIXh2823H14paa5jGXh0yrFYR3JsET23S3ZoR0CcEz210Tm6jmsMly22meEzqYIR0r21MTmns6QWll21IR0aSRNmk720tokVeAaekH20/jkRkAoq1m21Q2qFfZcR0icH3HpNY0fBAWVEk9QgR1k2rMR3f23ormZYr0R3V22MR0quBVmlnh0NWL4R2SR2ajnfh3NUGKR0PcBb2GIR2PqGO0zv20n218R0R2rER3Hh1n9KqUVx20fnkFjmxmnJ235YmaH5gR2d8Y3o0QtFhVHGR0ZRrwcF523xxphVEMR0hYlirJ120b23SjkTTooR2yR2eR2miZmR1bl5stGOR2bNAhYn7QJCVHGR0Lg3/lHRR3C5B/sGoR15SkKR2+1rWYkh6qycH8LJUTmn63pR2Z4GER1JR11mlS22Tfaym1/sEL23+fZa63/lE0R2pR1MR3P20+R2dqEA0QCR3/Dq1R3RYoOcEcR0IaEPsbuR36R1saFtR0uR0X22PjnOTCUVGiR0aY1FNLcR3e20XjlDSYZemKR2ZwBVsETR1eOrZR3FeQ/23S+3vB3d5mhHLQO1ZOH3QXZVHAk1YO29OAijFKNlgkCImCrUCAO2vQVaQDUh1pOGSjFFcG6NmX9pnR2T7HHR05x7qjFzWkFcHiilcDnoh2bR3U2C3R1rVm8FmGjGPR0bR1LcG4wWSNm0O17oUlnkHoVsh3bE3MO2kwVNAjLVTsO2Mh2BjHMh2T5Gsh2Uh1fR3TtVch0Hh0meIOcHpO19NroAmFO0V5B+O02mZuAnUy2iO2LNo2R11UGLEhyh3Yx1EcFBO1ox2UVFaO3DjkJw0ox36O0DW2whA67mEx20x0xsGrrJVsGox3TQ0Ux2+O0i+6GVrox3PmV4x0sx3tsGRO23EAc5DMVmhO00YlzFhIVlZO2gGalEjPUFkx0luKJ7mMx2bSpDVystBNqm8x1Yx0cWLJsFJO2Pjll4CelGax2ajn96o45Fsx3nFI97iqx2F+0I5ppqljrbe3oWam3PYSx1Mx3eqHWx0ix2cx2Pjn2x3NUGCx0UXVzsGyx2JDrqVGyx1jNqQWmQjA42C4aH3czcpEslJrcUkYlhVGtMxnki4aENLxTCHlDmwFABx0FqmMx11hjaLZrOA3UYWO2uETN4HMpr+qm4x1yO3iprSx2Mx2nZpcx2Ju72VHVGz1qHGdxEcHA0nLiCPqEMIpe20xx2FaVgIbJsHhx33wCPqGsGBkWnBx16Ykxfz/lF+x0gVw5x3ux2Yx2mx1zECW7l5x0qC2Pjnhmoaenex0aTBlsGvRBoEIhYlLpFBJGyx2JHx/sGSx0MNK5x0Wx1KoIhYnCx0xO22x17SawR1sx3kqhzsE7x0JCmXCFzx0DCgmcGux1lGzwcFsx1/FEaemLx0qLFI0EXx2ULGLumyx0dsqKcGtx2BqEkUnGHSVO2sCCvx1SiKjx21O3cWV/U1+pUNEJC+2m8Hl2nIAUqkjHpUg3Dd0GvpU48Hy6k9O2/WIxzFm7w/e0RagxzFE7XmOkvKiA8X+DYjO0dkjCQ0bo4IJ2cKxVDmJzF48ESxkDnF5o7Q8HLAVfO3MhHkhgW8GesjKNaAJ3Wzn/jpkG0/o7GjiIMFgJ1AW0k8QHO0PtzfcFDiEXO0sJ3hLmN0zTDl8BTv1b/rzIZJEJ2ug2orakJ2rRnkJ07CDOu25Vw0J2s3xXwKcKwpkRL8WBVBMJ14J0PBE+SXyJ3eixk8EuaFCxJKu3AJ3l0TEe3x4EsNbZzDWu02CKA8XGJ3w+1YJ1GJ28JJJu2Po4/1ZdLq7u0fsCiJ3qJ2gu0g7miZnPImEJ0SJ1uJ211biJ16WCKJ12Na9IYH2k2OIO8VtmYPO0pagmu1WNa+DZMu1oJ2ONZgKXcu37sgq8VwZzfplwJ3uJ09O08J0azHEu3WSwjDl7ZHuu22ery8F4NbSJ1pJ2/5w5djMJ1aJ0paEU+1WcVZLlpjiIJ2keHbpwIuTSu2taQxJ3FWQee2WJ1Z8VVJ2qJ3i8X9ZIWJ30J1L8WQVzFJ2eJ3KNb9ZzWDnUJ2NJ00OZ8bndJ1X1brIT8J19frStaahLgZnTJ3LLkDtrBe3JJ0c9AojAW8GFJ3C3i6u2ZJ2Q8Hi3ZIDZru3AJ3Mfr4e35uksNYM2x9J0NixjO2qtY6J3su1FIj/8W8gg2J3uDR+g07J3lJ3qwjRDYytZ1J1GFHhJ1j76Tu2bqHNnEc9DkhjQblBJ3AtZOag3G2+J3EJ2L5w/u3Y1pXg1gp3Be0UbyYNZNkEwe19j7k1rStarsQ+upknEoZmfJ0eAg4aylJ2+qC4+2q2LQJ0nJ1pu3/rzLu3wYC+DYH2mFJ2rgyae24p3rm1gSUOJ1kp1QC7Me22J378XlwJcAW0p0hJ3FRnf1Kr86NHAWe2Up0a87PcAPu0cJ2E8HEEAvu30zkoZlPkB/J0du2Ip2KtWLJ3Bu3IALBnEkYDGEbZqH4J1yp2qe1nJ0xnGLoCsp3VJ2M8mAqo4yI/e2m8FPkCrJ0lJ1w8HzVr0e1QJ3N84I3kYe25J08p0VZwmJ3xJ008Ffy13J3RJ2Sp23J1Mu3PJ2+8lZ+zWp20jSZFlmp2le09uiep2PgTGp2OJ1O8mCp1De3Q8Kug1qp05iIKp1PFmWAnBe0ep2Wp1YQje4ERRkIrQzW43qzZe0+p0bW7qp0KJ3EJ23tHyp39J1Yb4dyCKe2DqHs8Hk8EQJ3UbmHDlFp3Zp0Ip0WZmHW7pp3Cp0mZnL8kop2Yp1w8HvfA+e38p07W6Mz5QjlvDmHW6Usjmu37+pyZ4K8G7J1kxlqFF9p3lJ3o3Ln84SHDmp0yJ25p1NJ3mzl+J0Y8EtwQRp2ZFk5Nj1p1f0FPFlJpzgp0CJ3I8Hlp1hJ3CQ23tFBKAuzlpyBH855p3xe2mJ2Tp1xp1Y+1IJ1Vp0kp06p1vFmLp1Ce3cp1k8lzp1bJ2E8H8LCbJ1RizXp2cp3ep1W6Y08EAPzWp0Op1Dp3Wp15CTWdVjp3ep0HZqM8nPp0Pe2pODNnHftE+e0Mp3GoBdp2mplpJ208GwqIGp3o8HAdH6p2Pp1dW4r8TMe0tp288FAp3A+0yjJH84RiXI+3zgiyp2gSp+MB9ywaiQ0lZ+8lre09p0aDaYdGLe3X0Eip2+8zKp3YZ2y8nCoD4blaJ0R8nNp3h2i1p03VT0Azip2Vp2DJFvJ0P0Glp1l85tp1jqEUZ2K8k5nRq8EAp2buHF47mOkIZ2jlTgZ3cp2F85DcZMu0KZ2SBoPO0sZ3u2VoZ3pu3XJ0mNWdJ16zkIZ3zajlJ0sJ1O86np3IZ1gtXmZ0Np0oZ35Vzde13p22EltJ0zRlw8FR8jCJ3oZ0xFlSp3A+2mZ3K84GZ0WZ3uZ0+Z3WZ2pFk1dZxJ0AZ1H84IyXWzkhZ1YNV6Qj0ZneDlAdUaWb/J3eDlYNXKxzMxkmp1T1VRZ3WzkIZ0tdZwFH2Z08wV8+3YZ1NM1EEUk2AG+3ToljlDDW7rnFSNBcW2Ii2FZ16JDlZ0lZ3ZiBlZ2DoB2+2Uu7SwmcMHcbB6zA/85VZ3+IDFZ1xi7NZ3rnGCAy1Z17nEPEANZ3dZ2A556JB9Z2ayAjZ2dZ1DZ1dkFfhaIx2fOGOmb2qGQjCr+3foD2zjTqGLZ2++3LZ29hyTWzetXBg5l5xm7wl+0QCIDW2b85UMhYbnbjBn2AzW73WJJ+0WPLrZ27Z10zlrZ0GW03Z1p+0oQhLZ23tFqjZbZ2h+2zp0v0F3Z0gNVNp3b0FPZ3XZ3fp2sOl/Z33Z3gHaU8FxfixRaHW5JZ2rZ1n2KC8lb61Mpk8MCP+3S8EojD68Hk6r5PBCtVI50b+39uAj+3S8EwDYY50BiQBkVM8nT+0FpCcSDk8HLfpCOkEK0sRZ/p2sOlfZ33p2fZ1XZ2F+2wZ35KIY51o0CNx0M52cznyWDbZ21W7c4Yt+2oLwEZ18J20DYG9591Q08Gc8BcbkC53Xhjv+2UhWlIVsBHF43/+U2Wg6Cnd424PbAiZu41q42wCExLjN41ro0pFFttmX40il6hljKGxu43q50McBBtla52j8EG52bBHz40T3YRkh/gnF41P8EUsgznkc409xkalxFtl252H9F2uBFegpyG84284nXtT38GD40LFG+MC5Une53Q4kjyHFPLGl7w4mK53FPIgDkLFF6fRzpz7i6/CER51RognyHXkmgB2tfxNoma42IpEB527BF640CqW69K5UnU43zMFLehDwBd40sskf3b0NS/8GfqAHxkLFHOxSCCnkqgvCELFGu8SfyHOgbBB0u50WoUkJJUiHl50rtlb43253F52ACGGsm26F5523olqJJv8E/OikhHy51pdyn8GR43R8niCHAW6/yHD53tfmk1n+50JnGrBH151hekG2HSBHS52q4k8AhU40j42auCT50843gGj251yLxbyHZnFqHmF4mC1n+51yTCC1l943a/aT51o422Y0Z4l6nDp52F53RFFPqSB52r51V+yoUHt41xxkK1lB52PpxEOychH+50ev798F/52sTJ+50oUkB/Y2fiUhGdJToiHeiTP52QbqopFQF3353K51RxnjtnYdyp51Q1XZ52yEjm4l7AEp8FG40Hulw4gl52140LjZTjyvyFn40B/Youq3kFJsbV50e/7n51/vhhentkJs1lE+QmB1FizrtmWsn252EF1150YUk9524F1d53o41odKMhHD514Br3539l75Z16A74CFNoW4KEb27ICGwKHVoVogDWB4SF3kiliF2WFArTzhKhZ7HNoXsh35/at2xtoWSr6ZpydoUIh3LM5loUWSHdMlKCFDoWT7k6F2PYF6F2tMp0Jk6dEcDGQh1UxBGCEYdmWSGPPkv/nPPngO0gx2juA6dG5Oo6KEcO0xpHQx2PeGwx1+0GqF0Ix29+7OBD553t8GVbiiO2FFGEQjvkEbVkih29223BmhF38h0ytSm50mzjUxrTFH5LBVBFRF2Sh1BF195032Xqh3l53BF0QKBvxgDW0+52a535F0XCopF2hFxR51xF0ZF0R2pZF2VF34TbVF1sBG7eIZh284nlF0lvHpF04PZ5SKaoX5F2Bh0k4lu4KzbG1F3STaS7qJBFtF09F2bUkhF3MXquh2JpSvBGNF2SO3iCGnHAnyGb/RRh3hahhMpjF3T5So1zIlEcDVQl7CDgmUCu4mIAyACFVWCsCAGhUH509I1hF2F4mH8H9F3a/bZohzUm1F0ihUuiyUV7DF0XF3r52bF3dtRjjYkdBYF2EDhbh2nF3zF0ZawcvDi53tDWQqyQWnR22rS6sMzo0Ev22I/FWWWXh38LVQS51IHqR0BR1Ql3w22yR2ayFg2xOsGgl3VDro21Ph1ofEdWz922wl1zS4/RHol2gGrE23AR2nB3WTwU212R2H9HZKA021N23EfEPHnaR2pmAHShBJGAl2LDGy22Ul1chLgl0YR1AiHPSEC20ZR29B0cl1e20ER35Za1jng20FR11A7oyhf224tL3SH0dJjREVR22zkXkDA20eR3EfGonlm2084gsfF/tVCVEtR3657A+z320dR22zlH3Tb209R3al0LmVm22h/4hGE3drr21zR3sl3/F0gl3Yl1yyFu20ol08l19JEP23uB0aua523Yl06jFTUEMl3gBJh21al3vZ6sl3ul1YEz6Dx3h1uzlJCw/h1WR1xmAO8K2R1Gl2RGEy7R3UGAl3yAnH23x22NNFRl3n21hPS7Bk9p5f23Jl0Jl0il2dlExl2pl3eR3xl0dhVwZjRl3hR07/b3hxRR2wl1f/Yd21ll2QhEs21Fl1v/bT20D22rNFHKJf23uqQs16Nl3eR1Xh1B16BKo2l1o4qIpEluJ19klR0aA5rbTbUFSl2VNEKl0DRz18HFl1a3WKl0uAk7/bqtibulql2yvFBl0wl28R28A7llHOl09iYJhWzl1Yl0Rl2yvE6l3+VEOl0Nl3sKDr23xl2yvFitB6R3Hl3DhUp/h7l2SR1CF0jGGXenjen7GCXelgO1HR3PR3dGB3l1enmLGAkoDAxEHR3WF1JA7SiHWNlyiEenlZ1E/l2Ah2AV13R0v7n2iFGiFiXnSF2qiGgV1vR3c5YO97mNlPR2/hD+iE0O1yDnkh3YdlAx2nE0uF3QdAO95sO3INaQx2BxHeF3t1G+F3KsEmF1nUUq5a9+44056O35x09S7BoTLUGRO3EfGEnnpO2rA6sl1Ex0RABvA4F2hBx29x20V2wNmVUGUx1vA7J+B6O19Gg6h1w06y20mO3aIj6I0L2TA23MV1p0o2O2Ox22zmCV0OO3cV1uGHAl0Yx0IcAih2F7Lynk4eA65T9A7G1E40FZO2SfGEKJ9JFBO2xzlaV2ix3R56ejKbukMV2IHKwDkbx1rVqrVyoto/RG6x1xmBKqAinkmV3a7ZPCEmV03uIX9kYx0ImicA5nsQvRGghxRh1F+KjUHAbIjRB7fGQ5hCVHi8zIRARV0Gl2VH6QdwRV0Q1Gq5Cp4B7fETfgGx2JCznbCpV0+V1eZnbF0uV20nkyV3cukinkFV2QpR3UHFx1g/FMV0ZV0u4nG56wDnNUHJV17Vz/tCqV3xV2qUhg/GNV3RV1cs7VV0MiFxw5CcTlV2qO1L9pRh3vuJ8Nmdx09S6FV3o0GuO2/F1Ak6tpwrPTgKHe52TV1ZF3y51kUBX8Gq42DB00ZHohFm50rV0TbA540YSGCfqW53zV3arjRtmi40L5x7V1L43zV3bV1zUkHV0ISHHMakJxO52k5wh5EnyEs42H9G9TAAhkN40Po0upxLBlG51nJHIM7AF3q531AX9yHPV3B507p3J50QF2YpFZp2j53R504iGRpziRjx53+l6gB0A10r53IF3MZa6nDP50Z51q6FlyFvpIVJGtlxS534F0y6HumxcF34Y1N0CXV3L8FV52TJGPV1N51H436B0k11EF3u42zpaBhCchHMF1nDnFtA2oVr41XJHN1xzV3o431AWAhH951nJGYEig13d519lxw2B0F1s111nqz52C1375wL53UF2O5xEUCA11s13MLp6+Hv50l2CHBEN421l7R5yYoBq7H3V0DJEppps1ne50R8lUF2uY2kZZUF0353p1y/V3Q42WMEapxG12r52m11I12b51gsEn50gF0qNAE13vV3J6GvtIAF1s105i7AF0vV32dFwhFA12oZZHrq7BEwF2JpY+11v50J53Kk56JRD52yWyIpFtC6o13khbYl4p5wKsoJ8E553NJHzaiM11Y11211PV1W41l518pzXGR58FE12/JEtG4C13Fl4llz7BnN51rJEZ11o1l011B5yRGxsF0sY0qNA411Q13fV0MhFi11111YEwCF1Nl43l1HE5sSGiF1iCHt11i0kwwX2RAvl01HmWhn4DGsSHK9LwO2D12cSHXR3Ex7eSE9oVovZ4DFOIlYV2KSEz1217G4H6uSFGF1XR1912xmBmSGAdkepELOxWF0Eh3YV3O0A4J47oWYdnoV2lnlwx3+F1UxAGSGA3H5ImqpLtLBMh2Rawsh3EwW910CO2hz7slnrtnXF0ISFClIRl5tF3j5xItTNUlv12CUC3BFjF0feDsV1N0A/10yl73F3SwmZ11jF3U9jaO3412QN0lF2rx2F5zYhFjF0FF0DJHb3arBFv129TBwN3HF38h2YN1iYnTF04N1oN1gN1KWwih2p/lxnDIN3dF3x6F2uZjF0TqAkN0eOL7yH4N2Sh2kN3xGEsNq+wFj1whmDvvFf1126ES3BfF2rF2zpah0BFyELF1rF0L6F81kYN3E3xDBkMN18N3DcyW53P4aEpxAgWnUkSN3K12F13YN2F+1PUWC1kYN03VSxF0QdAkN0hOjPOLUN1NF0B0W6N3neL6N1GZap11bfFewDq0UshljF3o5LANxjJGaN36DJ/x2emkztWV3W8NK1k437F8yExk3BYhpTniHWVMFPpXMyHeN09MGRpV2HHDZgBN3GoyQHFNjn1t7N/JlMFLHF1jkRN0AgTqyFJ0pBMEAFw9kDqEoK4nC+E1IHWRkq4lyUDrKrh2lvCgRk2eN05N17s03jA8e4DY3fwEa240Zx5NTg4r+N3St4XpVDNneN3yh3xpXRYVVN3vjB3MrRYVhEpT+6TED0bAAHGZN0bqQQsKH/F0/Bqt7JcHJN0vsC5N1et4hcxITnp4nVN2QIZpTlpJoah1jN2myFNN3U1VgESQHHuN02DyrawfpzWdBcB3lv4KzQz/ExN0r+HCxUcYWBEiE25kjwweApN3J4n6jzzEAuY0TN3KNwuBwFN2oTYL9zpN3DN2FN3Wgi9N3OHGZN2f/hkXSnN03VzERmdN0HN3yB3FqA/N3RN18B3vN1n1wJIDhN1EzUtvRuN1VV33N0UaCVN1w4nXN0ztSwt2cTZSoXmHC36jLN1Qt0BcFDN3lDIAB10foXN3zN1wt3q8D7N0JIArN2UOytohhN1kTn6oWWBggyHUhpBh3iqwh/i/N1BMEkt3+G2yNxnN0Et3bN2vN3aB04t1LN2PN13N0Yt1pTnzfA0t0ot2PDHst03U0hB0tN2QY21Iw8flVXQPN3EMybCEyKCwOpot35ZbCDhYFh4t0jSH/gp0t3vjBw4nsQoxgFMHHBN2pflrN037HhN1Y964t07N2opFGt1ct2BuFuS7hj4nN02DzwTmpfnat0/YkMyEZfmUt0q2mHN0FjAr6wGyFtN187kVjrRpzMt0YyEkBGdjgZN2TJHgXTyt3NEnLfjlfkS6RLNkPjkNh13MpZHG354JB3et2/px/HJXJHLQA8e6pOlVN1725Xoh+TnVsRFSG7HTGt18zZ17A1SEBpVMHHpt0OvbvYxKopIt3zZav3SNN2at2R4jKt2fN1ZCFRGhct0/8ZFSGlt3MG13hnKC5tSGvQhMt3Nt1AyGkXrrLjlt2zSFOOTjNiyopbSE/0XlhSQEoSt2tZZFt0y2knSFTt1Mebf7EK4nMG5l2x9HExN0xPEht0bN2dB00WIBt1Et1VV2OYAtIJeN2at3XJi22qIt2Dt1dt3MyG6t08JWEt0bt2tZY/pXrN0ipW9B1XZrWt2WQQV4k2YCJE1MHGet0/ZaZt0Lt3J4nsG5NxVdN1Bt2kwHDt3Ct3654DCrbt2shItCHTt0W/El4lLt2OchiEp3SEjCE845qeL1t0dCGQd3Ad0od3zt19N0jN1C7VYEgzt3E4k2YBPpUgyF7WU9S61dSwd0hdw3jlLi6od1Jt257niIbpOQDt3QyH3pV0d0B7ktE2UHGjt0cDmMxUTt3kd3BZL2t3f4pRt1Li5vt24d1Mhlsd2kt3ct39A7b6DcfWBt24yE6VCWpTId1Li4Jt3ft0YyFd21lt01LnQd0kd3e4HjtDQTmtZYEd0/Ym2t3Yd2ykQmt29B2qd3nt2Gt2Kd1tt2GuEdCFyd0nt30d3fAGWd1Md3Ot0Kt1XSFft1kt2YpFcd1Xt33t2id3SPxst26uGIpFCd1Mt0QlLzMHWo3id3Kd3IyFSd3IyD1t1ZZbAmjsd0at2LSFR4zq2A2d3hd1Dt2Hu1Rd1FSE59JAd09t00jVbt03G1mooMLTMS4Yd1B/F4d1kaA8ep2HF8mqJzkGpKU4Icd2nB1womxd35t3Jt2Qe5qd1pd24iGpt3lHEjSEbhqhd3Vd257kkMLHt1kd2nB2yKiBd2Z9ycjLQiF2d2ht3BB1JsZ/t0yd1qS7GQQ2d0Dd29d3Zt0p7mWQhklxJd0xCE+Lxld1wzYjSEtDqJd0Wt35ZaLyyEt31d0jA7cd0Ld0Czmu4ykd1Yt0xCFh1DLt2Md1vA5nt0qt16GEqQTCd07d2rFUAt3Hd3qfGmTqggDnd0adD8d2Td1vd17d1pd1uzkWGgA4k6d3AjAbSE2t2texYA5J3TLfFBd0pl2FVqmLHg90Zl2x1ju4lVN0MdCuN0fd0I91g907d1muL4yFNd0wcCt136iEg7moCGfkV+kFi5Y491OtleuBaJ4jqAswoCfnHNBk5ZsoYj2nE90EX55SFDWLdOo090QsFTmz+qAXZqNZ21oVQVgD2kHcQpmBdZZDWLk91+kESV5092c92M93toVzmS492Q5L890+YEe+0Nx4W4DwhUtTlo3xK7kSyFy93G8A9S78VgIOrt8HdBwaV0sRw1LHsnWeKg3t13MrgKGbd4SV02YCnwwT8GomKLh1a92fyFm92Sh2/PHO0S3WDy93G93uTTF8Ea90qN26d1udYpt3K92ad3ZN1290e92yd35N3e92Lh08VYwt1PKCcsDbSEyyHt8H9Airh2nS6raz38G7Qqfx0HSGhN3SQqZapXSEJ904i6pwDbSHR93h927PwtuCh91+jmZ93Vmx3p7UbAmMrF8GYVrN4G+90UdyZ92l2jW93ODW9N3u90aV2kVpzfH4nU+91GF4Qt3+93W93eOjY/KZ91heyFF3N90192GPo5yjSyF8Sh2nXv4L3SFx5oAyGoq42qwNS5it12nVJ93US5h91OnW693US4Z93IDkgDhcyGq2KmLFXGXiywNS5z92pLZSNDtS4Zd0x937qil91Qo7LSFK90B90ltLa91W93Ed0InC992H91HZbt91WLE793vuDxd2BN2Z90V+SNx1qYAv92n90u91LDykULq9121JpS5dt3L8EERBTIxaS76t3IDkp7ivzWON0bfUSTmoOlS52D421tb5Kpy52OY27yGEVqE13Q12lzZLMkbV3z427yEOUzF8EHV1PaG3F1652V9m1UL7V0j41htBE0jHV3ID3Ok2652bV3ZyHTUJacyK13ceEycCO51q10qTlQHqfyHu52H/GVUkO10hTntyJ4D1UD1IFa+10gF2yoqh52y40/17KyFx50N41K43AaVs1in4nsUUBl4iD3J53w13JaWCD2B13oF17O779xFyHx12tzYbFGY10P50aTmsJB4F2AeaFc4XLC0125l4zvlzFCU13511D4mk130F28zamD2V52750byHZFFGD0sY2H/F5F3YD3PdxwhHd40SD0813sF3DDZfNw612V9m3MBsoXS509dA+tmL51ec7AUor53wD2YcTNtl941+WCG52H51QxE791HF2sD3IDmf51hD3sQqZD0JD3ZD3610W5GSij3522Y079kpdxCD1ro14JBhtlED1iAk3wGa13CD2EnC3BnwD3j0VYF2ND1EUBFyGcD2M36e115Tj0LFtEZCD3SD31F4QSRqD3K50DtBfJqUhHKD31F58D1u40ZY1e9Zfar98HaD3enUv0BcF0350kgqu51u434Y0kgoZUmrD0kY3YgpUF3WD1vYhUF210YS9bRrJkF1l13enWfZCU11uD1fHBJ13ID0W4ARD3XD09D1qD2CF3hGULR2oKGu0nKF3yF2D9avD2x7E911VSBr11nF6fD2j13UKB0nBKF36IkqF3Ax2oKEkDQaF2/c411mz11kV1SY5iKFT122tAt1nT1mwj0Mc7wj1kCHj1mMDlsKECinGF0VwDj129WDyKHe0lH110O2H1mtIDH1ms8B4j3kqDUtyX12SVDX11dMBuax310wx0P10/D1P10XqUU1KA0nXF3g4oWsiUG1f10NLnxoVbBJNF2VN0bF0QKBAN13Zy8j1EhkKN2cj2jF0YeIvWYBD2FU7sj06wqHZ1+Nw+tll8YSV3KyFt50cj0/sDyj00N0GW2aj3cj3EN06j1xbVpF36j3Bg6kty5updF2sN0ZooeoX8j2SO356H61kSj2mj3BEksN1eO09dBtUkSN3ZTnK4D98GCN2WzalLgl51ej3uj2jrhn1z2j3XTnr1TWj1yO0tTmf51uj0vgqvqA6Ckcj1727Kj1aN3053SQpztnKN0S9YqCAg0kSj1QG4p8FmN2GPXZD0Q0nvF2fx2CO7xj32N3jV0Yp48FDCqF8LVLKFTrrpph11WETJeKGOzAjzIb4HpMV1j06CLzSwVj1C7HkekrLWtRTO3nJFxFMGmfg/KEpbG/jgWfETFTAPkdj2CyUoGkqtm2jjjKFCGmVrrCEludaeGDrdnhbGGCDVMHzj2/iWL3nlj0PZHDfEIT50bAVHxALUZKFgkldjpJIW3JACbHVeQ92Hh/h7j0nj1/0F/XgSYkLgkHhobj0qYlJrpwWTgNWrj2VbFbahPj2lw3uLqlKiT5xg3j3j3bj3XFFANUKiWlzqfj1KNVHj1MPmqoHNGEX/hC7Gqy1h7mRqDkYnngVVNhn1X9j1wT1dqmRwlvtYorotjzjKHjj0I9bnbHfj0xYkbkEUqBfj2SxHvj2xeGTj1JNXPj3fazAlE4T1qLaiGGYdoYT0iYmBzq3j0oT3APlhGTKOF9j02GnUT1LbEwT30Gl8QWPj3WNVIqHET2tj3WNV7j0ATBs3yCT25KHZNFVVhtj0y7Gvj2iT11j04lLYT1Nj0sbEZszIT2m4yVj1YLqBKF6fFdj2UPn8OTj96sT3m46TeHgQQpfGjYlM7FL9j+G3/j39KFYLoIyZTj33j1yT3gT2ET3XZkfAErLXUaj2T1VlwXMGUT26C7XzomQAj1X5FRabFkvgEjGT/igdYa7FGh6cLV7VYsT4oVz+HAyT067F0mY8Gi7j2uKEWV6WT28T2qT1L7joT3yKmwT0/5HYT1pYyIT1pT22T0w1afj5JT3QT2f1VgI00T7xT0Mvh0dY8T4GT2/1VZYmGxkmJB5olBPCAT78UqOZC0T3mT2Nqomwh3j24T344DFcpHdmMSWm7HtT2Jbj4qFRdahT0Zog3G2ZwnAYk6xnpphBCXBFKiPmwOLvZTCz57j2fJAFuo0qGzT2+0zZT0TT3wPkj3q9T1nj2xT1rT3MG3CHjftZb4BgT0j1UgT1KT5AEJjj0AT3GyAUqjjT2LT0nQ4idmKGkcLbzT0zT3lKGoKACcT3T0pKFhT2Hu0VjZr6lA3aYXBBCXeT1e3aHHQdT3N1VdKFb4AT7DAuS7LUiYlQLai8gIT02GkOLb/T2cT0oYleql9HCST1IJAMvQxT0vT0zugTG0bT01KERhRJyIJT0U+WK/R9qmwz3944XT75T3lqxQz1Ez1a7ElT0MYmpqnwT3/KFaIWZKHqT2NT0W3bbOI7VStT10qE8x7hT1uT2hKGnzAtT1mT2Mz1BT0BGm0z3gz0gz0Uz1q3nJjVjT0Mz3LKEcFSqfEuazs+WtNZCz12T36XY5KqzlgAz2S2mKz39nB9T1GYmsXZyUh6fE/T0Sz0wz3zcbaGmiz1fT0LT3lKHL5gSCUpKaYz3aT3GfErT3dKEmT3az3giUDKHFT2JRLAiUOz3Uz0HniAz1Pan0z2kT3vj3BQnrSxWT0xYnJmm0Iygz39KGGz0NT1Bz1G2lXT38z0SYk1LYQz3/KFGT2sXYjzJPolmCXxz1i2qQz1/eWyz3e4EEz26z3rT0qT0U+U0EnRpwYz0c2m3iwHT0ZKE+z3RT04z02z2ez2Zz0uz3IT0ZT1Qz33yo1z2EhyFT0ez13T2MT2Ez1RT06T0O3hRz2mz1BCUGzI7KGxyLYz0Fz1wqG3ygZm2Dz0NmnHT0oz2nKGvT2Hj0lz0ugXcz2feKtKEePZaz3wLXuz1tXyoODsCVdT3F2ntsaXfH2z3TPal5hsYmXKHc0Fyz21j3y5Vs7BHe07T1SqGY9xmz24ewGz0zNybSrbz1eYl347lT3qz3Oz2Pz2+z3rz0jzzHZW3jRwYkoGmtqnzDQRT0h2ntz0GyUgT1Hflbz3/z3NhEy5nPT3/flTz2BNUkCXE/Z4z2qfGHT1wL3FT0KT07KHE0FCz0oL0EWnAz0Zz3mz3+KFuTwDz0YL0cfa2z3Gz3xKHMT36gmDz2XhEcFQ7fG7T1N1bIL3Hz08RHwL3EL0IRHpz0idlJz1N77fIUFT2vA4L/nrj1Xj0ZdYJ+UqKyRz1RKGs3b4T21LWIL0sH46RBgL1cL3iL3nz3xKEA5Q9IU4L0wW3PD2x3bTPY8hJa9Q6ZDKE7EoXvsA4MAVZ1KL3DZJSBAI1BtxBBDB6L1AkEV95Fn4qL0uuhqL0nXa6L3NcAbkps91Q/aG4bscA5sAt5BIJA6qEqxTaL3rWn2L3vsCOL0LCCOKFmL02L0vZ4UV3emlFXSEZx/NhEcScz0hWDtFEhL3NXBhL1/KHCVxEcRDnmDIhv1zbakYgjhmkmQC/Vx+FEGh0IXZFuzy2GRL1cx2+n53qFSFGhL1k2n5L1gaJRL2ZL0ZIWxL3NXDBmmzj0Dpw5L2K+XVL1P1z1oiK+V5z1pL2Fbi5L3TmVx7knipzfbdz0bpxT8nLfYd2rf2GBKpsgCjKHxaTI1z36QKz06IVpL0ViFas762k8rm5HEwGBFmk/qEWSBLkWS+UkT3nKD/MDfeXVj2FVzaVRtL2SnDAlEFL2VL022meT0NL2FL0ePabL1d1yNL33KGqIUMaI7GVQy7FL2WMgwKDdKFMzDglGDL1+1z1XbCL3dVxjL2i2nvL208oZkQbfaFHp7L1Br4qkWPL2fHT3Jxf9ke46WOKw+G1L3dKH6oJpL3bL3Nfazz3H2Fgr2EXYG7mxOGAr0aYBUqH8L0/L1siYYr2zL1zfBGaiW2mLL1JL10x0SEBHL2jL2I3jQr0MOnhyob9KXL0+KF/rTUr2YXagvpkr32YiPL0Nj3dVxquhe3atXqc2F4r3GtDF2mFRjvFElL25L3bTDJT0VL2Cr0yNIIMm1L0lj00akk9biL0X6CggXe418tgDO3JqFH408T0X6BKr3StEEjGyr1UaF7MYjL3pu3UwnkbBAVTsu3KUGZ2EGr2cKzD628cZ6ixjqHgaErBYCT2pHmIwnKr3AlGDqFPQm7hZ2egW8Gf8Lh2GWAVlplaJR2dB4LZzd4HO3MtxRqHQ9Y7j29KxvQmKRLA1DQbn7ORD2EeQL6AUBqHBjrQfwtu3QaGAToqr0//yJam9DoWr3ZgW+amz3LKyW28EJr2+r1UJ1163LeYiT2qr2OqGleYytwDO1yr1tKzJT26r0aUF3sHkhxIu1Gr2kCnUz0XywDzF3sF7YhMu33iAXaG9DGAyXZr12r2cUKxbGOr0Zr0EiAar3Jr3h2F/hwOr1er1vGUuSRLbHVY0oaHGGG3j1Nr0SQ419pzr0uhpBBHTdrquRIu16r2jr2QJ0j0ikmWDr3xDkRr3wOH/DwuJ1vZSNsF/7EXMGar2kmWxWz853+r3AjFdr1TixKr2SCSNr35ixar15trYz1Vr3KrnKhK/SWGr2EaHZQWfr2mr3Nr1w053T3Tr0dr2yLGPr2CnBvGXxGClr3pr0pr0CeZpr39r3Qb2nr18blzzo3U3edq8Mg/e0KUkBkas5D9e0XDrScEYVTSp3br32OEgqL0p3Hr1wjE/AzNJ37r1vh0k7oWJ0oUEUb2tr3su3UwlF+KQb3pu1Gr0Mb3nbHcnFjGX4x2Vr1lpQzzGMEagb0QHS5CnzABvz3zr2/aWRxAlfoUe14wnSeJ3eiWr0zr0rLEtT22r1vGVpBD/T0znGwuUItrQfyGZ3mUnEtrA1DA+378CbXYSb1Gz119XmREQeKib3fl7Fr16HGAb2oZqFqGKjiMb2CFxOuXU1qqb2Kr1uqEA8CKb3mb2ojHokGsb3Xr1kjGEb15r2um22qG3r3Gb0Wb24b2BJ1vG2stDeyVwaFbqHkyid1x+b3xqFMgrhT3L9XmRHPCp6b2Gqzob3AipOb3y8rDAV/nExz1Ab2sR11izxp3Lr0IYkay69T1vr3WYmsM6yb1Pr1saHRb1Eb3kb2YoaPxRq8GVb0cWKAb2lb19qGUb3rr3Vr2S2Kcb3XqArr2tb1h7l6WBEwlMWK1r2te3camdcqvr06cIdr1yWLVb3dr18rnlb2ur3QaEluKab1Sb0jb35b14b1D0i/LkLOwgz3db25G3DomSb19yzgaH28qKb3jr0IaGtWIZb3Dr00YlIAVKz19j4Gaknb1qz3bKzqb0DWLquS3u1Jb3bcopb2Jn5SR2IPi6e3Ob2MR1EgZcAW1b3ARhlz2xb0aanQcBmb0SyDmYnZhiNr2+lz0RE65p9b2xqznb3LAhDb31Fwpr0XGGCb17b3Urkfb1zb2MR0vb0Nu3bb0Pb0Fb00FwYaE3b2Hb2sHS0R1VQKnb1cb2FR0Xb2bRla+oIYkHb2rb1UkrKrk7b1Y734b0bb0Jb3ub19qHI713r2lqFG2w/b0Nb2e5ohb0Ee30b3A71dqlMb3fr3WFqgb18eAk73Q73ep1Z60E72kb2bRlLb3vb12owo712x1i70pe1bqEpVSXeqs73rhGJu40HD2b2FqG+RUxb1vb1Nx2zb1hnHXqFjpq3b0du0Gakq71rz1Kb2vqEgTms5BdnFURGhu6q72/b1zomixGrb1670LQYu+yhb1uqFNtIFxyO70wTmDJgTG2Jb1273h9qCb2g70qXFvNC/r2W718R3wHXMz2Zb0ITlpzyoJ1bqFB70c73Eb3eqHqr1RJ1bqGp70e72FqGz04xb2hpSUmXJBog73Eb1fx1Nb1a72ojEWWRU72F73zBom73Br17qEQ0Ew721b2173dp0V71k/pxr0l72dqEbgTUZ3J73r+oQ71Fr2FqEPr3871vb3eqFIvpTr3E731qFrriYOkj73eqEib2er0IuKAT4dO4j2HNyyVQnwMDtjk972C3lWMbT721b1T73ZDmVb1L70CGmRb0KL1vB3l3bUZpSaHfiaxjCz9CBEHe8GzTDZ5nn72qbmkW2yFm4kzqWCX73la1qlpPazF5C373khDVGmzI6UW1P722qFiaFW6yn72SFmQrQX71f71q+2YDDVsTLzBv737NBgH36FCP72um5Cu6zZ00anmCrlqFoiwFx2gwqcqGC6C3W3ijlsGArqF9lIWW0VomQaHh8GKW1/lpG15M51qW2ajm5dYR+1LmwoH0syE4FHIH2PjlhFicOk4H0Fx2A5hGOmMH2xakXb1t0G0H19qEPZrd0GsH1zqEur3c50YH2TqE2r2o0bkzVh5qQTk6o6tULM71qGmTWya3Akrk6r0UKBP2xyH3852BA3GNVh5rSH0G95hqyy728OnYgTpW1CH0ar0qf7lFwM70JZmcH0paapqEcH2UH2xaliRXz70mH12vG7720H0K70u/ov+04SpOx1hjQJZm8H3iKYN6kSH0jMChal+PT68G7GAhW2H5p2H0VeC5uAvokG1Ak8HuH12mmFr0RH0cS4n2kEH10x2RH19r0KH2L/CRx2+H1M51QMS4aFnmas8F15ZtW3W702r1JH2RW1IZphr0kH1k+i4aE5GlBWCxW2lH3iH3Ujzv4qlH1FH39myzW0ITmYb2453ZW1hyaz6noH3iW1opqpH0SmyCH0JH2gu0GH0lx1i73j+1iloyYCSr2g9byUIZ+mhMItvkZyxNSLhaFWqx8sncSlKkj6aFzH0V5aelIyAitImpXHptJDQml83zcmm8jLwhSokKmmmNJ7H2NaGG4XJlJbH3B9XVck8vIzwQ1aHOck1TLYBJOokFcm95zw7Bycm2xLB5avRATH1pOlkG0Y4rlAhLH2xaFfH33FGGNaPaHndFd2g/H2kUFAn1/0EfInWaEY1CdMLsLbdLxV62qdGLH2Jz4PH2f2z2zEvH20FbdWiT5xyQklcl/H1ycmtUJYvlk9ExSQgn0vkFdFBwGwRLaTH3lq6bh0ysytIkKRHzpyqqX6aHhUj5q7NL51VTHH0rzFHCRlYAwn2QpQXH18/jNzy5XE3H34n0Yn37g14G16cRXH2In2l60/dEIn2wn1NHFUPiaoI1aGL3FZJzQn1SREnH2Vi1XcD7H3BXEI2HSn3bH0JzFin1udbeL4bH0AIxrH20C2gn18n1qZHLH3b5b5wDmdxzIkbH09Jz2zHLH1znVEPzNGEGn1En2iOy0n06n1TH3uvrgXhUn07H3UQwDNp0n0HH2TBJg6rMn3NcnmJJ8qUyn2CvlOn1Mn2Yn1wn3y2bKejPIlIn1Wn3PH2xn0pZWPDERn2fH3xZ7An01z5fpFfO42/rhaGE2DSb5HC7R3gWn0tvlfFa42qzH2xaETFb+n0On1pyHaEDOn1kn2dvnkAiUn0an2tzZBr7cn0+n3FvlNn3Rn3X81yG2GALz2rsn38KyJ5aPC7Vn3qMh7O5qtjen1WCAnH2TjaK6ZSRH9hGlO7w7Ckn0cn22vm+VU3G3Jn0LvlvTrMG2Jz7gPFzO6dMIHpEdzFedXL4pWNYZn2SFAzn163F2XHjn3B3SEXGln15YH+G0An2GaFrUX2n27kROuWk84VkSrn33KzXn2Pn2a4WmaGjc4kn0ln3+aEhUhu7Ahn2pG1xvbNn1Xn2Vn0rn2YcmRRGM1Viaqcomln1Orpbmhnn3+aGxGW/n0EomTaGStbRJjDhH7n3wsGFOjP1bc+kY1URDR/n2Fc6Wgo4X1/fYHH3LX75n0en3lvkKKKZgjrH2Fn3wX2Hu0Vn14X12Qg7nCEn1uaEI5SXn01n22c7d7yocm+9JpaF1n1a7GEX3Fvmjcr1n2gryZzEZzYDn199z+1XOZUsX1zn3eaEj6oTG1Ln3eaG/JQ0X0Sn0y1ULn3sn24n3eaGvn2Tn3WaHYX3e4H5z5gX3wdaHn24X25c4gX08n2mvlRcD6UD3H2l63IB7nISYX3Q6GWX2ftzP1bbn2mX0EX393Lpvm+PYYX2IX2lzEg9UoX2wX06aEhKYA6HBfGdyHCkgjn13n3uTnmELun071b7n0B5rhn0ony5zHZBrOn2k0Q2X2hX0SX2on2RDbIqwxfnOckG7xDeoGX16X1eX0vz6yn1aAEkX0Qn1EzH7+5mX0Bn1ZzZ8KZ2X35z7tclqDYU5JARH0n3Vc6OX3aX329XlvmuX1Pn3u2SGX3qCyzn02n2fDaZX20X2GX287Dj94un3taHiX3mzGcX2jaEriB9qm8X3dcmxX3hn1VoBxRGRDYQX0Kn0rzHSZrln2DBlFX2+X2zn24n1Au5dUUSX1dX0s+qiqVfn39aGIBryDpycm7X3jpQIX1+NazaHKX3DhFGclM9UlX211ZYX0SDIiuROonHaFfaGn7JtXEU2AbyFyUWWdhXIlIX3dg1OX3+X1vaFcHJHe1AX1vaEM+LGfktKHuTmWVUyX3OX2fX2BX0DX3RX01XHat4rX2HfFFHbJJ6z6rHLbnH1vaEyZWceG9X27yH9X1AREmn3fyEsuIHX1pyGrH1mXG7X2/0gIX1WzWUmWcj3sX163Gln1mTwDn2E32pv53X3Pn1pyEWgR3X0XX1XyEAZ5hX1s30mD3DX3033+aF6AjKn2MX22aXyn3eX1XyFhn0TX1830FTnjX1vn2PaFDrTqn2zX1Wm3eoWMXG9n39F7SQowxAaX1EzFnAg/aGFX3No3NVaRXEA32qO5A306zFdX2a30Z+lc32GF6G30IuXLH1Y92iKEbxpZYBqp3dpCMDmO32rCCnRBuL2lg60+HJ3Ee31jlC19bEPG+31xi5TW4v6DO305rAcsDe31O32Y3TJjAgH1HUCAMXEPHrDJ+32DzYB32FrB5a3B33x30u32/c5x330iAOYSe33kV1VFbM85Rim3pGI8QmW2vc29aHF32uW2l33jaEQgwyW3nc7IqzkLb/oAlH3g1VoCb7LYN31owhAu4HjLLaHl306j0itRB+lN75KHHeaEhwSoLbV30V30d32ELbD330522X3an1d32WzblX3an3j30z32SVWI7asYD931EdZZn3wYD54CGX1g33HLbcbDeH2fDYydqemWNcZ+1yRDb2OKHiC8FzdW3nZpbH3q+Dmjyb33731huV5oqb32MmnnE5YcCGX2K3EOuUViHJaXGdwzH2HiASAo6j2z33130GjIWW0dtbImmMtYKoKXaEU5K5mVhLCjaHXNxD32XDIV33exWWXHz32jaG26Tgn1DDBq0CjaEpoJuRFpgzCOjoP2333ZpxaHE4P2Y3AH32bFbJaX+VpVXGMUrJH05dYImnf30r339lqEP3UP0130++o5XH0P1wP3iX3VLbT32vX15FpJn3T30MzYxsKo7DwYA0P3/ry930733+W3IODgP0H32HxCjaHMX1sP0j+C5uCjH3uPZrUpr0GTo1YNygaAELaQY3NNk19A+tacj3qP2uDFsFFKP2FpG5iRpTmIEhXn43RzbeLzN3StlViF9ApKtlNijGP2MfhpTljXhjiE6P1upz6jzdvEaP010HjtCnqyFpENoCI7buP2PwXTo6lvjxN3u2nnz7OfL3FHZjzqP3hJonO3v9xkplAC0bgpqP3L6HRP2L0Er+ECvF/fZVBh3t3ospIPY6n2aP0+P0Nn4bMIvtytY3ZP1vfmT5zOP3DvZhz7/Qo/Yly+IPiFVSSFP2eCkK6Frn12LaQY1x6GIn3hZqcj3ytnLz5o7zFt3mP0vz5tP0M6HWP3zz4NTh3t32P3zz6Sv6tHEuP2m/lVP3gGgNn7RSC9mR5P3Xz5xlJuP1N0rFP0icoPDmrN3e6Gw8WTLbdP2ViRoNwpP1mP3euHjpxOrwgt0oClXn6zP2VdYQh63pxWg52HFNtw9iGjP0GyEXP31iGQjDNeacj0NP3bITeP3VP2XP3OTrNGGhP1xP3TwRou16P0zpw16HMyFGP23pymJnj96Pjw7P2PcWBeq8EobP2/P2OabUY0rP1fP19qlFP3pP0MEh1P3TP0+n5PP1pTlOWTXz53P2ZZkIv3dYG46FOpB/0HeCW1plVpxnP0BY0a5SDiEoAGbu0/P0ytYPISGP3qP0CWIme0fP01P13xLfP0nP0z5x9P2QY0tP3P8XIv0gv1nZZcv2Qu1YY2V5hT75ovRa7HEY0s1hT740gTwv000mX770v3Av0oK1eVYmRHlwo/YnCtlVpxeP3RYUDP0qv34v2pP3stmM1EcGzf7EcxpT75FZTsRlXwUav3EELf4pf6Eqv1DKjRYXFhpXn6TNyKv1IEpxP1D7Kau2RP1Mv1vP1Wv2DlaHV03DGmd1cCk1P3AVCRez2v0CpkISEY4jvP0vP3s6GU2jrd026L1iGRPT8v0rLk+v2ev3EtkqSzj5weZjdt3ev3J6Gy+wq6IlLkwGG3HS4BYy2kkYUBJGWv0y2nmv3rtG6v3qErvzmK6GXSjR2n8tlLtHlv3bP0kk4bYWUv0HP0y6F8AZ3t0PbX4100v2xP3G6H9tjQkDtv2pv0MBxOv2sv0JJFjEocv0EIX1AXsv2VN3mP0jv1NP0WcBGpkDv0sv0Z8bRE6xYZ9v0Rv0y6HUSwTG04v0y6Fhv3ov3stnrtGav1lP1V6F1v1ev0kkLzv26yJqd1Sv3xJGErqju3LP3J6GZAZev1pP1plwlQqSe1ZP1zJEjODV3Df7Glv0zlyewQgyHrDKzpb3v0nv3NOBnDnXv1LNm5v3d5z5v3+v1Xv3xfQEv0xv1gf1Av2Ed1Af0QXDQv2eNyFv0b5iDv2H/HIUDfv2Puizv0bWx6E5wf2Lv0Yv0I1wbAoMv3zP2/JEImYEv0jLlgf2qv27v1kf3Fv2JP296E/v0+HE9P395wfv2pHElJI4pzPv3Re08v2Jpa0f1Dv3T6EAf31P13v1boA+t0hv1j1z/LjRYU3P1sN3X6EgyEtv312BJv3/P0tP1Sf1dP1jv07P1yf3If2iv1WE7Yf2+d2P0heVbO6Hif1Kv0CvFE8FSzIUf0+DloJjwf2Cf0r6F/9QZm2Mv1a6HW8oIe0Wf0b6Ebv0Zv3G6Hes4we0pwCUYUr6F7P1W4lvv2J5JkZ3KNwaciWpaOCQFv1Ev0sZYXUZvNlAf1iZIPv2Qf0i0WlvhARnNNlGZb6f3f4ohf0FDGrv2W1ABf31koEf2DrnJE4pf2yv1Hoa2R5/JFdv0wv3J6FX5pY8k2f3f6Haf1aP1kpmoHno8lFf3kHkVf3hf0p5x2f2QHGz8Kl5wWnnfP01f0qNASv1MHE3P385xuf3dv2hDnHv1Zt0df1/5V/P3df1kpzSf32f3J6FrErG8GVf0Yk5bP2gf0+Dlwv3tf3Rf1zf2jf0+DlTjxLP3hDxWE58/hW6Eqf2vA4/JxhXB8Llzv3MmHCv1qv1gYWi9GL6Glf3G6G2v2KP0mf2CsD+P1Lf1Y1yVP3Atls6H233Bk7l1wOtDkpiC+wqU5FBGVYVjWi531t12ff3Qznvf1/zACVpU0Bv7K1xDhL56HFaWAO8wt5AA0B+tqi9BwrAEX506HA/3Uio2VD8NBA/1ff1w/2KFmBv2UGFmNRQ/0I/2/LCQ/3Nj4b/bwH0oHmugJW6FClThWAtpxa6T30Fk/2Sh2X2A66GZ92bCwqN29TDX6EpyErk7kkhq6H4v0G91iizkkjj5zdYym919ITk/3413M/2Z90u7yMN046C6lj0/19Gii/1dxjC6FOpUxDgN5yv5Zu93BKQC/3vv2aP2y/3K/3nv0TbEYPbq/142xupzk45UVBCf1SzLF918BIgU6f8ngqyv90ibx8f0dzac/3bVgth0ppG5P1727biKoZZKmBm/0tTmjqz66HCf1G/2vwh3p7R6FTP1rTne4Bj1xeP2c/0i/1of0K/0s/38/2M/0vnqfLZq/2MN1r4Cq/1a/0x/0FP218Gs/2FF09oCewRh/02/3j6Fl7pM7bsQqU4pD6HOCk6CkMjay+CF6F8AYH90Z/3F/2G/2Z92lvAp/3azIu/0O/3lwqF6H7LL4SFkjgZiDl/1eGXYoouwjF/34v0H91VQGF6EgpgF/3h/2SN0GDiW90D/076Fp/2Z909/0r6H3f3j/3kjxl1xGf16Lbk47XrKSN0+TBK7GoKC0cCF6EBaQASHx/3/6H4EJkF1b/33paOCRG/28Bj/6HVwqzbFutgnED3pYV/12nXf2TgZZSOpR/13DBDwz3pZd/2V/32cSZ/3b0nNUlK/2MN2ZlV3/0D/1yP1M07qcFhGGF3l2MH//1sBHQlVGGFFiT9KlcWgBl7G55bKkhg6gTJA/ELKlyGEp0qpGGAqoislNcKl8G6mBDwyBGFIAOstFU6IPKloAMcvEoAN/gmAAN5GHN/wznmsboXNHo5nqsmgsrQhmaOpIqkjbxB14HTRANHYAOzNHlWQaGHMAMhvGSNQzyGF3nwhkFWLQMir1GOFzoiH52XPnk6G0yrEX/YWkAHxGQAOgB28AMQAP1NQ9l2THpcANjDLm4lA6bLxHXBrzME/WIAAPz6AmMEVzLSsmba43VzpaAZ8kk+FIPYhWIW8lRS76B3GANIqmjQ4mB36AMLxEIZQ9xnaANgJGXa5XJHqAMgAP4AMsAPE8nKGGuAMcAPiAN8eGOAPuB1Hcr+8meAOnNEs1DKLbEAPoAOpNTismmAPBB1MTL9KnsAMZvHM8mwANp8EHGCYAPKGHUANdvYCdLAXn8g474qH9EbtL+8mxAM5AOsGGuAPRvH/KmSGGaANTMGsNKXKkhg7U3jhZ7lAMiGF5AM4J4iGGFAPCtHfKmIAM7HxB14bpAZ8l5APRSCpxGdAMTKktAMPjiP/YSa2cHkCAOYpHKAYNAMVpIs14vvkKAMgyJSAODAOFxHGlY9l38KAqAMU7JKANdAP4eGqAMHNFyLw6AM4oJlANTx4WAMbGR6AM6NxosmGANkA4oqkGGGRAMbPajNIFAPYS5WAOHAPOHm2ANpAO7AMeGG+AOrNGbAMOAO+wzoAPB2TYNGBAOjANTAP3gCjY1PD0H70br7sJmGynIJkXRDAgNRHn7blSsC/D1J+CTGEvQUTGEsMkj13SQm711/r6rblz/kNoViQkgwUoj0H7kYgMIwUtmBSQnb/m4j3QgNWdDlEnHbnr/lhA6KOCVHmEO1711YmBAmEnsl9HnH12Ax2n11gj1+iEUgO5OqImGeF2mlFEV3HAkkV3WCFn12K61o5ZhhXpOKpxEoAH8h05OKpxHMz4ih1RhW7gkigOSh3UlrKTjKGFyGZyh2xhW7gkSgOygNCgP4eFZEapwCbNFdxHyUH+JSFF33ADdKlWGGpwxG90NWIZAMdTFDx0cAM6gPmgNhF1cLLigNJOyigNhuBmgOqgOFvH/b37yE6xk6V0cAMkvKbSkygMugNXxl8eHOgOegOJ8nyUEpNCuh1+2WYHnOgNYA46VAPKkA/7BV1cxqn1HX5DdviFvGZMEagMPbiigNv5SsGE+gNfNHhfiSGERgPCtHxxl8eGZgMrvHrxHyUH7AgqN3kxrSgOpgOygPmRpANEBgOvvHPKnKGFvj6rh0QtEAAOGWJx91FdLgBHyUFS14ON38gMfckCvatcyAVIpmHhB39gP2B1+B1SD5b4WG6X94yVk5D1kQB2jgNvFy7wj+MG0B02D4+FDJMHOB1VZzciK2DGLgMzVzrgPj6ViGG/eDN4WbgNZ9EEB196FZMERRk4jHJB2JZyz4WdmGtB0Fp2+B1lDRVmH8p0lmFDgMSrolB3kJIhZxVpEcB23IKYpEBVy1XmG6VxAqhmED3zEgmCB1vgNo8ZTjEjB3tZzPgNPB0TB1mJwPgNQGUaeHmZ7qcWk6ULB0N9EqlDzB1JwwHXFjmzbNEbB3RFzQ8JGB2IgZCR44QPLB0HB0cVyzcXmB0nB0emEQp3XB3PB3IQPSziIQN3gMw3FWcWsmGrgMAQPXNEXB3KZy0jRxMFMQPEZ3mMFDgOArqBB3dfTBB1NWDzE3f+1f1lr4V8QN0QNuR7sQMbgNkQNmJxrdJJB3SQP4ZxLXlDgOwZH7B3iQMG3GZB1IQNbs35XmG6Uy6zSmGtvgYglDgN6QPdB2jgOps6KQOvgP9xziwjbDFDgOI9GNB2zgMwNkqkiPgNmQMnVWn16hMEdB37w2DyhPB1/gNBs3uQOdmFAQNuQPOQM4tUpY12QPuJksZbR13TVWzeCt6VwQP+Vx0QzzB06QMiI2XgOG6VoQNls2QQS2DFYQNls1LXk7B29s58BQcQNEQNJQPHB2AmpAc4fsBGB0ceFU3HRQOUQN0QO4I1T4X3B3qmGUAxGQPFQMvB2/205lbLmE/XkzmEImYHqnAV1SY5NQPMXncCHnOlK8xzJnfB1z13UfZwWHIh0PZ6LJnBglIV2DQOjQPpkkjQNrJn4h1j11EgMSYCUcn3XmkEWlhCGTAfmBoh3wx1UxBDQPGXlkh3Ej1mXmYV1YgMgLDYWHlaogGEcgO310zyI+F1Mj3QV09gP533oFVB5QvNEjh2LXEDgOhMGhh0PcHIN7cVD6N20IDbgNysBalTAN2vQOCgk5h2PQOKB1qh1agOq6BPQPTuEXCr0JyAjmMmHth3KZx7/I4jEPQM2RpAwMWh3EQMWwgvNEAwN9rzEgkvQPQb7/jHdh0ds7YwPih3IwPKZyxygJmHowNiHA4wMt/Cuh0+pCVQMvQMWDDwwNxh2rVyfGzks30NXhKxuR7TlDWh0Lh2Sh3eFDmh2EZYhZxeaCCgkI7GZV2GR7lNEc32l91+WwWrHjh1hF3yWBnXnvQOSwPxwn3QNbNHtZwLC0AtECwNVV2C6AMBYeh34rF7VxqwN74Xph0zF2Wl6os0SwP8h2q950wP92IqN09l7N4UPQOSwjF4UAwMUKB0QUrJywdASZxXro2MEUn3ANzGwPPQO7h3dgN5327plNuXE3wHWH8e4huGRYW9PA8WHzfgWjYcLp+Cj8e7aWH/VaTSr+wN2HbmnaqDadXXqZltCr6WhDe5lwWxYW+MKnQnyCW8lYS1Ye2T9kG8uGxYUFt57vGWuGpYV8piiuF3SQ+nbC3y5P2oiYTwWxYUtEYh63rZhkG1kt6wISIUkhwPHpm25Kx63zlBQvVCeDhYGUG2jQXnplaKhLog61J1uEplAr5rZ61gMhaYU8TLhwNVwNynbiIY5wNTwM+nb+RB2hYQBFFwONwNI5gQBF2iZzxEaTwv63fgV9wO2CbT627kCFnZlthj619QXpZkccHdIQpwPeuEplCUTAWm3KyyrxFCsrcIK5wOhw1GlSC6VLwNaYVtNxFRikwnxvFeeUCPAtm2fwPDnbOBg361jwNjo46nbZxlrwOhw16iB1bITXUbP3DnYjwP9m2pwPAIPTvAxXX+fF/wMlwPBwMBwNbZTRwOONKRwNvwNbwMtwOgZm47AkG06BY3H5NqjNwNYIMUhDmugRwO4YUWTAWm37wPDnbLZgzG3HwPdnbvcQ6m3qs4cHYy05dlSQINZwMPtL/BwPwMWjZUIMNQnLwNMkDkINzwM2H6UxTxwNpUDVwMSTWqQT9kEmuGgZndwOfQnTa7DF4hK7fwNQl4KIOcNnqCUKm00IMXS1GHTBwORwOpVLsIOYIO4YWhCXUIMBwOP2B2Wo8WFw0SzQ1kIPBG0sINsQ27wPpLEllhIQ2HwNmG38ox5g1XwMQuE6lKpHZ6IPMIMUcG6Q21wPJuFDwOqeD9vDT62TJjlZn9wM3G30e5aYXqIMQuFMHAYeVRIN9vHXvGAn6DRJmG15xBKZke4TzuhBWE5pltH68MA+iktwNDH50IPWvG5IMSlB2IMZIMgphPxF7EgiGgUIP2WEj6wVINJ1LCWGsWEY0h7wORwP6QTaIM8IPGJm4VDPwMcLG4YXVIMKm0eIN8M1IKBLEidIP2WHykXEHG1IO4YVJkWHu1J1KZIP4MADqycm2ckiKINZlJ7IhALGapm4qUG2IAm2h/GhjYf3B3vjnwMcHYLIM1IMMINejbdwNmG2aIPjIMkINjINf9ITG0GINDIONDzcIOONIBwM2pJnwMJwPpZmqBL3wN6tJwIPPINHwMQGqpHb3IPXwMBIP9IM3IPrINKWHnIOFwNaYUnIMvwNAIOKNC0bytIMrIPmRz3m2/IObINrIOfIN8M1WQKFHDBIN5wNzY4woNgoOeZljq1bIPCINeWH/wPGWFQiz+WHuNp8JgOLFXwVA03lPydWFnwX2JkYoMlIM4dUjY5BIMbQmRwOkBnil6jIPZWG3yQ6m1MN50oNJF3/IMmVBKZlVXSf7CkoPtHb8oMPIOOrXdHbcoP0INf+k+nYhzTeIP1wN2HbMoOooOhw3IoPpIMfZBooOECUKm3wD4onbYoMIoM3wPpZnEoNqz1OVLHvFg03uYofzFwINaoOiuEWINeWEjwMQuGaINKoOzIPbwPQqVlO6NIO4YXSoPGWE2oPXIMSoMWoPdABuIMmoMXwNB+4CoMGoNiv1eoN5aiiuE6oMhWFN2hbvEBIPyoOgIMjUlutgDIOXINrWH4IPgLG4IOzWFIiSnINLPWH+nowiDINrWGHIOdWGeWFXKUdmigUnLIMSjZGHotm1AAi+h7Mu6kJxCCa1plb64loMbQmZINBLUUoNZoNnWH2iBbHGsoMKjb23YsoOcoOMo6yMDThoJm1UoOKZCUITxINkoMDoP6IOpVLsvWEPxjIjRoPNoNNqgdm32oOrDZMIOuoN1INqm7/PCVIPBKWAxrhm2FIM8LUtINC1IOIOBDZQ7CMoNWWH4Rb7oOroPJUnwoOiuGboM6VCNoNtoOnoP5IM6IOHoPX9w3IMdwMKjbgIPo8nxoMdUkwIMHoNQvXNQ7HoNvoNi+k/oNPoNKDY4s4IIMBoNKFaSs7lEzg1I8awIDYBGxW6HJhpOuGXoQlJI7WH0pnch51WF3oNLPXQYMh62boPoYMR6mLWHzlDC4xNoNPf1r67+IRsEAvMUA/3iNmEm5MeDUsBrh5EYNj+C2FBzZ4O3jA2G0YNxi6qJnEYNgbnI/2/67kYOgsD8sg/f3jmGzuZCKCUYNQrD0YM0YP8YOKFmsWFfWEBdpsYPOlC8YOcYPCYOhFlwH3/U1CvjgYM55kxDgwJErQoUUFjI3k/2sWHThoRl6IvThWB+jZLkXyW1Jmxs/1ejZSQ4qW35cbc/3WJnNWF5W2UUaina2oxXeSQxZlQg2YN9kUGYPSuEGW2b2mWYN+60OYOajZ6oPWW3WYN4oMoIMeYPKYMTAD9vC/l46YOuYNpzktWB+63FbBxWGeMLnW0ctYPH521Qq6ThW1YElyoPK4p5W2yRTdW0A45SWF5W0dugcsUA472iqdW1uVQJeXyoOxYMRzraLY/KXKIMvhn+/1BYNBwP2YOBYN800kEpWYOeYNBJl5ajWl6hYOd647gqJYNI3oOYNUjb4IPaYMoipF/1XKU2WHDW3W5gDWFhIOdW3pYPGDZngpiUivW2eoxbKX5YPZYOVxBkHEdYPsUHNII8GxUjb/hR9W2FOp8jZfgpEIpWYPycRUjZ9nAtW2iIkGW3gOkG6W1YMaYPhZHIUB7YNVYPQ4EXWGJXDdKkIDZB7IwYNtYOrDZAwKfW0mIgXYMmq12YNKYPhWC//243aHh3s+H+rUnh3s+GRrX2OF0AiPNW9LVDGU3h0KZwQLW2tri3mxrV4jHyeUqdGg4Nfh09jEytXKl66mBo4OstWSl6NF0N2GJrVO1pIrLpFzwkTmYlKmB6rWc438R0IMlEwBS43Aw05dFA4P3ADYAkI4NhjlBR1OsnU4MZDSN0lQI6YR1KR0UMmc0RgY1c4NErXALV6Yls4N50lVaxa41kR2uOF0rWlR3Lkbi2HvcjoY1cLKT2E6xApl5MWJ07lG0KlY3CR2m2FBvKcR2LDYIMkGM2yY0U4NOiWngRCR3ukDS2ECUhiR1VR06tXmLV9qGAc7OrU44MfJgkMko4N84Pm4NOLVh5p2AlBrU65pu7mM4NhFqR2E64MGR1mOB50l04Nbkpe4MirVealNjGotWDR2MZR47nIZn2R3OR2xdF04PR4Mw4PmR1x4M+ZzpLWBR0PymXNW3l4+gbM4Me4MMNKZ4ORrUp73vh0x4MAuh6Ymnzym2F04MxR2ZiV1LWYhoM4NU4N6Yl5R2oqVsLVFhqp4M84OZR1pR2YSWQ4Nfx3yR0RrVGIqkR2GLLS4PiLWlR1l4O15wSrVF73K4MK4OWY1DR2JFH6wnOjl9R3M+Ea4OtR354MKZy+LVHxpqR1nZzdMFL4Pox295zla4LSbcR295yfNFWBoj4MV4OzG0gtUH4Mt4NoSWG7IEYOzC73QUxnKrR14il9PkbQOnQV4imjPm7R0DsSNKqP4N34OZp6nR3TPliim1AnzMlzQPl3ZmjE/4MYwVsinbPlv4N8XlmjHH7nlOCGjEf2LtQOzRAf4Pf7ltMkOF2kj2v/nPl1LcEnOHlardWSnQNQx0Mj0XQOU3nMj0BF0TgWJXBJ2FigIWgOK2YmR51xzIEiSO3EtoDx1fO7EEMw55NjGVpZKO04b1OWS9SHkEPZx0mHKEEN/25agOLNqkEM9xybWrxH2uNFmjaQSCmO2HVrYR3UEN8x3fYH/2FEENiEOQ5ISEMsEMFx1JXqgdGhfwUEMo7aSOFfFasN1fh3xx2iENqx27HQV2GKEPZx3KEM92GqENeO0/73uumyEOxak5NjcpyJgPijldQqDxw0rbxh0paYaEOSEN6EMrkXCulNjADh1/loTqmOENMH1wZyQLmmENhjlR7m6ENeEOdeJsDYEfD+x0paZVjGtvmWEP2EMqEMpXDhV1REMGENU6L1h1hENIulttjUxpcH3cEOgk6rx0zqb+EOuENGEOsA622GGEP6Vxmx0TiEdI7fTjHolVmbzSFi7KKoB6x107meENax2mghG7YBEMuH0qEQu85QopKEOgo6DOmtEN6EPtx2CyE5EOFEPiqaY9G1EOVx01EO+ENeak6EMjENGXWLOkhENdx1cXXK2GVpnhKyRanr4OPVDdV3MpqLEMJEMRx0Zx2zEMpEP990cprM4MZEMGO2jEMuEPfLi5EOyF7gqEFEOhLa1QYPOmdEMFx242Dk2FnEMvomDHQfpxXEPDx1vZnIDbjEOK07CulvEMTvRoulTEPPEN9KRXDbZhDzEO2rmXEPEgixEMXEMdEMLJSNx1WrmbENiHDbEM02WLOmCEP7ENsdLb4NnEMITk1EO9EPnEMVz4NOnjEPWJofENf4B6EOZuCTENuzzTEN4sDAkPkaBF4P9uASENrEOQkOb1LpEPKmaxx2DgbAkPrgJJx2sNK7EPVw3px2sNLIkNPEMhYl+Vi9SFckPeYkiENigIcCBdYlokPoBAVx1gwbi3kUBEl5DTx0n8LDdZUkNtYl2lynENLnDmN38kPFEM/EPckNUEONEN54P9jJmjbjEOXx1mDZ8kPWTFLWaaJzF46NxyYhoG7QvtYGkNmGGrSy7jFKEPOUnbFGDENjRqipxPEPeqFQkB5OkGkOukMKDa6kP1EN/DZKkMhx0N1KBsD3tY2oGvL3ze7GkM0piewPnyXewOfcnvb4YYMhuG23Y8IppoPvcEjtgAINzoM61ESlSoINL8UIrAdgSIIN7jWJ/CKtzbIOA8W5kMibmOXVQIOutZZkMqoNtWGC1FpkPSIOFuGZ+X3WyhBG/wNxkNcjj1kPVwML0BqBCYoMHxzPQCJlKx629wMy1FdkMULHJoOip06jonoOSp3xNI9wN+Cq+p2PwqjwOPzqBp05cXJkNlwOONZV+GI7a4oPPQChlRbwOyoPktZ9kNToMcp2rkMBUGFIMlUDhkx7wMhuElUC4LpmG2eoNxhFnGj5kNYb4zSVou3FkMndXtED4e3lkOmp2KziQu0RIM0dUm3nyJ3LkM/V1VkOfkO1Bw10GvkNO8mzWYPDmPkNpp1+lBmG2hoNVp2gUM+oNvdWAUOBj37IO3tFwXjnoNHkO6nDfkM9kOSp07kOoYPUtXsqAEINmEhi8EkvzDkMQ50HkMYUMbW5fdTGIP4b6fByau2PIPk8HXYTeIMungduF7EYme23kOgZ234QUUMAoPk8EkUP8IOFuHO6GEUMfwPVwO08F4UOfkNEUB8ELVkNXZbGoCjkPyIO8oO+8modQP62qIN6Dbl1xmQQxwOy8nCzgJkMa85MFkMUOoUO4WEa2rWoNHkNKeg5f7ZkNm8nPkPWINpEJvdU1OhIfz2IOCv11aUnkMKWGGoNGZaaUMKWGuvGiZ1rHBbvEgIWy8nMsD+INOuEsZY8IoKoOOW4zIIwe3/kP4b6sXybu0O1JloNV86TkNALEJIOi8kPbDJINUoMeUMVoa0oP0uGuyIYp3XoPZW4IPJNoNV84SNzBG1doPDDYQh2BUPqUPZUPZG0AYPV4XpUNOoPIuFD3kIe3AUOFUPcUNJUNfB3yUPXCbYPDXNUpUNVUPelwddifoNgtUcUwTIOZUMJHWeUOUoPVoNO5w1UOioPn87oZKSe3AUMZNVW4qiuG0UPaHX36w5UNKWk08ECRS+UOEIN5EnI2L4UOqC5i+ZLUPwFEsUM4UPlMG2UN6UMmHWWUOXkM7UO6UO1UPSi2qpU/IPuUNrUMSoMhINyHXIKDAoNmi1UdxlUOAINO8mzUPhIOsUODNF9UPjkMab4x3AIoO9IMcNWdrJeUPuZ2hUPtkOUb4fUOlwO/wNUsFwXgEoNFoOg0N5lpDoPGdX0GxDUNzIO0Z1WaGBUMdUN0b5dUOpUPK87wsCUG0AYN8uGOUN1oOX6HeZ0NUPw0O+8kA5AXkOtLFkoMsNDsUN9vEQ0N/pHrUPzkPY0OJPAA0Po0PlehToPkuGo0PDUOj4WvUMaoN/UOjUM7WHOUPcb5g0NWUOBoOQ0PRe2vIMXwPG87c0PbUPs0MoGTpkMs0OxUO/oOM0OPChLUPDaFqUMbUPk0ME0PTUPMNVbUMi0NvdXE0M3kPDa4ZdXU0MSoPgUP6k440ODwPuUN0RFjkMhIN5Fn9NgSoN7kPVR5kZ1voN5FltUPKUOb4VKUMtUNFFk+UNPUNYcFM8HKqRw0O+wzHxZwK1KKyloM+f3fQOQNHEe7RUMlb720PI0MrJzi0ONUNvWwvKZo0P7E5M0NxUOcdVKIAXIOE0ObFkm0Ok0PGdWMdzK0MxIPIdW1b5p0NpHBVuEOghd1REUMZ0P00MnoNYNVgPJHIO/OELN4boO/OENs53UP1WnZ85IEY3kNY0PQcma0M9kMZtlA0Nl0PosE90NNoMZtnW0PnoPaWGFp4NUPt0PreCTkM10NWWET0OQUMD0PGckU0P4UMCRAk0MFUP5cxW4ruIOGoNYIUEMgQYMs1hqi7y0gh62c0Nci6apXsUHPgXGjZZ9GTvS90NXWBtkOL0MJUMVuHj0O53nmuHXoPn4Pki2AARzGCsYN+tBdlB7uFbWzvf1ej4f0NnuFf0MSYMRll+JwUYPf0N5a1fOGNBIkYMAMPfQMFVIQMPcYPNi5ftIo8DjFDv0MQpw5+AyYM/0PwMN8YOkYOJtboMPSYMgMOI15yYOgb4gbxb0M/YP3Z341ZqYPHYMgNWkMN9YMuYM7Z3J4JM7ac14Tgk6b47xymYOGYMGh0z4U1uHnYP3Z20MMGYO+YMGglrHDWW3UMMmHXsMNdYNy/180N1kMcMMgNVwMJ/kMvYMo0NNkMBYMaYMWk7NhqxYNyXCUb4Y0N9W1xw0c8Gr4RAbx5W1R2ZH33Wb5lkPXKDV3B8uH8UMxbD1/3sEW4LoFYNTtzuZ2qMMlYOAQnUuGKMPXYPyi0lQA87bEMMSMOzkM+YNNYNBNDguF5W0CMOhuHmMPeMPdYNysBYUN9YO8gADYOSK3jkgfRYhMNcs4qtFGBzjYMkvJYb44N6fLb0MOzYO+MNaMMfRY5YM08GkQ1GuGrYMt/0qtHleglYMzgllFkxMMOMOhZ2XHEUDYuMOUb4S7ybW3kMOUb6rkO7W0gbCOMMiFKYuH3YMuwh5FmdRAVuHSMMysHeOxyMP3Z1plKx60SumhMP9J6EuH9MNRMOE5zfkMGMNpABn4VFMMzYNGYOdMOJMMmMMukWzMObYMHsoAEV/FSL0GXRAFMMh0NjMP1MMlMOTBxkMM8MO2X5iMPlMNysDW0OtYPbMNWuFtMN1MNbYN/YOCeFlQgm8nsAMhRUaAPvAOieFWMZSHmSAPCg5jczs8meAM6G0wAOhAOvuF+mpEANfMPTGHJAOqg5AkmTMHUJygANAeH/MNh8nMAM/FbYNKkJzkANQxEbgl8eGpAPqW274l0AOtANKW2nKkpANPMNHG1zo5sAM4sPim0VAPcANy5GWzp8APYsOThh/kFvgmn4kSzBi5FPbFL9g+APTAN3Fbs9qvMOyAOJV7TUJjAO1FRmgWa4TjxHrAOUsP+rQuAPbAPqsXxERbAMbIS4sNBjL8GHHANjG2H4keAPYUZmsVosNPAPXAOAlbuCk2ANcFXesXCsNvAN/AOMo7ET2PMNwAO4sPdn5zAMEsO0kn0sMysOasPDDafglnAOGsM9zpYsMgsMPuFv4nPuHnAN6m1LvhQ/n3MOsUHxAMQsO+m13glYAOqsNcklkOICkkIsNFTGYQmSGEusOBsNyGGFAPOV7ZgOhsOCsPLBHDn5TANVAMzkF0QlHKnBsMxsNHKlhsOWyCsGH0AON1aNgIdAOGsPgRD68k2sMwhFUuLjxEZsPtLbuAOpgXiD0UJBEsMixpi5EVsNjAPaVICNYeAKcHnzAMH1aFsMaGGKAMvJ2BbKZxG8sOZsOoP5gQmlAPv1buDgmAP7AM/1YujBHAME+EC1E9LEWsNlAqnjUTsMlAOKsOYNYjsN3APesPdsOaQIKsOmsPdsOgQkMsO6sPdsOAQkysNbsPG7aVsOWMj/APsAANQNetYVeFJHmggMutZKql4wU3QXIEOnsNXsMPQUXsMqzA2cRfl0PsOHR1QgNZeHllF1HkqzAt8lL/m/4P9g4/sOAwVBkkAcMmQlUgM5lZbeGVeEnbkOlaPjLCqmgcPJlB1eG8JmgmHk3lEwU4ENXQNrpDjeH2HJf/kYEOEV1YEPEV2XQPqYAsj3zBFm/7YeGZgPcGH88kRgOgeEVxklgMWgPy8lksO6gMMEMUcM1xkBgOkcPoeGagPaO31GH88nGgOHZ2uzpEsOccOosOwnAgAMkcMTSkscOVgMFW2T2J3uFMcP2zotgP2gP051LzrsQkKgOKBpDVxam1ycNUcM2j2TeHCEn+gPScO1W0c9bdSkCWLOj3ZNHdKmBGHkcMAQmlsMJgPzEPyUFWRph8kxgOo1xXzEnEByGGCcMRWzxGFT5DUcOQQnqcMNgOacNSkn1xnhsOpeiiUFoPDicMlZSGPXugMZ8mtgNH32GxnKcOGxlKO2iUHTCg6cNbcUcsWBcMLxG2v3Z93BgMccM87wVx1tm2ecMdTFCkPyUGX6rqsn2cPSjSOcM+gMOUFVgD8GGCcOrgwAAMFcPOV7biI5cMicO9V6VcMacMPRjkE2MhkhAONgONV6Z4EMynBcP2gWlcMCcPzWI/F37h0PRalIJ+wORqBEViISWomhJIUD2Z0ym6MVzj2SCT6upIEmsihupyDcPFlw//DTsBJIUlALsQ7QAhgPQwL19DRSylLiQWfEkSL7SkM2w5wPzj1hFz0qXRwMwNXnyhIEkTcONfFUVrnSlV5lILWeSCWLGZdYB8oQ/FyLDnyhsylV3T3FEwT3TcO6KarwPqYmXAjmdY3G6Xj1TcMedb/cM9z2PIi3iV/zhkL3PcPMqFi34NYP4qFXcNxlFLcPSYlw8MfmaLwPrz1ncNfcPkghJNXMFwE3Yo8MfcPGdZZ4DkIPzcPv0G9mBmIO2CUViFVtZhXQCoMP1WbcPadaU8MeowlCzk8OyBXkz344BhFwdI5/5hBCUHoh9+GuY4ET0GvX9A0i7YRYP9WX3cOKALIZh6fEc8NE8OO0pn1yHcP1iXe/zo8nsIz08MyHYQINU8M4qGKAIE6ikyVk8NC8Mw8OE8MM8OzcPxfFjcMbiUpDTc8O68PNlHTjyPDGa8P8dYHcOA8MsBE6HjZT268NKBEGFCqfEE9gjiU8UiUyVq8PnZnsIOK8PaPGu8Mdz087x5db9VjcIOS8MDiV28OdT1ncPxnodIMC8Olw1m8OqDZh8NrO3j+zGTio8PjXBuA0QdgHT3wbLaA1eY5zcNt0nRiWFUCLINJKEO8NFc4tIO48O7lHWShe8M28OMnyB8NCLXFlyMnwKMg5fErcMVBFW8NiNX+3gGu218NbKHBcQS+E3VQk8OhwlJ2oVBGVmL4z0afF+BHT8yDoMPZGbmgyA0xcpnz39Izh1S1BGomjs8OKdB5BEQdg5fGi8N5BES3i7oknyjRBGZ8MVIP3HjAiWbgGQoPCHjJ8Pj8MooM0qH/WhD8OPcM4fHF8PINADIOsbC/cM18Ns8N78OYCTHtbg8P28Pn8MNBoL8NhYm/cNY+GN8MpT3TcPXDZ58PM8NlgAv8OX8M/cPv8OJDqr8M98NgdYlgCn8MDfGPtYPtx+7xP8Pv8O0dqZoMSHiYCTs4ET8M0qHb8MidpZ8MkqH2nBkoni8Mi8NT8NARqNoPu8OnlF5i6ACNeORaCWGuCb8O1sQuok5hJvT0W8ML/VzSg68P38MgCN+8NkCM8VGl8Plfh4KD9u1t8MGYxK8NH0H3wP5PjXCXP1JnwM9Xhj8Oltan8Nf8PUCOToNx8PwA0PuSwCOQ8NH/UV1RDT0iCOiPGP8MPZGg8M8PEE6h6fFRAIjtZyLy78OY8P1iXYryoCOncPMqFFu24CN3cPh8N2CgkoOZwzgop8+HIZjGfGGZqlPE6NxGCNAdARCW6COECO7XQ8BGaCPpINn8Pv8Mdsril4eCMJCWF8NWz378NePFO8PCz7ICOZTy08OzfEhCVBWT8CMoH5dKHAp7CCM88MN/V+CNB8MGCNeCOT8Ms8NuCP5z3yCMdk16COj8MZdaGCNbIOy8N5damCNqz3t8NgI36t7GoPyLXU8N2CP5COCfH1PG38PZ8NDcMZzyICNv8MJCVgzzZ8P38NBZxu8OMCOxCMMCNECM1/WRCPd8Oi9IV/X9COqfEIr6OPE78CmT108N5dYdCNe8MVfzD+GtCPaCNy/XW2QTCPK4AJCXG8O0CP6uoz+EUCOjcP38M0RqwCNgCOHPGyCM7fFSHo1+GqCOXfHoCMO4G2fAhLVL8Mz+GzcNICPydiUvGXCNX8PdiVW/j5CP7CP10GH8NQCOPtbIp3eCPP7jwCO735iCNb8P3CPHSH98Nr8OlPGWuadCMInD+CX/CMuOgLCOl0FWAFRYlUCNJe0pvjGfGG8O1NwjbLNCNC/W3CN/8OPtbsOxSCM5XrHCWYcSU8NvCN7+3MCNUCNb+2YCNtCPv8OXY6vCMrCP7VapLZBCP58Nm37jCOrok28N+XAK8OIiNsiMy8NvCNfd5d8N38PTcMb7BEiO0iN97b12UIIMlCOSJa2G61KViiNpJZLSFW6ECCMZdZPI4KMgg8Ph1QiJb0xx4YOMiMiEEqET5yXn8NyqkDcPEiNjvJXYPYiNS+2AgNI/ayNzlBJ5lDpjAhA1CfVSBDRcC2L06Ink6o6cAWPpa+35xo/+GOiO2iPdElYlXycDTLjW+1WiPWL02iP3J4eiMOL1+iPPJ7OiMOiNBiOKFlBUA/+EIjxa+0BiO+iMWiPTZ0CgNZ0GoOm1KUAGDZuzkA1zSihJxL3ZRL0scDpiO4NyH7Cy7bAxopvg1L08mTJL1zOqlDWu5GSwKBu1LcM9L0pdxZiOg712YMpiO1iN2lz1iOp5iNiNGTLViOxMCVL1lCPhwMNiMp+1FCNFiMdiMp+3pCNpL0DiMK4Hsb4dL34sajiM5G6xdGHM2/lGV3KJYOCpj+PAp/VNZJpL2VqjMr1vEE5wPNHG8JiBVGKiNQ1zhV4tPFiIqFVyTmjaLZFzzRwOM8qlCNDiOFVx/AwK4F9iOXiN5iNiCWJ8O5iOpiPMGU1YNq5FZiMcYRMxhd1w7yYO4GFiNP1w+vKt+HC8OFVzMqR+1zit43UZNVxJzpriMpZx4YNzqpd0T/iMw8MeI7i8at+FreKXiNKIQO4EBcSgr01iODiMbLzJVwYSOTiOyCMT1wCMxn/XqNAHiNx8pb2AS+FQkDziPDZaUIil0EaZiIOExYjGtDUSNcarViPv2wDW1pP67YNiipcigN/X0AzYSOyfRcs7RtBoSOFVw8SM84H1VLLEzsSOYTSwSPdiPS5EliOQSPw2F0SPaO1WNzTYM9iMK4FCCCaWGKSMz+Fi6hB7mZiMp+3Zmyx8OviNaSO47TNiOmSZkSNaSXPL2gvxDL2bDzDOKASO47jhkP3Al2CEgeG6m3jRU0hgjG0HkHyso6EmRG3dNwMiGCG2flxAdrpLGkaGtfwwxGrG3sZx+SPCeGevEDzFeSPMQlcm3uSPxGFMm24xWIcgF60uUGpzyOSOEG2Jam2SPwCFMm3zzlyMjdkMhm1+SkZSMULGnm0iRSkEluSMeurOGG/m09dYQCM2EnRSPBhSxSNJSMJdYAbpXJyAm01SPKeRbwOxvCYynFnEhj2HG2VSmNSON62nkHiKWZEmeSM8+TsEmym2DJWEsS5Emn61BBGgBRLxkhSMSQ5J+QDSNsm0dRX7Cg5GEVSNTCiBeH1SPnSl4zxRSN0m0JdZ/9quSMb63lXFrOSheERSNHZzlSP5UihSOHSNTkNSm17SM0eGDSPsQ5bSPij2TR2eSlrSMP62dm0ZNyzKhdSNXkFlOGlGH2SPcCzhSNPSNWXkLSM/SMmsQjSN3SMfzkQqgSoOGm13mQCAQBSPnSn6GQQyOTSP7Smy4RYhkHSMAyMWm3NSPQLm/SOGUOB60fzm9UYB61PQnvSPYUMoyPILn7gJjkNEm1TSk+WaPSPGkq6Sl/DDKwKgG2zqEzdZzCYgW30TazKL0yNrcOAyOKm1SykzEhmG1gyM5ni9SOjSOBSNcyN/SNkmoNpaLcMzSOWm0gylIyMNQk4aEMyMwyPHSNTSMsvjOqS8m1AaFocQ0hgum0dRW5eF8rinG08LkCMxUegNm3WUkfDBUyNBWHmUlocRoMXhm3EyOKyOFNqIm2raGe8RyyO5m0ldZ7xnWyN8yMZUMBpBOuWLb56yNuSOWHJayM3m3InDcyNPSPQCTRgi3G0iPWeyMLSPQW0PcMjMXiyO5G0E3a2yNByM08NtES7m0biXv5DtUOOyM8BHUjASbiwm0jaHspwhyONG2iBHa3TBfh+yMbiVjjIIoNSm1pyMuyO9G0M8OEyP9m06UFNnW+yORG2s8M6YggW3hyMIyNAyOSFBrwY+SMaUFEHbCyMFyOCmbBEmbG1+BFuG4syOfm168PqFqtG0XaHVyPNqjqyNi8NxyMB622BHLCRqyNcm2FyPuyOPG0X0FZyMIoPvigjtZv8rJyMzyP+IRFyO/G3LjYTQbVSNbO3qyj6oMxm0cdYL7ROFj6yP0RHbyPZyOpm1baHLFYuyOVG2raF+a1ryORyOcDDDUAxyNodZ6bAwyO3yM8BEYnEIyNjSxXyOOlgjSM1m1OEliyMZyNPhGNk62yMbSNbO1vyPeIMoyNKBHntQ5yOKdZKyODyMFT76vIKm19yPjO07yOCm1DO37yNbvFim125YAYCSm3KUHnyP5yOkaHXyNzyOsyP3yN2oOjG0WkbAow+m0FT6QKM8G3lyNfyOgyPEKN/yMWm0FyMsKP3m04KOMKO2m0DzE9iWMyPyyOLkFUKPPyPtSM5C5gKNZSPNkVu0A0KOlT7jyO1yPIobxyOUKMVODo5IbQk1BGQPUXyOHyMS+F20USKPAIXWcmbgFyhApyNXyOuF6aKMfyMH8Pn7rgW3kBEn8NWyORyPgTJCKNGKMX8M1yN6KOAdZbEB8KN3RpnyOOKNSyNc6rGA2uRgjyMzyOeF4wYQ0KM18OBfA0UOFBHAiKumFVyNKiIhKORyMI2WVyMTCxjGWIBpNyMvyOxKMTSPzm3FcXoKNVyP9MYAm3QW01CUgyNjUMHkEsVERyNiKOnSMHm2nkGzzweEk3m3it5xKNVyPms7/yMhm29PHsDgcKNxRG34o+GHDVJKG0J+29sgfm0BqEEfllBHzyMYvGNSPRLE5KOyyMh62UKP9KO0uGDKM9KOmKNGiOlNVAz6t1CpeBlRZa+1TKO5KAEW3R317a1f2B/izzKOMW3PJ7EEDjBELKOwMORRW2E0mgCcW3P2BzKN7KMwH1LKPLSC7KMsW0QH1+gJP9LwmnAH0nKMjEliHCrKOsW3ciVg8yBeD7KP+L03QNAG71xyNKNbW0u7B0BE3W3iW0/KPOHkVW35iPtxCMNGqW0lH0VvkZANgqNt32TjaRBFbW1xnWJBFwqMgqNIqlAqNa8MCHXlW2/PQWW24KPij1wqPHyP/xkoqPkKPOW0YqMp+0f7qOcOeW0K4FPyN9W2wrgS+Gzbqq9nBW3ASMpbThSNSKbJH1J3qMqPERGuPE0qMrYPUHD332CKN9W0RNzHiMkqMP617W18daryNLkM4qO2ITYqP5W3NlH+YALxH4qNpWJANGyqOaSIkG2tW28SNsoYNF3KqMp8OEyOdW0RW1DT4RboMGFQqMsSNyqOcqMjW1OBFIyCcqN3fXqKPu+J9W1HcQu4k6xYFSNCqPvO3kDghYP5W3pBEhWCUV5iqPJqzzWH2qOUA5VBHHW0yYDAu2GLglYMYH0iKM+qOSqMXU5cEl/KPaW1hqMxeEKqPvWzOYOSH3lLquSN0qPv0G2ZUhqODT7WSNTNWmzEeD3wD0ZPYeD0+D3xPaiD1B10j1bQHlq52fuGhzHFF1W52JzGED2c13HpUn3xL434D2gY5JD3YD2vz2W531qPqpK251q128J3RWqMD1HxHyRGk12cD2Jz7cD20D0iNYK2gT8HZqPEhpCD0Po2EXGiD1e10iNYLFxR51+12NJ1zqNQ11DD3r1YFqNh11xNb0GL351TD3DqNCj3YF2uNZmel6D1LD0vz41tml52jME1aFt53Z11L8VcIC2D3i128J3ovBsF0HD28J0YH6OD1K101aEnqO8128J3Rj0F53lD071ZIF3ID0rfZ+D39l4s8U5D3/qNJCnC10/qMZsxi13WD3v8DTqP/qPYgTxD1kD2tpyNqMdqN+mWtWjTV1OD2s1HPcO1D0/qNYaNT52IaO4aPX50W5G23aVD3G10PBElTllD2lqPkaMPD2bxG6ICZD39qOgqQND3ID0kYBM1lhD1qp27qOcD1qp3jtkzqN78AkaNg10q1FPkC8aOFqOSp0CKCh13wazWdWgPRoF3bqMbZ1YF1zD0rkPvqP6D2dkMrD1p11nqPNZ2l13mD1L8VEDR513O41MwAgaOPqOdkMbD3j41QxHSwlKaNM117jWwWKuD2fuEkYC3D3lD0CaOW12PD3HsOKL0FZ2WJ1p7EK0mIC6b1lfD2wcNOaMgZ0uaOgj1Wtb9gwj133tnjQNEEWGhEIj3KyDHtkwj2EgMfsPd1nToXleF3tnIj2RaOnsNxaPDoWFNbuhHYj2r11/lBxhGH132F1IcMMO14cMUj3V9Cq8WNBIeF0EV2HVFcgPP8k8gOhSF8gNewMiMBXcUXdJwhEcj2oraDtmRj3X81vF0Jj2YNb2cVn2jCj21hyij0taP2BHDF36aEjD158FgSVagM1aHjtkqj2HZ071Z6Cz38HjaOs1HKt5fF3aj3taMdpCkhENaN2CMHin9aPr1ZFtnNaMnUls1kYFTOj3Ea1qN1taNw1GXF13F3Gj0vcUHaMnIyKcNN1aSD1GN02j0CfYiDw8N2lh1t1awamZ8F+j2e8HXaMSj00ZEHaMLaMLJ1dcQWUHraOiLlyD39F0a1H1aNtaP8tag11A6PoH4maMNaMBlBDF2naOHiCVLgkl6+PSGPVu9B2N1LbwZkPbKKA6PfF17h3/x32sHUE2h9mUX11PlilpL30y335c1lgjmzE2n0UT7hKwY31tX3CT4U4ENn3RPnLLQ6zF1X0M6OygSlX0zc24yw4n2L3GU6NXbDGX1owlT5Bk6PmX0pr1ME3LCiC6PXZlpBD46NLn0IT56HELmwk315PlakIhj0g31DnkkFWdX32RHfTnOGH6328z08a0qX1ImVFn4C6Mxn2+amWyB06MCn3/46lV6IcD8n0fH1C7HS6MK6OY33BmlPRTm6MU6M+mlL/yzn1k3Ccz16a3sn2jX1b4D+yqocnM6Oe6MPoiocnbZwnfb+/zBEm5X0oaGO6MQDrXH2Iwm3T2BeEin0pr3bLbxGEx6Mm6PHCpEhmyX0SXZPGa5XFc6Nz7bwvyLX0Lr2Z6N3ywqn0rr0iXZp6OkX1tz3PIEjX10rlx6Nupy9X10z3gaSy6MNmkwERJn01n3kXY9eai315XZO6Oy6Oa+V+6MFn2TKEwEISX0e6PJjW+wG1X0KmkMXYD6PZ6MnfZGWDoYTp6Oh6PkpiiTIR6NowlpXZt6P66Ox6P7ZhG6PGmwm6NgRwmsi86PIb2WzE9/z6aE5n1e3YPNnx6MbMIMG2TxAV+QcX3l6NRgW+yNV6OhxAj6Mt6OZ4Be6Nd6PHZXPsbu6MKREHZUL6OTX2x2mltg5GEdn1572LzFMxSThHtcl36Od6MuaHpZEf47WQqj6P947HwZyyMa6MgE6/fjRpwh6Mdr3TPZQSDa6OR6OB1S2aHPX3Kb2tzFoGP2X1g72IGPKFioX1URG7z2igZHn3mRGVzEnxiC31RqHP44T6MS30AL1tQy3n0Q30Dl7BCCn6Pt6NB45MGPUGNHfm0GMq6MwRFRS4syyT6MiPX1hFv6NW3145WsGM6X3rb0vz7b9qQX0wREAsbRyMg32YL1/YbEGPORF/fZ58Tg3176MEWk8a0HpFQmWMC3Jfi8GPLhHMFXmzE+6OIC1YGP06NIWl4GME6OyGM8GO36MhLkLnwWGOlTy96Pl6NMDoz6NGGMDqN/6Mtn0F6Pie7B6OCX1IUHE/b36ONaH9hFeGPiGPaGMEWk/SAyX2KX1mGOX6MhGPGGNqyPwGM6GPCGOrX2qXbFcCNX2Dn0kWlE6MbX0Z6MCNVayMp6NL1ajXTmzGon1lfZlgiB4UaGPCT0nyOH1Y4GPmy3ZyPhX0EGNpGOrn3BX0WWmwGPg30O6OxH7PyMyGPefY36PuX3+WmzDJUGPlGMeRH0WkOGMI33J44nRwTX3xX3DAWEFz+GOL6Mm6MJVIQyMZGMNGMpGOh6O04REGMGX0aWkxGOOAJ8a26GPgGM3fZ5GP/6PprmrqPT5T56NcWmlGMJGN96OVGNn6MQRGzGPJyNX6NTGPMGM96AtGON6PDGMdGNNX0WWneGPv6Pga0PGPK30e47tGNYhmjn3Nr2XGNgGM+GN4wktfbfoi4X1OWk96Pk6P2RHXkISKO0X2AmOJFUKX3G314RFyGPUGNEREkFVmXFXKpP44iyxlGODGOS2mgmMZm1rn3WckuRFovJ7n0EGOMUFgmPVGOKRErGNwmN43aN1DdzH2RGNqqNGNEmNkCBQZjBRFfpFkCAtGO9GPNfbdukTGO40QYGOtwwjyNRGOBRFwtRm32UmOAXwDX1832ztE1BiumFX6NQNWimOCGNk3awmPf6PLfYArA9GPQmOCUBAGPgmMR/lZGPMGNLtGqmNsGPCwl9Bw7X3bhHi6EjGNNGO/8556O36OGmM2EmK6NZQnPGPQmNSf1KmNW32FQnMFWYckAGO/ICmRGVX2vm2NC4pHTY3G+GMapzPsazn2iX05/kEiFyREk6ODJFt1BqmOQGN7cmWmN+mO232v6ZP0MpT5h74ldKh33/70f4B1AHNRFIbiLKOw63iECJmPu30Z32kE4uMJJmOB31M5mTml1RFxmNOL0xmMoDA531uiOPfbIJQldJ+8Fh32H8DCeA5mMp33f735mOVmNEiTxmNeEAVmMlmP1mOwH06c5E/2S450Y5OmPcP31hGCRH9mOTmmCRHz304Wm9ZyoLat33Er1tR0CklC3Zk+g4Wn4IaELZDmNUL6gCF930dH1FNa+wEQP2KdC5L1HxIkRGjmO5GMJMLMP25L2FGNz32wP1HmNE6P7LaIP3Qa1U6NFuUb31TfbXULb334zDntXefZemPiP1U1DPhHN6MsH6KH3efYfmNX32qH2LpHnil331JW13mOa9mM1GwegMa3XmPf31aiQmWki6OHmMGWlKiDJ6PsP0SfZm6M5LZYP3UYhEREJCQnmN5OBERGpYqbmP931YRFi9lFuV4WO46FQSApmWQP1YCAgkCYP1jYxoWN4REvmPetb4P00WMAWPr1yECTwmP3mOemVn336XbSX69hFDmMz+2iRGIWPWtYHmOrmPaW0T8CUo5cP0AP25L1NsToRFZlJLW0uRFv6MSYp1PCKRHOebgn3p35AWMrJ0gWO/mPTL2qWNQCF4P2p3gKWMkWOJuUhqwsmMimOV6OoP2iH0FpwjmOnmPNfa4VA7lKEWNrmPvCACWMmWOWWOy0QYn2oWMxVzMCBI9kH330WO29Bo9mfmPJH3MCBm6MuLZpRLMFBERG69n/317m7pWnynATmOudBfFCBRGDmNRWP6s44mM86OqtY1ea6WM76MwCCRsZF+UsBBaWPkP0RADXMOioC7goAl0BR15WONV0v23iWysl18l01/FhUK3h0lWN/JDQl1V215l3iWBVCTIl2FWOll6Yl11WO9yEtWPo23VWPGQC4l0Il0wS2ZQgkl3bl0XOx0yiEl1gxF/+mG21N22dezUl3R23wex19nTWMBa4c21N21FexlWMpR3ft49Uy8l1f4CsyFMfUi23lWNLWM821Cl0brmXl1m21il0brl9l0jWlfREmzhO23pl33I4/5bVR1Kl33I7iuKql0N8Iu5Eluyal3Ll33WOTl37BVExHley620DR14xF27Ca237l33I75WOWl3Hl1Yex1l0BR1bWOcl0qR2wblxl0YrFttgM21zWM00Cel1vWOxrA+l0Q2M/6j+l1520MeVol2kl3/Y4cLoDvAjWMTw71cqFl2g2PE2Pn215l21rB8NkeR1jknj201R0HVbZyILWMQ2MM2O5l0urUCVRZ23hR1MxxxV3TWNCsrbUHTWNiWnVl2RkBPa7h6z5R0rWNHRy02PNl2praQANNl38LXVsFdl3CCBDLX82NBJH9l3bkkvHlK21TLWgsrr21XWPkWmG20sR2HoEn7Bzl1PWObmVs2POl0o2PG2Pn23rl162NHHm/WMcYEB/G6l1ml08YGjl0v21knY5TFO2NS2PeR1ml1RmMsKACxEEDlAO2vE0LOx9TGx1EHQOaw7e2Nx5FWNEp+AvsM7R0gEPTrGixG+nm1lAAO1AV3IgNeta2xGx2PVNWWxEEO3QEP6xFp2PuNlCXn677LSjp2OJ2Pr+BOxGyDmIcMMgMU3l8O0JaOF2PaxF4V2qTw312YEPnQO4cMocP4cN4EPE/HxVVyV00V0wo4Q1GRO2dewVV3t2MXOysV3lVLsV3d2O9V3qV0GW2t2N6O2QYjaO1FexJV1Mx3ft6B/rGO22x0G+yNV3pO1T2Nt2MWgMr2P0V3KV2L2P/W2RO03+xmV0WwheO272MhO2Ox0ANFnYCBO2b2O1Pag0HmV3M74RO3cV2E1bJKB1mmax1Md70NmqeCJgMpB4wFK+x19V0xVziDA1V2+V3ecOARyDV2b2N2vbrCFBO0DRyUNlDV381ahV2f2OnVYL95W21hV3rrbohW6206OUcvAQONCV0RcMeHbpCHL2MwONpO2Ox25WPvrb6Hn5sMGZnXdICsN7sNGrEyAN1sOOIOyHkJAM9xGZkns8kwsPUn5W4ph8lfMO3N66eFesO6sNlIMJjzgsNMONDzpEAN0OP6JlG0zIsNLsPGYN6OCZAM7yFOjbJbnFsOGWGGbnYsMkOO31FFsOGsM9Y61AMYsPdABrHDOsNDXy6oNaCbUsNVsO2s1vO6aOOMsP6H7VDAssMfNSJHYTmAcsO21kTACH1FdsP6jb4OOa04VyF5iBpbmVAMuAndADIKASsNjsMpYOK4QKsNTsMDHb0HiDsOIiainZcqUqsNZAMlH5/koasNg0mGWHWONMOPyJyYHkROMaOMSAOHsOYNXwjYCsnusNzKXCzghAP3MOkjal0Mhg6eOOTWHgXm/MNzKVwXj7flhsOsq0PKkosPzoOINHYsOBONvDbuuAGGFpOOa5gWsNsOOt66JON9sO3DYa2opsNRsOp64zdKJsOGsPFRZjAP1OMTpCJOPFsNMM7ubnSOONyGANDdANdOMV2pyOP9AOaDYUHnDAOFyUdONWGFaOPeDZbEC1sP8LXTONROOssP4w4TOOtsPLAOvQ6UNGdsNSOoDUmbnwisPbUkMNF7AOisMFDa4LqzgmSsMjDYcOORsNZOM3OONONzsMXONuHlJVBQ0mnOOrsNg0m7G5bAN7sNn4ERAPjOPzOMmsNn4MAgMTKMcBAdHnnsMwO2iw5CdTEqk3sPvsNetYEJGt8nZ5HXJiIgOD/lBaOSw6UJFfsN4MBtsmYgMV2Olg6sJG4JnXHZtskQwV/sMWw54uOnGFkgPgqACJHQwWeaPphFqJEIcOOhn/R2EwW5aON2P5aM/pDBKRsgMzGhYcOlaM4cPcgN5aMch1As7dmN8g5BjbWOMkcNCuNScP1cN+jbvdzFcPVcMHIMsOPycP9USD2PG0FDONhV7UcOiuNdcMJRhscN2ONlcNmQ4GO0TACUOOGxmWx1eYMU/AHxEiuOmBBauOlgN+OON0wgANMcM9Y7CANOcM2j3uZU1xm6cOKcMOuPNxnlcMBWEW8lMcMuuMMylOuOTYOEoLYNHkcMijZVcM8CwxVxn97jnnycPBuPBg7Y44EsnWgNhj1RuPoeEBuOR4jCcN6gOR66BziuuPauOsMMRiABHkqcOxuNzFjNxkBuP/620DYxuMnYP05hVcPmuPtOPKTqWcPSuN764aHnKuOiO0PrV4IzPuHNcOlJnR+qNuPK3wFj2ARbCONLj5hkPXMMkjmNV2Al2wdFO23nl188l7WM5R2tpa7vBVWOwl3l1y1WOIR0Z5xt2xNWNDuMdDVJ20Il12patWOvh37JHP2Pol0/Qn9WNV23bl2wpw4iw7uP5MGwpyn0qqcGUl3kC4I2OTuOA1H0l0XuMgexZl1Fl2kk7LWN+EioZYqRFQ2MS2PDf3pWUQl1QAP3uMjuPy2PMZaqbail221mwpwaEpK2NnWNPuP2dIyR1XWN61wA2MNR1kpz2QiPWNfSi/JG7xo62Nel3ytGal0W2NHuNxV3W2N0pxQeP22MYpzFWPXuPdLoi2NDuPPuPrWNml2xDlpRTk2N2MFh9Ful2TuOVUjI2PG20iIVo2NDuMITyY2PLuOnX6ruMhl2jMME2PgR0x5V8Nn9uOrsSw2Oj8HeE7H20QeM8wW02Ppl3xE43uNQR2TuM2vC02N5l2iLDkePNUGnuP7s5W239uPxEAVl1DuM1tDd213uORxDg2OPuNY1xrqhtl2iAOMp7i2OQl39Jy2V1m20/uP4lwG1Ewl3HWOKwWq2PDl1mp5QeMieMNs5IeN3WPyeNW2OG2NplzqNEm2P0eMmdXH21oeM6dX72242NY1zHuNXl04eOOeNHl2UePGmSel0aeOSeOGl1AuMOaPGiPic45nmR2MrQMpeNPl2wuO/R4peP3l2GZb8knwO2pePMgMgWEypH/l3k0CKNmLVnOF1uk5leOj7n8NCKNlrVkDQOGpHeNmQV3dMmkb4UO0F2OwWEHCSoV0l2O7QP8EX7QM4uMIRAtePV2Nc2y12PYcP12M8uPMuN8uOny4CuNaE5mC6r2NhF0zeMb2Mj2M4PaW5w92MWgN7uP92NJSDAN3LePD2OrePzeMDUH8V0Df1yV3CV0p/1VaxiV22x0T5VL2PyV0HePUV07eN0eQLeM7ePRSDb2O32PyHl72OKx0Ek5bUH6V3H2M9DlGV1qV33ePveOJO372NT1xeoTX20MV1wK3meMv2PzEOTJww4hOsHOV1dlDUl1sV0I1zvCC9V3UbjtV2wsA+WDMVkNx1plzVQiPeNXmaY+OeYof2OXcjrraTJxo+Mux1QOMXJwO8JbRHgONw5zUl0mV0rJyjl00+O+YyBV3HFYlE79UGVUFBV001ytviIOPOYzhV0x5VxV13Mxbh12NCd2M3AYRx2KlyM+PI+MDE5ThQgxHw+PvJxw+MD2MI+M16LcpHiV0p/0MKCIxHmV1E+MXePZpT6s5q+OZO2TmQpV1E+M/2NmJVQZhk+M92NCkNU+MM23MV20+Oa23m+MM+Nw0FlV0x5XT2NLeBVV12NBxV11V2l5wc+NW22zDIJV12+NyV2veNK1wvRGK+Pi+O9hqS+Oy+M9uPf43vH0u6OEX76STE6PG32EX465jan0y30x+NLpHU6Ph+NPj4fWDF6P4xmzoplMGPGPp+PU5rY3GG4WEX6Xcic6NkmlOcPCn0hGMx+MTarZGMFckR+P8bjxn2U4Wh+MkUCz6Mit2lV7d8gnX29pFN+NyLTkGMYSFfgoqubt6Ndy2BJLemOl3G9n78sjIGO8mlFn7l+Oi6M+n7mDhnH2r6MT+M8WAEn2yX0On5ICz/H026MZqnRAg9+M+mkacrO6NO3E+mle4LP6NS6myYYzX1NIUYFz7+PS32D9y7PY2oE8X2Y30xn5JSD2n2l+PSyCr+OjGM+n4qDD6n3G6OP+OA0Din0W6OxqlTnBn1zcmN/hDbPj6gkfGOx6mCnrd8AuGMYFyGbgCKhp+N/hCx+Nl6Ps6lP+OV6Px+N3+N63DGn0X3FEXbAtpbIlb+PZPrWn2t+PukCAX3wBOFTAH+Ph+OJXaYYRzIk24XbjXI33M6MQakqFqrGPlqlEBMGX3lqm0ZGock3BTpP3YBPtn0v+PFqkF+Pj+PFqlvRIN6MW6ML5w7WLd+O76P/3HxPaJ+PZn0oREdql/+NHGNi6kN8JU33R+OhxCUBMt6Pq6n0BMP6MLPY+DAX+OHvhIpx344b+M7GM+n7slQ4BMJfE3PbqxgCX0oiozzEKBMDn0V0hz74XEEjn0n0Sx6lF7wTn0/GOjalteg5X2X+Ne6mBJLD+PpP09/5uX3smPWUkLPbiBMaRHAPHTPYuBP4GNQmnTPb8bh1GNs3G9Pa2BMyGPq6k0BORBMaBOAX3VGMDqk+BPyBPBCD8sjy31XkGeiDX+OcGMbXGT47Fn0AmPpBOaBNwmOeiCJBMiGP1OBBP1AQSXn2CGMGL7B5JK4Wt+MdN7nX30GN9z6R+PKGOCBM5SluX1omMqL5f+PmzGqX1tpENLJaBMsC0pBPEBNS6myKi7n2DX0aL7m+gt+MM6mwsY2sJr+N8Sa831tX3Lz6KBMQBNColsn29BNdz47+OThHm3F57EiX0D+MzBMSX1dBNWCDayjU6OMBMoC0g0ZQmNHBMNBMBBO0BNaokFX2xGNz8258wJGNmBODiFfDrrySXBMbIDXBMf+O7P09BMP+OnP0Tar5GM1imI/lWX3FGOO6mvF3/X0qGO7P39BM/X2W6lPBNwGMVBMM8V7OgFBM96ByBOtGOHP0sFJhX0w31HpGJdIDGOmWhAhPNEhRX0/oC3amEFzRBOsBN7pGIhO3+NtSnhzGSX1YVyOBMUhPya1vBM+mO3pwdBNUBP/BMVX0vGOrpFv+Nqz1Z+MfBOs31qBPIhNFBM1n2UhPPBO9X1PpyRXxr+PlDmWBNzBMEhPBn306MzpwLBMchOEFwyhMshNvpyEhOn+PIhNUXiCmNLGOTpEwMTkhObX31pxKhM2n1177AtrU6Mmn0gZFjBNr+NzDl1BN6hO46EXBNuNbXqGP76fBP3X1/BPB7HfX1YmOvqHEv2HLl4mNBBMQ8ZOhNEmPnlx2hMwhOsI2nn0xBPcdxwhNIhNT76bWrQ30fX0/5zYtzln3MmOhhMkhMo315z40oIMX0/+MFpzZLlJBNRhNihNGhO23ZuhOChNZhOvtDwhPe0zSBO1fFxPaLya4hMWhMlhMn+NGhNLtF2hPx+NVhOc30A32Jv26hO9pHi6HRBMVBMzlxD+M9+NthMi32K6M+6HyhPR+NSf0yhM2mOuf0Q/obGPGBPl1zS+nOmMOMCzuMjpB2BOcpEGBPkhM+mNu5zzRR/Gl6hODJHThOChOrhOW319hOS7riXEA32e2O1hASzWR32ZYo4/0HhMZmM3KOpmMP0AnhN2iC5mNoH4KonJ31nhMY63r10UwaHhOlmPcH6XhO3cEdmO3KMQvZPhOrCAJ33cH63hOnhMpmMPhOyQnfhN2iC/hNAvYgRPvhP3hO756ch29+46n1F31iWPnPZoi1l30IROFpHCV1V30WWNBP2L6aRWOckqFF0vz6BJIt333L0Gh1dz6p+ncP0Z80/gj/30/306L7554wP1bmNURN8oRj30YRPbiFj+OwWPfBN3H38P3iW38hNL32IP1PpzCBPr31oP1ChNMP2YSGSqiAv17yKvmMhW17pGp+M+WMth2XGOX32p54Dy1pUB0P0ytbsgHEVyq+l+mVgWM3iHCn1SWNPlxQhMEROUROsRMIn3sP2lpxLhMoWNUWOrVw0L1sROsYAb32lpxVNg0RP932P770+nsRPaW2f759+M3mP8RO46GqRN98XYP0gZGiRN0WM6WPeROKRPCea5uB75xdJpuRHZWOov2x7zE+mkROpyA+ROCWMqN289CaROojzv93xRP6n2GROUCDt+PwYBQWM6hPVpH44C+cRT74UHLsLY5RPfW29cMXxVfZaTZE1n0RlCbbrjBM2ZHe1U10G9X0FBVWxYP6OS4WPyH06MDRwduxM6MKmmtRM9HKrGNNRNR+OqX31RNsFGyX0eDAUzEV+MuUEVRPKOQcBOVBWdDkN+OYYGXlknO11ROzRP/H02mO+lCxGiZBMRw6DOhkbIzhOxw5SejG8GDROFlG1ROsBMQnanm4TRNxg7yJ27ROw1JzRM26OonZc0RIBOnkE3pmjASNROEY74e0tRO3NxomIgBOS2NYp5ou0ABNI46PROqBN9RMryGQu2DRMStwx+YTROCo0DRMHRM76j7RMf+OgYHyUAMBOL3GXy5CwLdROBVBC5K9BPQxPOrgDBNcUkQxNx+NtX0DZ4NRMt6NXRPAxOi33oUniybcBMu6PsK5HRN4xP64kAxMy32UVmfRPlRMbMLvQLoxNPknx8wme1Z+MQK7q3CXpGG4XETUMxMGX00xMn+NnBPWNEHdizn2on1kxPNRMHRMLmqZZmS6N3y4rRMiBMjaFCI6NMjU6N76NmrYm7Sbu0jBPaV2D5jt6Nxw7sxMaxO8EK0xPYxN/2xPRN3GM5w6CxMoxOgDFUxN6BPVw40KiqBPq309rYqPSgX1AUnPszDYRs6Odw44Xra32ua5PqSvoQBGMvFCxGiuBPEUnKxOtX1feYTB7VVEqxMxhNexPuaSBBMv17uxOju0hhNjrYuxNwmNxw6wPQSGMaUmJB10GNGfKYNWerYGQzaxN+xOpBPFa7JxOrRMWrWvOIIe1RGMHVbKWEAxOCGPpxMqxMeGPq3Uj3Sau0yGNuJkScJxxPJOaFxNEmOKuMexPuhMv14AkrBxN4hP5rUM2ysQI8xM9xOSe2sxMdxOtX2jX1yWFhxOmGN51HqxN4xOy6Yoe11RMzOw1xPlROJXCvRMtRPNOwGxOH+PS3UKlJWxPpZGGWG2xOuxNLLUJxOexPTxPBGNQxONxOnBPa3GjxMwe3cmOUMA9RW7xP1LUxsr3BNgX3fY6txOXxOgdAZxPTRM317yUAjROJanea4UzG/BNfklz3HRe2AhPZxa9E29xOdGMv14vxOdxOpxOkk0KRzQhPG33/2nq6OCGPgOmOxMhhNM3XcxOgJPh3VhbCfRMxhNLWE7xPWX1PhEoJPzxPT+O/15axNvxNwJPgn2X+OPxNRxPkJPgJOtX10hPAJMDxNWBOJa6GB3shMKhPfxMuUCD6OEaF0JP7GMKRGZYOvxOqxPHyqUJOwJMNExkJOCJPMxNqhMu6P4JO96MKRHYJNLxPCryEaHSJO6xPWxMSJPmzEB6NNZXEJPQGOkJPTGMiPVZYGoJMy32sjaVjiGhOmaHBY6TxO9X1GJNNxMiJNP/SLn0/zzAUEdIUgJNtBONZH6JPoGOvqFxYFEaxtxPhbZHB1kZ3IJMdpYDxMIJNSsYYp0yGO6OnwJP1BM4m5MizhxMbbU4gTw31YhMCm6iJNAREBxNmRbDzQzxOX+P3IWX8zt6PmRZIJNCmPFRammO6JMkDSmmMIJOfA6FxPU30gLVGBhLxMIJNFJO6xMmn2NUkfxMpJNtCy2JP1hOrQ77xMt6N1JOoJMIJNIxM7RO6JMtJP/+M2mOeQ44JMmJNZRSYJO1JNdJYPDkThOrxaj4T8zEshOybbj9FlRPqhO75GG8hS7Ya6OuwmRB3LhNeaHhoRWyANJMTJOhmM2n3AgRc0TVBOu+h7hPa6BxYG7ZGFmMLCD7JMHzHXhNIn7HJP9pCnJMyDChzkXJMfhPnhOUSAXPh2+CHJPmEWslnZ323JNARM1+4S6D9pBgRPl+6WCg3JNQRPm76oeAPJNfJOZmNjrHXzFPJPxiMBL2w+5qsFy3HcP17MCOcmxROnVatvjwpOjmOb2nq3D/304RP/Y7veA0R7w6MxQATw5yCGLmMoROopMVDkIpP1LWogq2RPiW1zY5LzHL30yW2sJO1ROwpP/xOYWP930UJNcRMWWMl3W4xOWRNoP0aJMPmP7loJZGFeb2LalxAhW0yjbkxNSRPeZVpwoERNhWMha6WxMRLbKWPQF5cpOemXRwjaLZFZHspNaRMgYH8JNL330pNMJMURNKHHma5zCr8pMoROxJkZWSwWPma6E8S6RP931d96VRM2WPaW21WHjcnCP0JZG+0heckCpN+1wGpPmuFMWMhH3Y44rJPUpNWpNpeBwYyORNWO0PGDEpPT325WO3un/W3R23JFl4ePHl0rHHLWPtl2a5EfVoTuMRpNzqrwl31WMFSDP2MlWMzEU42NJpOscydWOFWPJpM9WMZpMuMoO8CE2OUAWmiEHuNHxFf1QUl3hR2mlxTWPZpM/K4C2MljFHZqM2OC2OFFwPuP3UniInbWMbWP5q4cS4vuOrOMczzfuPCLVFpOI0FXl3HWNx0rz20geNFpNekaWl1XWOmlyO2PQeP4VAYeOeeNFpNroi6l1vWP4VAfWOCR1CFYtg6PWODWNLejTpP22NksnhpN1pOerJdl3xpOdpMkeNOLXjUpU2PZpO2lHUePxpMGrF0eNkxHSelR23ZpN5RQseNJpO3UHBl3BeOqsnsVUlpMbjEZ2Ts2PxpPbETOl1JpMAZNJl01jGykhiePE0n3EhMl3ZpNgZNf21JpNUwR/pOZmEmdJc2PZpMddK82MoZNo0GKeMVpPjP66eMtpOr9zi2MyrFe5YmeMKD3YZNy2N9pOpdKnWNDpOIdLL22jpNIlLTpOTpM1SSal13WNaZweePweNTMXzVRLl3G20klL+eNw0kmizX22YeNVMmal27pNQVKReNTyGtiRInmppN4ZNf20e2PAuP+A2Yu5uNkFeOMDnyZMZeOP12XzbyZM5eOCa6F6i+3AFeP1eOlg5d5EleNWz5+DwBnl9eN7JnEDlgV09pCmZN1eNB2MN5EWZOjrFnKAl5GIV1R2NKlB6ZMuxFoV3deMUh1+F2FePD5El5GDeNa5p0j28JIEtBPQA8O28uMEcMQMVKQ6zeNhj3ISKQOOLePb5Yt2pEpHpO2fmCsapXUHw+MxZOi7xEpFBO2fmAIgx7eNQFhscNeSOHeOWx33q6rKjz2NHeN4snN7zSV3yV2FFz2+PUcO5ZN3eN1uObzyPePRZOMFw8hQfeM++ONZN72M0V3MskdYAHCHpZONtxH2MtZOVSM32MNZOGajT22P2Ms4NzCG6x3Hgpw0HdZOHNVdZPKV2qsnU+NM+Nesl/FR3UFs+O3zWSvDo+NKTwFj3krxlZMbeOWzX6RhlZPSbSTW0xTydV0dDmZV07KUq5FlV1zZNm+PlZMZlKW+PXZMVER++Npx0FsmlCZZZMO+MlsmweNJZM6+OHZMKba622Ux2LZNr6hZZPFZOLZOPDQfZM7ZNA5N0+MGOwxV2XZNTUFtV3Xq4cZFxZOy+Pdq5rZO1V0z2N/yXq+NZjKQD3XQORkOgs5huAmnGjXRcRa4nEfSzv5EVOBLrlOFCH5EmuA9O145OzDbTnHfqEpwlibqYJ1m6PtEV05NlMHdb0mu1U5PSJ3quz3+nvoqve1xWz5EU1Uxbr3LLRwkXbqAbO0ynwEm5cjjWzkWSQ3U0TpAAu2E5Nk5PinAnO3L9X/5F6ZDeu3AFFK5P8J0V+QOwnpDauZ3VY0DnEmDb8u1oi2iZmy7XSJ0C5MEm5nKxHr0S5P5EX32B+r2QpSkDbX04ZJ3vWDv5Gsb4OJ2U5OIlyHJ005PxBmSxIWJ0M5PJBke5OBb2s5Mu5N3J0c5PpBmnu3a5OCZm25MaJ365NwkXAlwLO0i5M+Bl65MJYpuZU8FxxJ2B5PKDZsu2cKyBhgOBmp5Ppu2QFo+Bm5Zlu5Ox5Mk5OU5NR5PxDlQSB0Bmm5Piu2z4KvUE3y58bmU5NdekRu3AFE6cIOJ0l5PBBncAg/p3WcUOZAue1TizEKgTUEMzTNJ1e5Pd5Oy2r5gWs5MTtXjp3J5OoK7Wp3m5MTUHY6j4u0R5NIs7y8rWDnG5Pas5V5PS7085OvUFAbzMZmkOggm6daypJ08FHjJOF7DBe2U5M3azBp2k5Mw0E95PRu3AFHZjCt5MMFH5EgGJ01kIxbbiNCnJ30aGYZwmRYP5NuRDBg3EYQ35OyeDDJMX5MWJ1cnThbb5Ugvp2YK6ZZ6j4TVu2WgVX5Gj4T1u2te0Xl4p1Bse1bb065M7NLQp328hmRbwFPBu2+TqsbaBLLwp1FDFyZ7gFNLp2crrwZ7AFNfJ119Xv5FhVJcp1N5MI0HB5O4FOYNUwwTpe325OH5EEK0Qe33Kxn5FJ4yN5PAFEpWxH5Mc5OuwlT5OGe0sFN75N4b2/5MxwlfvCN72kFNw3iL2ztqHAFF6zZje2GmB4FNrYo4FPJ5Qgm4rcT0FNh9YaZ6evjKp3vqEOwlPzlEZ195M3Phrp1TbA+WVr5Np70MFHiFNEb1CFMoGB8Z0y5PP5EaTDjp2U5MgiA/p1d5Mjng35OaFMBOKu5PfLh1nEqwzup1g8RWbYWFPep3J5MmFP+p0T5PHXhCp0ermh5MX6Hwp2qFMeFMVhDRp3uFOJbZ7e15Y2Jp13mBLp2hFNEbbhFOLb085NEbaAKYrO0x5Mi7j5p2jdJKFMEEPxe2oFN2O1/CThe2YFM5wk8FNjAU2CQxbbAVAyFNCFPXKBcZ3VFPm1JGu0UFMVFOeFPc8E8FFEbY+5Om71qFFfyk1e3ZFPM7UDHDjp0L5PuzgAFPx5NFRY1FPRr1QFOVFO3p3J5NgCRrp3q5MwFFpFPZqHp5OZFNHp0oipxZlLFOXb2P5PtEXXBREZ06FOJFPUFMLzwwFGq+Qpp11FNkXhKu3AFEELhDFOU5N9FPep07FNdFPWp2aFPzThPJ0CgJtFMd5Ms5NAFPnFNKZ2zFNEbYnFOQFPl239th2Z2kFOf3b0Z00FMJ21PNJGFPGFEe+wSFMAlNIQoYFML2QiZ5OSDRFM9FO9wlV5Nq8HWLRPG4WSDZuZhnEWZmrg5AlONFMPg4IlPH5M9daPqAEFMK5OSFHwlpnrmSFOPiUmHqXe2yFMp231FPKAW64QBI50lO28GIFPHg7PNave0uUrxO1fhrmOkAlN9sVKZ1N5OMSkWAqE+3GFHk5OaZ0ElPN22bVJH5MPoiCyOQ9TU+3ClMt5MWJ38lMOIlEZ0AlO3I5FFMElPKo0CFNY+3GFHmb4kFPGFGWlBa5P2jqSFH6lMk+0MFNcInylNru16lPmlOiFOgMFGrxxJ2f5PRSlyLzT732lPFdYXsp0J2RFMAaQ4LkXyzN0HLKx8+2GlONSli5PclPGFGulPTqGmlOdSmm5MhlMElO7JOTGByFEG+1fDh9dBvrlzpm5sRlmP2IkJlPe8FJlMKZCr5BdgXplOir6T/hMMGjLBG+15RWplP6FDZlOKFm5lOO+0llMiZCZlOJlNtZ3na11wGW+0VlP80H4sam+0VlMJb6QpOk4EjWXe+0GjK++1Ufhlpln75WO3Ip1COlpYyh+1JHi3Z2WMhR+067jgOU5WBEwL2bZTSSH2WC6AKVL5bbpSQUH16IT9lPYCCPZ2XDLdlOzlP9LYrWwLlNmO0nFP7Z0rlMFFP7lPc50LlNtFNAQQ1+0blNOO3HGyg538lK6+4meIS+1GC0fxxNkBj+0Y508lR+1xOlki51tQio50flO9+3xUwj+3PlM7+1CViT+18TgS+2fhzE5179j1+3p+0Gra3FNU51dlNXlPHlMSmy7lPn6LP+0t+1hfU0F7Yiy/Z23lPoVPDegV+2XlPoVP1+Jzpw7lOr+3J4BVoTc52yLLkF7N+2TWw7tzoVNd0FDH0eS3rrb+tiAVP+3CNxyB9iE50O7SRW3VKnKpl9lM0VMvlOIVP5yo9uPCTDcEOM4OC4lCVOg4OauBV1gQ4MC4N6ekykPW4P/8EkJHwNyJrWl4kiAnY4P/8G62yTs0I4PG/aZqw8tV1LVKVN44MirUe/aE4Nk4MsF29TZarW3NGDdaJFHV4NfjZoTL2rUQLVpxlV4M6VPMS2N4OF4NfjYSVMJrVTbyxqW2Mr84OiAOLcM62Efw6J52r2nC4Nd4OEPZfYLi4N94MCqXC3iG2Ey4O550Ke0g4NMrUf3ZSfgYMmT4OipkR/5jiWrLXYBXQ/gT4PWrVhekZVPa4MG4PQTY2w2pVPE4PhVOvqiBOHNmVXJEzdby4MOVN6AixFFiVM+VMUMllVPuB24+KMMm1VOOILf2H+rX/jYSAlFrUN50uLjs4MOVNdNqB4OTa6Y24d9CMJyR4MZpnGdjeSmh4OH9GVpmMMntVPTVPnKX6VNzVNWrXJ4NHHU54NxVMk7mjZmuOGzVMbVOxPm54NqMHDVNgqVlLVqMEpVNuVO2VO13ys2GzVNnIbi2GWVNqMFY3GhrVsLU3VOZ4NN4Nc250OJOVNSVM3VPhENNuSEiE3VMM4MS4M8fljDSc2FRVNBMEkamlVNrVNBinABb64OLLVg1NmlhyiVpVNQ1Mu4Pe4M+26aOnzVP6LV2264Koz4PGLUZplTTCZVMW4NqMHIqwwtW1MHXO1H4OnVMvVOhVPmLVRlPHt66GQ89G4lHnMkpa3paOdemU1MljIQuPoJnCPzJApvsMqZN4CE0lGf4M3emmWjTPk6ZPWgnz7nPa0WF081PrPmq9HEuN8lEC1NQENClGrgzAENVaOwmHqlG3MnwEM5aNPPmMO3GZOdFBcqVoEMHgnDeNcuOjePlaPBZPN2NBFHb0wtOlckMO/ZoLnMEN4kMqN0dyQ/OnG1M8qSmR08EMMEMO/abrzDda+EMm1MakMcEMwN0d7lG1Owc6FF1dFCrjGaJy8ENMZxocThEODEMO/YE6i8kPKV0h1MakPO1OB1NIummEMMplX8aVdbokNRqWVMm1ENCdlOAk2kPxF05njJ1OJ1NoTbpEOx1NedneSlK2IQ+M87DwkNQOM7dmDWp+1P5ZMpdkOEMIkNERMGCbREPh1N11MGEPO1PYjAtOl51MUBHAkOLePZ25jXjzSHN1N5p2QLnG1Mxo75ENt1MBbCaJyd1O927mkOj1NDx2XxkEOykyED1MAPzlOm91P3kCTs2PVBlO2dHVB1NBkOrxn0PAH0mKALduPFRMltZJxQdFnaR0idqH1Mv21HimU+Gi225u0neiu4ivh0sVHNNEzuNWk0Q+E31NQcEfh0Il0kKGCDo31MqKWRsFPh02P6AgmFpNJEoDWP5MHV4lMiic21GSOIZRB20BR0XSF/FhH1Pjdb+R2C2O737n1P1l1IiMczQj23aPEtdZLuAX1MS+GIcQINPdl1n/UwNPeR3HWOQNPFR2jpOADwn1M1R2kvFiURa21we1LQTsR3zpNANOKcHh23/PFEiL0NN6l2ejnz14320rCGX4oUNOA2MkNPnsGn1P8cHJR3Hl3HSHINP7l1F+0Wlk31OqvDwN5H1NpgwseNvWN1Irn1PR20BIqHiEBl29fTvpPbl207mwPCE2NgMFzeqYZPHl0wDmB+EBl16NPdR1XWPTjgq+Fjl1Ll4mNOwNMKMEWNMs2Ncl7Y376NNN23g7ill26NOS12xR0BR19B1QNMONMfG7JR16eO/PFQgkoNNnK6NonZR3RpMvxXOkwkR3iiNLORENPHWM0358mFq2N5a7DbBcNNkNNAtDANO62MLPBR+F6215l52NPdR1vWOZNPm2PdMGpNPNR3BeNJNPMNP22PxNMSR3ONM1dbtsEv22+NOmNP7l3k1NcpaZVGjWm+2MZTVFVGgO2Onns1M/kUNNMrR39cH4nW9QMIO1teNEq6xtEJ2NqIljVEYO39NNBA7TVGzVnDNOWtH52Ni1NA84TNMmNn0CGRtwzNOouPX+ArVGFnl/R3alEAx1l2O9eMVeOUlC7VHgx34V1a1NJNG8ggBZOw84VaPQmGwj2E/2e+1IIoVbBZx2YSON+ajV232PSCXn1PpO0pTxmK6KO3JF3PNNhlFBO3pt4aNP8V3vjD99jo0H++MLPFDJrI5PFZMz+FHvQFpOvNOkWU9sHQtO+KY9sE/NMiwMFpORO23SGSNPmV2otMmcFZO2yNymNOItOAjyYtMA+NDT6OdE/eOSO1TtAOyCMx32V1V+3HagyO09fzxh2+YA0mErx0GO2gcRlXkMtMGh2U+S3NOvNPjAz/lEctOerHXsE/NO4+G3NMotPiaboNNlV3CExctPyV0OKSmNPpO3eNQ0x000IX4EozHnsEnZMu4ntw6hNMu+N34GBrEvFClEN34EJrFNV36s7StObum/ZMStOycHotM7XRhlHAtNUIpsNNS+P14Etx0Q5O8SNCtNe21IOONxw4KTINNwON70FGk5KV0hvgxVzmtM/x1+V3D4FAB3EtNyO2uiRWiYmx0JJZi+GhNNDV1fd5ghbI5OvZNwEHTpipx2ytNr4Gogq3x3itOuVDANNStNjALXsFlV0wDnU7AGH5X3RA/VHwQfZNKZDQF6+j7+l0GtOvnQltMI5OJtD5tMYx04+Mne01mGlO3mN0W30dx0LZMam7ANNBO06AhzVLBtMxtPatPgOPgq5IVkrZNfd4KRxxtMWgOrfjltPtZM4nFktF3NMJJa4VhLsFttMpbQxNMvx3BujZtN8+Ofx0jtMCx2/x25WN9pydWVtWNTyGbtODuONyHYGEjuPRpN+mUWUgwl0RpOM1EntPbtOJyHoH6tJHBR0whF/NpLuP1WPnkDsAhYl1ntMIRL4229WO6ICpO0ANNQxHO/mQiHgR0/cGm20gNOSp1e3DgNMRpP1AWK22hpO3tHD20TWO3tEKO2INNVp2wkU4R1i5HD5yIdMYNNFp1wdM4NMHp3+l7/uM2sngdMjpOCEiap0DCiyl1kNPfoCNnr2l0zpNl5ypO1XUHzl0AdOvWOcZO9TCAdNrpMgNXaENW238ZOIanYeNg0klUBbtOvh2HW4+XBHpPl4VbrJQ2OkeOdNUCeMJFlvqnXpMCdOD4B3pNbLVnW4KO2QdNKfovpO9yEl2DPtPfpO0Z2nPZp23/tNJpaN22FWNadOidN886Y+jCeMVyHe5zD20MR3V4XU5q3uNgdPt5SyeNKdMdS4k2OIZPx1xUdOXtP5NVcXrXsGQdNwbwC2P2dPhpIi2N6eMN4X4ZPIdPXknS2MKD0utXg2OWeNuNWK23K2PMEmZJGxNOM8lN6ia2NGdOFMqueOOOPu2CvZE0dN8pwo5EMNMkb62dO5NOe8lRS5BeODWPu2CMdOSR36Z29JG3tPOdNXpqldMab7mdNheMJeOvB0guOhtBe1E+2NM1PLlCPTG/R2B2Oq1PNi5rTF9NPahFdbz5ePqZOeZNOb7+1H6ZPVNb+2NDdP9dOWhG51GVVE51EjdNNeMZ2NQ07j3GkO378llHAOZOy1NQVCDdMuZNdeMMuP0O3K1N61N7eEhpwz+Ju0GHNN+ZMnNPcO3NJg7dOY5M1aOgb6NgLhZP3Z1XdM1ZN+O2hUAVO3xZNLtEKO3JZMPdPbeN1uNPkCaO3ZZNZUPx7RCV35ZOHW5OOZFZMGuNE8na+O92PwUPXdPfZ2DURKV2d1Mg9M1O0NZPM8G9ZMegOHW4E9QfePtZMK8EFO2dtPI9M+O0tZPAdGvZFd2Mw0B923ktOWEPGoBLIhjZM0tPWcO/IB49OzZODJGOdOY9MsZbjJEw5Oy8kldODrZeCS+8mGR02+MI5Nl87x3gA5P/dM09M/ZPfdO2W609OqtNc9NfdPRtNc9NJTE5V3N4EmW7M9NPdM+vHw5Ng9OaR1lZPxtNl84uwH6tOVV1B7VQD1+B6VPogAPsAMMeU6sMYrFvf0ssPkOMg1Y/MOeAP/Vav1G5OMpB7xNqseFm9OnPbFOM4sP02NMrWcOMEsPohUiskwsNivbE20iONr17UBpUAPesNXK3SsOqg6ZmGUiG7gm69NWa74sNbsN+K5EsMZsN+K60cNl3m5mEXE22uOLOPvRNKMCxOPG9Mx9MyANGOMgYFSppTAOcsPLK215jbOO23jfROngQCsNxsNPa5+ai9sNDsPbK0p8mr1GSsM6naDsNZON19N7AO+ONV9MGANLsMY0FbANrsPI0H69NJrFhZDrOMR9PNxSJ9NxONPxwSK4BAMu9MvpAh9Nj9OnLX2sOysP3VY+DpSHm69Mi4PtxGFAPrw729OBOOdw71gNe9N/UHUlC5AMu9MPwl1OMurV79OzsOl9PWrYHsNxsO1a5aaJWGG69NSQhTANsOPtiDpsMYsNBjbV9PDONJrFlWn4eG69PoLXh9NB9PcWJDANqOP1LUX9MysOm7RdLWoqILON6OP1LU0ogGsOZ9NgDOLgltsP/Y6v9P7OOF9Pf1GbLUV9PH9Of1VnOMuAnDMAGcMysP5/SbmWzLWzsMN9O4DORsPN9MYDOjsNr9MqZGDsOd9NIDObsMYrFpNVfAMu9MTni/AM1dMnsNY44H8mvsP0CFyNHQuN01PMDNj8kggNNdPHa2fsri+JIgOzNPmN7BNG/sN4PW8riiDOOZOeNFHbmAcO+NHiDMQcNSF1N2MoPVeNHyDNlHnzrE34EgcOzdNleAiDMaql8JlK1OOF0q1O7NOF2PB3zsuNozwlaPHNNlaOmqnnNMYWF81MRkMXdOw+4VbxpuPmuOiYGUcN2uN+O2/K13xmZgNmeXLxGKgPsV3uDPdbkBgPZxGOuMxcPD9MqP1puPJuNPa5/APPuG8cNJrVzvqr1GeDOhDPeuPVcOonYuDMBDMWnkLxERgPWNFidwFgMKcOQI76jR5bkFcNkTVaskBDM/jH5DM5DMAI5/xFucPiuOSUnCgMlXFf2PqsNgQlWcOy7Y3S0Z8kWYKKoD+w62cPycOxxregBKxP7xFxDNJDOkGQhj2uDMi+4xxMZgMicO1a46ULyeGeDPbITYNEFDOaGXegNJDNzDOseEBDM3dr4eFNuNta7xuNtuN+1zxxPislyeI9cM46Ox8EHGBgwOoB3lGGVil/+22QMdDJCQMDB1QAPo2VzjHOB03DMwB3GQOzvHN4V3DMizooB2bgPJJoYB13DMAboD4XvDP7CgP8yEB1ZMEzXVngPyQMOxBKZAJmGtB3jhov4XHDPoAM6OUtB3nDORIT6QOOQMKRqXDOuQPur5wwO/gMx50tiYCB2P3RSAOqOWgQNNkYDvEIjNGQNQQNDr7BQMzB1qAM4CaIQOxQMDAN5eqUQOJQMXBlvQNJpYkY2gjONJmG6V4QO8A6QVznB05QMMjOaB3SQM0jNA9RlQNnCHjhpHDN3DPDEoAtGijNiMaAQPPB3vBksEAqQNiGGv+pQjPhB20MCVQMZQMYmnN3AfgPlQPUxAtOxiQMil6KuoYB3JB2u15KAByQP5QNYA7xEBVB3nDNmjNyjN5GGWjPZQPUjMU15aQMmW6ZxmLzAOjPQjNNRkoAO1QMIQmnHRpB2OQM88CMjPhB0517hQMuQO2QMIsUMB0+jO/SoAtGojMg8AujM9B3flb+IQFB2TgMNlbhjOMQMEjNHlYL7QaMGSB30nn3SrTB1yB2Pgmen4xQOQpGGMCsjNc9Nl50dsDHB0onC+05ejPZQPsjMAVaVjNQGXUTKPlYcEPKMEWB1dvaFjNcjN1QM1jO0jN3aWajPYMAqjPBjNxjO1QMt10yZMy+0D06oh2NEnFVaoh3QEU2DN106jjPIEWLGB6HG9NPVUOaDPEx5JtHDQNGA6DNNjQOSDMRtEtNPoTE52P6A5LQOQgPtNMjGHrjPrQMWhk30SzQMrNOwmErjPbQNk3ml2PIcPl2OGDM5tEdC2NBInQNmDM/rEWDP2XlWDMHOEgENXNMMvFb8jywOmwPtvEwNxItGhh3+hr8wPIwM0jOEnK2DHNh3DFygTPbNE5h1FNJHDPAwMwN0O1KITP0X36gPUDFzjEwwNbGk/gMywOigNpjBIwMATP8jNHDPwTPbISYwMcwOFvEVQA6wO4wPFr7qwO4TNlgN6YgarEkTM48DkwM8UChgPr75ymEgTPoEoawMIqSrVwgKCRXmhuGlh1Tr4V5hG7a6wOigMrua3DHwTMeLFowNYp6Fh2XRC0TP2wPmN0IhlLXl1h3C+Mohn0tEo7Gxx0M17tQEqElDdoVx0M14xhDGh0KwNsmnSwOGwOygMCwAiTMjh3iMCBjPcVAflAsA4oH6qh03lR3p6ePqtXkaTOK1zUxB8abXNEqTPv932MD+mErh1xr6bOjvNEFh2cA7mTOEtGhh0q60GwOWTNRgkawMATOmjMMBwD4WRTNxTPJMGSTMInCjNF+TOSmnWTMysFbh20mnzh2K4zY6Oa9OM96nX5CVNA4OFTOVVOw4Nk5wXh1/yX8LUWX7akPx4OSl6o+MyVO2skfnnph0N2Eo4P6E5Y4MaVNbX6ZvRFZxlTNPzmw+H44Oi9GGVOmVMaY1Bp6crVFVMT6l16Fv1yWVMqW7ZXSIOFA4MVlD2VOw4Mz6lOVNlLUqW7hHIQ4P14NmmEiEOJq5gY2bTO+VNt4OrTMVTOfVPwY0CVqp4O/VOv6m5LwbNWHLK5Y3yyCxVPJ4PTTP74OQ1MqW6m1Ox5yfCjpGlKTiZVOL4OyRDb4PHCz740p8DG4MY1N1l76DiJVMPLUfm43TNDiUV4MVlAfVMo4O7TP1VMgzPjTOZvS1TPdl56fBtVMQzMYPCB4OfTPBAZ+4OozPtNADVMfnmUGkh4OjVORGmrBz7FGEzND7WCnDLKUQzPoXzzVOTa6Rm4IzNJ4P18HqW4pLo7VNrVORp5RcDLTMKMGMzOrVM0zP3iwu4NTTOLXFUEMe4NFr2c2FzTNUkpXVPOVN+Y0fVMc4Mfm4uhqbVNWKhUTkC72yzNSVMSzM1VNBVOhl6izOXTP2a4IV7rOAA1NXTOGLbeiwPTMMzOLXHfTNJVOMV6GYUw1OvTODm6F1pWrWfTNWzMKZwo1OmzPNuQw1NFVML43GzMgzOYV52YT41MWl5Pr1E1MczMKzPMzNk1NDjOLR0N96C9GM1OA3lXPm34MrdM8W7s9FU1Nq9HrBj7R2NVJs1O4ENE/YEu1c1Mb/mdMl7PmcDPt3aG9GpzNy9E/LAi1Pz6xCDNh97ZzP5zMqXnq9Ey1NjdOzRApzNwEMPPl6DOIENOF23sMTxCe9GtSKCLKcuPmDPcuO61PjeMhZOpQmRKyUkPKV1VGm51Pm1OgwkoBoNOl8kNkVBY4P0EPJF0WX4ampm1Ozopcx2mNC0kOurScEO0+PsENe1NFdEnGECEOrzPo9FG2gKEOjzN5Yy9zOd1NbX5W4Pp1NzzPDw0KEOx1OdTPV1NHENKx36E6XzPRZP49HIkMjEM3zP11MojDXzPWoV/DbnzO+p5OkOk+OYp7IMq/py2EOo1zTTMeEN8kOd8keEMjEPcc1jEODzPnTP+ENqkOrTMLzNkkOv6m3VOCdYb1MILOXzNKqwFH1mmGXzPcPXTL1mmHr1N2bDZ92wLMrzNMkPz6niqzVMGCkPbF0qW4kc4WkN9zMgLP5EPOkPL6kCkOVENFJyem5IiQVEOkgHdDPL6kikMHzP4U65x3HzPwW6kCqwSEp1Opm6rEPULPj6PkunokM/6mDqmPEMiLOSLNkEOQLM0GkPzNyLOtcy7EMwLMNcyzEMAkNxO1CLOkkPLEOlczCLOqPCDm5EUDQkNoLMvm6sgVouk11N1l5a4PKdaJ1OVm4ikMvzOhLYlDXgkNcLMxDBiLNXzN2LMgPqKkPULNuLOvEOKLMt224kOzzOkW6B7kvtYqLNoJhqLNUNAaLP2LOsLN8oTrrZKGm6LNGHD6LMltIRFETzPbENoIUl1P+1MJGmckMuLPZGk2LM6V2szMJ1BYkOKLO1gXKdZgLP7eiEkP/VrwW50OikkNlO3xXkLzN6LOmzNhUBsDZ0kOFaV4izCLNELOmzPSMhHSFskOhl4FLNULNcLMejIjzPULNRBjFEMdLOmzN41NSLMtLNk60NTOSkP0kOhj4SkNykPDLMikPwLPqW4RipEY0qLO9LMzzNT1Mr40SkNgLOW5r/DMOkMX6BFjE9xwmkNqzNVlyLjG7LMbUHWkOakNWY0Ex2aENcx2pHmT1MUEOEax6unALMVqh6ulgLPWC7uum+kMi97+xTOLM+DCvL23LMHLO71P7DNBVXRVI6Cne53DR6s13q50mSBrqMIF1/JDlqPy50wrOrV3nV2K940D1m50LJCm52IrNmJCm51wrOJSDIrPorPklZXV0dqN1VUsD0YaNVVV1HQcD2210KICDqOr50YNltD3ID2oezQF3CD3weywaNul6Mc7Mmp3V1Zsk8HbZCR+D1DD2MrNKD3rqNRjaMzCW13bqMwNmaQHX502GEKIC5qP6D0wNmwMS411l50tFC3BmXqOZs0maORD2KrM3qOPqNSrMXqMYaOps3yaNV13irPgrO7gP0ZSh13lD3Sx6AaNNl5oYVeaJ4aNGrO1LDgaOfuEQNG3D3WD03+ywaNGrNNtmy10JD1k75orOarOpYVoaPdqMbjG5vY211GrPRgEC12uY2xYXmrOEaPXBFkt6CaMP52ajYpdRv53wD3hrN2aObxFdwN0aMMrNpu6/520rORVDND1prN/3mjqPJrP56SkhHcaPIVn0rN9D3DnYQHiDD1To3aeV/qNiaOxnYirOTD3R12XwMsaOyaPUVlXD1LD3Xlk3qNrD0cnZqaOVY2eZm8eA7D3aaOJrP7D1UiEplDxYjHD0erMtrPnD2KeGNrMWaM9xEceq8F20rMJAHN11GcR1NNHHZ4DGBaNQrDLrMXtmRzNLmHLrN6hHwKH1BXAj0Aj2bjMyw3L12/tl7zBy0kxaOFzN2w2nrN97GqDM4x4SDE8imgdntdNyc6XrNT1nJaOfHYA8BjoXxaMPjNrpDhVlZaO8EVuZMYV1MgNTjNKlC6x7Uj1RSGtzNvjPtzOWDNndPVaPVvBvZ76uw1F2g6PxxyID2/l6cN0GrDqj0IbOSPWJF2NDxKgOobO1YkKN2IbMeD3DaMwN3jYAEbMKj1mJyZw1YD0zaNoYU6wEVF3obOgfRS51v13EbN950Sj2zYWj52Rj2wbmdF1Oj2KcPsbNaj0Th0INlKaPMbO1O7yj0XaM2H5RAkaBE8j0QNGO51ej2IeVHnrTaPvaHWcPeUl5j2g6PrmGuj39aM9HYcbMcj1qbPFSPibO3+BptkabMQkXzaO8bMeDBVqMpj2sNn4LCCWGqbNphDD8HZj2ZYWuESej3+awFj3NvZfF3Fj171OS44A4NItGMB3A4O0QMfo2BZ4DjG+QNw4O3DOzgP+bMPDPiQN/h0IB2BbOY4NNjGujOI4Pfh0pQPhbMrXo/DPGQME4Mn0kAjODR2k4MpbN6l564NXgNmQMwR1kOFRbNhjnYAl5bOZqEPynDW6s4O+4NhB2fgNSR2bIF3aWeQNcH0iENXDO6HlhEO+bMpjNM4PFbMZjOS4PxR2yB2RQOW4PcEO5B1j4PiR10jMHxkEDClDGpQOstDb4Nw0UUY2ZbMR6U0Y1q4OkQP5QONb107mbC6jR10R1q2XlQMzqbhENVQMGjlVbPj6WmrPO4PsAkOB1u4O5bMebPxFpRB38QM+4Pg4N1B3hbMB4M6jMhR1/uiRbMGjNmybeSnHgNR4Pz4NBjOrbMOR1WjMY4OJ4OOjOK4N+R1PB2xQN54NeR1ZbNvbO/bM+QOJbOhR3ejNHtIRR1UEOFbNlR02MFHbM94MOQOQ7OYhrrbOuQMN4NGQM1bNo7NPB0JjPt4PrbNgQPt4MFbNtbMWakD4PaQNyl574NeDH4yI/bNkIqEQOJQNr4O/DEjbPg7NVjPH40M7N1jPTbPT4NNjN8jNb4P1qkXB3D4Pk7PhbOTR3XbO2l5ZR1PB11QOLrMZkB4ikQh39OHi7OTjNWZNEinPQV9QPvD0fOB7R3gh1jjMbrM5x6wEMA3k1OFmjHwh0PrM3R0yilTQNqjEyiknjMVzM8W62jE4h01cHnjMHrOihA/R1Fgn0uObNOMuPbdOdzNjcHLcHHQMMh1HNPgbM61OQbOO7OON1TeP+OFrTNRMHJh3U1oVTOiTN9x2IsCNDEB7P5GEVgYawM/QPnEOh7MaMG+h2B7MDjFITPDjlHPgyh1oTMWammlhP0DgwNCEOgR2RbPh7Mp7P+DF57MgQpTjHx7M57MoB0Oh3QVpjbPUTMV7P1qmeh2stASAnB7N1ENaYgJmFV7PGOKPbPl7P28qsUYCTOAkPxjIT1Nd7N2EN7TJu7mmTMuH2/ojmMEl7OCnEcTPkTNNx3Q7NBTM8YlB7NpTPdx2pTN1n3BkN/ug17PyxwFH0Fjmr7OXwzTL1ux2jNFuaydZOz7OJ7OOTOxjlMEP+7NGTNjpr17Ph7NLKbkAm17Ocqa5bPth2lH0pmEwwOlrmH7OETNopqD7Ph7MSWi5bMl7NMmgDjHt7OYkNNh3gTNMxoaEND7NEaHAHN/7OTrleMHh7MEkOtDE37OwsbsAlQHMVaiCAkl7P6J0AtHz7NItLr4OZTOfx3pgbM4PBE7XUK5WPspxjmnCQOHyGdQ1nDPlQM9xxrnAiB04jNnO5TFgzgNkHOKAK4QgLgPGQOk84RoorgOzgOk85hqxxB1MHP7dUoB0OB3MHNBwlEHNXyFe67/DNPbMbyFw9RBjMmjPg1WM/kk9Pa1HHo7kAmMB3ltb5KAOQN0HO3qEvgOQ7NqDZ6UVBjOZRJcX1LwBSjM1bO/9boU0TgNlrP7+5NbPXcR9n0qHOQQO1rN0B6NDHkjNlX2RgBUjMW5E0Va87OJQNsX3DbP2DIzvkZHa4QPaaOOHZc7M5QMuHOYQN8jO2c4vfnbbNYxGSVbjjG8HP2nzrmleB1TyFaAETiGLbPxOMG7ymWk7gPRHPlAFyHNsHMs+rT2qiZ1eHPYTkajOV9mYK4nbPiQMID2lVJSQNzbO7yHx9aDgPyQNPaGJHMCHOg31VHMbbPZyHdLz7B3UjNhtBXW5/bNkl7NHMNlHVHMKTktHOg7MFHMcoXsAnVB2032lDHyHOgt0sAnDHNU0xwjNqHObDyRHPx2AgDmx6GtbNSeG9vmKwTzHPY7MMErJjF47P4ErWHNYeF7O7flLZjNdbOcj1BHPfbMweEnu0+HPOHOEcBUWki9MO5F9HP7B3VjP3o21HO1a02AlnHN07MBHPHHNFQOKeHvP687N0HOkQ0C7Ps31AunC7ODjOJeN1dNiWAgTGGtEgh2/c6wTF/B1QV2KDNe33gnPy7N8DklQDK7OzjOq7MUKF67McXlnKB8TEa7PnrNQ06MTEwh2YKHYnNRtEwuOHjNSY54nMW7P8KHthgknPG7OXpDCTE8EW27PO9H7oXbNMAbMy7OUj3MlTNzO4WHXnxHdPvjMSEUMHD3jMNzPndMwbM3cGZW7wHPgTMtc61HMOh02aG4Il0TOWzaLJhz0ns5zJF1inM6OEN7PeaGC7xxMFJ7Pt32iVFJh1p7OGX3f1Z0wMj6qsMPmDYsAnJh2VyG1HMGnOZ27sAm+h0QDYsAminNOlor4XUTNDtZ5/kSnOqnMTlYpmFmnNWnO3ME2nMs+rFWnuwPf1QT31UF6p7M8TOWzZZhS77P0wMmj36VHswNenP+nNCViKh3kTOvX0nWTJMHGnPoJoD4WWnPyiURDFxnOOhitmGeh1431I/nRTMCj1yUCZnNFuHZnO1+BwTNdhSGPVlPF8AkuwPUzZG/GtmH0B17DP5TNnnVIOzA22hpOE5D7pNTyG8RmHtOrOOoRnQ20lWPtnMTbAzuPhW0ppOFWNeXrseO9WMDnNZpMRpN/xa5pNAkmvnQEl1WR0fMXDWP/tOsnrlpONpOf+DnuMRpMAXqzWP9nP05hQZOLnPf2AjuM+dMT7rvuP+NNGgUf97rWNHtMT7rLWOhdMCgWHWMUR1mgUuc6Sl00ZOGVB4eOTpNjQB0ZOOOO/FY/WPzpMLFZ0dNkxHznNIeMW2O0lZvnODWNPnMcdNYxH3nN7tMPuGY0Dg2MrnNaZhtpPCdMDNl6dNAG3bqkSdMPuEqXzSdNmsWXdTg22hpOEtll34Bl0hRU42MAXPcIlceO42NhG0d95TCEYXOq06AZNAklkXMgZPXBFDkHgZMYkmLnYNpONyE0XOwZOgsPEXM6NOIZPLgWt239nPGCjqeOMXNi1YedMksM/UQ4ZPiD1SGF+dMq1EiXOBdO6HmgeFg+P7WOgeEUZNmOOzkHUZMEdN9G1ozxxdPUXNHzWJdNnqNBGEsZNeEkSW0XpPLpNBGEXpO/nNaXN5dOYhFJrqCZNg0kLglQeMrnM+DoxeO8XPdQHu2OMDOOaOlg4dTGCxF9dMoW3Zj5O1FtdOfrODeHiDkKZM9g6IKJaZN9dOAbNQ06vTEp2PM6CddNmZPBXMk84XTFhXNVaARXOWZM67Pjy4xXMLNNAcPvNLLNOW7PkqChXPrNOuZObdMkj2gYBkj0NKAsuPcUB/TH2HIQx1u7OHAnHdP311e7O8nM+7MAsWVZN1uPbFZRZNT1NX1AreMNXNPEjg22vdNL63vdNhj2NXPj2Po5MigWIEA89Orx1keFFKhA9OmO0SgUXeO92MT7r1XM9XMYm53dO2W0ABD1ZPNXOqgWI9MWj0rXOX2PH2P4G3feOY9PrXPNZNI9PyzBHHld2Ovbpg+MjZPEsNk9MUtNEXNoKg45EY+PqeGUNlZO1KeFYnkLMCZcNCzAXePVVyK1yZON72NvXMY5PQbPQD3K61duqTJMu6Mhg6e+A87a432OzDDRPt6PyG3yxMP6PyG3CpOGxOVANtRO9BPw3NdRNOxMw3OixOSX2Q3PspMhGOZOPg3NfBNA3MWpO43MUnlTROS6OMGG6kJL+PG30k3N/4RrYWE306rrSxMt6Py8m03PQGPy8kIxNvxOkcMuDkJ6P7FYH11R+PJX2VbHXROb6P2gUYC1k3ObX31GG83N03MbkHGxOmGPzfk+pP06PLxndJOyJNrG1MVYn+MqJNnkHbdy/ROyn1i3P3RMs3P1/kExPs3NnkHCWrU6Pc3PCmSQxNnBMuGEwxMBGMPkEnDz/+MMJN8sMW3Psn3M6Mm3NoxNp+MuGE43MjBNVGFQ3Oi3O4LynRNCmMOJGVjhoBNf63KhlVRNom3grp5xPJW2y3NtX1uW31JPS3NYLpqJNy3Nmm3x4YsxNW3O4UER3OX+OUkmh3PG3OycMa3M63MOJGw3OEJPe3PMcrTRPUUGG9qL0Hpn1pm209xgxMRhOnW3XxMS3PugPGJMy32TV7R3Pk3NPj6h3OA3NPj6WxO7+NQG2JXAZ3Mx3MbV4pyhmxNFhMtcMq3M9n1VX2N3MyJOJGOuUH13NK3O6gOxxOM3M6xmbbqaJNSUEfJKLn1Y3N+UGV3POhNmsXcbadxMBnCAlbq+BjxNoJM+cOz3PyGNasOhzl+JOCGOTV4R3Mn3Pec0Z3PxBPOV4W3OocldX1P428JM2mO0LZB3MQ3M7V6sTOF+OpG1Fn7i3MyGPX3Mr3OVxOs1EEfBNJPk3PvBF0dTbJMzm24jJmJOQJPdsPA3MwJMqGPtLYr3N2JMDLaVJNZX3Kn4gJNd3PdsM33OMxPoPPexPQ3MvGE13NAPOL/wJJNAPMAPMEJOA3O8LZN3PUn28Lat3OI3OUPNS3N/3Nxy4X76K3NTn3SyBJ3Po3M+mn/UiHBPOcm4PP5JMf+PtLbYPPIPOy+y8JM3BPbsNIPPFBNK87JjX73PIPPBCoVxM8PNneWoPM53MILY/xMaRHc+kKPNsJO+BO5zGyPPeJMRhNpy7wPP1BNczESPPf3OwvaBJNdX2BjVIJNEmOyzFn3NaPNwy4MPNbn3qPMmuDFJNdxMj1bUzQEJPJX0mPPx3MyPM4IHCJOqX16PNPxPJ3NnjWCPNTJPTLYiPMJ3PTLaKPMuaFVX0qPMAJNoPOBPNyPOjX2PjX+POkPNnKICJPGPMePPB3OyzH13OkPNOPOSJPzckGXah3N23M5PMj3PWxPmPM6JPKhOSzHj3NMPMpPPaGPkhHSh06mMQW1huA4XSExNwy49HhQmPGPOPxjGJMn3MSEB8PPWhMezGnBWaPMIrKcy4KOQeJOeBNPG48yDCWqhJM1zEOJMQhN7jUPlSaPPGPNUiIVqwd+M/1asxrgn1mPN347sPNjPPjpWmPORJMtpVx3NqhOxJPEhH6YhHxNePPKL3JJN03Nn4D13OE31nmkuJO432XPM5JNAPPtY3cPN93O8J3WPMLPNPPOh3MXPPuBT0JNAPMfPPaX2P3OH1bFPPGPMonyAPMAvMtmGW3NAPOosE7RO/POcRFlJOxaECfbdJOQvNVziDJMKhPf32jJNGBPfg3oH4epNCPPH8VQKi7xP78U76CLJMQW1H3Ny3G13PovNE3PtPNgCSGpMg32i7Ou9DP6BPRAvhO69A0vMARPbKMk87+BMnJMgpPry46uJ/JOARONa17y7lh2vJPVmPKyAMvOjyB0vMiYN+qkHzHfJMuta4gJXhNvJPcvOzNZzGKgRNsvMWyByvOQRNcvNfF4wRN+pW4fV+uV6RO0LaJvquuVavPGyBDzGjmO27ZopOemUYpNxy7/kS0DazmNt31lLZUpPcP1GvMBpMoRN2vNJ7aIP3WvN5cmepP050RPNT30OvMevO4WMmW3iPPjRO+pOYNbkpjspMOWOCzF9zH6WPCROKzFSpNiRNH30NjXNRNhROSzHCpPqWOLjWyuJ6pN57zDjW6mGhRPBt7P30Ty5u3NN75QWPePMg3O2vPevOemWURO2zHRJR6pN6vNoRwupPsP0XLn43MkpO1vP+vNuvOiy6PgRRzG2pN1y5amQOpM00AhW2My5bJNEP2ECTkhGUmCevN6vPaKYSxNFvOPW6eZEqpM1zFf3NyWMu4kjPMM3MypOLPOk+iWclJvPEhEjZEeWM6WNzvMbROeRNoWMjPO5vMhvOdzEGvOspM8yD0eTkpOuW3iBVs3P7vP4EAi3PbvMhuNtRFVzG+RO9HDEhHVPPSP3sWPEhFHd4Yn2BWOXaOYZZ0pNyRMNzHYC2RWNM2T6s4HvPwpPJCXRWO7vPKpO/vM1zHzvMZJRBWM8yBrvOn303HG5WMWLYthDlNIERk6AiFDkqIPHGyqLFWPq9N1gxC5LHInRvcGYfMyEz79l3rVVe409XIDlrBCpWH3cxPU63HQOrzpLHg3jmnWjlCIUmwspBnUoiowt3DVJ6Ur39nXky4fNWkPGO5f/AYfM61Ig1oU9baEAofMcfNjXglD1ITqx61pz4JLHjCoTQzLe6aLFXqAbKaUG3SfOqLGhvaxsTg1JuLHenUOnAvd1ifNmHEFaimcKCfP/hnL2o6tyGfP5Tln24GyrJuGcfPenWSfPMfMlrDjKmUOIV60qfM0nEpCxLN1FNJofNv3onN1FNIhLEDtAmGTUIPDLH1F6+fO960MfMBfMxHIKWFtLHFPFgUo7WFWfOOgoWfM7WFCfP1F64GJkyP6cTGO7KZoGfO6fN1LGcFIfN25hp7/FP/Lk1r0fMCRnj5I5spHIP+fPNF6HThEfPefMhF7cKiel7PRFe9ZyJiEfMaNK5LFhuDykKYfN1PzCDa9vJ8fQRl41fNWnFMfMtfO5LGLuCufNOfNqnGBfNEfNofOiBisuhkfNBHGcbCuuT8e4lfNTfN0t1eXUFfNEb7jfPZfN8LGnS5koL3m3RfP06WRfOmfPGO7QIbJN0lAZGfPtfP2JRRfPifNIfKCBDiUM/KApLHlKL1fNgxD6qDSb4jqA5srWl5dfOK40Koi/l6DfPs9a3GA6m3vfNW43rfMjfMpLH29WefPxPGTfPT+qufMsGEGRnaUXbfPlhnayip9ahfNDe6IqpF9bDfO2e5CLEffPXsSSm3BfOq431hDsWGafOK40FhbT60sfNfKmCBBgUObfMDtJlt0fZBRPDE9Yk/MoKOdMAS9YerkBt3jhp3fP+nE04J2oPsPJZSWjdLROjyfMJLH3Kykt3jhq5LEg/PoyN0LFJSXafPZG3ffPXxKPfN9vEKfPSQWQ/Mi/PsmPDt0rfP/zHggag/NYfOvzEPsaHupI/OHWC4LERzoSoOtfOGF57lL9t08/MJLGalKy/PCixF/Fa9pWQHLe4M/MoLFC/MNQmcLEoLFmjifUPhfNYamwd1GTHGonv3Ji/MTfP0LHlSx0/PPfNERKvfO9fMJLEwTCa8QNfP+/NOFDc/Pe/MSO3bN1efPkfNVA4n8jBwOzfNU0yefPvTyeHGrp7njUafPM/FKMrc/MzzA5fMB/PHt3pfM9nGG/MTIPq1J6fOe/Oe0P4/Ou/Oq/Oy1Jp/OO/P5yNCLG4LETyx2oOl/PYZ7l/OF/N1LGXMXaoPxfP50rcKhtuE2/Md/M1zzSUmnTlchKnYagUkW/OShJu/Pjhp0LFXU51/PT63a/MSLEF+Uc/OqLG2OHzfPG/NLTlSIUZ/PaWApLGB2ER/NCRIQRljhK/fPaUH0HHqkrLfO8fMU9YL/PeINX9J1LF8/jXWjg1LhfPL4JId1y/NkLGj/Ok6xp/Ot/MGm3o/OyV16d16tLw/NXU5oagHyO+pzg/PP/PlfNR/MsOGk/Nh/NM/MXfO5LEX/Ohd14fMJLEn/OdfPbzSsLGa/PVfNjtz0LEb/N+fMu/MCea7/Mf/MmRm9hJnYr5fMWRnthKo/MKWHY/PT56X/Ny/NqAkh/MzG0i/Pq+C1GZ+/N+/GIHK+/NB/Pz/OOGYF/NK/OGF6Xop0/OGYSynH0BJO/MA5D7/NiqrUAv9kHk/NkAuJfN9vHD/OlNr8Atj/Mm/PzTi1nLi/NULEC62dVpz/MoRn6DgkAtL/NoXGmn45/NnPEERmA1rTfN2UGnTlaAuL/MUkNFHYtQ2B/N3/NNHLx7Iyl7ffN6AtffMsAucxYEfNklxQAuELFhSrYE0KAsxxY97RWNr1XXQ/OI1kYAvrvIOAt2CoR/ODfNPnFtMBO/MWAu8pjSAvOAss1kIAs0AsoRkRbqH/MsAvMXFC/MlvEWAuU9R5fNhAuf9KI/P2AsoRnpDYp/P6/N+/EUXVlfNw/MmRkayYmwXXRE8nCcxZs/Mh63FuRvnEA/PH0NembGjYskPGvkMAsoRllAvmAuxAvLdL1hCpWHT/N71IOfPtAt/zFUvNlKC5wmVeH9dgf2DWWB5LE56npMUg5Bej4jAuCIWETIg5AYKD2RZTAuSvBMvPjy5H8EDAuKzgzAuHqD9Avp8BuWDJlNnF5LUnValbAvUKBzAsBUn7At0n7LAuDBHHAvDAu7AubAtDAuyYNdmPNKmyXlRvkv+aJuAoLFd4IUUGPAsGW00GpqvnzTjdCi4LHeUoGYMd5SHZ2c0kjL0o14ycKEAndWkYvlvAsS9Zh1AtwUQgtXU6/AvWW1yCbvAtggtCUFfAuJuC4LHf/Oel4wgs9/O4fMoguIgtM/NOqMIgsrU6AEjsfMSmYhuPEAtjwUgpWzvPlhLw6lpYP4Pw9nG+YwmfMo15TELH/OHLL7fM9IJhkgSLHUguQxa2ZSsAvuSx9W0QBxlYMkbCMLGxYMw7KY9Y3/NLkOYgtv/M360QgtjFX82hHW3KSZPAsMqqcgsFE3dCisLGuPRKqMezVRMM454Mvko16BLw5FVKfOdW3n3DdW2IHLW6nAgtHIgWLFKgtsgscsU2V36vn2YPUEgWLEmgvNBk8UCsLH6gt5W0igusLETELvkESguV3gWPpQl5egsUYAS6mAWaNxzCAlEvmOgt+qMYeLnfPaMO4GgS9bZMMV604gvRgvkAunMP/Ate9YxgtuqN+OBGgv7s4VKhpMO6gtOLFuCJkMMeKzJgtsfOCqNpgsU9Y7aRpyDZYMggtOLHME2xYO/YxWguJcbkgtdhRbtBlLERguSRm5ixlLFCguuguYLw5gug6lFuoqgtbBIKoiUV4Sgspgsdgtkba77Im6mhgsa9O8nO/XNKxONKgvNGMB0EI4jgPlQM5tPX4W+QNjrbzgNJHMerWbcnBbNgl7pw7F4UOB34MAiwCcHPiQP7gtfQN1HNlw7F4WLgP6JkQvzAjNzbPI03XgsCeFOjZFjMlbP714714qElzgtWQKhjOLgs256qHPGl4FLUfgNaHM3144TO/IC/CHea6AQsrgtUk2UHOmHOqpNoBQWHNRl70oPrNE2HOkk0zgv2HOEl7r16qB0rB0XVxok2kQPljOFZHzLWeHM9E24QuEQP1jOnVZIk2zbPwNHh/TzB3tjN800Lgtol5ajb+QOngsgQvYjN1QPma4HgtQGXlQOSk23gNol6kja9jPVjNd94ojOzgNwD52wPRB09+n6jN8jOKZAGwPngOzDamQNsQtBc7qQPiQOSQvqQPUjMuD4FB3/bNKQsvgPSQvQQs9HNgl5WD4Q7PGl7zs2CgmMB2sBnlNEGQvpD4THO6QvMZIRjMVbPwBkqOag7M1bNmlXxjNTo1ZD7DB3NbNJD7wQtbHMS7UtS42MEIQvwBkz8yUQOKQu6LVGB2JQOwM7JQMJQMkY3aQuM7MMV5hQss7OVl5BQt5QPXCGaLWvHMO22KBhoQv8Qsb03fHPQBkaQvBHNHsO1dOyZOy6COFHAh0K7O1iBsEWVEkZXNDrFFQsq7MiZAojQLjMS7OYnOaw7DrG4EXYeBhgkbjNInOVK7wUn1Qtg64M8n4nOZzMrrEPgmdQtsDObrHknNRXMes7iVrUnO/bkPMl0nN3jM7NM8nNbZCDzAu7MWGLsnMQbMfjNQbO2DN8nPBq6P9METNNF1rQvSTNhnPFxMYQMAHOETPRjYngvQTM7QsWQNRMG+h2bQuGTNb7PD9NSTOGTM6nOYpPL13QwNp7PuZGMiKeTPgTN5iCoTP7QvXQtOnOT7NajaAQsOh2KjbyTPUTP/QtUTOEwP3JmMTOT7NAwssTPdF0BZXEkl/QsbYXcTOPaMqa78TPMwPxh2yMBQjORh0xVxMD7Awvq0AgVxxYHvQu2TPeRbNfidmFetApV3HRYarF77PZ90zRaXDPkwuJSV5JniwPJh0Eq3CwNGTNeJDmh3cTzaLZZYEuTNWmCxx3swvEgleTNFRbBfDswPAcQYRbJ8qBTMyTNuRZs3QiTO+h33IVWiZ5nOiO24ws7h29LJiwvYCiUElpTOyMDKTOAjwRx2qwvqTOcwuK1yYwvkwOswuaa6JLL/jP4wtSwu3DH0wslQoWTOEwMQNARTPgTOSQsmwMTh1764WwM2wta7oJnPgwufcB2wMqws97oiwsm3hOpOJknuwO5TPpqPswU+PmEHPS51Bwtpwnd40MT4UHNoD3K50MT40HNl42Sl76uPi3lW535c38HPL43YJBFHM8D1S6NHgGUD2DY1OcMriEHV227FRTJsrNK11IJA7521l5DnlVZhkrMPo2ZL1zfkhwtz7ahWk8D1OXbdHN/V1S42T7YaHNh50LXkKPMKCkLqPhXYGHNLV0JY2twtuDEp526+W/HMpyHI138Xb1wto13oY2UPNhwv6D2ZKEHHOnqOsV6LGF5wkKrM7nlSHNk12yY1sPPW7F2D2K+WzxwvqMMY3MPPIIkfqOZL3Bwvhwtz7aRHPL42dwugdGmaMMGOhvYsImnwvZioj2G1wsSPoEbHKrOfnltwtPwvXkxPiF942j4AcHOlwv7wuOfyI7GsD136NVHO1wsKrl3wsj43AItGwlY10W45NwukaNZmn0aESqG1wsIIvUaNbl4gCAgIvu51wL0enNDqPE/ZtWoJ8GD43zhETwuS40bfbT+pISEzqNk/YdHN8aNcWmyJOIItCaPzhHnwtjD0EIs2CljwsGn1QClzD1wL3zwvQIuTmlrwvEF31hHnHPkF0/jloItQIu3qMW44cHNo42PqO8IvlCknD31hHcIv+D0EWnMm5cF2DY0un0vwuBY28X00Iv+D29Avd4AKinbrOvfYKinrrMUnM5x4DPlyF3LWlBEKNKorrPNQvRmN3Pl/MGiikHPkhzNXrPUuOZp67Pn6F1ZOGOIvmF1LjP89EuIvjoVZ3ZbPnPrM4j3eXOzRDjPl2F2/rO5XN7QMMnOJXNBCDXirlarFaPlXNFIkcnOlymndPVXPQbM+7MMT5+u7L8HXF3JIsv0rWl5f10MT5NfbF8FpIuchnp9FJF3Ex1ixllbEKN3pIuo7GEbOrT0+NxG7EzaNKT4xnM1iGUbN6T58It5Is46aQ7HNItVIuZIunaONIvBDFuj0QT5RTIpyG7aNKx17j4gXJ6N0UEPNEB2nOlItDIvYz2cbP6Xakp7VME9ItFn7BwtSbOe6Nrwt+j1zws8ymlIvMPM8yll7aCV3hmkSIljF3Kawu4mZL1p/kGQ3kLNZxAW/kjIvZx1z7Z68SpIug6N5KHlIuxuDpx2T7aAIkFBI49nhXZ9ItjF02BwbfZj6rYz3zIu9lp9CkyN1q2kwFXVItsmRVEMMXbDwkmbPXnnbFEbIsyobz9H9F2Z4CDo43IsLaNUqEgIsDIuhLYePbgotpIvoouVDHQotIXzKOE4otGPAcN3PDhdx0nLmXiHq7aAkNtREZItPF3UEhRLMUov3Iv0YKQkMkosEbGFIsFH0ZPbzws1Is/wsu/nmj1GENYovVMHTIvF2ls0CtIu3ItsyAoovjF2FENRPYYotCov4yLYovDF2Z4ARWjZ60youhxAHHOlZ6hEPP46kovniUaLM66nXbE3uI7zyEXaNbzAov0ose2k5OS18HMos246pnN7F2kbMgE5yotfF3CbMgE6TZbgKGoosPZVp/kbItmDJ4osKou2lHgqHKovEovqwJLbHWbN147PIt7yqJEOgY7+ouYVj0kOgY6Uov1BI3BjgWk3ATmotqJYj46wMBe7GYouaAMebGJov6JAxj0PIsj446fb2ov5FBikPCY4UIvhwyhotRmlv50BovrEMDmnSovPF2H46EHOeota5VnPafQlZIuTmkdHMbIvGMGI7GYovqroDNFTQXXUIEWlanMXIvbmMZChqovGj1Ka2NvEJ8Etou7oRISFwos71ZhwkQovjosRFEbIsppC8alI6PEIuUWYsIn5j2vL1/hGQSHtovVnOTgvM86667YQhXo0AeBgbVtWreP0EKxgHEKi5pPj3o1xHGARaYDiHo17osXDZ7fikv3LHFd64IHScj0SRkPouMdjN4qAzk3ouZoMycCm/EXoutrIj4rfhnTrVU1DR2nHhmXrW8jR2P3AYvbotb0PMD2nfNURaVjAhP1HotroPhsohP1SPl+/GJDbVdgBY0VggKjaSbBoYvN4o2RlMM5k+h3t1OFqNWHPo6notpDxGfNS5Ofot78FmfM+DbpXwM6H/oswYucBgM6EeYjFUmtUKFP3wYvZDafwvvP2VbYFDbRGoiv1vixBHGNUm+cTtf3PosAIuSv3CbYJDY6N1+qgj4rfou+7webR/otNLGQgk0YtiErgYsqUopRBKYtkYtYqbHP33ohmHGrQ4a7jEtnfovESzCOPjPEFfN1JMZsSQY3PospHMgt18YtkHEaYsvtZcYt1yWXovoYvnot/uiKYv1wAKHHYw7jZToYsPSVC9WJd1sYsTUlzRq/py+Yu1EGCYueYtJHHdDFdojtEr3osmrlf02F9ku/OBgkZiJvovGYthYvqf2DRwdUlvW3Etl0Yt5HPBv19+qMw6CvDhv1Y/jHDajdJFNhyYsjFBkDYRooEv09bYERlYJG/ot8SNXHFQYORgBtt12YuIDbdzCipyBYso4RP2yCdatYsVCwJ8L3o0PSUq0iSYuEcD3ovdCayYsxYsGRnQDYvazzN0a+muh5fUj9YvjEKvTk1h7BYuQHFjTltYvxYtGYt4AvQFOnNypHG4Yt+NZcfBSYt7/ENETCOgEYt0Yv93L14hiEpALilDbHYs3v0kRnKM0HYvf7EVHG++m8jQuY25LnrYu8ZTuD3wHHesrhYuX4pvYscYuPYtT4CHPVqW0gY3mcbfPX/Yt+6FuYvSkzDYutYukQ0rhy7YtwoCHPWzW3RYUYYvP7HA4uLYvq/MPZFq0Dqf0I4tyz7d8yd1yfYsyHEhzrhv0SprdoNSIU7YviNx3Yu2CVk+jvt2lLm2CUa7g+HHfosX/PVuJPouxYvp+DEmJ3ovkfPKC29SI9YtJHG3p5Q4uuYvwHEP6kD7xnou84ui7wfYuNYsoGDdYsDYus4vq+AFswM4ujYuS4szYtM4avQ6i4t9XQ4YvM/GBWVsyqMYt7Yt84uJf1aYuNWFc4vhv2EYvCHGFWxN6TQ4t8KlI4uMTxb/GzYxqrg37EcHEh812KoCf3zWQsHEn71ev364vcz4Fpa/v35YtMz5YhNqz28yH7/NgQzLCGNjmnTlPKH04sk4tzTmGYknYuejlF/GeYnE4vIYsKjbrOnw4vnougX6Zf0E4tkHGIKofYsIDyVYsSulK4vjtBXYuG81i4vl/YBTmMLip4vZYse4uStSZf3O4vsECp3jq4sO4u24vRYUpYsu4vk4ubYsq4tLopB4uuPlrYvYule4uzYtSz6e4sSf3PotN4tqd1WYt14vM4sc4ucHHV4uOYuEHFAukBYuA4sXSUl4sdYvXov6+Fo4u2YstQL8YsZ4uiYv/hzeDbL4s6t07HFz4tq4sJYut4tEX6Zf0Zpa6HHj4uV4tYvk4i7C4uT4uuHGNYpXosI4vb5aCibc4uBYscQ7NYsg4vjHGZ3SZd1CPneTnG3SW4u19n7/PPlO3xg/YlnYs34vmul3t1EejXHHVHJ2HFJ4sPHHU4tP4s5HHt0gvYs44t8snjCrpIPh4sIRnGI5qwS3YtzTnclgrYuEqCnTkYEvRYs8gSIEje5Hv4prHGm/FYYCC1iq/H34vlnrRYtsYvb5ai64+Y3n4va8qYDhQEuoAXduzhv1gixYFZ1fOZ4vR4sV5bsEvwv1UEsZZOQEsC4s5HElnbN4uT4spZOkEhMt334vnwbo4txHGUOimYsCEt8skGYv6glwEtYvnXfOZ4v34sqEuiYvX4u4ly6Ys37Gb4sZNy9HGQHFtHHb5Z5Tw7osN4tb/E9mRdPHK4vs/EAaTLYSj4s5HHGEuQYv34v2Et7f0Y4s5VI2EuvYuA8AaIvpja3lAntDhtDkTDeEuNqAsvDXAtej4kEsgnGBEtrAsBz4hDjE0A4sqLAu+z4IDz+pAxtB+EuETLxEtP2ALq2ZXHW4ApEvaz7gWo9dAZEsiYNX7GwnHAVDXAv1pBxEv8tA5Es3AtS93RUnnCSiHGA8kKgtxAQJHEfIqMLGBh7O5S7/35NyogsQqFP2xh/0dliHZ0jWXvawb9mMiJ/ZFeuXVHGgWQ1Evb5zwYj1Eu9gtbPjtEuv90NEtyz6vFp8/3uMT052+4skYvVEsnYNt4th/3zEud663KFZkOa33jEv7s6qYuJtB5bbcz5XW6/yG7HS/UCHEuECSl/3F3DCHG4RmHu1XGUuZIMHG3ouu/3J1hnEsWBrj/05soXSVHEtG/0G2RlYNXrjVYucTgjguR4veP3LEsbEue4v7Ok/t6tEtOSCp3hG/3rEvcz705CK/0tEsrEscn0J8HtxBmgsD4CwksdEvSpKaHGTEuCO7cKjXq5UpWjHEO/3zZquHFlYsH91fWLdW0QkspHG9EsoktDwkvEuPEvsguHmDnEvC/0+3CG5aomLHHGj6VOguHmDCOi/px/EtBguE3R5HFjEs1EtV+GjEtDEsIktoksnOm7ArUHEsYtJ/3mhI8UAAEuIYuc/3Qkt64BRYia/3wkuT5b9AiyYv7Es+bYrHEOYtOnWUmCa5GBHin/2JLIWBB6kuQkuZ92XAhRMNSFEUkspt2XhJ6kuckuMkt2gtaku/otskuzvMkEv+YtikuSxy7HGgYtikvTEsvVCwYuipxAkuuHHI8xH6HcksO5abd6notOkvMkuHHBWjgvgqsYYRktiEtAD0U7IcECuHFxkumks4kuuHFnLIr/2GkvrrbJFmAYud92QGyqkvTHCb/3oyghuOB9gMYtX/3dCj4HMEDJC+1pnG5zwE5OhiyQ8E1k0k5NoMVpyEAFzCu3Vks70Ryu3wu27yG9GDM5PgeoxnG1LxIbm1e3hJ02onWDmqtSg31cnGh1mug0NkvkAVvO2gKG1kv9upuJ2Gk0mnEX8RkG3it7S5N1ks48GrksqJ2nKzfcHZjywZnMJ08nG7ksXO0jMXPTand0k+0TkszvnPmzTkvkJ3SCXs5Mzkvit4/O1jqFPO1htCa+xW5OjktsD0d6rWOlNkv8326+LT5MVmjfktYu0/e2dks8HHlJ2zKiLHPLCw/5MYu1iEoAUt8KxHHNo20OJ3LkvUzYGZzh5PhQALkvVQg9O2ZBZbO6m/gk5MIUsGD2WgQBZlhZBHHOf/hnktx5zCQ3v9wGlMu+h9ktWWNxJ041K4Utx5PsDgGD1cSzxDlfksGD0fkv7ks7ktyGYvDmtUohTmL3BrJ0HkuV3gv5PMUv56HYe20IDVksNNDjp00UvW6ED5MDO2Je2SUtDFM0hhZzZiUvi73hnFCUvlJ04UtnLkv5MYUsyD08UuAu3XkscUt8bkIUvuj26YLr5N+nEFTmMUtq8GrWz3fPtIBrp30UtUorhu1sUvYnHcgJDFOCUsZt3lJ02Utat035MSUu+j4v5OgUsU9avnQv5OGnC8O5vGJ3J1BWJfTngUvFRmke0b9lSUvmDnhJ24lTElPFajNnHL6XxFNmOKsfNGUttr1PkstFRrp3aMVFHYZUsKFN8r2pj3IKbAp1zhSVp2JUsfu1/xomZmxUsYp3bksOUviqxcp3OUt+UsEp0845x+AlD2kPh4b3OUu0BEKFNfkslD0/kvQbltUs845H5NvksupDkFNir3onGu4zBe29shK86NZY4p3OUsx/p8p3DUssnGD+0SZkhWBZSUDCqlUu5Aq9p1Lt3Qp3qzmNdDRFMEUso9aY0AqFMUUtPU5ljVLJ2dktrt0hFN/kv9D12UvWSwinE6wb+p3TUs1Usfp1pnEVPGuUunUs1ZZOFM+Uv1F53+3Op0RUvPUvup3EnGOgovFO7UssnFb3L+73nks9nEQG5sFPpUveLTap0wUso9bHUt4b3HkvW32vy45b1O/DT+E9WoQFOw0tdo17FOIuYZfPI0uAe0zkuL5LTczUblbUuE0tZFPpxpTTnt21qlMWUte9a1dQdUtenEDWoY0tVUuvzEDLPklPOUs7IkPe1lUtZSVid21UsmUukArCUv+xT/Dl80vDp0k0vc0teFME0vs0vNJ1qUvUbCUFHZqHKUsM0tJUujktWnEtUuBJ3/UtC7UHUvyUvdD1R4zLFMhUuY9ZNBHLFMfUsDtB4UtY+2nUu00t4b1uUstSK3p1s0ukXrr5MinES0vRu1PUui0vG0uJnFteggUsyUtsd3/p11e0HKmA0skUtlnF20tdDkJUss0v/J1Au3enHe0tW0sCVgZm3rkttfMCpZH5POUvR0tYZ1zUv1nGpUtye3Te2s/I7UsZFRQ9beZBkZ2PO2Hmh/KmMUvA8G80uld1Z0uc0v0LESRpU0sinFApzElMV0vYnFUvKs0v00srOrUlPU0up9ZRUt9j59u1241DFNZUvE9b10ug0vJUv1nGL3CceGR0tfzEV+bNJ2dUucSUYlMD0sm9Zj0tV0uvzHBPJH5MBUv69as4TQ+3OUsL0sWJ0j0ttiEHUtL0t40t3pkcnFxwR2Z3OUs70u1UsinFEUuhJ0J0sq6qZ5NT0v/zGUOzWp3OUuX0sOe1zUtjFV4UsH2k60uVgv++2vcEs+3neKQVPxUsA8Es6A65j/J3knEcuId6ryZ08nHNmYmnGCUvAMtZZ2gMtGYYS+3n0ueEv6aD4lpdTDzfh+tAIpK+FHMDgxEt6j5IMtlZ26+3DAthzTVZ2YMu8kGa0BFZ24MsPF4iYSdZ24MsTAujZmjZ2EMuHqDYMsPECkMt5a34MsUMttZ0YKDkMskMs1lOS90zZ3NKn2boRDYn/FLZ0JbW9lOKwjrZ28MuDlO+pzK7DjKm6lgUH1SSgAgvBLPJa6q97x+2G0t5+3F/GB+1o2oIO4Y53fQLvAsHcrrlOHwxqMviemYOlTYzvZ3S0u052qMsS9aB0u4VOaMtGMvgUsXlOmMvdfOQVOSCTg530j6E50khhKnGGCBw53HGwkkBWnGDkpD+1w1qo50TFLuMvI52lkhY51KfK8VOemwclhWnEAMu450IexmnGQVM1FEU53u0uwVOGMtJo1mZncMsiMsh0ts526MsCMuQYDn+3CMvvAva2VX+02Mse9XcpbKMuTWz84Y0/PHwrb0F1wGuMtRWrODY5WB3ggU9ZEkCVMtxwRm5GJ0sJMscmyp8D1nHh+D3+1RMuY9bZMve73OUlpMtI+2EVM9MtZMsPUtDH38DKdMs7lzMxnNMuUgtPELOMtpayTW3HLGAVMBW5Wgt1lzjMtxohR+3JMtcpmI5xeMthEEGa45WBiZiM/PGiTdMvtNDE2CtMs/0sY53VGpGgsxvGlMsrMsAgu1Ms/9ZgZwFrLfXPLQtTgvDYBrhOsX3AiFf32431UmoWRO13OxsYl+Nh3PLpJT+OxPOiUVHH1Z+M/fPAsvBPP/Mv2zFePM/MvP+M8POfMvv+PJX1vMt+1C43NlEHvH1HBOu9bRkTpRMfMsYsvfH2K6Nq3IuRN03OKRL4suM3MsTpdhNY3PjJLMROZ3NUdCSROsBNQGqIBN83MoLHkhiC3M6XEa/P3+MfMswTC6BOA3NwxJrBOO3O5RK9hN23O8ssiX0nH1csvLBNZX3NA66BPG3OIdB0svIsv+Ky/MsIsvvUzv+MSstajzgBPcmMVXLthMo3Ne0qkstrxNXU400Lf+Nw3N5mAUsuvMsysswsvm331A5z+Ne3M3+KoBPQ3P6OFT+Pm33p+C6BO2stEkMn+OcstdYyzBOAssH2FihP8svustqhMT3MkbBKhNQssoQgDn0Sst2sssBM53PWsson0PH0Wsvmn353M5HJEstH6NOXFaNq/MuKxOmAtvBOcssDyTSBPm302TgZhNXnEp8ADn2A3OlZ4isvS3MtQ26BN23NFsshsuPPPneLcstDJMJAmOst2xNyUFfOXI30+ssPFMBhOYvNiAsChPJ3PJZ7DBNksvUuYeBPxhM5gvghOAJPxgttSqImMZn2tsswJOQPP5F27CAUmN3nE/iSShMn3OlsspxOpaE2As4Co9stdX3ouUFX2P3Ocjn2svZsvpATSBNC3Obsvtn1zsuW6I9ssPBMs1lIDblBPk3OLFr1mYvPPhComhOTPNCXGevA5X1ohO/RZRrStBMOPPPstpx0JGNePOLuJchMlssvsvDxPUn04w2dsth3MqCE5BO431cR1TBN03NK4OShOsX3Aw25ssAcsmuAFstRPNcLKIcuj3OtzK9hN0hOtzJ+suyn3gctJhNY3Mgcu7svOcmAcsUX0qstZhW0hNTn3fssEX1/3Ms1kojBwGPJ3MDWL9st4ctVcqUcs53MNWIAhMIPOscsVX0xhPt2J1hOwPP0cvrsu6PPXoaPssXsvIjLBhNzstY7URJPjssO5qzsuWPMq8pxX1bPOVu7/VqYhN9PO1u5nsufxOGe7ictpX2e60ictahPYcs8tRUhNfst0OJkcvWaGdoZchMT3MccvMJOovMFxZmDTMhNasvccvMcuxPN8cs9st5st6cttsvCcvUFLkhOrssacvQ3NScuussAct/iIH+Mlsv+csn+OFPM+csSX1mctecubRNxAvChMAmNEDKNhN3nHQ7VOhNe3Ntjmgcu13PJcvmhNXnHGdzDBNWJPHu6QVR1hPKcuVu5ImiYmNDPM0lZzEDZhNPstpXEGhMH3PhXEfsuJxMoRmoK4BhNzstZxSicsCctIRPhhO8csDtzRhPycsptJCxK7PPrn15akQcskcvSSwu/FgcsdctZsuPaHlAN5hNgcs4J6TctzssfCiFhODGVje6KcvZxPZhlLcu16OVwVchOrsvVGw/PP1hP6yPQcsXstmTzScursv6MXABNgcvHcsdJM7ct6r5M31XnEBsulhPvn0CQDDhNhPNzX0ohlq31JRHBxZdPxEvMBPOLzAxRM3BPh61Seb4vP661NssfcursuA8ugPODkFEjg2XHUGMwMvxoCgmC+VLgpNUqnQvqMvPbAtqWAw8s+30KvMZiryZHJmOoMs5aDXzLPhNo8t8DKw8tR31Y8sPZA1+nyvP8vMfCoY8unJNej7nnHJ3HivPEJYk8vKvM/f0/jNnnXVSrJaG2vPgA4vpFs8vX/a9aGGvM9hXcmmTmODu6tD3RqA4pNzmNvWIkRMOvO88uRWNavMS8s+vOuW2kWKp+k88vWctDvMr33mcsy8sGW2CctIstNvNxAu8RMcpNeW0jqGCRNtvMbcoxROOpMhu6ULVHhHxvMbcqSRMrvOG8sBRMfbwBkV68tkP1ZvNlYOEFoJRPv33MXE0cumpMmW0q8slvPapOqjIG+n6WOgP2qjIUsv7vNcXFCP1HvMJaAOROa8uf9JtSqkWNYWNR8seRMuWOae6FD5632YHGPvONl428s0XZru6ahOZvOvvOqjKo+ls8tJ8sVvM+8sdDLN+OWpNq8uQYDvMvOvPmdKAX3B8skwL6n0J8sVXEWBLSpPLAip8sKu6CROhJJtW1pXEeROgfNAfNe1n8BOM1HnHEN8va8szvNu1mKCDtn2TvNcDLvMts8smxyYstT8uhg6dvOu8tEDIUsvD8sVXFLhMBWPTIBHYAr8t58txWN6xbrNyRRNCHpRMPS1lSsvaWMt8sbCIIn318uF9IqziuRO68vT8s4svz309uNDRBa32mGM7f1PH0dhPvN7v+MrhNaVIwsvh+N2NAn31ShMrJzVejtROufn/8tgsslPMx5W/8tOBPph2/MtnBM/JwLzhYxOon3P8vvMtEhMP8uosteXEg5z1pRk3MrhPXmCYsuDhOcp5oCbB3OiLBzCbCJN0hMECvi33z+O+p5iP1fBPyePgCuEJNwlwXnxqZHQCui9F4YLv3OP9EnCZmsvR+OyRCfn1P8sti7dn2YPOVJx031vRNY1zIyiK3N5+PcCsoctdBMcCvisva3Gjk4tQjm6PwCtRp5r3063Ojk6wCudBNSCsymGvcawxNkmmQzOastK3Mbk6kCtoPNKCvqCu8CsymEUCsjBOjk4DfhwBPsCusCv26MX3FYU47aG+3MDk7F9CYBPAZH4U6cCuChNblD8CumCt6U4LX0QBN6U6pX0rBO+CsNst5+NeCt7cviCvptiBsuqCsuQohstyCtiHbhsuU4W2CtRsuS6MnZx4CsyxNQmkHC6JsuiBNvVybn1KBOAi4pcvsCuPAljct03GFZ34BNO3EdZw8Cs+CuBM7FssKmlOJyuCsFJOD97o5JWxPtcn7ZymBPm3GYi6BCsDzGDZw26DGmml3GLeD6X0/+M/sxAcvQCtjsxZCvPIngPGZCv8cub3MBD6ECvDssIZE9CtCcuQPMdCsRBMVBP48zeCuRBPEi5xBP0GM2D4TQatX16hNsizDCvdhOLXE1CvsCsWA27svMssPYDEvApxNM3ER2pvBMnsuq6ArCtLCsPFowX2rCv46igcvehMPcG9CtPssjFx7Ct2JMXXGvcadBOL3E/Cs/stVCtZ5Mpss24UJe1Acvh+MPcHHX09+N5XkDcvx+MWu17csQiu0xr4BOgivddKGBPkBMjM0ocsPBPUQMeCtCPO3CshCv/Cswiu4cvvBOQiu5CuDCvAmgDCsEiseMo9svECvJu1chM3CteZy9CtOBMM8F7Cul+MBVy/CscBM1Fw1X1KPM1ikBVxcivYGP83Fsis8cv/3HMiv8cvzCsMitzCtM3GwsbNcs7CsPsadctiis+LzScughP+ZxycsTCvFFwqivg3GGTArCtEhOGTB+CtvxMkx49X1Misyi20csUhMiivUivdCscC3Mcs6Cu8isAhMKhOcis2itass1Fzsis+CsoA1OcslCtGiv4CtNJAGivsCuyitihMQisKiu+csU6nKisBctAiuG2CmBONCuait7ctWis+ivesvmiucJhz3NuR5EvQ1PN03EVERPX2ExO79FQivyBNY6wZiurCsuXXEcvZcuJVwPIvbcv5ctGZz7X0jCvWcnfh7E32uJMSZyzKKYmOvCtlX7bcs7CuHEwNcvsCuJ0p+X1iitm/VJhMfCvu6C6isDsucFw9ivFcuOwPo30BGPfh4uwF8mPOCvZIFqhNGhOl2yTctwiuf8vk31M3HtBnzctjGUQNkeCtLCvi/UH+NTiv5wAbctM3Fbiv/X2biuM9SzBM7CtVXSHcuxaFW+x6Cvk3NnitdhOP3MABw4isXithCu3cuPaG8HZK32WcuhYXCmmPcuThOxYWRiAfcsYcv9eC4P0/csVxHAP2432IhX1+NASuDzYgSsn3MavaAStW31Q8vQ4DyWD2mlw8uAj4WqSo8v/JMPa0cc5ISt3hMtmM66DuPSI8twj7WmkISsYx5HPV8vMqvOoStgx5Ttbp31k8tYSt3Wg4SsEX6LXH2mlVmOYStnCvwSuE8sE/1qvOwbP8G2s8soRMFZyz6q6vN2RP3izcSul8vlZ5Tai93388vIQP0YIWvP88vKZzUEgEpN6RMPYCGASS8u8StCSvcmncRMt0uBXGjmN2isGROcSvWitn8uspPEJwv8sBvMsJwKCshvP6iv68uPmPAQPdCh6pOH33RFzGCiyROvvMQ3G/8srvMkx64P0LvMA3GP32O8v0QMdGZv32ZRPiisa8ukRNaStK8syW26ZyASv18u6ZwmCtGSsfEB130CStSR5fXH6SvTR7JCt8RPkzW79GMmnBStY6xOSvN8uE+MpSvp8vEP3jR6uSu2StqxHZROaSu3Tw28ulvN2R6P8ua8vvh4mSu0RMSZzoCsEROFbjtV3FTD8Sun33snwyQMLDgpRPPdjJH3fh5xSuWvOFF0imxt8uQfPlSsO8sTlH/s3zZpKWP+rTyWMVisu8teSvrITIRMySuQEUWRO+SsNPW+aGTvMlSsZ+nD8s9uPn+nc2WmCsNRZjRIB3MlM42AoJOU9+OzDa/3FJ+NO3GSQtC8tShOARYuUCZ+P6CsXSuMKJUBOnSsWvNOBOHSvDZp6iuyD77SuUCtbSseHLvSs7WIbSuKX0lbmPEo7Su2M6vk7XFHdhOELWcBbyBOgys92HQGPnlUakI+xPBM6q4xwCuV+PcM5nStEhOyLXZCj0st5LD/SuVPP305ouY3RMbXHxZAXFKb+NH3G3kph7nnSuboFdqkchNxD4U7B3SvEyuq3Nkmn4yv4vjoyvn044yscit54HPSuKCu1UlvSvz+Nj4EPBrDiuiZAwyt3Su8hrKOEUytbZQ8ysQBMcyvAlGbSuTQIWCt6hNMytoytpis7D5DgZKBOobbwwbgyvnknnbGChMOZDNhISBOs9niRJZPNIpwUw7bYQrBMGytlz1fRNwr6g6gI7a8ytoRrkyul+PNQ4EyssyuQuoPSs0CsKysXMGJCtgs5gyvF3NQmnJfVsytxsuH9ENEQakLays8gmSpQAysigmRVIHStpUBUytP8tlwSlAxt3MW9nvMzqyvXSt3A3xyvmxP+9njfIkyu2ivQ0kRyuiPNu9m9jrest5+Oj4T0GBdCu1pF4kQP+i8ytSzwtT1cyu0rK9T2r3NqM6VytVGPyctgJ5GqyWJNaPM8gljRKhBMj3EbZHTT2RBM7UkWysFBPd1B2yt3ssSgke4iJ0IHSuJslVyuDhOT/j9ysaytGwThT1FxOEr6zeAXCso9mjyutX03CswNU9ytdysO3j9UQvPPV8FBytVcsN8HU8QwPP/3FhBD+yvciu3al4yB3Fi8yurPogz0Uytg5DDytiyutCDYnJKytZlLv6oHSuKtbMz0ayuOZHYz2bSsFRLWyvchMN8GwRyqBPkBNkwxq1rrBM6OnfyuMPNFysfyu7BP/Ctg3jXhSMytPyszys2yv3yvlyuPSs3ytVyu4itnytXytUcs8CGtyu8ytTSS3ytcyu27jnyvvSsQgztzgnyutlb57ikKv8itvx6EKtXysfCtF/T4KvehOBbglyu9yt2aZ1GO9pHjLiGyt3stL3G6ytMRGghMbvSZysxhNj8FJRhKcvg3E+zhrysoyvhwwmys2yusKu4KttZbGitdBP0KtoKtTJNj8GepYJGM6CsUKtKz1VsvcKvwyvsJPW3Hi21EKvnSt4KtKKvh+NMKuhz0aysyKvgyuSKtiJMnSvGdSfyuGxNCKtaytGyvl57BcuNCtiKt2KugCscKtSKvKKuLbZy0S5BM3FniKvR+N9+m35BpiudwnPyvyBOhKszysVBNDwkPytWNYT3FSBkGKvfCtBKtrz3VytkPYhiLTCtQmlyFHBKshhMT3aqKu1csLjZmfydytRKt9Nh+LbehNxrSwKtVit6PahytUKv4Tbey69cuwuXm51ebCHBP/Cuj7QC/rhKu1KsE30X3GjVykbDhKsq9aQLZRKv3IYIKvJytdFGOKsFBPpTAjKvgmMLFG5Ks9+NUsm0Kv1hMLFHBRxJit4ekLKt5Ksk4nW4Lsn16hMaYJAvQLPMDF0AdIVhO9pFisnkyuDhM7sKiytaKuauDiYI6zHq32leknkCfba4itFcznYKbROlemVdj/cuQlGAhQ3KuBKsdyvrJP7KuboRE2GUvOBzP5/Z5p1EStQ/1r3YYStE8uKuAAqtSvMUSvV8HkPE9zOgqt+J7dFWAqspmDAqsIquMr7wquk8sMSvfwwgqtI8vKr44gVoqtQ/2Z3G48soSusn78uN+YEJsT6fmkROpL6wfnkqtm/U93FqSuhwmWfnC8uKW1V3H+2EmvO4pNdulX5hWmWcSt0qsxrnkquElD0qtlSuZwwRfm0qskKsSyvkqvCquMpMcROmKsspOVStj8FOozGWOQP2T3EfAWMtbCROT3GlAxN8uWSvcKsq1g1Ss3HEaqsqyvi3bJWMqqv3KtKRP330KqulflP313p6D3FsytLSuSqse8tORMaKv+SsWW1j8FPKsmRMGWPcKvs+yYWNWRPdmJ8qvcRPODjIfnequNgLuytGSvhHGlfnBSvn6KqqvrvOPvP8GApZ5qqtZSuRquKqsipPcKvz6yLSucSuhquGquGROsqD0GAmRPSqurg7AKsxSt+BCc8xapOYDg9uPz+bT/4KUMEzn/QZl0PnCHP3DD0PL6FlSVrH23INkiG9FWIUkWoNbi50KwZwNGUO9B2PNK5NwcINq7mL+RlMOsUNHCEl2TXUO4yEtCggZzNkMA5YA0RD7BjqtSS6OlP1+N+UM0RX3WyZSO5INoWALqv9kMqvFMRIWgjFUMxCH35PAn2wYOVA7X5PABN+UNHA7bupzkOfwMjA5o6W4oPLqvxkgZQmvwW/0aCZxbkOpmBcjg4IOEplFA4a6LS0PEfEdDjmINVwWrp7BZxQUPcl3drLXwPOUPvqtxCTM0MPqu9ILBIM3queSQEn0XqtnU6i4o8UMA5aELmLH2HqupmAddiwUNF0Mnd3POgHquZwNq7miLmYavtqv9A60NBJGrbUPIatVqtvqswat1quoUMPqtXqtEUOSV38mauoMzvFTUp9qtzoPKfFgasVqvoAs/qulqvYAvQYafqsEIXTU4OEK/qu6V1rCDen2MUNAiHqFPnUOfwVsatMn1Iav3nKvqtwatSS6fqVhvG00OxznpSRtuEyIPx54bqtEfNnwVxmDDLLSUMSUNuzn+K4aIP0asmeK/n2/oPHfHroaLoPL6HNZ7sav1qvnfEfqtEatojEyata0Ms15OXQOauKQW+15IQqUn0gYMDvFQopWase4TMVax7Z8avdqurNHvTOnn27qsRI0SlR2oMXUOhl0WghmG3rkOhl3/jzRIPBUNxatXuWCoPq54fXoUX1VoOfPZTQWGDK40MmvGWeIhKpu0PvfHy64FIOEpn2avRn2TIOlIPFGH6avWoMlasumDJavXoP5l1H2yGUNLqtx7JXCrDinrwMFhUsaupUOVavxat2UN1UOKvFFasFauCvEMdjYYMWav2y3xyOSfayvHhavT60pIMDl0YasKm2EoMdl1NthLyOfwV6WKRK17UM7/ZVavcau26G7Q0x2RvqsyjmerwVqt3Q23BbDkP9atcaulqv04M+avq0MX/Z5TIfIPjUMcAM3avOINFwUXauSasn0OzNG1LpiaurfEXkWF0Oxav7avGav3UNkA4YJnpav9quLFp1auvav9hVmvyiuFfUNwmHr7i/UMcAObavCUNGAONCE4X0Xqv52LP3Dg0O0YUX/bHqsEoPXvGY6sQ6vdUNNvFxXwYX3lau5au3+DPBNJUOmvGNNyDauu2UBavE6vbauqlMSoMzatuvH/qthUPGv17TL0SpLIMY6vxFpnaso6tGBg06v/atM6tIfyw6vQ6vZatQoMX/bw6uhauzNEoashoOAauo6ucqDqvHHvGY6to6v8ascANS6tbaurNGE6sGatkA6k6t2oPNasJHaHau86tCauEINOvEDat2aua5Mvat4atM6v73AWm0uIMsA706vS6uQv3U6uG6tvUMC6uU6utINFAPvavVqssvGiFzfX0O0OnNGgIjMAu66v1FzGatY0MpvHRau5oMi2mnNGq6vLe7LIMZvHpSRB0PJpmcyb5uHp0MbvFx6s5avbasQ+rI6sh6uE9IOhU5IMlat1iPBakTas9vHZ1B9oNEv3rJp86vLurQZZl6tO6t50OP/bLgYMX3DUOXNFi6izoPNaskajl6u4IPCtHaauHauDhHpalMatFNKtatmUNgA47NKSatZ6tD6vUIMqvEoTNrasmasT6uZ6v2oMyjMe6uHauXX7un3k6uv+r/jxT0MsvE4avZ60FUPAhns6uHasrcTD6uz6vuTNmvzr0Niv0M150KxBvGQYM014OhXjvF1uEY143avT62c0O4hmPqtUfOEpmOlYlqsmauv6uzqsh6vUPoZFhu0MwSuN16K07fzBcYMpmBIkPwhCC7qwqv3RAAGvAMMAMMMA6umBgGtYqubGDmc6AGsyYNz7nrrRIGu4MMx31hA6IGsYMPQGv8R2ieCMYMEX6MvGgGuIMPAGtYGs4MOg/1sMsJiPI17o+V1MO+YOVNFqvGNYPKYN0GtavHCMO6YOCvHrobWW2xCr6gMpW5C8tJMPc/3XastvEMGsC/1K4NPvHiMMcAO9ILOYPdYP8GtDvEsGtlgPKZqjquiGuK6vyGsyGucA7a6tOqMCMNBAODqveMNRYMU6vNRR5W3qMMC6vEShaqPJYMC6vnqvjMMth1Yl5lMPzMPs0WHNGDgp5W2FYMGvFNiObYO2MMaGuwasnZD7YPC6tIsvlMOKGuIavqYNlgOsb47qulgsAYBM6tAKqdW3WYORgNYXXqgvgbi26vXqDzaHAgtZoRM6vNhhOqOtS111w2QZ3qvdMMktE2eCeGsvYMbvGdatI3raGuJ6t1quLyZN4A3vHqavhW0VNq0tFHoYfpExW24BZfNE5di8qOmEa8A6cpIBGsDbF7VwFGtFgtbYM3vG5Gtc1E4FyiZqTqsKGupGvfH1eGsqu7PJLFMNfNGi7ZFW0i6pVV0dDJUauCW3LMP4tHy66JgsNGvzGt8vERMMjYP4tEzGsFE0ZEBjGskasfRbOJS8TPHK36uiRYNr/13NEObJqGsOYNFqtlOLLfEQT3dSEOqRILUYL2JoUWpSNj10L1xfnPfJp8MhT1s7kvTptCNvfEFjCFghlMG6T39A7GdjuMyxz3ntYfGs7cxhz0vGv+PJwYmfIXuwqOmxez1SS6SGpT4hwmv9A6XGtPcMF4rx8PzZZo2k1j2HT0YmvnNSQL1ZCEIcvqfPkL0/0XR3JBCW1T0Qd08OQ5fHSz3654q5iwmsrj2lw2jZafGtImvdSGGOSFYnQmt9sUVN08z1tSEsmsTz0tCHm9rgT05z03t1QEI5fGaT2vt2OXKkyXZdmimsmYIVT1vtavt1Cmviz3G93p1g9z3QmvKZp28Rvj1SS4icswt10mvqmu4Di9N0cz0Ud0/vhSz0TfGwb4vd2tz0od0Umupz3ud0tgwS8OUnLNIWL5KPGuST02YCvGvOD73GuVfOqmv/z0Id2BuQm8MCmtLi4OKJYmvUfGZctLN1EmvBZJimsOmtPI5vlNfGu2mvVF10t3/GtXSHd+GGT0gmthmunNrymvBmtSmssz3654BmvZT1OT3ud2+mtqmvud2ems9Ymbj3US4kmsr1XgiUf92QmslmuqdZQS48OTBT12IC4iHgGBvT0umsYJ7RmuNmuuETbN3XGstqtymspT3fGuXmp9WIWmt7CF8mt18NGCUdmuyLJbKFmCUtqshmsQqHTIU6SVSPTAmsymvkbCIDg1T1aIVbi63Gs9z0TfG+lwKVJ+z3Dqvy8plt0wNUfz1VmtVnXPz0PCFKTwBt3DT0hGHLgZId3vT08atqbwj8PPGujS7hmt4mv9muKms0qHCdY0RURJI1mvUfEonwHmvSL0cGFOGyBmsumsYsvDt2cmuwRVPmsPmviGHVmtbKELfGUatJmugWvfqv9t3fmvKl0IMCAWv6z257nsssXmvslB3KGrA7gWvKz38l2x7ywd08z0vhU/vh6fEg8Z/qtvmsRmvml3TVhDT3emskKD1mt+mv0fFFA5vEDOmu3mv6svQWvtmsoOGpmuZz1qGGdmsxmucWsjmuTmvafFsWttmudz1EfHMWukt34WugasMWubmvql1jGBIWtomu4yF8+MnmuDeqUly8stfmtCWs0zm4WvYL0VGRbw2mkqBbCrmtnfEadCkWtpmvR55WmtYCO/iWcfEWpTGfHSyo4WvagzFCNOz3q55dYx4WvoWshfH6WtYWuXmu57l2stoWtMWu8hmhd3wWtyfFxmvPmsSfFMI0sWuOWshGG4XKCWv5JB2WutmsDCOWWtyfH3mtamsCas6AYzCPQmteWu6WtKWvuWsZCNXBxPd0GWs8L0zfHGWvSmvYas6ms2WuNz0NZYH2F6d3cWu+ssZnVdmu2mtPZ07mtUWtpWvFz10WvJWs8mu+WszmusWv42GiWs2msiauRWvimtPfGP+ITmvfwx5YnKfGxWuJwlzmt6zbRmuqWtPd1J7opWsNI1lAimT0umuZvABECMWvAL15fE0WtNWvLWvCdgwWuB8YKWvI/LtI0HqYOWs8ngRfHzWuxd27ms1HB6av+PL3z1OWtZatHWvIWtBavqWuSGmofEmKALmuML1ZGEeerjT0KdbFGG6tToz3BWsaA4e+xjWvhWv+V2bVK/WsNzQXANOXQSWvgmtJasrNhgL3vWt+WvumuVatnWuQ2u6mBw2s+WvFl0rWvyLVDmvfsthWvYmvo2v4z0oL2bNG5Wvw2uiLQVWvwWubNHXbyzWu3muscvtWtk2vGmtkL33Gsq8oMaR4mvhGtbvLY2uU2tdWtPWtFANWmssL0DWs9GAT5KjmuOF48tFZNSomtkmu16s4CqmLHZWuNNEfChWLFEmuytEo1Dw2vXmu9fH3Wvi2sVdkgT1/6vm4AArCIOrmL1Q/3vuJz6rtIDGL0MH6a2t4/FaL3c91jVLtGkG2sk92q5D5ip+L0gdBMJDm2v6L0Y4FHsF4/FeL1pYBG2tGL06ZAC91m2sOL022ti5Zu2vWL022utlPvKPhCGmOVgSNwr1HA6SEARL3UOBRL14RUA/Eir27A5GK01LGsOof/C2znQdxpL31RRERMxhJJ2lbL0XL2MznpfHp2uhL2Z2tTdlR2u2zkZFjZL1CHou90lWsmSNB2tmWuwmv52tb540mgtL0Z2u9hLlmtd1xWzDR56TWvViMWoH5Zar5BFsgCSPwsgjfGuNTJN3GI7kr06fFgmsAIn4r2SfFQEL4SP5wS90XWstzfFLL3wehmfEN2trL3GBPaWuImv7L3W92l2tFiNwr2Bl3FmvnL052v5w2LTTHL3h2sj7E/fHXL2y57bFqx2sHbAPL3vZ72muEird2uRzlp2lMr0th2mZ5DdkWSC/L2RzlX2volNAr3x571mvoSMUBLKzngfoqdFQr1VI0G2keVzl2s8ap8yzAOvrL1xmA9f7TiO/Djor2QOtj2uXiMv2twOud2uz1xDSpAiGNfrT2tEr3NfHHmuIr1Zv4P2vcbBhdl0r2hbAWV1o2noSMx2ztV0SBKtPQfL0D2uNrmV2uYOu32tP2vcr0wN3V7bLfFV2vhmBRfGsOvnFMVN2EOvkOvD8bTSHcOtYOtOmtUOvMr0uV1b2tx2vJL0uV0F2koOsj2tsOsYOv1NRUSMiOtgOvv2uwOv1Q1h/BbL0QOtAeKR2sAOsUeK0Oth2vW933oC0fHgOuL2tFiTS2tKOsjH0ubN54URuZQGF2YvB5VRPRyEtT1VscQL4suEsrJy+txX4viHErJx9fgs4sU9WVEvCeEjYsduHeOtRN0t4uM8mpsRXJxfosW9UHzTxGFQYtmHF2ND/cRAYtGfM2OuPyGkYtmfOCsBbAu0YunfM3zPO1C2EtNFk/rlIYsiEv/lAVcrlYt0Eucp42i7RYUH4u5dW0VqHYtNLGep6/8ZqYtJOurgwcOQ1OtSFai9EIi7N/H/ovpOshj2hOsw4tXmHNOuZOu5dV5wycYuz4tBp7D5SeOu31V1aZCYsu/PcsFEAw74sjdWJSYiv3R1l8LHTi6WH6pOtmHFfTNMPA/YnAYud8kuOtrOtGfNRp4xOtLOvH/EHK40eEdOsptmTfyKEuBOuoo5gwDUYLS4uSpUHOuWYuL4vnOv1OREhn1wAx/E9K4ROuBYsrOuBeE84t+/FYU7daYz4vqHACclrcwhOtvOv9Ag5GGfOvc/G4AO5ElPOt6lmTujiEt3Osslk0K6Zf2r4snC4rK4QyOrYvWlnQus04t7/FMFWTOuROv7Os9vAguuUYtSFYT0MeOsNOsnC6lfylGE4usdkNVk7FOsBY3AEvPC6Q5hOP0VYtgxH3Ji+shD4shcnMeQtYt0EvmJzVrK/OtxHHc8zYut2Yv48xDOsRYvkfMdZwZ0Qif0SRmiuuLOuCj0eAuCusDlg6EsmRl8usQuvAKGeHFcut5FqpHHvot7swLNymEv1cnEYo14um/FhmEU2J7OsScnMutayPVv74EuUcwsutZ4unTkGutqyPB4sERljswapI/YsIRksRC8YLuEs2c3ouuMEsHcl9OtOuvxONXWBHrwA4suEt+uuWuucEtqi7eus9OuH0Oxv5wLlMYvDSxiuueuuH0O0Vo6t3W4umr2Gnxuuv8/Fh+XY4ucEsDRGirK+yNIEtwi7S0rJyN2ut4xEweqmut54vqj6lZO/v214tTiyG9z/P0SuvFusNYuwus872Guusuuepnsuvhuv/0H66RX4u8uuTilYhmQutGi5AqkQuv94t9yxCuu+OsnC7vJbBElDPHeLF9yze4rautpuuWtTJYv6utWpkjyMUutZuuRutGutZuv5OsEYsLusnOt4Y02RkX6DVutW4so4sM8GOuvH4sa/EJutruu9Kz7uskusa/FscQr/GU4uGqz/cQr/FXYsBVyXuuFutGi4mKwluv4FDOus1pkFuuZuvr0HAAipuu6/Hcuvf7G5LlNJCYQpW4mk4uGTDTutD4nWusoqlKuu34QBTmgespuuJOuEusD4kousNXLLOsxJbPyNHOsa/HvxB24uVuvfgPBuvzjxb/HPusHmjMyFrOJfRGtpknyPhjwKuuUevt4uAEgGRkkevZyPi4tBHEEeumusCuvfus+t1vOuYesT4uBuuoevAv3seseuvCusseuwesr4sSusiesb4s0euCeuouuoo58etUt27uvcevH4tXRFSetvOtdAMSKOgusR/HZus+YucuuaMM5uu/uvbR5NusaDyFLmCQOkevB6F3uuqevmf14EuFHBp/HhOtAEsQetIUDzC7qEogeuuwRMet6esddpyyNKEtL/GH0SOetF/H0FyVfRoEv2uubmxquvQevb/NVMtBetmuuFHBL/EdusnuviWzNsq7ouBuuBesouu8Es5kFC0h2Ov1cX0utxuudcWtuvSuuVIB4pVQeseeu+JB5etJetWp5MetvOvFeu/v2aEuvI5IeuletSeuZuvix5Hry0EsY4t1euXOtKEsANGjOvhusQNF5eshusvk1xYYGEsiRnoOPs4nPUivA4FBWrLlm4uua6S2oTLnxTyQLG8NmudWpevDevwCHqetk1YpOsAevTevd8FKEvK2tyWCpoklEuFEu1lCbetlVDREvwGtvWC7evZEvbeu6WCXBCR5BhEvgGsd8nJ0Jw4A0SrhEteWBHeuEnBBEt5a33ixuRkqOB3etyWBnev//H7euOj7XevpEsnevI+ABRmPevjAsUGttlPj1GPPyq/H+kuTtlwRmQ+veWCfhnbEutEuvQNrGx5919EtZus7Cqc/2dEtYo5C9WB/Ew+smrmgCHCku+cW4+vD/0KkupHnT/Hw+v0533uvVOv4+vXuu7OtlksKgtHuu2Otk+u+cXiMnMN09p4huMCaC/hmk96zvMV42XhnsQqXEu6/HEuu3EsQaD8+v1Ouz4FPEtL0EydVUopvEt2/Ec+syKB0vwa/FkRnOumUWZBgv0+sJOsw+u0eugkslzLk+t1sjLu6mksUOQScna+vOGH4+tKevDzUubELSrK+tyLwzev+oXKayLI5wf5XJxW+vEUDWev0utQkvektklDB+RTEu9guQEVI+smnUHEsHDDMeQ1iEeAJtwA2+tdGEZkt0WhH33ZvW8/GC+vdW3h+uchGjLGMi5AmEZktiIpc+t7wSPOvBktB+tL+TKdYw+uNhnzSGZ+s2euK+viks1/GtTQGkuJ+uMi79uxs1mx+sF+sy+ty4J0ktSwM6+uUktORCt/GbOsb9kYkvhJBw+s7YPQoBp+vVrJh/1mktGi7J+twkukksh/HB+v++uxNj1+sVGwVhmi+thkhIfMn73ubNsHMSZ6kHOfuFr1pNbMrHMDV3i3mngvCj0MHOvbPmTGZ3SsHNkHMI2t3bNMHO7+s8HNsHOA1qXjGLgNTOKFwviHPceFRhUX+ty1mi67gjNmQNvWJzfl5bPUWKKHOMHM7+uVdXfgtq1lNfN/guzHOdoaxHMxjPMXE6HMsQNUHNjxZf+sQQspY2W2IdHMhQM2snZWKbHN7HPfQ1nDNNHPAw1OHNv9lK4OuHPYQvvssVwug7M3HMyjk+HNEQvMXG7wvAB0BHNIBsUQuKeHwBtebPNnOVQvijNH+tIJ5SjNMQvDjJ7bNH+tCEvcQOMBs7wqt6XYBuj/45HPNnMyYtpQucxZgIucHMlHOcyaPbPngO1tK1HPyHNPjkMBsFHPiBuNHMW5GsNKQBsU7O1yGyBvFbNiBvUIvC7PmTENHNxMEDHNDSZDHNH+vbYtw7M6BuHvimQtq1nggYWQv/gvg1JyBsLHORXUjwuGHMKD3BLFrHPNbO2e4TwtQBuClm360sAleQv8e4HHO9bOVAvmunU7MoBv7g0RDGpQMaNJ3HOnbN6xbqBtRQs2AlDR1PHMCBvsmMJQsR1nRX0UQsmTEE2T5HMJBtWBtpW7/HPZQvDjMPZAlAmwnP1AlZBukh2QnMUj3xaC5BuLjP1AmqBDxzPFBs1QtJXOrAk4nNjAkLAnVBsXjN4Dm1BsYnPUKCNBsDQuMnOU04tBt/qlrmFRwatBthIvkqCtLEiTEmXl/rMn10eZODQuQzG7AmzQsj+TRItfMmxIvfVnxIvcnOZeM1XPYe4YtZah1CnOFOKfDGinMqCE3jEGnOXGBtwsynNyh03ss3jFmnNrBsOTOXQunsuAIn1TPDXP3ACQBswwOW2KEHMgHOtzLnBvbBspqqhnMCj3DqbjjEbBv2TJpAk2nNel6hAnpnPXobjwkKnMW8u/BsUwOKcOBFrnHMN7O8BvPwzKwNBnOaXGXjHowvBg4CQbAhuETNcDIAhu4wNbu4gyJph3bBuQANph1HBvWxrZh2T7NpXHnBsz7NwdJYIvOOtmcOIhsVh3tuZZksUhu1h3qwss53RtKkhvQTMN8uPBsanNpXE1soawOsTOghvYhskjFohtUNKMhurBtoTD/jO8bOE9Kcov3BsihsAhtHBv/OrkAlpTPdctp/mYHNH33y1nvBsewNrSvciCKB3hB0xfXUQvZ8GdazLgvABspytZ4i0HMNbnWSFbgsL8Ge2xhbOajPPAQngubgMWhufDO2QPd1D7gOPDOYqBXgvX+sZbkoAHOhu+ysJcN3+uQ7PAr6KjO2hueJlKHMNblpgyIjNehsYHjX4WojPN7jYjM1bMqKugQu6hsqKuXDN47Nj8FRJk4tWhQMQniuQtdbPAr4ijMaQP/L7JQv0jMt3G8jPoBtYr6PguqjMFhtcjN4BtV3GMjPNjMmM4M2zJQvtjPphuahud8FAS2xbPmhtlqCMQumrOT3HpQO2hvayqpHNNhv+oB8QPVjOP3F8QuajPIVOCQuPDO1HSWht8jMpFEpJnpbMB1PrO3ejODhszhvZQOqQNLbQKQuQpHVpjRjMLB3W52Jht5bOFFGbhtZB2/4CmQNehtBF36Qu2QN4JgZTPhB1V4DBQOtB0OtT1NGojPCBBrhuRhu3hv2QtQANXhtUBuQQt/YlkjNuQsQCEC36eQs5jON4mCJjJQt2jOnYlcjP0jPbSr+BtuHPYBXtJnXHPO42FFGv8zZQOlhsgRvs7NzbPQRuFhtUQPhF19E1RHP/8FkJ5pQu84k7hvPB3revPdlwLbNQNKlHY3l5Bv2ItsCHERvlBsEGDY3AInP9QNtBtEJnA6V1Bssr6fB3a7N+IsqJ5MRuonPCPafB1G7OjBu+gmcRvLQOmJ5RTOdBtjNOdFD0RvIak3jNDBuMgMjBuMnPgND/yoTBtsnOcO0LQucnOfjN6JGXNOsSux8FnCXv4Ujh3qRvShtRnNpC2PguaRsyzWYTNr7PDFwzKFgwthnMN8FmME6TPABAgwMLwwaRsanMqKsvQu3Qt/L6JXDX4X6Rt6njmMGuRt4Oij7OT7Nj8HqjP+DGhh0bvTzIgchsUN0BRuygmeh0yqvBQsywv8h0hRvTh0ghsAM7ywDlNGhh3uO12wPwhv/+V0k3wwsswMT3aWJqGTNkZbYBXPQpkwvFKzC+N+BCPgtApNVV1rL07h38Gh+qMT3bZpStMEjh3v1i+JlhRuglgZTO1RvxKoiwtmRvm53XNFpTMT3ZAN5+wto6OwCEk+yMmFVnN5TObosNx4CUHWOOxAOjRvd9Ol8GQQk5ONvMMNlZGdAbV1JONyxk/+y0OMO9Mx+M1uOLRuEX6oBrgsMwsObRuyuNUONTRvr6Y8OOrRulV78OPlOMXNG+n6+9MVOOtn7iOMYsNln5SOMEOPLamDgCTON2MGT7aHnnEsM2n6s2CqOMUsOxqkzPCp9OiAMILY3nlCzCQl0ILYzRsbOOxqkZNStOO59Of+MWOMHOO7PZRCol9Pjl3SyD2OOGeGApEqyCt9PYDNYNy6nD19P0eM+mnJbmWAMQH55p0BOPnRtWAIhON7JG8LbhOMEsN/hCeoIGsNbsN/hC/RsMsOmsORqlbRuRsO0xsGXb3Ru5OPFql6Qi0DNZOP1PY5OOxAO06kNuO7sNp8EVxB7Rv+sPa6kqOh+sMosMdqnMxvP9Ol8E4J1XANsOPq6mPOOl9OeiAQxsgDNn9OqxtvRv8xt1DY39PCxs2Rr39P9AMNz5KuMcxvFz7k5iZxH8xslgDLxEZsNb80zOO/9NH821sP/RswKgrONQANML7rOOQDNtpEwxtQxumxstuMysMIDN9z5weBvAMqxuTml4xuV9PpBMvOOSsOeiAyxuZOM4xv6xsWsPN9NhxskDPnRskCN7ANrsMSL7fOMvRtWqh/OOsxtOxsMDMLrN/KvUfaCQkIuMCQlSQmd/m9BtEH5SQkouPgRO9ZYCDOVxvmItEH7OTD4uNX5CJHlZQDaQm0RuJ5DNxvWykahkdxtEuP1Bsb07dxuQcOkvbGQlUuNuItgRANxt0uOjQsZynjQtMuPzBuEnNZJDBQkYcPsgOvjMVXMzButIBBZMJIvLQs+7N5n7RuOFgOj+MbDPiuMOn7jupnKk7xtOXT9Kk+DNTPZM7l5uPucNbxvCcPquPb1ygwpJuOV1N1wsiGHRDNUxvCuPVcMZqnbxvvxupql7xurePszFiuNT1McvapeHycMhgPTVxZXZWskFcMQakEXmVDO/xtG4MkQk+uOcBMvOO5gOyXYUHmNDO46nrRuNDMeBUjcbycNODNSBVYJu1uMih2kGNwJtfxvlpZANFnxsdqmqpLdSm1gP4EB4Js6xn9XOFBPGxs7xuBuhdcNluNViFQJvZuM0/1wXnqslUJtyNo1gP+cM+PZ+5ptcObDNYNxMJsm8m7DNDRs/XPUx7SxB82DUyMma0VhJOSMwRGk6xFWggW0aWmbiJG62ggWrqMXnCQG0WWmEeJtqtSm1lfZTIz262fGMATCaJtcm0qJshLKXG1z6OKJsWey4G1jGPBki2tQ2Jvga3fbAh634yN2fa5azKJv1fZuJsxyMQmPK90am3JqEBS27gz8KOqXZBP7pUijyPwmPE5JxSOx6NduyZSMYyM8fYVBgBUHQKOuJtaHQ5yPs/lxJvuJvOfhSvQyJuKREjvQfIOGm0LWkupK961Gr0BWn5JtaG2fGNT8Y4whwKPCWMkOIWJt0qHPrC1tq7yPEmOqJv1JsWRHhJvVJtaXb0YNtlQVJsq3aYGYlJs56Pq8DdJuQyPxRFnYC963Uwm1WlKJuCG02RGNJt+KM4mN1JuSKMM3ZyxL0KMQRFsrSZSOjG3i/lVJtTJt4P3OibjJvZpw34YGm0jJuX1VO6gDJsTtEeWhtuFmr3bJtIdKIKOKRGx3LIyPQaGYSFrJsrSOc3afCTYyMG6PZ56kWyjyPCmPWSrT63EyMqmPmJsWtLYb3lAU2qwXm2ggWIamK0xTJv1AXHJvKJv1AXFJvjJtQdMwxpaJttAV+pClOiHJuwdMZJvjm1570wpvlJtNKPprmQpubJtdyNFdHu7YHJuwyPtdH09i6DiBJvpAV2Jt2oPGG3lAXK91mG0JJu9TAApudWF+9n/JsEoGnyOh72YN2pxoVm14pvkpvBakXviYREwSAhyhjKNkptkkgzG1ByMl/l3JtGKMXtEXoD4pigpu0vxSps3m082B3Judm1ZQnq6DMAsu62FQkIpsOyMrJshpz0pv9kFBb0zHPnJsvyM02B1Rqd1y5m002DKpsULE8pvtdF5DV3jD2KNFdHazLMpu8CYPqE02AotAIoOUpvKdMqbiwG3fr0N6HaptXSNkC5O1UWAHQpu7NndMigptfnzukzBpv+gjcbIBpvE1KsKPUwm/IAcqgcyNGr2xpuwpu4pu+ptRpvRIMxr16psRpumJuq0B8zqtJspptmpu5pucdHUpsXJucdHeptdKMppvOpsiUm6pu8OhlCjFps09P2ps7SM2X6sVQbNgOJuTQlC9g//N86KEdF5yQ7cgspt2C5NpvpKPkyNFdECVT2ps2KONC5Ucycm0iptoZaRFgCpuTQl7cwcoMJyPtdFGlT6puXyNAdFIhpzqg9ptxC6rpsWm0dpuCdHhpta/NOr2emOqzwFpuTpszHAVJtGZYVhLKyNSdGB0IoKPppt9pvcKMLr1JpbE5LYKNYpuNzHdps8yOaC63pvNyPKrl1puyptAyOjpvnpsQpsdMqGUOaptUxoEpu/psapw7JufpsLpuppsepsrr0apxQpuYpvcb3gZtLpvSyNftEgZveIOoKNzC5TpvJJtKdEQZugpukxFCGCzJvx1wbODyJtRqFEZsgpsmpvu2BFptBWE6alpdPuptUm2OptbuOw0oMpvYmOmb7V8g2ptMwlyxIWvkTQko2BnYDWvGaptKSgkpsUZuQigOyMWpvOC4feoXIM/yNAdGc0SHpvrpvOC6zpu5wWMpukk45punpubOoY4mRG2w2DyZuAW2Bp6WkRsZvqZukb66ZsTpsrTzkZvRKNoptSEg4puGZvQZuEZtRMnNpt6ZvWZv9punm2Q9G4Zu2Zu7pt8Zu1Ql9JshJt6ZvuZub6vVKOdTPwZuKps9E7mZs+Zuig0/vqim3prlRp4YwkIZucL2UcngwmCLF4wmt1VwhMlSMSLNp3CxBErJvRZvSJtTJtpZvcwkmpsT0MVBjDKPTkF4RtDC764ntsCHAiYSsJdErBD85DHKN3JPB2BFZuAfEXKNDC5phASwlbKMHes92AaDhHKMUStlZsSSBIW2EquokG3/kmuCNZsxkDeL3HTDlZvXKPESvU620XmtZvnKPtZtpQmdZslZuM8uqRs2qEl2ARZtbW082CwGqrW2CH3C2CrZu5la3W2FQltvrwgtqW0ppvxRrMMMkjwxsG/IA4wmzGsdH1YrYeWjWW1rW2GptXZvoqOLkZzzOCFqUwk1W1idFdpsTGs3ZsPptjJs1W2TQljpuEqMPZsbps6uKzEi5lakEiTQn6iDz3B+62SH1zC4fQlaGtvmNzC6o/xJYNfmPkpEmJuVp6qH1oZbQ5tZgv332YZtMERpMOu4uTQn5NBFgvfTjUC7Vpv2JsRqOPZtvZvXZvbZsyC4+Jt6GvMEt5C7U5vnZu4H2MZuvJuPW3SWMjsC5ZtpYNvW0SC7F0hOqPGZ7hdGVyzpZvfZso2CRFhyGEoqOw2ANuh9MPV8Zcs4MC6bZsNW05H2sZtA5tExAl4tMwn05v6qNFdE4J7Y5sxW3X31C5sa5s0OQ1H0JdEq5u+qMCp4bxoK5v2qPS5t9QkM5tzzNWj7WJuk5tdtW7punMOE5sSC4HDjtMM/jx1PDXMNXtSHInS53u5tSdbz41ETCV41CaPyOgul7VqMoxX3Lh3Y0j4109Bvo0+5tN6gS40HV2cnwS43d43h5tX1VW52uSnz87XV3ZSkHbpu53ErOEeTr5xEItp5sslj4SGD43q/Zw40F5u0rI18455tG0JPIliD2D2052SAV6UItQyPtIFR53+5uhsmEdZDwsOlNDyul5vI12F5tt41zD0A4Le5tY12asmDtYLwulSPvMxydb8IuYylheTZ5vKrNZ5sPqNUiEZNwQY2GaMrCH95sKIsoV495tID1ro0w0J043x5vV5sN5v+D0ulPgGjIok+5uboRWNWe5uaUnXZzrwt4ynOUnN5sF5tTlJCl7t41maw643JD0L5uKNCJNXXV2wSV75u/yEF5uoW375t940//BGuKhrN4FF4Kvt5uRrMdeLfIme5sAFsoIu6a4B7CSolf53TdY0KQj5uD41mvlvY3wFvaqBt43u53spwZ1WV5uQSVt5sxrPsrNDT7hmKAFvK51oFsb5t8rMM8NuSIT8HI10IFt/Y3d5vIYWLD3jUEvDDEomD5uZdbRLzDrOdrPQLmtKpf5u3qOQFvsFuPqOgeK7Int51KFHAjD0FsfqMBJwUNXz40vgKnImiFt4FsPD1pBtMDP13a6InGInaIsfc0pImaImkRuvEFKInyFuuaPmSAj2auopmIv6Iv2+3onSOImL11dI7RIl2IsjxssKChGoGFvkuOhIleIkfrNTQsaQ7GFs+Is2yml/VpaMjxtQkH6Fv0Or71niRv0nOSRu9Bud8C+IkFVJRIvzQse7OLQvrxtM8sISnr+41pwmbPQ4kQkAdIvGBiF+3OSIwMC5Iug6NiSJDotYbPsV3xFt0G3DF1RFsRFsVIvzzkssbAosoN1+Sn7rRXF2kbMdSOQbxkF3XF2nELRFvdovRdaXUo1pwKN15hS7Iluj0Lq5Rj5cothO04qwtFspj0dSPpHDIbOnaPNFsQG3TItp5sfRU9FuxFtuO32GPe5tSbMXUL0Ft+j1X0i8Fu7iut5sKmR9F1JFtnEgvlyRFtSEimu7UN34wvdqRVFv1BKvItoEh6kFxyo7It7Fuj5BNHKRbCeSljGzZFvJxzNV0KBxW63ZF1p92uIorFuoosfzlsgD75s1It57IJFuAN3daPAyMEDSybMnxhcs4zFvttbrossVMCUiNFu/VDhV2kmQ88hUouPaNvFsZFtEovRdZWjDIon1Fsy8wLG2ZFsilLHFtVovILnDVQTG2RFvVaonG1NFs4ltYluvFvTtFHe3/tClF2+IjElsVFtElsnaMjFuv5uFOxpbEVFuOdEAG1f13rqYRdYklurx0//Baig3IsoN2v5t5FuIotNF3slvbFv1FtOn1PkFMlugPAMomClt6pomUEiltvVY0bNIoshbB0Y1uj2CkNvY0VFsLKqUNydFt7gKiokmbPqlu2UHDF1mvkfl6+ouMpy/5tWN29RstpJ0408l4bosSJt7C45cz7FtrmlKFHms5MCX1ovILH2KV7ppCLZB70YLFUhXvFuBo4aSlBZxrUADaP9HGnF1W61PVHGon+ltXStryRwyNLsVycmncydSldcQWCs3ASYylAMY9tb5z7Hhl+mRN1WJlv/hlWlvHFt383ifOPlKuroulvHaI2dZzZyR60niFOWTILlx5YRLaulv5lvJdLCJM+GhgQ68VIH62Zls2LFlyTOlsuaFJluh5w+luplv5TmnSyuYo/InfhnZluFls5q4w4uGyNdlsOltulsnYwt602lsQylP+yqBNGjyrcMV2yD62BlvdHE44LK9RSonvov8CS0gLhaGRlvPSkI+yzn2xlvQLm5eHt5ztlsJdYsvju60HlvnSmLwBNlv1lsayPzLi6sstyQjD70TbRXTLlsCRl3lt1ltNou8yNZ4A1pyorZ+ltnlsJlsDdITlvRlvHLblltiynN3D7lsAVuvcPl3rnLY/luZdazJr7LYAVsPcNblu5ltUSrVdY6wETX0QVsRmYtFsfls09U2Gav2zZn2L/GYVsIG3wWmPltuHhoVv9lu3iVIVuock7luwVsQlvNltplsvCRtlvcmEdltMm4f60XlsHxwfmYMti5luPKKAdby7bHltNtJ7Ig4BGkHrVLYQVs6F7sG3DlsLiXEbwDX0wVuVplLlueludT6BAkd63oVsiYHbyNjlsvltbO0Hcg3+MjHG/lEyVuqBMb+hn/XZhCSVuIC3eLHy8N4VudKwWRl1lZrAhSokuHGNyOhlTrlvComnHQDG1MVsM8Pv2zLytnYv2Vt8VvW4WnHHhyO2VtMDowRkWVselyrov3HEmVv7BDPInLIn3SoQG1FltMom/SqKVsjouYNUMHVWG3CVu0KMuVuBVvFluQPVjlviVsnuJCVvEVulT4qVtCxPLImSSPDxPW4s6KMhVsEODHInnFIlG2hVvwiX4LCnBPnIm2G4+VueVsKLEjXzxVsS9D0HFxHXOj4/InComqDTNVvzlsou0OVuocnTltOBFx5bsLYCVvToZCVviVvZwYnG2xVvT8NoVsCVuuF5zltMdryVuSTKyVtKVu1BECxju6OfIlTVsn+PVluWBHl1ISX0bltuc6wS3rlvfhmO240SbdlvmLEiKMeVs3luWBFdVtmVulLFNVsdG16Vv+5C3tb+mXblvComCnExVvjeQeonx4DtVt0Vv9A3gTIim0NVvV/EV8OJlKuVsQRmP7yAkCdBN3YvmDYcUy5XHnImy2XVVt5luvInsxJZVvHImJDqGVuRVtD8ObVug1teVuiWrTVs5s57/WzluK3OlLnzJpEVvXhD5TkP8NYVtHVtvVsrihO4F0L72onQ1vGivbVvPVutX3rVu2KM3VtGVvzT7fVsWctaVt8dZs1tARE7gjaPHvVvM1s+NxD8MXVtSVsOKMmsQ+VviVtiUqU1vi1t5i54VuTVvAiIFVsC1vIVGfkKock81v4COkVtzIk7HEE1vy1vsnys1vS1tqhOM1sG7xC1otVtkcBY+Fo1vwVuIolBWT9GieluoommtU0X3iVs21vPH3m1t9Vu5XGEom42AfVuVDx/Vu0yGW1v5z7/4tCCN/JzHqNeVvP1Je1vnzl+Vshrr81sIVueVHMqTA32FVvqokU1sbX3nImraOHPNg1u6CPI1tS7S2CO61sjpFOVuGCOjVvEVsCVH7qBm1vKonp1v51vIHGxCN+1viVt92R+1vR1uHPHlVsnX2TYsMSO6VuV1vx/W41v8Vuw1tqSMg1tF1sovFXlvZGOook2lIhVviVs91tJX3LIkfZF1lviVtD1ugvPh1vkiNq1tW1vHIll5lY1vj1sBIrbFveL47HGbe22ol7UElAuoq7WlvrzldLFfbAMomKGPjIk3oi5NVjVvr1sZlswVtH1sfcvh1twEFAVt/Gnh1sFZuYcAJomCUClEvMcDqqwxomeCnA+tP7231vP1tcCnves03wf1t8dOXetmIlsoYX2CgqT/etZA09qReCClEt5q0ANuXyAP1svT6EtQ/1vgNt676cIEpolADRf1sUwF31tANuv1udmPlEsYCUQkWaon79wqgtVkXttYLV34NutMWENvLBKogvA5bEomM1Eo+tkFaJNVUNtHIjHtaalwEpNNGr6A2kRqRWPMNtOBGsvyRWNpEgp+2P7kEpPcNv5iNs1v/33sNv/VsJltkNs8Nui1vqpOwXziNvA4qV6MyeOetMS1uZvNKIQt8PwqFWNXi3Z8+t7JqrcR+mUYksaNttlv5lLsgsJHM71ursQfeCmu0hFgOuUNfjHiMwegeltd75kbamHz+mUERPCNuCNsSuUNEtY+FTsp6pPCNu3NwH1t4NvkNvJZQplteNsp+0+Nv2ltiNsK4HHK2qok0oI2qN7u1UCVqNvcxr4+GX1t+uVR8BVxy+1uyNtSNvXiNrCCMVtBNsVCUcokmvMHEuMMELo1C3a6ksd+BDlsUfnXwCiPEson98t3EuKVGKokFpxMkvs4HFuVr8tbbI2qPwjmiNv70yOtM9qHr5xENtPAtDrxeol+NspNt/lsSuXuks6JqsVuHiD1Nv8oli4SZvMh/wNVzsolQFt5vNPEsDNuftZ0Nv1+uJNsOuWUOKRW2dNukNt4dS8SOtNuRWOByQbNs8WBNNvLNtgA2x7z7ltHdALNsUwaLIl6NuhwDXMOYMajOAiL1IqGHMqvUkSL3/xJ8j3kL27hYr2yLWu3Nt4sCnJxVz1YJJ60weNXZdnQDoqQx/GvDWu/aUfNt04GKWv8LbreRkN2GWuIzpmggmWvvj13NuPyFxWuAcFQ3KomtUms+r3dc7vcMEL0fjoeiz02sWeYNmhNWu4tudF2i2uAcE3vQQ8OyWunClXbFEhmItvBjq1om5mtIcEjgismsqYlYtshj2cmt+Cn0tv4tu1iGiuiIz2jRIBWjCmvkYkkKBK8zdWs2Gn8tshoWmmsMUY8tviz0MUZfnRKmuMtt4/qBeFUtup2uQtvytso7GUtvegsxYlchLG8DWmsZWuP2Ekts5fHDj0dClrwg2Ekxmti0Yatt38P0GmlU5PNsCms9dqFXJvGuIL2lxKU0numtudrk6RAL23NuV3ifNuYttZlKctsPNuc8S5EnXGvTClBUgaT18tsBtpe8PEWtqOFzsQQyOitu9hL+tsStu9hICtuSWuHClStu0tuDEY0ttMmuOtuGN1uT14LaYfDOGH+T1eYnUWaKtsUKCqdYtNrkLQ1mu3Ns9nm+yPPNvNmZq2r4tsxWYituWtsqSrituVWvWYncgKettGtv37bNtu9iBGCWHVr1tv9WuFT3Vts+ts134MYkVtvhttAtuNtvnUByyNEtt9NqGQhTWtYjH1IpxtuFts4CydT0fz1zttayOpwnOz0ENpzN4kqH2z0BmCTtv+WvaGnaouX10PmvQ1pRtsHtutts5GGuWtUx0GtvbT0EL26mBFtus2tSx3NttXttLnllttgtvsal5KjLT1NYlutjztt8WvLdnQVpHts+Wt/lpglhy2uuKG8WK4SjCz4NKERkDbtsbtteYlyWI3tvYWvijnIxwaWu9z1wdsattEWt/NvQdufttVz1+WLrtu+tvAdtlttXtvcTQjyPlttwLoK2KIz1LGCxtsNtthjldtu1z0U73jHzBEnCz0Wan7+l9tvb3i8L2M1nEdvgmudZotzSfWtkttQrkX4CCyXTj2YdtqyP4WuYoYwdvjtt2WK3EwQWsnIVUYby8gStuOl7oduqtv7b3jBDZyNUtv52I2abLz0tqE930nyMrtv+YndfaKdtfWvM73CdvXWsmakQdt/tvxjJjaxPWv7okboxWz1gdvAtSsdunmtWx13ZSMdvNJD+YlRBgittIOyAz2yl42dvyz3mduVttQtsmdvh3RsdsQjJGdtgtt6duydtMdspjnadsaWt6tt9qGQIaFWtq3yi73RdvGfEhttRdvIdtkWvBdvLtu1tsk2BSdsSL2+dvPyPltuKBjedvYdvWdtYhkYdvOduMduJdsC5pkdvdtuFR2FdvLCORdu5FoWdsCL0pjkHjI5dvPtthya/ttXtt0OjYws8msK70tIINmvPGvnpogdvGdt5eBYdvzz3Wjluko6dv7WsQYkAgQjz3fOknWsWxor2znWuFrlTdv7z1r6k9GDJdvHtt/RRjtvyL1dYmmdugdsrdsVqja3oLdsWakxsJDtt/WtdYn1dvvz3+CXeYkJFrfz0JYnsmg6J5ZdvHds6T042sZJrzdsPdukIiumHGdtGNxPts5T014P2dsDCOIL2wLE1tt0L3eqEajBidtZdug9vjdvAL0T+ptdt9dsKRq/ttbdtrcY61lZdvmiSGtvyL2D71/dvvmtAdvetv/du7T2ePpDBmVduj728yAIiNFWuDX6O14FUnjttLVBsoWi2sIT4Q17p+EEL1k9vwCHPNsM9uomuIL1obF4YnyL0FZuqYlAarq2veL1sdIbYmzUA62vf7189urYmuL289voxUiVAm2sCFn8R5kWAW2utOCYpoy9s+2vZ5mPKoiVAO2sX9BquAS9uK9tC9vK9vu2tAkH79Da9ve2uC9uYNvsMuM97dNGceEr2t0H3UIGh2tB2ugGZIYlR2sQR1oYlsr3x2vQVp+sBJ2vsr2ajnMwxF2vW9scWJN53m9tQrkO9vb2ulL1FZov8F29sI5owtvZ2uB9vqdsmSOtL11ENpYaI7b52s65qvNtP1xN2u5FpqYluWV573utHWBG/LQ2Sz7onJtv92vMr3Lom6pyMOvWYmws2Z9uCsXzL0p9unUkz2uAShTomJ9uGOui72x9uwr0XL2h9t8j3m9sK71c/DOGHx9sEV73Nud9snqF/gnH2suH3e/CgCE0Fh0rSVx1h9vX2vZ9ucKacYn32s0YlWbHd8HP2vYr1jppj9umOttx0dXj7yEL2tVdtNgr/2u6OsuH1OvDYSNe9tDdsd9tIr2Ramp9tor2HItNu5soXz9tUSPMpoBWj4SNTL3F9udvxQCFiOvxH0H9s4Ot5Szr7PrRNsBH8OtNx1xYlf9vn7Mg0l59vv9sks0mSPJ2t2duYwpgSN39v3EP+9sADsoTlL9t5ylEOthyZsttiir9+JTjmv3QD2EvL0oDuVokCSO8FD1qH25GBeHD9sPL0gTmwDttSvPENA1SJL3F2vPEO1kqh2vR9vGYm19v99vGYl4ttRGoj9sLQYn9scfrBgBkaEsDvt+zBkOg6idF1xrSyDQ0DuQtu/9sCQZiYnQDsITlQDuErr59ugmBEDsgDsZH2IDsLCpDDIZH2YDsoNzDnQKDu1YmX9sNVwIDv2tvL9ux70t9tH9sYTk+9tQr1iybCDsGDtIkMCDu6DvSxo8Dun9t6YmBMqP9uisVX9s9GAsDsSArxWPmDuH9v+rRgyD8DvxGFP9sWamCo0ChHQDtrSs+r7zetmd2Er7TwoHt39SGXoROhwfd19ytu/T2d1gJ5wtppTkaHUpyvHC3qyHUt0JDsaEzxN0ad0xDtA3zyd3B9mNDwROudxwq4lhDuPOtN8YjN3UMxPH63N0AM7+Dt7f3+Syyq1T/HtOuPd1PL7HjW1N3VSFRC2WVDVt2hDsi8aG+tHU4wgk5Nw2Elod3p8F5CiaYv8t1PL6xDtlDv1DuFSBjP1VDv1DsjfDTN1YwRsqvwyhjP1VN1g3hoHCQt1lL6k+jjuvXt1pC1HLh4Y014kN8HtjXvt3pDtANUUTwyd2LDv4utbaykM6OZEfOtFDt7s01nhRDsid0N8GSsSaYsTDvYGCJjXMY0K4l37if7j0t3T8GrgGnOtud13DtruI6t3hN0VjbhDs7t0rDuAXBOP11DtV3FjDsGyF1N1j8HNyI2TnuN0pvQD8gRDtkfRLDtIjvIERweu6t16EAdvhGd3kt2t/Roes/Ds8CHyYCZf0JN2fDt9Mjqf1pJrcKu7Dv/t2kM7IjsnDuDDtCKuZDuYd1XDv8oPkut5DsYoi/3ahjUif2Tt2n+U3Dsyt3O51rIYfuu6t0WSCZDQhDv/8FzfAq1Qfd3NHG87DLDuwCG1GazOt0/yN4lUHonDvJDsNKsoju62nqnwyjuMtz9P22t2Sjtwet/K0CqVijt4jvEjuwCFinhHe3Q92wCHTwouY0K4n3KAm3hUjvYBX8jtev3Fd2UTb2juRt39d2ZRuWVCxt3Nej6jtmEgFutUd0Kjurizues7d3v1xYjsY92VFGKjvvP2+jsbhvMYzFt0+4lBc4yZUhjutFEayxZYtVN0V22Psphd3QRvVGqJt0zd1AelRjsOt0dt3l53BjuMd284lBjWuTk+4mYZY5uu+jvYRtEgyZjuejvYRs5jtHhl4d1XtQVkRZDt/YlruJkevbDsLFGfEr/Dvkt2SSk2jvRDtD22pjv7d284kj7ha4vJjvP6A9uuBDtwWCbDsGt3djsCVSHDuAt3njazjtrDsE6wYF1DsFwesft35jtbUXNjs151acRgEsTN39ju6eunDvYBWi8q2uvgd21jtxjtQd0y4lfBUuevLjuCmGYOgM+Jbjvh5vnju9DtjNxNjuMjuoTaflz9DuEd2zt0R52fjsy2m8d0vjtMeua6r251iWmmusVjviCEWjvxjurKsukqQTuM4mEjssd1Y4niCGkjt9f1cjuYlxSjs8d2ujuoTtwetXWVjjbRZSbjtvjtCemXxiJ4t7juKo1YeunjvgTtVjsPjsgTs3v1ijkR52tjsut2552jDp0evVWWrjaMTtUt3tjsATu/v3xDvgTt1jvAjuc4kUTsSjskTutDsi4nh5mZf2Cju4Tvjjvyjsk4mUjv6d1CenSTtA92p53iTvqf1GjuwTvijtmjsT53QTtpjvA9AFjuDjt8em5vh2HHQjsO3wHjvJjvuxTljtZjuu4mhjUejs4oCrjZMkDXjvYTsk4nNyJFd1fZh6qXrKAbUjld3xelIpRqetgTsxTyvjsrd3/8E8s4BjtmTuX50aTttd2N4mpCVLutATsZ/YlpCqTt9d0MF1RTt4juOjuV4k7jsPjtheS+KM6TspfLRTtZjulemgjtXd0vKvZTuFjse/bCjtz6HqjsO/ZyTuBjtI8xoTv7d2aVOJjV+N0+4ntIOATuZTtDjbaTvgjv61DaTuBjtSOw9DvNTvtTuKEvfd3/jZTjsSjvIoMQus9TvRnWbApiEq2t34K554led3bf1Yu4BDu/tJTMG0fwVJTsHGtSFuiljDvqyFNN3Mu4zTtrTv+jt0tmbTtzDsljucTYFZsR4nVVIM90U93uFDMQbL4n78B/1tXFBnTtE90nTsDTYGC7nTvC90SV6nYk+RLHTv491V/Yd5ks92PTsMH7PTvL4lc91muBlUQPTsnTtPTskhXP0DC90DTYgztDVCs91vKPE8SBF3Z2CrBGX90QCHNPzNEuV934TYu2LrtnO93tF36K6vyGG93e1M3VTBjTz91G90u0HvYm191VF2/+rYzvWBjxF1YzufyEYzse51F4mt92YzvwBxwksozu84n3DspyE0zvkTulDv0zurKsz3RO90HkCFh38slD4SZ92A+w4TsiwKk1mx93ANx2CGIjuJ913/A9F0Mjs5/0upIjF0LTvYktnYBQTuCzsb9msHwU4l6BW6/0l93WTvejvKkvMzs/jvhDskzvtF0XdJqzuN93xF3ZOBEhnmzsZF3myv98E4zsCqWWztwkvt9wth2ApRd4lD90T92K4nVGrykvD93mTstDvm/0yzuauDoTbHEvbqk6h2BsJKzvyztp92q4mMtwkksbaxjjamztl+t48qCwPBhR+zuu/2kEAk4nmcj9/0GzuuzvkztZzuOzth/3qOq6zu7Tt592793STZMDojFpczvRemQjt/905dQZF1KhQx+shzve1O0VU80l990uzvvl77yHj90xV0R4kw4mv90+zsp4k8zv+zv9912enlzs692hzs6Nxmzup90uqVjzsJztwtR7Vwfq7DzsZd5JzsuTss+u390J4ndztf934TZtzuFktZztNzsZksFzueele4nFzvvuDXMNpyMwXmMB0nztsBGngus8PoEn1bO/lHa6IbV2Xzt3zvGhu6a6w81/gmXzsb5hA8lRbNSqN7Rtvzv1lKvzuLgMF+CnRtThscNvCOMiHNgdbDpB74nVB33A7FBF5bP2nwAeEwLu8Z17nmQLujlTSBEzHM/17mDbCANAQs4iHoLun4k3zvKNse2BgBuEiEV8Nf4mE7OUu1wLteQt254XzvyBuzlE1dZgEnoQuiu1KuNMjMvCEb8O/4mqjPMLuEQtUiHLxYMLsVhuLVvENFxHMH8P4OOXzt6ZJghGCLtGuNdjOmrN7tZIXkOB1KxrQLtnzsNELv4msLs3EMoLuyLtw1rEknRB1ARofzsGjOu1ZlONThs1CVRxswLs6NySLvGQNFu2GLvUjMpTyHnmeBs0+G9BqILuzgNmLvELtGLv9ZxQCFPgvUSMMLtnztwjDYEmuLtPRuI7PGl5foseBGoLvH17EB12Ls1bMBLt7nm+QM+LvCLt47PmSOYBFOBvTPGT8DYEnkLvt1a0LtIQOsSMsLtwqyhu1Q1IChGMLt5l4hP6GLvVjPZLuOLv3HMRCOYMAZLvcLvJLuEQPtjOSbW8LtSLtkwQ+GGXzsqgQhLu4Rv5xsmiMfXr0XmgnMo94kgMQnMqFsJA3NLuERsEcAd9Ij13VQu9xsvc1iQn67P6SBbElNQu6FuVK6Y36iXmlElTLtjEldQsaQ5jLtG7OjVFDxvcb7zLszhDNEleQmVkm1zP5XNIEMLBvX+DmDq5OovjNTBvFykrxugYBrxszxtJzOLBtZ0G1aL7yEgHNBvrKskQhsGc4eEl3LuVNl7nlHQtPLvwXm+h33Lu3LsqnOPT4PLv37PH5a+LswwMXU7QLvJh1/Ls/LvgTPgruhTOT7MgruX4kOh32nxO7iP7OxRuUu2IrtZnMktO8B1ZqlfLsKZIhj2o+PdF3qHxIXnwrtnUElmEpRvD+4wXnwhtY+GBhLKwswrua9A6EmPLt3dtgElgrv0ru5MHwrsRHwZLshjBTx0B+D+SO2X5oEIm1sFGESnNC4Gbnjzh1mRvi4G8Emeh2NCOgrsanOi/Wxh2chsN/X+xK5MFJ7OBVFzciQHPawt9CNhbDCeG3JzCXwS+ECBC8LsqwNaruHUGxh1HvSOPGRupIruETNRLx8rt3LuPxKmElfLuBSZwrswrta0mfLuiwuRPHmeFkhtxO2zzy8LuVh3hV1urtgEmDRuOPGnNyxh2gOy8SP2rsxRvR7Nm4EiSzuRuSruWrsBEnArvpqQMruQruLywIBFD7OW+FZuN3LtYiYuEnWrsaKLATNFnN6ru2SizMFlnPW4E1uO4HPmluPMvM84CUFHDPyHOlrt1huDkF08P4jMrHOGxlrgvoRtVruGvBzjGn+uZc27gtsHOZV5jhsFHMdrs2htkHOtrsJbMFHOm6NHgMGjO27bXNHCBs+mmPgsDHO8LY+htkHOZ6MfgulqMMIYf+tuy4pcPlbOmBs1LYRhu/CEw7bYjMrHMILZxhv2BvszEFB0kjMqLaMLGdbNCsnCLYjgNNHOpqnZhtv9kcLZ5htbD3jrtcjM3HP3rtGB14BvkzG8jMlHOXrskBtYxFnrtz+s7tMRPxUBszrsY5i0BumrOKzHthszruFTRdhulqOscyqLvBBt1y4xUjlbNgbspTM8BumzFjhvvruaOjiQsVHOLzHmjMzrtFlwfbPrm04bu2jNEaN+mpGQP/bMuLkujPyHNnmlrhsDrvTFw6Qty5EfltHhszrtKrw2QMMbvWciGBsj1ZqhTXhuWQt0n13hsbruKGOPhuSXPwWlOQuvhutInvhuHrt0Y4ZTNuBuorZoRsWLtxo55bY+BsqaPQyagRvoBuelvthuPrvUbuwRsDrP1ouxQtGaOjxRtjOKeGSbvVhulqPPMFYRtcbsFB0i7ONLtCY7eknZBuB1GWbskRumFtMY42bsURsmhHPwzURuXqllxtMY4BkkMRv6zBwEU0EVCRsw855kmrjPDQDcEVzLt2bu5kneburLsJklZqA9BssRuXpDlkkjQuP/kGinP/l1zMGDO2FsO5ANjWe1SsnNgbPLxsKRtxIuDUBLQuhFssWG9n6MjMGnOFbv/QNRnMjrtawvIhtWT7JRtGRsLm0DJX+MFmnMlbvDh1WRtscO8LZFbushuT7bD4VZ7Oqj3+y71NHFbsU25NbuVbv9bvbDENbvorqoHNlbtPanmQpEwvIruyzGTbtorv3dP96PwkkNbsE2ujqk2nNEXbETPjbvfmrWnMwhumzEujPkrvSY4AwvtbupQvKruORtwfNtbuVbvkY7kwPnbsUuqRnNmRunbulbvbQvChHjMH8rs7o4RRuJrt5o4TghzbsGW1n4AfbuRRtfbsixr0tEyht346p+D1btL7NL8WRVAhh3KhvmOtYHaWl6OUn2SNUVOa63Lm2rU3e62RG1BWDXW1AyNBWBhW0+pviWASVS6Js2630Fx3MQYKM1/HqhK1608cm0NBkr65psNWP5631Jvw7tMCX3Jv7WxgW1vJudcU160gW1M7tvOgCpuiPWJ60s7vQpCc7ukpuKPXHm0U7upIBU7stpsLFDRW3gKOlPVVKoC7vor6ZSOqpsmdAS7t+KNNuwyG2DG2gNkbG3FyPgo47G2mm3mpWwWoWm2/XznWOWZofIOtm0ZrCK7vRSOy7tQ9LU7uvI7k7vC7tyrBC7vG7sYNkX61cm1nEBhxRTkM67u8pWO7vxpvBXG27t1Fuq7tW7vI7vo7vm7t0G2I7s9VPz63zm0detjPKZJv+1ai7tZSP7YXpG2dm3O+zq7usyPh+y0m3C5BcUntxAOm0a7uz2Pdm0oZvf1EnxsFG2zSMHrla7tALGcUFR7vxG0YyPh7s+lv3Jsh7v1W0NpuYYHZhDIdjmIMKUmBHYW7v0G3QJD8d48m32SM9Hb+m1+KMPLAZ7uR7tW65zm3x7vWFId60+pu1rBG7tp7vD7vR7sCyOYNF67tgUNim2tRNx7vLyN42NNIEyoPD63lRxFTS87sdHYqm3YCzUUmaOkDG3RSNE60NG3ayMTB4FAoRG0AKPQOPlCQ77uSZsL7tEZAom02KMr7sBVu5m184UHG1ByNj7sAG3ipv9eCt7sx7uURjH7vVKPjlHj7ujG16YEd7vtSM/7sv7s97vS+I/G3z7tJrUcEAFG1P7svRMlG337u1lHBm2iZvtlluG3sZv7pn77sOptfkmtBpLm2b7tbRPvhj5yPKUGoHs/G2Gm0AVFL/KCG1dlEAHsx7u/Nzlm2d7sStyJ7vG63hVlx7tEHu42Aq7vUcaPK1T7uvG1AUnYmh97uoKNXROJ7vGG03plUHu77vwHvMAvQKPEHs77u57vbknv7spdgLkmYHtLyNvG0a0E1G1wKObnaSHsiHvLf5YHsl7tM9kim3oHv5rUaHv6oMn7tPa7cnD9pvEyNKHtoHs37v8V7X7uR7sa9kYm1P7t9HzVm3zpsAI6QHvCpsDpv2HvXm16HswZlx7vbpv2Hubm0tpvWNHd7siHuWHsXpsAI5X7sUpsiUHGHs/G3cHuqHtLyPL7s6HtPpszzF+K4gm0wZusHsGHu7JsaUGhHsKm10HtmHsUKOCUn+HsgW0+Hup7vx7s4J6J7tEHswKgMHv4HvFHt97sPm1vkl1KrnUPL7s2HuMm1lptMn7Fm2AHtOhoSoN/7vQxDem09m0hK5jm2RG2dHsAHtP7s2rvhIPb0zXqGuH4Cm1aHtq1ZtHuW1taKOvqFexN7TgoHvuxMTHs37tB6AjHtP7vsTB37vLHssBBWHt2HuJrYCHsX7soWW2HvDwhAJMhKB5HuJm1GxMCHviHsvFDcco5HuHHt1Hvf7tk7spm0x7u3Hsnm2CUmgH7JG0mZt9LWLwBTm2R7vvHt97unm2b2nRm2fHu4HuuZtHknAVC0HuCUnAntQHuR7upPQH63dHuQnveZunm2kjbXm2dm3wnsfHtwnsP/CoasVHveRYSVTjvHNKOJEWw7tlpsVRY7CWJZuM64AW1+KM4ntoluInv1zSw7tByNEntQW0hm0FZtew4O2JdZuYSv0nsMW04W2KFnMnu1ZsUSurRw+UlrKNsnvHwYUW1MntWjD8nuXTsFK2qpI0W11ZtcnvYW2VZvvJMk458ntinucnuynsvKNSnvQRPEqvLoHkJnfkFbW0cnZnRkW5unVbP3XttYvZu/K2xiWq5tl9Oan74gukH3ynaUUkanv55Tr5w25sMYFqUlbZsUpMgsEaGFAqMxDPW7uWnvfoL2W0oqPyHtsCXfZsw64W7tYbFoP0NHsIlt+W1jHuZpzjW1+n6FZE+eH4gtK5uxNHRW0o5tvoGWurjW09yyxw7+HuxYN8qPJntiUEE5vZW1enu07tunuKaLvZvbZtMK4vW0+nv2rshAOenvjHvqgvoRxcs6seArW3hW3pH1zw487uK5uKH1zw7TW1GnshK5DW2rGvX31tnsEnu65sb8vNnugxl2GsNH31nu17tZW1LW3Vns3kkanuNbFUCU2ntMK7EnuF3pZns1Rl7kGG5s9DNFnvvTNoWP3S3t5z+nvkzUXS3Ttb2nvaW2yUlanvFnvKSbu62bnunVYb62ftav6trnsdjJBnuugiPvM4eAtntVXTMWM4eANntMqORW22y1olsantXntLMOFqtQ7tkDZk0IgrPID22bZ6rOFJlMOS8rNDD2j4T1yFB5sVh4UsCh5tBrMFh7IrM+D2lQTurOwXuXQTRtkIXsEKwtqNkD34yXtqMerOJC2H8HpD0jWV9qPCD3BnihD3wD2XQw0rPlD0Sgz0rOTqMogwxD1dD0u4vcN1SD0brvZ7hcrNlrM0Xts84t5uBKlm13I13Cz6R12yaPjL6s11LD39WVXD1rD34CXyrPqaNyz7r3hsF3WD0EXuU116aOiXtmD2vqNCXuuD2KeH8Xt6D0UXsCOyGrPw5H36xyD281024vczgWrNaXv1qL55sAXtV+FQaPaaOE3RS13lD2hqsIaNBrMs+GkD2vqM3CppD3ErMMOp+rOfuFibRBD1jyHuXsC11LD1ISqW13FD3Iyr0rNWXsYKoCF2bxG/4BKN2cD0j9SMaNBXvKuDO13RXv/6jZrOTqM9q15rN0XufmA5SC9D0brvCBBcXvoD2G5ZNTDeD3EFtMNy8XvqD3Xq7566zD1Dyto5GGQFGD0+XsCj6U11rD2v9QdrNbD1hXs9rP3pOtWL9rNExF1XtMF0erMCDQ3qNuD0+1xXD1xXunBE+D2ZXt2aPSFtOXOIu5S0lGIu4nNPrO11kVBuS0lTXs6FtlFZaph7rM6FvcRsMTFe0nHrO6w6O0kmFu+btQ06mxWQj3jpD/D3joUrXscBAHXsYj1/KB9OI710zXvkqBLejvvRoDHZaO3jPTxuTQt7LvK5Cm83uF1TyiZbsxIvZbuzBu5bshFvzZsiu7r/iKbNIovWNUUhmRj0MvjqbNKbO4yUr50mosoHH+yh6j0jFuGh60ZS/11YtRscM7niKbMFFs8XvP52UbPqYlTV3VFszEsUhkmbOZ1UFUkSj3GHhMbM8j1ZLg80mPFv6+Hl8H1IuHaO+KH0hlPF1w3uU3v2tsDFuoktwN0g3tljbLaNybP5ktbNDSN2c3vUEsNea+j0Wou08p43sU3tLL2aN3QN1S5Grizk3shovvXPP2tM3v6cEpV3sSqaN0HIuG5ZBr4A3v4wvAOsG1DGotKbMkVOQtv43s63tRSP9aOj7Q2oUSj0UVXiN013QgVxC3uE3vqovFksr0C4bOgltZkui3uchFmls8kuq3ulUlgrCQ5Om3vbBkmos2kuM101IsvVBUN3wN2qj0vKKaN2A3vGI7wbPfaM2ipI9t63tT8nlSOG3tC13sUHzoua5FgVKLFvWN3gu64lr0bNY6MBwv7M2EK5yTCT2HtVPKZmlTN2MEzrG9VNvVMWx3w4NiVNl3sK3mKVPPmUtTM6VOqJkEzP6VP13vqVMV3t3cx6VODVPIqXJbOTVPn0nlHhGVOH9FOjZSHPwTCPpzbxO04N13tFiSG2H53sTlDLTPwhkOWG9VP3VPfxN7TNKMDgK4uLgL3uQl0z3uBVO12wzvaT3uhVOazNObkTwsw0IJMGGWGEHNp4M4K5lqDAzOQ1N2blYIsQnKTJH93sfTP0eM33u5VP2zMX3v/TPOzN2bkHHN5Cx7JGH3uF3s0l5akB24Oj3ueliwzPmLX6IWLotWrW2VPYJMj3ugPtpeJH4O+LUtIW9VMQPsESy4zML8Fu/zqVOEzPTYFwW6jTOHuMXoszVM6VOYPvUzNp8E4PtLVPjl0bEWnTMszN5LAagSt4OgPtYWDEPuDVO7bVYPuHVNMM6X3vtVMyZDnVPYPuOZJizN0PtRcCxFFSzPBM5kPtuiWL3sAM6QVSvVOQl2WlW/3sb3uQVVEpC94M73sfAmcVE/DI0glX5pn3uEPu+8yZVPn3uwM7nHNX3ukM6RhjNVNZVNqM4aPvI1PdME5M6qPsm4MZbmKPu5VM41N4YvAzOgPvRbo+zPZ8ECPuk1OOXNJeMrS4NMkc9GUlEsr7pzNu2K+IspbsqJ6uPtX4OKCEIgBlBuv4N1xsnM6DMlLPkvrP7VkM1MZzMhbuY6001OC1O7MlhPvn5LbXvRK5RPuS1OrMmsLDlzPcRvgNA3MnVzObOEIEM7Lv1zNPXtZJCKjbLIzJ4rvXvTBufXurxtzBuPXuEnP5bsY24LMATwvB1M1PtC2GakPFMn8HN1Pvoevil6JLPAN0n9MvLOQLOpMkv+uaJxYLMTJxabkNPtmLPaIULsz6kObzP7LAmAw+kPh1ODPvlOnG1MzPukyHO1PRjZAOi8LNAPt6WxFpzZ1NOjZhwkp1P7LApWmyLN+LNf2lrPt9PsegPoOl4/ncdZ51NzY7etDcdb/zO+K6cTgWEMZRtd95bPujgJVV2sjaDmlfO4m+OkjZVHPB1MijbJEPh1NLWFJYaj1PvPtb+vrPuikPmqs9K6HEOxyi90UyjbLPuNyPUVhHYFgixTPtGLNwvtSHOUkFbh3iZWPLO4nyrh1/PshLOlLNHYG226CdbO1MfPs/OkEvs4i4DNFdn3+x3p9lbPvqLNrF1wD63EMEvvpOI8ul51Mqa7/PvXLN3L61BwJLOMvtEUD11Nj1OyMDIvviLNBYEVr5QGHG1O4wtD1PdPsnDbDwmNEMqOmEHNkvuFh0duMx1OhLOrVwAm711ORLN9lWcvvxEMQkNCM4bnMCLNbEMth2ARZSvvDPsyOnivvZ1PCvv91MuLMlbm7PssvuAysZWmBkO/PtrzI+EODzMlbnUhKDxxUvt3L7dsn/ENEkMuvtVMzvzOivtRBhbOkEvuuyK4kM4vtg9nNPvOvt1lUdHNLENVh1DlUl1OHLN1lXNPvavsAM5396zPu/PvmHPdLNDx1BpP9KgAAP3MOBlyTRu+zValZQ/mzRuI5Om9OGsO6IIrRv1OOWd4AsNFvv3BHbRsO9NGzJ4ANFvtPxVHRulvuhh5kAMlOP4Fa3KlSxv35YB9PvRvgFZmnypONFvsjb7PRuiZNzLCKONTONUTYxAO/9M0JzGsMiANi5EXjaD9PG9NkJwZ9NkZMldamOM2snzxxLAN+xuRFGPMOl9MVPkisOOOPn8Toxs6XMdvvYxv3pPlGBN9M8ZNMYxExtQxFBcQd9Ng0lG5bZvsV5ZZuaNsN9vsga2xOOMxsVxyj9N7sPpXDWsMcxuFxxY8n1j33pPGmTz9NFvs4ID0HlJONbnVTXBVvtr9M8EMb9Nixt6DYxo4GxuNyFwfv79Oj9l86gWsNbvuJwGxsPE0nofudON7sNYfsgDP1OMALsGxuIZNN7rZsM4ft7vbmxuGsMV45WxtKOMjXwmcOzONyX0HsOADPVc4a5JTANzvs0ftuxtkZOUfs8sM7OMRTlkfvT9Prvu5MXHOPXBGRDVoDNnqP5B6jsMYxveaHgft3OOcZMEftxxtw0lifuLsOQfvCfsfOMhHOZzpvAOkfvU8rT9MafucECtOOmsMFZu7yF6Ww8DN8DmEuOlxvRbs086EuO1xs3zYxvzIuPJHklQuo86uvsSDPF5FbsmOfsTLt6j6jskYuNETHUqkaDPxPvTyVefvDxu4nNjI0wcMuFuysDLxYHeHXsMbdN27NbdP6DNLQsO5DMqULxscuNLxsfXtBFuKRt5bu/XvXuHzszCcNODMOXI/xs2j075ZBDNZfsbdCnxuWQj7Bt5fuXxv1cO0FaLIN3uGscPDDaB1MPxvDXNCTbPxvpuN4sl0fpmuNVZNg5CZfttfvLAN+cPlfvdjH/xu5fv035EJsgJvB5YDfvRcNluM8JyucP4JsGW3h2bgJtlDOe+JosnkcMu+KYHmoJsEJw0EmseEYJulO5P9NecP+x2lO5L9ir1FMcN+dVoNH7fs3AIqgPfWgW3sRFApDN8JtrO4FxFyGHtcNXfti8lyuMRcNU2L3ftJcOwvtU2IdDNZcN/tLzn11ZRHxspcNlYNsEmkJsushS9MHfu+eEkcMZvn+SNFuNHO59LZSuOpabJaUUmZEJtrJizvPAu6Dfvo5M5vnpcPVftAu6U6AtDPSuOVpmtfs2j2hpYeEkQ/u1n1fxl1cPUcPLFYnfukKJIzZaa6Xxt3fNH304/tdcNdgO5WPkpFE3OsX2EtWNvO13Mh0Vs3Ps/sXpll3OA3NjJFo3OxPNJpbkt6I3OC/vI3OmyuSZ1o3NePOCZ2Y3M8PMc/uQxPJX2s/sg3M0stM/uTJNosvo6X0ewAytq/sDQHbKsyb4h/SpPPuZa6/s3xOiMHbAiwytumFBDkcBMQXnrJLm/v4Hna3NY3NU2Va/sxcs0C6qgjWCukUECNCGASEyskb4kai0PO/yuDNGzHTe6MHH1O5y+/urGOWrEHRVm3Ou/ud3My/t9Hw2/s53ND4XS/vy/unflG3POcm4pzXKsaCvVcm4pzG/tB/tp/vIxMCCvlMHJ/uYPO2Elm/sS3Mx/tl3NdX2O/tR/uE33Wb553Mu3MYk6W/t03M4k5u/sQ3M35Uj3O8/vahskPPUn1UsFJRi6KsduENDFuPMT3PG85fRWh/vpUS6xPG3N1/vh/vy/vWSE1+N4G0V/sSxO/SvK84EgzCJOwPNk5xDDkpCuD1XxUzSPO8/s0wh4PMl/vnCRpJPk3MrJyB/uF/vyVKrxMC/vaOFmxN23PROvh/vlst2NAh/vvivWdXHvgKJMKzFAsAd/sZ/vvCDzPORctVFl7yxz3NWuFz/sm/u3Jy3QyOJPRNWr/t1yuqitVFkh/TpKu0Z20NBPxNmPOo+MfeBTssvkG0+NAvOxaHn/ulxMbCsYdV//u1/tVhsQJPvn2ep7h/tb/txTOnBPMsu4ln1/twmOoAf+PMnst90P9/vEActi7zZqg8u5dUS8g0X1QAfrmZRxPlcusp5oAf2hN4XGsp7XKt/CslaEcAdyPNn/urfRr/tt/udhuL3Nh3PcsGb/sUcleI6EPNdX2d8kUAcu3Od8n7/vS3OKpFe/t23OKAerxNYit90PyAeYvPSAfFPNePNfTMhJMs3OiAfcPPD/tCAcqX2yn0sAf+PMYcs8AefPNkAeUckf/tm3OFp6sAdY3OFp6cAfm/ubTOqPO4JPqj5SPYAJNcctOAc1JOwPP2AcP3O6PM2AeQAfk3NbY1GPMUcnJfwsxNmPMT0MyAflcsT0PyAfeAcLrJ9JP5cvGcm3ohJX0PH0n6k7/vG3OhAeePOyn1BAcCJM6AcsdjmAdTn0+AefPMT3OuAeRPMviuEcniYKd/tIutzmSfPOxPP+Adr/upXF5AfGitSAc97Tq6O13MZAduPOA3PRAfFPMNAeJAdrVsHH1xAcFPNVX29AcEJNlAcRAcxivWaHZAfxisLcz/PPhAc8S1Fcs7cukGliAckclwf0QPMLAff/vXX1YXGXeDOAfuAf51WLAf63MvX17syLkBVitXsweJNRAewNszPMUcmC2HH3MhAdG8zLPOBAcJxh6Ae73MOi5P/vVKuH0ODSwxJPrn2/eAxlBNKs8cnes4+GG432FkE7/uE31Oj6nAfAgfc/vziskckrfIPPMLcvWSzxAchAc7FR7KuPaGpnFyPNSAePpnXAeoge+lzzAckck4gc1xMn3MV0FZ/vAgcVfUQvPLAeD/sogcvkF7qCIgdggcwNaIvOVAd/JBFclVsvWeufQHfivFAeH/vzhNkzEB40UvOdAcv/uTJNSAd8gefKskcluz4upPQSvmbuxj6LJiPJPMSuVj5XckwqvNZvd9WSgecvPv0NNsvUSsiYND1VSgdHhNjlA/swagfCvO8kHqgfApMUSv/lA0oEQqujZs9ZvEYBwFIGgeYSu4llfsoISu+2swzugb4yRuavMr30mdUgfMOvMugeeZGGvNBp5+DkMquHZ0gLPYpNdStYo4SF3SSvOgdU+xJ7a2vNegfEpPOvPyCuuvOGvPlAf2quj2OeAfiquuW0tAcXmNHvO0cnBvOQP0ltlYjlCRO730uCvYvPetYSP0V1U1/vxqtFgdxvOQfMV1VMZaemVpvMsln49qZvMKpPHOs+3BJNsL8spgfe8smW1xgcFquAP2Zm6VgcsRPGckxawcSulvPGcmIqCFvMOvMQGn2DmRSuDgdlckG8tVk5IjnRvMScnmwscSsZ8s2cmDyhcNvaqv5cwF/voH5NSt0utO/tr8tfews52emHzZHG8t0uuVcnH8tZkuQ+Dbgf+8vYP1rgcXvOZgcmczegeR8tjsz7Dn3gcQRtyqux8s9CtbvPn8uhm5NzEp8ungdXZrLvNdvNh+vNJhbvN3xKXW0nAcQfO1StGi65DSugc58u3gf2vPQQekwE/vOmvP5czngfw6PpWNHgcHgfb8toQcmLZUPg1H1IQfa3PL8tXgc/vPNgc7sbySttgeQQcTvMjgfPgeeStLW17swG/uoaNzRohcnZgfYQcb8t8kFfgcYQc0QdAQcwfOKcOLeBL/s+gcQQeRBDkQfsWOM/swTQ69OGsPKdN3vt28mgxtzvsDB0W9NfMPSQcLRt0ON1pvlvt7sNs5v29P1OMqQfMHmyQdDpsNvs2dPl7DNvuCOMBMGXRs74WINLosNTOOW5zsxv3MO4pyH1EWQeRruX9NKOOSNVjvvfRv6i2AxtJ9MiNXOQegDP6i2gxuQDMz4VvRswDOMMOexsT4W9kEIxvXBERNWBxtJdNpcAqsMSfv2AlHvsydOAtE+ONw0kJNUXvtc5EhQcV9NrsOXMHiQcz4UUHmyQf2GO6OOvvvIFUKxvl4Wk6wT9PKQfAlvcxv0dPtGOAfvKQcQIAgfthsNksCixstvtdlDaLswftYNVVyxBsOiQch+1IfuJyErJzKxtGdPIpIYfs+THV6laxttQeSOatONqQdQNXVON2Qdsgv8GEWQfi6Nv9OiQeVcSTOP2dNgWI/9OOQdmeMOxvIdORxDOxuSXP9JyZQdgxvQcmextmOOaLCpxGWOO+p7IxtNOPf1WDsPnOO4lnhxuuONP1WPOP3OMGRCPOPN9NXQeJxs/tOyL0pxucdPZ57qfvl4VIRBZxvfQfDQcgDN6fvigctj7AcOsDNAdkgwdpymDLuFi7gweCDOIC4qAgvsPtskRPvllCn8kufujNXcDMyDOQwdL8ksDOdxtKhFYwc9xt2fv1dO4wcDxs0oBz8nefuXXt2o7Iwc6DMRfu0nNbNMTQuhItmfv2BC38nxfumDPHLv0j3Jfs5btcnMVPuXLuJIvM862MFLfvSuO8wecHnkcM22A+xvsJsUMMVaidaPhcOynPCwd2gM9fsCweFxHo/tiHV8wfhDPlMHqnhyuPA9MGHWluPUcPelx8wdZfvaweCwfucMZHVcJuacPfUOJOPwJt0b6mwdjDPcb7rRtMcMEb6jDNDft8uGAxtCwcVCye9OmcNxO0qtF6uPrftVX6luOZcOL/tFfu6wf2VLxgMkcOSlxmuM+wfVQg6wdQMCzvOo+ONQch34K3tRwdmgOtDNFJzTuEoJvDn7NV1VFlvxu3xtWuHEwAzSlmwflTMgfu8cM+uEiweSwf993cVAMJtivSQ5NewfZDNdgOb4WduO/U7hV0lwdBcMK5ohuNe1F2gMdKggNXUjwgfs2wd1W2zgmdwcfGqFuPNhuAQAc9XJwe6wekqvUsPlcObJzJblBwcaAFIqk2wcnwxSHlNuNFuHGxu3fu5uGAxtiJtZ3vXY2ebPoaODY1ubPfqPebPbOzviHyD0NbMkluJwvhwtHwco2FJwu44N8bHhwsRbOTs3nwdZU03wdXwfxbNnV0QIuAR3/DOp5t9FroaNlwujbPW7EYIs04OPwv4Iv04M2Cn/wfIR3YFtVwtER37wdkIsO4OMXu84MPsxXwu0ItgIfsXsMIti4NqD3bqNUR1MItlXsE71HzNV43zbOHwvGD1QrlUEOj5vXokWLOjwvCIuTbNF12G4NsR17wum4PQPJL5vr41y4N9ClXwe24OjD2BY2QIdj52YNW7bPgIuDY0q8pkOEhwvHbPKIv512cKYVTM8IdXbMb53Y40WR03wcdqMPbOAIvErNuR0sIn/wdfbPt40yId4aM350Z4MPylV40A7PM4M8Icg7NVD0Y4NdR3v5sgF0LSb4If/wfE7PYItFR0JXtOl7whprosQIcn4NQIfN4MzR2lrMJY0WIdISGIIcI7No40oIew7Mb52A4xMTn+BpOwnQIvj4MROEMFu07MUSEEIchYnL4NO40TbO6IdiIus7NNR3DrPFwt+IeV12EV5jR0+IfMIf87MiIcfo1C7PEIf2aPpBtBzOTvqJ7EKFtPQXLR3KFuIwdH5ly7Mgj0FQvlJqkKCmIt5Ieufu9OAfQVbXusikV7FuIltxumjEyinWIsG7O1AmHXtNIfY2BmjGeIuyjFQwWuIs+ftW7NXQWqil3XueFu0wfeFv0weihCoENFaNvXuJfslPtswdfXscwd0we2FtVPvACkC61pwlpItrIf/2E9Iu1GGwou3IvyAlNjHvuLdaP+OHcLrHkEyoubIdpovi3v+OFtCBposFFuwhANTOslsSV22qEiEMQovXtvrId7IfAHRbIdnIccwqgdHbIevLTJouiotix0xcz/IffaNCGbb4OlIvow2SOEDFt17N9ovUlt/lpZou8N0uakkCmrIv+APn9EbIdoJi22HgodKQ5lotw3s+FpJ2FVos6R3hENkosaLPJl492HaotVh2S5qQofFovUkP2x1DaOpFsz9tViA3IcQwO5FpR7lQocoocBbEOovJx2Eofm3suH2OzOf12dIv/nV9iGYodw1pSancodT7PESG+osPwYTqkZ4ZVO0lIYKCne3uyodXwsVIvf9uoocAVD4LOkV67IcZjLMkPqfL7wdzFv1jnKVMvIeex0TbEbIdWdOjovpotxx2Uof+yxn9vvCL/Ifi3uRaksoc5FtIZpSofGodo6pEN04ocgGsROHgocTtVzIuiofsxp4oeJ3tMxrhEPSodYHMbtIaEOHIepENAHMWoe2ocBodrosTlD77O+of/IvZovMkNeodGodmodzdvW7HOodi1KI3sgodOJoqodIoufxoTqngofWt7AodNF0ZJoaEPbIcu4TNot7IdyLzVFsg9tfurFFt5oe362CodnIdnORt9ESoe+5ABkNGlsyoeONJZovObOArOUhXiIOpSNAyPa/YFDxLkOdm0XF3ZhzZKOoPHse7rSOsyNBTsU4E+puX52LwhTLEk6mGPLBSOZ7sZ4nBcQk7u7pHO2SJWPRSPjocHmP3JvDodZ0xPJuJanWhXl+DtAtVfyaVOKdDLJuuik1Kwy6NeJsO1PU+C+JuoPEALrFSNlpsO1MZ2w0pvSOnAkIHodi7txxlCfT1Jse/ZdEzxJvfofT1JtSO57sMplTchbwOjG3q1BUVpAZsDimdggmvAcyMmOmrCQz6NvptfjZ3WDa7vD62wYdIYcXJuwYe0sZT/PfocM+PLSN/od0AG7oekYcQoO3SO/G1DjbyBTRIMNimtxyfoc9Js7qUVSxnSMrofuAGXSPFyONTu/oezodkYczocwYdS1U16OSKPGdlCwwLJuUTbuNp1SNjof0iXh6ORG1oTbh3KCG3RTZ4+TJHtIpxribfGPoYfRTaWQBL7vtCuP5JUGNcm2yYdoYdV7uNxlwYdT/MzikqxLzoekYdsiQfSNV7v+plehxvodOHtNdm9uzgLFEm07dksYeAptMfly7RRKNZSOY25wCSBKORimntAWm3G63y272nA5JsmOnM3bSYdp7uBYcEYeyG2UmWBYe4YehZvGBNCYb6YctcCddmAxZuKPO7ujxnl+B6G21pGVO5zGO6YcUBEmGN7ocdI4Z2zRal+9kpplFYeQm1q6l5YfTyM7HuY24jofcpvFinAu4WKOeYdLEM6YdByMRYfSYfiptHHVlYd+KOdYdYGM3m17VORYfdYczvzmGPtSP9YftYdNYe0/C9YdusolBNqMGNcaOHswYft/rN5DTptqMGSUjxyOiZvLYdZ0zcpsKUk3VNdYejHtg1PwbIupsNimktZaGMDJvbYeTYdJ7v527E3z5YdDoflLrDYdjoeRLpWGMyYcrIk6YfXYexhiJYeGm2mMGxYdqYdZTbOGPJpumMFyYclSNg1OzYelwOHYey9QPYcGYfLYc2ZgTyPq3EjXzU+BmG3GG2nYekKOoKNqMH7YeVpu5G3b+4bYd4YeP7w7Yfg4eMnzyBQRJt3N3b6DbGP0Zv4fmE4cnyPOKP83G44fHYfLps8fkCVS9Yc2KPo4c5YetYed3X/GO5m21ikaYekuFrYdh1otYd2YesBr/Yd6HtCB6YYfRakvilc4f1yPRYqnofnZqqYc44cp0pCKPiHsM4dryOy4dY4dnYdI4eU4eqKPVCye6ljCVE4eRZtv3VVyg//NSm19+4o4eQZvT3XY4ezoftHw5Yd3YfS4fPocbXES4duKMBYci4dMKMU6m84dvYck6mO4csyPonu1imKYdMYf525CspuKPK4cW4eIKMTildvMtHuximba6aKPzm1CB4rYckZviMGluqVyNM4cesFVYcRm3zPbV+pU4dqKObikViEZm2THuJzm0+E64jsZv1t5p4dcZv/pHMolU4dM4ciNyNYfzYcK0TWKN2HtKk3e1QWvlbYeS+GqYf84d14duKPHHtV4dg4fYHs9MHBcSzoNl4e+1A24deqFJt69uwgW194fZ4es4f3ku3YcT7tHN0ztyqG1M4dh1CJYenm2ih144cD4c8HFF4fVKMGB1A4cL4e4VDc4fzYfq8BGmOPYdb4flSMZKPqfn/Yd3YdJa6T4fL4d0cRF6Na4fVh2FilxYfbf1Jj346MA4dK4BBYdGG3YBFy7ldEy9KPAZG34eDoeeYcf4e30Nf4e2Dso6n5ZtAwdbE6YcD/imMntQ/3AEfQSmsnsY4HgEerKOQEdaB5ozwwEdKnsApOOB4ZkFh2CvKM3t450htZumgfYsEoEdynsMStWO4QEeIEckSswJk4EeTZt4EckEccW2EEdEquTePct4p3waBFbW17VNpilrZscRMs56OREvZv2MEaYd7ZslH0zYfU+CmntzmOmMFCfSBqPMEcD/oIqPOqPsEfWWO7nvKh3jbrjxHOnv64cTodMEdORMa4fdbkoqNy4f+snKEdggGJWMnnudikaq1KMOSH3QPUAWN5GtvmOtinzocvntqt74xx1SNxnte4eerK0qNcqNJW1wPWa9ko1645t9+7kYLVgvZW0qEdOqNrW2yEcHofFW0B4cnyiUG0XW3v91GBo76M25sB4dp4eBGF2vl9FycJb2BFfW1uTNHX3GEd8nCnSB7ikCyBfnsKEefSYhqNCW17injsTqgseEdSPEb6MSEd2241J4iEdUqM9MH7loTGvhnubimzYenMNpqNu5tt9wUDYcxutiQCyVCxvBa6IYeHzlAxsBl7EP4IqWLRvtEdVa6W9MqqWTzmdEc/qpL7Y9EcDEcejadEf/oB9EcwsM+QLgOUwfsM8PQvmb9OuVGfl1M7ZdvuXDA4LkcxuMxa0pmrEeIsAeplLEfK1qJLZx9NoLuoH2CDY0sOsyHM3YGa6tEe6HlgxYtEdNsPCqPJqSQxu21lrEfC6FyVBzyHjTu1EdnQf7O607Yoxuhu2jI56LYqtk6XOFYdX0F/vtbLV/EeLEf4xsK4FfEcuONr9NvEcpQefNHPEcm8meANLEPLa6LRsnEeHEfPAPNlEM+SzsNbsPMsYrEfsAOAtbjSkOsM9lEkyWyxvwiUQfwFOMO9N1c6DEclOMIQHODZNQdjCWp7arEfP6CfLagfs0kcMkevEcixpbEdNONY+FgLHYfsKMG84dskekke4TsMkcZsNGBqczmrEcPtLmuEikdquAPEeCkdMkDF7Z7Ef+LuQurQ7ZHEfX/U3EcgDPG9P2bwIkdXEeiPF8tiRsNQxvgloh7aPEfxl6co3vEcskek+jAkeV9MscD6yVYDO/Ef8kd4DPG23Txq0kcgkfkA0WkdA3Pla6io2mkdrsOGkcV9MYkdoTB3uFwkfyke6ft2PuAnML2AmynguOLNPBkc6ylrLsJA1hkcIweaylAWrwarRkeXXtAz6Wyluym4gNhyn8IzJkcHjNcwcaQ7hylogNxynZkf+fsJkey6DxymkgPXrNePxEhJ4wfmItQkFJkd0gP4wXBIs9eNLId5Pu+eBJ3pfJ0FynMweBFunNPnLucweocMbxsjzknnhikeZgNEWJ6kcRgNd8ArEf9kcEBJ7a5FwdpFszOxS7ZDDPRda9keZxHo/v/b56kf5wfsdV2OW6gMGuMtpJUkf9ke4+F9kfVcOLkdikcBgMbkc/9Yzkf6dYkrjzDP2wdigKbSprftjDPqlvvEcBgMXkdcbnugOsN3yFAIkcRgPjn0jEeoJuwYZ2Dauweo1xEfqXkfYJsRwfUqP+gi7EcWrDbF1Q0bs7aE/uizZVfvVcNBvoD7YZcOgUeh/Ajke/fu0KO8Mh2cPz0rZ90CrqbkfBDNKBEtjyTDPFfsrNtztMMke3fvnwErEdNuMwUceDYt3P+x2QUetuPlftgUdr0EzkfpBEEkdbfsgVy/kcPkergwswMebqYUddDPL8NbEzfEcJweM4H8pG1EeZgOktbDSl3keqVbAUfXkemi6CUfQUeSUcm8l3kcKZK3kfucMRHOnEf9wcK4GmbFLDONweqUfNuDfEe1wfrraMnx8gBSuP57CNx1jCXZwd4UcGu0FprGuNNfsoruLSWPkdeO0ZzYt7Y2Uf6VwI9VtLZwUfN4FB+qYUdODPkNodEdCUfESxQUcw/vwVEUyUlgMAUcxNscaEucM7Itq84mUdcUf+UenEd3cPNV2zerjSnVfvIVG+CioUfnkdkWrvkeWUdt3UIkdnxumu0NEedgOs9PAomYdpGgPdcOOtMadzOUc6Uec1v1nKyUcaUemu0TSVucOtwc3Im8MiGcOKUe1lEKUc0UfPVbqUetwcm1sBUcQUfvMERDYQ/uKiWxyXYJsWgPDVokUdNUfALJHkekUeqxq1EdEUc9UcmUcM/s/nvwjZX0OGfizvN53WyMM9h5dSHKOMIUOUyWOJDQqULJxzcNDsT6ONzgq3cN0/LqOPWUaAtuXO08HZ6dVnUdRJrqOPghhJIWlUjJWH2MP4qH0/QpYODaiTcPMu1SoOl1BoLXvUc2H5QvRr0GVwxsjtXKUJjzLcPbUcHYNA0dgYnbUePYP+9UA8P5LANUkumBDkOeGBQapzKVe2KktvTZSNWEXC410H8qG5N2zWF4UOY0dlTGkjb30jgLXPUeg0d7rzsCXWCCVOOCBzc8M9kXtoNK8rZT1vYSvYO7UPKC1kTlb65bUMmWUq1FLiAs0fhopZJnO9VM8P0+3NoPXWDZT2o0fCHEIEvyJ240fHDbCk17UffUerDavUeNfFE0eoj5r0NHdnWCDzoOz0OBWWHN2oj7K0faWVs0fx64PDmM0cvM0RiCbUe2CUd/1AjaPUdrUcNUnC0eU0cQ0fuD4/sqUyWG0cbEVZkMm0droP80eDCUg0cgYsXkNLUd8jaeImau060dkHEpcwme2s0feDY+0czCMHgje0eGmCe0fcdzkyEu0dou3/UeNWHjdUC0f2JWCKW3UcKGlY0eM65W0dPUdqHLtOOT3jQ0dsjxJHEt2psFHZ/ha4zFUnI0ekyU20cZPyUCMw0fPoOmgC+0dHXkNUkHWCu0f7UdyDYqpw80eO5nWYs00diNWyuLGDbU9XZT0WcTfDZUvz4e17Xh6GqHQ4c0eaiyClkmYuV0dlHCHOO9TgYp0I0fx4ntpCdACju1lWXy8EKYswe1R0fCHEadybu0jnhht0X03yUPSQz9d0z0dGBwcKmQ5Jc5GP1Bz0fXmBY4n2Yvx0Psz7rUeiZApUMX0fV0ct0dhYntaR7WGETlr0dV0fl0eF0fg0dIt1XpCO0dbUeX0dC9UIe3z0eAYN30c6YnO0fuJ5S0MPZG5jR/ZG7kSe0deOwNUnxX0wmU30dLymCvB/0cn0ds5Ge0SxUOWgw3jlXpBv0ckqEh7R/Q7pcwaWv3UeYMfi0N+0fGDaDBnP0fHUeBQ4Z0dV8M20f7g1/0cv0fvUm5sScdtU0fvUnzpjLCN00fKM2D0dN0dKyUM0ca0c3Unc0eUmvgMf3Yu10fbKLlUmQMfLCMEMcfERXUPSYmy0e6VWLUPL0cUMd70cK0fh0dsMRb0cMI3lUkn0SSe36WXnBEmRZoMdh0cL0fSUJkMeC0fth5EMeheJ40cq0jRe0jlN85FOYT80PCz5r/Kd67dCYaMc7IKH0f6MfbT3IMfdoNxRzH0dl0f/PVJ0PwMeI4sm0MK22n0eIyDX0eOMeEKkv8yR0fSvA2AkFRZCMc+nzPyksMdTIVJ0c0ISj0eGMfch7eMe6MdHymo0P/0fth4qMfCMf40l4MeHomq0dWMdQ0P/KH90c1h7WMfEMdGMe/GKBNWZnqZMegMdu0eQKnpMd0MeIvUpMeeMc/yl+Md10eJh7X0dNhK60frzphMfnUewyWD0dvFJoyUh0fLCPXUctMcV0NT0flUnb0wK0P/0coHGxMff0cNUkSAQgRi2CUW0fh/iu0NLMeX0ceQiyMfQMffPWUMc0qFKQQZh65MeXfE4MeGh7gxrxfEyiq+h7X6lkL3BMcsjZodVkZ3+McoMddzAVMdAMeX0fA0qT0dbMcXSW3g5r+H1TAoMdLoooe3oMeH0ffiaj0cH3hVDYAsde8NnMcu4uSMek0dKMePfE+GH20cXSU16rBtvLMeIKqkttMMcMHGh0M+MeaHGrMdIvjqjuHmAs0dvMdEkuD0dMMeykvGMfNMf+3uPMc+Md83uzMdrMctjEv25QMckscfVygIhzMfwEvYdWXMeeMfb5YRbpCMcoscDVy4sesseTVzy0dFMetewLpNyuH8sdukgpZPsqKomsBLQJq490diLUSsfKEvomhDyUNMeFFyLUcKseflyLUd4seRFz30gzolMMf6fvfj3/VCu+iEkHegsKBB+YnygerJn6sAWqF6sdnh5EJKGseE2DCnuVpAPga6se3Tt/KAGsdkWAZfw2scqBA3gbscB+8CryXxJ5msdAzt5a28bZ1KnueBesfusfNcAuscsSsqnvRUmaPz8r0yNKxuOyK730HP2se92f0czQK4NyHZtkDY9GRkDuJoA6uP/ERfvACSPS3AQMfVpxF2vfbInYMErxM7bxscxscVOwlsesgWxuNQXIMKWVscLEtmMcmSOFsd2MdfUg10HQeAJsfaMc87atsdVsfIt7jiPNgQ5h55MNP1zwVg/yl+MON2sbOA/yl4UO/LQyzvDPXjscpbQKzvDPXDscAIkqzvJMddMPFO210wMvWPUfENhpzux+nxkMIOttsf1sdFiONseHPUZ0f4SOQoYnYPlASyMOdsenseDkxb9u9seGh7UUP9iMgZSBh7tYhR9t3ODCHFLHPmuETsfFweJRbn0MoNyb90NM360c3CrvuC3sfCzjoSPPJr7Mejihb9uNseYKlKuE/L1tsdN8ZDkMbsdS9OT/j9sdVCqAcfWNXzsekCoK3tH5GpMN/rSzsdIcfLsdRF6ZsdwceL0EfsfdW15EsUDZdSAT93sh7gcfoSOCOxRMMbUy1Lpd2uTsd1gRiMNKVi690NM0aseFVwoprI3uFWx6LbPuAPsdyz5U0YDlz7UsW3uAvgMccVaptscjb5xse1sed64XMc9sfeLISXtTMN8ccefISXvIcfCVwcqgqcf4cchtzIOPsCWKcc5FifseZdxr0GlscnYPfOmfLZGcfvc7zUfWjUZvuGsOWcfEOONyEIpKSQerOPsUUyQfWcd7rElvs8AmWylKQd2cfQeFVvv1OP0GEaQcucfnPzaQdiAk6xAuwctvuT8GGQdHxHRXIW8nFsNX0pFQd2cez4oDvuoAmEqDDvuIZNchJ8xvjvtchJuQeMftf/NZceOcdHJALvuEiGVU4+Qfcfvasv+QdDyF/yGbvsVyHjeY7vtnqMnwn7vsO5FRcd7AP3OONccKsNPQd1ceJQcpLFOiakxts5EVce2cdTyFhap99Pxcel+IvvtnpONtodQfGLGmEK9vt7sOP+IZOMAkfZUu2DAVQd2cfrvokke+cdSvnMHlhcdfCBmgPtvtRGHjQd7sM7cfokc81nAJyofsVyH5GFjANn9P/0uDQd7ccpvm6xtjyHVaCEftq1n5VgLxH3MOZkCFwfPce+W4LQcPcfBsmFxF0fu02KEyStOPZce/cfFcdzvszb3sfuFcfAiprvtmOMvcdHQewxv3svIJHIDMncckGYifvy8FtOLXQeRQd3ceTsOcZPo8ezsNPQco8cvQdc5HnnHkDNg0m+OKnQeGsN/nG/QfNnNGaG5xtZQsyFuIu5EqlGfv1Al+fsQwf4wfHZCM8cwwd7e7lWY2fsXsNHXsr1nOfvoweSqkqdUufvc8eGtD3sPYweKqkC8cqDOdLtQ05yqmlHnsDlCqmkwcYwdjBvOfuUwc0nPiTFTxsO7MXLtdkcXAmrPomDMXUYswf+ZMndPfXsa8dQnPcwfGW7YsqODPUcNm8eCJviuPwPIeDPSuOOsreDOmUc/AtE9LQJt1uOW8c/fu3xu4LGUrs/fvKwdhao7DNNftogulwdZfvctv5fsW8fTKSMcMGwdp0oNwfW8e9hKCrvAJtI9Mx8frxnlcM9nJFDMR8ersSJ8ezftMI05fv3dOpLE1DMRuM+LHIxvrfvJZ5osn5wdbBJAJtrkfjXP17YzftB8dkrhWslMcOqWbh8fW8d/Cm4/thj0C61+8djfsMdBF8kkcMd8dugNMcMtQ12gMU/sTLHRuNLwet8czDNFUdrwcQvm8BMVX7lHOajOsothHO2QPxPa7Bu+QM9qnr+sNruu6nFcxPzsYSEixqXjHOB0D457+uqQO78eH+sz8db8f9rsil4gCDn+tALtkRNuhuDiHRyKehvB51zGUQbswl6TaONDHhB3r1aQButB2I/kDjGojNLIl/+sWBv0hO9wu4LvfBMmHOBQOv8fzHMkjPjpynZAnrsJMGJz53BtULu3BPSzwDbOoxvqeT+HP5hsfIk+HN9huoCfPrst51XOWuHOIRsz7GfrtXJHQCdz8cz8fiNL/rvRJFQXJAbsCY1ChMSBtkCd5TnMBsz8dwoRsBtQRux9Cf8fz8cBQR1jFZB2auV7+u4CeKNBCBsgjPi3aiBvz8fcdzUCej8H8CcMBt2jO23bmBv/bMISFAmQsB3z8dTSTzHP78elgs0budpwmzjaBuajMrlyjHO2QNqp2OButB1qp3THOojNPkDmBuRhuGCfLHODB16Cd2BuvhtN0AQCdQGVgCcaCe7HM2GGCUAeBuwCcU/2cgKg7P0jPSwnghupQMISE8/lQGXoCdKCfqbtrJEeCeRBt0iHSwlSHN8LsuCfwCddjNiGFqp0ZHOngsgN3mBtmbsAnM5QvQGAz6G6jHlQvqZbbqltQMDIfbt6pCcgnNlIeLCCy6YubtFIfXqmZCeebvAamwallCdC8fr10galNBtAvY1CdRbsePvWL71CeCRsuSHgOJcRtSRseiCIakDBs7QO1kfuZOkV0+FseiCPcUsnNHLttkcG8eLIfjIfLIdpfsTV2tosxRuETOmxuihuhh1WCCJg6fbtURPEtzKrvR7NBP0dlG2DE5h1ibuohvNbvb1zbd6hRt2RtL1bSPsXBtG91oVxhCcjh0RRF7CdzCfXCeygk7Ce04T1qmLCcO+59qm4rusN0v5zXIsrCcPiE5IuenP6N3fpyfCf9h2uh3v8DinMQhuP778HPIwtmRMPLZNbt+nMn1zHfYmrt/Cd/HIakmLCeqBLxTPgTMav1h7OEwMkZEshu3CcsvovBthF07J2L7OCwtT77v0LDMF5rvoidx7OQ7t9ofACnSr1EDb2SPOr0Kr1TJv2r3JkMrJvWr0EjF0ifar0qW3FyPGr3RcAJHvmLZoNJFMGEptqCkyahbofgtu0iBsicGYcMcZmH1NJvyr1zIti7uIzqQhAXofer2D+ac5SR4dOCkfFDtwM+Zuhr2ob2Miea4Skodlpuxr23j3RSOJjpSictpupr1AgtyieZr0iT1GieBr3XFHtSMFr2xbHqZslr3nbHsicVr1h7k+ps1r3Uz3oYceiddqmCictr3JT2mJtOifoyMJr29r1NSNOr1/yECT33Jt+CkmifWieTr2oauUpuzr14ovroeLr2JicsHvXDHZb3DJvVr27Z48T0uidiidkyMsichievSMnr30ibYUPG61Xtppr2OicQb3OieKpsgb0+ie/psAb0/Itcicfr1vz1eidNidlz2+if1icSoPxid973XJt2r2VifoyNhieXr0noeMOHFicEoOXocob16idOHsYb0RiedazH6Ootr/T3sid21ThT2OicCb1tieKptbfGeie/pvl+L+idcicsb2GUN6Ju7id4/MYtV6Ylz70fIPons8b21idJYda2ErieaYcLr2Gb3TT0A4eUEN6b0Bicyb2e0MJJtzie9T0Z4ekmUKb0fid6Hsab0Iz3sZuPiehz0hG0Gb2b73eG1Kr2mb0/IsipsHifmyNsIcVGHzidrieOb0/ic+Zso8eQb3qZvXnGa73YZsoSfOidQSeIScKm3gHvBb13T0mptyWLDXB5ZtuqGTb0wSdFb0vd7jpuTifJb0ficp4dKlpV72mJvpb0gz1eie0ScKm25Jszb3/id0iekuB+PSqidWENjb1TJt1b0NiesyN/loQ73uiedb05JvMb3gapuidTYftbPF7287sESfCSeUpujb13z2hJt9Fq8ScFpucSctT1MScLb1ppsDb0rb2yHvrb1R2JPifiHudZpyCoF7uIwm470sSdyifVWIpz3E4dqduE726HsaSSh71WSeGHv3b0Bb0USd8H1PidQScpxCBz1ESffb1zpuiZtc72ESc7Hvg72eie/idC70XiceHvBSfCScxJvw72rie/G1iH1+SemSfGSdAScpSeY73XpvcamU72RHvNr22SdKz0X4emH12SesSfZSdKYdSR3mSeZJtGH2ZHts70s71oScBSeiYcmanc73iSd872sKPMb3NSd1KPcb0U5qESdJifxSfoZsxr1Hcpy72YScxH1B4duqHm73p4fzm0GpoYSdoSc671yKPK72Z14DHsJ4cDH3Zb2iuHRSf8XGq72fif3EM270ASf271rz3AScaanO732ZsJ71r71He1ESde711Ydxb1R70SZs0SeJ71zpv7HvPENS73MZvWUkpxqqSdMScZyZ/z1oSfXSc8G1vQkMNKbSdoScZ70GpsrNIaSeopu5R0CRg+idQSfqfwXicOZscfMxz1oSdl70HSc172K73KJsN1KNSdQSft71TkMrJvN72GicZKNd70bidZSPYyegyfISdD71ontim2uerP6la4eT71HSdtKN4wlcKDSH2JZtNXqHr1v4eFqGb70Myer71r3w/4crJs771E2GYm2c9tH72YEdOL08yeuKCUEdmgcbEDX70VZvtZtv/YPLGQEdR5m23u8ye89siyegEfGsckuDSyekEd8yfsPYcntYEdhcFKycs5B1Zs/72VeGzZthsfUEcm9s9PokV7LZsAkCz6k2nuwhCz6kvZt4H0eocKW3xH2iLT2bHhW2kH3sdtUGnmyfo5l3qGuyf0H0eGGi5s/WIIqFWyd5Sf5nsdH3+ydWGHeyec8AMieC5v52JNH3A5toP1JSfhjZI3qQ5svu48rkGEcBH0NqFAgsmEdKH1OqPGqNqH2JyeJW3r+X9Sc/qEOEe6H0RycRiem5upSeiqPOqOFSfAlHBEcPwZ1H1hE3OXT673aidVyerSdOSnhEcDH30ycc5u5RN2pqpyfxEfHVy5H1sif+EfZrmRyeNyczzka/ktyeRamuGn0MMdyeSQZuifREcPMvrHkGcKifNDodJVAFhZ8Sc4nlVfMD4c/Ec3fOLycZmr7fOcYea06UfO8idSnn7yeE7vM04/jQiicanntguhJurydpfN/odLycCfOHofQlULyfmG3JRmTKo3ofAZFgknjbS5SO94fAkllgvdYffyfqfP34c6rpFfO5pvc07bNv44fflY5Sk7ydi4eoTZgkmxfOXyfvydyfMjYcbkGwKcyYdpLqUZQam0DikFLox/NwpuQFACGwFJuuflIklZAvroc4Kew/O6YeoKeQ/Pg4dIKfNfMtpuQFD7fLgLEYyOQFCgKfAKdsGGnYZ0YdF+PJJDJAuCieQFCREGsYf4KfplB5AsLodsGFryfyYeyQWbyeeYeUKcIt09m23gk5+b1Se3gmnyfrydtX5AZuuimoLpeAuzodYLo4AvYKdYLoEAsnYeaKfaAtEKdqKcxAvw4fKKeEKfUYekknkKdQKfflZIguAYf6cPHfNvJu3gkjhVEyNbYcdTEXydN7uH9F+UEP/OqKcVoJG/NiKdiTC6KfeKf/2D+YcYKdrqAJ/PnYfp+NoKcHyf5+NhKdAycNlZBKenidim35+MqKfz7v4xm/AsnJvtCuhcPyAsAKdhNvBHtF+NCCfsAsmKd0fpN/PuKOTlb5Kek/P84d+UGE/Mcpvqxm4/OeScZ5DTCjHSetYcWV7qKes4dPj6RKe7SfuB0f40FKcwYftKclKfL4fGyAtKdjoc7V70AsjYe9KeQ/P1Kco5Kk/OySeDiGn9Dc/OtYfvBGSnakSdZBNhVqy/P04eBy1m/PU4cxn7cKdC4d/BM46ChAu6YfgRCD/PhKcULbuKfvYcULblKfyYcUJCDKdjofr+PGAuXKdTKctHs06nkEOb/MhKdln4kKfhYe8LYvKeXiexqm4KexZujam3KfA4dkmlXKfqAvUYfnKduAt7ocnKcayx4YeHKcFKdI4d7Kc7KcTKeRqlKIRZKe7pFXjUFKfQKN0xv7KfUKcILad/PAKNDz7yrrv/P84cILboqdrKd7amj/PLKcbs63/MzKcI22QAszKfhPHzfPLKfOy7TKd2YcGXYYAv4qf8LKPKceHt3amNKd/ocNjW+KeoqdpXaz/O7KdkqeIqePRsbKffKcbZYEqewqdq4dwxvrNsxHuRPa4qe64ck6niqfcAtPKfIqfjKezofJjVVKfdYd8qfKAueYfcqf6AsBYfnnkxAvHKesqctSeuflMqfGKdu4cGqer/NpYd3alaKf34daqeQAsQYdCZGcqc6qep1yxd2SKcDfkgqeXKejflLKcuqf7TzzSfCijHz7tPFKqfsqeP7Z8fQJm38OnOBMpZg54fBBPiAvLKdT/5O/MzKecsrs/Os4d3478qdxqd3EA5/PVYf+pXaAv4qeSNr6AvN4caBPXKdt4feBNmAsD4fZqd6qe94ceLlRqcyYdVqd2AszKdftJeKdgmhxPbW3wR/MzKctqf+YeVqcXNJKqcwYdJ807Kf74e11bOqc9qew/kMqdDqfo7poyeuilrpwcKf9qfWzKPKc9qczqcn4ez4e+S38Kcvm3GBN931FAsiyM6ZzXtOPyfQqcxKdP4eV3G23ZRLFlqdIKCPyc9qfHqfLfEpqcxgvzKfjKPJCfYvaaZJJJLyyfcH53qcSyeCyeKSFPqdqyc4/0UmbPqfdZuKSFQSm6yczKMpmBW6n3qd6ydaJ6f3OSIUDZvcH6fqfvqcKyfbCC/qe4Ecfqci6oyyfQzt2DMliG0fNRvn0EdGn74LHoadqAtSW1EqM9PbetiLLG2yc/5zNpldyfHZuRqnjNuCEdORMLy0twVYafftg1LHfZtln4dLFsEeYqdpfPoadyqfBye4aexqkIqd/ZsYH3lqkXyeaEccvYOgumgjntUcvYWguD4DiRPBQkMgtpyccvakfOa5vGNUiac2gs6gvGqv2qe8qOOEeJXbOKf2qMQanLyfyEc0/1safaac9PbRAt1SH0ae06mcgtGaeuqcVnvpH31PZA6m1nuNW1SZHNguNnvtSu06mCafHZtI6miafGqOFPbJARmqNrnCdpxy5KrLGG5vFqn2KcWMNLW2WafagvoadHvaZgs2nuFPalYieqNTcRPlwGadygvWqP5pxhZPYguiEf5qM2KcRad26mfAsxac31z9fPBG1+ade6l2ac5yeu6lUqB9W1uafRhC+ac3nuE+O7z0/ycXntmRPb6D1fP8acZafTSFGafviJ0afKEfeyAGfMNafB8xUKc1afnPbsM6ILFJ6QRqttRFjgtdW3aBMONWxgt6OhBWNSBVCKeyacDy0tacGYMQ0qa+ONadkMMLaeSBO0KfDYPX335ac/yfU5CIYsrPZOacl4uXNtoZYKieIz300UMifPNtw0U8T1nad6wZ+T2WtsPpsjL1Vz0vpYmr1GtsPac8iezmuoZtqy4rLWIdu8dGRyccz2umMmidUtsnafLj2edtzC5Hadpmt3QnioAYtt9dt/pYqie3tujtXaidnad8Ginj3jWtc5st71QtsFdMXadA6d8pxpr3/acbVaxbE/adQ6dBr0stumb4iT1nacsMnyT0hT1i5u0b3kdti5sQ71Pad1RSuz3DtvOC50vI80efaeGb6Qb146dfKy46cY6fj9N+T1c6dUpZvUdUmvOC6gQaGmsiYmWQcMT0M6fRdEo6e06fBkgcT0dWvOC6dRBzj03afc6c2tsZKFE6e46fPdv3W4hvDHafq4EgD4EL3Yb5s6e66cK1bKT3k6dUsHc733ac21bBtt/NtUsG/r2itsm6ctz1BduHX406dydtrdEw1aZmsLj1xX4TFR3Udu6ca6euT1O6faZv7WuXj35tvAYmIK0CT3ZtuiCWTX52b3lz3VTOAydnaeUnJlz0x6ckz1M2u1muHzOU6f3afttvpT0kz3kwlp6fZT39ZSRC7PrDJT0E9tkC61z0DCPgIiVX6x6de8O1duo+Pu700z0SYlkNCbb2CdtkNAG7146cIpbrT0zduhX7N6fbT22WtxC5TJZzz2AI5B6faP6hz1ntuA9H5FQ3muIL1AsCm6cI9sC+Ns6fXWtbzNHz6Y9teKEGLB6z3A9uOp63r3x6ca+Cl0e9z3ag39ZRvtuuKEL6ct6eaWtq3l4cl26eQ6fcumlcgHttBp7R6cGdsIg16b22dtJp6z6eqdsCp59OJHz0s6eP6caWtldusp4R6f3aeJcbcz03adrwnsz266e6unMz3PNuH6f4L3k6ed8mO6eqBygzPG1bEz1ldud8kp6f9tvsGnjd4Nz2C2tPTPj6dats/zMCSd46e/6fr6fTj3bQf/if16dKul76fIGfockxz10dvjTO4MTpWufacYFWL6cC6dZp5V71UtvSll2Sduz0IGmTnNKz2advwW6HHQkGe6dtZp4f6eX6eUcl16cI9tblADSd/tusclvz2D6cH6moGc6z2em4g8ZRWv9T1SGfgGfRWviGdH6dZmsX6l9oqJWsqYmCGeBz2Cdt8GfX6f26dUGeEGe0z2Fp50Gfi6cMGesGccL2hl4sGeFWswGccGdHz2aT3cGcwz2WtvaGcD6cEL0aGcSCXOGfdBxx6cOGegwpH6e2GcT0PgGcwGc5fwNz2xduhl5eGcDz3GGfuGfl6cGGfeEtXz0b6epm6m6duGeKGhrz2jz3F7XR6fxGdr6fTz2uKG/m6N6cjdvBGfS6caWsKGcQGm5NhVCUbz22GmbSc36dLm6FGc7tuYRERcmcGd9dvUD6ib3CGd395Xz3Wz20zMYGdcGe/eDW6ed6emzOqGfGfFA2uT7V7VacduUGcSpZ/z1AGeXdQeGdL6dsiylGfOGdXadUL0ZGeguAYScP1UdtuOSz06e1GeI1ZG6dQ9v8Jx0GfOGeqxpHz3rGeEMMgGeIL19j6oGcHGdaMQMT3OGcnGcsT1o9uaY006fOGeG6c49u5KE0mw0T0QqFJz2C6BxGlmGeCY3D6dDj0GGd56cj2HU9ufo3tjlAGeB6f91UHGeAmeAdteKET2xyL10L2c9sOuvW2u69uRx5t0DG2ua9sYGu5RDwmfO2tOL1meMImeG9ufhPtTCKaEK9uwmcFkEomcG9su2tfX6Cp43ZKpAlomcxcaomfQaeS2A4meeL0e2tC2A0meuRCy9tlEvG9v2sEy+DP6m+9uYp48AhW9tN9volzM+ECr2gwmz4bir3pL2AzOKfH7FGYOvjTMg6Se9s8meCmdkDvW9tBp7arnx9tRp5UGkh9smGdl2tN9uqmdFiPUDsqW7kGe12uFL16U6Ryd0Dvr6mQTlp9tgW7IUMDL2Oay/LPZhAjL0iDsH6lpr3D2v0SPr6nSH1zL3r+UuGfQOtkWJJx36mcCT3r9vmGeYpZx9sGDsamfh9umx2ZGfaieKmd7EbVMGhmc30iQr3EDsX6n/QRkDuckquWMdk4midZ9tDL2em54SwySO4OvGLOEhxcr1yOvqDuJmc8T1aDuoGldH3emcxmcN6kcmeXeCAGllmeEPwhme6DvZ1WEr0wOuHIu/m5Ome2Du5mcNLTmmd39sX6mzvzQOvSDu5m51H02mflmfFqG/9tVk6lmdwDtS5tUuuMr19mf0PD5md0Oupmftjn2mfaO0lGdemf8mfbm4ynAaSPkDuz7UKmedL3+LPEbiN0H4DsJmf7ZgiT3Jme/LNQXOm2HiDvoLPHmdoDs5mcmGn0ayxbEFmfl8lTmcwaoUp5oVZCmfW9sfC6cqFlmeYpiLmcPmehl6tWLVmf1mdXmdglhumcv2tLm7GmdF9saGm9mfTmfT94EjF9mfyamccdjNKRGnFURFiNkOuRGnkLTADufL2J7VZr3I1zsr3bm6iqwXmd39s9uMs6ClSt8hMTSqICvR+MMdBfMukWd3WJf8tO3G7eLUCujX3FGGJ+KACvW3HeV0gCs6Cs0WdT+NdBONF1QCtSCtkWfwsuV+PEWca8tEhMEWcoCver3FGEaLrByuiYbYCtzKsw4Z98vx+PSWdpn24iuXGDnivQCu+OImCuCWfIEhT+PwCvzOJH8ul+MSWc4svL+NMWJ0Cs9+PgdscsvUWdmX6GBN0WfQdsDn3kBOWWcH+OsWdmWe0yuimkgBkhsvKWeZB5sCuaWfcTQwsvuWfeDgKsvcWf7+nKstOBNXBvaCt5+OBWcncv6CukdvPisWWdEdvv+Ph+Ny8u/Mt6hMGWfaWdSWd5dt8P2mCu+dtOCu7GkZdshsvxWck9S5svUWfdfYBitIpzKdtkBNVCtFWdihOsWf5WdQKtkmmOl7hCuCmmZWeqVuaWej30citYl4JCu/SunNFQPzz/vYmkBBkwsuKxOXNGkevDxPUWd4tzpstrGlpGgFCscvEdQ7FCvqmm/8AocsWWf85shsvWWezWeqVuPPOvvFlCunKvK1nNCuvanDGBtCue6nztIRBMKWfRZT6cv/Csw8sDCvcWenjw9st7PO9WdfCv1ytHWd5ivNyte1lzCts3E7WfNivxWdhZAnivAmkLWdtytOuUStEsiukWciMKvstGhNFNKHCvxWfWhSkiunCsA2frCtA2fjHzHstgX0XBl3CukWcbEqPCsVBNae4vCv1BMOxCVfQHysIZHwhrjCvg3GA9vMcscWccNLMcvWWdHbFOcs24W2hrgivUWcDBZDWfAmlgMiwitw2eS4q2GPqmkDwRwcsqmncqxoislWcs2ebxMbWeM2e2Wel3FBUP4itVWfU2dEivKWcU2enxOCmmPULEcsBWdE2c0JM82f42f3xNo4feiaMisUhOzC1vBPKWdpFkJGOaWcRtKcctvstojN8iu9itojNOiu73Pur59Wea4UPWcqf4ChOI2c+azSitrGko7FBX0o2ffWGw2eghOv+qritXWfh8G4hPFit22d7cvq2eY81qhMq2ekIg6ctVWem2fyKuHWfTKRGcuTGmq2fKJPBWca2cWcvWxPa2f2ivWWdh2e8CtK2euivqmkB2f4Csp+rBhOyWfW2fWKvJ2d02cjX0k2cu2eDAeufmO2dhiuB6nu2ezBOsWeZ2dmom1pFp2d+2ciPXuTNaiukWd9lKJctSWcPNyU2e7Gkt2f0AcN2f08g3WdImN2TN3ZT/X1u2eN2dLAexJOxTOaPhgAcYhmcP2GRHzCs3W11hPxWc/FnA32I2eszRtisPWcgpWdiu3WeQlk22eqitq179iu9ssM14a+KHPOHWdDDALTmChMOE3I31GhOLzCViuChPn2czcvR+NobFLivRYdeVBO2d6hMP2dXcuDpEQeHbitvycZ8p7isX3GGVD12dP2dtZCvWcbXFKbGastP2evLBXitzKsKgW3isgOdNC6YhNn2fOdv+WcvitatlvivMgeryfvH3ECtAlWKRM/cvLgmASvx+Opg7vH1P2fOvLgSs32d/RQ7hN232AEdJk4nZBMSuage114WO6qgcY4EUOfISsMSsGoMMOeusc6mAOxkEquMOfjAzsOcsOcgmBsOc/hNo8uo2d0StygdaJ58tI08v8OciOdcOf6yf4MPI16Eyn9gd2RNgxANSskpNNAMKOdqSuOXXCSuERMaA7gNZnSsSSsOxCUd5v31yOfxrt88ucSuqOdKSs6Sv+kOqSuMRNw9tzStGOeR2eq8ucA4B2epgfSqs/kHCn1GSvV2eUWM8pM0TPp8sSP1Qi32SttSvmGscohm8t9SszcY28vVgfur4YP1LNvqRPlr4KCtLSvy2eT8vWOfeWfxgeFvFUsAQ8s3vPBTPwQjaStYWPQmkRSsxSuOsDRStlSuOsCdSsuOd/oxVXHBSsCuqpSsm7G92dvKoWSsxqsCuo5Svaqvur5SP2tgdOROlOdFSvapP6TMFOemOe3MBH8vcRN49t78umvPUxBn4o7gd1OdWTMe6xsWObgeGmkKOft8vtV1XZAJRO2StuGt98siStaTOuSsSpOLOe9SuDStsmmdSvL8v6TNROcbGR9FzMmkc8tGOfJOaHGuKOf2MBH8vROdMAh78ukSETgsWlv2sGtpxPQPaR1YCBXDAyR3Hl3CWPzE1odM2RFrgu/h1N74fOefh0wCAF4WfOeVFMv1N5l3U3bbgOfOddzCP1M/OcTlC/1NWR0R/le23gR3CwnEwNSeOC2PCwlF2igdMczPi6FqJn3Of1AVaQNAdMl/mvOeINMl/k/gMHnMEufCNOjuPwpt4ueYdP2/n4Pz4NO21lamMYudSl3Iud3OceR3lAV9E2UNNkpsKybUdPzpPwuesjNG20UY3rtHcudMdP2/nsueGl2b4O9TAsueA2MMuekNPPOcjv2hNNnh0vZ0kuekeMzAUhMG/h1E8HhJmYucBbAyNPG2082CvOfHh3AdGbgRnl1NTNC5Mv1Pbl2NC5F8A9sFwueC/v2NMBR28dFKueuR0WudGNMMzMapzYuemdNLQnYuc6ufylw1NMIl0s2C5ngkXPhR3vQlsNM6uf1cuudNWuf9C4JR2+ufutUyucrWNKdFOuftpOaC4dctBNNVTPhufJR2hdMs2C4GjAePHWM8C6BjPRdPtdFHagJNNXWNeuf8ufQeNeufBQvpNM2X4kwJZNOaud8pw2ud6l1FudpNOYeP5ufJNNFdMyC5iufBucDtKVNMtudVqQOXN5xtJCcZBtS9FnWPjTG8DODRADWmeXMRkdpOHtWmNNMDudDC72ui9NPaZOdIfc2BPWmTVnx7HvXlDNMK8fRmNLudmZNZ3ZrucJXMTIeruf/XnpXMi9HVSp7ueufvF2CTWnZXNUweq8c0wcPXv1kezxu+RDfWkHNM12OjCdVXNG8cYh0rIcx+VLHBVmmox3i3bOQPBtPCmPn4V8V3yV1kCB26xAtOy+M/ueZudkx2fucqtPfdPCmO3YoP2Mz2PkzA8gbUtPgtPkzA+8CTtOc3bQecbx3t2PU3Zfudgee0FT+tOmx1LtFKufmV0wuf6NOSx0kYB/Odkx34efEecEtOCueEueCx1l5xOhvg+MaLMX84fOe6x1ZQkUOQZsHAtPmmNfueEef9hN/NMC9NZQk+3DRx2NjqFaW08EEeefZMCp69bDstPq9NtAWj5gwefxtOsefFueox3d5zIN4oeczAXKefkee8uDA+GdtOsed3OfgOOcedhtPfzM8ecCtNc+NRLOGecItO/x3SedYec2tNFdEbAoKtMI5OsefD4UstPWeeA/vYOOIefAdHKeeKecx/o/x13zOXZuUecYecw0B6ueMx07ZM7ZtKufkeeeefYOMT2PhdGvYd5x1CkMmuevOeKefPlUTx3/udKB2H1NlV28dFcedSee8dEpJl2JUpV2Zee8eccYJMLMPpsQeca+MMp74yIped8ecvpYOefcedLFJKNMceenZsxNNS+O4dFqedWeeTQmkbCDrZhkMtef2tPGedE5vK4DetOREN1edNtM+tMmucBedaecvpbFufkefdrNGed+V2vZunYYvZPEEOTptLtN9zPaGVex2LeeG07nsG6ed/paWecetO25vaTPVtPLEN/pbqwODraxLMSC6/WIweeg5Ms2AGTNAeeA5PnednXnaV1qEPzedkWmix3ptWa+rvudJeegtrCtPH2N+tWptOveeFQOqcHkeel6jfNOHLIhx0x85sNPLtOvL2UZvOtPrtM/nvuLpf8h7f0PbWVrpvOTPP0pv0ZbFWHQvN2Cf2VrpWeBgjvbICLj2F2tcf3dj2JCyemgKf2Pj4JtIE+fZ0EbP3o+eMmuXv3I+cY+dB4k+2lTrpX2uPv0cT7nrqImsM+fTbEw+cBP3phhbj0p2o5Ouif3uLptMghP3hf2c+cU0Iif1V2lDbFgOvUf2AT4+Lx02trv0LbH0+d/fpNxaGroU+dy+fXZkdN4It3S+dBGGYmsGf0IT4VMhumtFf2lzowAhZYtw+eZSm8WuCCXaGkTSmpmvsf0cT6vF2ed0af1MT0ikZyjsDP16+cgWtq+fa+eq+dK+eW+cwMQwt0s+d0Pmy+frrRFXZPbEGmsGf2UPlLYzfDtlqK2+fB+d3t0nCh6T0DwTQ2y4+eUPk3mqaYuG+dtSme+do+eCKc6+chv1cPn82yot16P1tzo4+dnf2KT3HWDmt1I+cy7ETmvZ+fC7HQWsm+eiPkx2uZf2R+cOPnQ2uk+cDXZl+fCd2kf18PmZYKiYu3v1M7H6+etN0eP05+eK+fjP3OT37nRCt2Ef3uT1P4rqfOEv3A1bZIsN2tj+cx3navAHmul+c+KdAd0p+ezlPqt2L+et+ftf162keT7G+cNv16T5O+e9zKPj4/qq9mv1f2Cv13j6dmtbf07ZnNcbW+dsNSHZlL+el4s9P00T6PWtQUsC6E8T40mhqv3gGE8T7R3Jav0t6ExwtYWvef1uXbhcOz+fNmPET7vcZgd1/v1vbHIz5Id1EzWX6F3+fxugzf1KT59bDJv08+fST47+fLSZsIc4T7/+dF+eMJDB+ca6Edf0JT5IBc8+dt+ML+cRv1K6NO+c1f0YBff+env2CqGUwq3d3oBe8Lb7CwPf3Z2nSyAo2sQBcuWE7nnP+f+f3j+ezKdoBeYf0bfays1Hd1Lv2e6OEWs1v1cWkis1Kd1b+fb+MbmsPP24z2MBdo+dZxDj4DnP1V2lZxD3mvZ+dz7Yl+eiBeCnpPt0CfC83ZqBdyjuX+eh+WDgqiYuHv1G2lwBcVv2Yz29Txa4vt+eZKFSBe++esz0eLqv4t8BccBciBf7f2cz3OGwVusJv24+U6WuB+flXZkBdWBcU+XOBdbNnd+ekBN6d17o0oXYBBd0etfv2a+UCBdmv21pmeBdoBfWv15XasBcwBfkXZy2wJBcoBMzmtMBf+WlpWJN+cgBePL0qBdpf3wr2r+evv20YX1XaKBdu+ei2l1+dD+fdKFQOseBdZXbuBd5f2S+VeBcGBfhBcVWv1+dj6Mo+d0euLYLDwvx+cgyE1+eNBe8BcAv3RBcOBdw+fVBfgBfSBfZPqtd0jBe/+EIusp2kZBfqf19BeyXY5BfdBeoXY5BftBfIr2A0CZBeh+cC2kTBcR6HCtmJBcvmi1BfF2lGBdDf1QqGa6xyBfc6HwouWBd4BfltSpd3UBcOVzABdbqpP44k9RNBefBLBBcitQLWt6v0+f2yotw2sIf1RBehxDHBc5v2QBcbo4RBfOv1QL0w+dRf30BcAWi7BdpBd7mlqRpa4tkv2H45lBe5BdwhepBcnfpuXZ05Wg2uU+eWovOSDs4l4Bex9LL+dI+dHfkY+eHBcD44SiDJBdZhTrWsCv2pXZP1tst0kBcIonm+fp+deGOAhfSBd8Sakd0C+dlfbFBfUBcWf5UBd4BcJEhS+fSBfchcvd1Ahc7KF88zW+d4BdChfwv0shd+8Ex+eCHFiv143bc2tShdhB7i/mIDjqyENBcM3bwOsP+c4mDvJt32u6+eYSGKheEhfXmDS2sChec3awKjq4k3P2c9uhzHy4qOtDo/3ACDW9ID2nff1Umen4DWhf/f0AMM7nny4pNJ7oGtYmcOT4rmCoCFvf1OhdmhdkCHehfcOcehcxIEg2CWhdZ3ZEtg2heWhcmL2ehfBheYMOn4BRhdXuD4/1IacrQt1hEvGE6dnU/3NfYg2vTSFphecz0fWt58Fb/226NZ2vgD2zYP8XbR3LW/0AGQUBe92t8/3B/3hmkFhdZhd0z1TdnR/2K+UAOR8/0M/1R44vvpwktVhcxXawmsNhdxBd72tKnXKYMDKEN2t6/1r/07BcN913tj4QAVBeqheJ931vZK2lgmu8+uGMP1XaMmt1/24d7kXaThdXdMSd4jhfBzte/082mDheKjj+/1uBeImu1hchBdh/3B/0NmlKnDBzsthfQr1X2vdhej4BGhdSktV/0cr28Pg391l/022k1heF/1S5unXZhdk5/01GvIqFb2tzhcTMPIqGSOua35FhcZParhdwqzLhcgRfIOspt1rYMARdRfHt/2HIuzflgOt+/3qZw/wtAOuHhe2G4X90j/03hdXhe7hfIRcePZ32twReB45WhHS2vXhehxCdmskRdRmvD/3B/09uOzvYyr0Nb0GvZnL0r71R4Wm8xbr3kb2ZvYkT3nr2bvbST2Fb2bvaDj1fr3W3EDRy8Rd/r1h4WYpg6r3Db1R4WwfzxDlIb1sK6iyBJr2w73GMlu9RG5Mzik0RfT71SReEK46VBBr2MRcQVnIYDXFF771qRcDCjQZ2F72QMmkr0L721pGRnZLr1gb3iTVh7xjr1yRcgVkVAKur1KRf4yKFr2I71aRcHj3y73UMn4T3WOmsReucGMb10RcZCFtb1VnCuK4CfD8725b1ix4e7rBRf472BRdEMgB5MNineRdub0WRdsK6rkl9r1Hb2eK4SRcolNKReK07WRdSReeK5/ZoH2ntr2MK4htX/e0RReeK5lYTH0vk72hReHeTD73y6GBRfMRcpe0DinI0E2r1M73uRdORfJ71SMkST2d5MMZHcK5cReNRcIrVxRdeRdApygb3Ub06TWez3cRdHMlPz0C738RdobpJ70S70OMklfheFMxRf9RfhRdZRe0VnnT3MlOU4WdReiRc2RfAK4YjyIb2XoeSV6Pk5Ku1bYcXS0NReA704l7xCZ072DRdqH4YSeaRepMkVchkb2uimlO0DRd1RevdJdb3U70TvYScw+Rftb3gK7vRdxRfmbqivbPRd3J0i71+vZiRpdJ0timDrZjRcQ+ph4X+q1He0mRcb2nXq2hz0x736VmrPDjb3iTVnRcoFPNoReBOyUkpb2e25NvalNKyb2t6tQmk4eBiz36b3f3FyH5Gb1672pMmzReo8FeRffReLu1nyLuB0cSCSz2t72JMklRd6zn7r3qIWI3K9Rf3RcUKBXRdiRfsxfU7W0xfUxdHoZ0718b04l7fvqvr3kxeb2ndrgRlNeRcLQy6710xcTvbhvDwxf4xdaMmingpb2JJq3y59Nzl715RfaIV/ZqmpllRfaIUsxd0b0U6lXLX/iccRf7LCI6YVb33RdGo7R73dRdixfXFN1Rda6bhRcBRdf2lRRdMu36xcnPtEhhMu0ixdf2lKigWJ0y70+xfDRdiRcHPtfz3IxdsK6yxdEb1LRcmxclb06g2MK6qxd073+xf7LC6xcLFNo4fh+6M70xxdf2mGxcP0HSOkgQt471ur1ix5XfSnb2O4JHYUFxeXb0h71NvbEQIu70nRcZxeMxfExd4MkmzgJb3kxeKjYi2CZ71LL6zrk/b3Wb0FIWyWzixdVxd+IXxT1Xb1q6kyjZ9xdFxfkKsfKD1b2bReY4HgxfxRdHYGGfro71kmmpxfwxdBxcJIU1xcwxcn3sVRco0vTRdf2nMRebRmAxebxcJz18RdL3trxd6xcmOmv167b34b3oOk9/App2sRdNxeBz3XReOa4I71nxec3VjxfOxe9xegb3uxeDxfC71xKePxcw70bxcTxf3xcJxfXxfe728xdBYGUxdMxfkOl7z2t73UOkFLQ572GRdwD5XReNxd0nV4xduORAOld95Lz2Q73cOmvnQO735xrlitxYEQL0B72eysFnoW70dxfKq2HxctxdPIXVODQxeNxdMbne71EJeWvvaTz+73KxcmM5hzTtxd2lxe9lMJcNFPoxfVM4jkU2xfpxdBYEVAL90uNRdqD73xdsxekPu4JcCJfazJu9LV714yt5gbQJe/RdwytDxcwJcQQHhRfCJcn03l71XxeaOgZb0D71BJ4gJdq71LL7UBoA71XxcFRfH0sGJdCxeilPKJcLRdUb0S9nmJesxe94ePUGPGfdY3GBOj4RxIX2Jfbf2XoS0Rcz70lM7/Rfc+2V3EwwTfL23xdQxfx70o9n+JekJdPL40ZDMxlvb0HTv3IXH70V1Asr6j2VAH3qyfLM6xJc372QqsY01hOniFIBhdGJDmqHQH2QquRJem+0vqe3XmZJd5WN1ZvmxdBOknJ7xJd6A5BjYlJcV6uuLAFJef71lJcm8eyIUMI2XZ3OH3aIV8cArqGcH37LCtJes8GsH3sxfdALmH1u8yFF15iCpL3FH1t30nPsZIXtH1ORPG0GtIXdH0cROTJeQaG8H2jJfBqHdJfoOk1RcY53NJfLJesr37Ww8afzxfl0HzJexIXCH0BpAJSsAJf08H3YzCadryU8rk6o6yH3AOnyH2BqztStrMnXJeDR5wr6MzDnJeWQTGqtHJf7Z2lvB3p57Jf6H1wqx9FzbJdOH1bJclxfmH3OH2QJfrXXtMsWH24vu+Jf2H3p9kMRftJe8QsMicDU0SqsaEZL2knJcVIUEMF+H1EsDiROE+5BH0kkAhH3AJfrj0Ipe2qsAPygaHzJdBLUaRfZH3tV2ZbloH3kpcmM7/k3fJcOAw6vu+W4+e1xH00pcVZygaEqH3s0W8JDaH1Vrob8v8vvGRfjZ5jSs4Jd5H0/Jd9lUbKH5qGwpeLp0Or3ipddxd+qH9H3qq34pf8pdmOtUicem5YU7YpC8f0X6mGRCI+c8+ccW5JKKHBf6mcchhqpfL6k5lvNP3aGmUcm19yCBcvm4LSrNTwQv0DXa+CuR63ohdP6n6pfbHGf+fapfWJte+cT0PXYTov3d+cqpebyxOpdXZaVm6JlK0v3Z2mXeABpdLf1kzOV2gkf3oBeQ+AG9hqhc9m4bTRQ5K+pfpGlYTGupclBfF7VGpdupdT8nemYJpeDm45U1JJuU+dkzPWzxjP1apdgi6IpvZ+eAi7KTyx+dLm5rAjtP3euGVpeGwzWpd6zOqLrlJv2pdJJwcUytN20+fwi7YbjB6FepfUFpA5tupet1A6pdZpddGfLNgA4mv+egLDxpfNBcfm48BAhJsW+dDpcJGDtf3ytm0zOwS3/P162mxGmOpe6+cdpeZpc2f05LMYtWD+dY+fkV5ppdo+d4iytpe6pf1ehrpulpdteju3Ayf0mpcR2qZ3DmpemzMd/w3+dk+cU/GXpceBdOj5VpfDP1FXZHpcR6Qov2mzOFcSepcTwURXnuhYfpfIb3eizRpdT+dazP0uwMusgBf9439Nhr+eDm7ww5BpvrpclJ4HJtIZdCVhnpcnP0NXmhlTNv0LpcCaDHpeE+eYGkFJ4lpdIilgW7bJ5Npdrf0Up5GonoZeuNSxX7Miu3pf1pcfm4R5Akpvi+eGY34/F24sO+fbKwjtgf+efpeP55Sps/+eFfZnb05EwGHFXwXpXmcZdsBcwGkVqglRl/BfMBfL9W1DgJBcM8G9Eh9f1V2m4ZffpeQhd3l7SBBev1apceXy8ZcshdRvUqZeHper5WIZfN+d3l6K+LhjuRpdaZdO4uuBc1WMvpdyZcUyALWS3f2LXl2thSZdVGcKRbWptfBfj+cmSCwZcFBcPm5mTzgxmvpc+ZfNpszpf9XmeZfGpfOZfkWD+pulpeM7KGZeRpfE0yhpvrpf2uERpsRZdoZcr4s4ZfPt1kZcaBfK436xraBcR2lTl7vpcxpf9OkOKbqf3sZcxZdmBftpeRZfhv3mBfFTCiZe1Bc697qZcA4nbBdklC+Zcj4qWZcJsSSZfVZfa42CZeDpd2l7uNJdpcAZc9l6wS0gyFcBc695pTShBeof2Bl7dZeRBfuZea6q8ZcuEzSZctZeuZckBfjqCUVsGhepl6v2wwf2QBfAkAKZdiZd1l7p35UZdhBe8965ZdBBcIGlZuEJZcppderB0ZfS+eLZct63NpdzZdsZejpdTZcHv31ZcJMoBZdyv16zMxTttBfMf1DZf9Zd3pddZeNZcV+fNl6MOIaZcrpc3ZfC+dBpeI8RXZeHpcWrDnZcYZcbZfWZd/Zf5l4HZe7+eYGk7ZeiYvLBdVl6bZf0ZdVl6rZc6f0dm5g5dZYv2P3cl4YXgnZeRpdNuoEZtbpe5x7sqCBpcs2lNVWOZdyZeoP3hZfcxfHm6iOy/ZdPBdHZefvCk5fIhfgGVyrBrlsTZcwGkH8Hs5fIBcTvY/iS/Zctf0k42yZcGhdpx5LZczZd4MlBXQTSY85fn0nFAIoZcABe+K4K5eJ4v6v1px7K9Tx/Gjpe6vTjWJDf1cfVQ5d4heF0nc5eVf0QNFG5ci5eBQpRZdbhLqvZ5ylnpdm5dJZfzf1kpnhrDjZfG5f2ycBZcC+eC4Xo5fO5eE5fwBfNNlkt79NjNv0+5dTpfdTsG5cQnYI5dF+fdvYvlhihfB5edhBzpdMf0n6tKN5W62n+fyTUoMtKhfKv2f01tfDY5e72mwsb82R5+dyMkhDiw+c+5eMZd0tmif17RezJh0BcIGFkOe09EArAzVD+hfeL0arAFunTGrkGvf7115dAeC2hd596XHEt5cRhdfX5hvXV5eAI5OhfN5ew/1uhdVZsgpDiiXRhd95cjbEd5eD5fSnvprAj5cG9AhheM9EVtYD5eN5dG9uUGtJOniWFSksdhdY6zK9S5heYReb5d/6Z9he6YNVOmv2zp/1lhfW94jtilheeoyCY2esqVheS/3wW4HIoiPTRks35c6963/zD/0XheDl5X5eH/035eCY3DZfHheP5dLU0DpfXhcrWwepcS/39he062OpdDhd5c2XZfg5s5oXjhefo2hlQH91mBC/LN/7Evwm3HTzhfRlCR61LhfYLMLINwhOz4Eq6IJl488ie/23Phi426BBA5tIRfm96sZdB/2/5d9Zf/5cf/2u3bYoD4FfAFfk/20ulLpcMFc3LNpRJzpFARds/1MFfUFfcpfoLPQRL35dfhdF/3h97HmiV/25/2EunRpd/hfoLMQgx6DyV/0n5e4ulwFcpkv1/1yFfp5dy93QRd0FfSFdUooz/1iFfjdh0op7hel97CFcP5cgFd8FeUReUFf/oDcFc9/20uml5fT/0PYM0x60gIf5cgFd27BAZf75c3LPL3v8Fer/0QFfxEDegiWwqL/3yl5EwHm/3Thcql69EjxkvPhc7I6BFcV90P7Ai96LzYZktJHwNmffidwkvmFfEbOoCqMkv2Fc5Lw3Qm1hdc5dgFc4Rehl4TyYV9gaFfdKleun0FcqFct/1PJAFFcYFequmorIGkv3hfro0ZFc8Fcvm7l2KpFdvhd1l4uFfD/2Y2yjmexFfp/0v/0+FedpeFhecFchFfrzQKFdRd4/nsW4khpOwl0cdygXNyVMTvSCl2kufrF0dnMjFcwAndnPol3yLLI20jFc0RoPtNp8HmIrY22gl2LFfvtNyePnsxTnPBeNcdnpUiaNPq1C7AaIufwhkzdbLnN2MF3lu1pNv8HMfoNpNnFf7cOTFd6eMZqVtpOvuPPFddpNPhsPFfWjBhNOrja3FfUudSB1XFdpud2mEE8SXWPjl2KyNOePTl1BcRvnOsZNfjYnFc8R30eO6yM/nN6PuQlesdP7Fdgleml2fNHq1BEZoVdMuVOE9NruP0qXQXNOLX1qVwXN2dklO2Al0oOYu2Nel3F1PoXMjFe3Y6KdOj8Fs2K4XMXNHq8MEXMRl2Xxkz2I+ufnl125ZwXNslfpdNkNNeim0XOqGFBvqbnO1MEjlg2NPhMG1Cp2dNUB0rkUqeOwl1Rik8XPOME8mT8XNC27ax1dl1PFflxaiXPPVOBzgSXPYB4qlci2OhdM3VPhdOT2KddlhZpDl2jpO41PM9Nyl3TpaMZPTl2MIFBePQld7VO8ldvWMOlfcZNrJG2ld8ZP7FdWldIeM4ePcEYiZMAB2B7q2XMKlfElidufU8ejXuYh1deldNNklHhletNNeXONCfqB5Rlffl3cCFM24R2NBXOzudJ+CPemxXP/6CXenleOxlfEx4pWi4O0EGC3en/B3zQO2uCFle7jNCvnLdNHufCJlz5Onucq8e+QkXufq8edkfG8ewmFCvk+ZPFPsnLulPtnLvlPtXueZkcvud7+X+BpTUHMV1guQlO0MV2uWQ022DldMOTQ23JZMXF2AdMmV1DldXZMRedZTslO3AtMm1OHFf++NXocvdOXeP65wDleblfJcHQ5MN1MHSw820jlcr2AaEm3ecTF3HlcHCEGV0l0nA+P7lcvMQXldUedcdlRdMjlf79xYXOP2NZxmodPOV0LoIYxGDlcHxbfJGzldKzBu22Tx1tDPGdnM9N/lf/x5B+PtZN7jbYbhJtPt2OQVcK5G4ec4PbjCZPCHMV2IVf65EmV1edW0NEoecppkgiGPNPRZNeYcgVfh1OPVAy9Nied1plk5GKtNC25/Ngi222+PLjb89MwVfjlZjleXeOwYanePxtO924giH/ePRtOdHWvZGqtMcVcDZMAJtPNZT0KS9PPHW5maDx1hF1AdbygOYVdJbpMVcm+NsTaORgG+OCwO5MUL1HZed7VzyVd+ogatNTx1HVOsVcKx2LkaI1Ps23z2MRedQ1O7TgfZM++Py24hEgy5COeeKMHvlcI5Py24vrCs+PNefy25sgD8thtecdot2VfAxEU+NdeeKMFk5ErZPmVci22U+NEfpftPwVdg1MbaJOsFoVf73wqVfhtMzYcaVfiVf+HrdnMGV32LpRdPIVdmk7bUHBVfVCzGV2A+fKlcVRk2Vc1tM3VMXtOOVdFrtQ+kGrUvMth3N0I7V+MQ3MLMAGssXit3cy/MuA3PUlDUsve/vUlA5+OI3N1VcsWcnH3VVfsWeyn3PmVcWclcmlVfkWfJX1FVckWc9VchjDCWdh61ejZRPAYCuniv9zY4svXisVkryWcXitTVdECtTn3TINqsuyX1ejYr1QIyul63DMA1Vc9VcJsSJWfG3P6Jkl8sxcu+bmJWddX31BkmWctvlOjaVstw3Ob2l8ssHH2XVeCssrzFnVdiCttVcIHjOWfOckHVduWcPH2UpOysvvVf5wDkWc7VfY+TwOdePMjY6LVfBPOA1east23MjY4PcvS3NzY5lVdVVdJVXGsunivmoVsCuE31k+4tWdh3NLWE1VddX1AwtZWfw1fC5ZOsupXFI+4IivUn153XFWfBXFE1dlWfNVe+Th82fVcmqjY1WdV62Y1f1WcPH1o1caWcM1dnVAo1eq/usjaxsuWPMzRba8s+yt/ZGfGhJ2elDY+xat2fU0fDLEdKukUG6vu5WctvmzDbnVfe/tU5OVCvBXGy1dlsvwgdS1eYitVX3i1cH+NqAdd65bWcJDaevC7WcBPNywuuctePP7JPHWclcnz+kMcu9svVKX9stcctG1fd2cZn361djsuR+k61dPWe0+n4zKohPk3MK1cLsuS8TtONVnLbCu0+kvnp/Wfvn2y7Vbsti1dyJgg2eum2WDb5BPf3N1EXXCu6X3HEEAOeYYvM9gI2du1dL2XmhOR+lF7xCcuwPN2M5Y2fQ6E2lVchOG1fHPYE2cHH2Z1fE2fzck/05WhOsX0CYu5CsY1dOWpEitV1fHUausupXHn069hOxPMpG7S1d23Mt1eYisKzGN1dbBPWaGx1ezBN51fauOHPPOckV1cEcsm1fbTAUislaFF1dS2c91f51ey2clBMVEEhBNm3O2xXK2dD1fJZRchPJX3KDY/BNkKtBxXfxXshNW1er1cghO21fTaV/WeR+kjaVm2du1d7BCW2di1eCJQ22fjst4gmKiuH1c41c2PMJ+nIJTqivZ1eVywe2cM1fX1fe2cr1efWw12cWxUL1dZX1L1dmis91f71dqKsnH0b1f2iuFPMQNc2ctt1egNe52cl1dH1f9WeS1en1etAe0+kX1cectoNdWTC+isN1fv1cFWfN0ebpQF2fdclRQ69hNQNe4NdhcvgNdf1eV2fo+noNezAdoRZ7csY1fqqypivgmNXpAg1rNPO0+lVoDI2cMNfchTd2dGck0J55cvc+ksDaVctliuvqGPyXX2cZ1ckdBMNdmPPkRYz2e0+nOJVO1di1ed+xL2cB+lcJVtcu21fC/Yb2cdzEmRbI317POx+kHBOL1fqkTDcu13NaNejWdKDYVVd0ZFGNdmNfQgcK+kQhJ32eWh6P1fXsvh/i9hNI1cgUfMcsY1cuNcNisB1fcvD0Ne0+leNeu1cY1f3oDAOe0+kBNcncuP3MOTgv2cK+mEDhycuE312XQQ1dIvONVjjhNjJOEioFVcYcvVpjfcvqhNssftpJG31dX1VFF4Oe/H2O1dCgdEn1uwskOeRmMV5dr65zsoSOdYkFyyy0Odej5GJbMOeEkE2BOYqtrh5EdEVNcMMDlNfIqt4kHNNd8OeGgcGM51NdNNco+DkStWgewM4E8tUOcQpN+2uXZEQuDwRNavMqPv7OdTNcJxgvpGGvM6lWGOeIQfn074RMsqsi8t54GBXG2vOLNckQeuW3bNe2OdyDbd0IPmO0RPOyVL8sOvPQNdJgcnYMoNcOOcr32zUHOOeZgfuJ4mSvuOcMxWeOdvmO0xU2SurgewLWyRMSpPPNfJ8u28sdUnw/PhOfpW1S+kTSvUQe0w7FVc9gfnNcdgcLEt3+pgZHn8tws4WRP7vMq+mh8uVSva+kR8vOvNLx5EsuItdfcHFOemROd64fLzp8v4P0sNdG8syP1BgsALW9Ss58tx0H5StTNf4te/NcDgd0NfE+lwtdOLxz+OItetSYjOf6SvKM11XHotchBZ18v3NeWkR98twtcKba9SvlOdKyVd8skteeh7v6ojSsUteH+YgStbNeCtcO8uURPXMOJ0GbZ3XGvcK7JFi0WuVtY4TUB/BNWsw64sjDlz0QK4Y6Ypdsa0HRiBnUeJdtGte9IZ5WtMxOfjgnT15Fw6tc86dcduatcUT2eduqte4J2IttKtdEDbptuseD2WbqtcRw4meHvcNo9sv2MPp3kL0BteI6ehdvYUk21Jxtt4ONatdMmu2H607jRtckeHc8MC6eete+DYMz21a5sslfj0YL1jrZliwHT14dY4eBeNy8ttvfHJrFCxJ9muFtdIGdGT25tdqHTgmuZtcaWYRtdOMyc6fS6cUWVA9p2tfKGcBrFRtccz28rHzEyVtfVuwXGfvadI45dtfIsfZdnttcy6cQGchrGttcCmsNw66tdBte1tfptfA9vtiCatR6td2h066fPGu3N5Ztfatewg5rGc5temIBgSLkdvlrEaoqjLU/KE7tdx6cM6cn9Nbtf4Wuot5FteGWvLtfVtfRtcLtee6e/iWztc+6dkts7QsOrgB6e96dgJOd6ZvGs/T3uZEQriXtshT1ajZo+LetcP15a/BAL0btZvY7V3zFttLKFvY55teGtdJ6Tp6emtcwdfZ6ckCWQdcVtcF6egdfntd0duDE1AdcWteg47WZCLmshKEjY7JFhTtsjY4nAiUmtCGkXPsgaYLtv+CVkdd76eOdvEQvnPw96c6z34dfF46VGekk1HLQj6cgddLJyhGdLtfwdevWsZCUhZXZz3PGt8dcd6fA9s/DYrtdgL2sjb/tcptciddXtc+WuCdfXT0nIXYD4ntdbdsRiD6ZqgmfUrW1Mjsz0Gdvz+kEdeHdsD+nFThZNXPKEzRabCg1fHsqGGddX4Z9mszRZ6dcpdvz+nEdeST1xYESddidfYiqAGcYL0Kdf7Gd4dYnDZgddWde2aDQGfZdknDZQddftvP+m9b5IGdaIUudfDMcmdeOdcDGdCGl2deHlKGWvWddiuTiz0WdfkdfV6cZdamddHz0l6f2bbizJMdfgmugkWJdccz2drVmddMmt767zvAWWvBYmFdcD/yHms67Vj8RHz06z3Zdd76fWz3YNAD6dKdfhg5NGcbtbRs27teD6fvM2KdevtcbbUEAgyGdGYmq65odeudvM7WZLqcdfKGetdeHtdcduM6776TxdcZdcNddats1ddCdeC2t5ddHz2RduldemGck9sAkVFdfmddURw2GeVfHzdfgdf5EUIGz5z3OddNdf1WuVtZjddPdshT0ddecdeaT39dcNz2Jdu3dfF6dmCVXdc1dtGT3ndcpfHBdcndeSdevtn7Gctddwu6JGc42utlXRdfkL2A9cadcCdcZ/70df98RgRbrBj5ddMGe47UAAaJGet6fobZFUrzCW6dv5Q7/VrMdcOBlGddmdt0+lE7XY9cpaivji7dv+fGzUEojA6dcOZCYdfldcTUGzjBe8O9GeU9cXZ3xddv5Q00JNWtk9dtdcA9cf+qVLUCdds9czGdndc4qxA9dp6cgLXIL4Nz2HT3u+lodcA9fvTzoL0Cddi9caWvAL0pJYntfOdezDKdddC9d9te51UtddK9es2u6CUi9cCddrtd3Gc3taAvgdtcF6cSgxk9xPGe82sc/TKtdI6cQVMWiRJde/FNgNF09sCdcofTutfOdd29cs9soSW+PQrIWQmelNcT051JOjRBMmcG0FuOSUmcOkGf7N+9fTRaLPWB9ellNn/C4mcWL1oO0WqyMmeImfuhfhiBh9e0md4mdpiDB9eaL0x9dD5e4yDx9ek5GJ9fjZAkeDh9dzZvhsftlPcYjBL3b9uxY7RpaBmeURZgbl8mfkDsj+nskhFiPSDtE65zCSO9sYgjV9eYMDi2FQr3OJO0UJl9d+LU20772t+pOSBqt9dV9erddqmehL2D9eamcXL31dd+mdrmcXa26td0DuTdcCjaR3sgLVB6bmmecDv5EWe+BimcZmesRar9eTL2oOtZEVeNzj2t83RZEXh6aXiPLL2GRaozjViM/2vJRa4J2+9sj9dl9f07V0dc4OvUDsmDZqtc99eURa0slRme8Fwv9da3ZxmcWQAYwtMZ0Ar0WmcyBnW9dgSNv9vJBlptdgSOjERw9cBxsNsdMYhw9e0Io7mdH9tMM72Wbf2tj9dl+j2Xqd9dblUPp3Fmc7M5z9daDt2M4W9dqDtw9fvxK0SM7Odas5YDeor3CmeE7XBJhCOuRW3VDaoDdUr1EOsIDcrcywWfUr30PurgTT9vwBmQDe19dYWdBQsqnpSOs8r3DrHJtcB9tWO3fCLhmdLme1UlXtcz9fI9fjiPxmeURa2eoYDeevBFwo55PYDcjmfhbYHWBKDcAP36s6iZCUDdYr1USNXQ7T9eWDsTUHwazNGGYDfCDcT9dB2v8DfXFFX9fR1qGPnwDdzQl/9crwYu4nRG5IDYIOvYr2NUFZbhKDv8UDpBmoFZMDf0Df+DY3mfyDdsDv51BRte7mcf9ch8xwDfRmfmDf3FFR2v4WdrcNwD3o40gKASrPq51FuqgXuDB2F3qwrNxDc0VswXu6jNbnE7V3o41wBBIXuejOKCCoXvpDcTvQYXu610DgD+GT4rOarP5NlErNlwvVlYBiSVwvB50bZkkXu5DdrFpfV1bHnAmYgIeNDe5aBS11ul4sVbXaO15tVsX9DdCaPVlbl1IIIfEFsjDcRrNCrN7lZaD3oId0VaOliHqMFjOSSMyrOApFVsAarMsFuUVb1DfEIf5111DdKrNU12UVYVDdoD1K13VlYAHq111nCFjQAJDftDdLaNMIfq50rlYmrOUCdTlYeXtTRu2ZXWrMHHnFVsb53bDdQnqOrNbHle2UurOb52ZbrIaNVDem05erMP5uuKfgyHYaNbHlgjcGXuj8Ga04gaMG103roRrPFD0S068aPe53wjfxrPQjcgCO1D0vV3+rpRXtbHn7CixXu4jcU1tmIePpxOLqdD29DfqLrIjc4Fue07Ebz2IegB0kjeiaOBQOFRkzDdTDd4jdx12zDee04nDdu41wjcwKitrMljOB1vMFvMjOVbEgaMfDcYjd4aNqrNBGEGaN8FvG17cjdjrN7JFmrrarMEjedS6pIcHHnJ1tSFtdudZIcVVazoWlIcahmajfTXsrueChlroUTXtqtG99MBaNVIdVCf2Ql2hmhaMXGAD10RaPbue2tHWjeGFtGA4D10dIdubvdGBOjenXtl5D6bPOFvZCfuhkWjeBIu1ld/blq8fRfvrxtZJAxsWvXt95SzIftlfzIdlPuG8eNlfPudTCcCvaHHlR3tv12Jjex3v9ot1Dfe1nJjegwqMhFQ3vpjeGN14bMpjdVwk5FstNm5oWB3uFF2nnOtaNcluOVZQ6MIbOGVAljcmbPFjdI9v5jduwuw6PUltQVY+oXkN3vCcDlYhoWdFvIVahjCYl73F1djcRoWPFsAnlztluj0AnnGbNSbM3NlobO8N2EVYkpGlGEnIul92F3kZjc1jcKkohj1H7KPaPRVb3qP9ItDyuFwA0tkW531of6N2m067qPnF0wjcA3uHjduF0VuEDjdb5pibPlovM06q52dodx91HjcCN2Z3u5WNWSojet2YsqSoapIcusuEstQ2U+uBYvq7YZfghYuDu5KTj1OvMes+AmUWY+OtXBHg/N/EuQTdiYsmAk0bwhOtzOsuAtjYy5Dva4shu7ZI6FDtF4sDLH/ViI+fu4sDLHLrJKtkHHFLsuIiBwYt0Eso7YZOupusBAte9EFOs/jcjOC1+ujesxxZFxDNevoesjXXxCqYTd4TdTOLEuvIesjLGhHljP1l4vkTe1Dv24sY1m8TdFpz/jebiogusfje8phyutCeuw8cGTiiesu/ObBtwevkeuyTfDutITfvsujHo14v/otcR2rOtXuutzKN+vcTfMXH20yaYv8TcNOCHOtqTda2L1evqusFfNLGCWTdXOuJxamTe3OvnCaGTc0+u9uv4Bv6TdiTciTc9OuQhu8qRCt0fjcjgGAutkTdY5oSTeBTcknk8Euz4v/Bs9uuDuvZ2VhetQTf6u6aZp4jvKTdu8tgevReuo6vYussTcm8sESwnDscTfSjJcTcEuuJxYpxEsjtoTeQhvUTcT4u0utEDLuTeKzg8Vtp9L+utATeD8tQPxtuvsQZhev/jfJJT8uvhTccnm8YsNus5ANSusjusVXEaTcTYseAtc2vSTfUetzYs9GCdevy4sNXH/3v74saut3BCuusMTcVXE4Td6usThkFzwnjtoTd21k1TenYvmusdDLrTdWuvb/O3OAGetp4t8XGKjp24vgEtpXFausAeuQdLJTfnTddTcnDtJ4ulAtwnn1us/jdJCCEeuaEujNLdTf/jc4J71TfG4t3Td9TdXTdPTcCjtJuuevFIeu/uvBuFUHRXTeX/oHjsnTeLBkpoL+et8XFB/kfus2Bgyu4PePXjuVuvGtImet2TcBXXbTdRTcE2QGesfjfgzdaes/jeJWFLuv/jcxWGRTfhTevRCtTdOTekwmqTf0etse6mNxLjuUawBe7kzdKTc2RmAzcSTsozeEzda4v8Td4zdwLlaTfYzcrTfszf3Tc7us8RlIzecTsAzeJf4/utCTerhn38xO4taTf3xHXjvZTcyMxUeulutjxaKzd0eurQaVxbIjNozevutSzfbTctOYIRl5KDHutXTfUjz/uv5evx+oxTefutoXGCzkSTtlTffWFjTfqzeae5MgFrjuU4sEVKXTcGTd0UFAevFYsjXXGzekTuSzenwXQzfG4s6zeEeulOtSzcvutnOurhlGTc2Tmb4tgxodrRmYsKTdyzd94udTd3P1sevhTfizecetkTfezc8etxHFmzeJespzccfqkzeUze2zdpTc0zeJxaOzeiYuDesFxZWzfqf2JTfuzfmzfBze+TFeetHOsmkURWgwus/jdiV5qeu8EsCupZesLeuDxZdzfAze0o4rTedNzHu7so7XjsIzdjxZtzcWetFBBWeuSRmjMLqEqk4s6+oOeu5uuO60i1TletZzdj3vuevAzeT3s+zeQzc6cRLusHTeDu7L3uGjtXYvU5AezfheuGAs7zeczccRkHiapTv/jcHzf8eu5OtcKAzzfdzcPzcpev5eteXq9zeTWZ3Fb9thFzcuEs88CFev3zdWtglet0EsQsVazchustXNVetALfyDcSTs/zeJ5I9DuBYsBVbMTf3zfKZqtTfQLehTcK2kKHGvbqG9wSetzYsGG0/Tlj8nfg0qtlLetzTdA3MS+sMTdEXOf0iCyFwLdnevzeuULdEpAzTs/zduEGreucEv6fsgfrQbJA+t+tAsLfneuY9wYNux9d3aAgAlREvQNtFaD2Ev8LdPetP70aNKsLe3evsLd8LdXuAJEt2hdne7qLl/esoNsOBucLffet0n4xhnIzniODsLc1VtbevcLfNd4GydnnUSBAQ+tgktq8u6sY+/GQ+srNKt+sqkvphlP3zD/0Y+tje7JTLo+t9EvphkXKh5+vekv+hpe+tU+tmBte+uM+tje7OLfu+utEvRzcp+tGLcOzct0xWztfzcKgsGzcM+thLdq8t/hzLzv54jBLeItpG/1z9gqzcE6xiztrSrFNt0UEC+sy5dC+sZLci+tZsN0ktk/oS+uNY5d5CrhkJLfC/3eoQthkuMpOP2p+t+zeq+tBLfhzcuTdAksmkUlTe6+tcshvkW5dqG+uNLdw8A+Tfb5dNigVze8TdSktEIrvXM1Oe5LdJOwO+vPGCd+t593N+uePrVOsEkvt+ss5DdOv9TmtLeaxZj+tZv3pLfjxYR+ti/1GkvzLc6TfsnW6ktayczLes+uxkX75zkzsKku4QAWLenLdYP2xLc++snZDUus6kuB+v2YOV/E5/1G+SsRmV+uh+uMRnqi4GkvI+rvLca6jazvEvgH8uYHHrtlZLfdW3iMATLdN+t3Ev7LehLfD+uHZ2E5ALLeGfnJOjLLcbLcJks98tX331zsxksqxawrdC5fskvTLeBLf5+vjLfuLdmLcArfZ+t1LfTzeATcfIrukuQxa3LfhksvLePLfl+sPLcJzvhiQ98uoP2A0mugLwrckrfLzu2LekjAWLf9+sh+MVq3Wzli3AdjNZCURu2RRme17z7BY+3Crdq15Fuz9e0sRa72d97KKr0MxkO5kE7vJu2f/Z/+lW615Y0rcySmmyrfou14cWqW0W7sL71KxkvXqireWr2NOACreZdpbb3Grc015CCWte0Qsq4hmGs5W5NdmhujMrCUSZn2rfzgkotiftafQO3RmurfMZkWiIm06AxYH616rcAtmxoM9tbVY3mreGMCarfBrfZ06jI7t5z+rcVjOOreTO1187HDduMo/e3irfilY4G3vWCpjP9wP2p0W/SUVYr5pUb2SxkylYCG1qrcO16xqArG15Xl4cUprct63Rre6tlUHpRrfVxTZ04ToPu63hrfQKdipje62VrdvHl43CBJ2zRkjDdM1jOp1lzWUVbiCVRJ15rc/Nb4UsuMRzDfXINbr38rctNmSrdJre3RnVrdHr3OrdNsW3yR8bkTrdDeHF63urcFRkVwO/kvOrcjNk5rcWlPGVZ8zLXFNZrecVaRYLSu15rdhwPNJ2V0qPglNKIQG2lrdNRmh0AFrcZRoAtkbrfo70hrcctSrre1rfQKfurof62VrcLrdUUTr5OYxmwnm/5RMUuYxmzje+1BWG1prcitlwSpCre3RkM/EIG1rrdNRkvoMKlPSrc/Eclrf99BinkDqy/kulowq06JCXQbkrzi7lYl5Ed62QiuyxknyeE/jFRlI6rsnmzNKwbdW0oO16uEIBVvdb3pRk9CX/J2drdl3ndt5tr06zWwnniCVie2vwiTlZ3wNoxeBqCjPbMbckHtXb1zCQQbdJhjMp3hQ4QbcYyjuZnJrfz6AoG1eDnQbfYbdgjmhoo0tkcbfTrcFRlvdxgbft9C1Rnc07obdKu3Jrethod7s3rfzgkvpCpreabdqbegbe8FNkbd1Rn7re3u3JrfrgUlG1ybeVRk7vDsG0PLOoxk+QUelxCbfaxmc0T77sjM3505ys4dG2Gbee05zCUpe15rdebdgbeobd0VZ0s4DG3gbfHglnfBQbeObe47Dd0tbrcoFDwm5alNHlbqCUWJeixnDa4Ebf7K00xlZbcAxdkbcHRk7rcLFPpRmpCXXrd7BBlrfqs4nG2trcxbcGbcPre+06RbfAp3lbdNRmhbcI0vZRmBbd43DBDmWbe3glZCWMbcVbfmbe5RdsbeQFBBbdGrfZ07wRoim0+beTRljbelxcaST8behCXxp34KXaxmmIMabcBpCoxlMN7ubembdNRk+r5O4EObebbcUbfsJdswIGxnkTzXrcLbctjPVIO30t8bePlZnbdie2MIQNlZHbdzRchreR4qUbfvaQAtlbbe9be7bc9bdxrcnRn9bfFbddlb/bECm2FrePglTbcuznkxkHRkuCUnrfLlZzbdK72ZbffbcfSxHlZrbdHFPJrevbeqbe7bfOBjNJ3Lrd3bdQ7eHbflIO5rfLlZXbeonEg7eyKcpbeP5G9rfrRnHrc/bcm05I7dardPRkXPiybdItzdRmLrf9e0XRlJ5CQbfI7e8xks7euDlfRm/rd4Z2TzWjRnDbdSe3507niSW1upHnuxaQxkOCXA8H/rcoQmhjydpnibc1KcdbftqHJrdUiW0bcbbeIxmAxpibf9Rkx+PLDSdpkS7f86M4m2Pe14xkx+Nk7dZxeB05vqbd0vIFS8xmOoPclMK7d7bfRu1M7cOFd/Jxwbcq7eAbfy7dtRkqkm1bcygQRn7WBmD607behqnY7dru0XRmzKf/bd07c9iFWZD/bfK7eRqnWbes7ef+NE7cc7c1P3m25+rdB7ePRv9rfO7cBv2yXYkbeR7fg6lp7cx7cYSGy9QX62Ebeh74gcHXZx57fbf1n4CWrdp5NG54eLk7CV0bfqhelpF7G6MSzircl7eOUkO7crqml7fe7eFpGFCURlPOrcHTtixlWxn9gzQGvd7d8FAecRL5c8LfxVbvkUD7cjKRQ/1SGEexmD7fpJe1VCZuA97d1zYT7ej7edZ3N5CyLdX5Bz7cD7f9VB97dkChj7cr7daJ4mSlT7eb7cT7fr7fL7fyNCJhebxvDLq9Rmh/UC/0sSlantPs2RUOe05KaTYH2/PSsGv1LqxiXdOn1SiFbegiVBWD1qoYnmPCc4xlX7eSh2v7fr5x37fX7fbd7AHdf8SAHd/7dZ+3P7cqN3++ctrcAHd6VZTbdt0EQHd6Vbw7e50EoHejRlrYhY8HFqDRsWvbf7Z2sFK3beOxBWNU9l4o3i6tnfSyrrd9/4TMPrRlhrdMKllqVLzoWCU1WNEd47RkqxkwrNd1SYHdTrcSmyU6yjRmCrcqMs5uiIHdjrfmH1IBiwHe99nEHcIHejRnt7e8HeRUOEVY9IhMCUgHeAHcyHc7JcwHeoHfVcW+MsEHejRmuYgeMsoDLANwAQm17fu6C0G3x05JkUHO0YHdSxmmrczU3X7fcdyprc4Hdr0WjT26rd+m3FGsoQndt5K8GWbXTsDqxksHeJSAZySuHf9nvY7uS7hFKdjdxurdSY0t/0oQkcHcvGfI2hyxllPVOHeAeasxkSWSyHdiHcZ5C2rcv+1CHd6VYCtxUCWC6BcHcZ5BEW7d0FdtdVV3X5CJrf9mwazhzRsf3CpRno/b0oByxn7rdDH2InBF/0gQm5Hc9l7sahRHcZHfIHfx4b2HcdTFnfDopc8aRJHexreTWx8Hc9uNs2JWce0xs9Hd9ccAB3Z7t5vugDODxl6uOBAN1lYW9M7RvLjaoAOUxtKIaqQdp8FzHf+cd9Hf5B1BcfhMFC5h6Qdr9PLYeduNSxtqMGKaIeGHWxuhftxcdaMGpNRUft9HeXllcAMHHcQuAOQfCgkV8OzvuiAO3He6OPG9P64eeQd9pPoB7FcdextPtZrvvaoVcJ5BQdzTuf7vIDM2lcnOERQc6XO7Hchxs8xtuc5xQeuldAnfgkdMlf/HcMxsYldFc7iQfoB47QdnHewWojceUCdQB75QdaME8JtTce1MEwHvT9Pgnc0HuLcfYnfjqJL9OrRvA+qr9NMldfTqSxt+9MRN39OOzHdsSjjcck7mMndH9Pjl3lTzFccaxvsnfDvu1MHiR4jQcLHfp0a7cfwhmEcDGxuxAO04pjON9HchiYfcdC27iFbLQc3HdXHv/cf3HfyncqkeQl2bDw7QfuxuCN4Q8dSB1indrAMw8dBt5hxTw8c7xlzpAXQc2ldzHtXOM3Qdet53Qf0eNtA1XAPxxv1wDXQebHchP6E8d7JEnu3pxtaMG8EK0DMSndNIH+kdqjc08eYh27bmgwdklH+ndM8cBPvQGCwJlFxtklEI9ac8eJzOa8dJk48JkoweWFDggM5kfZCe+uCJnctxtm7MqGCpneWNHJndEJmZnflkdyFDkJlBfvejfTjCdxy9Hk1keRft5XMuQAFXNUh3UgNy1BqnvgMMJft68eVXOMj0/Xv59cf+0x7o+smFgO13wE/u5gMhLpasmdnetWJ+8fyuPDFy9ncxeG1gNdncdnfBDMa27ylZVcPhDP64eFwcvxvqHwW8mdnfTnfZDM4JtSlZGwflfs5inJbk9nd4DbnxnwJsC4dUnh9DMsJud3UeSP0UcHndHxn7nfCcVF8k7neBceVuN58c7t6lwcRuN7ikg8hoQkuNfNt4LiwxeGdnd/yaDDOoJv1t7uGGFUd3Fh2t7fnf3FFLj55UcLMF8rsTkdqt7AXe4UezndSPFLnemUft4eoru5UcMyaIXc0xHl8dG92NCMislfndMGEaGEQJtRLyfxtrnc+SXYeFjneGsmtuMD8fTMFZbm3ftgB2H1Grwe5WMqa5jh3yHP0XeVrt80d+tNl84rHOqwu+Jm8HMcXfNrtMHOzDYKlnrgsIYt0gkb+tjyHRs09rsw5HBrDngu8Xf567CHPDrv6lV3gtHxFlyWitEDHMm4EcQuFJlkBpwjNkHMU+lBhva1EdG6hhucbtlG7rrti5EGXdSjPsXfuyX4jNCbtaXfEjO1rOaDephtCsnjG7nrsW5Hn05e6h3aXOHNtyXICdbD2KXeEQM3HOeXeg7MvrtuXekQvLUngiL4CfdoMW2jMXeHQ5OB1sHPGXdABt0Btk9eyQsw5G8DwP8cNUmu3y9hvaaMsDasXdP+vF0Rsgl1HO/ntCXdALv/UmAtNX8d1Yv6qwaBuRXf2rG4btKDZlXcEbvXBGYwTKQttHM1XdqQsw5FDzoejMiXcrmzmjNqHO5lP0bsw5HxGBGQuRXfprGsbsCcftB36Xex8To7NMXvDXdY7OsXtIpMvhvgBtUfiuQuHrvlfjlNFuBuh4z/huOXeIt5ybsL0fAwPs7NKbscyWQRtI0mtXf7B1+XcbXexbMlHO6CW6btYxFLXfxBuFJl/DDQbuaXdjXc9HMjXv2PtEnOjQMDLsLJkzQO2bvZndsu5PXfpCd/KB49pFCfvXdiWDwr5tQt4MDvJk7jOS8ck873JmA3dfJnNZTBbt/XfOWDg3fxknV5HXJktCcrueqJH/JnXjNBIvlnchIsTCcNkeXpCwLXpbsjCfyRtRjedlcxjfdlddke9lctyngFKXbsCj265M6wOinOtUnaknPbtU7XrNFHQu5D56km/bud64U3cEwOnBtDD7rh0chsQwP64HEkk3Bsb1dgTPIhst1dYwtU3dPJo3bvi3cPIvDbtlbvNQ7I8LanPdF0s+ny3dfCe1EGcojbCcEhty3dM36AifOuPgw54if3dOgLWMwt+nMUMfOXfpRvxh1TymSfRBRsWj3rUTJfT2nPBM1VtNs3ffUkW3fa3dbPWl3NxMG03dwv5Cht1uNOYR3B3pnNhDsWwsi3eboQSwsa3cgaQiwtEicp+m+TOg7sVh5uUZ+wueGrj8cablM04vKIgMv2pl/IvWDkNqChjuPzpbr1p3f5KvTTxMUvJ3eHrRyu1VwWZOoDkuWBly/aY/uYJ1nLIHulZPwjkufwW8DupZmvwUFSCFTyAe2nquYSnIAUMcrvjuY0AmnGcLwit2lDRbksxeq4pl3rfy5OnOoBv14JiExI9Uscpm8jL8J2Efwf3burrEUtd3fgRsZ3dN3ePwXpJjs5PN3cHCXIUtz3fQenyWKHqHtatwWAa+mfkscplRgM0p32pk8TJOFNAmSN4nnSI/p3QIVoBhPJ2Aau+5s35OvFpEel/Gy/ksb3f5jt25PzyfDpZLeg4qqPktL3d0Ogk5Mv3eQugeYgq0ve6FIiLkUsV3fn3epnNGJdX3egsrUUuF3e/3ffpmvIAe51f3fWSwH3daKjIUtZ3c7KuTJh8bkIPerFFVpnMJ0cplJou/ktZ3erKuGJqkp32plqWmPUsEIUpWg7/BFe07P1UPdyUu33fkPeNe013d1zzup313cEPcNu3N3dPmlDJ2cPdoatjJ2qauuSkXO309DuTu8mLxDlCPcB1MVnOtUv2plebcx0scpl9QXD0uyPcwFUr0v2plHQWn3eF3fse5O5NX3fqPe/kvF/TATYqPfBUsK6tvZzlJ2JGw8TZyPfbxe33fTa6VUtLDwCvEZNxALi/0vAPcK0TnUv/3cSPe5ReJavwTCZUs46uz5sw0u/u1Ev02PcyFPtNg950WPcUJeG+0vKsqEaN71EPel4nZfLMp21vGqhXuySkp0KPcfOxoxfoPeYpmRPd4PcspmmIP9Us73eH+ENUvhPdFcxrp3GPcB1MM+O1Uscpk5NyzUs5PeW1BCp1zhSKpm8CWrUtiPegF2xPe28Ex6v1EcHUsP3egF0eYgpe1X3fniRLJ2F3dY+PnUvYPexiQBFPBPeiplxhjd0s5PeFPfep19Pdg5CuUuF3etCA35NwEYyqX2PLBUtFwWB1NPJ036sCYfjp0tPf4YemFN5XndvH9Pf9Uv13c9PeNbeRohsdkQPfFRmrPeuAQHUv5PcMpkH4wpp0bPcqqUzFP13c6upEZ1t3fqqUZ3fUbmNPcFa7LFOTCz5VOAKBqlO1PfaqX1Pe9u2Kpk2pKrUs5PcgAlibcsplSFcc0tVMwmvH9PA4p1/PdXRLWp1fPecqWKPdie2NPe27h2Z3PPeNxlw0TNJ3/3dgvddDnAPfAvc3Pc13emFdjUurPePPco0tgPcuVOFTwuzkGPcfPfrFMsPIyqUdmIo0tn3c6TYAvehizpVPLuopp2gvdsmpj3cQvdKWnD0v2pnovfiUuF3fJ5KX3e0PeivcWJ0mAyEPZCvfAZ233eQvfnrerPd4vcLDkcfFoFu70scpl/+lZ0t93ff8ETyYyPd8vc/4bx0vcvcODiFUsWHzRpk/Pco0tL5TJTYavcR0topTJpl5YeilN/PeVO44lPQvcAPUUmZU0uEpnNYeVUtD3fiMGX4is0tmwWhYfUlMOve0Bjt0s46uTHVDFP05DF25aa7+p0bPeFYcfe3eizuvdBvdKZ1JPe/rqFRfhPfJveilOpvfm26z0u7oO41MkPdgjnL6G0LomZ1upm5gEo0upvfFvfc8FupmKBhqvf5veVvdFPfVvcQPdqZ3uvcweha5Nevck7ksPcr0vuvdtveGZ1upkIZTBZ0K6uF4fhZ0X6tZN0mnFT3dIB0LPfQbkjvdlN2oPfJZ2DPc9MG9dCpPf9pmBPcRlOpvd60NhJeDPcHTuZplFZ3IGtxjAIDnVZ2oMMMH4bve7vcxheuuD5tuHvdD7dp9dSGCJf7wMtbvdKB47vedZ17vdP72YpmbpnM3FHvcz/ZRYgPED3vdImcz/ZkezFwB3UhAquXvd3veT5fKnt6LcG1OUtpQ52s9gZF2F74QMGWrUQfdQhtP7f47gW1MqLng8EVQCzYPq1CSPzKH0q8B8GsULkUH3gff4TaIfc0H3K/YwfdUSo4FGSCSMGtYfcmMueYNZxmN3cqMuSGs//BUfeTWw0feEvfoHfUOAC/1kmbYHcztzIvcVIj08GAH6mTZbFBgpf1+gSzsudXl0Er2CGMPGpm4PcxmyLYOGYfiHwRHeXAi90WCqW050dlh3p6sff7Z3jnQ/FecvcJHcMfcL3fUfdy/1V1OelPQffIvf8ozLMs4ffWYcxQBCfcEffIvcmfdMffwffIvceUiqHdBjLepnu0ZM53GGv/jYa+lQ53dvUVJyqvfrMs4+yrVx/px25OZtp225Qooi50kfcC/1+dXoFFBffKh116L8FF+fe5pmj3evlP6sO5plZpmU7tbGs1YcJffbU0P/01YcxffY7txMPZ24B4pk51mffxfcGMvnGuDFfnOm45PZZkzs1zktiMa2DnbU0k5PUBgKI1HobgZns0w63HU5PSjTmZ5N0r05N1ZnpxwTO14J0mu3pxxNfcWgaOwPjkuwe5T9590ErO3ckp/9Hlfcs4Ids5ttraAVY7qLxyHiR2rfaZnxxxzfdOrdHpmLxy/0FKu0Lfeds57ksKJ1X5EQNmZ5OIwOCZmIbNx5MTfckZxNffHfeLfcPktDusDnGLfdrktAqnSmFkfRv3cVffHw0M+oYbelfc7I7QUsNizzMHQYXlJ3idlBs0U8hdJ1RZnXVXvfe3fcII3B5P7fcoI0eIxHr1nfcKIADfdQ/f1xfkAVY7r7w2LCTDrd9ffCrN7fejDCZZ6o/fkUs/feI/e55PNff+Vxw/csRevfd27CwJ0bff3ffIUs1ffGJkpEOcUsemhes1NfcU/dOs2g/ePfems3CUsI2Wms3e0ttMRlw3N0vS0pmQ2NgJDFPG8Iys38oAj5O+Znix4s/eDffNw2P0gOJ3Hfd8YWnfejfeMc6oSr6UszfeMc5rfclJ2Vp0pDADfeAFicNk8/j75PZZlpwNXUu0IDFZkXHp8lMG/d8QZUb06/cCRezPdVZnBrOM/fY/dW/cv5PlbCRHZbjQAxfOjRRjah0BPJ3Q2wlH6G/c4vetZnhrAgFPbfdFg0yQuTFPC/dEbnnUtAvIYs0dlDQp1YQSduXh/e8bdNxCinbB/fGvca/ce/dl0GGe2PNTpZlhzSevdM/esNmXJKCFPG/fPfcp/dEp2zvbWUvG/cnUZoxcU/dRrMS/ebrfFZkpRhsFOvSjl/d5/ftqHF/fY0sxRA1xFWw0kFPFZnUBoiFNXKzt/f217x0vFHLqZn/bsgvebqQlH6OFwUp2Zdn6H6uWAHUt9feXwNp0s2/d3oHaFOW/dknZePes/fdna6DpGFPd/fWcyJbfd/fZ/cpe1m/dyNA/p0L/f3i53J2z/eH/fOp3u/e/pmi/d8rwNxGC/deFPC/duWpbPdg/d2HZ1nZsFMI/faeUwFOv0FBZkj/fRp1hZnT/fq0vu/egZlKnYpp1T/cXE1rp2h/fdnZI/cjffkJ3Hklk0tj/dgA9E0sdu2x/dgA/4lOJ/fdnYl/djAWp/c3H4AA+Ge3FZn9RfklP0/f0n7N0vV9YmZnAUlTUtD/c3H5/fd6zmYXCC0vfkndFPIuKOg3b/e28Gy/cIrVKZ2gA/KlB47YNu3C/cgdyB/dBZn8Tpf/fNnEx9PNPfe/fgRrLFNaGxtnZkwjLFPH/fxOwo0sc/crnbY0sNffKlCYA8/e3YA8CfD5e1KA/A6zSu1m/fLxqWFML/fkqjffd1ZnKlDkA+P5HO/dkA/e0v8/deQ2I3IfFPf/d3kkGRcWgaQy3e0t4A93y5be2KA8cZk9/cRu3FZmuBqQlNKA+/0GeZ0YZkCw34lMwA9ng2OA/CZ050sSlC1CbA8GkA8hA+BA+Jb0oZmXRdqlP2A80K1BPdxA/KA/5/dEA+vdIN0vhA8mUkvp3AJpUA/vRdKZ2MrwYeWpA/d0tAA8rTyxvf8ZCQ8EZA9G/fXpknfrH0uJA+hA9d/dlA8ao6SlM4yrQoM0A/2A8gaXWp1l/fGYNp0utA+SA+3u0rfdA03/FPFZnyQI4p32A8jlDEUsjA/R/dab19A+E+6uUv5ZnTA/U+1TA+oKB0+0iA9S0cv0vGtxOODtOP18x0J3f/cdEWelMjywvpkuD6+lOZ/fEbUmnF4A+CJdZZ2nA/E3y5Z1M/f6fsGH55lPx8wFlPOlDICZzplYlCr7fIn4TvTPA+MMtnnYW+3e8EvA9MYNszOu+2/A+rrPvA+m+2Ag8iYNdwO+FFB/VzZ6UeofA+q+3D7fXHb/A/LzCgg/qNnXqAAg+sMt4MO3AvGW5vK2dlPbQquYMr7O5fc4g+inZ4g/TqFbVdJMtNelp+1gfGrMu4K6TlMUg+sMN+K7yMuC6AayxNnaV1HLlOMg/dnY4VPc52sg+0IP0g8kg/051WA+XMsEg9EIMJMs8g8g00m/cXlPN4SuYMEkM3lON2Aig9kmTMxlTcNy5FMK6BMt/5nlMsznuflOHXxeMuqg+/lOXeS5YMtgbOMtSNIJeUkkOgVP8IzE53KlABlOrJd0Rb6A/nlOrJecg98g9cfc6z68g8WDAD7bbU39+2vWEnMsNWO1GYvQ0AtR2g/KvAs51za51Ms4XxH31+g+3Muf/hGDDxQ1Cg/xwohuP1nuelMbf2xM2Og85MvtpLrZ3vrYvBxig82g8DkRcpkxg+2ZlsAxyg8Rg+2Zk+nGxqEhg9ZkucrFMVN4WGfH6UVPu6D3DufH6kVPug/LmS8ZnJg8kH0ug9tntOg/QDwag+aCP5zk0g+eg9NMsKS1cbORq63MuUTN7DDxQ0oVMxmwjWyiw1eg/7Z0afLLUetg9gpe6VBtQ35LBX+1TjyJg+V3KCDYMg9LZ0iy1s50MTMU51qJWE53jg9IQ15g8Y53XOqTW1Fg/OMtzKevH7wKxGg8EgxcbNpg8ypf3aWHZ1Jg/bMvNg85WNQ+cDWq8JjuZ6afC52FGYEVw2h62KOG+8xPZn0DmDtUn5IRAbNQ218Dr+VyqnYw2ssAw4SY6WB8w64DNZ4JKCY6VoRKIXB1tuw5kAQXi8aKQAqSqOCpa2HMOhbmioQ+NYiY6VpEjWjAIQ9/uW1sGSwJNZ5QoowQ9FaX1CDsYCA1rgQ9FaUAQ8rQ3CigTaX9ODvZm/g+/aXL+7+TQDV1qXiY6UwcC07hHwcF84lsEMQ/ZZ5PdZfGXvg8eQ3NzBU6VWRpyI2OXBPsHhAPRPEPNbL+XBZKvKLiQ9oQ+Y6XrcQeQ0lJjbQVtCx4pjCQ+kQ83KllCpKI26gKkmUJehwJinEYJGBKQ8NH7ZQ1hEovaXKQ+BzmT/KY6UkgRSI1i4dL6VSQ8xQ32Q9qQ/u2JnsBWQ918DE6Uq6S1w1/g/fg+MQ8Rm0gQV8Q8UI1D+LgGXaQ+GQ95bUaa3/g9PZnhQ9sIfWDFbmgWsvNGwmQ8aQ99w3YQ8lsGGgABZ4zWBAF6pQ8oU76Z4Xvjw6W1XhpQ10Q82Q+5bCwZ7pQhECnNNsgI0aSS685ZQ86Q+DUYgUCY6WBQ+CQ0TwSXgWWQ8BQR1Q8ODGmQ/6svXPCY6VpQ9fp56YgpQ+hQ8cQ3TairDHqQ8H/Ah9p/ZkAQXFQ+CQ1+YApLa+Q+bp7GkrIb3S7VcQ90m3CEGwCkxCRwo4zidn0XUQ9PZmgrzOeZ7aU0Q9YJIpJ57aXkQ9dg1kmr0CnkzZoG6yQ0RQ+Vik3hDaUX9Q8jQ9nG6/1IEQ8KiMCYb2g0SQ8uQ9rGQXg3UcY6b2bnzB3Q6SUJQ8lsHAMJUmpdQ+8Q/7Q/eg3CsD1Q+gw9q4fclwAw9eQ8iJIpoDE6XPg+i/OlvAQQ9d0SPg32Q/oQ+Z0CzPF1R2QcCJQ+jQ/Yw8oYkoyEOby0Dr5xwcQ9rQ/2g2xvCGH1Qo5e8Gvmqepp7Q/bQ9Qw9ZZwgw9PZn7K2yQ+zQ8Fg31qjaZiXgUNQ90pIt+ykmWOUrMw8Mw8cQ9EQ9ab4MbqiH33KmGLC/JIkw+pQ9H3Cko4cw/f8NMw/vZkaeUrMDdQ/ZQ9/aUgUCXgU9Q8iw90Q8o6XlQ8kj5E/phDHcw+t1CW+R0w/vZnIjJSw9Uw+sQ9w9S0w+1sFkw8hF5JiRDGXXQ8R8Dw4C8w+4w9nG6HHq8gCY6VohiJQ3uw+7tUlsEfQ9fp48tS7Q8Aw+Iw/rXx4a0ww/ew+iw9U6WGw/ow8Qw9PZlGw/aZieQ+JQ2aR3Kw/Bw+/Q/DhAJCQow9K+zvI65Q/6Q+Yw9Jw8CQ8Ow/5Q/9G6/dYhx2Ew83Q8ZGWIcCkw9c0jZw/PkLmLYsQ/sYArI5Vzwmw/FY7xw/yw9lWpPZl5Ubww9bQ/vZkx5gJw9kQ/Uw9/iopw+w5LVw9WuAZw/kCkdsjyJXBQ+Fw+WQ9rEWhEOF91Zw+/PG7kiiQ8hw8Fw+Jw/Tw5VfqVw8Kw8tw/+Q86w/cw+6XDmw9CQ9bbDWw9Pg+/Q+2qJhw/zw/RPHRu71iA2Q/IQ/CPEuw8TQ9311+hhXPRKQ8nihLPHHw/3Q9Wc169IrQ+inFJQ+Dw/FlwODGvw9pPFKfBFQ+Pw8S56lw/e2pCSiLw8FCCc9vwMA2FnyDfy5n3hxkbDUBriFlaU2xECwI/TnDII8a5lJVVT5nPf5jbVr3qaoLaFlFDReFlwZw4I8oI/sbXm5mSvhdESlRX4I9aFlPg9kI9ibWL5n2/wM5m4I/vBCeSAUIgZRX1NWsersI/UI+qeoEI9qbV79VhcEajDcI8a5lCI+kI8CI8VOHjRyEI8sI94FmmgBUI/iI+nQX93JyI9gkCiI97HD0I84c0QtAtOpKI+0FmaI/MI9qI8RA1L9DrrRiI9gkBh7xaI94I8PwZcUL8I9gkC2erCI95GXow02I9q9sgINSI96I+rM0ZkBf9lGI9q9tuyJ6ajOI+VmWdkAaW5eI8a5kAvymI8bY1GFnj1VBI8cbChI+6I/yI+NcHC33uI+tcExI+qI9RI+gEPxI/+I9UbARI8pI/ibC1OVhI8SrbwyORI95GUr+bMFnSI/ZI8GOxBI9zTD5I9ZI9qjE5I/pI9mI++pItYzow08I/oI/QFmwfoZI8KcKxI8krYtI+y5lNI+kZWBwtA6Z7+zBhKqp49I8DkIkKD1OCER3MLopfiuOX4NiW4N2gEGOUE70z0XrQ+HRlefYhWJAWA+/O3cAK72Ezj9T71EoGjneXX9G4bI9rqFNTAcFTHp6+yzfomzI+CQ2HI+MR3vXULw4OrZc7DM72HVX4Z4byz3HBRdsEMGCQ3iQopjbzUdcUOrLlt4xsUNfjcxT1wAfYHrVOsbT0/I/zjzxGEfI8A9PEuucT0JzEX84oHq/NsXknk8EgyxnUcl8JMUOn0onT2p/uTmdAo8GscAUNaYtvUftISNOtKFi2Osrj2T/vJUiM9too8dkM9oBpRrfI9dW7eTp+teETL9aHHTC3Lf/I9dW7OHDQ0djeiZFlHH6o9sZuZO8mfnoqtvBkiT/uscz1Ot4o+NOug8xyttEo9W8kUo9Io/R87c5o6Td0o8qUPmgr8mtlEwkb6CFrSTdgo/6UOtloDCOiEEduG+TKMdvwo9Ko9Cuv/j2p/thZOnttCo84tULLd8o+q8mAo8S0dYo8mo9OFr86d9G62W6YLe0T26o9Jmyso+ao+2W62Td9j3dcmDJG2o9dmvgo+8eB/I8qT1yo+mo+LWuvyhG8lGo/pMXUo/YCKlGHAo8/Qmgo8ho/OdM4iwyo8QarOdPKo/gdd+o/UhLLCPyQj6UPp+sJdsxG5V84Zo8VT3Ncmm10pus6o/aNWAEiMdv6sBO8l85X6o9co+NOtD3mgtuVo9Yb5ho8m8NEo9wtW0o9fR5OXF3MGkrf+T3TvJO85mtxJo/7UO4dtUo9gtU5o+iT1wAexRE+tu+o+Ub45ig80dpo+A0Oxut7tduo/0GwVo8fATZ85wMK0duf1VWm1v5WTOslT1yUGlC4ezeRwl5o9I5CLmtZcyMMOGzeFo+MMM2i4kddvXhyHXrTe7msO+kfNEsuupwk1XEKi1NuvXHjTvJHo/+zfvT2lzFgb5nTfnz1wAccZFFdspKbDo/So88df3n3G0N3o/Ro/uZ3do/Gz3Uo+ztJxo+Bo+z/tZeuFo/TNUzo/fo9ob4QY98Wtz1ejMN/o/9o/u0Nrqid1zIY/YY/wY/zcYfo9YEvJyPPo+to9U1HLtsnnjsAd78Hjdv+RTu0P/Fqv6dZo/OuFXo+UnLgo8j/aUWuyo9f/vwY9gY9WuE9NIBo/OuBWuEpo9PGtSLRn4VQeuKo9n4Xao8ZT1uo+P5k80dUAEX1XFo8DCNMo/u0OCY92o/u0O8Y9WT1V61kNAEY9so+muGz/ZyCOKGip/vkY8LdcMRLnMOXuubo8JtmbRBvo+Deqp/tZuYUY/aY+bFmmY+SxGT/tmJAxzeZ1XeOK7FkPuvSYkNG72Y9ozekY+0Z02Y9Cdd27j0uEWY8kY//o9ZOu1VqQY9ZOuDo/vo9BY/PcKYY/94EG9WJo+eY9S8pwNWiY+UY/n84kSaYY/mo/9FlRY8Go/WE5eesno+4dWWY/6Y9T1WoY9/XiHo8xdUOY/wEGcdWWo+Jz1s6ruY8uY+uo9+Ov2dIaWtTo8xdVXo9jo+FY8kY/cY//MHhY9Do+RY87o8dY83zMFo8sY+31WJY+zo+IlnyY8c2tro8ZY8vdfcQ5CdU7o+CYOZFlyBK6WupG0ti6XTeSo/HtUOeuSo+/tWdNy9dvxo+5dW7Y/pGdwAdqeMCdufeJg6Ey+CVY9Aurn86h5ISKPXo/DPM11Upeu+Y++lmDRzTdu4eylzE6wU+Y+hY/HOvdLpsdf8Y/osG9Y/RY/3OtqY8btsvo8ltkLY9qkA1XFblDg4/T7iwpXPQp+eugz26cUpd7lFlko8NgcDY9YY/7C4oo/K9d/Y95mcfdtfY//OuHY8wL0flTPC5jY94Y/E4+iY9gY82cn0Y9CY+wY+DwWfY/o48ZDUFo/dY9jtnDY9YY8Rusuo9M49WF6so/7Y8jRGTY8o49Zusk49fY884/0Y9TY8ulnXrzE9sKijfg1NJBLetlY9EzE+pAS+sy4+n0N5RF4YlM49I5AiL004+q48RY/bI5K4+K2uvyj6fsymHQbJ4JjfIhagcx+wa9vPCYiYP649plmwEDv0NyyGm491JdSY5hMPtSop8lH9Um48K9tm496gdHeujhtu49Ti42496L1u48/0Me48MPZWgcO4+u49249k3fhFmdhlm9shL2uW0KK2y/EFL3R49Z+sZiNGiSAP1kNCgrdx2uKW0juGJdWYWd8XzNQeHhlx489MMbyxD9tR4/54/wuuj9fP3j9Fn1/JF2vNrj052J0PVOt549idWWo+l4/R4/BY8T9dV49idVQ6bViMSMBeW15Y+V/Fp9v+W18dWXhlZ9vdvNtTP1Ov92sUP3D4+J5z1AYcsX94+l9teWr453LY/ViPLhhlYPV6mN+sL2v7W2MdW2Ot14/1Y9Ehl149Q9W/hmxL3R4+dubb4+qaL3Z3BNHpmdg2yHZ1VOtH4/TIBj49X/SF4/NdojMPBPSf9t5ykd8vCwW1+uj4/dW0cAc94/banp4+sp4S+sAIlwLYglna6j4SM9UyTW2f482DtThSRwcnY84OvshbK9WlqZ79tS9wgllpHGymcIE+EAe149f9lr4+n49gDdHRTC9YlRBoE/UODJgdQSmlGGb4/osGitRW9vvRwsllLPJGDeAr3yWPosH5Ot79d+7wsllNvzQOsxeQcsWQzNf48cfqp8vzTNv4+PXA7vMPY8eDukoheW1Rp6fhn748Jgflqx34+t48slnMm7PseL0CSE8LLc0Fi1ygglkpo+aVwcE9ZktrY+8/Hv4+1Ad6WxCcfRSSwfO4E9X48sE/3OukR5kDshKhAfNCE+x49PEhgfN8E/jiMGE+ME+3LcLCpH+iME974+ErqL/DURc52TnsGAl0iy2SudF3srTzYNPRpM3Re/LHYlf+E931Pol2Qn6P1Ogl37gtCXczuP7LB3eQ/h3hE9GwRf1PLuP6JlUrHftM9xmSxcpE993skKuKcGUl1802SNMeE8MmShufnl3srWmNPZE/GdRhlGINNLxckuevFev16VE+r3ulE9fFf7WPrJceue2eO0QtQNPDl1pa6kNMQeOGWEm3esuc+xcfFkludsK6ZE9LpN33uDE9Xl1oePr15sNOYeMnPvdE+A2PoOnxDpPOdF3vIjsCNMLE9fXzoNMiNOY4FiNOgl1/Pu5E+wl0fPsauf6B0oJfyNM7E/vVBKNN520jIWRE8hl0nDYFXdHFdPSvwcGAl03E8UeML8Eq9b2ucmMGM65+NOmdN5LDInIWdNJ8GENbZR1yePSM6WueC2Ml1CNh1XUF3E80vNBufnl1ZD4eNNFl1mlURudPFeNUlvE8xuczlUIk9+E8wk9JuevHeQk+RNMAeO8BkxNPDl0SBm5ucKPuJZG6l1ueOkLW1ufzpM5M4bE9el3/E/dR1oeMkk8FNO7uPzs0Nuc4eN4k9lNNJ8H0V5tucQk8cOgeufSZPdufZIeZ1ADVl+XPvM78k/KZOZkfPM78k9uXN51AEjRynQzucujd+J63VmjdNnMmXVnLufM8fLVmnVnrufCV6Kk+fR0hneRPsak9wV3vM4bVmHudpPs3Vnfgk4Dn+jdjQv1ldBjdPuc1nfQ7l5h0HdP3ucE3ftkddldY3eVPvxjcT2mekIZtOXePpw7ztNPeMurZotMek8hyxGXwfNNKgM+k8nx3TPtuk9/ucLlf7LD7iDuk+A5P7LA35DRlFrlcTPtXE/MV18OP1ecek/dXdNtNj1PRjZXE8MV2xa4TtOq+O5k9LsEGV1XxMUNMmV0Fk+XCH5k80r5Vmk5k+WNqhmmvldFZGaefOV1tZW+eereNNk/wcEmV3wnsLefcvtzyBek8+tPkOl+tOLxUQ+Nd97GrG7ecRvtDk8TtM3XN9k8vNOWVfs1epk8xk8dk8Pef3letk+CeeveMCOn8Gjuk8wVckrXNk9hF2bk9tk9PeNxYFkkmdtP8vsHk9cVfxiBlefsVcRiDqtO2+OyMBiNPMV2ARbhmGYVcXoujtPvPvFKXvefnk/WpwLk8HZOdbnjtrQ9MAJttrXxk+PZOWvvtgSwtOXeNURYBE8Pk9OrrtsFXk85Wevk9BUcYys2ECKVdfk9rTiqVdAVf4RZemE6tPaPt8BKQU8C9N5LBfZi3h2q+MZJO1k8z2N5LCqiinecRcPEU/dtO2Vd/k9eQg5VeOJxUU/+VEutOWvt7FmPNNbeeMU/qtOU+MEU8/h3tk+7oZNmlcU+Bqy/2M42CjlVoU+3k+ngWJecQVesBm+k8bk8Jbohk/cvvT8waNMvx3nlUUU+ZVfyM6aecOtNx3dK62QhsPrKbwcmTH6XVqXsmTFuWrJDc2Bu2lFYD0+D3RtIQXsVqNtaBfXhB43lD00kP5De3ccfLyYrPID0WU84rNkD0rNIG2xFwuX+sWWTuU9y1nTUKEXuTqPjhpvV1DqNBWGR13wD00lJm12cD0KRqLV0YFtSzcMXuK40brsKRoxU8Hwd0e5IStw135XuhU+CrO1rNJ1KFXueIebXWaU+cjcyBuzDLCXsoBvVwRiXvrDdUwk3qPWD12UGqrMDrMO1LHBmSjc+LfHyF652kBuykhAXsxyE0lIc13YD3xU93DfR8mDhmPDcoRkUKDNDfWU8Pr1mXtkxGVlKWXsmTFmJA2XuRTEqqp1qMerOF3oAN0gjdyAlTJLgjfNnNLU9QjeJyF+175D3UXOkp5FD1tHOLzBhU/ID17U9ojeJyGGMDhXvCD088C1U/wD05143yENwscW3BU9nU/okHJXvMrMEgWFrMbrvPU/wF1lrMwsV5XuVrMssUQApkFtFXualZB7ysjfZU+alYqoI0FtbU8GFg1Xtv9mGMBYN0KrMGmCSWh4aPWD0nU+tXs2AnQ09qaOvqP3FbdXuKeFXFZ9XufuHYMADXsHU9JB7zrMhlcPXcMc4N1lihn5Cc0G1VoXfD0xnchXMt1lVIcFla94AmjcaFtak8Gla71mWjdezLeaN1Id6jcPZDuaOWIn1aC80/Oje2jc80/OaNejfwKFn1nvrP3rPbufPyBs09+jcTxtP/mBjdJbsxftKlDi09hje0j32k9jCdKRtRNGFXMTeNSOc0kXxX1u3tKbNDSZW3v9otK1Jg3uA3u+5CRU9Q3um09abNw6NG08G0+XIfR6uo3t83eZU8Y3slFurkHY3uhj1q8uJRoG0/m0/e0+Xje209EuUNF08j3XGly3sAoerhlLcRK7FA6PeiZ03s3aMt8cgxlS3s2ovP1AFFAUUHB08lb4c3sIodbKCWU8rF2CTOzGuh0/K3v8xa1U+6of2YOE0n43sgfpeSSe09HLfdkj4SFF0/iMA/Bn7IuRos5xa63uxoeJcOFvrwbO2ocs5Ae09hofFweYxBN0/2bMKhvlHidF2+oukjABU/4octgvaYkSj055mE0kT0+KaFGj0qDiae7NIL2ttEofWcNYbEh3uvBskqAZ3sR3t0hlJjeG09NV6pjcM3uK5tsoVD0/badg3up3ukRmd0/O3tqU/PoUqJm+W71nOFWN3BzcdMlWPyRwYdNHtPXb7dnOP09JOrzFe9WPjHZLFcRpMArHppOhJmuo0bFd30+WA7bFcAM+FYKmVfTnNjUF/tOEXPQIOAdMTWNOxEXFc9xGjRFXuO/081dJ3FcKg8EaGPFf3UmbnaodNcl02H7h9ovFerOOUrG9pOFcd0g+02NDpOXy6GldKXPdnadUYTpO2OPhmqa2OOOMY0FQlcHvu40GfnMydNsM+IldExHMM8oleDWMIrFAXNs5FXCFjFe8IPA5CEeONyE4M8ElcCY30n68le/09LMmIXMDxHOeQoXNRQ2etQgk9309MORYXN520rg0qdOFpPUn5IdJmucwM8BrF/pPiM+bPHkXOfxEmM9UXNBZmwg5pl3E0lntcMXPmJmMejMXOfxE3WySlf6H4B9wyle/0+bRDylcDxF0nhaeONpMY01CXMvM3G0EmdOIk/GYPBM8v0+WWB6ldkZOUMBUM9mONUSBRdNSl0HIMWlckdNCuPWldnqNBjYpdPvnN7MDH23LpNZM9rl1w0npM8mXNQxEpM9elehONmJBWXPiM+2DABlfeM8OM/BlfzR0k08w86yNmh2PV5GKNnCk800+EYONeMJlc7rNe8a9dPvl0s08IlCqNnyk94MDyZPZlfY3dg3fDM/VeN6Nmx5EpXMFkehtDix6CxG6k/PFC7x0VleGk+7MADM/rdOmk+Txvmk+K0/BjdAbO7x2tlcRjeswcOk/E3dOk89lcuk8qJl7RzXeN1uOReVNXM2j3ynaPdPlZNnRwbldBefDnbxBhcV0w9PXM99XPqh20INfdOA5OsA/D21rlf0n7cdPxZNxHsQ9NgA/iO2zZMNHtw9PNXN3y7Y9NI9Mws9H2No9PcK4Y9PpZPws8bXMtZNDnvXlcNZNtnvDZPk9O2Zly+rQ+O4s/cw0TZhWV0Qs8hKDIpEos9km3blc0V34Wet42w+dx6GyBtHhS65eytGti455dC2ugaSY+ctv0pABkqSx+fCtH2l4BOvpZejvFYV78s/rBdss/cs/VZdF6tMDWDpd5gPAQh+BePwUMs9Isss+fCtFMhh7f23v182sJKLc+fNNl96tkoihpeo2fCKog5csvHrG3An3MZc0jPbSjfDvt+djGkys89ZfDpZUG1cY0lBcOxBg0RjP3ms9as/fH15pftr7ukLXP2as8BEipGQSBc0jN2/hyjsAv0OxCVvSiYvdBeBs8n8zEtn0f19WES0iB+c6OdUORtpfdvG91IalBWs95r4wTCSs+Ks9HBkss9rv2G2fXyjRs8GzfxRzrP1eVa5s/ABMzpdZs84HA8s/ps+LH0/P1gxqps8mf0Js8En1bpfUxDp1S7pecs/Zbbc4nF5dQCbes+Vf0KjO0Q5qpdQi06OJXpfbatem3en3Fs+2zcFUr5s/PBlifqFZf8tlds9Mn2Zs/ts/Rn1ps8ts//pfWs+8Y27peqs9ajN6s+kv3mv1q+qps9SbnZAOhF0YX2Vs/OIq/n2ds8YFRDs81s9MvQzs+sv3mE1Rs8hZerNGCl5JjvmP1I3qxs8FY2Cv2t15F4ix5ciA4Xs+iYs6Beu16hqa66ERs+xoenn3Gs/h17/TUv+erfHAVBEcTAZdkA77s9ev1u/4XAMwc9Gv2jPbAguQc9y5eu17w3h24uxBen6tuVCghcsvGyKnun3i5dPs8ds9S5cTJzF+BbNAaZcEtlJx4Hs9u5cJ61Ec9h5fUPob9Ka+cY15MhKmZfF5ekc+SBZNZd9avHlbHxC3f3HDcyGo8c9rFa455pTmYc+T61FwpbZfZrdkc/MY2lv06sV8kXis/Sc84X3Fs/mnoSc88s9rFbCKrNv3ktkDAXHs8mf1L62dmSss8tNl9s89s/n62Xs8rrqjrd+s8R+fmP3H62Un1Tv1LRlb61Gc8NBd6c/cc+yc+vLQMX2Zs8Cc8Mc9Ss8qc8oc/ohfVlams91ZcCvFyc8uBecc8EjTPBNec/oG3sc8uc9oRzyc92s/QG12X2HZeaVZJbYjZfGv3PHkyc9uZctjPAG0Hs/Ec/vsWic8wBdQVbAybZc+Nla/zxrZeoxmtPP4c9Jf3axnoodGc9hBdtlZBs+Sc8Y6uNlb6c8/pfdlYFc9Qc8TNm5c8hc9Bc+3Zfe6Ghc/pc+OBfIVYich0f2Qv3Rc/vZcn6uDc9dBfmc8Rc+/v0Bs9dc+A5e6tntc/6s+3rdiY1zc+LsV/s8Gc/Fc8zBctP0KgVhs93pdVc+bc9yhfC06rc/9c8O16iB5ns89c/f63DY1GZebjf1c+Vf0YLc2Szdf0gbfYbzhv2sc9RcBuc/i5febqqc9+6Euf2Zbp9c9eZekVYjFLfX18ZcfZym06+rRic93jfS/DBf0vvGa05fc95c9MmhGaj8c+ZVE5/EZc8Enk6c8pc/kbfLc8of2Jc/d+rHc9wc/ilWGCxa4vqv2m04JghYhcEtkY88IuvXNnTGFA8+6c9k89rtYtf0mSnPc/EZfs04DLSR5esc+PCFGc/9f1a3ORc90c+4Lzyc/Uc9pjAOc9Xc888/4c/U894QFFs9ac9C89B5es8/dFUs88EtkS8+M8+k896qCls+7c8UxlYV5JDvMf1kQnKs8p5d+c87o3w8/7f0L5w2V7zaFXc+Ac/55fPNkG89l5fB7fx4Z68/hf1d7ftnZopAJhfFVZW8+Ohcz7fxVZ289XLlz5dl5DjCputkN5cO88L05fLLW88u8+O8+kxQ+8+AfdIEf2Qne8+j5cT7du8/orCt5cEX7F17u8/Y/0pmDR88B89nvdZT7Afc/F46nq8tkGFfX7cj+yPNlZhcY14XRLNEsthcnHl0RLNFcn5fXHnCKrn5d8GsAXqCtlJFfX7dhnpNXHZ89VsC/zxh/0XhcjDeV89OFeK14Rboss918/t8+LH3dhftsX/TWc/1N8+jla+rSH/36/05c+Utl2nVmjgTNlHQjwFcW/0jNnRLzW/0dFfdlZis+lFeT8/iXAH91UlKLsVHUibheEFeHNlD8/j/0mGSZc9Isud88Lizd880Fd3c+vNksFd6VYqA0n8/LwTX7cJxhcYIyFcofeSHqWs8UfMifcR3nb8jL901GvRVb4UT9/0tFfG16Q7rAn0SFeotl4+wfpEcFdljf0V4/aHL8/RVaNSAQC/N/17Vzebrn8+5Fcd/1QC8bs86Fc4FwJVYPKxV8+AHc9661880Fewnn/Chh/0T/2SHpAtlWFctMObjf6tmt88itkx+AgC97/3RVbqs/W/2iFdatkBooiFef8+A8+Ss+AC+UC8oC+gC/kbdUC/BzuY0rs0UqVBj89QReBHdyVCcC+VgJIC+sC9rH2kFcQbdMC/p89YC+cYHtheP5cXc9UUyoC9Hlb2iL1+MERe5WNKLNZF3wD1aC+6U9TyFjm4GU+SXNJJxmU8+D3GC8IrNkD3tGfwXvID1VZwK120D1qi62jrZwt0xGXdSlDebxHeWBuU/erNFuuMKYeC+Y+uebCvyGcD2DqEBU9hD0rRHkXt0xEGrydDdy5Fs8E9DezHOT9Gg13dwvxi4sXsKD2RC8pU/fU9XKxZXtSaPBC9oF3A08P0Gd09Y10P0ENU/KaPAS2lFpmD2lU/GOnlU/aaOlC+yXsDrOJZliXuvqODqH5C/XwtZusbNQ7wf6C8sMmaXstC/zhrb5tAaNqlBKN2mC/Ce4vDdL1EK1bDU8ydNNWCRU86C+3TyTU9jyGfGzurO1C9RMlptnpD33OnLU9L1FxMmBrOuC/LC9KIcW5GbOk7U8+TGbC/YFvlD07C8ZIeuC8nniYjfa1GpIAXU/WC8oHj4jf6C9YpNu10nC8r2KPU/RC/PabpXti5E+SBZXtDD0+SDtU9jD3F5CFXvpC8XC9A09Csmds71C+5C+pICp10MFvmoAw0/iXvmoA9C+3qOQi/I08ZcmJRIdXu1C+dOcyjdylnzcaTrNL1Ei0oN1031Ek3pE091M+BkdiDB3tn009jk3RaO3Xug3cT05Xtkd11AdmVdHi+LLXuplemWDodlnrMADU/tkMi/Kk8d8nwdns08yclj1mS085leUu6Ucmci/7Pmp2O7bii0/I3eGo7d1nDIfo3fUwf27MWk+xjdWk8f85BCjTIfhjeNnenLsuQAdkck3dNldh4+f9a4Swg6OA3uai9raMm0/cnGtaPai8HWAokJdaOynP6i99aNw6M6i+UhE5FsP0HtU9+3teDm67jIN2lF0XutnF1KbMFp1ai8Cj1ui+6i8M3vPuspm08j3AdnnaOK3f+i87aM03teZxZ0+x0+j2MuTvBi+J08+pAxU+Rj3YdAMD277KPaMVGxmU+vaPLZ6sbP9aMwrPyN0Zi/hWGY6Pai+/qy/yFA6OS97ui91uNz/Hg6Mhi/WS2vyEcj0kHdN50Sj2x6BNolD085WCF09908SclHU6Y6O9oc1nNBFHkTRXGvemtX4De4gAdewCH5oQK6e3msuKqqOvlz0T3aajLbCPfGv355AmvcWvTi8E+emmvji98rzymsji+amtO6cDi99/e0tuFFFiShHUfKGeFFF/XAotuFmvOBA4Rj9i/hF3Hi+s2sdjtaGyrWvCBCXi+W9dEemHtyktsC6dA4kbi9MmtdFFLi8vi/OBD+9QMtsTdlKakcmvPtvzKufi9Xi/N05/mvvGt5528WscWuugnsWtUduCTamX1hWuRdsLFHjsrM6cxfFLejp3zStsTdn93UIt2Itvw4k1febi9pdy0mtri8R53N/fLi8Q9UmmsM6fgTsa/d9msES+ShfgS/Ceq6ms9i8hKaamv3GvyOgAS8w2u8JTyuRji9eSlgmtEmuaSkH+dcS9Aeptms9i9q8IU2simv6miMryZo9PfEiS8tWukS+ymhB4rGdd6WudRWQS9cdurFEoS84S+ETnJN2YS+sS+ot3ptuBzs3i+h6fuTvAygftcBT3IlGAFj7dcZ4nS3B7Y+Sdn/g3NmvDi8TCzsWs9i9KQ0nN3gS/plA8S9QS8Z4kdHQIddDmsZGRgS9mGc3F0KS9pdeV4miS9YdeX52UA+4ddEfGACg1BdiWvGuTiBd6mtDlcqWvbqn+CVGS+xS80dcZ4lenB6Y86z3a/bbi88deUPdCNLs/NI2u3H0U2vYmsqmTOS/Xz2NVMJ1E1WvDi+lS8BY8BdnndHAS8FS/dvLr6ePqiaVNuS8XT30fFM6yxS9pddCdkyS9mduofc0nKqdfJVPjECHj1vWvEn3hS+6duwYfGS/36cB/ZZ9IIdtIS8AZ57WuJdujS+xS/CS+bh0nms9i90YyAWuMS8AIzHt1cS+dtGiWsrS+0+ZhWuLS+BIwOS8uS9pxnCiLYYnTIVqn2wS9Lms/dEU2uIduYleCRBQmsjdkAynrWvRS9LS96Y+3S93tU7mtI6dcdkxRAZfGQWvh2bDS9ats51OxS+Pi9Bn17Wu7i9+n2lWuDdckTaDi8WWv9T11xmE2sjS8UhKfS/FS+9qXe4jNS/APc9JzeWtbdvGdkBS+E9c9500ORBWtddfmdllQK7olwy+SdUKS/RWv/jadS/vi8U7i/Wsgy+Yy9TtvNqUAy/vS/8Z7Iy+C2vwy97WtwS8Qy8xdtjmvcy9iS+JfGgy8tY+NdlIy8/te1mtMy8XmuMS8My9Xi+0y8Xddiy8hbDUy/gS+WQ1hWtzS/ky9hWtBGfmdkKy9SS8yy/vdchKHGdkNUQpte9xkKy+Sy+l1BHWs42tldn9S+rWufpwyWvYmti1Bn8g5fEt4amveTS+NfHBYkpdnG8JFGcjzw7dn6S86deFpluy8Y9d4VcIy+3mu/y7QBdI2tRpa7BeD6e9273S/ey/P7qSS+ndu9264y/HWsRven7KbS9BduDxnISxq4/0fHRy9WS9LWvRkXEhdEms5y9klwhy+fcDPS989dpVeE6za9eJil7S+J6cBdkrc6E2v3Gs1y97WvZy98KY7S+By9Ny/LCM2y/ES/U2uBy8dy9c9enil8S9Vy8Zy99y8IL3Vy/ZYIfN0F6cRN3s0w82uSciTvf7i+fGe6y9+t7CiKkmuCdnVN0WgaWy/ZS9AmeofGeGXS2shy+/0gS2sc9vu9eXt6MuAwmcR9f++CHy8h9dQEeny8p9dZ9f/6BbWz62up9dT5dl/YHLBHy9gEcXy/R9eYmfnveNFBetDtGmq9uA1B0fAYmdEmcPveXPJfy90megGCfy+59eSOcYg9vZ5vCQ6dm+9sO1O5dkwK8bdCaOtV9fHFd5A+N9fe1NmJAotCoK8FPc8yj2LHwK8TJ5n2vF9fIK952tLmdpxlBdnP9cMpmDi/r2sZ2vcy+l4/h2v/S/L2vEK8eKaji90Dt6y/sOu9L2mTZPZpEDfL9d2dlvi8iDvGdk8K+gWfGdkLy+HiP79csK+yOvumfBpm5NjjiPn9fiy+mDdUK/UQy9N2t9tDVM3i9V2uMpx9i/P9cJdksdmN2tBUGQVcoK+MDsX2v5+I6OtcK97jZi7RADefL3GK8ry/aDezzuQlkKK/6DeQVfjEDf2sQOti35H2sAOs1TYEOsAOu2y+KOtH9tldmZdmXiPQDfZfdCK+WK9J25dhSmLFzmf5276lmyOvSDtKK+eK/r9cRdnedl0DftV1OK+VSFf9t2K+UOtsDeQVfPi+eDutxkWK+hK+ey/YS9IDt8DuFpl5K+KK8Hn24mun5gQOvAz4GOtICoRRrZ26+qFa7FVK9LIjURd/fqf4cBYd0I558QryeQn7cYcwYcmUnkYezofb9NmYdPKelO2s6NqYeDK9roeSqdvRcGnwSYfFqfdK8zoeoqcdK9UYf0KetK8wWOHocGrVBmO2Kf7gvWLTtK/zWwaiez4fRjZ6WPdYe7K9BEfvofTINZ6OXyeP9PcYcLK/etqTK8XK8tr5NSPZxdbK8iidAPtQ9TQYdWxf+l78yMtK8KeqdyOcYdpE8syN64ffK9YYftCuxa4/Yey4dw01hYfUYek46CYfLK+drkzK9KReaxLzK/Zxc/qrn4fAq9WQLb4dEKf0oMoq+pidObmjXQZidIpzooOdK8OxeKwh8YcvK9PK+FiepMGQN65Ef2SPhbnN6MyYcOuNvK8vK9/tIBKcdRfBW324c4q8YMFuKO/K+sq83id70lMq9/Ke7pFFZGJYeoqc0q/9ieU4WSk39K/0Kdkq+WYdPyfkOl7K8uKcspeJgOOYfYb28JesGMUq8RiCwmPUq/jLQ94co9mY0Az4cDimSQtAq9PKezDYL6NqYcGq+gq9Nqdfk9eCSxKeB6k3SssyOJKcyOk36OcKdMD5kGO87v8vtKGN4YeCpfTyPg4fz+lKq8BEj1Kueq904fOSdvx7/k3x4fEyPOq+M4eV4cOq+l4cS9kwfrfyOeYfGq+ByPzpslbndWYXm0S9mYph+q+z4dBQugq8wYevE+j4eqps5M6Gq+tYfIkVnYfgHvYysb4cS9mboHRyOs4fwk/DYf04dmlWhq/Bq9JD5nYfsqe8BnJ4fFqdNq+q4d64f1q+kKPvYdZD5XYezoeVq8eYeZq/K9JeKNjodMyvPYe9q8NsrRpsU6kVUl6q/tq/VxqfK8fKf305AGP34cjq+i4fw4f0ytDq/UYd9q/CHvSOndq/uq8tq/0V6I4eQ9mtq+GSfTYe0w4uq9wKNBJ6Jq/AKdvQ4amOHofKDbrGP2SeM9nf4Rk4f84fXq9L4d1q+7Fx+q9rYenq+hq+Zq+w+oV4e/q8FLTvyNhq9FwLRq/vq+k5In4e3Sc6yv0q+bKenysga97pvCq9ktpuKMCq9/q8BHukglnq+6YeND5K4eHq8/oGq4fWqd3q+a4crqfhM6rklk4fhYevq9tq8mOmYa+kKMBYffq/y4cxq8oa8D4ewLWS4e9q9wa+lSdQa+Lq+ka+Qbqu4efxcsa+e4c6ys6V0qBHYa/6SgXpt/L6c0Sjq+Zq+mryh4fL4eks6j4fia/rrQx4cxq9nyj5YeDHvIJdsSWq4eNq8Sa9jSeFKfxfWJgMVKctyuTSAlm0U9nyDIXyP5q8OUkRq+BJdCa/VKd9ysPYfVYfd1B2q8vq/lWBMa/N4dWa/rq+rq/Mb6+KPUq8Oa8aq9pBNApZD4fDq/OUnhKMxq9N0oeYemq9PL7Qa9LYdnj0z4c2JdP5uq4eZq/Ra9wyfea91Uqi4exa9iadzYcS9nIq9HSMxq/pa+wns2JcRewsyOZq+5a8Lqe94dRXSIq8bqfGjvC9mEa86ZzJpN34fvofVpi0WOJZtbi/IWMD4dVa/NK+3odlQapSOtYcV23THICpsRJdyTAldIPqcsr69a8IEffqdQ4GDa9QafJ1DHwZDa924/PM5yVaoEdFJfrkR9a/AacEX6y7XQSmPKMsr4Ta9ja9La8za9wafaJBba+KnvDa/e7N+YGyA10EeiEcmEVjin0Eena+AqO4aejlUbmPaMP7Zv305QSC8EcjJfjG6K9nna9cxziEcRaf6lXiEf0afPa/SEdXa/Y9l66Mfa/Ea94qMcadoa8wWPfa9lpSkqP1TCHJcoa86EfeH1BJ6pjycqNlEfw69Uq9Sae09lxEduafNQ51a+Fac6ythkOpnuOEdJQ4QWNzntBac0a9lyceEf4a8SqPpEfK9nSq/9yfCJ4VoR+EeSqN7x5oEJhEeeIR9FzIw6Na+vW25RONfUo6/dycTJwIRbuWO5lZlYu5fX+WP3Zsg5uhfUJESseHKEcNERwRHfa+hsmQ68gVB3L7vTzNxmrnsKvtrHJm9kDaeE+Ntx72EcPntBRM8gnU68jafCJ6gCDO5tk6+q6/JEeeYD4HOVcS308RpPbcTEdNW6/XTmTFdHtMdTlv0+FWOO6+Ph29WNJj0/092cfbuWrFfVD3jLKxE/O6+cdigM8+6+pxAFpPTnO/PGHFf/tMeYBwM8VpPktCIM+oAkpxC+M92ce6ODoM/69bKTJYM/iD3AAovFcEZMZ6/vFeSXOL5IYdPnnNoCnkM9mOOF/L4dMUknK5IglceAnbcrgle1ccmZoolfQlec2rsM/ZUttXxcM82Ak8JX/nOYhEmgpJM+7pPl6826+J69cLdiM/9cexyJCdOjceB1TElcdvKklfO694uhKM9WnEwwDUlcRpNzF6x23YXPWjWMlcpD0dvEslc7yErBZGM/9ccf1KmM+JyGb6/Ol2TpNO+YClfNo3gDp2M+oAmn69ildtfMKbYIZNy5EAimcXPz68JVJoZMP68IxxKlcoLE4sredP3Un7eYaleK9altjalfz0v969Yl0F6/lWD4dPF6+P6/XsEJM+SPJOeNVce04SpM/y8FJsp2lcHvtUdCOlecZNIG8ulet6+FQfuleDWOATrmXNYxGQG++lfT0suuhVM8EG9yMq1M/1QOhld4DmmZPik+D9amZOtM9NlcUG+GZMRlfUKBH8DJle9M/VIe8qnjv4Zle/YqdTGjNMzM9AnO+XOTdO2tC+XNbufci96j78DnTM/UKBteiteNkwdZKAcG81ldy08JbsK085PvJbujM/2BAcDmlXOHdPq0+PufSi9dzNInHwKqXM9hj2OYDgs8NZPw4D3M+92O/PFPM/0cMmG/dXNaMs34JZZMLleG0s/M//dPUbD/M+2x1sApAs/lZMlF6gs8OG83M8GG9LKZQs82j22Wqws8Wj2BG8Is/NXPBZLIs+zZMhG9os/x8fz+6Ys9hG8mxw4s8UtNfKk3tMMefWcNJsY+G/vAtedMk+Mw9NWS7a+O/M8lpLHZOc9NPJZDCGM9NvpL4Vdi+Op9YS9NS+N2415ZPDXMRsb89N6VfNSVC9PEVc1G/UV1BUdW41VG8AU9lG+3ZNmG8fTqCee9G+f1sOx3K9O5G9K9MAUc9uOZ+VTRN7LM3VyC1H+vM19H4zkwCAF/tzG+2Dlu9C4xNTG+ESFYJ0W8Gfyg2v1RQb05MNJ1T77qwg9kvQdnbG8HZpUJ1VDlVpy0jRMAV+J3nG+LG/h9pfO0z5xjgcP0E68EuCeW/zi5OKJ0ev1+FJ2rcWDkg8mD3fqMEYSFa6T8J09CZM6HEZ36AUxZ0+JHp/vkZ1XffSwk3G+twiiZneCc1/uIOl3G/dtEExPNyxXG/fG9W5PIfI+DmKnTk/cBDlHk5O5OLDlhXQ+pMX6BIJ2K6H7/u6Z1jO0km+vROt9EY/frtHX/v3XFTMEntEa3Mom9Xfe9TDIQcIm+wm/HkOrG+3G/sm8TSDkAVXG9o8kO3N0m9Hv3KvDH0s/tmoZaqIHEUu1RiJpauVACm97zzNJE8m8sRf4m98BTF5M4m/uDTYm+gMF26GQjkDO2LDk36Zyu0BDnYHqMm+99EDDnqfY/p3am8gQPXFPEm8Qo+OxNkm/Y5yyVw4vc4jkzlwUAeCm/66EvKh+xd8m/6m+S/dPG+RpwnG+28Gem/O6Gam8Qm9gZ6Rpzo3Lr5MSp0r6EXG/mUuIp0dJHCm8H2nHdwQGHgMARu0BDlS4F8lOJm+SnpUb2LDmaZKEm+ym/M0WRhTaPd7G8bpZEAcPcF6Z2kZaZm+TmRxZnppakm9rul1nFFpbvAdUm/J0UvG81u2gm9C8mTFNnG9+8ljxNMm8HfdMdHQp0SZ0r6HRm/ip1qFEr6HBm+eZ2hm9Nm+vb1L9pXDlEdEZ/eAm936F4wSCFMpm85m+Ge3U8EZ5y9m+MSwpm/Lm9gaHqm8Z10Gm+/G+81yRUpsFNicjhlwFm+qBD4zloZZoAdqKyJp1HuOOm9Hm8DDmEp2zUtTm9kpxALBOrdvDkqNDSzijm+0mxnDkQp28beFp2tf17AdOm8p5yesgo0uSm8I1wfm8xm8Wm8yp2HPexm/Jk7xm+IJ3Hm97R3+p13m8Xm/cxNrG8weMVm/OCTNJGvBZOFOAW90pwlm9JBQS5ypm+5ReNm/vgNeFMtm+wW+FA98m+DcVEb0BPg513Am9tr0tm/AW8kaE7ffmdG9xNnm/T+F75W2AerRn0m/5dHBe2UW9plzZdFEZ12BpzJEGJJ5FM3AaeZ4GHVuAcIp39m/3uNMW8SRQWZmgFWvxP+qEIFGsW+txPrm8DDkkMa4A8BDkt6xQve5NLT6F9x61UvDm9S2TQ+0LiTJE76W/nbdfm+XdGIW9cm9zJEaW+S0t8m+qW8Nu3EW8wNyAA/2W9rm9foHuDm5Vzrxf2m+CW/0vdkzq/uOFQP0veYW9/5U/m9Zm9vuNyW8Bek9f0vm9Ku3qW+4p0RW/Hm9WW/Su2LDk6W/mm+CHnGW9Iu15m+ndGUm9Jellm9mW/rPf2m+xW/0W+GZ6ck4qkh2W/pJG2wTiUuRW8JRjWvfbm8klwPm/QW8DDmygaQlORW+Dm9ZRnTe0MeNSW/CW9lDlbcUVW/veLdE7KQNDm8yW8p4/1PPyW9XDnGQitW/wW9AsAwAeQOnHm9rnK4A9Pm/eE56AcrRF9W+GQPsJeGW/M+PLgfUbndm+zW++FMtm8zAQ+GFLG/8wX31xo7cjDn2E6nAe7W/MmEXG8TW8DDlx96SlNFm++p6km9Xm/J6FkrjpW+VW9CmGBW/bm8KmE/m93W8sCtmm9np34zkymGXm+vW9sU5Z/snW90FXgm/KW/OmHGm8KlMWDkdk63W9PW/1wUym+lm+js5l4DwCHb5Es+1OJzLDl5W+Ts4Zm/5zkuW+P9G2u4S+2Gm+p9Hxwp8reQ28Tm+i+3E2+qm+rvdTm8HTu2X79NDjAwPA9xk4DVdzplTZ0Y/3U2+M2+fA/BZYUwas2+wg/vy9LE4Rd2u+1M28qU4M2+m+3828SV58pxUjkgaR02/Pm9i28S6Bc2/3y8SZZ4ETLzD828yZby2/6FDC28g+tjNcY24jMFcMvjv6++2tf1FclqwOr+2629I28GkoiMvIpyzck7MtA3yUk6epYnZ2HihnZ0Df0fEirJfbZ1Upxm2/a2+MN0wKh5cmWl4G2+a8722/07uh+0FW9Yjn628629Ii1+zEe2+B2/GW9ig+O289Dlo2/7WzK5qZDlO/vEg/Pd2l5wrfnOMusdg2N1WJVag+x2ZveOxxoeMvS46oZZJ29pqECgTBMuck56fzLMvLHqJDmZWK5ffOxQ4pxh28O2+e2+2W8HlMc52TJxZdxTg8R2++sAGckB2+MN0PSxMfL9myDBzvDlR29/JBU1il5xTjxGg91HS90VVX6pZHdOkc0gXJz2wxpqFhfhX8RT29x2+oVN0GhHDlmm/5g+wYK+raTJz3PCEVPG28d28lZTxg9vzg729N29K8HQ/ixRack61gcmMtL2+pDnBm+WffJfpV2/Am8v+0Z2+X2/+2+g9E35AXJyH2+nMvmoprDm728HMsRLia+PEK1d29z/EUJpT2+VckT28j+0wjkL28Y7uEjtT29ccnditugiXNs0id7f3BN30iekLN1DuSic8T2Dju8caRye8Tvmr0jL2gt1kTncidFMHzjt8iex4YEO9+d3AtsxVbTDvkyEYO8CT1od2oO/AlG3DtIO+I+eDDvyifiL3Ad1otvqicijtD2HsO/xjtottRr1CTuRr11H1mjsGifKOE0O+Jr10O+XDvh2HbETrDbiO8r2GHr3jN1EyHKidBr2+t2HsEFic5TvwOHEBhZYuIO+5MbJT24O+YR0Nr1dqmEO+P2HySfqd2HN1+idh7lKO+P2HqO+XN3yO8nwkiT30O/hicEjF2O+br1W4nZjl1dqPGfmO/Jidms8ad0eO93t3JDurr1uO/Xt1RidoO9md0MUaYO8oO82O+xbGVTtOua5NhwjuHIswb04O9hO99id8O8EOFGO/BO8difYju6O8qLllz0GO8/r1vz3GO9XnlpO/NjvyuYQ70iO+JO8jDtlifxO8F6bjXk3+LRO+2jsZttzSecjs3jlTicOO+8juk2Hfidev2aO+LicsEug4l9Nq/r3oO/rif6O/BO9bidmO8BO/QScyTtvh2WO9FTsNbNDO/2+fwTnnif6BdujlPuK5O+kO9cLagSeLTuWY26b2hz3uO95LH/iciO9tO8K2lOTv2OHlSfoTtNY3bO8tT1dd06b36habO8Vju0tpV6e+Tt6cEIyeFjtg1q3r0hTu+7MR6d9O+4Sca6F1N0+b2Qb3vO+A9744szDvfO/nbF3O9kjFHO/tt36MGKSfJv3+N2YoYkSeQTvqScYSchTvijlo71UyGTt1KlpvO+m/j2jnMSe/v3kjsMScxz3ZO9sSddjuc4PFb22BeIO88Sfwu8oO8qSfMz19O+Db3qf0ku/e5gDO+STt/lqU6d4u/SSf2+dujm9b3Uz2CO9CSdkjvATkUu9a4sTDtwu/hT00O9aSe2BfYu/4u9rO/Lb1LSe5jvgu+lyeWjuUO+072wc/5jklSdlO/+ydfjsYu+k71/jv9d1mSdV73nO/0dseScjt17jkyu+wu95yeDxz1d2e5q9O/XO+dSfYz06u9TonFO8xTtOdsgyeiYt2TsxSfo4v9N0mam9O+sjvydss73uO+Gu/Id1mSdou+zTthdsGSdbNleO8qu/ad0CscVydtBfbDtau+4u8jO8ZSc6t18yGVSdJO/M70DSd9O91SfSjvOu/pO/39spO8/DthSf0u/MTsNSd3T15O+S73uu8Bu9aH2Dxzgd3ddvc719O+jSf6TuRjka72Cu/ku/TSeNDs9jlzSeWTvZd3G70xu8TuEQYktUYTzeOjsbScSJfWu9IZoVGf6u+jR37SdZt1Qu9dQaib3Au9EaEpu8Wu8XScMTkou9OU9ZO92u93Sclu8JTtPSeUu+njuEDuoiCqO/1Yklu9fO/fScDu/ku9/SfTu97SaAydqjtTO/gyeR5cTu9Xu/RjtIt2V72du83u9Bu/cO/2RpVu/ku8N73ju/dO8YyfCO/ku+oyext0Hu/did3u+C7OAe8vu8CQBrr1hu+kR1j71KhehWLkyesyfxN3gTnUyc8rnQ9009uOxDkunku9Mye7u+qepwe+wu8cyfq4neN3cyciyevTt8yciyd892e8/Jyan+Kke9i9uAH2WLlfTta9tQH3DD1gzuyjGEe9491ke/P70Ue927AOsd373se8SyCse86yegzuce8AH0v71Ee/gK9YNs2qGIH0EbEIzsWyecqHGzuYH2z6nWztmEPUH1h/1d926u8LPyc/3Ke9kH1UGkye/WyfD/3Mzvae9sztBsxeEPkH28zs1ztsH2OSf5zvy90Ru/6e8me9eSe8os0zt6H26/21PbTEO+ScsIkR92C4OGyFN/2AI7Bocp+AjL3SzuwkPee9q7ETztSR0bUQee9s9S5yfOe/Bzv592MR3enae/2JWD1qGhye8ouSe9BydhFfK90K71UaC/yF2e+BFomifye86R3tjkjzvP9u6BBZbEtzv0oc6ipE+s+ztjpqAGkdztS5tn9J1H2+e+ADtpe+JLf+8ZNx3SH0Rzvb7NWH0ee8zzsr9v1e+HzuZV3Vyfaiez4Fpzvle/FqFae97TLarnDe+Ag6Fe8rzuBH1QCkLzt+qNopqje9Fe8Bx1Ze8Kn4xV3Jx0YWcDT5A/JjyeJqF6/2jsfMpquGlOpXqcere8iT3uwrKcfJx1Ze+Oe/PEO2lLUzsGe/PEOZH3VzsWe8qu4CT3B93TEPF1webGuAvEodnesue8AeCgkMfe/nhcrGBTjlhH3wFeVE6NH2Pe/Le9Ve+CSzSe8Le9ze93qG1e9zjmH6lKe+Ne+He/7wmznTHEODH2V/2t/BlEPViSCCnMiY5ee9H1D+sw9xWodjYwTe97ztQ+/+IeJe/g+9BIdk++5icxe8De9c2V9e8ze9WDtEpCfe8de+VH0/qHn9kVhK1H10+9hHRKx0Pe/Twn2zsZH1ye9Fe/4HMDuXULez4tRpa2OvdzfepZ/jd0EuVpmkreuTcbOEWOQyTdrO4ClT8s+IutK+840xJDsautzjagTfmTcy++oTdl4uS+/sTfAYti+8JOt5Te1n0aLeETenfNQ0YUTcS+9b62CTeaEssBWG+uBYsO+8Rpd1zc6xYILf6+/k5OG+9GfPRFWITdYTfsHMhSwtOtNLFW++CTcpYuOaH9jKsYvS++NCHBTd/Ovnc6JnC0EuUzc3c7yTcGRmJ+94Y2a+9yGtLjuVuv2Lp9KaaTdB+8baYXDt+++hfuy++m++VyErZk+HH/os59ZmTe+zfJ9YILfVzfV+8dTvFzeGX2EZiOTfLHGQw6POt2YuF++vOuR+/lEkR+/2+/fCLkuvt++go4BTcuEtQB5vTfS+8hOjILflTnGdzgLcJ+80b54juq++/9bv5JUt2a+9T+9szem/HH3VFzf6++Mb5ZTdG++D+9gYve+99++7pf64tbX2dCEFOtlTfIOAwvBXovAEuvX1hygPTflTk94I5utO++9qs5zfD+/Ot5hTcx+/Gt5DTeDut9t7dTexTfVc7jhEnDusEtIzYjqv0zeb4v2t5lzdjTlVu21zea+84J6zTeTevPTaoZoSzeZ+/F9W2Bf6++rHwfusLs6o31oB+XYunTmtrxMzy2etzTl69X+zeLzc8P1veumju/utrJ5AzfS+//+9ZYu3TcAKGWutO++OPIfuv2++QrL9OvD++BLIHjuh++Lo3Z+8ZesTzyEesMzewftALlQLdGTlSY3RyP5ev/u2fTfEB/N4pAyQuY2k4vvvmEeujzcGD1N+8Yut8LG04ogLcN++QHFVDLDOsGD2SSyZd3t+8hKASB9O+/twdEzfS++CB8tzflTkfFIDusNuv6NxDTe/+8GD0iWRyjv8B8sUtqExCzdb/Hqd2UB+Z+9GB+czfl+/6B8cB/eB8n++but7/FyB8fuuu++IRHXjv8B/GaXTix4etr+9hREfuv6+8ZU7yzdG+/9U5Kzfwes+zZJB9qzdXYtvzlqB9n+8xB+wc+5LnH6FEB/kB8ExY+zfD++fqV4jsnTcZtyUB/ZB8xcxrjsZB/aRFOzf7/MVB8STscTdWtzmzdxB/XqA+zeZ+8nwyIB/RB8agpev2u+/xB+/v21+9pB+RzcmRkG9wrZnd4su/OZB+ALcJ+85B8BuvlTldB9pzclB/tB+ZzdULEtB/P+/zB8O9L5zct+91B9J+//qXVB9lzegB8mFMSTtDB9JzoJTc2Rk6aUdB/RusydTgLfD+8j2btze5Ot0CQGB/S++VbgSB/kB/XBQDzcDhkKqBqB8KB8AnE2cjx/H/4vRkswvAwzfdTlIiBqet6zdZSUfKrXjsuEtQO6wB90Etxj0mzfgh+MfNzYBgEuk4usO7mzf2zckfPmzcYB+cO7L0i7zdV+95V5kEtwh8S6JNTe5OtPUgvzeBYtkh+umH5evLfCvB8fzf69avLRwevQh8Mh9v+8KHHnF5azcUh+1j5Qh+sh9yJg3B9xHFWG9CB8JLEjFKwLdwh9Ch/fDuaEvtfPILd8h/j++Mh+sh+f7OV+/lzf1nEClSRHGGEvNSVa9CWEso9bAB9a8+lOuC/MhSxxet8h8wB8i+/Qh8Gh/OEv6h/d+/0Rk7Ln7y9oMuuSY3eu+EtjlAtFTKLfwNuiLf2h9fesCLe2tC8UYuh8iLefvf5EraWDaLeIMvWh++h+vA/3o2nLnItCuh9ZtDuh/CLc6Ley29JUAaAsKLd+tCSTlQJBsLcie8smf8nMTtKGLea+uWzZU3KmLfErfdA2y/GM+tsD0mDg2Lco+tD4nKBLI+v0NvWRl4RmQ+tTHP4rfZh/nSQnLfekvOHGk+tRLcmj1pB8a+v1h8th9+LcGj3rOCZoVNh+JTkX++d90++sXB/BztJLcqaWpLdvLfOzYK++R+syD1aAic/1BjKa1VDPipLdtOzB1VFB/BztfEshTlBVhVLdK+sqD1dh+AkvZh/th/8ksT33vB+fLd6+sFTk6B9cktBLeGUs2cg9LfkrcnoqW+sy2LEUAFTkzloV91koIBD3E/c4rf1h8PnvkuuVh9J6RZh+4reh8RSutUrfRktMzzd/1S+sP5c0rdV+tWguzrkJzs76qY9YwDUGktmYSkgvvTNXLeaks/mSArcqksFTn96pE+vvh9HoaQrdxLcFTnaegZkvwR/ej2bB9Y++ZkvJaWVp71zv9+t4R8B+9590xhDVc6vh9MzunYatzY/cReLeidDWktnTm5h+sR+JkuAh+krfj+sQR/l9UGkvF+KKcPUWRgR/creDFeN91Vkt+t3uGap3fczmzh2NksyR+bd6tkuSR/sdIRu3wu16t3F3eHUsAmuOMmHG8a0txfnKR+y0vIyEKR9MAVPO0/GtX5T40t3G8jAit3dvO0P4ekdDs+3dnE1SEEmhW5PMUtK4AOR+LUvkzlFbDcJ0yR8uc5q5PEnGjZagZFpUtXfeGbDYUtWR/Q5hDJ3BR+3FjIUs4UvOR8zmqHqFAu2vt0/pGfksyR8SpaN5Pf0E2YBbDx3J00UupR/kpIxm+Je2ZR8rPfdfeG5A6ERexfazmGj4aUvGR88JUPfeaUutZZMulMAXBR/D5LkAVlR8EIlxJ2K0uOmt+R/+Dn5R9fnzEUsfUuOmtspJru2qR8hF6mR8/e0pR/K5KpJ2JR8rPxHr2dUtLi4uTBLrdDR/VpvSR8Bzk9mlH3fzR/kMkKlMzR+50kfp19R8rs1KZ1dR/UbADAbbxcYu1Li5nthKUvBd3LR+5RdlR8LR+/kuVR9Li56R+zO3mR/IizU/cGUvcS5n0g9UsmUukjWKYjmUsBu0f92gZFru1DR8UJQx0syR8sMmJvf/R8nR+DR8YyGKqweUt9R8ZzVO5M5R8Rsb+Uv4T1GS5pR9Mu1P0sYiFZR+P5Gke1bi7g3AKvf5R9QwaWPewjz5W/R50K0vFR901Yh/dlR+lFrQp1Pe2fR+j/d9u1qYCHDAJ/cvR/4x8gvcSnFQS6kdD4blAx+HR/c8FAx/VOS0xdLUsTJzXxJfR/2UuLd2M16JPduR/q4GLR+Ozm5OlEb1vkvLquc5jMp1Ax+Ywi8FM30FvA5sx9b0uOzkq3KlPcyR9mZsSFPcx9HA7ifivm90x/jwSbUvH0HARVspKNe3FR9LDLbFPQx/6x9m0t9R8yFDnUv0UsMfFRgi8UsBzmVJZ3UsyR/tOmPUsYyHCcztA99R/gpbvUvQx8+x8Axdox+jRIox8LDk7fe7EF2Z3NR8Hwm+FNlR8ax8UW/Rx+4eyOPemx+Cx8q0uhx9mx8UvcKx+cfFlpFB0vIyFfR5cW9lR+mICT/fBR/aP6fPcxznqtvQA9Ux9XBLGx/50syW9XBJ8x84ayMx8N9ogvcyR8ZT2s0tNx+oun7bf1x8Xhk80vVx8PJMGW/lx89x8WJ0zEiFA6dx9i0vmR/ttvMA9lR/Nx9Zx9qWs6x9Tx/Kl1yx/Jx94x/5x9EZ06R/IatX5Quzme0urx/5p29kt/qtL6rMvfex9Jx8gx/Kl0zx/8x9Pd2pSA9Uutx8Yx/20sYyHDx9O0tq7n9x/ZR/km8CebBx+v0tlm9utp2Z0rx9RiF8/c+R9wuYGReSx9c5670utx9TR/mUtuR8Ngx/R8hzkjuYGvetx80x94Z0Rzmf2sHUuDx/t2sDOmdW/Le1uznVR9Vx9yZ7G570DgtZkKW9AeLMZ0J0v0WfMx/Kx8EAMGMnMp2Mx/6+JbPdFUsYJ+2+KZA/k0v/WuXx8NPeHmgRV2kmjSZ3FR9Sun8Jf4J/UJ+Ax/qm9hSp6EjXUv4zk8J8d71OR9x7IOx96u3dsR1hXPx/n0viJ8mZ3kznESfr0vczmyJ9l0vcJ/55IAJ/8J/KJ8H0uqJ+Cx9qZ3yJ8dR/pvcyJ86VDSJ/8J/6J+L0t6J8iFLBZ0bx9+1nT7060t82tSVJ0J0+R/fSe7A+4x/VANHzV428cJ/Yx/pZ3yJ9uJ9LvceJ9jR9eJ+TiIHTv4KoEMts28q2v+rY4Mtog9eh9aattzmKcoS2/7eYYMthJ9wg9og7omjwMuUMstmB4QJJJ9xJ/c29Yg6JJ/kYA7doa2teaCxJ8y28yvPQdB7Mi9Z3JJ+ZJ+HpzRkAIMtJh8r5d0GEzxy5fdxMtoWDYIhtJf8MvW920f4QMGpMsl2tngJIfdXMvil0EXrofcSMvG7ncPnYfeB+2rA4DAaCHfDJ918G/5HtJ89S6DJ8mMuKnICV0DR8KMsG2+lx+v5FTJ+2zk6x+WffjJ84P6Rff+l7r28/x+XMsOMtuGE6EQRHdGHLANzTU7GH2eMsP2tSfjnJ8LMudWu9dRgpc8GiT+1b57FCRjg/hMtGWtvR+rJdYQJrJ9lpEJHfjJ9Fx+ZHfNJ+7A6xmZtg8Ap/R57khSGfdzJ/vZ7fJ8qMubJ9UPmKHeWMuxzmkzmvlM3+1vd1Rgi+MsnJ892tgp+ufe66g6ZyqWYGMvjJ/PaaefeGMtuzl2dApnEDMvDV21rQvDmrJ9xmBqXD4fcHJ/OfELJ/lg+P+15fGiFRDH1SKDiJvFrt7C6eYmXf1Y+eh4uapcI2nKYlzP1F+fBKG6P0nP2ZYmapfytn+nhIbkzpeSp8ibkTpeMbZiffohfCp+Y+ft+cCp+aYu4f1EbaM2CI+fqp9cp8qs+BP3uzgqJ1Ff36p8RP0C+cf4sJP2Cf2mp8RpcNBeZmKuZ1rv2JPSCp/ap9NV5ap8eP0xvQZJ22p9ZuwRP1GZckVOup/mp8EfP8v0nP2i6L5u1w5e1HS5vf4ZfnSmTgqzv0is8Bp/4e3ohfpqt9J1rv1ep/yJ0s+d+BBIPdJp+uAv2p8+2nnKCAPeB+fnKDuyQEYs9P05p82p+I5fnSkifOrf3Gc+iFF0fd6P3Jp9sZlFf0Jp+Fpfp6F8cchZmVp/Uph8p+q6HSGBxp/mp+XwYr4t4LkEHqLv0Av28iqbJ0zpf9p+pf2Rp89p+Ts8edadp/vt0Zp+0+V+p99+fFp9dGFLs/gF65Yurs+BP29i9MFHgZfilNhqxQZdkv3Ko3Mm7Tc/XRURooPc8I2lwWDUPdDf1553ke2Vp8t2rRp8Nv0Y7wzp/dBc3p8aO8Nf3XRXWrByjuo5dnp8Rp8R2nHp8Dp8vZfsQ5jfMYp3Gs8O531p0xp9CEu2Bft+fXi89u3/c+v20Avcm/FXwXjFEw0vI8/XRWap9uv2X6H3+gEFMGheugmzu1oZ8AItZYvWv1nRVQZ/mp+6eqUv0mp8qEsG+dHp/LZXWf2ep/EZ/VjukZ+mWj1v3UZd4ZyiPwYZ81f3isKd/doZ+crrkZ8C5dp5uIZ9ic9VhTgZ8s5fTdajdIPv3N+dp5vCsCCZ8Cs/CZ94Z9lp9UVxwZ/+p9sZ+Hp+tp8kIta4uif0MZ+9p94LlWzWzv19p9kqyBp9Fp9p5vPp8EYsfp9qZ/6BdLzmZuAYZ9CZ96SmmFPxp+yZ+bv0cLlvQZOf2mZ9c9W0Z9Wp8CZ8Bc8jEX7ci2PfZp9xBs3v0Zp+I62iZ/qp978jUvffc/8Z/mukJc9sFZDleqe3wZ/GuS8Z8cZ+uZ+AZ9MZ/2EtUZ+tp/FJ+pf2xBdtywmZ9ZBcZGTnp9K5cfzk6HOiYuDZcpZ84f0eP01TJfp/eBcfzn5KBgc+NSlcZ/VZcRZ8OZ9LzneZ8Vuv5p/RBtDc/dxZ+Z+Ke2Dp+1Z/9s/XSM0Z97p/RZ8Xv3mp9xZ+np+JZ+TBeoyOBulrc+yLn+0gZZ9iZ/pZ+zv2vp/uVKLv2Rp8DZ9bBcC6E8vIGEOep/ftW9p9Hp/h6Ref3p+c6ywvu01p8m1I7Z9MZ/M/a2Z8FLR8xZM6xhZ98Z+YyMFkRgEscxrILmbp/cZ8bMebZ9RZ8E/hhf1F+efcSoZ9MZ9QvgRpfJZ+r5DmZ+lc9KFFJIypf1hBdBQFFZ9Y89SLmceqa5cedZwcc+GE1p//Z8k8/c6H6GbfDtKZ+Xopi89Hp8yfHsZ+W5cwFtzgrNf0vZ8P8bqZ/p6FDxxnZ9F+f45/PZ8df1+dWpZ+if2k59Ov01f1dn2Fp+E5+SggTf0C+d6PrjZ/k58Tp+hpdl+AenGn+ccNu2pkK8/HtaeFB7f0NBfNHzxYVMCmkDZggEh7ZFf3GTbs7Zi5+/p9F5cI2ki59uYUW8+Wh9mFsnveL5ct5DjP42LmR8+KFmq59o/0vveKRRq5+d5dP71FpTK599dBK5/xhd659eh8G5+z5fa5+Gai65+B89EEdvdYfpSh899dD258m58259UEe60/Bq5w9wBbG4C+JpTC8FZhfe59U/15hc5qg7/DH5ezYMLq7ODZcC8dSPFczX5fKYOB59X0G+5/UY7Z/17/07eQdpkX88dSNVZgKC/R58NZ+N8+P5fdZ/KksXhdcchsZngFdwlsGBvBzs9GzTda0f5S7ZThcsgAfzm9qzP/2GMMDooJe9gRdas4pfI4Lk4FcSd5LZ/f/1bhcfzmNjxG/09/0558UFcZ59BZ8/5dy/206xMFFY97QMhTSkFpZF+uf5fRqyZZmNUjqZzyUIh7a7e3xGvnswN5+2krHVyYMWj5+J59sCfyJ3dhcLtXz/3J/1hdbb58h+sdFcF/bdZkCFd/Ft6zfNEu/8+MLlIPfsC8b5+L0FcC8kyMJffL8+oMUd5/hFckyMZfcERc358F5+ZFdTSncibb5dVhen5+FkuAF9H59D+u95+rZ8kR/RFdXOccp/E/FXj5qh9y+/ST5AyTfjdxHHec1S+8/zd1eKd+8x+8WV4K+9gTdj3NUSvozd13P4F/SeuuUE4F/mTdoxlF++rTdNm2U+vF++IF/i+80F/rwAjevpTcOUGvcakTfoF9gx05OuaEsbn70TeBYtcF8dDtEev9sNO1j1+9l4uf3PUF9+++lV6kF9+++VV46TfLuvOV4sF9RuvG1vS7bUR+peu27bcB/NuvvBFx+9aB/G7bOB+xzcGRkvGFFzfVzfqF82B++zfvBGqF8yF9sPPSF/F+8in4UF8cTdnIuiF/CF//xCV++VuuPBE1+8auvOF/1+/z+9ZxDPtKaF+2F9t++z4tWF+YF9xHHmF8fOu8EsGXaXh+1TeyzE4F88F8tqLR++BF+8pgT+8tzG2SFbB/kfN4y6L+86F+A8VIrQJTeuF+JF/zut7/HJjXaF+ezdL8XRF945fAYtPakSF82F8UnuFTdH++My5AR80uuk4t6Y6y++Muus1Gmg7Jzcx+/TPYB+jIF9ULGhzGpF/KF9to7xF/StZspEdTeUzc4J0/+/qB/DF8AB+11s7o4aF+9etzYu9F/oju1Lnp86ZF8FfNsyAOWAGyF1zfKL0FB/GF9wpEoB//otRPaaB8bTcReudzF7F87TfkNZbF/4B8ERnrF8SzcnTfLF+wh8uEuhxCSmgD6GBF8Mug3TekHFvm026APTeBF+UHtMB8KHE7CCj++3F/KdIcB/Rus/F+0jsfF+CF/tO9Juujn2UB+3F9fTqiB+/utAC20h9XF8FHuXF91F9WqjyB+U4t0Y4w2TKB92J0sBDXjseF8ol/JzdDF+x3y2ut2Ytwl8P+90Ev5z7Ih9tusQl+kzetF9sSiWB8El9fJH+s8SRl4RNGF+OB+NaH5F9ELdUl85F98LHkl/w49mF8lzm+B9NLGl837TfGF94l99B82Rnol9qB/hB/eRHSB/RetL1ZHF/pTciNYe4Ju4slF9acrJB8/B+wREuY/HF958XYl9Yu91F/2NIfutXF/rWQSze3F/58XFB+BF/+FZlB+5Lk96D3F/Ah93cVFzcYh9y8X2l9ol8B9lNB8ql+2Mql4s7F+ml+LTfcl9Gl9RB+5F/6l9il/+LkuVnXjsGF+ql90esKh+EXHjB9pF+NJ1Kl8L4tDF8Bl9zB+dLlfmAFus8F9el+Ul8Wl93zetF8ul8wuvxl/KSZweseF/p0bojub4vWl+UB+hl/ul9yetBl8frSXB8KF+J768h+dF/sTD3B+cF9w4ikl+3F/Nl/hv2tl80TwfB+FLnv8AYl+mev7/MCfZ/B9/4uIEgLJ1wGxnF8tzF1AFgh8WzeuNbJQFch+dF8RVPrzdkl9fYJbzdWl+r2l4h9lTfi3bdF9al8Qtabl+WeunjWrl8Xze5F/xtrXzeLl/ll9eTfEp3kh9kl8YF93t23F9FiS0h+AB8bkPsl+wl9fAuWB+aEt6p3sh+FOvEEBqB+vl/Z/wtzdxHElUA2l/nTcOm/NeuBYtAV/1++vl9xF8vl9/l8QV8aEsKHGoZ09evDTfWdVUJ4Desqh+CZ2MF/8F9So/yDpah+AHEqZ26h9tuuoV+Gh9/l+4Ap0LeEV9QuPu4kI4v6fsFpynLmJh+ayC3LERh+se9DNvBh8XetjlDJP0Oh+eh/xJ/cY5ozkBh80V+PLFcV90n4vmnqLehh9yY4qOAeh+Rh+FJ+u9Bwzmxh/MV8SV/SLeOh/L5eg+sV8VExlph/eksgCB9LmQ+sqV8cR+WLd0n3v5IdEtFh/yRElh91+usMNyQkVh/Erd/fbaV9eku9gumV8sR9oR/XH2Nh+aV8al9vh8WV9hl9rEvKV++l/yksuV+SnBIR+3vNel+JLe+4oc8U8+urLcxvPcZzo+vN+sM8UjLezh9p8VYGQee+Lh8O8V4YIrh/lLdZLl9h9krcjguw8Xi+9qV9OV/mV+tEsYgW1+vTTlLLeSSDw7AEv2dLcDl9u+vj8/JV+kxJ2zujLfvXPuRNhV/Ph8TJ22h8dh+wp30GKOj09h+e8FmV/7h/mcdKpdWDEer0fcsu6MMO8Ayu0O9YxMU6OsicWCs9V8cidycke6P6r0vadZ+P4O8hltK3PYO+OyuqX1UO8EjEp6NMidqctEO8vb0T/vur0Uyd83NsO/Q6e36M2ieLRP1hOrDp1H1V6NaieQytCPNCO+gvNnBPGic8T063NmieOys5GOWiexbHLV+5r2VPP2ifO/sBr0OzJJysjV+uieaVsv6N6O+ENchQWmIQ/yuzV9aO9pyuSX2dr2Qb3LV8qO9fBMhO8CT23V9ZicSyvhGOuO9LbHcmPeO+rGNo18CCt+O8o1+GxOBO+I1806P2O/SyvbhHhO/vV9Fic9u/2CuHClpr0nV+lO97V8ge+mGPZQXc71GGOtid61tD6NM18cxP/r0vr2VWfAb201/LV/U1/w1+DiccBNRO+a6f53PjicdWdURF055w1881c4b1HO8jBO0tqAycnV/Xiei1f+b3yScy1/TO8xyvjO+3r1TV+jO8ymPHifpfxg1/WxNzO+1sv8b3s725yv/r2rO+RcuASeB2fSb2tu/0ssqb3/T3VyuHO8R6e9it/iflytPssW18fWexClm19NGMRKp3T1NGNa1/xBO2b1218k6NwSdjyuHV9YSeqVsU6PoSeDKubX2Au8Lyv+b3S19UcsQu8rKvQu9PT2+1/kSdcKtCx2bb273Oou92192JM4u+YKvg1+Yu96GND6Niu9p+NCx0G70q19p19V6O8u8GJNkScPO8q190u9Ossv6MSSe23PF18su89n0gGPsu/A1++GNcu9cAfzb0UFBvyvhGOku9R19ImXCu8mAcoaEl1/QGN51+z1dq3k+u+o1/yu8MBMj19Ku8w1+hu/7AdcH2pqGB4V6RGuSe8KsMmPz1+7yuJu8vPMxydsKts733Sfp1+Wu/nssqGO5u9Kcub19tSdb1cFu/uKs5GM9Seact8rnhe8BGP71/zGO71/m19b1/o18r19aKsRu81Ad9qGSu+l18f1/119USfB3OH1/MGOP18P6MZu+YPOX19+/uC703183/txe9118J3Nmu9vz2T1/Gu/xiu7e8+19B181u+16MTSeDKsR19Nu8H1/Ve//iddPOjdvPu+r1+cKbDu8pKu9ydj2cP7Oq70hhOMJpV72+18GrGFKvQmMbtIDSeMN8btICSdZ19Lu8RJOqith71oN8Disbu/72fj1+vSc431B18fSd4N+Hu+QLZB19/Se+1/Z71QmOPPP572HKvsN+3u/SN+wyfAmNuqGaN/bKuvu/YN9qN911+SmPfu+gvMR19/u+6N+0MAQ71V1/c182mNourge+IN+BqFQe8jhOcL2K5viL2T1+Ie8auU/ct0yfBrnsN8Ye+36MuN+fbaSmO4e80AcEe+z1TtNdy9uhN8mge8e/8yd5V9o8tCx2trlCOdS9sv734StMe8RN8M8uvA98e+4qtUe/371LCDSvNB88n9D0e/0Ssqyf0e+2gdq2/2gf2sHie9OgeByeoH093H9mOmyfMrl7mNuyfcqvqOfzbMOycBgcae8+rm1N+eydQtcW9tG0T7NfOyc+rkNN/sH2NOeBEMmiea8uVSfXNeByd9nZLV8hvOH1/cpPCRNZycauWHge6akjL3xqvLN/iSuQfMLN+pvPKROzN/ypPqRP2e9UQeGH2lyc2qsjN83V+IWNYl6JqFjN8mR08rmXN+jSeuuXgQeVx2AGkbgeNW29e+QyvxvMgYk/qEBgdNe/XN8rvMPwbSH398t65uIYkfN/L8svN8jSuu8uDe8Mrm1N/pDaMr0kpNTe/9gdQWN1dsXN/D8svolcO/6Sthyb8H2ot+gmAa18zN88+9yqsuquFH3aicngc4DuM+/Z8ubgdIZp6rnd8uZaka1AjStrOe0N9LNt4HEITka1+TvNot8Micwt9Lu5Br2st9vRxG7Z5vPSWMEYmnN+jSsE+9UigfvPr8vqDufnWIt8YQdYN8yuX78teDv4zBPV/fgdEt9w+8XgfUWPPnXQt/Yt/Dyf/H138vzUdsiyOgV24GMj7JmOp3frrlwCzQBapPcLrlUJ7gZntXYui4+aKDR/CQ2iuvqR9pHGSpWoEPaR8HeEWt/SJ0x9i6t8d9DxDnKnjH/EUtX1R/C8rxutRPBUJ0lhwrcnJl90J3yRKUuskpHy5Mxeomt/xLPsJ2XHHo8H6/fcJ0Gt/xt+T3emEpZuvIqwim+ht9ZusC9pbr0RhyEuvouMBt++t+Ttn+JTWOmet8Scnht+vksClg848tyzjR+Jt9e8JH3frRHh86qPfWt8JnFivcxnF50E33eSJJZuuz6p3J2ut+dt/0cSMbc4blDusVR+Bt8a/Hut+ve3Dt/X0F/3cZt9hnF0+09t9XKyYbmox8dt9zt/kUt2t8nC6GK4wPfWt9NnHwPd6jYznGpJ01t/foJoPfbrmioBmlhYPfbt8kJFrJ2Jt9sSg0p0Xt+2MpKPfrRHjibCvcbt8frRbR8Mbny+uOxhmPeLt/s+vhx8Clh2/Hr1odrcDt+geulR8Ft+WayWt8i8FAd+Xv7U/clt/G+uygWBSx9kCN/FwbmIMGK/hYo5IUBrp3mt8SmzRarnt9daw1/HSMjyPeYd+ZffSJ/3/Gv/zpR/D2RE7t9t9qu1iWQkd/+UsVVgl+uEd+Ix/MORAo4riT/p3SqOT/FPt/nrdOt/d29xUvThkEd/adJ2PcEd8w0hexdTt/yWB6UouPftkoF+tCd+vO0LWoF+sg1owJ+wd8UWx+PeABad/HBt/4bmJt9uaxTUvKd/KSbZPfyd9VcVpt9xPe4d9AY0Up2nZBz1E8dBXt+6d9ycQZPeY+HmoCkd/Yjkmd8lVN4b0Vr7LRE9VO1vcLrm3l+lPeJt+VbgVPeevtwi7WAw1Pfi8ClcU2d+ovcO0Rji0lrBMPcA8GzI4HUsrt8MpVid+MSzEd8wlBSd/7ksTrnBkJEb0Gd/xcVY3EjPeud/jqLjp2od+7mFTPfWt+IxCzPcvt9XI435N2d++d9iaoQUuPvj3WN7Iji73ft8K7v3/cYCiug0GrDod+TO3/t+tVOHPezt8jOxrp3jPwTrnd7wo0tFd8ANHcd/4veua6re3Rp0Zt9FexBd/f3eiZnSx5bx95Tn5rUVT6fPdD4CnVaVgK/Pc+d/ft7ad/50s3rlzM9+PcobklEBcZ1Jd/ft7Yd9Qjnyd/ft5V1iN72Id+Hd+/t/id//DkUNnDp0XDhq1aFIUj5PDt/HYV8/fDd9bd9erfft/rd+3p09t80c6Rd+1e1ld8jd/q0tOt8Td/a0t0d+rWOMug0PeYZy/d/KlPEd+fd8od9II4+OGW0ubd9ADTr5Pw997d9xd957tHd9Y+2Q99z84tt9sUmY9+SvdA98CBzvx//d/FT5KZ0dd957ssuI8d9ea61aIZd88bmgTgVW9Jd932MNd/IPeYd/Ghzud87d/5DCxd+xqyHXQgYHEjB8W/Xd9Qd6M3yve2zXBZZy0HYd70nd8eHZOvc1mrf1EVF/zbext8ZB6Kd95vcXrmXVNRPdrd+LcoBvdLd+vBXBvcSd/q9/MA+C99k1bkUrSZ2vd/tEk7W+Rt+y9/I9+M99j0G8Nkpvcobmmt+eZ1W980TxZvcfajODM0A+s98LF/tvddaxJrVdd/wZ0obmW5puvdu98xlFVvcXrmavyOd8+tc2d8NvdM9+sZkmlMy98srE3t86d8Xrn686L0sIbkh9m9vc3qjOxOWJ90d+1a6dMLWzkk99+rZdt/jvemErn9P+JTyZ0oblAay9pms9/F9/ZDml9/7t+rvdJd90ntBc6bvfNx0UeC19+HvcFJ95N8k46N9/vvf198XeBgCRlZ2WDCBh/Ai919902/bVb99/0V999+jZ0998aDDazPt9/N9+25+mWAjgXZJ9j98XeCz98VJ/z9/u+3Jh/j1HyJydlPhiSj2Pq1NgffZuy+cXb9+oVO79/JcX/+b7Z1mYQDW3Ko7Ug94LEGh1FezRao798beTXWM+aLKfe79/3990zkkfe++3X99zlOv9+F+3bYUFfd39/f9+YVPFbDDDM498WMtP98QNGOgXoEos+45JFGg9vFY3d9kIr52+erKuMsABxVgWZfcoPKgd5ID8aH03Higd6MuhDH1NUCT+0QNEF9/Wg+9Xjft6KgVgfd0Cqnd/H+3QcOAD8I992g+b99NDM5NjKpmf9+nVaarJMpkMD+Sd5lgXnmz2VeYd4lrDW2/uMRVnuU99Xg/54ivnvRu5Gg+n984U1fJJwD+C6VvoFMD9wD9JPxWrZCD/LMuUYgtMttrAVd9DH1BjJc99gbT9MsJkvDDOp23Ap80D921Yw0g/J/AnB6D+FDhZH3sKCp8BrSt/nAiQe0xuDIVInd5JlkONCPutQOfMOUxvpJnyQerRs4m4zHdWD9ILfrceuD+eD/O9MeD+tsCrHft3GWXyhcdLsNGlVtvu0nfxZCdvvWxu4M64nfZ8G3NynHdJ8GWlApcePpzKDax9N0fsXq+TvuKkcAM4StyzvtCPtkZqGOPok+JD859NYk9xD9cft+xtBJ7zXCwkdRsPBM7SQgAneApFw9n1ceTJERD/RQfVM5UiKQncmB31D8dccmM4s5rdccU9n5poDHe6JcecSPvtWD/ZD85QeElft5NYned8HVgMxD+d8E5P2lQf7E99HxjvtWD+L+TVQeuD9HHxeD+bHfAFNbcfhD/kze7cdJ8E7D8Hccmhv5NzHccvE+zzp9QeqGFUFPcnfZ8GnD98ncL8GwJGtQeGxsEAQkfu98G/DizQdWD/so5SnfOC20ft2xs3PhrQeopE/D8sftCPuIcSg8eIpGcr6anfm4mzYzQ8dlD8rMeCfswgkQJFI8ceJdyqyLsMSfukr6j9M8xt0GA2nd6PsUGCYDPOkdZMGZ3FOndXJHQj9fQfZ8HHvgenfPD+AGBU8e4i83qcOFCzbkBnfDblcXnXQUjudylE0j/xkfJ1AOzJRnfFCcANBLbnxnfQfZBnfYuNC09qJC8j8pkdYfZBnd5ndmjfBLAij9EwccRtmU75kfCi9d1Bcj/K8fyG+BSGY3f9CdS09Gk9lPj1netkeaG/NneWk86G8/dmowQTnc4JsyZDdnfGwfP06svCBGGFgN3G6Dnf21ONUEp8ebndGj8Tnce8daJcTfv6uMIN1lG41DPJuMIglrpRIqkWj/ghcGj8tk++j8bnf+j9ej8eGG5gOobZbxkOUcAM75xoXndjDNBJ7gDM3ftXxthj/Rj/2weNx5b+CbSmhj9WrxEAO/nfrh5Y/tPncNytmj8u8dRRt5fYhj/xmAjRDxfV8uyVuOGj/RyG4Xcxj9VYQdfvbk8Aa3dfstk9lVNkXer1PbymHftCJspysPKDVj9zUcdV+5A6kY6A4M6VNJnFf3vJd1aUhYzNvVOVmrl3uDj8SJEKVP6VOxsa13u2VPkCEN3uDVOLj/N3tTj9DBJ9TOzj9dAP/DNd3vax+oqVjTOpmBnviTTPOVPyl3gPtAAMddpsPtnj/+rayzOHVOLDGz3vCgksl0L3uiAMPj/c4Nt4O0l1twtHTPFWtXj/MzOSPuIhJ73uA1Pml3ETaq5zLVNDI9n3vTl0/ar/TMWzO2zmHj+35zQPvk9qZVOP3vgT/q4MAzPal1v3sNVMAT9H3tiVNe0oqzMLj8JeskKVwzP6WtVHNBrWSfFzfnCVOP+IZHNdVO7B0M2ywPtAAPEOYIPsJCEWpnIPvIT+hl3MoLoPu3NHq7a0PvIhmsLCaPuDVPsT/zVPLVM3OXEPvZLXFGGskTkPucT9fj9ktWJAPNpkUzOHVNE7bS2HtVO8tDMPu2VN+A5sPs8AN/CokMlcPvDhUdHPbTOopFyx2CPvXDNqT+d4OiPsnl1/j9hVOyvE3xDPiVD4PFl2oT+g1Mzl0D3smzMzl0GPuw1PQA6ET8I1OyvFi/pWrWP3vgA7xMmGPtpAPR5YmPsYlfRlrmPvIhkLLpWPvoAOlFjEPsBzM8k/Pr4S1P+Pt9GES1MRzNsG+vl3C1OhzPnGGr9Uv4O2OUw3egxBf7nBPv8i/m4Cv7k5T+Mj9T575T/hPseiHFT9xPu8G83S6X7mX+IVoWn7nlT+yj9HRBf7mFuJZPvbLuVne7LvXufpiFMYwa1MtyQHM/68daG+qi9xjetncl0XSPcKDbG1NoDpdPt+LM0RXBvLIDajT9yLzb1NxvuTT8HHMSvsEzmxvuLzNMOudd5ukOrzO7j90ENmLMyGGvPvB1NQRXovtj1MHT95OnO1NaO+kvt51N+U6VDEokNqGGGvtPeOjRJYItLT+XT+kLPZ1M1x8NPsXT+4v4o2GF1P9V3p372kPXPs0at7T+MLNTZZYP2HENRxDdDOxzlzfn7T93xJ2vv7PuQOthvvOkPQANbOmjT+jUAj2H7T/Iz85/EXT8Cb3fEPdPtojEmEP2vtJznpwsWvv4z90EN51OOAtt9FzEPBV1y7QBvvecNtNFhvvO1MlokF1N0z/aEAMvvuvtuT+1PshvvQA4Az8gkOE+PVaBz0k71NOVfgkBDPswkPmGsS6KIz/h1M8z+kvtPEP38uTxWWD+UePSz+VD+0xt81x2D+fuPOkmOD8Kz8qz99ANp8FO+PuD+UeOhHjzHeCeO6z9LHc6z+B4HQsOrRuZdXBD+bHfymcRccX8GyRCRD+3RsbOtHHdWmGACCJcf6wVcVi2QeGxtmmGpD92xuj0N3Hfg13ez+PHeQl0ez8FceIpFmmEHsNexsVlDQDO6ndmCvPfs2OMmMGd8nU8kOOOApGUp4ND9T96MzDND80U7QYStcd6PtJz+dD+MU6pWhQkd7JFKmdInelk6Dcdf1nFtCD9OMxvmwXvvt2MEz0MOz9VmHqfZzD8CQOUqCLD/Vz93FpkneKxutczAsPTEeLVxbD9XRuiuvwftf1mjlFMnfuJyE+ysnexz95u6tOMaxvggeXD/qmHjz94ftp8H3iw79Puz/p8lPceUxt7uvinfVz/F1wfD8jFxfD/fRsPYBfFgKne+z+42CbQeVk4o0rAj+js6bz8F9MAeNrz86ndlD/4ywwj+Ts6d2jwj/DVzYj8/EfV50Lz9XAM8xvvz9yftrJH3iwvz/3ANmJyPz8qftXJF3z9Ej/qmGx8lafsbz+uz+AuM+nfkG92w3dxuWft7zDdxumfsiG+W6CxHnyNGPsMPZ6XoPsj+ZT9rM0MLfcj/tHlQuOC8e0i/712EL988d7E5guMyj8si/MNAUL9ZneHmEhL2FnfSG94iA9HnjxvxbtKj91kcnM9tM+oWAVHk68e+ZNaj/YEM6j/61NkmGZmUGGGFgOcp7+8m5gOJtmd8fvxsdRDc8mQXcg5waHxpj9XxtiL92wd0JvhZujDOznchz+2uMvxuGGc1DM4JtqL8iL/vxv6L85gNXxs6L+rDMmj/RAfMQkRj+glyeoyDUd6wOuVAwqm1gMWL+JeH7ncdk6bfvHkcnZyx9O/nfp7V+8e5j8/szzfsmL+p1zOHl8UexJzyEnycMxUh3p70cyrfvYJsm+MHC628d6L/MTTxcMxj938wvz+FgOYi7SskQJsWRBxL+reOZL/+DMBL/kzb8GFNuP3p7vglUXdpL9gJG0XeDFfebrcdOAl2VL/CM8fNmZSD26+Ql1HjczFfnl1NL+f09yeOOzApG+gl3TGHaM/ol3dL8jnN2MEdL/jnPojfLwoh6/7Ff1LrQM+sleQFBCrgnuNFl3TTGx69fbfqFQoM8DL9YibJ68HRnuhb1E8rWNDbe4M+Ik9bL+EM9QAOWzr56+vHfNRlF69SB2uzpUM92mGxeEP098ld15BJM9ueMUrosM/V53F8mN6+TlY3XIt6+PlYon6bpMXNE3L8CM8Gxk3WS968HHnqUH8dMAr9F3KnpP3DcwUG76+7bdTWJbRHVL9WkzT6//RlydOwl3M7eL6+nE+jRsr689xlLj6m3WqdMYnn3s4k2MDL84r8PE8+MFPj68lcQePdanH6/zgkSmZn69NRkUr+X6/1iHNTEclfwhm9n609OAl2zaleM+m8+LL9sXNH5wIEABM/ly29hZNl3/RtM7l/68xn4xtCRM9fVMULYxM9SB0sr+mlfUM8On75THkdMQeNFn6FdNueNFn4ZM/2lf6vPZM84xt0r8wl1oePKr+FM89xkKr84G8ECcRCb4G8+7clRn6ueP8cCr+kG8HTv2nmNdNiCHWr8B2OFT+px52r+MG/FVZkfQsG9AO1ij+svYQV1HelqtEpeMjM/tT/t06+r8TM81VbFeMzdM4L+yVApeMLM8L06xnnLM8dCf5nn2iHrM+Kj/PrH/rMcL90G/Nnmxnn7M+Ki8dlfKi+Ok8qj+TCeDT+Li7qLqi9OreOFr8ZG+K17H3Ly9PFr/1awdXPAec0KcVO0mV0lr+fM8gwPgm1/dMIN1qT2nePgtM7RnuG8wVfNr+zedhF09r82Vdj1OoLrcdMMV3XzpBG+uh2jr+hG8zF09zoRG+Dr/xnLRG+djf86FxG9Tr8rLkAVe4s9hHcpG/OV2GxmmG/Fr9OHh3lfdr8j2brCG2+OKkkbJFkVfp+NfdOFtMq7dsRLheco/trRuc+ME+OK8+2G82VcsU/5+MS9OU+MWV74VeDr/SvB7lefr/2ShpZMLZM1Kcc5GeVeS7fY+PdV3Ab/bZNkU9VT2FG9GVdbr/nZPYU9m7HzldaVdJKdEVfFefp+OdG96Vf5+NfdPQb/km7u+PB+NQ+dEqGnzuBbP4b+ULuEb9jfMoLt+bNsyAwAOnguZ4Dzqyv+uTl6rPMJrv7bOgY7AsOfzsW47jWydXmMb/uud/zuJbOho4p8nyXcaY3X80iEnngPE/ZXy638ctwvdLyX4kebPWhPr8GFbMEolf4nVB1lfa0cN+LuRa2TvuYLtUTlL1Yqb/kb9+NZkb/NbNlfYVAPRLvAa1lhewQOk7OIn0wXnOCdeGPxz9qB2LwvciCkBGZLt0qEn0QpLvVjPCb8B9NGZY0Y0jCA2b/cLvmb+VLtUQOoWnPftUb/hX2+LuMb+3go4LusQNTfZIQl+b/lSwSb+Eb97lLyLswbtYCBgLwXbOrbO46HxAPZXcPOfMb/3bNN74b9OgLvZWlsb+0b+Sl7i3Zhb/RB36REmLvYY1ZhN2Lv/bOs3Z6b+Sb+gPB2LshbO6IBhb/yb/SwmbfuFbMkYB5sPNb9KAvSb/yb9qp2lsNKb8x/l6b//+vCwk+Zig7PY7PCwmL/2xbOvhsjb/fxH6b/5AWtb9eQtIecWb9mb/SwnOb90Luc3Yz/2xbPoBtwecFb+xb91b+GLt4BtwefYj/00VkV6Lb974nc7Nzb9eb+rbMkYBY8lUb9PkB9b8NLtRT+A35MXlWbuTTB0XlUXmki/89GvTDFElfXekE4COz9LvlQser/T/lGXm1Ce/XZaXmVCfEL/QCB6XmA7/ACDg78NCcqG/89F4y5SXl8RsbuejDCI3kZXPF2BGXmiRvii/nueSi/bM8CL8TxA96Bq/D0h1zQt8L8N2M479XLs3OdABqX4kB7NDiHQLvl7OVX174mU7/+rwPQsbCfE/ZtxkkwOT7PE/bayLhrunBuoWnWsNnCfEr28NIxRuORsaWmKb/07+UWYU7+AHNrn3U79s78nCfXzs079pCnwXlV7P0WnPLu17Pbpz7b/x7OK7/y7/Irs8fatb8079olIC3cwhtuWMYLvkrvUREWb8lRsbfYQ1DSb/boWlj8TtHFgMgHMWRGUb/K786urYEmU7+O7/OwNS7/gjHzh1EidkmM1Lt5rt27+v1GFrvsp++Xl3hGzguBbOZGxjh37bMeZc6hvDb+MgecXch7/Khkb8dfl60NBtrurbPAkC5Xcsb8p79iXdx43gPM4B2JbOll7JE9X8eGx4eXA6Ls0pAprGaHNOl7jYA8kmFbME41zrv7o1gQiyCdehvwezpXeojNFeyuB2RhvN79bruDB0N786huWCezYUHrvR10443pjM/huGx7A3PIQtp43kBKoQODbPAo63rsvCHF78PrvH42G7slhs0Y2T7/+HNzbMuoAm3epBvr40KIBh78h79aKmkCf7o0X77RXethvO+xxXf7o3JHKvgu2QMm5fQbt9hs3+yN7/n79JOJJBuj8FfLCp78GjOCvaXWzlHMmjOC4U5B3hB2tRPH78+MHf7/SBsmMG8Nm1Xeubl388NXc0l4gH+qBsP794zvKCcQVnmmHCXdjo1zPNMbtzo1LPNeLtD3th1YmBvh50AVEFB2t7++zzjXdQAP7pmCbuBQMAxzstEkLsgMklNFeQvdvYNmF3aV2jPjlFARtl53gg9ljPMjNdwM5B1FhtMH/qQOlhv0H+gRuIRs0H8xBt4MnMOgGbtgH/bQlYRvX0m1793XcwL/1M9hx5LueObulhB3XmTJn5BvFleJkGSH/PXfSH9K9S/XcVT8e+DE3kQ3fmRDkRvMRsoL/8RDaH/sRvmpDkRvtCcyk/MRBGH8I7+5rAI3nQ7/+r+oWAaH9xbvZPutT+5PvWH8QFA03myRttleHM8a0+pfv5r/KpdESHX7OAHOhPXLh1RnMql4l7/8ru4ukBE/fQNHIdBH+mRslof+H++H9c7+vI62Ru3Qtux4peu8784l5u3Sp7Ov7PxH++H8ZH/uO7aRttRsjd/X4Whh3i+xzh2W3euh1FH+BRv2nPq5cQ7t5H/WLZHCcyrvTo0lNGFH9TzCBnNG3c0fZzXwvQswic0fbtNHKrs5RtG4WJtNTbs9H9U4UYgmm79G4VdH/uwMVRs6x45RVTDEjh3c4X1RuYidnVaMwtzCfzH+tRv6N2z7vuwNEiduvZ3B1kiczH9zjE+ruXNsCUFH3tA4P7H/Dj+RT2RwsgFxVTMJwsK3ko4MXH8zj80zO5wuw+FXH+fOmMT+3H+PH/aVOw4N3H8qdH44OlV7n8c7j8lwu93uLnneBtuiUrTNkPOnj95b8wEvy2FA4PFKFT3stws9p/rTO5mGsXa9wvaT9pz2ABvpFxKzMDwvr3t9pN5KHEPs73vjwuRVO6zNtz2M2DgzN3TMHwsg1OPTNLwtIT+QT+rwu33sUY2bwsP3ur4Nkn+FVOb4PEn/WiW74PTwuxVOw4NnwvYT8czOXwt4T+APvlXYuT8V4M5PMgn+PnnPwu15yL4OP7bvj8Qn+pfN0T/+KFUQEjVPIT+yossT9/H/8ouET8Qn98BuIzMTflZwsZZwMzNnmlaT+j4PwIspBse4M6n9UPsfnmCIvST+ZmGYItyT8Cn/3KzCzNWn8GBvgn/izNaomcPvuVOdotaT9PVP6XYqBu8PtVTOOn8iPsYn/bH0SPs0ucsIsWT9zyHsIvyPspl5cItKPsuAkSIvo1MUn+mn/WzOauexn92zN0n/eYtOzOMn/fdz+T/r4077ZBT95b+TH2hT9FKEen/hZwBkdUj8hxAjPkZT/x7G9PltMnc0/1xCGIspT/x7EmIus1Mcj+3Pnf4PLPnM2AuIsAENUL+nPmHPkFT/OItXPngEPtn8L4AuIu9n9A7/6FIFzP1T+Nn+DcFNT9nud1ldY79KG9K08MJBFjUsnPoEM9T9Nnf8L/aG+CL91hFypZ6vt9zMbn+EEPnzOjT2e1MHzM5HfbT9Cz+hLZ7n95LP7PvJIubn/9PuZwv3mD1LObT9NPkzLObzOxc2DLNbn9fPArzMHn+vn8yENyLPST69wsXLOZV5p/kokMQT7/n90LM+7EQLPnn9/n/PzMegM+L24z8TT+OKFILPfzMmF+8z9/T+ZKGAIkOkONn4ivvnn+02mgX/EENz7bivswLMg6krzMLLOtws/Ps/LMU+UIFZ/zPHn/hXZAX+rT9tz3nxZwX8QvtG2kNV5fzNjLM4X9XT9DLMIXZBVEWvvIX+0LO32Oq+XPn+gz+AovKxisLP8X93nmLT98kNPaninMSvtFBc/Pt3zNtRHnHOoX/iVa3EPiLM3heiX99zOLz0DEMjEO7KFYX94x05qMlLPecPIqHMvvkz+uWOyX9aLPkofGX/gkM1LP6X+GLMRcPIqFwz93n+aX+HEO2LPQr0qX+2LP8otyX9iX/HbzOLMuX+TxAqX8HzN26nqX9yLOhzHIvsaX+kzxYz84vtS44GX8hvt36NuX9cz+6osF6bmX9HefhX9WX/hofC6kpLP5ZMfBc6ENWLN+X/uLNeX9xpWt1MBX+7FxaX+XIvHf6hX96X+gY7RX+EX/ZJq3n8WX8NqMrzNW8yFaVlX+MkO5tPG448PsAvunIsFX+HEO+X90tx9LOdX9AotSLNTnAZosqX/MX8kVEbzN1X9QhcIVGykPqvuoE4qX8VX+9X+yLNhX+5X9nn/rLOTmkr8eSX81z7n8eoX8QpxT0l8z/IONIWlzT+qX90Vtqa7nzNyQlzX+REN2ol5LPzX/jSYdOkaX/DazsvsBX+53ufn/zX84RYu86RX+ZGMF1MxEM0ovqPfrDbJtgdoushc/PuIvteGM/n9iX+fX9fzOLeNBpOwJsDKNWUE5LR3yfLm1VFHXydZSNiiq4GhqJtTH1ggqQKeGm2jL10fMDJvo38E+eCidiiriwpwKMI3+iKfQKNJNdw38YyNd1xBARDifB5bg3+KidDVf5UUIKcw38hKXbK/kvl4JgdciW4eoAUROJ7qdEzGE1wcKcGYdnVyBLxgKe65HUjYU38C3/n3C3K9Yn0M38PK/4VCjgokq9FpNI6rwYdTH2OKXBYc7H2EB6PKdSm0JZNM+QNQnaG12uBfkpw4e7612uBTeiEYdYn2GR0SKdi7umlyI3/U7tMS8k3+GvkAxXLqdt4dhsrc39jK9FpPwfw8KfdcnW39ZfOq7sW388fOsyOm3+iKeam3Hp9UKc9m09Fwk+z1Scrsp438o7v6mj638s7udJWzqeQ39Ityr/No39x5S+Keq38J3/6AtpYe5lwycI8q8yAWNviPKdE3/h39mKek3/E6ih38m3+VFuot1pSONZMs3917uFzEyyhm3+/JsMG22sm2ZSuYeGzXhDbMAu+39mNYVqegn2EynR39TH2GLLBKfx395SmK/NJ3993+GUMha/+TLBKfonuHH2PKeJKc3Zx/sYpKeBn14W3HSdlptusltiQXJtuskdchfodYn1H8AFKfHHt13/l/N6Hsr3/gqfsZuL3+rKc2KN/yVQjBgSft38dKWpa/n3+y39nSf3n16qwdKcqvkQ2zdKenm1gdGK/Mt39KKUqpt160v38apsP39SDZ4SdvG0Ipzp3/Tps0n16/NByPE2EgqfH3+fwjkqdOHuiZz13/YqeeMUcmgHYeCvlQFl4Huqn2dxwFKfx3+abW5KfG61gP9eKe+3/ujaF0N4P8X39jUOQ3+OdEq39d62acTa38Hydz2FYKfJpsIpzq3+iqf3vtEP/L3/En1Fqc538eQieqe/G2pdKr3/MP9oP+qqeoKOiZy6MSo4dz1dzBKrKfiHs0JywP+hJtuOISqf53/oqXtptNG34Ai9/OyZtSP8JqfQP+b5I7392HtqOJH3/w38VeIkAugP/zuY5qcaP/A3DLfM7HtwJz0P9KP/v2bGKceHvORIxAv538LqA8qdW3+hgvMP97xy3/NiP9qP98P8Z616pxKqep38KP/v/MVa/UvmBLz4KOqn3+uxKqfx3+VQWqqfYP8iP8uP/aP+OP/y7v6P96qeQ3+4GFx3/kP+kaoq38260WP+PKdj39GP9Wqea392P/6Av8P86P8OqfYHtbnX/gGToeOn1LOKaa/P39+I4cP++38/eLgP/RP/uDb+qc1BFOpwSqdWP9ahbiAveq8iNfoVd1qfQP8Hn2xqcaP+TjZ9qfw3+EVfpKegP9dn26P/9P9Br7GAsmP/JFAGP+Qa9Iu7T38PSeo32TP+Aqetm15n0Q2so7szP9t3+HX0prJ2AvLm3hvrVqejP/5KXMAvD38jzpZAujP8C56zqfkvnA5YSqeam3XP8qP/P38oFYxAu3P+uKWX38+X2/3+FKNvP9O3+PHsK33heqXP/+aG/P+Fa8/P9uxZu3+la+7yFKOBYnuvm1431fzAMP8KTk9OLVAt9yNAu4nr6+vlDP9z3/MydvaEDeBsyf3kEpTwNwXda8K5+Eu6kXSIacnzbe8BfqdTa+iKHEv8ba85FbGQBgaeSyd5a3bsxAaf/qcx5FsHF7a+kv9YnMCIXba8RFao+oUv9Dq1sv/Kyd9q08v8UEf7a+k783cFodImwVbW1J5aYafOqPiv84af/ZsJsm3IIEaf9W3Xq5p8ckaekH1Z5Z4IU2nv4FZ/sYU5smW2VdCpvnfZuqv8nwUvZsoJx8396af+P8dacoqOaP+Imt6v8Rmb1adkqNznUY6SUqOSH1E+IKadJqO2n2h39pyceRKSadsqMzjG5AqC6nY6/bRLladpnvgFYWwUuEfUQeRP+k68YH1Gv8saeSqOFxzfwVWv8KYA2gtxv/lP99YOVnvXq4kgtHYMpv9znXs3/aMNK5vw2LlafOac52LOv9ev+LnWxvnZYNeaeZv9AIV+af1hJbaf2qMVWIhaeSv8EeI+gvantznUi391MMO5sxv8hgsu5thgtdP8eW0cafkHNB3/3ZsRv93ya6v+2v9fO4zsQS6/NoQ7vOgKb+38uv9U2LfwX2afn31gQ/9acTW1IzbN/3jacJadXfvGv8jnv7W1Dv/yv9rW1zO5DwViv/dv8hv/bv/kgL/yeVv+XDABv9lv+lO4Vv9Fv+lO7l3+OyeN31Hv/Zv+KH37v+ZacZv+Zn3UaeS5sRTlrhcTGvaqNXftS3+3a+Pv+Lv9ygsjW3dHceHpvKvh+PgHqfSuChOIxacyvx+OhfzeytzBNgxbIyu/yuBYcVLUrBMJYdFMFi/sxYcof9dBMIf9LV+l+Owf941/wCtQf/VMGKCu8BE/Ss8BPGVcMhzBytMPXAyuDhOyfpnV/R+OMf9zVdZYeZXpCyuEf+kwHEf+V+NdQ4of8kf+iZVPV+Ef9FcjpKxYysrIlyyswf+g4dfV9O3Gc3w5qtShMLYc/yvkBPyf/CCvtCsyf9g194f+Sf+qVvQCtif+Cf80CtQFaIf8kf9FBF419af/EZbY18UhOmnyWLVUBPmf9bKsCCsP+4AOQcX024WlBF41+Qf8tSIEf/Mf8K7Uk1+tvftoYkxPSf8GzyOyt6hOBHwMyvyBNo1aZyt8hPqa4BKt0WemHxooz/1/b+5Rf+Wf/t93uKt4f8weghf/vBMBf9Jyskf++f8bV9qt7UBqKyv53OrikL+yzn2ghOkF6If89WckdrGKvSf+yKhhKswf/LBBeKv+f9EwDJf+Qf8a+Fg18Rf/K+FJyuKf8tf+LWcLctKk3LLVON/vndDgbBcvm3EOomcKvYf/Monc8Y3xO54fpHif/u54cL+ywysLMH8wiocnnWelf9AAfAPESoku1/NytzOrMKvZKsjf9sN+1f/3bXnss7f+2sge1efWdvEH4Kvwf8B+Eh19GhOGv5Jyv+f8/Br4Aeum3St4Hf9H19W4dnf/LyvQ2fXN2fysVBMb+Gn6eRBMxDyVf/ehPEY0bf8fCtiHEMKta2exHEGKtOBOg//51+Kf8UyAnf+of+hTwxKumCs/f8EN+9pH6jzlKswf/rATuKuQf9yBD1f8Of/QDxg19Q/+HXx618Df9Y/9d19ZYfo/+c19fvnYS4D18pf9dv7D1/Q4cvczIKtmf/Q/9KKvECsQ//T19CoVSWNmKvg/9Cvgw/9af/tfv518kf9x1WaKvfCtq/GUKu62d89wJKtrf/c//nf9s3GI9wA//Mf8m1UlKvy//inwScsy/8Znjvf+S/+WMiqN+b2cXtwCKsg/9q/9pAeU4WgtxDf+Ef8K/+Tf+y/+c/9mf9S/9T1fG3Hi//5186Csi/+aKu2isO/8WcuKf98/9cJMO4dW/8Byvm/+oNeRimm/89+NG/9eKuQf/6//wNdIpw6/8Kf9VCth/8uKuB6m1NyILWWf/cdzG//KKugnG+KuzyuYCUBKv+f/V33JKtCmMRB3Y8a0f8/qq/f/Mf9nQKrf892cph0gf53OXg3HZ4FZKvFcuDh05jB0N+5h2XFiT2ds3FWkuzKt6hMuUvbf8Bfnhj6K//zCuk95vysfCuJtCxf8fAdRfn9//219Rfm2nrDivgXStKuChN9/8J/9GhMwfDdKuT//IEhz/8VBPcG6Vf+1CvMmtJYjLctr//Jf8z/9DHr518t/87/8eNeDpE2JVp/8BflhZV7f8BfmZlUcf/R+PS0vWf/dhNKfLr/89+N3/+6/8z/9jDKmf/R2clpLPYWWcuIl2VrBjf+CSWGquYOd3+Yifl4/G/rGSj/i3/1vCYFNcBY+bXMCMxjskzxf7+mA3mSYTfSjoHAAMib6vA9rPyuLiHJvpCq2IxqNNcCL8IT+Fprgrlhg1TwAC528WeFT3gvw5wwAHVNd93uhAAwpvimYGwAH4ADSm+yGnD/2ibUjJVacStmDKlKrRgASPBHOWxqSts6CfKrBZzvo3ER7S8Qd5Q6Wp0YMDswR06FI7NdLQ6BwCU95iIAP4AFHNdWnOzv/bpvkwHSVOD7NcMPyE6UKVVnZEyDRRsysjJWSf/cnCm28zdDpGflZwOfodEtQGxYzqc60h0tHOfUreloNoAMAsa90V1ABdYHCJzioAKWr5LStvf+xzfW0Ok45BFVYIRNkW6g14Z1VqA/TDDpyACr+WdtuQMNjGuW4iZ1IpfVWOkrE+gPl/y8AEph1r7YbjndwAZhxFTVZpStnbcDFAKIARny1CAFW4UEPmih9MMOt1hVIiaRADFm+zgA3MOq7mkilbOyFmEoSZ9PwAVT7F8AHyqsnXI5u2EB+l5EwFoDif9DwOgchVIAb45zVbxn7BJW+aznQOQiwtXlSb0t9A5CngAyCxkFpx70pNN8ZJWKQUZgAT0AJICI2ACdnOR2WUB6K8335b6Kt1VbEQblRoAfljiDcrLOc1py7srBZzolS0GAG2StegBNTfKVvimHU0PxcNsxnOL2OJwAbZKwqAGyt9mm+1QApu4km8wO04p8B7KO7ADYoCv7ZX2jYwdEMwuwx3Y3psLCXMdCqz80XOnPsbojjCwyyhLTVhGHGBLDbTzuSRwd6ZfACRiOngDN4ASMtUt6b8ec3HKcxHW1NtvvjOjac41d3C/xHDNhrh0TdsocxtGhcQwYcPpmi5z0yBbEcYQBFrnXYjnR+146I52Up32VE5JNLNiALOI6RC5vtquxHDUjt8BV5I5QxsEQBcC1JTwsGf1+QCXACY5+lmNeOwIItQ+I7HtFb/A3xHSVhmCBQ12zRxteXOGprTOftRXnjsC8LUcR+w0zLApEaRyH6YtedaQB/wAirzuqR0+AF4gDTiOKJHRoXActBZjZoud1m405Hc4AageVxI4z9MJBcurUVRxluwwEFzXhQIF+W5ebA8t8ALX6ZEC5VbKEIAm9GtjCVpI4qgDTaIzJHH4AeaAOtAGl9M4r8Se6CefqESQdAEJOU3Z+aLnO0MgqR0KAZdX4dds0jjc0/om4X5AHwgDfWAepHFUAfUDklI4YsMnFaMpHTEAaY0FdAEADNcI60YA3kjncANEVqSgDIBmpitSkASpUGQxpBgCxSOXbDOK/PkwgZYb2gDYmg/xHXQBse0Wvyb30FX5+P45Ki/D6AM5AGyY0KwB9pHJ5xnFfgcURmncjQBBYAt0jrvg0TcKMgDxQBcwgH0jlKAJCUC8kdAYOd2/Na/D3+ThAbbWlBwB4X7Bs/rf+RHAG0j99IgZzkTx6CGRzDX7T/lO44+/5Za0lf+TIX6JT9Hvsy4ApM7vHsXXAGUL8+meSKQdA/Gf+Xl476RB4MgcxgAkBqqPz+mALgD7/y9IDUZDpe5xTX5FXMbr80wBDUfrrxwfc7aj9Vz+B2vAqZp2/X6WyE/t7gBuoAgsfnh51rbrkUdMwGWpjBJyn0MyHO4SpsxLIBcceijl+AMPsq0Jt1Q6IwFb8AehdzpjpSf0gXohVHD0fvx53gcq2L9s46IacOCAZ+AMwgFQQCAwGqEA7TXMeRydTaAgD4E2REAvojgVwzuAr4gC8IB8tdMiAWUM1NTbd7YfwBoMJcSrIyNm/I4A5trrgRQ2FiAa9mwLdioUdwhmcwuEEAS6P0eQ53JEoIBAEAwZImmAOEgG2u4HiOVEAoToh+AIjAYs2ARL0qFHJwZrJAMrAEQQD9f2D5HYSAcklFYo7GwdVbAci1ZSAdrOn3I6aQDDN8XlHarhgwLmCWoMQCnvOPFqWcEvnBw0za32V+IBGS9Pv9vFRyMgHqHVheC2EAxEHKWAKogEzidGx+FBDRNwtzxiiGYOQCYGsi9BCMfn7p2ANCvndfIBrkhTLMspAOrgiPSk3IBDAcRRfnVR3rAGMgC2KOjHnZ82CJuQaU7kocvIBSG5DFfokQ1iaDWUcsqO9YA0oATZAKK6IRQD/WSJEA6v9iFmQCgGTX5GQBwkA/tWCzoT6o5YK0Bds6EAueZkXJH8gFUQDx38U1HS79qYrQR2zyeFbv2pitYiAWPxzou66/NrZydKNBl6tE3At4IGsZ3qSVDALdeqNAKju5anQ1eCg0A+bFtInW1mBkHFLNa5d3KKaC7d1XNTs+1xeIi0Atj5q6vQQGhTQDwwKuFsRqwlhqTHXI58gXbu2mYIdcvnhGOGz9QCIym+0AjshjNBF7u42gYceCt0An43qNAMOeoTyxmMyk0A6xqpwBR9N7NnFGCYzb3RmeK6DSxH7YAVzoBIMlXAxBJmSBgG3scg/YEIFYhOo9AKtyZZPQgDiAoYI9eu9AOOvD+UtgSyiKhQrvoHuExxaUUI2U65ydFxQuPkw2gGY4s1gMLbtHaARV8VOToRHx/oB8XaDROhd0nIToRbY9oBx0AmYlvEcA1OK20oDcWHLWOJOrDALlnwbKZj6WobcBIbGwC2PpagHpvBsZrwOn2gtALpgEk5NZoB1MA8DMojAPJgEIwD7AKNuLNDUHxuRFgESulrByiMAmhyP5S3sApA5FMYBVydBejsPTnHTqCwCJDiCrIbeLitANwOK6wDxM64SdOVcHZnVZgGSqEDLejMAw4lpozC4ApgwC9eawYFBKxG4nRdT4vDlSYBZBtDycBc7V1iCSslXCG9X3ZqgDTkWTbBrp1ZoBmafAZ7u9AJPrBDFNg4BUBmT3JijAPydpowC0cisnzBxOrzAMpv48oIHE6GyILArFCKnvu6L4J2jih74cfJgWwmGOIRzprLe4SdHNPhx3wrfwJq5XAWt6dM2ASQS0zFB4Z1LYBipLfFgIk93orDlq4/YBChTNX9EIVn4+YwlMPYBuJLRwzKObyLeACAUQiGGf3MOAVAUEb3p9wCkJ0AsXFpxDV+zU+Z4b0+4B7MAvWcs9ALmrjWwD2XaKsA7flAM91hgEZNch4BXAFCeATXANyi7ZwCUsm9eQAeAfPANgz6zUtg4BgTOdzvl3APA1wZHZVqWbcAgW/pPALCB7H0FGTOuOKGWMgmriSBbLx99YBjJndeAaicXRgFMNwK4B6sA0gCqX1iI3oHwCf5g3dLX+AdvAL1i6RwDExy/6dN+Abu4A/yZPwDwEBThTMMhAoBRAQEDx8OHgCauTIFv0UyJgE4SIA3uVcA9aMO532ugEC39XoBhMAmDwngmBfgGPG9mzizN/Sf7pvAMVY5JUsy4BCq5XKluggJDKi/PdaYBodKMmllurBjVySbohLeTcAyfLDQgOl77nwCci4BCA78BihmRVY4yFNg4BYRUckpgIgJD+bsJdj4B96uQBAXBoR9gHXq5v1C1Ptc+hJPlhkQG30tGEBEgFfuARqcToQFnCIaE+WCA6UuKypjvgFfwDToBKadChAaw0GhToIICv4B2nzFGlpzAPA1zMID6XuvPAcZ3JYgL1gHnJ04i4Fz3MBAZQgPHgHAICO4BOG3XeAYIgPcQHsAV7R0SmdAOAQvPC1gFgICFEBWMAmM4vqaDVgEKJ0ERy41KcF4IB7TxgGvlx26WxiAgrJtogOEzoNjFwGk46dYRATLAJmgFSwDzi4XYQEaAbvANG6QSFNhEBOCAyB0inSzaHh4J8lEB96udJAVlGWCB47eQtTokiAytOlsvCde5iICV7+eCfYOASifErpb3QD5j6+K6T7eiPAKByb0fQwYyUiAoHJobANroKDp1TeQNCfPxyHUxQxZb+p0y4Bs19I3vu0gJWPoiICyd6mSA0YyIVFxaQHfLhRSmwcAsyeAM92TgGeMVc3Yt9LdZAZnAM9yaLICgAWAFvXeAUcgKbUKLIDA7CqSA3eARcgJ3gHsAVuYBbsXK5AYYgLWQGLICylCdxTXeAS8gN2QHPIDmYBw63axAbD+2mYorDl04BGP7N2eDs7XiQGk84TsU0G5IuAdnIXcOAuJ93oBZL7XtMjCgJ7gFKgV54Bej6K4HqNAP0/Z/eQDfal0IciYFemX3OIBXhKNc2KAl2MrigLhUCHhgcUB6SfKMPmaoHFmQYoDCUBstJbfKF1MExQGBh9gSK65xFU/ORMGJQEEoDSUBYlfFlQBSgL0SBMoC+1anKA3YgFSgOZM7VJ8RXcGpcVVanuD3+GST5Ydr4fDLd/WOKgMDeBCMsfAQ9OdXe7qOUwU+SHZ1dO4F/fJVAXiyU5ZTblNkag62dBVAeSDyeChTfs6tO65TOVAWwgM74zblM5eeSTLSh0LTnSlQEJICX6CZqAqb9gogIvKZGoDdAKrEweO3nW2HkQFuRAHymq4sOXIppKQ79rZbZymWbBcNUHrK4jJJYcuN07eLoEcDXPjqHmZYpxVM7+8MAqHOjNpDKwbp8J5/aAFQCnOqEgPIH56oC3UBZNEO0HlKgOZZIcQgxHStqA2+atbNi14K5oDu1cDEPA5llKgMubbjqlubKHEXdC8ttKyZi6bZUgoBNaAu/HEdKzLXoQREqY0V69KqLiATmp5iHG99YugBjW6VkJF3bNKdvxW0B2sXA7Ko2gKzi6R6N28ob0rODeibo06oKKRcDdG8+gCtAYjvSO/K3ahNjefibL4tDpFwH3rs78dnE4a9PxNhJFDBlYrxdlwiHCMeNepHo1edSZRcnV6L5pIXlhOgK3NJ9ihIfuNybFdAeib3zXpiGM5ZWmkXYTfv3K0rQHe1sc1W3EXZnfiMq3Gi5UIsutg4UXDeLszv2jlYo71AjGz6A5yLn4YwfQHJRdULSw6A89ARF9hxlDpFNI9GBP1SqLoOgN6XLWf8hN6FlpfdAfvF3A1powhKouzsXQhenWgPai4JXY6vce69LdAZ5sCSi6d71v04+EGaV2uomyNditoDKt60sQQL/o+gNt4oRysX0B4wvGHethgMotKcKsv0B7GtKpVihgIi+xrCxAPa4GhBjAYtFxuTZDYQ4ouecXfi0megPAwFkYCcv+cm9LfRieMB3QG3NwCDG1gkIdeidF3Z/LHys8MBCljHeVjol2F/K+nA7ouMERfHAIxgM53rrLk30Br0XRSIhp2hw26FJtW4YP0XI8Ttz+QAwH/0FiZO4t2T9ARO1U8MZdJspoupybB5JtNPV3QEKWMcFWW29UPRrUm2ji5ZRcZLGt8rCPegldgmrIFb0y4uhljX1AIgl203rpRE6ngSsXeWLg0m1G/6SJdhIiJ3BRvejRgIswG0xcnt6wpjDhGDGbz8TahI80YubMXcmYKZgPrQFsrRoEueUXYUxoVgMSwHxAUssBycXEoJlSmx7lZ7717fyzXsCLeq7vU+6ZhKsfd6Mf5LzAXglyA6IfKBAsBw8XAVPMEpC1i5Ywl+sBAFvBNNt1gLp3rYYDONGMSrStAS1gOgS6Vb112ijSrGtAWymzr3pAps9dsTsXGNNtYthei6fRdNBc62A7tvkTCTLzgOYD3Eu1HnOrAUHF3hc7zYCR0BaMJabARHF2g0ITYDo4ug6AtVOqpgI8wHFAU5xkjXtXVNltWAXi7pxc3gB92AkDAbB0yIVZQYCS/ywBoekpgxm1hlSFxcWEudgue+NpXFyiwFtAUqsBtcXdroq9gM7gG1QkC6q1CXCvelqm3YwE0JcRgKaxMO7elREWj0KMYCwsBbQFHrFOdt0WhIhpx0cBq0XFNesjgKT3r+YDu84eksQDARsBQ6wHHYCUOmgWA7Heustm+wHl70/0BMKbInejFzEQzZA4C/LeCabMHAQBbxjTa8wpzouQKbWHAZugOOAp5yRAEuSOA2l+EnvWo3po4CjsBbaApVNvtgK7QFY4DwouO8XaXAd/FzNXqk4DJaW6abBHAbPFz4MYN6EicBmmAtoCiIeAqt75YDgOiGmAx9ASbgNawHNYDriKiCXIf6CoLjGlSVxd1Yu4nnLUhIQlw4S6Mw89U2hFTBhLgdm3wgxqOluM2jpjH7Ac1gP0T7uYD/cBouArgpuZES06blKtOsBg6bC9AMwl2xi4A5ttMBygFRTNpj6HDwG04CSEwf89M3AUOm0lwH7AVF02hFTJnektCV/uLBJdFIBrWA3PepELl2SL970kcBJeAixLhmoQMg6qJdaoSIG8P3AZ3vQ+aIy4DZsBw3BFLAbVCWXIKFRdZsBbeA0xLvsBWBLZKJdW8BP6A2+lsbgL8ZiVRdlcBlenAECuzgM4XqR5U50BB2Ara/LTZi8S7ZAVOnORNhM3AW5gOtnKzYDl8B0sXNzNsRgNXe77r1Oe2fvJZ9QCfvTRM4nOE4kuvHvXfAUfgMGzYt55T8ByluRbfnvgOiS6MXkmgQuSXQV/gdaURiCogUqkuPUwc/AUklxZf4GIsn8B4B9drNlfgPvwGh48zmeAINIZQE0l0EPq6IBdgK4yXXJeiClXzULdJcI/y+arYZLghAM1OjbFFtqac5je4AZ/cWmS5CWMl2isBAtAgXPMxS7z0qsCUu2BA0SoCwfU87S/gD4IQkqXcFLn9gPHQHuH1tdCn0rPAgXELgugIar0RD6tBA4PAbMn28PozAUw1WMh9WHNv+0TPQH5H1NBcPoqPpPhUfVYIH3KsND6mObCnAVx+QN7y45ssoS5NULHgrKl2pwHUECTD6rOA/5PsCl3OApsEDwCBjBAy9AVDnUUIHC2Bq0BWBAuIXJEZjcPpEEDGCBAbQOR0iil2k86SpRWjush9c0xmi5ihzo4pcq44VUJSDAZrjEutq2EDnpWKhAnbNouSCY+4wEQngKyWAoY+jciGE86jcout6IgEIqJr2P1B6wMNJtW+9TUZMMpBQFTu78gVs9WjZLSIgV6vTNb5NgUnxy0idW/+NVy1LeioJ0CwKvU3Xk8HtGTXYjJECQO+elgFMCnlqR6drJkoQ3cWCXeqPuQnTL1anpljaEhnuBAPnQnQTAp3Tc+lIjkfSIgSOqx+N62lJhBsPV1bhOpEQNt1jJt9mziVBtciloUQMW5ZGt8ReCpRAseNgG30GIE4zMj16vRAvepHUQMPULquR0wy8IicaPu0QKBQ6EPd4iBFQsDyluSHDG9wMIoqN6aRAqVwjfd3CTpqG177ueRA8DlEnAITAp2Lci2+j5LUogfr2iMj6lECiJG36ZcYgUnUg2EzZqE8iB0MaYilrTkg5rKPECjEumxA24gXT7SSIE7hl+iBoYsZHjucQPMpbzEDZiBn5LYUCknT0ZvibRlYx4q4ZfsZGsnUiIEfFIaU6MJA04Pko92R47twdhXupHhe4WhcU3eIFT6FWO+OxA5EgeLvQeIEIkDAk6RxAuigpZ3zsAqXEDyiSwxAtxOldxjBIGy0sLGMJpFbK6MxmTjEh8XFM3gPTtBkgYtTwVIaSPdkeO1wUGOlpEQPvQBOUtuSB+JA/clhyQM2D5Ed9USByINJ3Ju8QNFIHaPd6AMJutFeqIjHzTngFxYaimHtLUt2mkwzfb6ox8diBXffHGPtywDfOIEEN3u+eRAos2gnH2ITo6+oQAeofkViMl930+kyC0s1fUXj3fTbr2nXWYYyFM2DAOEZLsPkE92aIGu61wjkYT3PkgasHFpi52kCzWGQMzYL2k6QM1Kx2YREnuIJAwxgMSQMDYLugVBz8/VLaYgXDT2JIGUxRQyBbJAx+lj2Vnr1oVd9ueCgYFNGZqU92TIFfup46WnpA41ilE8BtgGbVQuSSQa+TKln49HRKygh914uKYFJC2mF302IEg8BTSBCtSZ1im45F6e5NgUdT0DPfRyWPKBQhLx3Us0yBLpA+DOvWQPhLTtA9ViBV9QGUgQM7QrIEmHonCmqLANCGqa0RWe4ZgVMZmuJAoUki2QNN26EkCGyBmyA2cgcjMxa76lkD8yBpL3ccgVKIiIzrDkDwPCxOTHUgUKSU994I0tZyBiC0J57sDUH2KxibpPnuhZAw85grUHpe7GOxASsh5A6XviyQMPOb+kCKAea7cP8gtuQNfN6BgU+NAtdLeUCjjkyhe6ZkCyPC7ZAuT2pWnXBPLC0tB06QFAxF7ueQL/IGJkDTiBbidQsHCqQI5+Kug1Cwc878e4gbuQKrEA3PdSyBe5A057hmBVvIHBDksiBF5AkHvqicTlIG4UDJu+oKIEAmlhQMGj6keFD90VZAiEgSNc2zIHMJ13yBwlfHqlnRQJSXQCvdnQKXhaR6luRQLOUI/p0KyBHFAyV7gRQIgoEE99wk6MFAuSlvSBUPOa5Lx/k6EZAmzdJBQKxlhfkDDMKtPfQMgbcji5IE1gV0yBi1LQMChtuhhKaV8Q78skh6UbvnkL2vgFQnp+e+gLtYIHmXeUKHAAUDe06BhtJ17r+QKFmBaUDIsy8oFZluBn919IEw3MuM65lAmCvKr30AoEyzNmk615AlUrK5QOl3rGkD5DaevfJCgeqxVY3wzIC7KBKrZWCgU2QPR4I3rojKBUlA90CrEQM8zqBgVBC4Wb3MRPun+Sd76xUD+SBkVA19wn8USIzpBUD0qB0vfJ0gXkbX/IGpUDcWGeVAqyge6BVeIFqZ1AwKJVA4HgoGQOzNhX0syqBKVAoqgR6w2LIGP0teKBW6/SxPnKQIcoLTixM++wlA6+5ivVFz74vplX7mhwPIKgeqQPSzqBgVBqBS73YagaMQNGoF+J8YABYlgOPppu9yCT5ezBmnA773NlAS33y3kCOFxu++c1A9CAOCNl3e5LUDp++W8gWsFFe93WoFZUEFqBS/fbagWNm0FmB7UC5++B1AgFis2Cg+ICiDomLa51An97rdQO68L3UDTHYj1AlfvoKgOeYop6YtbehKkdbOtgwC3GIqMshwAKpWPupvHbye9AycMRLyFB9SosFxw063zSMssCWZ2dMjwn/mEuzoUUgfqBYNA5T7gDQJZYraehoDuINAlUrItblNQHu5oZOGH5A6gfqjQIlAppgVkYiS2dUCgYDnVxoFY0CCxQuX3VQ4JTQNmIFWEDoA4h5zCDsHAPzV1AhcM8wMWoPcrNCeQOOz4eMtWFYsXDfq3NMy29OjwXM6aB1oPWf2mR4V/e5gfc+hAmoFBEgdbb0RoELXN6KBKNA97OovTj59p4NsfqBLT2f/voTQPlmAg1oX/aENArkkqrQLtB4c0DHIqD/fU5ljM1B1oHCeAlwe0pMI5lvqDmUH4Y519aB+oOfAftjuwI4wm0D0WU4g/XfyH+QTD3jOMt/nYmkVBRkPIPzhhCe0CraBxfxCWgZGDi4H7/UDSaBrqNXVATLQJVKy60DlPuAdA/kHHSQKcPo+0C4HeRzQRKCucAO3g6NEdbS8Pmzd8QgSAKhwauAZHgBkpeU+Dm5xxCjqPwcbemnwA6+Dj5x3Mjp3wdfB+HMzC+DibPzYcZJbN/hm0xHd+DqaAIy2ZEIdfQBpWzWt4NMP3gjruQVzgBSCHN2fuaf3gQ78ANf+meEdKb8i5B0HoGp9MqpmfdAmVhimAO7oG+xsaXOACHZiUtmALoQ6VD97QBSuDT78kWALwQ54Sk2QBpCHObjmVvSp2YgDNm+mQ2zNJQq84yoQ507kUvCtCHZbZqnQPhXLhENFo2I9A+E7lHjXYwxoSl/gBXCHEewvCAN4Q4EndNXOWq5NwYs/QOEQ7n0Ddke+eDL1hkaAOjaRXLMmoOiiHDWfjjgy+2agftgGBMrDJegVoh0qAbOgDs8GD8pZ+gdAwPAYHM7MW6B5JDSKOv3QO1AHuIdCSOnahFxDigwJx2ZqSlMQB6SHWMAbzg2sQ7fMMHEOteDCegRif1MQ7akcZ6BxiHfUjleeUSQ4Gncx8GdUdISUqvQMCQ5mncJP2S+DOwElvQJCQ5cMCHSObDAwIwv/Pwijrb4MT6Bo0dbxDp6R0roEpIdv6B7eDZnBiIwMpH49ucJRieIpNnjvkhylGIP/lKz+CjAkpDiyPzILLP4Ma42tn7HcARmQFqQ5pnd5/yZoxPkfrofzhgpIwUhR+F0dP5gqKP1B36x4AzRieZ3d6OixEmsYEDCcEhAsBDBUfqwvyTX7DBtc1+MO/bkIFMhzmMANncnwBK5/fqfjrTwgV4OKFzkOuFHBSAWEwNMgE2mYqCGn4A/ZDpOzTkX7RMC8JSeEAyJgS9+04IavIdEoKlkAjHbFuBWiGZPIcJxCsTAj5DqImyMgHpMDKqO5X7XJgVN+RkgEQod+pSJEAypgYkMzLcagocxJSyTAv5DokM3tg7Qod9vyFTAxexOG40iIZPzIzwKGCbMgtClKQAgFsocPIBXRDFLuJFAPc4a4odEoKKlHAlDmpKQSgGuWMSUOgibROhFEszmYE/ftDKO16JGlDg9+3DQ7U6sMmBllHZlDor+WqYHood7IBQ37F9Ekg5ELiKTMCViGxkpZJgRP90ccIQQCVbKH9A05geqhwKX5tQD91CKUpLqAXXHSm/I5QDXmBFlHDODpKh36YFoUdc5OAwsA+gdWuy1Q7Cocofyb53PVDlVBQGYGGodwmBxBDNt3GpKVBYHJx0NCGHUxIKjvCwMkcLQQC0+6GxDR6Uuj+0dQ7PMCxmBXtZH5gXp/BFb4jx1of2SLA6NpB2hxLAYxecAGBKkFAZgcmhyhYF8x1wI0WzAvyjtGh06gqUOweveIaHFFgTHBwJYHJuh+pSFTA//Zked2hYE8sCGIBIWJbupo1R1KYGb1JL6BdzAotDn3Byqo57SYuGBZVHELEnTcEkMKIBJ1iGm9SQBge8wJQObywdtmB6BzYyUtUwP5YHBgNslmAIaFVgUUwOrQ6iwda0OQ/UCsftCwMruRXMDkmBLaHa8Ck24zyDSksCQTCXaHI1gV24zwOaDFdMA6j8nfeBmLQHJv4VqtVwmcN/JdVkyM1EU4esC8QBDILBhBumlkYALRLFoEKFVuDG/sJq2jzgMbg2tWVehDjJOx8351b7JFN3+F6rUrStDf0lQZfUVoX+COrbrAn84Tpv5Matc2BFTderVio0H74qbqsdzehrUMchgfQ2rrq2ZQYtWr8FNoYnDf0U1Z8pxC7+GbAlPOLt8DXIa1sDK94hbAgFBp1/QA/4nasBGgEd/UtVpEMRof4hsCnc4Zj/RzVgjXAfDQZP9ANWg7A4JTpFqz7YFmKdYtWdB1f2/uIg2NJwsMJE2BzbAjFOCmwKTYGMk4bb+s7A3IKDp8yw1ageMm+KsCDRT+lWgBtv7Nqs8Bcm7AnChsinGrv4matF2Bxt/A/VsK4TS05G6sMScTbAv1gbw0jMU5vsClLYjynQNgS1rFX+bnsDiLAvinO7ViGTgWf6BatUhyt0cD7VmN/S/YHa7ta2B77AxX5g2wJOtKQKd4OBTx0Eu/v9q1iHIlsCNNWAX9R6JOx8xkoYklwm+KWlDXHxqD2AD1aEplaa4vinP1gaSq2/YEzvEf+WQ7Aq7VnY0H7YFjsD0c4BhUPcTtm9yo4HBKcbdW3OcUdgb5qzZzg4Hd9AWoaDInxqff0Qwa6f0zfqUT/WdgXMTFyU4LsDygIUKnRLVpiORRU446syGg3D/MOhphwMWMrUSdC9WqPjfjgV1qxWTiAP91OBYOQEZTomaXcDrikEClOZHApdHN0p3b1aCp46OBFGrawnDOxDjYFa6EppIOnAwzgXhwN61YjEVpBWmnA8nVi2Lj8UQjatjdCur0Op/ipwPlMp2oNGdWisFCR/pKMQx1aNp4JVOs7AgdADc/wjYHs/VVVO57At0oPvf2s1ZCmFLOBFarDgVkWpyXVad8lnOBRurTvkhxwKu1ZRp5KH+62rbLgdRwN6Qa5z9MuBlbA1LgTEC0i1ZJcDAVOC7AzzgV4p0q4HlsCYtWn8FVlPAFwLB1aKwVBH+DnAwUwqal1Ef5oas6C4R31VVTrFq0LTwtcDZNWHbOHHQIo/0C4G5s4huBvj/CvVsRTlLJDBqdNNWfJZdR/oXq3a4FQP8UuBZ/wKlTkxq3wpwgcDadW/lcZAkDECz84HupdjFOB+MIaPFIdmzv4x6sJ6GaXA9dgWtwN8U69cDluBQurBbgRFq0/gqzcDVVOxXA9+Wtqg0A1YYLNhuBetDUdnGNwJ/+ZAcC+uBEqnZtVvdwM11aMU4X+KpbA7inJzRRO1bncD9AWHrAk7gTECz+4GHcD/MO0CFXbgY8pzY4EnzBwOB9urLyrODwNP+Y36sOLc2qnS2hmHcVO4EpcCwz0bqnLuhifMEI4HO0NieBCXArrVr+bnk4H+kMI9W5ZnaR/sdwIJ4Gaa886G4GeFkKgpwM+eyzCs3VOHVDDoVoM/xS4Gy9QRn+q3A1uoOM/3m4GBM4i1OO3AlQGvoC324EcVwxeB6GbRLVsSLiLU5lcCMhoZFERLgVLwPM1YBv0Kfi1anCjVmrwO6f4pcCV9mXincXZCfPyg4EOvEVYK2bab9gSq8X4Tj9cCTNWZvA7ngabwNs9qr/MUuBNvAxw9nbwKM4FTkNHeBR7At2hm5Hhv4rVatl9C2HQM5/gfqyjeo238keB6B9ddTjbqwkRpZsCJdW/ccZNlNUCwf1b7s0cX+YPAql/uepw14Fx8Cf8OKXAgMAhLqQAwYHTsx2YvCFGBhs/MAy64PLF8DWGP9DPgWBpzz4EqU4aFUufAj97uxX3k8aZ8C36G2fA4TwCsCyANZaJ5PU8YGnYg1uTQBL4FQGtWPeFfAxvgde934aAlAx71OVfAs/biPlVpxpoadqmG8njA9/kPwNFTyZadqGG8i/TV/hzmxQ+5xz8r5A0/Avg1lGnjVf6+GtZ0sVYSbhhpIaxBBqfv91DWi/Ak+Csoaw1gopsDl+BjFOYjpPww0kNY3cCzjWjBrPSnDewOHkxr0UseB9YLfQ1gJThLf5JYNpwuxBVT1/hNg0uzhtvkFsG9f9e/gYW/3sNYg8DytOpWDLrgcm6GJBZnMMpycXrAhQ1q9wOS05hGsT5gVwsOUFlvwNeyC+v8PsGnMDBngcEwzWNZx3EpvQGcnFAQZTwOrf6M2oqDumnJcrTpwa3dgrAqB4BB6TDZOCg/wJutprYMT5gWXoTbBgUwwoEH3v83DW/v9VAQXW/1oNZVk4x3+ghrRAQSBCgDBbACCOycc7/ZphpVGwOFyfv9X+BYdxffgf1gzqlbSgoJFOgRrd/ulGlw7f46MNj+84HA05hiQNnSlaiCDxtOexrAIfC4JFKI7aGs+BB8r/LfgQE+glf5aCCuVGQAg5RhlJnloEFFGsGYG23KPN/uUa1Ezw3v9pBBKQ+LAQVd4AkEH+jQgBBkTDIrPNQXjIYYCCCNBBBmDVwQfAqmS074CDfE4+2qcbTtUiC+riDc4l3+SE6TXxpIIKXf442xB+8vgg1MFh0a0EEFRv833MFCFTYUGvwPP4HaCC9mGJ/A+wQUWCziEHWCCz3+kxrOMwje/3CEEWCDL3+5IyTIQfTr38EFFmFISqsWDbwQW9XBH4ETYNqIuKmQIEzp52Wttqnad7jWRttC7Tk0IPES7Xad3jWkWFO7TrLp0FwqCRduLW5v3XseqRL06EEfacYvilNjEPTvhL2aEGOtd62uCuFMmEIDpymEEJvZuF6vunbt7NpFwh07Yms5XsBOnNHtkZFzh05NCDWS8IbXdmXmZF27a6Pi8EOC6OnOYQd29jsi6bi8xXsxOncYQepFz/Hp/i99ySxOnJoQZBgH104dCC7/uxM9EU1o8z2WM5zS93hBpbXEE1n5F2Jnq3S9You2U9Q4QYlF254a7i96ouTbXBcetfSRWS6GWtIRBclIYXTpSXEvlyUL1ApeCIgsXThnp3Ki45RcUu2kIgjZLu2azBEHK6d6PidwgtXTsD21ai5C19sRBL6QO7Tk0INSaBk6dVhBViXB01mpNW8M6Ndl5qyohnY6XgyIPG65wS9aRBnHXf4QdSIOhEE9RdXdOplrdaLo5PQhEHsK42ouWkvBwHlsIKJl4eMkSJ6ukvU6LiYlxMl76MkLYuJ4vMGLqIZyaEHAxcZRBfSvV4QfSIJpi6DCUJTWGQPdPTjnpz+i4GnxiZ66svCmLo7PX307n0kA18LIgoyevoyWrwA3ms9hBcMXCgziMINxi5vS9PkKmMXPfTjT130rI1xc2DOWlZR8nPbL1LNaExcdDOKMvLSslaIKSNKofE44clc9bGXtqIOWnovmtUmSmcXIk1gzF0X05LWsMBmTwg1YQdzF1B64b6cOkuK0XUC1rGIL307tS87NyoYg281pLFyenpI2tjaCyM9PGXgrFxmEHpWs0pewy1RfTpTL2aWpP6cRhBmsXBjHk98UrEF76c3hBqESb/Th0IPDi7yiDrYu6M9JoQXbFyEx71CDHYuAwjN4QfvQW866NiDhxBMmPaZCuvXmWM57CDexB8prOGmqpJz1NZFiD5jO4wg1sQW9LzrEHSiCGu2scXEhLv511Fi5liDGZeJ8XPfTocIIri74McBRBJcXYrrsl2XZWqMGdOjOyyXVBLjfpyXi5xiC3rW2yXdGXq3Fy4FLNdd6Pid8XcbrtbPT8Qq5iC0pe78XBueklLxfi5/iCXZeX8XMRjhCIPfEFqGcjviRyXWcQfXF1m67/CDifu+hnXWXjnF2W64WiCLxBa3XQ0QShIMsM5aiCjxBAbbb41vuINFl79iDdxBq1rSCQZDazAkHOtt2kKo8Xa7ro12V/EEqo8JTWVEgjm1mAjS/EFH6c4JeJEgjcQdPF2bi5hz0BHS2iXIk1qyNnAS4w2tYEuf+nW81nxINLo7YmsH+8eBnbIzsw6RvEFQy8tkKPEghOXh9nEFS4o9cxRBcWBaSQQZ2yCwJJxdQLWd5PeoztjL11V5NGc3rWBqvecQSNL0ES7jdd/xBBkg6nrl1PVoS4hxcwbWnqvHd3sRILYS7Adc0kKbQgrHHt7oR4WoSJckbW+EWYsQQsZ2OEpAk9jRBwkgxRLv3Lw4+IqJcM569xrfyQXdazSQp6Jcfuub4g0KQW3L1Q+KaytTjOAkgwxLj3L1JV6ciCuJBiUgjYQbYlyHa6GiDHEuriFN4zmAnitEGzy87kKniXDcQYPK1CS7py9HJBQSXYiQaVIJckHhDxXeuStrKagfXUESS6vy9j5e8SQLPAGfL3ewJ1SCBe2DUg+pICgfmakEMH4KkuT8vbRIK1INUXpt8CepBOvbdqQV0kE6kGXy9/5e4SfIaQQn1xGkGxk9fF6d8vID7m7n2qfaNJdA7WGdrYZgDEvQAdZrSC3zO/JnHpLlMl0yV6v3sHZOng7IB9nY8SlM452tZkuz5nVaQYn8DuXrUDsFku/fXaPtkA+yhEEwK90JBNCvSUOn8l3UV7RblVl6m5nViQXWZzbtbTxdMV6h5nNZCg+5DX67ADdp4u0k9UJXr9INxXoa2JIX2rkmMgbuIry/tIoqEz+uEDrV6QRre1OkGApcb+u2SQUlelXazhS4iDc1zO5DpK5ep9IKkSBGoYixG0g3I7AoQohMkZGK8sUu2ZnYGQVIkCKkHODd5HWXELe8zvYN1RS4gr01HWDiXJFLlv23LtZd95KV6MCvESQffYS8V79946zOjMg+1Wn9IObM4VIVQUut/bbfrlIkFTgBkDdIlePMg1/tmYr05kEDmdlBuWyFPGQUJWCIdYEyDmZBaSvemQX/1xlkHcgIBDSOSvXlLr+Z2ukGl+kDzOxCvQ/vImoT2kHGyC/BuMSvdmjuOZyVkG8Jd1pBqsgilLrSl3HEZUyC4sCGMguh1ipIIeQpgyDPZBAsgxB1m7IN/M6CyD+X2H0gr8zi46QdkEcyD2a81g3AhXpbIO0J7SK8zZBJ5nP8zt0d3Xp7/nt1c652QPQXgAHUecopU8EC6m3tVauvLnWzkFYD1zq6rBuHIburnUqwC2U8EhC51hIobsXIMsDguC9zDC9KobC9kcN1p2p4XtiVmNmAcyJA0NyDQrZJN+hevbdSOQvwPWLkGS2oJ1GwedRfJKMLzovb4d0Eqe3cLYeQQkL1ADoDyDeVm31PR01mkL1CgbFCEZhuwNPWU1gJe0hSImgpAReuCHZuQbVTwVWbNyCQReyqzbeQVVTzWSK/dAahedIhVeQX1eyZEJ0OIWqevbdL14NcNy0MKRhguqejpdWSnisLyMMKvEAO5BAe5LtVO8NygjZkaBB5BxcgiS0BMLwSEIryF7L2x8gzF1HMLybkE5JZXL2RhhfXEo/IISEIQKD1heChhDhPFsL1UMLwcZAr2WhhOBQeAWx/NaevJjheQaFXPoqms2LkH4B1LhezBhZ9NESN027pUvR7hebqFdTmE8L1NbpkKCaRubkuc1bPSNy+qbD6omRuc8g3BQX8LwGEKaMNKr2K8gj+QsQhzxro0Gp6r21edEkUk1e2G7pIIoBa6aqzbhQQiL2PkEcKDGqeeyRLg1DjTyMMKnRlMReMig8fxDiLzIN7iH93jCZhdea9tzllUUF6Is/t+cWAVRQYSLwmlzH6ZqRepo3GxgXiDknMrrXslA8Oo3G0bqYwIkKDmKCHRu/vgHUboLT0sUGOB47FB7o3PKfvPeiFF4o78PRAraFQkeiMh16E7Jr8vGBTh/TkQA9IRA2YBFsid+Y3jEnfvUl3CEK/6kbCS9Y3BLao2N04brsG5DG60Sg73MOg3TpQ5tSEiVwfKHOG9gNIRjp63FsmHWoiOKJQTUi3w7rXU9Sxuxu5SvmKTXTfrp2w9t6eSKLGzAJ4ZHlRanaNZO6pjdOJQbDPCHG5h08ro+qIZGtDotLgDvZ4bMx3k3Y3YcbrZagJCL03sJw63EuMMXuuNwh8ZD9ZNG6M43MEuti2xeRaG+NEfiQuiDYtrlXSkSyTKCylB2TgSsXmahwmUFrjcBiOgsDBZQesoMO0bjmtkVmZSg02drlSXOLo5JYzxuYRdY5QalI3uLrJhYpi6id7Zc1uXTyDQ6nJ8DlBE/BC+nj24zxFiIrB1ZCLb9J0fGhgEpy4E28OjwCfnKDCm9iRFT5Y+cGs8aaIHlnhSLjkHirTtzH6oKg0x+hjlyBUG5P0vOed/MNS9DT527eLVmFMn6drPD5Qao/Qa54vKDatKOL9RLOHRbC+UHoQNcVBOrPB7gvNcEW57IQNwg4lqfZV+um7RY9hcZcp+8WFRNVPh4/TlIDAqCMVBtZRRNPuUFzOFauvA7H65T9XBOK2cDrT5e8CrR8M6fd5QRqFivT5lp9dYa5I/atLs2zmW/wRp96P6jq9Sd+kJn1wTicmEssW5rPemcimmCTZ54wNDeQAKg9VPjUXEAqBbNl2WyKqZLDzNGzyPdZrP1oVBBqgib+tpn1wThe6h9n6wqgtWciioMBUH3uspn6lX9JVQSyoINy6CQN7n6Pz9D4gIyoPtUFyLxuX6Jn9SzWKKoJ7Z6GTAYMK7WfehOKfkGr84QqC2j2w6fKVQZ3iUXfrqv0fVByn9VlQVTAy9UGzp9oE47qg1FQcM0mXT4c+dd+ixKgzdnkS/XZzp2qDd2eQmcWaSLRn3eUHfzp2M+xeXWPQOC/XtUGa4x1M+ceheXGjKoMtUH0B1b0+EKg+tQQ+n1fZ41qChVBqOXcXQFSsW/Z4R2l8Y82iYf9npC/TAzj3PoM8ut/RYkgD1nyXfoa3F5rg1Kg6IuAWoNg55q5dQUgfr9aDPnFHkMqK2BdYQuGtxSagE5l3tuKllE/0+LX9VamvB/W3UFNqCkM+/VQftmix7Hty6YIV3j2hGfJ1QY9Zn5UFQYUByU7GffHLtNVX/FjxZ9T1BtSAWjPjoFyqqpeoBKc+YeXXcwum/Wy57Ao5s36cX9F94obuwyIDA88dkcx6ggLPuAjR9vDGBcnvuEGgrbniBoPnUENv0YGyZKgtTnq1VWbIRyZ9MEK7juFD2vaoL3lTGf0bVBUN6dTPi0/RuSCzhoYNBqT0IVQT+z2FWa+qC8suiP3ANQfqoPQ0ElZckVBZvidjPoqoK9zJHZ9o1BoEUarPgK8R2RzQaCOOeIxFITCmuoOqy6Mc57RQnmfLTCq/cR8z4eP1GOcPyggbLu/OTE0GAVBP36o2XfjQZxoPgz78aDQNB/6gulBigVwvfo1f05fu8h6GALkxhV7UHrqC6MKVGg1Dnkr93I0ELqC5MyNZwDD+pJoLwH7YaD1U+2mg8tQeUFw00EDwN0QuPGgoDQXxoNj3ZsaCJLCwmgurPlAgzjjwvv0FeeA8NaTQXelzk0HkjJY/OimguDQVj50c0GjqDRP6dmgiNLhFoJD3apf0HtqTGFfTQXDl0M0GxqCxM+SWgqbPh9l3i0HYaCRWe1mg1L+g0F0i0FlZ9jEyQGiNbPrhhUHtwPZ8Ov6oR2EVUHioNvcoVaDbv6oR2CdQe9zxFtKmHZ5NB52fdTCp/7Cuz7B0NAI428RAzQQ8sFa0G6aDg1m8mg9TQUNEztfoGhdYsKBdQA9QYnA0mLAYaDfs+Sf3YNQTJoLJQZjRNUv6IOfEbQVvGHBz6hwMsU8UOfQT+rFhRm0G3c8UygV61Ib+jtoM60HDaCITs1Wgw/zhkflaDRY59otBZ2glfFunoQmZpNaCi/ON2gwLQTN/TniLvqCZguomFGyNLuoLu0FuHsTVBH2g4o9vTnzxC7rH4jNBG2g4Y9udoOu0GBOk9VBPmg6k/DMJg/Z7fg0DVqrygodQSpgxa8Ra88DAufo2blQW8oNEwp77NuU+0Wg9HQdLnzOQYo6Clv6NwPIjtnj/V957XHYCdB9vPQMPm8Hi1z7QGt59+FOgtvgSqkEJ0Ha59UsKZzQC0Li7nyFk7n6BXWylWFWPnv8sANLyk6Cls8bOgh3PpzoNd5SKfNTc+qNuEJgUFVWWcLr5dFBe/h/f3PiP/QgbLYYVW+eVVVFljEXzxn4F2cYAveXP9WkHsMpRl/q4C8pVm2iYIfPgL/XGwDa6CL+eS8ND/Qg2FzQwo/KCddBrmDFPdjXQW7C5haDc8+j+XaX7r7/TcK6inZbzC3/9UvPlxhSiwp+Fcq8+/LNe3+igVwmYae6DlSWfAvYVmnwEgrz5rhcEvKTugrfnpitFVZoIqC9+eVWDKPdjztizC5SaC4/6A/9Rhsh8lHPC626D1DsCegi8Ltgdlx0HdFcbweLcQS3Qd7oIywZbVgE8+m2oAbBgKHHwwof88S9BPoqB/PvnoIXcrJ6Cjf6lRXUI7G7oOxJamMNag8HnvMoVAeDzBBTf/0oC+t7lTNQSoL0Q8r/ix+8+GmDLMOOL/VkF5x/dweicRXffnpnoLpdQkC8wwWkweNv+rgLyswqeYVMBeF7lUdarPn3n0H44V7n6Vug0HfMPoOgK4PH5cg8eegoKQB7oLMjgIYUnTqQ8MS5tldYG//5019kl+0H/EnRicPjg/7QmNMuSiH/HqvuYNRQ/4e6MLM8PaAqavm/oKw/4oN9n9B81fLnRg/oNc/5XV9b9B3H/XzUlfoLI/6sBN1LcNRCD7lmiy3Irw0f9mDG3lgWAwZqY1uljuysb9BblqZAwVMkzYrwYKJLq+SJlRa4u0ANur4ves+P+BXJcivM0ALfiYwGCRP+AJjMrGsQYKr0Yi/FAv+MtfXIgbJ/xxr55Zlkv+PujRgwcDX0NwpsV49u4Dlnc/Gl7RE0/7YGDMFqOn/HIxi3S30/6EGDDjOd+gwAwSowlM/4LV9TlYN//b/QcQWVBebMGDxDB15bV/QVc6ic/50rlBDBrn/CnRolmXE/5CmNkUg3PmcmvieXjhzB9V8mkgmS1OAwVemR/lZP6CPl44X/F/RqTwQT/7yGDugkJtfBdegJoFj/7zGMYCgyX/MQwQC6DS/7CGCEma91fYQwd4zRdla/St2rywQAgQJlREV6kDFf9RAmg5eTAwdrK0HLwgSg2GujqhA3vEP/xv0EVQB6v+qhgzRuE1/ysMG1iRWv+Q+jKcpjQYNX/69U1uv+9jfN/Lvf/2AMbTAU4jBCf/Wavun7QSwGT18T/iG3/S/xlU6Wm/4218L/iMP/PZ5uEYLm/5qPNQ96cEreH/q7XyqMFmKsaTG5Rgtv/rEYKGHhrytJTGWRg9WVv7XwGpow/8NDB9ILc7/qZoSYK7ZGD79B8HaKOvsyyxmMEjGC5jBhyyJRVieyxdQBOGCmjGb33TeVqSY3iqr5/9IHmuceCb/mM81xdItGDKG+dBXMH/uDX3OMGQ/9MjB4f0YxVlYYMF9QM/8n9BRJNJH/rEYJUiRU/8NDBoOeDH/qoYJAKhmGD7jBEqSPH/jcYP+MEc2dPDGwBQZL/nSEw2MEBKtJDBbxgwerojCT2MG0/80YS7wveH/jUYOxQCnGDKjBYyNfOvjcKwzpLVGCKQmTH1Hn/lIKyWsYXGD4BWSXsUX/t8K2JMFC/965WBJg2ZVqCE1xMHS/9/0iWJg7owdH4yt9jufkt5W6H1Ib/t6E3F9ibGCPhWRR/XX/pvZ25MFa/9wbiHJggJVkSYOVMxeKtoBWTJg5P/k4E3pMGW19eVe6KKZn/qXcUpMFgNcAVeZ7EUX/raKzJMEu/8qhWCpgkP/oLl1WMFINdsHSmFaC3/nqE3FMF+LZ4/GrJgwP/k7cUFMEY/8bcKfJggGvmLHglew/yto7OFpg8hrkqYLsMFUNccFc/l6Y0wXOfSRLy/DpFlWjCuQGzJn/zmVZ6hwc/+PfjQMwfsYIWwodZYi/+e2FWgMBL/2LFbfB5K/+8YTG7GhvAFr/5r0kslW7JgxndM3/wWwqu/c+jBM9pdzNJ3/zZuKU2NUf+XJgvTNCbK0EVau9MvFW51nfMwVT/y6Cbq1YJ/+JpgoswZOKwvuKNwM5/+Jpg1Lkn0q0ZMFL65BlWS1nek7E//wWwrv6Ef5WRoTe6ghcYMNME+9N0zBg6RU4Qsf/y5wq3eF1f+hpg2QwesqwWwozmDtlWkleDdiJSB2YZLb5RVG+/Zgw5qq//0aFZyH4P/+lyrHp9hfoKhlYMxc//+6TXYpkq4AODMFTC03lWhpg88weAANiZJMJAflWYoHfsAeUl2vFTwACAPs16QUgAQ+91ZWCoACEm+HEQAHKJgAMULK3o0cABSBgD8wQBYIr7zYo4BmuTi9F4Xr+YLxzKgWCumupWbaCwUK81yb7Bz4ACB7H2NQYAwAL0iYWFc+gBeFjaIoHbhSbeYE5dmUE2ETXFJrK6QX9gERMMUmBOXYyRAIAKEsbAuxOABKETH+AHhYL6b55s5BVWjETNUwTIAIZjzl8gLmuyuXfdUGR/24ibh+xVAB8qrI0wW452VVaL2M4gBXjnH+okYANslYiWD1m+yznQSwRkAJCc58WDAWuz99EsstkAI6AG/Jd9TBkjbGSVkxYOGb6UK5UFAIn5YKVras05lZGStvsKXqrHSVrGsFWwo5ACsw4AarXiwaF2A0AG4tcjcKvDICyVvg/Ro+y2WDo1WzFjGj7FWmWz5Z1OdomyRwAziVi+TSiAHFSs23KVFgsSwXgBB2AFjOc21glBg4CDu/3Q7pKeWD1VWrR/GoAcK11aP6UGCdLBgVg91VvxEz8sFFADpVWjB2WD8lxYJkhbTN9eLBrQ9SGVjpYIAzCmqtogB6JeRIAdsm0MI6g755gBiUTaSLmvAiSbb3N8qcKzAAgKwbxKRXA7JACJzCnMrBZziFYMqAGcQcxY8luhSVvoB82wdLdWCk1WjQA9qwfsAMuc5G4VkhAQ7zTKJilYOEAEM4U3Go42hUiJttVktVZDAD0S8gRg2q0vRB1+LwlWCmIOe1cDw7IVYN6sFLWCKrBFqBaauPNYMGAF9Od0rBqwAwSDq8j2vITB78yDmp1+LffldYN0maUHMVjmXZQMI/qv60esG+JlT/WzeVJPfpZowCPBvDMmDm+hOVPfrwc3esEn8cx5CovRPPfnldxBBp8b8wYigE4CgOvf61gM6qXcl6ipEKavfnDYIvQCLrtPSyN+/UwNoYZ0Mu4q1F0bBJl3MtZmaYXSu7rHNSOSve/G1khWUGIP6D78SCeW+/Jo5mAZyvXZnqM8OSU+/Z6xpDYLwhbDC96bB7C7L6xm66WX36AxFusBwV3e51mEaHIDaI2CSKejYbOmInrtgoE7dU9BDOP+/bn4gIKlhsFi2CBwEKV3MmIhAaRv35kHMTzcw4bAo5t1zBEhYlHNzE4BV3HRdjNySw3Z0xFOOoC4bVwXjrYNggYbC8h02xG7No5k6Pn6DryHNTbBpm7VwXoum2gP4+SxOru+gvWdAYgf3tsF5yR+ruBHtQa7mjYKilxYH8N12zfVPjdgCLklipTXdCuO6btEmwYeu3thoLXdSbBjksZa7tcEUWuLBH9LN+urfFBBJtdy2Hovet1IGNxzROwftdyqF7o5pOD+gMRMdATwf1RRz9CELruS9RUmIsZu29sEDjMxD+eIvEMfGFuyUP7ao5y7B0uzEw/h3yXLsGfb9kfAuDwcXxBXYK0UFreBw+0mh/GlAGwRR0P7eMC/aid6xCHflOLiKhZ8RsW7BK7AXuweSc236pzYpwt2RZ3XsfG3YLsP4tT96fAVZ3dxQb2PmEIquH8lz+SovenwCqLxvAHBMDRPetB1MS2smcyFObvFkqj+vGzdEzg5M2RDZmp5rYWGwnI0DnK0TNOb72Dd7BXN3PDkkySXv2YYc1EVilkbE7dhWUB9u5CnM77Bu9g5ENh/YOUYJmnNX7BMMLMrdltjT7DpvCdnR6gDgzENoTAxk5LDk8HbuWYHIBwTac0osKVnMAHBzF2HmFttu0oNJM3cgzmNnJZ1pEKuw9F5gRwFj+WDgurjElMw9gYhckxw6BpzeEXOs0VFOZsiwcg6xDg6DgMLd142ZEj45qkz27Whwa8MV/sHfvNWd+Yd3UBYPTd3lDbGushw6Mt3f2Fp6rUMACVAB1CKKAAFAANYADsADaEVPAAWmwUAAKOYRAAAAAAlMyfMgAHQAC4bANpqLzOPLvNDdSw2ArgB5ziT0AE6IGwAA0cG45lkNgAAALwlAAHABTsAbAAHhgLYUW8gD8ODI44EAAcRwYo4NwowuYEePMvQAPRwQY4MB4zjAByd4PVxTaALAACKACiABzwA/gAFAABOAESABYbBmwAKYAAcgCHHCLwB4AAkgAIgAFAAG1FjaiwuABAQAy2RFcAKIAC4ABgAB/AAWmwEAAARsF6AB2ABiAAau+QlXPOcSUcE3sxSEKw4ABxwQSAB3sTOODUiAtkwdxwZ44MQgDeODfHBsGwMAAAE4Naiwx0BgnBtyAUJwbiAAicFROCwAAMTgso0nE4IScFJODLAAKTgkAAN7HBg2BwbBiAAUAALTYL0AE6cGJOCnAABGwdEAJI4IAAAiMgAXEAHI4MkACgAB5ziLOQc5GG0RiCYBgAA1HBnVxBVLEpPC0cFyLB8nBBAAfRwW2IBoADGOCGAwthRQtgOY4LHABWODlnB0CWQyNHuhHscEHODHHBQgAZxwaZQDegA8kEynBXjgmpwSmABKQAvAARAAsGwe6au84MQgBgk0XG87AAP5wSuABXAAFOC8W8YYAJFAL0ABacHRODcHiozg+JwYk4OScEEbARAABOBNJwRk4LEpzXODUEsUEBQBLBC4PTABPOCMgAmYtHq4l2rW2AAeODzwAKAACIyiIAG+cElABfnB2hFMFwQC4KcABAuDcQAoLg8FwQ84P2bxQuCaAAMLgyJwXC4InTIIuCunByLg3EAGi4MMAADODRAA8GwYZwZYAD5cHjODVgAkzgm0AJI4IAADCLwdBZwQo4PnOIqpZlHBpyeVRweo4JwO7/IRtHBplAPFwYY4MD8ZhgATHBrjgsoABc4MscGE4EVXBf8aOwivc4MOcHMgBn8AegIUxwfvAAZcGrABKnBfjgz5wXU4J4IANODwUATTg8Jwdy4LacHwuCRAAYzg7pwcEAF6cHouCiAAmTgjNPBa4IoOq5OCBNCergmkAMU4OHAClOCyXBFTgnxwa64NqcEmsBPXBKsAb1wewAFhcF+uDeXBAbgxFwUG4P2AAhuDhXBtLg0VwUM4JGcH5uCunBEzg06ijM4LN14iAAlXBBhFDaasulkYzRrOC3wAGzg9Rweua12cGGaxrXBBjgpfACc4Lu2BORlznB8quS5wea4M6uLNuDnZIz0RXVwWy4NtcHVIAiXBC2JElwc4ACTcFOAB/HBXzgvaAD84JBcF0uDwXBS7g1YAEy4NpcH/ODp3BKqhDlwVwQBzcHtOD5sSIAAQNwQK4NRcF9OD5VcGLgrJwWO4Ji/plgE4WEzgAA9wbqAAJcG3gBbCiC7gp1wdm4MpcHsABqXBzLgzdwV+4JAAC7uCN3B+7gm1wYe4P40LHuDfXBp7g0fEue4ILcGXuD2AAQrgkVwWK4IrcHsABA3B1bgqZwXaThAADTODYKq9bg1AAIs4KbcHk5ZBQM4WWDVwVs4M7cHZEBu3BPgAF9wX24INFIDuDZ2gprgq5wWO4MI8Gp1ZyKMz7gsDwa+4NncEvODc0Abzg7dwTOdjTcG/uC13BNLgkDwfS4J48FAeDoU82A1YFwSAABZcF6uCkUAEHgrlwa04Og8Gw/EL3BPTglFwQh4OvcG2q5b3BEbgxjwYzlkJfy4uCX3Bt4AZ5wR+4O48HlOCnAAFLgyeSlS4IE8H/uD/nBIng4DwZJ4IA8EvuCZPBcYASDwfJ4P9cGoeC4PByngwVwX04JLcEbuCy3BCGwCVwZW4KlcHsAAZXBVQAGZwY8tQbcGDOpOriomcXZnK24OHmybOCtNg2zgh6VBo4OIIyseDe3BxzgmjwbbADo8HDuCzXBwQAJZwRF4LEybfxo7nBlHgtjwfp4MJcGceCo0ARngj5wXx4OlQDruDbPBVng4zwTu4LE8Hgk0pPB9ng1LwdC4J9cHOeC83Brng/lwe54KvcGhuDw3B/kAZZwXl4LigK6eCivBb7gudwU5GU/cEieDTPBdaBczweeAGq8FSeDrPBDXgiTwU14LY8EOeDWvB2bgqDwS54Ng8FdeDg3BKngkAAIh4NLcHIeC/PBnXggLwb04Iw8G0pYsPBiFAeZwXh4OVcEReDvSsXeGYjwe24NI8E7ODyPBSXgvVwdR4KpghnOCzHBmXghjwVpsFup7oSRJ3BPbgwpwRx4MM8GOuCRPBK7g3EAH+4L3cHCeC6vB7AAGzwct4IMcGreDOXBbXgnlwRwhUlcGFuCLAAvTgnrwTe4LDcGYuDbvBoZWHFwVO4JG8HA+DiXB5XgxCAFN4Ih8EWeCofBW7gmHwaJ4OcbyWeD6XBzXgo9wXJ4JR8G1fkHrCSngnbwR54P6cEHeDy3BR3grbwSd4KC8ESODMPBAAAZWutxheCcvBWmwCQgTYIC4bJxiFHvBcXgk3TgbdHXABiwpAfBrrgGoMF0AH8ew5wAYrA9Hg0dwRL4Lv5hnlpFRCSKEZXwTCAGfwA0UAzTS6BAQDwTZ4Mh8FCeDqfB54AOHwXZ4LY8Ehw42AAIcOZnwbm4NR8H+eD0fBmPg1Twb14Nx8E6+CRik0BQcoAhdQD1cGk0RfbgQfgrggIdMHN8GLeCKfBs3gwTwTV4Oh8E2+CI/BVPgwPwfKUjDAAh+DnfBCngl3guz4KLcG7eC0XB2PgvrwWw3Al8E+T50gAc2OT/GNsABfcE0UAogAdX5ZQiou4Jp8EW+DKfBVvg8PwXT4IT8EvuCHfB0gAQiZKn4M28EZ+CMfBWfgtTwbs3g08H9eDOrix/nJrxPrMx6DDJeCBgASfgx3wUn4NN8GBkB6/B4ngyPwYhADm8EAeCFvBDfguvwU34LH8Et+DcsMyPgl3waz4LR8HweC9vB3fg9JwTj4IfixIeCefBwQANHweh4NlcGYeDpnBs2JXDwfI4MbcHznELKsf5GByHLaTli8GWAB4vBb4QRLwTL8BH8F+1ZUvBH3gnq4kO4NtVwjuDsvBTbgyqrBK6gK8El+CifBBngknwaD4Jp8Hg+CZvBc/g6PwfN4Or8Hx+Dl/BK3glrwUj4PW8HteDXfBx3g93wV34K98F3uCtNg9/g7IAk+4NjcGjeDSvByCAUnwSZ4J/cFVeD4AhC/gxAIUv4Jj8GsuCUAhTPgjfwWn4IE0Id+CPfBu/grnwd54MO8En+C3fBZ/g4LwZh4KkcGEgArvBN/g8Lwb94PtRy/hol5Asvgl/wb2IC7cE6OCV/BYFAI1wWPiTeABa+DAAhyzg3OGpP1nokDEBCu5YerASfwT4ADB8EpuDqnBlXgoJwd+ABCcFhOD0AhLPg2JwW54I58G4BDNPBYgQiDevvGk0CF6eCinBhLgkpwYeUEA8EuuDDAhgTg+pwSYEMacFmBCQAAJ7g9vwVYEMz8GeeCj/BvngngIVgEL4CGC+DzvB0zg85AMIEPw8HLOD5vsD/gh7wc/4OCACv+CVAA7/g/ZwWx4Pe8GnODf/BX3g//wVl4P2ADi+DWZAjTWCBwMN4MecHE+D53B5AQ51wW64NgCFOAB5/BtXguPwXQEPh8HsuDZPBzAQwIIdt4OCCFY+D1PBB/g2wIcUEPYGI6eDCfB5QQiAIZUEKgCHkuDKAhlvg+gIdP4Ma8F2+CEfBqAQpzwRYEI6cFBBDO/BnPgrzwbZ4J88HiuDwghfPg/wAJEEPlUJYeDRfB13g2/wRF4NdawJgZH/BJHguLwWR4IyCGG+C/PA3/gnIIQtiT/8G7N4AAhhQQjaat61gDqwA+DCvBQwQkrwSD4LN8Fg+Cagh/HgqPwfT4Ot8GAuCkAhkwQxnwa0EPMCGb+DLAhHQQ5YIV0EJ78E9BC+/Bv3g44IVS/iICFOBCKgh43gqoId+4LM8F/BC4AhAIQqYIUt4JmCEtBDHPBbfgjrwVsEJ38H7eCuAhx/g/YAKf4OlcE1uDMPBAAAaQAACiAAATXgAByuCAAAKlI4PeixxBCbvBWmwDOeH6rS5EoxeD1HBxlILRwS8FyuCE/Qkx9Awq8SfwSoEKeCEquDaTs9nyT4gsQELKgAe4hdAhpLg2gITP4NqCGrAB6ghsfgoEIU0EPxCG2uDFQhA4uAIIcSELYCE4BC8/BYXAHkSi9MnlCGl+DjfBFfgltYFX4MaCFqhCsQhdQQ6gIQ0EO1CEOhCQQhbHgsvwXwAAE0KGhDMAhJIQ7rwZ74NNCHJwARPmcoQnbrAqEK6ABKhC8/S3wQ1UIeCTQmCEIBD7Qh0wQ0DwY84P1CHDgAfQhW/gt3waSEM88GYWJOrizsPOrWv6thzgCJ+CSuA0FgZUIXaEOTcFVOCYAh85ADNwXUACzcH+BCNvBRoQpYIRwEJz8He+CEe8DjuW+xILSCuCEVIBx/BpAQ8MMriENn8FOhCcQhi/gt0Ic0EKuADqYBx/BFYuVMIZCEKRcH+hCGwh3QQ3PwVmEJ5CFbEBbiCAgqUMISv4JBgAVIBiwhPYQ9UIb+4OdCFahDGXBwIQocIRngBHCEt+CxwhtYQ30IcaEJWCFzhCg4AY4XRWxEuEPzCHyBCVAARYQyMIVP4P0CFlhDfghTIgSsId8AGrCHjhDFghUIQjgIasENg2DrBCUPBWwQnYITM4NI5zsAAxfBzwQtfrFxRmSCEduDnvBlwQ94IUc4MNcG3BDB3BeQQh4IQUEKsAAQRCl+szHgsoIUD4OGCFohDRghFTg18IbGEJoCHxhC8QhiYQgkIWt4JrCEYBC0whWAQjMITYEPhCGr9ZMIhBPg0UISQEK+CFPhCafB5PgzcIa0Vn7CHRhDSIhDPgxgIWCEMoiELBCz3BZ4QnrwX+EMGcFhBDKQhvAQ6kIWd4KcAAMhDmQhQvggAAAoAABBOVwfSELV3zX+D4ghEXgipCOT0gh1pSBDUghQoQjqACKEPgiHEKBSxYVIAWzAJKEO+8Ha+ChJgdjzXGpORwDDCHOOCBxcYfggcITGENr8GTBDnIhvEQhgIUmEPDCEGhCTwh1EQv0IRz4NEiEXhDwVA1UeWyIbeEI9CHWhDOEKHmQDcIY6EI1CHbhDAQhu4QnUIWREOCACehCTfBbQQusIT+EJNCFBRD8MgHd3UKIcxEOTCHrhD3IhvYQ2KIdxEJIiE4hCnAh+UQtKIaeEPrCGZRDRAhQkwTknpe4lrFwFhD7wh5wAJQIWxEK8cEGBDywhb4QnwIV64L8CFfhDhIh9YQ7PwTOEKbCHvKBhuYDUQzIIQY4I7CEt+CuwhUUQwqIZxEM1CHxRD6vBiUQviIRNEMPCFeaAiQhVUQjKIZz4MbCF4BCLaSJ4uKSwK82HbCEEuC1whj4QvQITxEKKiFbhCSohroQhMIctENH8En+A1ohlUQvyISJEIDCFZRDC/SVbqHzAAdEOMiEHhDCwhLUQpyMvhEOXcEdRDXwhxgQziIbAAE/CG+RCJwh7vgskIWsEO4CGSRCIgh0kQ8/wdEEN5SIaRDuQheCZQ0YpdbnWcEpBD9gAaQQrtwa94Ko8E3BDaPBDnQKUIehELv8GDTYQAhLHg4gIaiENecF/RDqghlXgoiIS6EISiGDhDdQh4HgwkIQ9EPBiG0RDtohvQQ6hMmKgQ1USf+D8XBFMQrjwVTEIxCHTeCYohF0QhPwbNEOQCGzBCmAh4IQlgIWz4OqiErBDQghGwQmGIUBELhiH8BDoghFw+MCIQcENqiHaDkY/Qw16aCIU94IS8F7OCrgh2QQ/GIbgMEJiFFBCtYhOJKLCIYMEJwiGfBDIAhUYQirwau4P+CGixCzohjfg/iIczEKliHtBDJwhAUQz3wezEPoiHmxDWUCWnAK2ITO4NwiGUxC7YhZPg8YIa5ELjCFXRCPIh0nguYIetEMeiGyxDRIh8sQwCIWh4OViFRBCnAAAAAORQACBAAigA6kQ9WISIELNiEkNoaVsQzlG/bAKEK2cH8cEu3BcU1RPwdUgBzPC2FFJ8ApsQjaalktm/Jh1o5sdIPMQ19wWdAG3AC1xCNSC7gQwiIRHEOIiFRxCyohI3gtwgDSADjiGsxCpwhg0Q2EIbOEM1iGFxCl+0J8xP0pHlEIciGdxCBYhtPgt0IbTEJ3CGLRCGYhSUQ/FwUPEO9CFgxDvwhnsQzoIc9EKniHtGUZ4hZ1AHEJPPEMJcHpeDAdaKoQ0qIXNELiiHRRD3Qhjzg7eIQ9YT6iEweCnohv4Ql6IY3EMxWwEthA0ACoQheIT1cVPVr3xDV4hC0Q2HwXuEMZiGvuCn4hI8QveIdgELliHc+CJIhFgAKkIYF4JpCHneCpHBYRlPOIZpEK02AClAD2Ytm+UuIXL4M0cHkeC5Ah9vgoxwQaKW+1wt6B64h85xTBIbY4IfSStxCnHBLgQh1waHEP+iEvhCjAh3gQ4GIaDEKoiGjxDrAhPsQwMITdrVIvTKODgU4zEQ7QIS44IWxJuODnwhqbgrwIR64O6iGZuDeohu8Q/qIZtEM4CFQxCKQh8CQqSIYgkJkiGrABBAhOgALkIYcEK02BANULMCKjgvSIZjEJkCH4JDA4hX0Q9OAIoEKcjIoRCLHBP3gtMQOrwDJ7wUupxohhTggRIa4EI7PLuBCAYhTCQ8RISwkKkSFsJCoEhArguiIVwkOavDY953XAdiQ21wQ4kLoSFtRDSwhoiQ91wZugHfCHbABWEhQkQ1+IbLELkSH/hDoYhiiQ2GIcokPhiFOAAAAA6nAAGsAC5xCQAA4EQ+c4vftggOzkrYVsAeiQiwABo4MvQBlJDHAhhCQ6uIde4EXiHKBDLIhqgQzq4gUkOLiEKspz4hdQgWpIaEkOXcE9xDHYhdfgsWIQ/EPsSHOODn4h0iQuJIZtEJhCH7+DJ4hBcQkIAI5S1niHYMxPohbcQv+IQtiQASG9JCgEh98Q/cIeAkIGSGQJCZEh+8Q6EIYfEImSFNJDT4hDu4ahIbdgDaSH/xCu4hSyQ3uIXTEPXiHXRDPIh/SQwlwYMkM8SGbJDoEhgUQo+IXskOKoDfxDWkhHcQk5IUvEJr8HdJC3IhzsQ8WITckOHiEsxCvEhY8QkIIbAkIViHJJClYhqSQlWIU4AGmcGyYANEhR8Q0I7Inemi8EznYMYhpSQi4IQbENmSFGxDL4hJsQ+pIdKEIi8HHHZbnBZMQlEIcHEP5iH0JDqYhDsQ7EIU7EJviH/JDIXBAkQl+IYp4ITiHexChohO0Q647OcdiYiGzJDivB77g22IR0kNWAAcRDhYhXEQqlIf3EJdiESxC6UhQyQhlISMkIDCFJxDefBKcQqFIWnENWACX+DZHBGsQiZIdp5VoGjIpCn/BMEQ/WIRR4LACEpeDEIhxsQiuQGQkPxSEPnY3gh2qQ62IVykJGCFkpDePBFKQvsIYKkPpiFXJCY4hksQwSIRCEOBSFexDpwhE8Q4aIc6UBvOxG5ZsIhQcQm2IeakJ5SGCxDzohAqQnpIX8kL6SG0pC3YhjqQ6WIdv4JBSEJJDxIh4KQhBIad4LSSHypDGAA8KQiZIW9dhc/S6xDzghsEQjFISakK/8G6pDsUh+qQ3FIUTEP78HbjVLYhzEQvmIWV4KXiGdRDlkhvSQ1ZIYj4PmCFOpCHkhbMQ5lIRzEOEvK/qkvUhRiQ9jwSSkIrSEWpD/Ah4cQn5IZHENtSHRxDQQh4aQ+lIen4MZSG/hCpUhmwQmVIQmkOhSHypDEYAKaQhuIdndkAIwZpCX/B6KQrVIa3EKxSGfeCTXBhaQ1NIUukMzqxEpDwAhvqQvCIT2kKrSHnJC14hICQpaIdckLDSEURDR0hrAQ8dIePELGSHupC68AJd2AYIWWkK7SFkBCl4hfKQqgIZdEMHSEDxCRUhI6QsVIWOkIlSETpCwUhycQgtwcBEIv8E4QAF0hxMQtR7GjELbcGopCsYhL3gj/wW94LxiH5pDxcgBqQ/AIfA8Sa6jGpDDkh5aQj9ISekK6SGUpDg0h1KQ0NIUzEJvSGAZC70hwGQh9Ib34N8SEAPEewC3MQ8mIe+kKYgDohDe0hmIQ79ITakMuSFDpDXYh5GQ+5IcMkK2SHsBDIYhiSQhRIfGkIF8G7BDYUha6+XJIUqkKbcE4vZoAMgCWM4IaukKzSHrpCUMheaQrdIXUkPyCGWJCkXscwIQlId6kN5iFMZCVIALGQ09If2kL7iG/pDhUh5EQtAIRGkI9iGPJCmUhbqQllITC9mReyj35kQhh6Qs1IcekP9SGsZChYh7GQ4jIUKkJpSFkZDzMht6QmWIVRkNBSHkhC4EhImQpBITCkLaMJ5JCx3BiH2KCIXJkJKSGIZC4IhOaQvrwKhkNUyE6AAMMhDH2VD7ES6lACG4ZC9Mh92AAzIYRkOtSGeZCTMh3mQ4qIg6kL8yFRpCXUh1GQuEIbRkKiyGvpCOUhLEQ7lIadELGCFsZDq0hIaQ2tIbHEKBSGNpDo0hYkQgCIdKkPAyGpxCxMhfaAaDIcWkPh+zppCYshCGQtdITjEKyCFJZDcgh26Q9TIVZEI/wDDZDSghHaQzlIWN4JDiGuZDDMhRGQ35ISRkNayElZCKMh/mQ/jITgEM4SEfxDofs1/+BjIcSkKPSGrZCGshYcQprIWekOASHLxC7Uhw6QnjIbEkPFSH7ZCYEhQWQuNIUokJnSFypD2AA2HgiTIRFkMwyH2b41Uh8mQ1IIeNkOQyG4xCVMh02QtTIahEI0yGluBwt8paQ2rIXhkOYyGVpC8shxUQjjIRekI3iE3RDr0hvmQ3bIWVkIPiGupDH0htmQlQwD39nbSFvpDzshpKQ1zIV+kOayFbZCwEhdaQjZIXxkKsyEgZC3shYGQqtwX1kJmcE5WMkYhmiQzA1iikCI8GjZCNUhb/g7NIRukKmyF3BDzEhjwQotIfgEL8BwaupMshjGQ0nId2kLWyHI5CRYhBWQzjIX+kLMyH1pDI0h6YQ6NIYdkKPiFeA4bwCBEcJbIXVkL9SGXZCKAh12QozIRckLRyH3ZDuMhWOQ3jIc9kPpyGCZDY0hTOQ/nwaFkPlSEUABBsh+AQ/EHPd4J5yF6xC+chSmQsHIf24LQyEHOFUshxHQLF0J1GklyFnZDnMhF2Q6+IQREJpiE3ZCVkh1OQtrIe7EPSiEvZDRkhNGQl6IRTOSN9gBxCSchoeQsnIQbkN5SF9pCNshA6QxXIaZkMxyEq5DLMhtEQrrIUkkJCyEqJD2AAQvgnJIX9kNTI7385JKg62NIHIfokNZa7pAAvIATOMK4IU9qV58C1goNfBEnAf3IR13G7RQHY1y60rcQ5vwU74JOiHh5DCshHmQzbIV5kNIyGGODvuAI+QuPIRtEITyHWZD8chLaQtHuP3kKksACEgA/BK/g+5LGv4Iq8yj5CSwh4+QynIVPkNWSEh+Dx/B6/g+fIfHEICyE+JCXohjcVfJNFrYkHyGJ+DZ8hrfgvfIYAkKjyE1pCwEhw+Qp/IefkPYSG45CKsh4yQxRwdOlHsMDNEph/Bifg7fISn4OfyFnJDjch56Qu7IVxkJWiGgFCJ/B7WQunIU2kJsyF0pZJ0hisQ6dIaJkJmcG6lZ2chCKQ7zdOlpEByGxZCQchgSQxLIeDkKFyEzZCochc2Q9CAC2DjhyEJZDO0h0uQ/DIbLkMjyGQFDbshtvgzeIcVkNFSGW5CgMhi+QvHIUnkJwKFUFD2UhNBQ5bIdNEJyyGfpCc8h+WQyfIePkO2yHsFCnshnBQ63IYFkPkSHBZCPshGBQ4Xwb9kKkyHLODtIh2AyJwQrFkLhpwK+ClfBHKQyzWE14nV8EWRDZshDSQ37wWpPQ/1Q+NYrghKUQm0IV8kOBCGH5CJCh7+QwiZKOENwbylZC1ch5WQvfwTwUOVSFmFD7DA6/4YAoVvkJ4KhgFDWohWeQ03IRJ4LsKH55CishJ+QnfIZu6AsyHx5DZChV+QzXIVHcxoaQWFDZkhVhQyKIZX4JfyFMFDo8hrBQj/IRCiGiKEL5DYihGuQiZId1tyDYSywB+k8m+QwhIXAULPyG/RCe0h3yQ3PIcZkLCKHT5CIihARQ3IoRfkK4KG/5DOosqBQiFIegUIdyHsAApHB+wQ/OIRtNRLtDLpD3chuCQlCIDq4MOiEKBCRGA7SQ3vIWf6Fn6xqpCtAh5iAQRIU5GUWSHQBCXEhYiQyJIRIkKrCEeJDpChlGQl7IXEUImSGzwIoCMj/g+YoeGEMcSEMRAT0hqxQiJIVMgCiSHOAAYkhDaQxAoe54JjSHdZCp0hvWQ2VIbsEKF8FYFC0EhyMQxqYOCAJbI7I64cEh0gQ9Rki3kN0KE0FDq1Savg+5ekYUPIKEmFCtD+CVGQoQDVWF8KHhRC3CAqUQwIoWPkPqKGhFDgihSuQ4cIY/kJyKEuFCaIh6uQ5tIb7EOUiC7mp7DAQ0meEobAUP8KHwFDkSh++Q1Eoa/kJayEOFCKihu+Qr/Ic6kJ/yHuFDKshR2QqdXJfUCziDF+DW4hKRQgqISGkLRKHQFCMShB4QrEoc4UOxyGuFDmShexQxdIeyUNyUBxBoyihZJQ4PwRSUKqKGuZCaihYhQvPIeiUILyEHhD6ShURQnEof5EPFKGcJCOih5eQxNId9kK5ADO5CLaSa2GfAoWNkMUyETZCdUhPuQ5LIdMUNqIK3xpg8hTmQlbIZnkJRKGWpDA0h80QzIoRjkJ8yFF5CYihSBQ5fIQSUK1hxaCYashAhQvXIS5kKCKFuZD3Shd8Qt/IawUJpyEIFCrchJeQ/UoYoUO6KEgAA5XBiqQ/ooeQkIURymj514qKKQzVwYcyG1cGhHhDohBrgk5wSQkN/MDTFCZ1irDoXXIdvENrFyJuCVihjCQtYoVcUI2KEfhCtihdxQ+MoQ8UIKKEbTVyyha8VW2AFoEPjcEhJDwyhHgQzqIUDEP5SEgxDmyhquQ3EodYENLyHCZCkyhFeQ6RwVV+UkyHplDOrigxQ/gTOUjkbyGlJCDEhYxQ2ZIbThGLKEXUBNfBO6QgYoaFwieCyVJDH4hCxQ04od2EJESGeBDLihwccRsodEkNHKHF5C2yh+JQ3xIURMD7RiTEd+EhJ5Q3koe1ELrKGXlDXgA1xQkcoc04NFKHjlDgghjxQsvIdOUMNKEplCVChC5QsQIUajg9HyIp5YshWrgyXYBuUJoKGdawdi0xCQncoaWUL3KFqBCoKhpItIgoWskJcCEJuCEmyziQz8oem4OvKE3FDbyhvpQ+8ocgUIDKGmOwyccoPwbCoXG4NwqF9lDXShI4AC4oURUPcSF/lCOChOxQ6BIUBUKnKEpJDPshYmQzJUjXkOVkDiY44Mh/xQ4HIZaUNByGTZCSChyEQsgoRYkIoKEcV8RMcpMQnTIbQUIzyEy5D+yhcuQoNIeIUPqKGSFCAMh7FQvbIfkUIfKEvRD00qW3SYnIfDkOyyHFkAWMhFOQmkoVTkJjKGx5Dmih3+Q7ZIQzkPkKHvZCeKhShQ87wXK4LlUICVCC/cUbgvVHCOLlXKEaODnUI8FQgsoZuUIl8aIRCSyhOKQ4woXikK0SH044uyh/CQ3sofVkMYqEDlDAYhzCQ4cobcULHKE6lDlghEpQ7JwVFUJr2AxVD6KhcVQqkodVAGYqEVhDiKhv5QuMoTIUO8SGTlCFChzlQ5MobCkMVcGqFDi0h/BOYSoTmUI9yHpBD+chymQm0oRDkJSyHoVD6qhLBOBSobrkIRyH6ZCkchjBQ2ooSbkIFKHqlC2Ch2lQ7YobpUL9KEeFDF0h/BOYyoSGUP6qHCFCe0hFlQjIodGUK9KHjVDHshLZQsqoZ1kMTKFVVCZyhl/gucoR5ULjJznE5osh6MQ3nIS1UK9yESVD2qhpBQyHITJUKhKFnE5g28GWQg9IR8EOUqH0FDVKhQ1QlUoXUULVKFFZDYyhjJQjrIW4UIyqH3uCTqhwZQrLIXQUMRyHLVDRChKOQhXId9UOnyG/VDbKhTJQ+yoTbkKeKFoFCXihvFQzAodXkLqqH4BD2/2l26FdIaJUM1SFWlCEIh11QqSobdUJFyGFFDsahvVQ9PIc6UJUqHxVC1KhHpQtaoVekO9KG05DWyhANQ9soXf4PJqHzVDQahr1Q8GoeTkMhqHy5CNKhMNQrSoZtUNSqFvxCkahwFQvaoaBUOmcHuVDMahRugbSnDrEOGKEKZD8ah4lQ60oWl4NtKFdVD8AhRlOdbSDhkKlyFc1CBqhBGQj6oVDUP5qGjVCfqhNlQ7UoSLUJZKF/5C7/BGtQwgIYpUMEKGsRDwyhK1Q4aoVAUJYKHrVC4ahptQ+9IXIUKEyGVVDIUhaNQi/wagkPnKHoJDV+s6NOOWoWdUOaqHYxClahhNQlWoR1ULtKFw05NahEBySmoUIULMqGDVCrUhBtQ1UoUbUNhqEm1D/yhaVQgTIebUKfSHQ05rahfVQ0yoRN4PYiG81D1KhqdQ52oQzUI2qEW5DJqhOOQxGoR7UNtyE9ZDmchrxQ1nIRjUIgqF+89O6cjVQ9VIaHUKQyHYVDN0hUdQtWoW3UNeCFx1CTKhYNQ3WoQwUOTqF81Cy6hoCQ6yoTtkJ0qE11Ds6hgNQ/AIYPTiRCE21DQyhYeQ/KoRGUNviE/pDNKhMeQmeodXULFKG11CuKhXtQrooftUPdgAmlD7EgFzODuob5UMIKGGxDBchxNQzqoeFUNFyEegkL6hWtQkPIVTULeqE01D9ahE9Qr6oWnUMFqFV1CtqhHFQ6aoayUM1yE7M5tchp2Qp0oQnUKLqGNZD3Mh/JQ8uofakKkKH/1CpqhO1Q0DIQ3UPtyEzlC5XBHxQ/2oV8UM7ojipZdEhCGQuCodOQAQqFD5Dgqh25Q1WoQ/UImSGes4TKaOVQ+1wXlUIIqHhJCWKhyVQ0ioXkUO8SGs1DOriFDQsCitjhkOSFVlC8Kh1NQ9eoQlUNcSHrFDWKhpVQgBoQ8UIqqFOVDvahLlQmFIUBADPqEic5VbE3OQkOoZmkMVqE91Db6hGXgshoU24ME5zUFDOahb9Q7moe9UPHqGl1Dv6hsDQh7IX/UOFqHu1CF6hRugUTnPwUM0aEQNDzKhJdQumobSUOnqHwNDjGhl+Q0RoXbkO2CEs5CL/BaZQgOoVm0Ex5xu5D5GhCtQz3IQTUNzSFE1CVGhkJQiKoba0G8aEaNDtahWjQ0eoTo0MjKFb1CBahO9QhxoXeUJZqH6VCEUhaPOEGoZE0KsaEiFCjchjtQ5goVPUJdqEZ1DZ6h+9Q+eoc40JQaGuNCm6hdIQpkIfAACUiEpxxWQhLdQzxoRVrUaaryPJv+cvlQgyIeuACMiECFCt2sZkQ24QLuUNUaFqBDBTi9nyb/nPZEIviHcNDqOy69Q5UoSnUP0aF5NCK6hYOQByISmEMzqFm1DjVcyzg/YnBKQRD7KpEA9XBPJQ8AoXyUMsqFH5CwEhGzQv6ofcUIBqG+JCTLcJjSVzPpssCGaFg5B3yhU+QmBoVM0POaERhD9mhzNQ8UoUc0N/dpgxJgMUazQu8ISc4JGaFnlDayhdDQoqoYI0PuaHbVDg3BbRQgnIXpzFrUQTvszmhK4QzsIZc0IPyHbND7ChWRQ1aIX2gSEaGINDkmhFFQo5oXULhAFzwK43mhVSQyFoZs0JIyHXNDL0hD+QlQAPdEP+aHCNDDmhBlQ8uuEpigeoqYtCVoh30Qz5oTNEO+aEXlD6Gh0eAFKoUk0KLcGi1DuKh4jQ6qocoAGkaFDC4muWcjQ+DIedULDqFKNDJKhwTQu6oaE0PaiC8tCImhr9QzJoXrUN0aG2NCrKh+TQ3eoQg0LnqEHZCUmhqaQ4YXOk0KlaF21DGKhDtQz6oSNUIMaHm5CfShTDQpBoYzkNKaEQZDzvBQvg9JIeBUPqaEQ+AlES+A1FeAAQUP5thaODhiUVwQ8YVGRsDuaFmJDpKhpNQ54IUSoIcMykq5iAhCKAEUAAxUN4aGFVC3whosAUwIWxUL3qEAVD0qhLDQsQIXF0gkCG0VDUvBt8AINobQ0IZaEVhCw2hvgQiNoUq0KKaGpOCY2hcHZEQpI9xj9aFOBCA2hRsAGsoR+UJ+aGhtDiqhzLQsioROUIMqF6U40foQMmZiIcW0OTaHnlDByh9Tg9NoT1EMzaGONDdihJTQ54oY3UJ9qEIxDaqhrdQzfckMElkyG+NC8ah/jQ8OoYE0MjqE3VD76hITQx+ocO0LWlwU1Dh6hOtQpaoWPUNiaGo5Cf6hCTQiaoVm0KjaHz1Dc2hC7Q88GBzUIyaFatD16hOrQiZoXq0JuaGGNDDWhLRQ2IoT20JRqF9tCJGh8qQ1SANy0InlyqPpTghDrQxRoTfUOFaEExD+6hYWjZ7sJK0PAaEntDu4hn9QvRoRe0PxaFXtCmahALQ3Uoaq0OeCEzy4NWhgHQmhoZN4JsaFRlC7GhCrQxJodW0MeaG7VCOWh+1QwCANy0J0mrFnRzShArQ7uoV+0KCaE/tDemhkWQvJXC/UIQ6H65CP6hsrQlDofK0IrqGu1D5mhJjQ/dockrjmbD51D46hQHQpDodk0N1aFO1DL2hBrQyDoSS0Mw6HINDe2hqDQiWoVa0KwaHKq5W0qXU1VzfL5UPXKHQAhxihJiQj5IUIkM9aFoRCJkhMEFR1XFqjhjiEgwAJygzbQ+loa20J4IAkfUGGhnbQllodG0Jg6EquDpOhJHEDhodp0P40LVlD8KhLbQxKoYZ0PiRhMtDGGhN7Q8qoVh0OPqES1Cg7s2BQ5VIYxrnTSH8tCu6h8WQgXId+0LCqFztDfOhHGuCBwJx0MQ6HQBDaah9HQnZofY0O3aFdtC9KhKLQgyoX50KNyxRdCaOhp7Q5DoXE0M3aEJdChahpnQ4poR50NRqGPtD2AAckQ+AAOkkIAACS6cQupoZJ0L31yXa0Q+yXbAWLIa00PaaHUJDOmh4YAcyIY+EOmKEwwQUDUDXQvKId5ENpaFpFCIChOTQz0odM0I9xCzNDBOhSLQx5odfkIuPQaFDvtc6zQiKIVC0OpKGrVDUOhFdQvZofDUP+qFTdCj4hdVXcnpECtVqyEVRDKSh6RQ4bofTUNuaE+RDCmhu7QmqIeQ0Kf0oEkE5uh7zQg0UgN0NtCEptCDOhAjQ4zoYi0LnqFAtCV8hkrOJ0gmS4FlKGj+DVwhUTQwboVs0OW6EMdCCWho4QuZoWd0KzqEqtCUuhW3Q0DoJmNngVw/dDhwhf3QhOoTYULoCF4tD0chFdQrzQKD0Im6HKtDzwhW3QwgyoN0Dh6HjFDmoh93QytISG0KHKEudCTOhGHQjHwWy0KPqHFdDqqh53FHzoc8EMK65DFCx2hmMQ6+oZikOUaFkdCwuhjPQxjalR0JeqH/dDE6hMrQ9dodDUNy6FodDEuhBXQyHof6UKOaFM9Dl6hBdQkeoau0PtqHZdCN2h+rQ/9Ifl0Mp6GFdCROh97QsTobOkJ6KESdCOchFU1XDaJFNVk6GwVC8EhhDQgsIUp0NCqEFpDyOhWmwPKQqFNQCSGvlCTihXHQ/ToY50Oe6Hk9DXuh2bQnOoQTkJt6GxTUqEhxxQ4pwY70LLaGptCuohfzQ9boQc0MAqF3tDOihtPQtBoQ3AG5aEIDcGccPlQ43of5UIIaGBVDEKhxDQlCoSEkK66E2m5ksAVDQ4dAqW0LCSGB9Cyeh4bQt3oed0I96EfdDM+h71AbPoXZ0KcSEOdD+GhDZQ4PoW7UNkSHh9CDSh2vQrDwUDAG5aGSW4GP0uNQ1noWJUKFaGkdDQuhorQ+docpEEEtwAdC+eh0rQtdoZvUKV6H8dCVehRjQ8XoVtEPM6H9+DSuYXFCI9oZq0Oi6FQNChehhtQ5XocrkKx6Hu9DE4hGvQiPoQ+0OTKFyuDewAL7QvAXFpDkIOpydC8yhAVQj8gIWUPCVAhVDUKhhLgO0oSf0N76oDi4eyhuVQlToecUMIqG/NCXuhxLQyboWZ0Kh6HKpDH+hOB1Z/oU4EK4aF6dCA+hT3Q2voV/0JD6EPND0qhjfQkCoc30NhSF+1CjqhvduWYoRZDhEqFd9DP2h7PQkLoZb0K56F3+Cu7cT1QleoYtUIF6Fj9D+UhcrQ+LoaL0NV6FGtDkWhkvQ5PIXgMPg6Ej9D/ehV2Q6BoTC0O3qF5dDp+havQk0IUV0P36H7VDwgAL7QwJ3CNkJZ6FopDu+hJHQ6doXfUOjqEWth90hBAwwuoblkJA6GkDDYWh5AwtgYZQMOg6F/9CIIh4gwugYaakP56GQNDGBha/QyeoeB0IE6FF9CIehr2QxyoS40LNaEwpDFEAL7Q8YTK8pEI6GBdDWqh3uQkQYSK0K9aHLOCLBh2mQ2XoSu0KIGExNDx+hwvQjfoYXkK36HF9DE8hQDQ5VIU4MLUGE+pDXBhmgww3IUwMKB6FkDDGOhBTQyNoQYMJ36EmtDROhZTQ/toTCkJGPoM9DrnBn7uHGofLUPHaEXVCAmhxBQ3vodgMP76HKpCgPcw/Q9QYaP0PcGEkDC4uhcgwqIYYq0KS6GANCLahEXgooYRY0OPaEr9CtBhHgw9foZP0M36H6DCFmhsAw8WofAMMSgAvtChakmP0KwYQo0InaE99C7BhnPQgoYc8EIGGHH+oh6hC1QqQYUnUO0GGTNDdBhU/Q69oXZUL3aFz9DfvBUwwobwS4MI0GHWNCeOh57QvjoUsMI6GHf9DsehcQwowYaa0LcaHIJCpahQ7QzDKmIlg/ZjYJCmqhIxQkGAKb0PkCHm9C7+h0LgMsoc5xkoSFADDB4hb5Q41we/0PLaEF9CM2hnQw+JIax0L88CfDDo3BfCQ2rIcEkL+GFrZDSehSVQ13occMPd6GH1CxGhnnQ+AYUSADw6FwB4G8MqAwh4YX40OyGGTtDchhYwwvvoQ4MLHcGYjDlXUjpQ+gYc0MM6SEyDCKhhLAw+QYSsMIRqFrDDlBhuAwswPI0MOX6GZdDAPBZ7Qr+oWB0LR6FwNCxeh7AwwwYZ7UJRGGR9DQKheGwPHAjV0L16H2OxqHqpdQALoXF4MlhBduDCyg3JQi7puUBAhKETDDyEhd9xO1ocxEJK6SLFCnIhTvQmvoVeULr6HMdDZEhoIwya2Kf0KPKGFOCtRhp5QuloWAMOd6EQDCERhUAwqDoTAMM4GFa9CvshF3gxAYdLUOCiGzh5/OhaAwwQYRgMJoKG91CZ2hdpQ+5CMx4Iy6FhlDaOhCww7kYWbkOWGE+DDYhhS+QmaoWoUMXDzpdDl2hOwwrJoeEMKO6ErdDeRhFAwtzoca0LOGEJDCTBhSaQwdoda0KRjxz3p32hFpQ30YcF0LyGHoZDf2h5WFRxOsUMOCGHJjDBehrQwnQYTyMIg6HAjDL8hoIwosYX/AUkGFy9C3Bh2rQxXoZ4MPaGHeDDWxhrRQuuocjUL36HOjCxMhcbpT4oRKMK6SBJx4MhhAgwuLITYMKuqGEjD8hhxIw/AIXHHjJGHPVCShhDAwqkYXR0Jy6FeDDGahQ4w5LodQMM1yHrjCghhumQ7sYaEMOzyF7DCuRhBww5sYXoMMRGG+DDJUhu/QpvoS6MNhSEeNDJOhOvZbpNEMMNxGGCtDhBhP/ggMYVWMMzqBWJ5nBhIYwteocB0N3GET9DDhhg4wh8YTGMO4KH+DCm3BtieM8YUpUPrGE81DrxhoHQ28YZGMKOGH2jChOhB9Q7oYdh0IlqHijCj4hfreWgaOcJHtaEIZDng0XbgyNNK3ENZ6jj+DumhPeQwCYaS03QkiJwxmIhSnQ0PwS6UN4aFqVCSqhMEws8IaY0OTgAXPh0JIzrQqEYSc4LYmE8NDwJhgaQriYdhMJ/6HFuCXohEVaASYarlByqH1qBtxh5KQ8SYVW0MUGEwDCZJhhpxATat8MMfiHCTClJhsPgqcANYABQAB4AAzVcBfpUSgDoENK2BGcAHehFkw0SgBo4O82A2TCdAhVaBQvodxMPiSF4TDURhr4wwuAG30MbTwkXoSxhRHQoLoW1UOXGGVjCreh1tgVtPLWMPPGEhDDpBhEEw/sYVBMIPGHOTC2xh6ww4KYQ70ieQJdjDwphKYw8MYRhMJgKFYTD6+hw4w5EYcYMIuGFOAB6QhogAXwAIRMMKKGPZ5rYaYDAZRAMb0PKSH8cFDoh1SQ+iQPYMLU6FqNCcR8WaAc7PO8kN9yHy9CwxhjYwxYYXeMJ0mG3JDoxhCzQ9sYTuUzKmEkP49uh8yQ0MYWM0NsKHMDD4mhrBQuioYCkNimHZTCjmhkONIaYVEYkOSHtxC2phPYw8aYSj0MmmEi9DRuhECQw8YSXkIMqHxcElphBTQX+IRfEL0mFp1DUehmEwoJIeskL2mHZjDBRhuUw8podEEPJAB4dCJ88/AwmUYT+MOI6GYDCKxhfuQwCYZA63S0i89CtxhlIw5SYZ1MIjGEZTDoJhkkwk4YbGMPgmF3+CXphS/Q6joWNMI5GF9jC2hh0UwyuofSMI26G4TCnRhiQwkrodI4IwaFHVClyh3zaQQvOf0NGKHJ9CiGhExQi3oc8IGmKEHFCVW0gheX3obQkJxaF59DwBh+owyAYVlMM4qGgjCnyhIvaJQvJw0N+GEHdDq+h9ZQxmYXaMOZmHudDnxhcAw9yYYdUPdGF0ZJHV02IwzuocMMLxGGjDD/xhogwwCYR6jVCmHITDShhHUw8oYXuMIHGExTDwZh2/QyGYXUMN+8HHF5YZhFIw9kYdx0NTGG8dDcmhyMwpjoeD0K6GEYzC8xhpXQypoUL4IAAASFXQvDYKyEN16FHxDZe8uZBavrI10IQyHNdD+bYooQtrodC4RVGGrjCGPsXdtBzAJ7ML66HjdC6Zh0LQiIYZUMJO6Fg9CYhhXQwj+IfLjT8RJhzDkihC3QyOYUt0LTGHA9CrQhiJQneIZbMJMaG+JClDSJjSPPrPD0PxcH7dDFSh4ZQ8ZoTeMLNmHdTDCnBZcwgWYZ1kOTyEDZ4HbEmXHG7oYQkJpaGLdCCqhH/QoPoUzMMNGH8ZD3uhAZQzo/qC0JbmElzDDHBiPQjuYedMK2mH7jCZ8hhLQhFoXNMKPGFxjD5+hFX/QbwAKlRHmGTRDjoh3MwwHoZnMMiGEg9CjwhccwndobBMKFcGJzDkuUAleFeYYT0I+aHjzC+GhvMw78oZW0Nc6GrDDqehQowrgYeJ0OKmHPBDzuazPQt6YVkMN/GGfTCAph30woKYZ2AAULxLtDZhhF4wiKYWlMOrmGXTDNZh9cwqgYQvMNMKEfV4DZhAMwo2YcXULQmGyDDaRhVQw9DoWpMPV6HxDDNehmMw6qoQRADw6FN15Tqh78w9AYSMML/GFIRD6ph0OQoYwHXXiVmG21DAZhbpQ4GYelMMFKEozC+phLHQ+KYUrEAoWGsjC4ZhYEw42YSAsJG6EZjCFBhWYww5odbMLymGrAAAAAqs/MPISHDyY5xhBCw0pIcaBS0cFyVYjYAsbg6K+pV4ThWJTFDAJhvytNX8MQ/hXqG9gVTpwuDeWsgqrMP5mG9zCWZhzCwvrwHypikgBuc4GNwmow16aFosJEmFnFDiBheiwvOYQ30JeiGqLCTFhUqLXXIZosLDDBWLDA4gZQw2xYfHMJcmEOLDjFhCgkUDIGlrHMWFZdBLFh7SQzxYU5MK1mHF9DFmhnVxRxYQmmhXzR2RCnAhriw5HgKEsN0WHhLCIFhYfQ3xYdWxBMWHvJYXFhFiwtxYcksI4mEgdCJJhaSw9SYVt0L8WGGRo4lhYUQx5wYksJyKE6LCClhujQopYfosPKqEZLC8w6hkaTlgDksOCWF5LDPkhDYwnuYXYsO7aEOLCR/qqxNNpYSqwGICHVLDtFh7EwsSYQaMN6WGcVDfEhMCVPU5J6riGWFyLCElhuSwpJYdQsNtJyFLDVJhfCw9JYVt0LB7SDLDxLgwywpZYR0sJWWHwLD7YhKkw2+YQyMNScEzLCylhFyma9kIckNGWHuLC6SCNiw1JYY0sJEaEOLCHbiieAW/FIEsNqyF3LCzph62QzYoRT0LQWEXLCHFhP/GExYe8IE+WEhlDvlhqyw35YU2UP+WGbLCSlhEyQuJno9xFBWE3LCRlhyywmpYeMsJ+CHrLCzlhaMw6SYdD0OIbrwCQkVh+ywkbwRCsOOWER5D6lhGyw1YYYCsNxWFrYYCVhiywolYaisLGWGiTCMVhZKwrFYaH0LhWGKOD9Se8ywvZYbSsKqWH0rD7lh7UwupYacsJhWEUrDMwhR8QrvvDWYU5WFgrDblhvKwn5YZxMPJWHnLCRVh5DQqQ7LssMlWEorDDlhaKwxlYTF0MxWFCrD5VhUSwrRITkWHeWE0rCglhHLgo5YfDMKZWGCrCbphNbQ0VYXFzhBWEZJJCVhPKwtVYQysPfqECrDJlh3iw+xYaUsMyWFC+YPG8Xyw6VYV0sMeWFAjC55hTSwq1YUGUIlWHIrCDlhxqw9VYU6sImWE9LDXVhfSw0VYcNdhtWELLCjVh/GhE1YRwsM1WHMrDtVh2KwylYeQ0MtdzKrDQ1hdKwh1YXysPWmFRrCvFh+8wniYb4kP19JzLCi3aGiwn1YQskNOSFprDzVhAawl5YaKsNZWLvLDShKDnSb1YQWsPyWHFrCnlhUywwNYeQ0JbWHEFo2lhSawuMACmsKviHOrDo1hpawnxYc2sK0EzvLCX0G8Sw/NYeGsMdWEeLCUlh/qwiJYQYMN1WH8N4Z1hO2aW1YdysPNGE1rClihdawk5YS6sMnWFurD+1hW6w7ONF6sPBWH7rDalh3aw1dYcUsJxWFnrCC4UQ2Gel4POsPtWGLrDC1hyxQo9YROsJqGFNrD4VhVyw8azHmsLfWHJrCI1hy6w8dYSWsJ/WGWrDH1hI6gx39NCTVVWHvrCu1hZqw49YRBsK2WFQbDK1hG+YatYZ2sN9WFhLC71hzywyDYYo4IHWFqkYVVhYaw4DYUusIeWHYbCO2hFqwlDYfhsPPWEEHVYNhxGwkdYSBsLI2ErrCKNhjawvDYdk4II2GQiZhWwlSwvdYZhsNrWHzDCkNhM/QjdYYVCxo2EAbC7VhPGw+DYVhsOY2GSJCM1hrKwh9YdRsKfWF3aY6NhC6wkjYR+sMPWGkrCG1ha6wstYdfkI42Gt2YiNhymwhjYaRsMDILkbDpNhlGwtlYexsJE2HqLD2lhEmwvjYd0sPA2GCbDy1hOaw6LmBUsOHWEhLDIVhsqwllYdAMLk2HkJD/1hF5HMxYR2sOs2EHrD+Nh36w+zYdfkPjWGPIJnNh/mwlTYTKsK1WGmbCvNhrDQ5LlGlzAi2FXrDeNhpqw+tYQJsP5GFCbDxtqHqwjoWElsKlWEpbDU1hX6wuzYRlsPLWH6rCZPY5SDV9YeJsKi2FubCYthrGwqjYdk4KVWFObCuNhLmwzpYSSsJ3GEabD71hWaw9lYZCtGLwTqCUKthtrg4lYalsMK2E9rCY1h0yw6/IRysJS+R+bDkthAWwgrYepsPS2EArCFVhHZQt53ENzFy2FwbCqthrWwoGYcFsOK2EOLCvNyJmmXrYdxsP62HXrD0VhaWwzbYfNsMy2HfrZg1hE2w9tYVNsLW2GDbDZthJ2w2FYXFsIwSE+bCR/YGGw6bYWOsNvWEsbDNNhU6w+FYcCsPC2FNbDIthBmwwtYZeMJoWH3bDhVhZ2wg1atBsOW2H/bDrthgOw6LYemsNi2GdbDyEhOywxrYZNsLy2FvbCNVhQ2wnDYb2sN/WEdlDVBMu2w8rYftsPxcEDbCZthbWwubYQ9sMR2HRLCBlhKOwq7YWjsJu2Ek7CNthRWw07YZcsOy2Eyvo9NhQGw2HYZJsLA2HDbCT1hsawv9YSzsPWfRKbD2dhrmwmzYX6sM+2EdbCFth3mw/nYZjule2F07D3thiGw0HYTqsNcmHCjD4BhQgQ1IYSSMM3byvTDvRhC4wy6ocrULlmGkLDZKh0reZeyJQsNXqFHbDMdh0cw5BYTwsNRmGybCJehUCw/3wBrsNgWF1jCVZhWXQxBYTSMKmmF0jDGFhTjQgRYQ9MKcAByuC3Rh1wwoMOP4kPVcEJ9C55ISfQq/oUFUKLKFp9C+6hv8wz0OItdAhGEV9D7uhwOwpioV3MMBGFi7DcNhgFQ0EYdzvhsSGE7CcKh1DQ9bYZ3MIBGHwjDudhyGwx0YULMJ6GEujC5XBosw/3YaT3jVcEwVC8GhF/Q0PYQQkJWiER7DTEh+uw+6odPAGwly8JCzRhV0w1/obdsIYSEF7C3EhCuwzNYSX0IDKHV7DcbqL/Q3PYb3sOdcFwjCB9hjOw8nYSOMLFqH4TD4BhnWANvoUnMN4Yyd9CfRhRCwr+YXrsPGGFBzCU+8+2NABYZY0Lh2FcLDjuhLYw2rYQfUNBGHuzDaoCOuQ0CYabsJaGFqzDIJhNcwsGYeLsNOGF3TDzhh3uw1YAEL4J8cHFABRFhY7g0qYQiPl3+ySLCKkhF1QyuIRC0OKoA1JCo9hOAw3/YU1MMsGxh0IVpho0w+nYSDsInyFNjCwFhOew3OYSNsNqGFPpDmM43hQxEfCPMPZxzHJC89hE8w83YW7sJ2mHXTCz9hxTQg6YRcLn/2EFnRWphZ0wyuYehMNAWGgzCt4hpBwr7YU40IOmGh2kqDhsBwk6YfgcMn2Ew1CLphjBw1A4XckPQOG3TD66huYwwRYewAEZCE/7DY2hhVaKcfIAcIQspOtDpRh7PQk/wKkKEDmENTC1AhsPBGQ4bVkPDCHE9DqihE0wog4dtMMt2Ee7Dsphxow01LrRzT9HzEBCtDh48wug4UgsOIOEGHCEdhAowkQ4ZgsJtmFYeDKLcU4wt2YQFPgkWFa7C2ehfowjnoUSMNUOH9+D3DhB+wpoYQQcKhWFVzDuFhp+wlg4UYcMMWEuzpgp8SEwqhYQQcM5GH0HCwjh94wiI4be0K92FJDDVEhkhw8JwJtUhk6GSBC69hRMwsPYSn0NJmFvDDAphkBwnkIRsoXGmqEHUaZh5kw4I4dPsJd6FF7DBNhoIwu59AtNR96HADCuZhPBwpPYf3sLqOFY7ChDhE5QtI4VjMOw8EvtDjZ8HhwnEYR/MI+mHeHCsBhJRw1UYVpEOtnzG7DCBhiewkI4YkcJP2HJHDn9hOsw3OoUMcLYWGGzD2jhCRw6w4focPCOErHCHKhr+w0Q4e/sO+yG2FY1dh+AQvxfP3Rh8mHWDCddhEdQ7fYb4cLIWEexs5w05IwuBYe0cIWOE7HCp5hFswno4UoMOPGGFFCLjhSUw7YYU7sIRmEu7D1Zh5sw6IYTzsNSOGl7DF9h7kw12YYUUOFXw+NDADhXhw8sYd/MIDIDTFDLBaNbUf6YY7sKP2G0LCGDh9Cwz44eCcIwOEE5C0Thf7MNPIUmMMBOGcLDsThSRwqMYXYcJf2EOHCxxhWCw7gYZXsMLGGPr5L6hH7QzfYeMcK+mEonCfphzJwjE4WFMJQmHGbDTZhlJwzKYWnsPP2FRHDy18XUsEk4YAsJSmEQ1DgThD+wlA4XicOL2HoLCcxhjhwsQ4SmUMyOEd2DYchVVAFcocHsJVkSGJDr+hyFQlvYWhUOj2GAMMk+MPeMePYaAMPpmE2jC+Zh9RwjLYcaMMpGKsOg4e84+wnPofZ0N1GFXzDhQAP5QuVYUPsJymFv7D0jhPRQgsYZJ0KoqG+tDcjhuZQ/I4Y3sNH8FFHCVDhZCwh3dr2ZmxbgJtDoRhG8w60YXqMOvmFk7Cwdhxhw+wIarxkLaE/DCrJh8Zwi04YmcLdOE3zCZNhnmwi5YX0cOqqHR9CzjhPQge29MMcKlmHvTC/Jhtgwu44SuML8OHnHDyD8sxwuYYbZsL4OG4nCwThCpwm3YVDMLHcF0H5YjhJuwjHYXfsKQOFdTC5ThHZwmfoTScNHGEvjCxMhfpw6cYX5mT4tzfjDRjhNZwpcYXWcMmOG77DHgey8KZs4UAsKC2FDnCQZh7Zw6oYWOcNWOHAtCcT8fZwuY4bsMJNmH7DCcThY1Q+U4fucIOOG0nDJzhtbg98YdOMIPPwMpp5zhhCwmWYcQsL1SErnCGzh+EQCrOBLkM3GGYnDqthkUwpGYY/sPAWHCnDGRhPxw6TIfBfgd2G8nCyThCCws84aEcKWOFUnCyDhHAwyE4W5MLEyEhYBPJhj1+Ss4VfUKEGFb7CSFhO+wr84e1EEwuGBHC2Rhrxw2LoSCcOAuEMLDqThB5wlfIamAIu1gSnDD9hqyw7Y4a7sN2OHLHDQLhyFwjBYXScKcOEVdDD+h3LQrn5HmLSDOFbOCGvSWjgvQQFcEOxWBsABHHAEZw2Soaq4PJ7gJtD+8AP0QnUYWbsJM2FIXDh9hviQvi4VhwmHQLEBC5Lh2hw0XYUpcJSOF9rCNpqalw0fdNhULGQDOODtLh/Jw6FYXYcLO2FQG51LhjUQpwIVpcIvmHubCCzhDow4twcWcLQaF9FDrWhXZRHRIUHsLr2GJ9DZAhHaQpCoU7yANOH3HDZKhnlw3hIWacMhWG1HDbRh1pw07YRnsOcwI9mVwrhNRw5PYYXsO6OH4nCRGhrlwiWod2ADw6F/YF8n0Vxw6WYZ/MPZOHInCtaes7QqY4fgEOyuHkupnjh/5w4I4WRcNlOH8HCrzh/IwvwYbrMI9BIQ4EoLhysws6YUxcPIuEjnC9zh9Vwp8YRxcLvOGYeCU449IQ2ZwTjMLFmGhQBDamg3gfULI/AFiyHGKV5Dh3fgMTYXlFRS7jl+CKxcPTQ0o4XKACobTA8AKeGu6wyFwXJcI/8G59C+9h+fQmOgPazFn2F3zCVLhBlQnavCY0lwgCIGB7Uh21w+7ocIkJdOFflCi6KiYhaK4Q9sMPmE4FCKW4kQSLy9JdcMZ8HXXDzThe1whmYedRUeuEpXCFThL1wzwoW9cIYtpwSIaChpgQZxwTtcOdOE2+CPHBeAANqLH9cIeuEiABmwAcNwtqLFYUSrqwo3DRAA8Nw0cANYAD0Ipw+AjrhDIw++YfdMN38EzlCyuhapwhFcJwOXuTAy+CEMh23KBFgm00O6mrUJDIqgZkQpa4UQ0C66GIV51aCVNw3A4WN0OGaEIbDN5hApwhC4bXMP66GGHDb2h1+QmLYDrEU5uGHRDNShqmw5HoSvEMnmEazDDHBUtw4W4ftMKPiE/7xxbhCdQLm4WXMJvWFDdD+bh6Yw8qIULcKouHvxCVbhkgddWghsTUOiHQQAxkAvNw3FoXLcORmHvIBRwhStwvEoUyMMXKHZK4Liarcw8oIUT0IcuE1bC9LhPTg/uYY+UOFFg6xFTbhsyQxWCOfMM52GPdDLThSZwwfYbJsJ9uGhbCjtY6tBFK2CPMKDuF3dDLbhOZw104XGAHdOEebDnLhwNw6jYX5/V+jp5loy0h7twkO4fLsIJuHYrDM7h2TglGpLHcM2qSrzCXoAFtwgu4XzcPPOGCnDMShdtwg24UTcO9OEE4EZyhA1wmIIdy0KtbhFTBbv0gBw6a4RVIB3sQ5JoaChbRGRa4dpcOmKHJYB35UpZeIyhK3EMhuGEuDobhVfQu64SawEOuFPXDjrhvEwjWAP6k0ZQCeCluyhX1wqG4TdcJJ6FJXCeCAS9wwG4QV0JLuGdXE0b6/TQCKplvcMYCHfXCYRh/ZQyK4ewFQG+BF3DI7hEuw0+4cLRA3uEviCrghM9whToTfcMYqGY3DsbhYdwpG4bD4NRuHo3DkbhqNwnG4XjcN78DL3DCbh8+w9lodOkNbuGgVCyuhCkQ8m4Rv4HePb5tFjK8gBw2m4cYAnpuEJ1ZY3BTNw9roSzcLl1rFXDVzhHLBa5gKg8J55jhzCebhNdwq24XocKnmEzNCKHhylwp5IYUULLoDQSAaxEldwxW4ZQ8KuaHW3CKLhjRQhUofscJPuEu5DAsspDw07GrHMKTuFRzCt5hMcwvW4RHMPoeE7JCCPBMeSU/gEwOlduGj+DzbhNzKdh4aI8J1uFZzDCEhbhAd5APbcMgWHdnCXchG2gOR4QUtC5uERcAHwh2Zw0nYRHcM82FR3DNchv//Ax4YEcHbyG2YBg7hIuw2+4fvcK6OGp7DsdhgLQk64ZrkJzkLQSBFlC8dw+x4YncJUeFT7DnHhUVwo+4Wr0L4eH++Abo43jwyz4kY8PzuGOPCpNhfyw2LYWE8Nn8Cs0QeRi7LcM24eP4MDQBa3Da7h8Fw3W4Ro8MbuFSPCbzhE5wj7IXA8Ob6FldD7ZhAAAeRjjhqRC2+hynbGMQurcPQeFFBBMHhvweUUIbg8O3R7KLCjThVrbDm4XU8L26H63DYnhG0w2W4dQ8PluG0PCLmhTdw5+4RL4JqeF+xE6fUktw8koZUUMyeFUPCxHhFuwvwofKUMqKG8PDRnhHzgUxALU8MmeHdPDJHhgWwnQ4ZtMIGeHIzChnh7rQlZ4WdsJ2Eyk0EA7hKfQpR4Rk8Ll2FZPDFjhOTwlaIZo8LQOGpXCdHhjVwkfMuS9BduHRPCHHh5cwuJ4RZcLIOGWPDU0h1MnM54TG1DseHtzCAnh+ew/a4TPsMgeHF3CPHhqaQwlloGIVzuGB3C/HhJjwnZ4bCMKCeFWnCQnhaCwxJ4Wc5jheFpAA87hnzw2Z4XdsMfuEWPDVnh4rgR7wNi8IUeHDhDLnhIjwjOYWo8O3mEr+CHnhghwp54cJ0N6uFFPDkyh7dw4a4f7sIB6acMFDiY/ZAKa4WtlBmuEvgA5rhBfABa4V6EPweG2ikH+h7eUc+4ao0A/uFcIQd7hP1wwJ4Z0cKmQCH3DXHhXxwqnodC8OeCHGdNmRygLsaV4R9YjvpByvCwXhiNw/iKgDcOVeGMvDVXhZ2wnZrIT4nHUDkjkIbhMrw2e4bvcP+GHgvDN0ASrw3S4fesMxeFSyBP1KlvtK14dPcJteFf3C3+hSpQ0B4f/cMNeEgPCsbhaNwqKghjcNAeG6EUUAA+NwyF4U/cK9OFHHCSbh8DwypoQAAHokHh4ghJc6G+klOxq+VCMHhzCQLB4V3sLfIBemlWnhvqw1E4Qb1zhwApzCQyhmtw654XM8JpeHiPCRvBdcwti4Tj0MKKGUOgx0KpbwohoWw8N6eGHdCq3hCzw8oodM8IZKFe3DSWhmuQjrxE28MuxpbPC6HhyLwiuYbocPmeE2HCJHhI7w454bRkO/BAS09aHgaTwlvwVc8IIeFjvC9nhE7wli4fc8LyeG9vDvjhtuw11wEsnHYUILvD4chMTwr54VzsPReHPXC1XhuAwrJ+Ae8MsrQglDEXh8lwit4cncPuuGp3D8zhCTwi94WO4NtkrmIAYrM5LwoLAHe8Pu6GfrDH3hjLQ6N4US8LO2EwjsMR8X7wj54f48LbeGF3CgPhGdw4l4eY9mYdSo614Zci7w6u4VB8JueHvHD5bhttwo8Ido8KZeFKnDOLhqwAYp4S6MLK6HqJCyzhM2AXvsp08M2eEjHDMYhWbwghoU08I5SEtPCCHAbTwla4TNgEoWrkfD1uCwjw0F4YQcPXeE0PDubhwzw/J4a68P0tZHsJpfBrDw7t4VEUPxeGqPC67hAtw4cIa28O3eG4TDk8h8YyP10EJ8PIeG8fDR3hP9w8d4R28MneE1vCenhMnw8g4ZrkKf+z+3CgXhQVQyl4Rx8KsOHMXCp5hmHwrR4SM8NXuFTGBDvIJtwgz4QtUOPeEKXCCXhMHwnCYXBMJeeEXGAv/qtnwkzWMC8Ic+EPvDfrhAbw0DoMmcKgeFWfCBpCreGCNbDi8IReEgvDUPhCZwlO4QF8PMeGwfCQPhopxHWInHcNxeGQfCVPhp7w414UDcLg+EZdAZQI5dw+F4Rc8PSeFUvDeDhnDwlA4eZ8MeeGdnD7DhhTwnioQR8N2CFldDHoseHQh03oO8IbyGxZDqPhwoQhm4Tg8PzeEMfDC3hP0w9erA8EmLmFKfD3WhYnw6l4RJ8LueGC3DtnhM7w5PIQ18JLeFDvCU+h0nwwb4UV8P2eFcPDV/BTRQ8b4ZrkNlcKNfChHhU7w5T4XN8M4+HqfCN3ho3w6d4XW8IYeFNuCnc4GI+YeYch8OUeFRfCOHhC3wkr4c/gAs+F8fC33hWNQ99CNe8O/eHseCfPhENpdL4c68NAuF/PDjvhujHAUUoe8NveGRfC0vhodw3M4c+8MC+FQvDgvhRBOT94afMIi+FvfDrFhTjwhV4Wi8Iy+HH3CsvhL+cHuRDn4ha4i4ZDYfhoGwj7YZ98LceGstCUfhMAgNH4eB8PO+HLvC4fhqnwtd4bt8LM+G3fCyvh15w5u4XG8Oq+GSOD27hUjQkj4a9gGBaj0904qaXsw9RwX3cM3AAD3DBXhRPAYV4Z18NaiGonCNmUSSSZLACA8i9eE6vC57hj6FYNoai8P+uFg/CY3h7YwkX4QPaUctjWvDJfhdrwlF4Qj8Ll+FxfCXPh/HwzW/KL8P3JwjzDP7hurw7+4TL8M1+EAPDCXh8Xw2jIXr8OV+Hi/Crrhsrwk34eb4P9eEg/CD+CQbw+G4cA8MAeHBvCwHhkbwiB4We8JXuFK7C+2hDPwipocyEIAABqSDw/PQlqGWbeGZvCGnh2bw2j4QIUPo+GzzDkXhdpQjZEut8Je+GHPDHIhvnwob4dk8PUeFeRCxvhh3w6R4Y4MKPmz15CNvhXbwpZ4T28O2+EmfCOrh/Bw7h4cs8Lz+GG3DlUhwZrFP4RrcK0+Hl/C1Phw3w7P4ft8OU+ErfD6/hKVuZ74ZXcKM+GXfDxPhWfw2l4bk8Kw+GWfDjRh3KWa+FGd8KPeF4vC3Ah0Hw334UF8PH+HB9Ve/h3nwmf4Su8PiqF33Dw7hFvwnX4Q98LCaH2opEPhcT6AH4Vj8KY2Gm/CHXhwTwpH4aE8Ky+E5dYwPh0Pw+z4av8LJ+EffD4nhvzwy/4dq3ih+FIfDDPhBXw4z4a38KH+HVvDN3ho/w+74bG8OVOGqeC27hg1wlXAG30MHlzACp9CAvdwvl4f3cNmuGbXChXhIdEQX4YqUOmKEW44KSkzlFZcIVfcPt+G+vD4fhp/w++4Ua8Nx+EqvDXPhT6QlAEQNUhNOjZ7CjfhUvw3kYMD8Ji+GfvB5fhwHwguYRZXnktSNBlVfh19wrAEev8Nl+Hm/DnPhUkw114TRPnR8SkAjtXhLAIj1odUUKd+HUAjDrhv9wkN4aRADDeGe/CI3hUbw+f4eD8P9+EneDA/h53g9u4bh0JZ+HTZp3IkU5TUCwLy8PKSHx/hB7h1EwgX4Qn8OWuElXDFdmc40AFAGd8H4BGYAjBARGvwnAEVr8K3+FcAid/hppAa0KM+oGrnRwAjishAgI3a4fK8OsBEcAjZARMbwguYQYCQUaDJbAXAR5AI9X4dgCINeEu/DtfhdgIk54X4CKFKAvkA7fhtrwvV4UB4OEBFPvCwgRCQI4N4e78JSBHY3DpARPvw8/4Ri8OgeE09CA/hrLwwa4bNtlUBFEdY6JW/FKSa4eRMOgBE8/DYARolw/QEaK8PJmEKzCzF2LFic8gG8EFiBE+vDLARIQI/z4TQCPCBFvdD7ARWxKTOgMQ8Qy/jmAi4gRDvwnmYUkCK6BG2AiegRZrwwEgn/YBdNLMAiLAR7gI/V4Z0CKdeGP/DtPhrrw1t8g6chlMoxAjt7hwwI1gEWM0MSBGL3CH7hYgItIEWICK9+EyAjsgR57wgAEXh8KABGgVCmfhMJw474T08HhoAFeINSAWgIlvIToCL5+HD3CRXho9wn6YZGjyK0abUChgRbQIhYER0cM8BGBvDugRRTQ774WzUJMyiNBJjlIXBAVoEcb8N2BFUAixgRywIn54asCIJ+EgBJflgzrZCX4W4CJhuEAfD5yASIIm8oU5cO3+EgfD0D8BVSaEEf8CLhBHtAif7h+wI3EEYcCKAeGhvDXfhCNwzIEUSEFBBG7tC6fhgAI+N4SU8MqaGchDVARmOrCbwleaE5+FbOCWvhhkQtr4Xp4Pj+F1AiHlhwvwyiZpFAD5BH9fD0/ha/wvp4S5EOu+H8HC0/he8w8r4Ud8Lv8H52JeQRk/AYT4aX8NE+EZ/D5vhXHwjD4Ut8J4eG1/D+PhK+rUaANKCOHeFbfC9QRO3wtv4cP8Jz+EHfC8fhsnw3T4c8ZEESKs5oSfhhXwm0Ed/8M7eG//C7vh2nwrs4W58KGMDWop5+SboI6f4al8Mc+FmPCJgRYII3oEa3kH1LLBgiHLwrcQhO4Ui8O2+GXzCxgRadwgkERECMV+G/CxIoAnHQF74YmCPveFygiEQRgHw7wEXQCOTyEvOZswRuzmFL4UmCOtBELHCGlhjoIuv4U24MBrSjQAcwRffwj/4QP8Mz+G3PD2/hDdwv/4X6CIq+EL7DYHhyZQsroSIsLw6F/7CNWCaDwrXYYKCJzeG0VDRQRf7wiPAKicNI5LMPCxwRZbw5v4daCIr+E1XD6FhyoI7D4U6CJKmHQHDJeSL3w6v4WX8JXBFf/COwRdoI0fwdJ8K7+HPBDFphgjw1P4Tx8IG+GHgiKfhtoIn/4R38KOeEmgiUfh8HOaCQPI8JbBFLvCPQRq4IqKYYt8PpeGbgiwLhu7wkbMngkKcg7XgjjHh+YI0ZoTj8JWBEuvDowRsWFS7ZEpm1zBG/vCPQRKYIosEecCJXuHtjCLsekTw1J4TD8Lv+HY/DRgRqEI/AESa8PrBGW1Ci4gWEIjH4eTEKP+FGbDvnh+II194SB8NAWBkQi9wRVdwi74UD8O1uEPgjvQRt0Qrd4TO8LSOGKAinAA7dwsHvMUCKqyJxMB14A+lQXyodz8LeBEuAiPgRiAIwwEUQ8MvWpAGB4GA7XQTEEfMCOxBF+fDnfh4wIzgEZMCONGGNblrggoEaMkERQCL1CCFgjqQReAI6CEV98Mv+GFtdvjACkI2EEXpCOy8An/DQgRakI4sEZb8IOmHG/Mx/AOkI2ZIUECPiBEnAilgRNII1IEXSCI9+EZAjcbh3vwpkEZGCJZBG5AiH5hCgIgcEZU0KkcFKRCpHBUjgsp4ekkKQeGh9sXpkmhQmm4dH8Jo+HCgiivB04Ixj4UYCKsLJuaxEoR14I8t4QWCNYhFegiNPh9oIzv4S+CMiBEitRcoR2oI5PwQqUJb+H3giioRe3wqT4SJ8Kt2GFnD63hDcQ1/1LX0l26FLgjtnhtUI/p4QaCIOeE3gjTuhBAIi7oW1CIqZDWOJ4wRifg/v4SxCLQ+GmfDDQR/4Isf4VEcMWdQ7BJvuhlYIiCEV80MUuHGQi6wR4II/w4Sd4DGhGIQjAfhyYIjf4XmcNoBHxfCL9hsLw/aIR7SF8eH7QjqwRh0I0H4cyCKzqHcAiBPMC2AAnoaGCKrBEFQjjthQUI+6EVl8LBrRPQiLoR7oIz/4XVCOPBGPgiuwRvoIriEShcNRqE8QjVgAfEI9y4f6cItJx7uFhIRzwIioEdoCN5+ESQjagRXwIo04fJ1V34DyQj9KglkI4IEWwCLN+EggiPoRbAQraEb94OBsGVhA0CSMII7YEQCCOUhEeAjbIReIIkioemCMmBGotCNyiyzACyEZTCPJBGAgiUIRhkI46EYSCKZhErlEaLarMIjAETsCIpBF7AjPfhnkIxMQkcCJ8hHpAiGQR/kIs4EYRCMy+GXAj40hEMI22YcyEI7uHFAivCh9/JP4oZR8KkWEpQjWvh2DwkUER18IMBGs3CFZhAF6J/pHJUDY+GbfDbwRb0Iyt4WxCOKhFPgjBoRREI4aEcs4PVhG/FDzYRJfw6qETM8LvBG9QjKfhhoIs8EWVCKOaFsxtzQRWoImUETOCJluEKgi+oRFFwjcEZZ8P9hGRtg4wRjEIyaET1CLDhHewibbh1Pwhl4aqCOouGUVCJCAaPwulhmBCMohEPdC5/haEIhf4VEcMbSrnbkQwRh/w3CEcf8IMhHdzDCYRA0Q2CETnXmWswVcNwvhZcIsMEddCPYBG3Qjq4RP4QtYEWBVnLBFt+gVoRIcI1s4fZCJ5hGnXCmD23cIxuEUQ0PjhGewjE4RNsIhqEUKUM4hF+wjuIRBQI6ZwehcNUBHqt50TUV/sKAEUjCOqBGzJDJIRhsI/MQtMUOhUBVlATOaZAI714ezCOphGLAjVIRdMI2sEQQCOJhGRq1GPQwZgXV0K5COPhFWQjpiglcIpFPA/cPUhFRgizthERzZgIIAEQfhFq/D4gRnMImEmm/CIHhERAjfEhX8Iu+EYOrRxhHuQiqQRgCI8WEbSCIkBH0gjTgRWQIuWEcj8IVhEsvDgARszgpB4Up9nGCITXD14RrwI5GETUCIQBE7wixXhDEw94RJFAA2uG6QjcYRNkIsWEdzCIzBFRHDyG0n7wqdxBQiP/hE3QjkgR78I4KEWdsPZLaVsByERv8IrEEfPcOi+GIgigERBcIuQES9EM4RGrKNwbhikIoWEYCCI8hHnwivIRbvwyWEScCMZBHzxA2ERn0I1BEVV8PChHMhCAAAGmH8MSCFTfCmvhyUI74WDH8LShGOOCMoRXXw9GEU8i0b+HBwjvwRR4I9D4f1CNreF1gjHYRRwQxprOm8MYhGzfCJ4RIRQ4r4VX8KNBE1/D7ERrUIpZoVztF0RHF/CSoRlsI+/4e28KnhHcfC7ERQ0I3xERF4Jn/LzvCb3hY8I1sEVNCOthH1Qiqfhc0I//4bacOdCLL/CXoRq0Iq0YU58OAREaQii4RGqcU74SubD2hG5wj/3hKkI6gEWmCNohHGjDjq8RPwm/4QmCKQhEcfCAERKew5BERf8LNeFEXZr/hb/w2/4c3CKthG5IihERPgIgyoWc81f+EH/D4kRX4I/6EV7CLCRGzQjZ4RPiI8c4X2CPBhELwir/Brhw3dIap9kKEBlAjcER6QQ8SEQQiLNhpEIj6gR7Twg9Tj5EmaBFbAjBYRVMIvhETiCJgRE0Ij8kRjtwiXwXsiKTMaDAieERSkIk5EeUiIERFGQjkQRMEIk54TrqX2RHeaRDkREsQ3hEdL8JfhEHXDBERLSInIEW8iPTWY3IiWgRbMIp+EbdcNhuGiwiZERsCI7yEfAiN8hHSwjwHhgUI5REUTCJChHE3ClYRIAAMroXcCLVGFaKhWPh1Nw9RwROCNj+GM3CDYRYoIwMgnaULVnJq3CKPhK0w5cET0iMH+GAwj2IReoQrT4eeCJxRESGYJnhrsIuUoe7CIPBG0oj2wRNiIxb4b7COmRH5/DolhXq6PFEU38O6hFuIjj9hI3wxlEbn8IFRHEQjolhhp2QF4V58Pf+GjIi2wR+oIpOEX+CKmRGRIiGrhT6Q5s9oX4POeGY/Dy4RAPQ9aES8iJMhFWfCOJAxBUd54Sv8O6REhIj8IRn/Q9uEX3MNghECu0kvhFdwy1Ea9COtREL3DbURKKImuEWa8J9SDmojkvhWSIvuETpcI2hFXwjL/h5YPJ1EXl8JGREofDEkRV3w8OETd8NSRE9giZkRMDwuZEaTcMqaH2zCw/hkHXQOEZrCKrOGpBDCURRiI21oCSiIDRF2lDjySGaI9lEXbCIDRGrvDxkRySIwZ4QNCJVBG0/DTIRCyqKUEUHCKCqGuIjuURqqIiZEcnCP5RGaojBURv3gqKHO9EjNhF5QiaURbqIpJEfSiNthFSoiHQRnaI2VEd2iKU9AlwjxoRK/g8eES2iM9BHDojp4RM+QjVEQ7CNn6GXIiMVAZ8oStgEsMgg+Guoi1oRvSIwFERcCM0hEUaxY4Rl0I0pEWpsMeREEQig0RREI6+EfCD3ZVZ4wUe4ROEIq1EXhCPdRFVwjPURHcI0yEflXCbBEVgj/URyEIxy4bRCIWmE9gCR4RccIhJEQnCPcRGKgj6FhpXw1OEbWiNURHe1CMURZXQ6c4at8PnR4bPCkoRBKInWEUKCL1hHpQj80RmUIoh4RDXWWsyKfDLQRwSI59EUOiN5REoHDI4R//w2jIWLQ0pRElojGoROoI6W4bs8IrRGLoiqfhHaI1dEWqCN/2EAEERURliIsZEZPCMrRG2IimURfsIib4Yi9E8+EzojCEhc6IwdEdGiLVRGxoiV0RacIwgEYScM05K6oi7Ph+qIp9ETkiIjBFvoj7URwXwtkWOaiL1RF6uC8wRZaIvGEcCCNi+F2oiIYh0YItNOKF8L9RFNwjd0RFcIm1Ea+iLyREfwiKMRzKYMNEaPCIohEGoiOyC1EI+mEf+iIm+H7egHMRwGI5VEVGiLpREkYjPERcaI0GEcy8LURHoIizBh3IIlXfjjoVWRFa7CxIR+CIreEajCMkuFt7CChOb2UaLQGCiKOREnwiHkRNMI6hEXdCNRREQ/Cu++AwI1LEd8iPuRG/IirMRr8I55ETRCKf+FEgjXLATQIz5EYECMfhGUIi/kRB9wgFEVeiPlhG0ZCN0cuR0SSQLciLmBGSIjT4RUsI2mEbIiPEBG8ABJARfkIpFEUoiJsxHsIj5ARiQwjFEcoCMZOGSdDqxsm2RKLEVrCPXAAxYjN4RQ9w+LEZ10MAmGTdcIDsNWIphESMCJfRGlYjzkRH8I0EYZtiP7SCdYiJERxyI4rEXtiP+RFlYi3MRFWImZYfRcgQoDbYi7kR3WIjLEWfCJEBFNYjjURm0IrL4dt0JOxEFYj2XBPyIygEdZ4OgRH7YiEURxwI8N4TLCKQRHNYiUERE2IpwAHBiMqaEPnCEUhqc8QT4RLcPHBFoYjJwRzTwrDEaYiKY+H4ZBGv0HGIgjEbKCLExF+YiZoRvGI6VEeOiLWBGI4iqMRLiIpqEVYiIBhH+YiIMRXiInt4cyiNy8Hb8QKcRoqIkd4aBiIlRGdgjS5hfGImVEWTiNf74KojhMRK0Q0TEURiPExFtoj1UR3YI454caMOAEzyYjFURXSIizEYaiP3RGQ4jWkRxowowDPp8JlxH1IiroR86IppEclcL6RHAfDNIRDVsXL4Y5iJfcE6YjkIRLCI69wAdiPGxEGVCIKmXmIndEdkiKohEP/CPsRwaIs14RRxwNxHeYjI0R7OIik4ZJ8JnhHi4i54RYMI/IEaFiJj6E8kC37hrkkNZEfy8OK6SbIi7gA2yIqVgBTMMbRKMoBzicl9wwrEc9iIuxH8IiDgR12Iy+EdeiOjBG3EVNXhuyUHbEfCCJKxFXYjzcRKiI8tYeUOVjxF+FEc8RwsIhrEY68PexHlYiUQRZ2wsuCBMshfUAMiYusR52IgHEdX4KBxH54iQcR8iIsHESNiICSCGYjknBrIIq4EeyCMI+GVNC8Ng1XQvDoSTEJuzgoYiBQRqOIolEe18OAlKR4iyURP0wyJ0L6Uk6hHUoixUR86In8EUBcNIxHVoiAIRDiIzDIZNNgnxGU4jaMR1OIhjEbTiLGqH7gitSh/GIzx4SLGkqhGcYiVURC6I0/EUVkLIxHxoiu0R/vgZTNLtCM/BFu4jxURHuIyVEV7iJBhFlQj2xhxY6e5JALiKB8G5witzhqmIozEcF8KgXjv4iXURtuIlzEVQiNUhGVIiKsR7Yw2nqO9EN+hGPoi5cRcBIivEWf8IPRF+/Dk8hmkpVAkXOWl7hG/ojPbhryI2d4SWkAIJGG4iRMRIGIr/EffsN/BGSYjvcRPOItFES3cPURHwAB6QhQvgni4cvCOxTrIYj8URU+IgxEalCIwxHGIiMcRIuwveEaxVG4JGs4irQR6+I6xEUTiIjhHb4io4RMkwrgkWyiMPxGcojdQRkhImnEdISJu+HMYjpMRrrw3t5BFwHwxFdQi2cRNBI7c4XQsLGqFP4jGcR1vQ+5MEJiNdxHMQj3cRtBIzfEQFiKkxHQYjQRh9yufnETnCOcxFgEixsRKiIpwkck8I2gBaYijcRDSIu/EVriIheEeEicsRjRw7I/GS8NPRHOYiykRmWIhAkS+8NuxEaTDbnc4RIogkY0iL/RFxEiiJhpNEF3ER/iOsJGGEi2zhZ+IlOETviN7BGJoi/cRCbw5kIdDCJnOEzlxKbhXTwxbETmiIEJF5oi58RpKIiqYHaUPU34s4jb8RvmInlEeoSKVBGyEjyMRZLQnErGISKmeFH4iuMRYGImNEZ4iM0JHQYjUWhg08XHEfoSIkJEE4i2iRlfw9cEZ0SOfxEToiM2AoVoFwkZkSNJ+HC4jCcRsxI3IkYFiP/xEFIiE6ilhIm3EWZcNcxFp4j5YRtpw/JfCsSJgJG6Yj4CRFSI2IkTXiOqRFmqgMiRFxIk3Ea3CIMxHgEi+8Rl/wpurKZiOdRE/ojkiRJBIk1Ef7CNCSQPEilURn+I1QkSfiPaJF04jtiRjBImDEf2COTRHMhClIhSDwtSasWiJ4JFxeDqiRubwmCgEISMT+EqLCU+AiJI8QkYRiMsxHTQjNiRj+I+YkWYSLUGbZ3ClPC1GIjUoVTiIGJEc4iTwRNGI5Qkc1COcuG74i0xAEt0BtEZmiPY+F34iN8RyBwjokREiJYxEv4i/asg/iE9EX9CPZJFSEiCSRDRQvIkfNCPXRHZ9dNPgroI4AkTO4NAJH9widcRJ0IqI4fiewFJHoEjYCRURI17EamCJuJGvIjjDh+NOBuESUiMiJHnojoiR1xIgvETliJmWG1tggMRBxI4gkfDsNSJHwrCy8AX6Ih9Efl8J8xE2EijCRF5w8IoWKSPIxHzwiYSR8AAMp4Sm8MfXx68kkSRL/glEkVOCPRJG3VBUThMFxBcEWQ8LxxGXEjQkRPGImQkdySK0JEo/C/SRu4IqqEafkK5RHTEjW0RsZIjQkZSSK6JHxFDVF0V4InEkfjiPWJEzEi1wRJhIokkZfiMKKE3Zl3wRhjwwUka0SIzJGMYjJkRDBI0nEcZiIjvI2PC4kRTmIpTEfLiJUxHBEivUR7Yw9Bzq2SP1JEdkjMCReeIoIkQqSMJBHtjDMyAUCQTZOORCL8JEa4j0yRQII2yEYgSJrxG0ZD4xkY+gKcka4SMHJHqki1lh1pIpckXJ8O66QpPDpyRVBIp0kdkSI8RHgkiHCR3Vwgp4bMiKKJEcgiVYRUUImKEXFCJX2EumAb8RKOIvgkbrCNRJFo5tmbhBaIwCYc10WXxHkki24hA6IoskXWSIfxHT5DTCR5ZIhuIb4KyfJEzfDsyRtZI+/EWCSNyJEjEjzyR3AIyzWB1CN/JFP4jnSRORIwkkfGSNGJGJzDylE0BIoEkVkSJBJHcYj6yRycIiEkU2SKs+Hbl4loRMpI3mIXKSMDREO4j08RZFIo50rhSPMxFqkjDSRGpIy9EbRSJOJELQj9f2FBIgckRgSM3JGBEiXHhOBIoL4QXMIZcLcUjLSRPxI7ckaQSI/iHN5VRKRNZItCkSeSK2JFnkj5thCaIvIEWFCK9JGj4iBIRYMACxEc+SIzir8Ei3yRJiI4QkT9MMNVhNeI+vhUZI4/EYRSKApGrJCQKRkJIhaYZpSICRFKEjUyRKhIuckRySOHOHDEioKRxJIglxjygjspEFkjoyRhUIoikXGSO5xGkUiFphJuaTJEY6SOBJFOUjhSRJZIt0kSRSJ5JEyYiV8hr1hSf4cUiLEpGmPCGdhrxI724bBCI4kBFIiUK4ERIjckSxSPnJGdAjFyR2pI0U4TX0SGREHkiDHBxuIxpEabiIKpF/Ejk8hVMDEqkeuSN4pG5UiawRHpw/pEZrkO7FZ1UjViRZlIwYkRJiPsJGNkiYqR/eIxWESwSOmcH0hCuQRiyItqERVCNHBGRkiqiR0+I3NEVm0BDJFGwj2nhxwxfMkS0SLkpHgYjSyRmFIhCkV9CPGeH+kiUyRkRQujEUqUIipF0EjXKR/RInMkamkPahFLUjTKRVJI7/EZziL/JEk4i+qRm1I0aEcVQA/BGyUjjyRq1IqKkYpSLn2FaoiCchi0IqskbY8O+JHJUjEDhqVI9x4WRSIBeGPUjqyRqpInykZdiJHJGCUjwfhp0IioWPuSJ4pHMUi97h+MIl4kd2SPfREnPDHoR8NIpKkdBSKapHp3DB4Rbsw/XxJjSOepEEUiuqRouI+gkX/iOspGekjiiR8AAWpoeYMJ6dDnUipqRL5I9DEXpSLmpEEPC7ShP/wemkaviIMJHE0jqSRQMIrnEbdSITJFTAi6aRE1IwJEaeCKgpErUihiRdOI+CkUpSN5JF2ookkkyZI5akS9SIlpFrUiAqRd1IqYEZZBH7JEdUjLqRthIzkkaeSN6pEC0jlcRsQAjWkUkSP+pFbkj2thJqI8f4X1CCNpHg0iniRyNIs3EdliJ7JFFwizNY2EANckdlSIapFI0j9MRdtI3vEWlSKdxE/qpCaRf1I7GkSkSJ3JGpNDI9gftI0KkfhSPCpFqEiRSRx+Q90kQsSP6pFoIiqaR7Lw61oWR4SWeS9EjtKRdNwmfEfrCLqJGfkj0YRRwZZokRdSKFJGR0jIqRwFIsskdZSNOuEvIYJiRLbwsWkYrSO6pGS0i3KRoFIp2EeVJArpFskjoKRzlInc4crSP5pFYUicChhzVfYkUTSIjpGgkio6RDhQ6KkfrSKLhEE7FpcRlFI174W4SPlJHQ0iFfhI9Iq6cD3SOtpEVUjniRntIwGkfj8Ks+EpwNrcRjxIxekbbSKqpGfYizXhV3GX1EV8SNlxGI0ip6RiuIoFEUc0IatqAkiw6RaxIvEkcRiNgpFvUi9aRoxIymkc30OUBFXDCk6RamnebEb+IBDxEwAiBXhKMIwhEfUSNU6GRnDuQiW2Ikh4k3iPSxFJ4jTkRwOIr2kUDSOqRHTdAfsRXyIv7EUViJbxHJ4iuYR9tItGkUc0OPX4PYiQGRZ2IsBkUgyIgZHt4ioGRq9I9BkQBJjgZG1Yi/4Ru2IqFEX/cJhRH0gjQcRUgI8HEciiNRpFqYjocR+HwheEQNkOKBG+ssc9SZShMiYVz8MqBEbIi4sRf9ItGEVjiIt2QswpVCab2QSBEeQyLwZGNYjU8RzVI3XEUXCP52xDWJFXUojI8FEfViOHJGV4ipGRuNIkBEQZUPI2DhXgDTAmAMMvERzCNNxEXwjpGRDkIhFIVoyPkZFzLBFGRaWIiFEV8kLbxGSMjqGRneI2hkd3iK1JF/Ein6RQ+I5kIQAAEV4SR4iw4WkQGSOzRHTUiaiRs1IrOkdhiIIuFGLC8ZwHNI5ukeLSJrpHt0ix0RqtImZYV4yO2pF9Ei6SRnVInmkQyiIpJHHUjY6RWXwqKHLGYxYeEK0juaRV1ImkkXzSOiZEC0iHNhZsOUGkb9SKvpFJMi8mRvNI5dEQ/SI2pFWfCMWuVtIo+kYcSPtxHV4jCqREpIs2mKuSKepEL0iAiRlVIpxkbvSIz2EJUJQ6R6uIs9Ee7SIXJG9MjHcRMywoJWIMyPbJFu0iT6R7FIqHEa8sNMiGkh1sIR5TIrWkS6SPruG/4iafhtTIphkdcCOvJHwAAhFht5I2KEfFCJLSFF/CfGRVHwvxkczSMCZGY4isoReK6UOYdN8M5pFTEiAKRMFIgekdNMJLpGBUi2Shv6pZxETtSKaKERMjSaRR1IxJkXISLdmH0Wl8kS62NcJkdXSN+ZFzEj1qR0tIxYkR/gDJVh/fC2yRs6I6gkbkyO1pEuUjdaR5NI0ikRfsNx0IJh9EqRxtIk94VBCLmZFK4iFoRnMwOFkQjSIhpHIMjrMRo5I2hEW0yJZXQOsA6kR2mI/wkdjSJ6ZEmkivUR9AIuOCPv8NKpEgEiDSR7hIilkYzCI/iGZc02WRVhI6+kXbiJjJF+UiyaRmzIqFkXHSJCxE3AjBrhfQw4oETkoTVwAkQ8uGRglwnhkbFiNWxH8MiEsRYrQjIrAVYLr6B+RlsGRVjI+14X1iLUZEMwjDsRjtIrVkcGFwsZEJ4jm8R+kIlRkYq8KrxE3Yig6RyqQpzCFy4gMhDYVC3IR4jIi9ESgyIIZGmvCpehVlISE4gmmT0ZE9YjpERb2I2FEXIiPhRG9YjFERPeIlekV6yJcZG7BD27h8OI+v4YoGG7uEVtYv6RVQIn+keHiJHuHqsiB+h4CSHCBIsQCnuFiMjc8RkNI1RkUyyLRpGL/DXoatxQcEoHmyPLxHWsjcARRbIxhkZoyOZAQl4iDziT2Iy1kdZCKwJHVsjUGRtbIkxkfWyLLZHx4iEGRieI3BkYy4JsZGFsiO8RobIhREXQyNGxHcsjbMR0bIxn4YUCOI+GjUjrnBkPUJowHyIGTZG8MjVWRWyI/+kSTUOCZFyNIfiEYQgX7EVtcMQZFWsiC2RNrIw1kVUiNkZEAK58sR8DIvdkX2yIPZFksjIGRkbI6FkYPKnaxEHIjSGR/2I69kRIyKHZGesj72R4iqJoEfbgmfZH7siW2RgOI6FEUGyLsZEjsiu8RAUI8dkdPSLoBFTsj+rhhQI0oka1SNSXiLsjEDAokI5VkStiL0BFqsj1sRRpw/dmo+yMexGgMi9WRVgIg1kTWyIgJEDTCyeI57I39kVeyP/ZGHsi22RH7I/j4RZnmqxFYMiK2R+jIpekYYyPUZE8sjWqRKmQVYQKdiPo5EBsjB2RR7I4DkYNiIQRHhsixmRdFI7ZkYPiJjZGFAiZsRj5wzEdghyM0BGIwi8ERKHIvVwdvCPXZGEPDN2RW4vVtcthyN1ZHKMiKORNgIu9kTeiLPcAFN8f2R/rIl7EXlSKoZHtsiICRtGQj7vM8YTU5GccjDOR/FInjkSZyLeJEgfDzOR7HI3dkYe4JfZHkciKGRCNwrLEVLCJoZHDYiwOREbIhhkaZyKg5HneChFhQvgsUYZ3cNOlogwAljA+96LNEegMPTgBGcBUSR7cQUmgnhcN3hEMTD9nYrWwLfkFS0P2bwRcBOOglhwg6kXYSPbOFZcjsyh6TIz+ESo6DS5Gh1wMuReLeArkSOLnDBHFkjDqR+XIlQANlyIBZETJCkVIpYoUasuVyJVUIgwBqR4HtwiSkebSLoRGTilWtgrXI6V4dBAE65HpzCAaR/nI+zkaAiLSDT9ci/7QbXI4qIh1yKdOHvfC8WRLTI6qkURMOn5gtcjpuR0rwubkZX0MghH5wiIORxjI9ToagoCZuADoBqZhwAw0yoalMMqZG8pDEAAK4ADTYFAAHy5HOOCLqA7lI9vYcUeBE2AZEwFJhgbQkbkRvUORZEjVCUAAl3I67kbdyNOmGNciNpqtqjVrYEdyJm5EzTD+ehZ3Iz7kVAUO+5FXcjlwAf3I1kAPkSNYxE8hCFFGpXIl7kUJMOISHjzD2rhG7Q6Hkb9yMvOGjeDbYAD3IrVuL9qCQR7rciH4Rm3IppkYtyLtZGSUiiJhMz3KbkU8ZkG5EnOCtuRe6IrskROyItxFETCJJItPIxpoDHEKG5HzcjtuR70I7TkVl8KwxpM3ABuRD8I7nkYzyOUxEpUixuR3tI0BEcSDizQDC8jrXhovI8nkTtyNPpEXAjpeRzfSYnkXTyJF5EM8jFeRfPIyXkUDSNARHciAheRJPI+XkVryK65Fm0jd6R+vItXkbLyKN5FevCFeRpvIgjkeNyMC5G8QjBrhcKQ7kETlNwr8Dwwjl2RKrI1DkWuyIEZHXMihjAqQob5xFjCIphGWMiNORN7I/BkfzyOC+ErNIPmkR5FbGEUoyOYRGMcjbWRxxI+Zkbp8LwrSB8i5vEwfIi1kTgyNfZHusizkRdnIqXkXJ8NT5GieAXIROHI0PkYC4O45GUciJYRIHIhxkb5yME5EtYjHeRkMIkAEbByMKKHYAtdVUkAI6LEchyNTZF8MifeRGbIwooeTKnxlTc8IS+R8fI22kUxyKNZHsIjxyRWMbdo0iUcAM5HgMic+Rt7I3XkYQyNLBEXBR++RZg8dTkUPyI9pEj8j3MRVjwpfkZPyJX5FWciZ+RO7g8vkTYCMr5F8ciEURiCI+hkSzyMLxH18j2AAbLwuNkd60PPXKS0AFWRnvIuTkS+4IU5G+8iZIRtOtH7oD692n5H9sijSRTyI+3kd7SNTOHqMEzWRLrIurEWvyPw5F58i9eRtbQpZoim0B1ZF78if+RrFIj1kRHyKeaHQCjZ8u5rI3tkc2yOfhEAcjKGRQHI4dkSfyLDZFjsi/ORF/I00kVfyMxRERQiw/hEcnDmkVH8MZpFo4i6PhLNI6xYdHUPMgBhMiLYRhZIm+kSLiMzJFckiVaRRTIgyoRQKO8ZFfMiaoRYLI9gUbXSLSZEE8jn6gctI7JkfnSJbpG5cidaRUTI0qEaXSIRSFNKMGmREaI8OkY8yNbpHGEj76RaLI1WkcaMMKoI/Uj4WRRPg6ikeZcKW5F9MiR6Rio4RQUXSyNnJGPMibORiPw3bkWOSKLhGKRJnaRPjwzekd0yKXpE70jxmRmjIxRoFMyJRCHDMjZmRhgo1wUfIKPcHAeCjDyRYVIlQUVIKJRZEKUiamR4rIpgkfT8JYJG6gAsrhvr9SgUc18POZHBkjLmRBlIjDkRT6QjJEi0jR0RDzI1gURsSKLpGWUjXmRMTI5PIbiuCYFFuwiHKRe1I8tEeZSLvpGikipaRH1ImWkSoYBkTjFCigkRLAooVkb5SIspFgJCrKRbzI/t4UYGB0FECsiKmRkPI10kaKSKHpGOEjRThs8CUwUZ4KMnpE0UifBRdFI5AkVFflGFFseDyqRTgo7ekbXyJQRHtjDqMgk5IhwUV0yIZZHOCilhRrSIszkUh3AYhFY0jkwRgdIqnkbCcO5VgBCjBcRiLIvukRUKOeZHrVDIMRCPInq4bh8IGpFekjaQhKbw5Maunkj7RH8gjkSRiQo9HEckKIxJEYcjLZ0froMkkf2iLXxGXCiSaRggomQUc+CLkFG/HD7MRLJI38kefiLKFHk/D+6RuQoukoXXSMhFHSZD4zYMIooEUVzSJBFHJMiR0RBTI2QUR0KN+OGjKUVSRKzIgukYiKNq5FhCiNBRw9IqlkZ/vgxHzZwiDhRs/wnXkUQKIdpHUijWMA9cIukUY4KM2FGLCj/+R0DI0U4fXTntJGUEiyqR9LIg6EVsKO5FEL8j4ihUsEC0kTiyMOFG/EjzeRyeQus2vyKJ6FGrMj0KRAwo96kcKsOUpGhQjJsRC8InBYaoCLlAHDZscER7fIjeEZ3yNXZER4jFORyAIjEnDEmC/cKfXCQ+RYAozzkRHyIv2Hmii6wkF1wi9kS5yL/ZGYCjNORXgIpkUWgyKkpEwNEgAgSfZVfkW6yN/5Ep4jRRRXrI70UTsOhu4BWijM+RuHIiuYYfyPN+HH8jyAA/HIggUdsKLPpEkCiyuhDswp2YTTSNUBH8WRbmReiI1DEdQKIzpGYYifhRoZIwCYcYjmTmF3MjQWRSLItZkZ7iJupGFMjO6R+xQwsyNmKIyFGpMj/mRpIoq4UUiKLhaHVCi1RRtQolfLKWKJBZHMCjSWRbAokVkRwKI7pFbMiZJh3ICPxEtiyLwpGCsihyR+JItsUTcKJjpES4i6ERniJBzABOKMaZF28iIBRq9Ixo4dboHHFFZUiORRwoorkUeuKNNeGszCIa8/LI12kcfSLw5H5UikxRKvIkREVrumXmGdIjFMRMzIiYUZTyOW5H7FDIqUt4o4ZERNCIuFHBCjC6R5Io9QUWKyJqFEXkjCiRqlIqVkTEENv5HznECxSMaJFXQoqyLi8HLYijRR3vIk0UW/yM3ZEpTxkqCrIotAUZeyIwFGQoi32RtnIqjkdGCKQlEO2JaaiqEol0UWRyLdFFh8jbGRB4oz9kY8LjwlFw6Zv+R2fIwMUYgKPn5EhiiiJhwYQqJwLAKLj5EBijT+RnnIuMUXwAATFGOMjgxRAEolSkZqKPQREhgBqnhsYYOkpNAcB26xIcjDRRYeIrvkfBKJ75FtQiImIuTgXfkaxKPzZEkSj32RdoohaESs0iPYTjSV0ARkYo0vkbPyPD5H0SjP2R0NaE41EjwCPhFkMjlJRmEoyjkUgKI/iEmKATjUfAIptkVnyLc5Fl8jAORf/I3AUfGKNP5ECcjeJRErI2DEQvCLrcFzsix3BKVoI6dhz8Kf5GwSj5ORa2IoX4YviPsiw2h9/ZC9koqMUXpiPAFHYSjgvhxTsErpPpTF4CBwCiaJRCAo3PkQlKNneHC7433AtvwpSUZWyPdFEEwirJR/bwnKUSwkBV+H+ijzJRA7I5yUUGKNclFcSj3JRiYozyUZEKLZBGw4jmQhrIQpSIaFyOXhG4Mp0hRpzI7WEXmKJmpF5vDCxR81IwRkQOR26lHeUjehRlYon/EdWKPxFEFCiVuRT5KBoUaLSLSZE/MiwRRbpIjsUfKsMR5E3wj/Zw80ozIUbiSOaFEziifxRxdIyFkf+KNdeG8yE5LynTIkkUZIKO/FF5ciKRRf4ozsUbFSIDKH4cRuhR9IohbkUryPxZFAoinCRK9AU6UWDSKYpH9ii9JRUNI5XkehCKiOGIdI5Ly6wo76UTbSI9pEuCihORIiInxMvsKKlFHVgijhRz4owHkQB2RhlGTijxpRyoo6OkYMKK2ZEpijKmhVTw4oEXB0N4FH1PC+pR/jIgaUbkoHnxENEjjYRAwmLaUXiKJ2lHTijb6R1wo0boYdKNulFrAi8ZR8TIptEVXSIrFFoyjkRRwgo+ukY4iPH8SUyippR1MozckaoKP6FF5CiGZRa0o2oUc2W0elG90ivxRZIoq6Ub+KKgxG1MjqkRrLI0pkboKLduHjCiDBRT4oowUVSyKxeazCjBRR5go7IUbRKPJZHWCjKWR4Fwp2EbbDl7cLssjVMAQooluEfuKKylGnXCHB4ZwojlkTlSK5ZFGyiWORnhQ5p2A7KIpeGfij9ZRgFIyoUejKNVFFiyi+JRGoomHESwyOxRFCojkDUVIAfUUYtiJglFSSjjRR6bI9DkYIyOtWwmNIPrhzoo1wEa6KIwlG/SjVJRBkonTka6QS7/zhiiU5RrrIyqUQbKLn5GeiiO2RtpI6ayK0oAjFHoCiHJRxEoiyUVpyKzlFfYigZcYNwyuUWhKOrlHpyiD+R1Uoj1kZxKKGxGIoia+RjUoqEkUmiKppEdSi/JR3aImY4ScyI+FGBkivhRtAowaUazSIVmFdD4tKRkxIgWUblSKFlHrMj+ZR9sIrgUQikPWOGfMiEmRpQo1GUfJSJWlEoiiCRRzwQzqKvPKPuZGLyjQ4RoIowcURCyM4FG1iij5R4qPEKkUoKKnFGCyiQhRbdIuWUXcKLulFHNDk52ZUAKf4auKPe5E40jR+RnhIx2kWybXvlFmCivBR54omIkX3KM0hHtVYTxRu4o62UeDKMvFG4EiN5RtHaXJQLSyLGFFOyjvBRGso3wUQ6yPvybIKi7xRH4oo8kezKL3lEqijwhRR0opqUQPiJalEshD2QhaccPDoXndQgpHRcjepROlI18kUkKJJlH1Ei64hP0wy+XLQqPLFHYijzuRuIo1eUTWiJHFEnjD7QOB+IvgUR7CIIVGvUiqhRB8omaUbCcMRIAcKi+xRu8osRUSLKOvlH8KjYThIToRikQ/KLkVFK0jX5R4pIk2Ue+8JxVhAEj6qRsBI52Uf9KMLhHUijsjAqiokBUZyyP1ZEXiiIFRopw5aJjJSI2FF7ii4FRfcoqrIRcFDsVE/yiAiR8Mo2UUSeMKg5iuKi1FRSoowhUX7KOIVGMyjSFRjwoqmkQAAHEw/hBScbEkQTKIYVFM0imFRH5IoJkZGcLpnhRKiJBRS0oy+UeCKLXlE3yiBvBP3GDEUcIqLTJHSyjWxR+0o6OkatKKH2HrSis2gh6OHJUTkyK4VF9CiV5R7QoyRUc8ENiq7TojFRRLYoi+Ua0KLhaEYyiIhRa9IowNFuiJEKRPSjeeRRqIyYURxSK1lE/TxGlRp4on6UUXKO1xEuyjjWRWso6eRAqKNGVFgyjRmRTio1LoWIyklFH+0jpRR3XIzxUb50PWNorKjzpRqSo1pUXOKPaVEkKj+5RV5Il0YcoCIQxHKpCL+BH9IpdkQaKNk5EhSiX+RYUopAEQrMOXbLAMjZgRFUogqUSpKKwlFqSitZRTyokhkdRKMclEZyiPlR9cos14f/y2eVHOcjU5RREotuURlKOLlGTKjWeR//QlrLj8qJilG6Sj25R2AolyUV5yPsZE+cjZYRRiouQEVjKPkiFh/CTdOySohmkTEqJoFFx/C6BRgcQB/oS5CgqVEpKiBBRaSojCkYoqI6VFjEiL9IGsI2EUfTiMcpH5KiWlRvsozmUc2KKK5FPNCN5GFKoheUU0KJplEDii9lR9Mo2lUYcqNRaFlypiRRvio5pUTiKKXRG3CitFRQEIiHwBml2lJH6KjteR/SojBUVMKKLhHkOCRlRMCozXEYyyLIlHZyjls618KIyfAKKLawBWyidVRIoovVUZf8K4oazKjYZRmuIjxUZgqPVeGOKNtlRkqoi6UTLKOkFGaKiPSRvuIoCUbsyIUiGhKjpnB6lI4eUR84HGpFbyi06RjTw/qUWiSOnlH0CivyRi1IseUZUqNZVHSqjwkRIqooJUeVCIEMDAsjGxRCtwtmUVUqImlHXUi4RRb8o7gEWdSJjVGUqjRFRGiog6UYmqIDlF5qiHqR+dKFWUYo8K9lG7SjaZRs4o9HofOKJ2JFUsjvqRxLI3pUUzyIl5ElyjCORC0IkGkZWqJJZHzKirFRFqosikWdCPR+F9qit6RjiowdUQXMIxpEVkFcFRqCoh8UerKKT5E7CjrJRLowaBUSjKL8VHyKjB6R/sokpUfcKMOOHNSitRRKbw9TXMBKUjlF0KilsRHfImOUXBKLjlHhSiMOR2L/HyJMnKNI5HoSiRmRtoowFUQASOVHRiIjm5RhEo+9UZYqOM5G2yjPHhdN2MhETBKV+VE1yj/lRlkowFUbRkJXqY+RInRRd6o1uUdYyI7lGZSiu5R3Eo3uUROqOxVEshClIhCkQqvIZ3cIqwh+MDG0RBKo9OkWGqPfJF4PDs6Rw0o7bFoyqMxFFZCja1Rgqo9lUS8yNFlFbqjyJRGGo4jUbkqJZVHeyinmR9aokAoRIqPXlFNcjMp4/spC0EXyqLGVE+yi6ZRzdIgnkbzgS3/I9KipZRjGo5eUVWKNlVFpIi6ERohIY8AcJqNWVEMijVVRC6ot6UXQiP24YyajS4RQzIixUWAqONJGDqjWZh8mOe9EcaqMtlF6yiyNRQGozf4cVKLrFHfA8NEiDpI+8UWeKPnVFGMi8aR+xQiX4BqqUs1F4KighRomo5+UWoKKIVGUijH6RnqogSUcBKOTSGysjNSkBAqcX4RJKJuVFnqjQpRaHIy9UYIyK18IlOAhF0hvw0AUWxKKM5E4CiEpRmkIyxYQcEHDFCvKiGORw/IxPkbZqI0ZEbyiIZYcmQH7qOlqJ6xGWCi65Rnao8bkZbiLy1GGsce/gAGoiFUb1iI4lFwIi8BRo7IniUYhqO81HByivSReGwMP4THUN5VHHqigyR3wo5hUQRqL95GG0sARR7wo2NUa5qMulFuqiS1Rw4oulUZoyKDqF0ajt5Ru1I9RUZEyP3lFcyjURRaQwk4ZLNqMLVGZqiOZRlGo0tUdRqLWBHESctVRq6oqVUdwqJlVGNqjISRWgo61UhKqOmZEGKj0FRimow9EaeyNRgiXaiZyRoCojoEeAqO01G2CinKcepIuZUWOqIWVETqjNGRXMca1UXJqNtVEyij7VRyzgkNjADqJ2VFUqihVRD+QzdUdbsIKJH8SjWtRVNIiroS8KMlwjxCj9ERhKo/MUYISIjVGkqjuvhXZAPmUahSMh1EUaj1qhtSotjUWiKJREB8yic1Ra6o4tUUUqNY1GZKj73BShYPHUfMSN2VGE6jhVRk2o0VURN8O5AQ6yjq1R+CozbUf4qI3VGBKiy1RxmI4DopOSLOlFWaiVVRCuI16UXdqOpFF3JFOdRBmo57UXFKIHVFJajRThZ1eD2UT+8MM1ECqjjNRR0I37UZrkKIuzVxCQZRouoq0kWbyJB1E9nCLbQKuowxwULiNG1GuqjQhR7qorlUSQKLZeGJ0jJOhCOaOrUkeqOC1HrIiveRYWo7vkfHKL95HpgZcXEt6o6rUQ+qK/VGfKjtFRYzwxwEXnKMg1GxSiriRKKo0zUW1CMZmDfzA/RRaUov5UeMqNIlHfqjTqRMeo0PUX7qKEBEwajIGRcGo+qUU1qKylG26jBrhxpQ8LESuKiDCDO6iXgRruo5/kWx4Nf5GySi7/B/5tIaxL7qIRVE2iiA9RT6opXUSrJgeWLiIj49RgGoxPUZnKNK1H58j4ihKB4FYFnHqPylEZaj1+RWWo5jkbZiLlFH96i09RDeo+LUYGyJRVHZ6j8BRueopAUfnqMXhGgSj5+hHMeKfVOJKLL1Gh4jdAR7uomSUZ7qKIeHqW5gdwwMqRSUdaKPi1HFaiPRR0KogBUc2qKdHy8AiDNC6eozTUZHqJA1FSUj4jAp8qE/UTpKMb1GJaio9R85xQ+ZiQCLv1HT6jC5R7Eor9UfPqMa1EIai89RLWo5hkaFiL92FMnCEdiUnI8oEdwyMklE76i7lR4Woh5UX8KLm8QzAjQVRBcot5UbXKIv1GYqiZ6R1IorGESRyPv1EvajP9RT+o3T4TSu3QNH5yi4tRABohLUY/qJ71GQCiyDRLroQg0f/qKwNFVSjkVRNUo1FUVXyPRVEQ4iJdRfvwpDUXjgVpCGKRD4oR779CukVQKPR1G4aj9KRvwowRkWV9jzpHcaiFtR4LI9JUXwqKm1FuzDhDRqdIyCkYtKIJ1F8ajFnhnKognkQ6AJwaB6EjT5R/Kop+UWNqKt1ETaiaxRSiohuITsMXnpEQ6ii1Ri2ojzUTdKIF1FkUjxui5xIwHUX0qPF1EDKjlhRnFIvZwc4aNBlHfaiFdRgeo+VUTgizfCBhfDR1RCwo8dUcnqMXSHcEhEiRLhoiwUXaqMhlGAsixiOURo6w0TzqPXVFtKiYdRLUI9UUeiiJ8lHicjAWRuNcVAQk8COClGhaikDRHuoiLUV7qJ436ueJtCQGfIquUeHqNbZElajL9RIRIwlkRD6k57paFBCtR1nIgxkaPqP/lGmkjeWR8kCco0X8COYNHD6j4pRX+o/w4d0aKaNGx8jT9R1Bo2fUewaOANGgciMVRPBooSkcvqNV2EBqjhR+HZQLZAM0kAKNGIGjK9R9yo6SEcpyOTo7+AizARfRoorUW0aOPZFIEjRThOxo6IEWHqMRVGQqj9JRdBosUUYUUIbhy7Gi31RYKoj9UQ/qPYNGDGi1xhoYeM40UQaMpBGZ6j8GRUxo6vkTMaPcNE7Cjl9RYSVHUUaXbBmqD5GjrlR5eo25URsaOQNFbGiHjh32FFBIL0aMH5Fn6jDjR1io6kUfCaKA8CB/59jRrRohPkUcaPtZFgUiz5QCJoqrCi0aP35GXGik9Rrxo6EoZb+0UqDNGiO9RNWoiY0Z3KPq1FuSiF9RoBopfUeAaJ2ZGuMj4AAMccKrocFyJTeERmYZDR3WoyeUcSqKx1HigjF8RLaA1Q0QYaJ41FMajClRbQo/IUSTqOJiFQ5Em6RWhoneUZTqNsNHU6jltRh8o3AYdmlTFNGcKi41Rx2ohNUazqKTVGgaiwMMVho51UUzqM0NEj/DPNRCso0U4eWOjHpHKqi1xRiuo6kUeVPFC+G+Ei5hRpqouckefqLbhH+GjdHhO7gfeCokaPU1FoKjnjRHqI0g0Q28Pu1Ab0jojRjGov+UZvyIbeHaf5L6RJpojQ0cxqLpeFpGiGSRcOooOURAaOAlGXeDZWRG/CWA0WsaPeBGbGj6Jh6MIzZJrRyJeVE0mj/dRJBo640YeKKLhEFmimDRSJo6g0e6aNYRFBmjGehHd3Cg0ecaI/1G0Gi6jRzLIy3EY2aKc5GUGizJRLBopFUR5yKANEMmi6pRTJo/40WqqLr5GsmiROR07IxeEbOyMwaHTjCMosk2QMSURVMJk5GQmjCjR0Jo4o0SgaMEZFuysFJR2koqo0RcaJoNEvGjm9RVLIzc0e+wCn5FYmiSTRe5ouiUWWaM/ZHfY5nMgb+onc0S2aP3NGXmjXXh15oj1jreaJblHVGisBR/ZoxLUb8aK4NHn8i2zRaDIpDUeXHDw6HABDg1R2Go0NUUTKPDVF9aiElRBuw0KnifKO1NEW6iClRsso0w0dNKNlNFjuDgLRJlItQ0ZyqNNNHxmiShR82ogHkXf4L52KwWjZFRypo+Q0TSqP1NEOGjaMhQP5WJEU0qJdVEIWjxtRASoi00R0qN7JHcnJgFRs6o67UY+KNu1EAyj8DRBeMFi0S6aLV1F8UjdVR9pooPUcevgI7g4Kj3xRT2ojTUcQaM1JGLKjdPhuL+US0RbKKopESWijiR2Wo12UQ2CLdKDtUiRNRRmomrkYhaPotH2GjdtRwSo+Okc/SOd5FnKjJhhllhOHAI/yIhNHb6iczRMJovM0ZFqOdGaf8iUZyp5o+AUeeaMylGemiAwROjIjtJP5xAIlGPGioNRn6o0s0X+aNLlGTDDatQNofa5ctWaN7NGkmju9R/lo0zkdwKKCtHACjPjRIsItg0fSaLhRENajpjR3BogE0cmKPHNFTYjBrhpZwxY0RWeXNCFUyBELoFlo7+kSuaIMcFV6j99RynI7BIGRkhSkAjshiTRTlo2s0XZCMfNHNkjdXokQSIvvNVaOLNG+WjWzRuBoksEfEUKv3hYoB720cVomo0TgaNmNHCIjurR2KNDjADbGRqtHpSjatRA5opK0YyaJANEjmiOLRcxojK0SwSIAADc+6olkYYCKPHlG+MjCZRFzIyC0VcyJwxG9YJ8VR4pouQ0ctKKQtEQij1TRJIw9a0cNqNZlHqGibDRJFo8RUWqaLqVG4DDQvEXWouC0ZpaN41HYWjGhRihotnUZ48IDYAHaikjROpo6pUeJqNO1HosirTRsiZR7UXoKLVlFKWix9RY/I0U4Q1cD+tF+mi51R8uo17UYJaPlVHkplDVRzYI7VUW6aIEtHkmi93hD2ovTUbaaPEpGG6i4jRjDwj6UU6qOc1HKCj4LRbKos00T6CN0tGw6iMjRzBIr0kRIcMGOF6w4WZRoFowxEeBaLw1EFvCUhRkWowSEQzqPyhHJGiqdR0poqjUXTaPFlGqw5RpRc2o75kXGaKlNHtiiadR5hotQoQMcD5tH/kjKbR8aoqtEcLaPSNGi2j0FeMuog8IebqLetGSmjtLRfOohi0YcqMlxGNgItbRE9IwckYYqKGtF4GihLRZygax1KbaPmFGciiwjRrlo3OodGNlXJF66jzFR/poyS0WxSLStFXiiN5RroCZGUW4qIDpHA6jibR3PQ57webKOotFYWjpbR+yoxM0S58PYuEPCiDLRJyorK0aHKL3xEmVAtkAngwbM0b/SLXNGwmiDdh+uuSV4fOmUctGTWi6rRG/I440Q6aMdq7LzABYR7+o5E0TiaOktFRmjeXmP6gUY0RXaJrNEomitdRNdo4ydGXaPrtF3miZ9RMYogmEd+aJ7lHzWjlLRk7Ipa0egiOMtHLOCGRBQeIoIClHKNPVHrGiSrRuZo5LkejCOtWwT3CYHwPbIt80buaMLtHtGiT2RWso+e0VniOGzITWiE9R4VogFUQ1aLNeFOvZJXh82ZfO0bvaOctFQqjOrRe3Ii8EYvbmy6Db2i2rRfrw740UnqJ7tFn8jwORl9onmESQKIAABS8UI8b9PYj0WxGcp4TgAT0AM+ULRUJyhFSWAKbRnJw9p4T/aKCR5cHDlOhpFw6kYdTaIBSG02j1bR78o6yUYRwSgdHlRD4Dht+wnIUZHaJIOG9TC8LR/fg9dQr/aLgOH/ciCDhYmoyaUWDyPllFKGjTqR4CJNB0TW8IwdEDnCsHR+tol5kbtMJOpENxCYOghDo6B0WtMMT2GkOjrqR5Do3NUV9CPUgrsOj0HRxDo9o4dw6PyZECHC+HRRyor1UQnaOmcGIxCcrRjyAOk8IbUGgOASoAXdRllojO0XvqJKNHv8jL90CkoiVAPfaM9tEXmjIrR9nI4w4Vo6OPNHRllT7Rneove0cBqIPtH0qiWiK3EQUx0aFaP6NGPqirHRZLQz1QSJUFglr9WiPzR8Uo5+0R5KOa1HBYjvJRXpIhSISnHG5NHUKiIvYYpo0Q0ThqI5tESGiixRGHIvxXIX4ORxGyGjiLRJ1ohRUWRaL0tEgfC+VeWpoxU0bhaKO1GA2jJpRFOolh0Xf4NQ2y6Ei4nRR1ohJ0dSqNOtEZKi5bR77w28lN4aNjNG3WjEnRBtoxB0UmaM+pEr5DleyfYAC1EWGaM7JEdqiDHRAAok40Yo5WqdHu2jEbREeor20aOaI8NFomihu2vpo/p0dZqKRtFaajwjRd/gxUHjGaKu1ESmiIzRNpIptwRGtiCNFmYianRAtolU0fU6IodGiqikNRHBIuR0fJSRPlFhOiwLRO1o+JUXtaM3ZGW2Jevhzbw160erqK0tF0WihbRO2okW0Z+yMOdFeUiJbR/Ao2p0aU6NVNHaGjuZRphQuhxIRaM0+HAiiAbRWaosR0cTqNp1GmFD4GwPFo84UdzqKBdFbaio7R/OolJ0caMPlmD1wjv5R+uo3+UbEaMGVHW2j0IAOnCSF0SaqL4tGNUjsbRB5ozF0VWsg6RFiWjeLRcuowZ0YGaKcdHyCjNz46lo9p0bc6NG5FUujChhA7cWl0f9aOVtG6miGyRhtog00UhqOyNHKpCYdcfJo450ezaNOdH4aioLRiWIllZi/mH0NE3OijDRluol+UWU6K+tEGmiDphnIWBU0ThaMltEfOiodRGTo5b4T86IxUAbKMlXRn1o460Z86IedHJOinnRawIze0ppiIUxHk2jH5RS8otzUcLKO2dESOjNIRH7bY00Qs6LtNFO2jgWhGxFVXEePSPttEOKiftRKNor00TxzgZVE53D9NRquo8l0QNaI9NH1miR7RstQ8Z0axaMWdHoujk+RvLowlqKGaNZdG62jRHRVTIiTUTbqMHtHASj6ehcjotsrJI+Af5GypB07RabIz4EdXqNQtEQpw0UgGII3R0VM6I6tGW2iZGR+Bo4t0c/QGpNFD6iDjRVdo5u0apaPzaQlui63RYxosK0efaKuNFdOj6DRvfIzzgeisExNH2OiuORj9o99kV46IalE+Oi47RkrI3ZkQAAC0w/hjhgo50QkKO2tFxKjhXR5zoyM4WaYSudFliiiLRWTo4F0VUyNBdEVOixAhvNWV50ddaMwtFS2jGHRc4o4pUUa6K+xEa7RD3R8Tord0bC6JZ1FmGjKHR3rQ3NaDi6M9lHQui2XR2To7NUcDaM0FFRHCYw4X8olcUai6JNpFLOjbiRP7oyzqC+6MDdGKWiKXRhsot+0cbKPlVEDdUSXR8lo4OgK6aIsFEEujGXR3rQp3lHJaIJtHuKig7RLWI2toZJMgw9Ga0jb3RvOo1I0fC6IvdGSOifNRhloxeEfbqMfOHA3BW+RnxBFR0UVaKntH6SAZ7RxCIq9UZo6k6NSvmj31RPlogM0S5aMJdGo2ijD8O/I7c0cvaPvNH6OjoPRKlo4mIcx7nY9GCejOPR75owqUXWaNQ9HieifZUAno0yUa5yPMdFTWivzRg5o7uUS/aMIFHdujCGRy+o71KtyCMbiqHqj3PAebo6SUReqPXNF+8iy+CN6o7hEYO6OxNGZajcTRrTIol0ZZ6NfVHdmiVPRNWo1e0fZ6IRlH5OivtUf6owfUe26IcdFN6j5PR77w7z0VPqJs9Fnmi6TRsGojT0fBqL7tHQ2jL+Rabo3ZkVAaP9OHUbAKiRVKIgV0bpSKXdFc2jJDRA2ozmbHyaMldGWujjDRMropJ0Q+6O+tHxsiMYC6To5V0e86M2dF3WivnRSpovJ0RF4PK4I5ejN3RNFoqm0R9aNLRESOijmhFUSN10eHaJPdH3OjiPRnLohw0eP8KbdQOujI3RTro3j0T66NSlROmizXR4loj20eW6KGdELWiYaRRcIpDGvM6Km9EDOjg3RKNIwL0b94IbRTxuiAPRgdo9ZUUbqL1mEKn4lvRgQosB0fS6L1tE9ei4XRfXolJ0cJyMytGS1D6vh+rkfpoAcBHBKD0eiU2RxVopj0dZaNntGCMifk4vYFFEgJ68LLdGQeiL7RlboxUkVLqMX74HDAfvR9bo2z0SPqI89EbKjjvhemQIqYJQ7CXtHSeiV7RTdomZ0fe4Jh9FcoDQfRfnood0QlaIi9EzWihzRc1o1K0cM6MBNFxejpHR1sAap4eJVjyNFIlgTPRscogt0WVaLIWHe6i0Ug0Uo0L0bVaKR9HOuiaLhrDSXFxClKNi1E9mj/PRflo0T0ePqPxpGp6ir3ADPone0ap6Pc9HV2jo9RcGcE7AOVKN+9GO/Dh3RWEo0d0YvqJA1F6ejX6R/pwrnQmZaPijqU+jz1R1PojR0Rc6Jx2D2WiQrRwvotz0cz6NG9FuWjdfRy+JCssO46Nk9H1WidPRDEogIYdUxGCtEsSiMfR4PogY0aG6Ii8EOokx9AnlokAUVz6Mx9Gfmi59RkXonPUcyaMV9FE+jRORMQQlN4bIsUTZFUaANfRu+osz0VnaMSxFtNF68RKuheH0d5aJk9HvKjLHR1vo5B0SnyKsOhcoDc2RYPos80aL6KbdHQzDWj4DbI7P0Y76Nz9FG+j1vRD0uUKLNl0GL9EN2iO3R4XorPUX76OHNH4+i5vRPgIvT0Ql6OnGEjIDzMA4Joie0QgaKstGZ2ibLRfvI1CtuiCLbdE1+jufRFbo720ZxaKJdGD+ja3R7dooT0ZXaLs9Fi+j5zilPoO3wBUaIt9Ep+jajRvPomFUQMUO2mB2+BSQRZjo2k0V3aOSBHy+iA/RVjovT0Ty6Ng6FYy01fRrqgSP0UUaPUdHmeiZIRtt2dMTLdYAd9Ej+iG3R8/ot7UVrKIf9Hu+jPvonvo1z0SWaLH9EE+iz6RAyIoQyjAKK8tGYGjR/RD5otP0UzKOADGoCif/Raco6DUVj6Pr9E4+jNPR3josA0b46OhJHASinphOoo/OxK2uQWxHHqjo5RjHo+a4W96JY9FSGi2fRTZo1f0dgaKKlHG+iiARpAYrs0c2aLn9EQ+iF/R+DogX0VLoAwNFUGiO3Refo5H0WM8OYDGbAi6Ax4xog/0eMCKP9HReiOjRzLI5fUU3yI7KEnxs37h4xQa/0auaNv9Ex+iNWRLLefcQEhgFJoDkBiNdRlAYg+0f0yM9WJt2jE/RYAY1/0QwGPz9EReCwM4VI5MniNoGLYDHgBiRPRAPouzUd60MFt7FwBqXYjPoya0XX6J+NEN+i8fRv5ojf0bF6LQDEDyjdmRAAAchTeEJxVDrRqXoxhUb1qLOdHc2iLPRP0LQ60bl6PPlEq2jicRRXo+V0cA0JDNEvWj1XRFXomF0UR6LPdGy2jH3R+ToiVSPEGIBdFYiikgxKRoonUTKaLBdGLblXJC4NoqF0S5qMTdFWuiV5RKbohcUdSKKckBZwjt0RNqo1w0czyMgDHGYjate8NoiZ0Ys6JQ9FNBjgvh0Y2NkURjaPsVGwKivXRONo4R7EKijJtHDejCbRjAY0q4asHhGDFHeiLXREQY9l0cRSOjtFSTDY7RO6oshUSwSOqaEuzDnphmv4WhUf4GNiVGBBjl3RwQYnDEVz8hkVFZBjSNRJ3opN0SkyN4VFtejSwRmwYppofZSMydFNejIgxfKI1IMcV6IbBH+RAjgxurokp0Wq6OODFnWjHrRY7gvSxGYqIRZFvuiygx+Xo9zUTpaJ2dFJqjxyR0jof4MRDaPNtE3aj+7RMNo6kUXPGihDG6yig3RVbIkzUVQGMJOFdKkfFRbQY/tUcjaMGDEX7lcjAD1FNtUeGaOjdGLqit+REmuc6EYQSMO1H3Bi5gxYuIi70aR6Ku9EsEiv7Rw4I8N0S7CJ6lH03DF3RuwYjL0VE6I+9Fgb5TYRXGo4p0YR6NyDH3ujkLRBQYt3QCyGI2tFvOiRFRlXoup0TLaIetEoWj1ah+4NTIMe8GMFDGC2jttRhropB0dRyLCTrFBiudRpQY04MeUGKBtEHKjwQxRVIko8tqGNlJGQ2jmmRAAYyXUY56N2GCGqi6gxfQYs1UTbKJZ9EDzCQss4OohG0ZM6L+9ETKjXAxnRoxDEUUCCmDGqyjpvRFoY5v0V1aLJqGexY/QxOoY470VK6NotEmGjQQxbXopDUcr6MfOFYLpkvRk+Iz4URyGKnlG7Wj9gx5Vo8GKjq6Na9EfBjmdR/GozV0VGv3EmhleiOURNXo6kMR+6LEdG5OiuVRyeQ0Ivg16K+DGGGi8vR0rokEMQa6OiDHkWjqwxGD2Ib0dMGL1dGfBiabRYIY/r0UrqLlyQ2miiQxHTohl0Z0GPbGE6n9OvRX2o0I0QMGPRDHNOirqeW3o7EMb4aNxDEu+jF6hfmVQ70f6GJW9EvSjx/RQlIuUUUyaHnDEAhjdQxkYY5r0dg6Oh1EkeiNQx+loyd0eyaIAAA6l4Yo5kcNkNZtH8mjUwxgpo9MMZl6IP1Eg6k5Ly4gom90WWGO3dHnBjd3RaQYobIf5knJ1HMqj4RR8oIo8Mae6IbVHnuizwxJzwongnaJXxlEbaicgxqoYvIMWraMadG1CiI/y9cIhCEQR6K/DF3uiTwxdIYyCMfaKNm8KSyi6XRFtorcMfN6ObVEHpsCIxPhoqcMX4aJnDEBlCEp8aEYt20ct6PdDGrejl6Ry4Y2G7BoSSWZEIejEeIEHoinkUGGKvtHf6j/UqwMoqJ4RpaL1DHAhjrXRvXohp0THaOTNGZGivSRsQAFN4aeMNgjFs2i0vRnIYqSEUNKK91FgaFxbRcEY990d+GJ4VG/hjngxszo2cYfJGMrpE3WjpQx+ro2UMd86JW1EUdDxVYitowF0ZpGKwjGNeiCeR19JUNlOhGKEjGHhiHgxorI3sMQi6JsVF7h5QIRQ4YvOEYyKNHDE2KjNG4dtopD0eGaI6DFehjmRRRLotivI/6JdpGY2jkPR5qozgMeZEHSJGm6jOIxAYY7iMXCGMLxGJzDoB4puoky4YCGOEjGNhjRIx53o8SMYsGMkjEM2iqaR0zgg5kZa0LABF/XYhFR0So8J0UK6K5DEqRiD9Rrs6N4MTmGJVDFbOi1QxLYYy70e8yM+hQr4iWNRRkY+CMW1GJSDFyhjRQxXhAcqwM1GO2lH1hjZgx5YYnd0fkGL3dE1mMd3EwGKDCMRHaLAjHYRjCoxEMw9P0bukIVphIhjHZRGBIoiMZaGIn9EBGiiWRpUSd10cFGN1tF1WiIZRGLogI0TTcyxDEMRj2gxcUYvEMQrsUbUDPQiA7Rayoom0Th6LcOHD7hroxnYY3MMfA6OBhGrRjtZhgcoqSMRgGNX1G/eCrtaJeo4z0YVaOe9EEBj4ARffo970Vl6I7SwD6iHjROgYp30Y46P8jFDKj4YxIXog30X/6IgDFhRivRRCOIlxugjGJc9FwBj2rR2MYiwMTlqM2VGVooMYx0vojx0XVqKQDFReim/RaUY4gUUH6MnNF1O1uQR5HcLM0RDGJXZGa+jlIxsMYg4McF8BSxGExjwVRWMY8wMcRGKttGo2j5PgtAYlQMV3qP3tGdBjQNRXCACzkXRyJz9FM+jG3R8UYpJ4WN3AljF7+j4AxPvoyY0U4GJStEuBjSYxjMIpDUfSEPTiGshD6QhggQzyYaIXEw1GZojtgxRKo4lEUKaIXxG7IiAu0lsYlCkYzqO69HRhjmwxIoY2aMd8UIhMqshj6NRwEY4Vkd2GIWlFmRjzrREvg6vUje8iutGfhiloxZ3o4UMd8GPlDHW2AbfaSqoxaMa7GIK9E2ui5VRY3ooYXCABVU1Hj0jkoxO0Y2EMTF6PqNHX6jug4mcYkI0Q7aOnDHqBjCWRpwEf2Ur0GIojElxiqIx5foj/ALC7Ec1EBuizbRG4YvyMTjGICtHf6iUOmlcY79EQm6NyjFRhjk4xYkY9yMfSGOX1Fn+iBvBsJURNkf2BQ5jFu6ib/R0fo/v0TJCLtVgl4ivAKGsY4mMcLGL2jHGKiiXR+TSC14Q7ExMDFe+jkYxAXomWMal0LjTgLxjx7RmMY5eMTx6LrjEZFZD4xWyAPGtJLGMANHqejaYx/vooQMf+iPmNFUejlDRkK2FY0W8ECe9Gcxio/RWvou/0ZuyJZsCPiROuKiMY0wMboGOd9FlxjSIx2PQD40UvGO49H/eiRYxwYYxdIQR+lMBFAJid4xpfo5WMfdGJ2TpSaFnARN8YtT0b76PvjGN+i9YxsCYy34UCaJfaHIG1JAxU9wz+MVPGJkDEzxieYxFzojddLtkQDxrlsjFYxBdosv0ajGPXjG0JjNXhRIGLBMRwGLxDF1TEjAxyShThMcwmLbjFRWj5BRxvgdhMah0BPjEP2iEAxjgY3BMc4GNftH6xiB7R7gY45UTV8MqaE+qihFhiDw0n0SmqJ9jE1RiTnR6Xo7mMZGqIWpEgOiJQxGkYoEMXlGJqVEzRi/wxYzwoNUeHGMMjHHujVXReYYhIMd4iODjFrPCQ4A62oiOMUnGKbDHtRiPYx5iYj5wBWqPZFFUhjI4xbsYgeMba6PUlFMyUE4x9QY9tUSOGMETGGOju1RO0I2xompqIXDGURilwxYCYiKMcOqKNVHFxjPXRtcY/eMW7MKnVGfaiwkxxIY7D0TG6PF9GIOJUkxicY2xMT9GI2ZGDxjIIxDIY9BEaF4JGuHvk5eEKnNeZo0eQmIr1HT2iiAxOyIj70U6Pm0ZFB8j+ExqCY6iMbRkI6TFmMirGMlRo2f0Y3aJ6THnxjjqhGYUFYFkB8SgTF6Oiz4xmSYkMMRMmP5hEz+iEfRUCI2X0RXyJ1jF/Gj6YxecYkQMUzGOg5GLwi2/RAio5Y0Z7Kjo9Fb6iGPRvfo2QMbPGO2NFeA0tzRynoomMdAmK7dGRJjunRJioq5MSY6Kk9FJ+jEfRoyYuZMSs6PeNG2OjXkxSMYlBMW/6JVjH1JBvkxWkom5MYLGIz1GSJin7R6yYn80bImIITHv2idkx53gsroSKAGemFGBh53RaOo2qMTomNJlGsKir1R8Rgf50cqGMwjHJBjo4x5TorxMTNgBRTHXujrExpYY/xMf3GMGjFBxifgxLuQ9X6qmqJI1Fnyj6MRfcY9xMYhGMedGVJirgxfxUMD0WbqJrVG9xjQIxUcYlaMRUmOQjHrRiCPBlLwblMdnGLYtE2aitkxxbI0U4SzoDR+Eouj4kxNcYxJMSwmL49F9sl8PRMUYkKMXdGJYjG4h14VC6qYul0XxSJJDGABirHh4XYPVMT3GJcjE0hi3IxsYY+FMU7yJkdFpojZfYjwI3N0ZPGOaTGveiYYxxAYgbUXiUH8LaImjxExMyYmBMavGJIjHrxiPUxUII9+KEMmOWTH0BjQExnyYy2oew/yH9FLJi3kxwno2ZMQ8mJ7dFqNCo0x0/okNMbGmM7tGrJij+RUKY3u0ZsmOEDH/mjrUxDfIy/wcPaMiyGtwkzqAVyo7v0SFqKhjH8/DWkxUeIthUUQVn5jG8Bj2AxAiYuRMfCGMc9GQStnjC+nI6ZMTN6JXjE8RjLAx3+o8GIvLGKLNGMJiz7RXCY7VMXqkGo94dYjWAxyCYpy0Q4GMhTHSJjdYxMKYv1MS36PzTHKwjyuhs7o1f+qjqNzFFiGiInRJKo4U0ejCN8HLqRjXExpSYlr0eNGLldGthiEUhCRVA9MeSmLuDGUpjWUx4EYp4MTEGPOVG6CMrIx2QYmyMQSmPzDHmRipDhCGQEXUea6K7DF2JjzTRf0Yx8YSKmLUCEk4RTbREqYsXUY0GITTEbiiNVR8lSIKMXi6KFjFQejm0xV+o9eMe5lldtGCRj7QxWNorVMWMmIUIr+2jtvRL0Y8YMaSwBZ7g4Zif0x30Y49MeUmKtTEKJjVKRvQAdwAH4AH3AB+AAFHBuNw6wAJlABAAAhgAHAAyEAG8gFhsFDjgEABkNg+hFdgALiAGbABGTDI443AAJwAMy4KjjiIQBeeAT0ATQABJmKTwCYAB74AmAAeyAJSRVySFGTCFHBqAAWMAOM3hTKEiU41tgKZQj4oYlABc2AplDUEhugAXTMamUK2ABVfBVThucQhsNDY8FVOFbAAVlkYFQrYALJgGA+AplCqvyktwVU4bOyIn+BHbAUyhmKFD7ECmUPxVxHSYMfBvRQ4zMSrsGxmFbABXPg0jgtBvNQwV8zFVflXHg0jgzFCid8mkcH4q5x6AbmYs2Mb1WV0zFSOC118JhsUk4NI4OytFbHAMsxIlOAs0NI4NQSHvDJtNgewQqzMa9sCw8EfFC8VQWHg1BISGqCw8FoN4FrgzhwrYAEBKCw8HRZjjNgWHg7zMRDsBb6GzsjMtILfQ3OId68Bb6Frr5yQAumYmIISJTmGeAt9CPih2vwFvoagkNPOAt9C0G81ZIFvoVV+X6RAt9CmsxA2Yl44pTsAu8Gzsi0MQF3g3OIQKhAu8GpZiBsxoEQgYqBd4I+KHMYhXRhWwADt4Bd4LQbwlCgLvBVX5AfYBd4MxQrgpgLvB+KuRrYHsENnZFeag9ghucQjQ4HsELXXye7A9ghIlOZ9EHsEI+KFywABsxrDI4sgI9mNmcFoN4Ssxszgqr8gXWD2CGYoUAsxszg/FXEBiFKzGzsjkdgpWY7rMbDmP09HFkA2sxsKQobMcocFKzFlZjwcxVsALYAPByFKzFoN5mWwpWYqr8m2xFKzGYoV+pQFWY2dkfucAqzFmZiQcx3nQiriANmIzdG7xgKsx2mY8HMb5KP62AVZiwcxw7wCrMVV+URQAs5iYcxmOY2R0U7iGqzGzsi9Dg1WY3OIfzZmqzFrr4RBQ1WYj4oYkgAGzFqxCtbg1WYzFClQqGcOHdZiBsxBoALYAFTCGcOEaZit9gzhwj4oTgiGcOETZjvNgzhwtBvNxCDczGqwiP2YuWYy/wVsAFxOBuZihwR4lwwBkCAACZtF20F7MxFrQtdfNVgDczHKAjisxGOwEAAO3cLXXxlgpStggeYgvUbrmIuzFsvDisxAWYpn4brmMD+Bh5jF4RVmY9bMe3cLmzHlZj27hHmY5rMe3cPxVw5loE8x2VoysYLpmOUBG5xC030GPg5QEXLmNTFC55iNMxCEkXPMaNmNlOC55j8sxkeYrK0WDmKVzGh5jpsRVmYyLMacqKszGP7Bc8x+KuYH5EW4KDzEdZjJsxQeY6XMfLmKDzHB5iWfgCeYvbMaZOAnzEfFDp/0JeYwoEflmIMzEt5jCgR52Y3TkBPmIFzHuwAC8xhQIjzMStmKDzE95ja8xfEIpHMcjmL4hHS5jKwQCeY+UAJ3mJjzEF6iNMxeuYviETPmIbgCb5jZnB+WY1OEGfmJXzFhZiz8xAuY37MXxCI8zEI5i+IRPeY74UAnmJd5FSWAA8xbLw6XMS9mLZeFy5j9sxbLwjTMQEKAALEz5itngABY1BIdudAALFg5iE5QABYubMapAAfzFQ/FxgAX2Ytl4dnmLw1AJ5iZWRTzANrMUz8KLzF2Zil8xMjo4PMfNmKZ+E/Zj78x5BY5n4bYIAfzG+SjRgwBBYsHMVnCAILEC5iTcxTPwjzMarmKZ+HZ5ihsQCeY0+odgWJxzGxsiT8xJWY2NkcHmKhzGxsjoCx3OY2NkaNmLydACFjECxJmY2NkWDmOGzGxsiP8xYhYkAEdFmMekBuZiiPhxWYnHMWTcOKzElZisURbeYgLMWV0I0zHXZiyuhM+YnbYKQKOZCGIFjGLgNhY+AAGDmLILFFuCyuhc2Yw3MfBiLbzH6FjKmh2eY0CCA4WO8DER5jucxZXQwC0dgWMezGIpii8xkWYsrocm8OKzFtZiyuhq1o3XMY9yAcLExCifusumYsroTJGIjzGhFjKmhcJIqzMbmhAcLFrBi5cx82YsroUPKKcAQOFj+DRghoqzMU5mLK6H7OiDG8oeYyosShqLQ1EkcBAixlTQtkIRyEODzEU5iyuhNuY9kACkWMqaFlRjooRhzI7IsV4WJvJG9FiKoxxjgvXMe0WOGpHS5jJcxZXQnGUVZyi6LHMhCjYxJsYxLMcWQFPzFTFj2CRExYxoscyEPa1FWZjFHgDhYkfERMWIDzFldDwlRneYjIscyENTRFt5iYixKaIip4dMWIVcQY+CyuhSOorYsecWOZCFMhiRixphYypoc8KKszFE5iyuhI1I3A6jcWMqaF1fDT+AxxYjk0VyaPqLGnAAXixzIQ/1UQ6UhcLGVNCfSR2RYh4sfAADUTECsFZixcJY31UeCWPruAOFiVEx8JYpYsbCWICdFBOjjHBF6IBwsR4yKTzHm5iyuhixYiOmA4WMihFDFjh8xAJY4EscJgERLFpijnZh0uYo7MWV0IzFGKKFESxbUooose9mMHBHD5jYSx+zIiksUnmNBLHwABQ/hVmYjAsTUWMqaH3kjjHBuBwBwsVoiLbzHrFj4AA7uYnxQPsWMqaEzujdcx/vANzMQVMKKmFBZiSsxmcQ7OIdLmJxzGf7CJwA3+w+rMdzmMySHqljcSx9mYsroWsGNziHP5jKixlCo4fMbSWOUiGqRCJixiJYyrof6qJumTpZjRRhb2Y+daCAAG4uHS5iMXgOhYypodeGKLzEKLoLMxqYox2Yc7MLXXzKdx0sxwJY+Z8CAACF8F9ZjPSxIvgk7MZ7mLKzEsxgQAAwXIoosa6WIszFPFiSTARquHwAKhsAIAB2AAHAAOoAXoAHdNQ2cEFBDQAA6iQ4NwemaJ6KHwABSfE8AARMpDHHDacHaEVWwAvQAcNwRj4M0ADpxCCxY6SQ3EANM4PgADTOCynhS2IpgAHCWIRAB4AA8AA8AAe2YVnEIOcEabA/AAdaBXoAEmDmDcENwAJwAu3guVwTWWIFuB1ljx3ADZY6wAE2WO78EpjZ5yxHZYvBQF2WJEAA9li+yxA5YocsTEABHLFjliJyxujgqcsZPJV6AC6lZdyxnZY7ssb2WP7LF9oBTyxjAAc8seOWO0IpXljPAAN5YkQAO9znvLH7ljHyxx5Yl8sQpEOHLGjliPyxk5Y78sTOWJEAAsNx/yxKoAA8sd9kKfLEnliQKxZ5YsCsZeWOvLFQVj2AAj72YNwTHHA0RHwAAdgAiAAXEAEL4LZLEcmjcKxCkQussROAG78FJNZYKx1AAeCsVh4MQrHAVjQKxF5Yz8sehWO78FFI5g3BfqohSIbiACkcErljygAa5Y9iuo2WL9jjd+Do+h1FY2isUeWOfLGDljkKxb5Y1CscxWMgrFCVjWyxIAAdssQ+WMPLH0ViJKxjFY8CsV+WOnLFCVi5yxRbgnCsfAAAtaFjlihfBhFY9JIReWOsACwABcgAnjg+AALSENEAAobAigAJFYuEsXE4OsACQAB4AAOZ4CisS2WJ3LFFuDFKxAFY5SsUBWNUrEoVimKxEFYzSsS2WLvLE6VjcKx+lY+2YYZWJEABhVihHBZlYiysVZWJsrF2ViFIhDlYpysS5WKErF/liPKxe5YuCsYBWPErGvljaAA75YtCsbJWJbLEwVj0qxSlYhCsT5WJyrF5ViZKxgVYkQAPOkODcFyuCNNgRAAGssZoADQAA5/YQAACkQ4gAJ/sP9jhtODnKxzVYsgAHCWP1SDnljg/hiTg3G4c2AB/LHsABYgh85YnQAKhsC4rE8VjByx9ZYgSsc2WOqrFsVii3BHFY6asbWWLmrGbljBKxs5YissUW4LqrFEAAGqxFIAHqsbiADarFEAAOqxqGwLqsU1WNpAB9VjLYAA1YoasToRQwrEgABZtsIlYrKsUhWLUrH5Viqqx7AAS7wU9WO8rHZVjJKxuVY6SsQFWNGrEPVj3KxbZYjKsTRWOerEMVi/Kx6lYlisbOWOCrEg1iSqxdFYsqsb9WIqrEA1j7qxrQ1L6saVWJ+rGvVjKqxgNYup2ujWIRrGY1jIaxb1YnGsVhWOKrFeViMaxL1YwmsdjWNRrFUVjSaxmVY76sRTWKkrH+ViNKxONYpasXDWLJrH41iGaxf1YpmsdDWJEABPTC8axYlYzmscjWOZrH3Vj0Rh/NYlSseVWP+rHC1jtyx2lYjHwbpWPwrGEVjiKxulYzc2K5WN5rHA1iFKxoNY0SseLWKRrGS1ieax7AADyYdhWNwrHy1jIqxitY0isY4WOvcAq1i9axaVYjHwVWWOkcEzVi+Kxd2ceasduWKKrGy1jDaxfgAAiscbWPalEJVi6yx5tY7csSTWLZrF01jyaxENYxmsVDWIKrG81iaaxbZY+yAEQACXLF21j1qxW5Y3oAMaUMrLESZDuKxa1Y9csY7WNvLHbVjraxOgAOwANHWJTrH8ViNqxC1Y9gANSAB6cGeViA6xHNYoOsVzWJDrHvViQAA3qVYNwe4IEXLG4gBlyxudYh2sfnWO78E4LCxaxiNYrGsSjWNbrGw1j1ax8NYgWseXWKFrG61jq6xVtY3usezWP7rG+Vjg6xRNY+6sfn1XbrEE1jJ6xVNY1usX7WNHrGl1jx6xEtY7msaHWMLrHh1jl6xYNY+msQPWJ1rEb1jq6xrNY7esZrWI7rGU1iu6xvQAPoYRNWJ0ABR1iG6xMdY1OsS3WIvrHyViS6xO9YwOsRPWIrrFT1ju/BQd2WesYLWP3rFV1jzuKBtYvSscZWPCrFGViTKxMVYuwAJZWOsrErgBbKxulYxKsaJmIgADOVifaxF9Ynusc/WJPrFz1j36xC9Yi+sSPWIUiFTgBbKxeOBfUsYZMOj7IxljjKxikQoisXpWNpCFuMjQlR5XQggAMUACF8GOVjjJhF9Y52scfWPBrFv1jB6xB9Y0qAMXWI1rHMNi16xldYwGsST6O/rF71j16xf9Yo+sXjgSUiGshD3YAH9ovDYBV0JTjgxxxHyxQvgsp4dM4KWxEsPZegAp9Q/hsSw2N/rGA1j0LhADYsKsRFWMryFANjoqx5lY8BsXFWKgbEJVikqx8DYlKsco2JlrFMNjd6xajYwRsRo2LVrE8wApqxIgAZOsauWNjrGbVjoKxyDY+usSIAEbrEuNj76xcdY6CsSPWJQbFcNjtaxtjY+6scDAGLrGR1ic6xPjYvOsX42PYACgAjVGx3DYj+sco2K3rGBNjrGxCTYjBsdBWKPrEpNjX6xaTY8+sSIAESQAcNi+6xWtYzusVLWN6ACwVV4mxwTYnhsfdWJ1zGJ1jVqxUTY5usTE2JAACZXDymxxTYoescvsJ28GJODtCKjlY+AAHjgTAABjgBcQAeGwKcAGAADvrHRNi/Y4cJYscAHh0DQACTNxzyxeOBAgAFAAAUiEjuDSmxATYzhsak2IqbGJNi8mxjDYrJsWXWJsbGVNju/BySAApsWPWKKbFn1iSmxeTY5Jscs2OybGrNj0mxmFYo+sQpEKkcHshCmAAwfwnQAEIsNoAAaIjCKxZTw1kIYA6KkABjlilwAljglTYBAAEScFDODKKxGdYqxsec2JabEH1i54APTg3asftWIurEYNDjqxp1Y86sT1WKurFAQAbqxgQAO6sZRWMsbGbNjV6xFzY3JsewAG9AA9OCbaxzjY3isa42ILrEgABlQA+zYlesYc2PnrHYtiSWxI9Y3Ssdo2JAbHjljTKxBjYiBsfFWJgbGmNiEGxygAC2sSS2I2bFnNitmxOTY45sTi2KXrEYtiKWx6DYqlsbCgB6cEAAA/XEACnHDcZF4bAFIhMmAJ6ADoAEmbE6AARyxlFYzJsTy2MxbGgtiq6xugAcJsdfWMibGEtjfGxbjY9gAGaAGLrGeNj2AA3jY/VsSM2OJbGKYAyWxL9Y3lsVi2P5bEgAAD1stVY+qsY1WMOrEiABYWxKAATqsdYAG6rGXViFIh/VY0csYNWJRbEjVj7qx9IAHpwU/HHtmG6OCG6x/gALgADsABXABjljfdhtAAdcAEIsIFLG3Vjg2xrFYpZsYU2NPrGUtiHWxigAHpwQ42NqbEWtj6mxhrYx1sYK2PVbHCtjWGxWrY05sZm2LQbEVtjAaxfoAG1sag2J/rEhNihKx8mY5psUc2KHrEPwA8WxWdYvVsbNWINbHEtjwEAeLYpOscM2KLbH9tj8zKbbY7NsR22IiqzjtiRWxDrYtWgA22KCbGatjAaxLlgedsSs2MXbH3Vi/LIPTgk2MUpEJjjjYAAhfBtIQvHAtM4NebEuzClGx1VY7ZYlfWJvrFeNjh2xG5YhpscCUBXbEgtj22xB9Y8coD04JRuGetiyGxPPMTk0enEIq6HrgB6QhUrYwa4fAABfbHNgBHCxIYIKRwXJWPkrG0tigGxOjYohsXZWPCrEshCfVRo/gCkAFXkM0ADOVjOWxd8AZ9sUUAFfbF7tj32xVXQr9sT+2JEADt3D/2x6HYwDsaxihA7EtlihAhWjYiDsSA2N0rEwdi5XBcHY3LmJoAEQ7HIdi5KxPdY8DsQZWMo7G4VjqOxtHY8qcAx2M0AAodjcOhwbggDsW+2MX+AfticOxv7YnssQJ2OI7FyVjGGxLHY4BsZFWOMrFUdihfBsHY8JUXR2O47G8dil6x0nYyDsfpWPk7GKdj4Ox9HY3sAIx2NI7Fb1j1OxbHYgysdp2OU7F6dieOxclYo+sQJ2Mw7FCdjsOx37Y0TsQR2NfbESdiWyxz7Q8jsax2Nk7HQdiFOxNHYpTsVx2PM7EodjHqxRbg6zsbSEKw7Gftj7OxeHYv9seJ2OA7FaVjLGxQXYkLsSJ2PC7FidjCOxQHY+vACR2OqrEsPZ+OxSXYmzsexXTs7G4djr+REXYpLsc52LS7E91jYuxtnY0Lsbl2ITzGOdiiOxUXYlzsTS2NCrEUdiPOxWnY7zsTp2JU7FaVipOxdXY9zsbo2M87GmdjfOxSHYizsS52KXrEldjsuxZXYhzsZF2JS7FaVjDOx7XYmTsZ12Ma7GcdiH4ALXYlzsVZ2My7HBdjSux8XYvLsYl2Kc7HVdjqqxfNYkKsYA2I67FQdiZuxPnYubsX52KErGi1jAuxS3YuLsWF2LW7GVdjkux1AAVLsWNWPPzEZdiMOxy3Yobsat2Iq7GjdjbuxJ3YtWsUZ2Ia7HsdivOxs3YhDscd2LcrHFdjzuxK3Yy7sW92IK7Gbdj7uxtXY3bsVN2P27G/djuuxR3Y3rsSh2LmcFudjYexmnY+HsU12LM7FI9iTuxanYybsRp2Lk7EY9j/uxunY7HsW5WK3rGDdi7s4OXYkbsRD2LG7FuVjFuxT3Yi7seV2Pw7Hvdi7uxClYuFIaj2Px7FddjMexPXY/TsdVWKLrGPdjAOxWXYinscN2IS7HXdjCuxY1YmusTt2LpbE/diTOxXPYxHsTz2PF7Ffdi8exxnYjjsYd2IB7Ek9jeexzHYpXsdL2JV7HNdjAexvPY6HsVL2Om7GE9jVexxPY+Xsaz2La7Ew9iOexB3Y3Xser2PF7G49jLexyvYv7sSb2Pm7G89iJuxDvY7XsU72Jt7Fm9jzkq7PYx3sQj2LV7He9jL6xkvY+rsUb2Jl7FE9iXexY1YngYb72I97H+9jTexfXY6qsV/WLO7H09jQexjPY/LsRt2Jp7EJ9i1ax5PY4TsWD2KZ7HU9iPuxLZYqRodH2ND7E69isexgfYg3sSH2Lh7Fh9jnexevYyPsYw2Oz7GU9iRexzPY1KsQN2JB7Evdjc+xafYqrsRn2Mj7Fk9i2+xQvY17sXn2PT7EF9iE+xdPYgXsc92P77Ed9j1uxXfY4fsWNWJUbFJ9ix+xDPYqnsUP2JZ7FwpAenB9swmKEeuAFZCGMhCFIh9IQ9cAHK4KWxGSZiY44eSAXEAOv2P7LFb9id+xe/Yg/seuACP7ERAB1wA9sw75sZ/sJXAB/NjRHBN3IwqsTF2L77E59jU+xU/Ym7sSv2NkABodjk+x7fYr/saL2Mh7EKViRj6/PYwTsYAOKX7HT9jf+xFfYvbsej2Or7Fe9j4+xs/Yi3sYb2Kr7Gl9juexSA40Acfb2NQHHwDj0BxcvYzAcR7oH/7EL9iU+xUA4n/sUJWOEgA9ODvuxJfYz3sWX2IIHH5NjwBxgvYz/saQOLF7EKViymx8/YiAcRP2KAHHN9iWyx1TY9gcYwOMb7FXdjuBx1VYppscH2LgHEE9iEBxtA4lDsW02NEHFo9jxBxeA4gPsXQOJHrEN9jhexgg4/PsSv2KCVzF9i0BxNA4jAcVIOOwHGV9jcBx2g4/AcVIOLd7E4Di5Bxhg4hQcVIONH7EcDimBxTfYtQcUJWLlgCUDitex1A42PsRH2IUrHgtjNBxBg4lwcbX2LcHHv9iABxnA45gcSAOP4CCODj3exzg42XsRYOPsHHA9i/BxNg41Qccv2PsHGwDjZBxnPY8Psd4OMCUDBDjTBxiQ4mvsbb2LcHGt9iohxAg48HsbEOJbLFitiGBx4/Y6IcXkOOgHH2DirBx/A4lQcaUOLIHEtljtWxRQ4xfsbYOPyHGLViwOxTg4rQcV4OMyHH6iAiBx1g43IcYP2LKHG1Dis+xH/YnocZ32JqHGLVjIhxxA4yAcY0OL6HGLVj4hxVvY43sYgOJQ7G5tj6hxJA4yYcSMOLGrFlEAuhxlQ4gfscMOJYHGpwBUhx+g4swce0OO97H1tilhxEw4mIcVMOI+rGtti+BxxQ4oYcd/2JYHHa0A9hxYg49IcfMOO78GXQAHhxCQ463sZIOJeHFjtirhxDQ4s4casOIerFTtifhxyw4v4cXcOPKAAQtiXWxB1YkCgEdWParGetizqx3rYi6sfQAERbFkABa2xqNYqEcScOP8HErDjQRxeg4x4cR8OJ0HFfDiTBx+w4p4cZ8OK2rFH1iqBxbQ4sIcXH2M5bGWoANhx1w4qocb0OP+HHaNA3hxsw4iQcXiONnLE5WN0RxJQ4+kcXcOLI7FAjjThx1Q47kcZr2JCHHkjikhxmQ4xOwDSON+HH8jiQBxb1AcUccCOMlHHd9iHqxNVY3kcRiOJBHFSjjxqxSo4zkcdsONVHEVDjaRxWw424cVKONc7HqjibhxwA4+UcZ+cBlHF8jiuRx+o43wceMOOVHFyjiZ+xD1Y9LsTIOOZHHyDjKRxLw4swYR4OIOHEUjjXBxcjAJkcX72M9HHeDijjgPo4mPsX6ONFHGnQBAxxoQ4kUcQg2KYABUjjbCs7o4okcayOJEACjnAwxxwo4jIcWb2MQiBmjibRxFo4k0cad2Ix8HKDjdRxxo4u0cRagCTHGeDjgxxqY4m/nByOKNHFCDiPqx+tYw0cXSOM1HFZjilBxgw42scXqOKzHEoDjCRxuI4owcS8OLB7zljimxx+Y4lnsf1UHTHEajjmxxBY4hOsY6ON9HERjjMBx+zAAccRWOLsHEw1j5KxuY4yfsb2OJeHES9iXaxQo44sceOONcrH8OCCNg5zedTMVZmK/JBaZiHcxb+Y33YfVmMPHFoN4TMxh/QszMSmWP2dHWZi5XBa6+OzMW5mIr2H1ZiSsxh/QlzMZ6WIVcG65j7MxblQ2zMZ5mL8zGO+CAsxUjg/7MdzmJkcFbAA38xUjgiLMTZsCizG7jiA8xUjguLMd+ONziHj5iUsxhOYgdBBlmI6zHgTjBAhOWY+zMSgkK2LH2ZjZnBxWYgbMWVmO5zEyOjbMxOOYxPMWNnm1zH1ZjiJxTWY83MTd6KiACY5jMsx5eYkP0bZmJBzFs5Dg5gS2YobMeBOJiCGjZjYcxKgI/zYEtmOmzFcTi5sxVE42IIT7ACWzHeZjwcxz7Qg03LtmM2zGY5iqyx0k4jTMQROLCxHHCZdsxqCQ07MQqkIjzG7ZirsxVE4044RtABBzELIiQcxmAY7AAC9mIwREnZiCJx5+Y0mguxOIR0K/ZihrhQWYt/MY/mN1zF6TiwcxgOYyHMVROMNbKw5jC9R0gAYicYAWORzGwpDUcxeE4uXMZjmO1FEGTiPJxeOYvCcagkKJzFvjCTsxIOYycYRTmJqqG2ZiCJxhBYunMbamMJzGM5jUsxNk41nMQHmJkdEc5iWcxqCQuKcbzmNhzHsNiI4AQuYh3MSLmJ7zGw5jBCxfAAdicUvCN1gCY5i/NRSxY5XMYrmJsnEq5jqpx6uYzHMTh4L4ADa5i5cx7E4zK4fuYW1zHG5j0pxXLQ2jYNrmMtzGv/gW+hJ2Yu3Md7mNyzHO5iDJxruYuUsRF0DczFe5iHcxw04tUsdkkI1LG6ZitSxBpY6QgLpmL1LHrTi3UiumY40sctONNLF+ljYSRNTQy0sTKWOaLFfFiFSx8kQ+0sVcWKJLGiliquhZmYh4SCk4KHlHT8ILMx3pY3ccVK2AcLF0lj1gx4lw4acVGWM8zGxljjMx8ZYkSnO9OPeKHGZiRDgXqtbccX7mM+YIP5jg8xO+Y8PMSMWOALHO8jo8xjBYuPMZfmJInFqpAH8xqeYmQsYNcIzzHm5is8xypY1GcXnmPsgAP5ij+hxjggXELnmLLzFYzjBsx5RYymcVBkOMcH75isrR9eYhGcSBKM7zFv5jW8xuYAYmcVoWPAnEv0ik8xTM48ScYZYGhnHD5jKZxVZY10FBPmI0zFT5ig8xM+YpQsfPmPKLGszjl8xceYjQsQdUPeLGyzjC0xuuY2GcZf4L3zG4ziC9Rh+YhWceiML+MIP5jTJxq1KfWcdfmK5nEF6i78xys4oHMSzKhfzFx5jzZxH+Y4QsQXqO/zF2zi4cxWxYx7MWy8I6zFs5iQCxWxYpmcejmJHYzkFiApxk8mOfMbCkLgLGOziCcxpM4k2ceFOJ8wCazjYUh6BY5WcVgWNOABhzjE9SpM4x2cYQWPGmgEFjSCxys4pnMZcmjoLE0Fj05xd+YsOcUwWLqOAsFjyixkc4/KcacACZnEk+jSZxxBY6VkXwWMrnFTmjyixjs4yqcW4QnILE1TikswAhY6QsQ/mJSGHFkB5CxsbIxQsS7OJABEqFiw5xoAIxSgO3OK0LEPTjdCxfK2REsdLmIZOAOFjg8x8eYswsdkWJunHMhCrCxRhYypoXYWIXnGOFjsixb+Y1wsfEWPAnEeFjOQAAxY+AAD4WNhLH+FiRixMpY4IsacAABLFIpi6ZxO84pN4ZPONhLFxFjcSxy845kIUkWIbGyIli0ixIxYgEsVkWKpAD8li8ixEeYteceyWNhLGlFiMSxgw6BwsVUWL3HG1FjUNRoBY06cZQqNaLH7ziOix/WYkUsYMWLvJETFjYFx5UY/IsdfOJVhHjFjsix6C41gkTqWLXnHzFjTYx4RYi6cawSNWLHZFiZSxmxYm4fIiWN2LHZFiiFxhxYtHlIiWNOLGcgBYSx5Twyp4ZPOLXnF3FiER8iJYrMsWeth+LHMhC3ixHThREsedOP5LF/FjXkhiJYj9sTiWJBLGIljwSxPWYsrodCWKpABYljJ5xMpYn1UX6qNALGPzikSxqiY8IsViWMCdHAlijJI+JY6XMUmmDJLEMlj+Sx5JYpBcUKWKpLGgFjN5xdsw0MscyWNFnAILjqaRei4ixca1KPalE6liZSxk04vRgIiWJ5LEmLjJaA/JYwUsSNQCdLGkFiiFxUpYkbwoiWLlLHFfJISxzIQpUsaTONHnH+libwxEeY96cWmWIZLEPTiuFxHS6NQim1FinLHwABaMxogAXDYPw4IIACoABRyxoccJFwXoRT+byrABQ44q/cN4AKw3CAAAA")) /////////////////////////////////////////////// /////////////////////////////////////////////// diff --git a/hardware/68percent/~_autosave-rgb.kicad_sch.lck b/hardware/68percent/~_autosave-rgb.kicad_sch.lck new file mode 100644 index 00000000..cf7e3025 --- /dev/null +++ b/hardware/68percent/~_autosave-rgb.kicad_sch.lck @@ -0,0 +1 @@ +{"hostname":"framework16","username":"ukim"} \ No newline at end of file diff --git a/hardware/numpad/numpad/~numpad.kicad_pcb.lck b/hardware/numpad/numpad/~numpad.kicad_pcb.lck new file mode 100644 index 00000000..cf7e3025 --- /dev/null +++ b/hardware/numpad/numpad/~numpad.kicad_pcb.lck @@ -0,0 +1 @@ +{"hostname":"framework16","username":"ukim"} \ No newline at end of file