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Some work on the GPIO, enabled DMA for TX as well

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This commit is contained in:
Oliver "Kim" Avecilla Cabral
2025-08-25 17:56:49 -07:00
parent 70ad2130fe
commit 826ddbcb1d
10 changed files with 1018 additions and 644 deletions
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50
firmware/core/core.ioc
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@@ -6,7 +6,11 @@ Dma.Request0=UART4_RX
Dma.Request1=UART5_RX
Dma.Request2=USART1_RX
Dma.Request3=USART2_RX
Dma.RequestsNb=4
Dma.Request4=UART4_TX
Dma.Request5=UART5_TX
Dma.Request6=USART1_TX
Dma.Request7=USART2_TX
Dma.RequestsNb=8
Dma.UART4_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.UART4_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.UART4_RX.0.Instance=DMA1_Stream2
@@ -17,6 +21,16 @@ Dma.UART4_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UART4_RX.0.PeriphInc=DMA_PINC_DISABLE
Dma.UART4_RX.0.Priority=DMA_PRIORITY_LOW
Dma.UART4_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.UART4_TX.4.Direction=DMA_MEMORY_TO_PERIPH
Dma.UART4_TX.4.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.UART4_TX.4.Instance=DMA1_Stream4
Dma.UART4_TX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.UART4_TX.4.MemInc=DMA_MINC_ENABLE
Dma.UART4_TX.4.Mode=DMA_NORMAL
Dma.UART4_TX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UART4_TX.4.PeriphInc=DMA_PINC_DISABLE
Dma.UART4_TX.4.Priority=DMA_PRIORITY_LOW
Dma.UART4_TX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.UART5_RX.1.Direction=DMA_PERIPH_TO_MEMORY
Dma.UART5_RX.1.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.UART5_RX.1.Instance=DMA1_Stream0
@@ -27,6 +41,16 @@ Dma.UART5_RX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UART5_RX.1.PeriphInc=DMA_PINC_DISABLE
Dma.UART5_RX.1.Priority=DMA_PRIORITY_LOW
Dma.UART5_RX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.UART5_TX.5.Direction=DMA_MEMORY_TO_PERIPH
Dma.UART5_TX.5.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.UART5_TX.5.Instance=DMA1_Stream7
Dma.UART5_TX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.UART5_TX.5.MemInc=DMA_MINC_ENABLE
Dma.UART5_TX.5.Mode=DMA_NORMAL
Dma.UART5_TX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UART5_TX.5.PeriphInc=DMA_PINC_DISABLE
Dma.UART5_TX.5.Priority=DMA_PRIORITY_LOW
Dma.UART5_TX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.USART1_RX.2.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART1_RX.2.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_RX.2.Instance=DMA2_Stream2
@@ -37,6 +61,16 @@ Dma.USART1_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_RX.2.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_RX.2.Priority=DMA_PRIORITY_LOW
Dma.USART1_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.USART1_TX.6.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART1_TX.6.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_TX.6.Instance=DMA2_Stream7
Dma.USART1_TX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_TX.6.MemInc=DMA_MINC_ENABLE
Dma.USART1_TX.6.Mode=DMA_NORMAL
Dma.USART1_TX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_TX.6.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_TX.6.Priority=DMA_PRIORITY_LOW
Dma.USART1_TX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.USART2_RX.3.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART2_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART2_RX.3.Instance=DMA1_Stream5
@@ -47,6 +81,16 @@ Dma.USART2_RX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART2_RX.3.PeriphInc=DMA_PINC_DISABLE
Dma.USART2_RX.3.Priority=DMA_PRIORITY_LOW
Dma.USART2_RX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.USART2_TX.7.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART2_TX.7.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART2_TX.7.Instance=DMA1_Stream6
Dma.USART2_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART2_TX.7.MemInc=DMA_MINC_ENABLE
Dma.USART2_TX.7.Mode=DMA_NORMAL
Dma.USART2_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART2_TX.7.PeriphInc=DMA_PINC_DISABLE
Dma.USART2_TX.7.Priority=DMA_PRIORITY_LOW
Dma.USART2_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
File.Version=6
GPIO.groupedBy=Group By Peripherals
KeepUserPlacement=false
@@ -110,8 +154,12 @@ MxDb.Version=DB.6.0.150
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DMA1_Stream0_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA1_Stream2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA1_Stream4_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA1_Stream5_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA1_Stream6_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA1_Stream7_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA2_Stream2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA2_Stream7_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false