pcb stuff

hardware/numpad/numpad/#auto_saved_files#

@@ -0,0 +1 @@
+/home/ukim/Projects/modular-kbd/hardware/numpad/numpad/_autosave-numpad.kicad_sch

hardware/numpad/numpad/fp-lib-table

@@ -1,8 +1,8 @@
 (fp_lib_table
   (version 7)
-  (lib (name "footprints")(type "KiCad")(uri "/home/kymkim/Projects/mskbd/hardware/footprint/stm32f446re/footprints.pretty")(options "")(descr ""))
-  (lib (name "Package_QFP.3dshapes")(type "KiCad")(uri "/home/kymkim/Projects/mskbd/hardware/footprint/Package_QFP.3dshapes")(options "")(descr ""))
-  (lib (name "Type-C.pretty-master")(type "KiCad")(uri "/home/kymkim/Projects/modular-kbd/hardware/Type-C.pretty-master")(options "")(descr ""))
-  (lib (name "kicad-footprints-master")(type "KiCad")(uri "/home/kymkim/Projects/modular-kbd/hardware/footprint/generic/kicad-footprints-master")(options "")(descr ""))
-  (lib (name "Connector_PinSocket_2.54mm")(type "KiCad")(uri "/home/kymkim/Projects/modular-kbd/hardware/footprint/generic/kicad-footprints-master/Connector_PinSocket_2.54mm.pretty")(options "")(descr ""))
+  (lib (name "footprints")(type "KiCad")(uri "/home/ukim/Projects/mskbd/hardware/footprint/stm32f446re/footprints.pretty")(options "")(descr ""))
+  (lib (name "Package_QFP.3dshapes")(type "KiCad")(uri "/home/ukim/Projects/mskbd/hardware/footprint/Package_QFP.3dshapes")(options "")(descr ""))
+  (lib (name "Type-C.pretty-master")(type "KiCad")(uri "/home/ukim/Projects/modular-kbd/hardware/Type-C.pretty-master")(options "")(descr ""))
+  (lib (name "kicad-footprints-master")(type "KiCad")(uri "/home/ukim/Projects/modular-kbd/hardware/footprint/generic/kicad-footprints-master")(options "")(descr ""))
+  (lib (name "Connector_PinSocket_2.54mm")(type "KiCad")(uri "/home/ukim/Projects/modular-kbd/hardware/footprint/generic/kicad-footprints-master/Connector_PinSocket_2.54mm.pretty")(options "")(descr ""))
 )

hardware/numpad/numpad/numpad.kicad_dru

@@ -1,133 +1,169 @@
 (version 1)
-# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '<project>.kicad_dru' file).
-#
-# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
-#
-# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
-#
-# Inspiration
-# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
-# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)
+#PCBWay Custom DRC for Kicad 7
 
-# TODO new rule: NPTH pads.
-# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
-# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."
+# ----------------------------------- Minimum trace width and spacing (PICK ONE) --------------------
 
-# TODO: new rule for plated slots: min diameter/width 0.5mm
-# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."
+# 2oz copper
+#(rule "Minimum Trace Width and Spacing (outer layer)"
+#(constraint track_width (min 0.1524mm))
+#(constraint clearance (min 0.1778mm))
+#(layer outer)
+#(condition "A.Type == 'track'"))
 
-# TODO new rule: non-plated slots: min diameter/width 1.0mm
-# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
+#(rule "Minimum Trace Width and Spacing (innner layer)"
+#(constraint track_width (min 0.1524mm))
+#(constraint clearance (min 0.1778mm))
+#(layer inner)
+#(condition "A.Type == 'track'"))
 
-(rule "Track width, outer layer (1oz copper)"
-	(layer outer)
-	(condition "A.Type == 'track'")
-	(constraint track_width (min 0.127mm))
-)
 
-(rule "Track spacing, outer layer (1oz copper)"
-	(layer outer)
-	(condition "A.Type == 'track' && B.Type == A.Type")
-	(constraint clearance (min 0.127mm))
-)
+# 2-layer, 1oz copper
+(rule "Minimum Trace Width and Spacing (outer layer)"
+(constraint track_width (min 0.127mm))
+(constraint clearance (min 0.127mm))
+(layer outer)
+(condition "A.Type == 'track'"))
 
-(rule "Track width, inner layer"
-	(layer inner)
-	(condition "A.Type == 'track'")
-	(constraint track_width (min 0.09mm))
-)
+(rule "Minimum Trace Width and Spacing (inner layer)"
+(constraint track_width (min 0.1mm))
+(constraint clearance (min 0.1mm))
+(layer inner)
+(condition "A.Type == 'track'"))
 
-(rule "Track spacing, inner layer"
-	(layer inner)
-	(condition "A.Type == 'track' && B.Type == A.Type")
-	(constraint clearance (min 0.09mm))
-)
+# 4-layer , 1oz and 0.5oz copper
+#(rule "Minimum Trace Width and Spacing (outer layer)"
+#(constraint track_width (min 0.09mm))
+#(constraint clearance (min 0.09mm))
+#(layer outer)
+#(condition "A.Type == 'track'"))
 
-(rule "Silkscreen text"
-	(layer "?.Silkscreen")
-	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
-	(constraint text_thickness (min 0.15mm))
-	(constraint text_height (min 1mm))
-)
+#(rule "Minimum Trace Width and Spacing (inner layer)"
+#(constraint track_width (min 0.1mm))
+#(constraint clearance (min 0.09mm))
+#(layer inner)
+#(condition "A.Type == 'track'"))
+
+# ------------------------------------------------------------------------------------------------------
+
+# Drill/hole size - listed here to maintain order of rule application. Must not override rule set in Via hole/diameter size below.
+(rule "drill hole size (mechanical)"
+(constraint hole_size (min 0.15mm) (max 6.3mm)))
+
+# ----------------------------------- Via hole/diameter size (PICK ONE) ------------------------------------
+
+# 2-layer standard
+(rule "Minimum Via Diameter and Hole Size"
+(constraint hole_size (min 0.3mm))
+(constraint via_diameter (min 0.5mm))
+(condition "A.Type == 'via'"))
+
+# 4-layer standard
+#(rule "Minimum Via Diameter and Hole Size"
+#(constraint hole_size (min 0.3mm))
+#(constraint via_diameter (min 0.45mm))
+#(condition "A.Type == 'via'"))
+
+# 4-layer advanced
+#(rule "Minimum Via Diameter and Hole Size"
+#(constraint hole_size (min 0.25mm))
+#(constraint via_diameter (min 0.4mm))
+#(constraint disallow buried_via)
+#(condition "A.Type == 'via'"))
+
+# 4-layer advanced
+#(rule "Minimum Via Diameter and Hole Size"
+#(constraint hole_size (min 0.2mm))
+#(constraint via_diameter (min 0.35mm))
+#(condition "A.Type == 'via'"))
+
+# 4-layer advanced
+#(rule "Minimum Via Diameter and Hole Size"
+#(constraint hole_size (min 0.15mm))
+#(constraint via_diameter (min 0.3mm))
+#(condition "A.Type == 'via'"))
+
+# ----------------------------------- Drill/hole size ------------------------------------
+
+(rule "PTH Hole Size"
+(constraint hole_size (min 0.2mm) (max 6.35mm))
+(condition "A.Type != 'Via' && A.isPlated()"))
+
+(rule "Minimum Non-plated Hole Size"
+(constraint hole_size (min 0.5mm))
+(condition "A.Type == 'pad' && !A.isPlated()"))
+
+(rule "Pad Size"
+(constraint hole_size (min 0.5mm))
+(constraint annular_width (min 0.25mm))
+(condition "A.Type == 'Pad' && A.isPlated()"))
+
+(rule "Minimum Castellated Hole Size"
+(constraint hole_size (min 0.6mm))
+(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
+
+(rule "Min. Plated Slot Width"
+(constraint hole_size (min 0.5mm))
+(condition "(A.Hole_Size_X != A.Hole_Size_Y) && A.isPlated()"))
+
+(rule "Min. Non-Plated Slot Width"
+(constraint hole_size (min 0.8mm))
+(condition "(A.Hole_Size_X != A.Hole_Size_Y) && !A.isPlated()"))
+
+# ----------------------------------- Minimum clearance ----------------------------------
+(rule "hole to hole clearance (different nets)"
+(constraint hole_to_hole (min 0.5mm))
+(condition "A.Net != B.Net"))
+
+(rule "via to track clearance"
+(constraint hole_clearance (min 0.254mm))
+(condition "A.Type == 'via' && B.Type == 'track'"))
+
+(rule "via to via clearance (same nets)"
+(constraint hole_to_hole (min 0.254mm))
+(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
+
+(rule "pad to pad clearance (with hole, different nets)"
+(constraint hole_to_hole (min 0.5mm))
+(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
+
+(rule "pad to pad clearance (without hole, different nets)"
+(constraint clearance (min 0.127mm))
+(condition "A.Type == 'Pad' && B.Type == 'Pad'"))
+
+(rule "NPTH to Track clearance"
+(constraint hole_clearance (min 0.254mm))
+(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
+
+(rule "NPTH with copper around"
+(constraint hole_clearance (min 0.20mm))
+(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type != 'track'"))
+
+(rule "PTH to Track clearance"
+(constraint hole_clearance (min 0.33mm))
+(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'"))
+
+(rule "Pad to Track clearance"
+(constraint clearance (min 0.2mm))
+(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'"))
+
+# ----------------------------------- Board Outlines (PICK ONE) -------------------------------------
+#Default Routed Edge Clearance
+(rule "Trace to Outline"
+(constraint edge_clearance (min 0.3mm))
+(condition "A.Type == 'track'"))
+
+#Special Clearance for V-Score Edges
+#(rule "Trace to V-Cut"
+#(constraint edge_clearance (min 0.4mm))
+#(condition "A.Type == 'track'"))
+
+# ----------------------------------- silkscreen --------------------------
+(rule "Minimum Text"
+(constraint text_thickness (min 0.15mm))
+(constraint text_height (min 0.8mm))
+(layer "?.Silkscreen"))
 
 (rule "Pad to Silkscreen"
-	(layer outer)
-	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
-	(constraint silk_clearance (min 0.15mm))
-)
-
-(rule "Edge (routed) to track clearance"
-	(condition "A.Type == 'track'")
-	(constraint edge_clearance (min 0.3mm))
-)
-
-#(rule "Edge (v-cut) to track clearance"
-#	(condition "A.Type == 'track'")
-#	(constraint edge_clearance (min 0.4mm))
-#)
-
-# JLCPCB restrictions ambiguous:
-# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
-# This rule handles diameter minimum and maximum for ALL holes.
-# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
-(rule "Hole diameter"
-	(constraint hole_size (min 0.2mm) (max 6.3mm))
-)
-
-(rule "Hole (NPTH) diameter"
-	(layer outer)
-	(condition "!A.isPlated()")
-	(constraint hole_size (min 0.5mm))
-)
-
-# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
-(rule "Hole (castellated) diameter"
-	(layer outer)
-	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
-	(constraint hole_size (min 0.6mm))
-)
-
-# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
-# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
-(rule "Annular ring width (via and PTH)"
-	(layer outer)
-	(condition "A.isPlated()")
-	(constraint annular_width (min 0.075mm))
-)
-
-(rule "Clearance: hole to hole (perimeter), different nets"
-	(layer outer)
-	(condition "A.Net != B.Net")
-	(constraint hole_to_hole (min 0.5mm))
-)
-
-(rule "Clearance: hole to hole (perimeter), same net"
-	(layer outer)
-	(condition "A.Net == B.Net")
-	(constraint hole_to_hole (min 0.254mm))
-)
-
-(rule "Clearance: track to NPTH hole (perimeter)"
-#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
-	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
-	(constraint hole_clearance (min 0.254mm))
-)
-
-(rule "Clearance: track to PTH hole perimeter"
-	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
-	(constraint hole_clearance (min 0.33mm))
-)
-
-# TODO: try combining with rule "Clearance: PTH to track, different nets"
-(rule "Clearance: track to pad"
-	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
-	(constraint clearance (min 0.2mm))
-)
-
-(rule "Clearance: pad/via to pad/via"
-	(layer outer)
-#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
-	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
-	(constraint clearance (min 0.127mm))
-)
-
+(constraint silk_clearance (min 0.15mm))
+(layer outer)
+(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))

hardware/numpad/numpad/numpad.kicad_prl

@@ -13,7 +13,7 @@
       "shapes": 1.0,
       "tracks": 1.0,
       "vias": 1.0,
-      "zones": 0.4099999964237213
+      "zones": 0.3700000047683716
     },
     "selection_filter": {
       "dimensions": true,

hardware/numpad/numpad/numpad.kicad_pro

@@ -56,6 +56,11 @@
           "gap": 0.0,
           "via_gap": 0.0,
           "width": 0.0
+        },
+        {
+          "gap": 0.4,
+          "via_gap": 0.4,
+          "width": 0.8
         }
       ],
       "drc_exclusions": [],
@@ -188,7 +193,8 @@
       ],
       "track_widths": [
         0.0,
-        0.2
+        0.2,
+        0.6
       ],
       "tuning_pattern_settings": {
         "diff_pair_defaults": {
@@ -475,7 +481,7 @@
         "clearance": 0.2,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
-        "diff_pair_width": 0.2,
+        "diff_pair_width": 0.8,
         "line_style": 0,
         "microvia_diameter": 0.3,
         "microvia_drill": 0.1,
@@ -630,11 +636,7 @@
     ],
     [
       "1d905906-6e74-4741-8b2e-53dc470a7c79",
-      "Numpad Matrix + Rotary Encoder"
-    ],
-    [
-      "ead3be26-7f43-4289-81f3-aae72a11e5f1",
-      "RGB Matrix"
+      "NumpadRGB"
     ]
   ],
   "text_variables": {}