documentation and inactive mode code
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docs/firmware/firmware-architecture.md
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docs/firmware/firmware-architecture.md
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# Firmware Architecture
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The firmware operates under **three distinct modes** that define the device’s behavior:
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```c
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#define MODE_INACTIVE 0
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#define MODE_MASTER 1
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#define MODE_MODULE 2
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```
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These modes dictate how the system processes input and manages data flow between modules. Together, they establish the rules for communication and arbitration within the modular keyboard system.
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## Master Mode
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In **Master Mode**, the device behaves like a standard keyboard connected to a host via USB. However, it also takes on additional responsibilities:
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* **USB Handling**: Sends keypress reports directly to the host.
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* **Neighbor Listening**: Receives keypress messages from connected Module devices and integrates them into the USB report.
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* **Device Queries**: Responds to discovery or status requests from devices currently in **Inactive Mode**.
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👉 The system can only enter Master Mode if it is physically connected to a USB host.
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## Module Mode
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In **Module Mode**, the device functions similarly to Master Mode but with one key difference:
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* Instead of sending reports to the USB host, the device forwards its keypress data upstream to its **parent device**.
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This parent is determined during the discovery process in Inactive Mode. The parent may be either the Master itself or another Module closer to the Master.
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## Inactive Mode
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**Inactive Mode** is the initial state of every device upon power-up (unless it is directly connected to USB).
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Behavior in this mode includes:
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* **Ignoring Local Inputs**: The device does not process its own switch presses.
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* **Discovery Queries**: The device broadcasts a query to its neighbors to determine its parent.
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* **Awaiting Responses**: Active devices (Master or Modules) respond with a **depth value**—a numerical measure of distance (in hops) to the Master.
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* The Master has a depth of **0**.
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* Each Module reports its depth as `(parent depth + 1)`.
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The querying device selects a parent based on the lowest reported depth. This ensures the shortest and most efficient communication path to the Master.
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**Example:**
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If device A reports depth = 2, and device B reports depth = 4, the querying device sets:
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* **Parent = A**
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* **Depth = 3**
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After selecting a parent, the device transitions from **Inactive Mode → Module Mode**.
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Devices already in Master or Module mode should respond to discovery queries with their current depth value.
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Ooh\~ let’s make your UART DMA explanation sparkle ✨ I’ll clean it up, add clarity on why interrupts could be tricky, and make the flow a bit more structured. Here’s a polished version:
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# UART Queue with DMA
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Data transmission in this system is handled via **UART**. However, standard UART operations are **blocking**:
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* When sending or receiving data without DMA, the CPU must wait until the operation completes.
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* Running UART directly in the main loop would **stall other critical processes**, such as scanning keypresses or handling module communication.
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An alternative is using **interrupts**, which allow the CPU to continue running while UART signals completion.
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**Problem:** Interrupts can occur at any moment, potentially interrupting time-sensitive operations like key scanning or other UART transactions.
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* Frequent or nested interrupts could lead to **race conditions**, data corruption, or missed key events.
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## DMA Solution
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The system uses **DMA (Direct Memory Access)** to offload UART data handling:
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* Each RX port operates via DMA, continuously collecting incoming data **without CPU intervention**.
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* Received data is placed into a **queue**.
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* During the main loop, the firmware checks the queue:
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* If the queue is not empty, it transmits the collected data to the parent/master device.
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This system allows UART to behave like a **background subprocess**, leaving the CPU free for:
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* Scanning the module’s own keys.
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* Processing received messages.
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* Managing the module-to-master communication efficiently.
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## Queue Usage
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The **same queue system** also handles the module’s own keypresses:
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* Key events are pushed into the queue as they are detected.
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* The main loop processes the queue, sending keypresses to the master device.
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This unified queue system ensures **non-blocking, deterministic communication** between modules and the master, even under high data load.
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Ooo~ let’s give your UART message section a little sparkle ✨ and make it clearer, more structured, and easier to read. I’ll also fix formatting inconsistencies and clarify the purpose of each field. 💙
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---
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# UART Message Structure
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Each UART message is **32 bits (4 bytes)** and structured as follows:
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| Byte 0 (MSB) | Byte 1 | Byte 2 | Byte 3 (LSB) |
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|---------------------|-----------------|------------|--------------|
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| Sender’s Depth | Message Type | Extra Bits | Key Code |
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**Field Descriptions:**
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- **Sender’s Depth:** Indicates the module’s distance from the Master device. Useful for routing and arbitration.
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- **Message Type:** Determines the purpose of the message (see below).
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- **Extra Bits:** Reserved for additional flags or future extensions.
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- **Key Code:** Represents the key being pressed (or released).
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## Message Types
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| Value | Name | Description |
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|--------|------------------------|-----------------------------------------------------------------------------|
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| 0x0F | Handshake Request | Sent by modules in **Inactive Mode** to discover parent/master devices. |
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| 0xFF | Handshake Confirmation | Sent by active modules (or Master) in response to a Handshake Request. |
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| 0x01 | Keycode Message | Generic keycode message sent from module to master. |
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**Notes:**
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- All communication between modules follows this 4-byte structure.
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- Depth values help modules select the optimal parent device.
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- Reserved **Extra Bits** can later store flags like key release, special functions, or priority indicators.
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@@ -7,6 +7,8 @@
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#define MODE_MODULE 2
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#define DMA_BUFFER_SIZE 16
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#define MODULE_HANDSHAKE_REQUEST 0x000F0000
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typedef struct{
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uint8_t data[4];
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} Packet;
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@@ -26,6 +28,8 @@ UART_HandleTypeDef huart4;
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UART_HandleTypeDef huart5;
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UART_HandleTypeDef huart1;
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UART_HandleTypeDef huart2;
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UART_HandleTypeDef* UART_PORTS[] = { &huart4, &huart5, &huart1, &huart2 };
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UART_HandleTypeDef* PARENT;
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DMA_HandleTypeDef hdma_uart4_rx;
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DMA_HandleTypeDef hdma_uart5_rx;
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DMA_HandleTypeDef hdma_usart1_rx;
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@@ -70,13 +74,64 @@ int main(void)
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while (1)
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{
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switch(CURRENT_MODE){
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case MODE_INACTIVE:
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uint8_t candidates_depth[] = {0xFF, 0xFF, 0xFF, 0xFF};
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//Poll all UART Ports
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for(uint8_t i = 0; i<4; i++){
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uint8_t rxBuffer[4] = {0};
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HAL_UART_Transmit(UART_PORTS[i], MODULE_HANDSHAKE_REQUEST, 4, HAL_MAX_DELAY);
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if (HAL_UART_Receive(UART_PORTS[i], rxBuffer, 4, 500) == HAL_OK) {
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//Is a type of confirmation message
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if(rxBuffer[1] == 0xFF){
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candidates_depth[i] = rxBuffer[0];
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}else{
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candidates_depth[i] = 0xFF;
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}
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} else {
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// Timeout or error
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candidates_depth[i] = 0xFF;
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}
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}
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// Arbitration: 0xFF means invalid
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uint8_t min = 0xFF; // start with invalid value
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uint8_t best_parent = 0xFF; // invalid index by default
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for(uint8_t i = 0; i < 4; i++){
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if(candidates_depth[i] != 0xFF && candidates_depth[i] < min){
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min = candidates_depth[i];
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best_parent = i;
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}
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}
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if(best_parent != 0xFF){ // found a valid parent
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PARENT = UART_PORTS[best_parent]; // assign UART handle pointer
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DMA_Queue_Init(&RxQueue);
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CURRENT_MODE = MODE_MODULE;
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}
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break;
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case MODE_MODULE:
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break;
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case MODE_MASTER:
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break;
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}
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}
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}
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void DMA_Queue_Init(DMA_QUEUE* q){
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q->head = 0;
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q->tail = 0;
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//Activate DMA to all ports
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for(uint8_t i = 0; i<4; i++){
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HAL_UART_Receive_DMA(&UART_PORTS[i], RxQueue.buffer, 4);
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}
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}
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bool DMA_Queue_IsFull(DMA_QUEUE* q){
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Binary file not shown.
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